trunk/src/emu/cpu/upd7810/upd7810.c
r241597 | r241598 | |
1174 | 1174 | } |
1175 | 1175 | } |
1176 | 1176 | |
1177 | | void upd7810_device::handle_timers(int cycles) |
| 1177 | void upd7810_device::upd7810_handle_timer0(int cycles, int clkdiv) |
1178 | 1178 | { |
1179 | | /**** TIMER 0 ****/ |
1180 | | if (TMM & 0x10) /* timer 0 upcounter reset ? */ |
1181 | | CNT0 = 0; |
1182 | | else |
| 1179 | OVC0 += cycles; |
| 1180 | while (OVC0 >= clkdiv) |
1183 | 1181 | { |
1184 | | switch (TMM & 0x0c) /* timer 0 clock source */ |
| 1182 | OVC0 -= clkdiv; |
| 1183 | CNT0++; |
| 1184 | if (CNT0 == TM0) |
1185 | 1185 | { |
1186 | | case 0x00: /* clock divided by 12 */ |
1187 | | OVC0 += cycles; |
1188 | | while (OVC0 >= 12) |
| 1186 | CNT0 = 0; |
| 1187 | IRR |= INTFT0; |
| 1188 | /* timer F/F source is timer 0 ? */ |
| 1189 | if (0x00 == (TMM & 0x03)) |
1189 | 1190 | { |
1190 | | OVC0 -= 12; |
1191 | | CNT0++; |
1192 | | if (CNT0 == TM0) |
1193 | | { |
1194 | | CNT0 = 0; |
1195 | | IRR |= INTFT0; |
1196 | | /* timer F/F source is timer 0 ? */ |
1197 | | if (0x00 == (TMM & 0x03)) |
1198 | | { |
1199 | | TO ^= 1; |
1200 | | m_to_func(TO); |
1201 | | } |
1202 | | /* timer 1 chained with timer 0 ? */ |
1203 | | if ((TMM & 0xe0) == 0x60) |
1204 | | { |
1205 | | CNT1++; |
1206 | | if (CNT1 == TM1) |
1207 | | { |
1208 | | IRR |= INTFT1; |
1209 | | CNT1 = 0; |
1210 | | /* timer F/F source is timer 1 ? */ |
1211 | | if (0x01 == (TMM & 0x03)) |
1212 | | { |
1213 | | TO ^= 1; |
1214 | | m_to_func(TO); |
1215 | | } |
1216 | | } |
1217 | | } |
1218 | | } |
| 1191 | TO ^= 1; |
| 1192 | m_to_func(TO); |
1219 | 1193 | } |
1220 | | break; |
1221 | | case 0x04: /* clock divided by 384 */ |
1222 | | OVC0 += cycles; |
1223 | | while (OVC0 >= 384) |
| 1194 | /* timer 1 chained with timer 0 ? */ |
| 1195 | if ((TMM & 0xe0) == 0x60) |
1224 | 1196 | { |
1225 | | OVC0 -= 384; |
1226 | | CNT0++; |
1227 | | if (CNT0 == TM0) |
| 1197 | CNT1++; |
| 1198 | if (CNT1 == TM1) |
1228 | 1199 | { |
1229 | | CNT0 = 0; |
1230 | | IRR |= INTFT0; |
1231 | | /* timer F/F source is timer 0 ? */ |
1232 | | if (0x00 == (TMM & 0x03)) |
| 1200 | CNT1 = 0; |
| 1201 | IRR |= INTFT1; |
| 1202 | /* timer F/F source is timer 1 ? */ |
| 1203 | if (0x01 == (TMM & 0x03)) |
1233 | 1204 | { |
1234 | 1205 | TO ^= 1; |
1235 | 1206 | m_to_func(TO); |
1236 | 1207 | } |
1237 | | /* timer 1 chained with timer 0 ? */ |
1238 | | if ((TMM & 0xe0) == 0x60) |
1239 | | { |
1240 | | CNT1++; |
1241 | | if (CNT1 == TM1) |
1242 | | { |
1243 | | CNT1 = 0; |
1244 | | IRR |= INTFT1; |
1245 | | /* timer F/F source is timer 1 ? */ |
1246 | | if (0x01 == (TMM & 0x03)) |
1247 | | { |
1248 | | TO ^= 1; |
1249 | | m_to_func(TO); |
1250 | | } |
1251 | | } |
1252 | | } |
1253 | 1208 | } |
1254 | 1209 | } |
| 1210 | } |
| 1211 | } |
| 1212 | } |
| 1213 | |
| 1214 | void upd7810_device::upd7810_handle_timer1(int cycles, int clkdiv) |
| 1215 | { |
| 1216 | OVC1 += cycles; |
| 1217 | while (OVC1 >= clkdiv) |
| 1218 | { |
| 1219 | OVC1 -= clkdiv; |
| 1220 | CNT1++; |
| 1221 | if (CNT1 == TM1) |
| 1222 | { |
| 1223 | CNT1 = 0; |
| 1224 | IRR |= INTFT1; |
| 1225 | /* timer F/F source is timer 1 ? */ |
| 1226 | if (0x01 == (TMM & 0x03)) |
| 1227 | { |
| 1228 | TO ^= 1; |
| 1229 | m_to_func(TO); |
| 1230 | } |
| 1231 | } |
| 1232 | } |
| 1233 | } |
| 1234 | |
| 1235 | void upd7810_device::handle_timers(int cycles) |
| 1236 | { |
| 1237 | /**** TIMER 0 ****/ |
| 1238 | if (TMM & 0x10) /* timer 0 upcounter reset ? */ |
| 1239 | CNT0 = 0; |
| 1240 | else |
| 1241 | { |
| 1242 | switch (TMM & 0x0c) /* timer 0 clock source */ |
| 1243 | { |
| 1244 | case 0x00: /* clock divided by 12 */ |
| 1245 | upd7810_handle_timer0(cycles, 12); |
1255 | 1246 | break; |
| 1247 | case 0x04: /* clock divided by 384 */ |
| 1248 | upd7810_handle_timer0(cycles, 384); |
| 1249 | break; |
1256 | 1250 | case 0x08: /* external signal at TI */ |
1257 | 1251 | break; |
1258 | 1252 | case 0x0c: /* disabled */ |
r241597 | r241598 | |
1268 | 1262 | switch (TMM & 0x60) /* timer 1 clock source */ |
1269 | 1263 | { |
1270 | 1264 | case 0x00: /* clock divided by 12 */ |
1271 | | OVC1 += cycles; |
1272 | | while (OVC1 >= 12) |
1273 | | { |
1274 | | OVC1 -= 12; |
1275 | | CNT1++; |
1276 | | if (CNT1 == TM1) |
1277 | | { |
1278 | | CNT1 = 0; |
1279 | | IRR |= INTFT1; |
1280 | | /* timer F/F source is timer 1 ? */ |
1281 | | if (0x01 == (TMM & 0x03)) |
1282 | | { |
1283 | | TO ^= 1; |
1284 | | m_to_func(TO); |
1285 | | } |
1286 | | } |
1287 | | } |
| 1265 | upd7810_handle_timer1(cycles, 12); |
1288 | 1266 | break; |
1289 | 1267 | case 0x20: /* clock divided by 384 */ |
1290 | | OVC1 += cycles; |
1291 | | while (OVC1 >= 384) |
1292 | | { |
1293 | | OVC1 -= 384; |
1294 | | CNT1++; |
1295 | | if (CNT1 == TM1) |
1296 | | { |
1297 | | CNT1 = 0; |
1298 | | IRR |= INTFT1; |
1299 | | /* timer F/F source is timer 1 ? */ |
1300 | | if (0x01 == (TMM & 0x03)) |
1301 | | { |
1302 | | TO ^= 1; |
1303 | | m_to_func(TO); |
1304 | | } |
1305 | | } |
1306 | | } |
| 1268 | upd7810_handle_timer1(cycles, 384); |
1307 | 1269 | break; |
1308 | 1270 | case 0x40: /* external signal at TI */ |
1309 | 1271 | break; |