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r33007 Monday 27th October, 2014 at 17:41:53 UTC by Osso
peplus.c: moved function to driver state and removed various trampolines. (nw)
[src/mame/drivers]jackie.c peplus.c

trunk/src/mame/drivers/jackie.c
r241518r241519
264264}
265265
266266
267void jackie_state::show_out()
268{
269#ifdef MAME_DEBUG
270//  popmessage("%02x %02x %02x", state->m_out[0], state->m_out[1], state->m_out[2]);
271   popmessage("520: %04x %04x %04x %04x %04x\n560: %04x %04x %04x %04x %04x\n5A0: %04x %04x %04x %04x %04x",
272      m_unk_reg[0][0],m_unk_reg[0][1],m_unk_reg[0][2],m_unk_reg[0][3],m_unk_reg[0][4],
273      m_unk_reg[1][0],m_unk_reg[1][1],m_unk_reg[1][2],m_unk_reg[1][3],m_unk_reg[1][4],
267void jackie_state::show_out()
268{
269#ifdef MAME_DEBUG
270//  popmessage("%02x %02x %02x", m_out[0], m_out[1], m_out[2]);
271   popmessage("520: %04x %04x %04x %04x %04x\n560: %04x %04x %04x %04x %04x\n5A0: %04x %04x %04x %04x %04x",
272      m_unk_reg[0][0],m_unk_reg[0][1],m_unk_reg[0][2],m_unk_reg[0][3],m_unk_reg[0][4],
273      m_unk_reg[1][0],m_unk_reg[1][1],m_unk_reg[1][2],m_unk_reg[1][3],m_unk_reg[1][4],
274274      m_unk_reg[2][0],m_unk_reg[2][1],m_unk_reg[2][2],m_unk_reg[2][3],m_unk_reg[2][4]
275275   );
276276#endif
trunk/src/mame/drivers/peplus.c
r241518r241519
203203   {
204204      TIMER_ASSERT_LP
205205   };
206
207   peplus_state(const machine_config &mconfig, device_type type, const char *tag)
208      : driver_device(mconfig, type, tag),
209         m_cmos_ram(*this, "cmos") ,
210      m_program_ram(*this, "prograram"),
211      m_s3000_ram(*this, "s3000_ram"),
212      m_s5000_ram(*this, "s5000_ram"),
206 
207   peplus_state(const machine_config &mconfig, device_type type, const char *tag)
208      : driver_device(mconfig, type, tag),
209      m_maincpu(*this, "maincpu"),
210      m_crtc(*this, "crtc"),
211      m_i2cmem(*this, "i2cmem"),
212      m_screen(*this, "screen"),
213      m_gfxdecode(*this, "gfxdecode"),
214      m_palette(*this, "palette"),
215      m_cmos_ram(*this, "cmos"),
216      m_program_ram(*this, "prograram"),
217      m_s3000_ram(*this, "s3000_ram"),
218      m_s5000_ram(*this, "s5000_ram"),
213219      m_videoram(*this, "videoram"),
214220      m_s7000_ram(*this, "s7000_ram"),
215      m_sb000_ram(*this, "sb000_ram"),
216      m_sd000_ram(*this, "sd000_ram"),
217      m_sf000_ram(*this, "sf000_ram"),
218      m_io_port(*this, "io_port"),
219      m_maincpu(*this, "maincpu"),
220      m_i2cmem(*this, "i2cmem"),
221      m_gfxdecode(*this, "gfxdecode"),
222      m_palette(*this, "palette")
223   {
224   }
225
226   required_shared_ptr<UINT8> m_cmos_ram;
227   required_shared_ptr<UINT8> m_program_ram;
228   required_shared_ptr<UINT8> m_s3000_ram;
221      m_sb000_ram(*this, "sb000_ram"),
222      m_sd000_ram(*this, "sd000_ram"),
223      m_sf000_ram(*this, "sf000_ram"),
224      m_io_port(*this, "io_port")
225   {
226   }
227 
228   required_device<cpu_device> m_maincpu;
229   required_device<r6545_1_device> m_crtc;
230   required_device<i2cmem_device> m_i2cmem;
231   required_device<screen_device> m_screen;
232   required_device<gfxdecode_device> m_gfxdecode;
233   required_device<palette_device> m_palette;
234   
235   required_shared_ptr<UINT8> m_cmos_ram;
236   required_shared_ptr<UINT8> m_program_ram;
237   required_shared_ptr<UINT8> m_s3000_ram;
229238   required_shared_ptr<UINT8> m_s5000_ram;
230239   required_shared_ptr<UINT8> m_videoram;
231240   required_shared_ptr<UINT8> m_s7000_ram;
232241   required_shared_ptr<UINT8> m_sb000_ram;
233   required_shared_ptr<UINT8> m_sd000_ram;
234   required_shared_ptr<UINT8> m_sf000_ram;
235   required_shared_ptr<UINT8> m_io_port;
236   tilemap_t *m_bg_tilemap;
237   UINT8 m_wingboard;
238   UINT8 m_doorcycle;
242   required_shared_ptr<UINT8> m_sd000_ram;
243   required_shared_ptr<UINT8> m_sf000_ram;
244   required_shared_ptr<UINT8> m_io_port;
245   
246   tilemap_t *m_bg_tilemap;
247   UINT8 m_wingboard;
248   UINT8 m_doorcycle;
239249   UINT16 door_wait;
240250   UINT8 m_jumper_e16_e17;
241251   UINT16 m_vid_address;
r241518r241519
257267   UINT8 m_bv_last_enable_state;
258268   UINT8 m_bv_enable_state;
259269   UINT8 m_bv_enable_count;
260   UINT8 m_bv_data_bit;
261   UINT8 m_bv_loop_count;
262   UINT16 id023_data;
263   DECLARE_WRITE8_MEMBER(peplus_bgcolor_w);
264   DECLARE_WRITE8_MEMBER(peplus_crtc_display_w);
265   DECLARE_WRITE8_MEMBER(peplus_io_w);
266   DECLARE_WRITE8_MEMBER(peplus_duart_w);
267   DECLARE_WRITE8_MEMBER(peplus_cmos_w);
268   DECLARE_WRITE8_MEMBER(peplus_s3000_w);
269   DECLARE_WRITE8_MEMBER(peplus_s5000_w);
270   DECLARE_WRITE8_MEMBER(peplus_s7000_w);
271   DECLARE_WRITE8_MEMBER(peplus_sb000_w);
272   DECLARE_WRITE8_MEMBER(peplus_sd000_w);
273   DECLARE_WRITE8_MEMBER(peplus_sf000_w);
274   DECLARE_WRITE8_MEMBER(peplus_output_bank_a_w);
275   DECLARE_WRITE8_MEMBER(peplus_output_bank_b_w);
276   DECLARE_WRITE8_MEMBER(peplus_output_bank_c_w);
277   DECLARE_READ8_MEMBER(peplus_io_r);
278   DECLARE_READ8_MEMBER(peplus_duart_r);
279   DECLARE_READ8_MEMBER(peplus_cmos_r);
280   DECLARE_READ8_MEMBER(peplus_s3000_r);
281   DECLARE_READ8_MEMBER(peplus_s5000_r);
282   DECLARE_READ8_MEMBER(peplus_s7000_r);
283   DECLARE_READ8_MEMBER(peplus_sb000_r);
284   DECLARE_READ8_MEMBER(peplus_sd000_r);
285   DECLARE_READ8_MEMBER(peplus_sf000_r);
286   DECLARE_READ8_MEMBER(peplus_bgcolor_r);
287   DECLARE_READ8_MEMBER(peplus_dropdoor_r);
288   DECLARE_READ8_MEMBER(peplus_watchdog_r);
270   UINT8 m_bv_data_bit;
271   UINT8 m_bv_loop_count;
272   UINT16 id023_data;
273   
274   DECLARE_WRITE8_MEMBER(peplus_bgcolor_w);
275   DECLARE_WRITE8_MEMBER(peplus_crtc_display_w);
276   DECLARE_WRITE8_MEMBER(peplus_duart_w);
277   DECLARE_WRITE8_MEMBER(peplus_cmos_w);
278   DECLARE_WRITE8_MEMBER(peplus_output_bank_a_w);
279   DECLARE_WRITE8_MEMBER(peplus_output_bank_b_w);
280   DECLARE_WRITE8_MEMBER(peplus_output_bank_c_w);
281   DECLARE_READ8_MEMBER(peplus_duart_r);
282   DECLARE_READ8_MEMBER(peplus_bgcolor_r);
283   DECLARE_READ8_MEMBER(peplus_dropdoor_r);
284   DECLARE_READ8_MEMBER(peplus_watchdog_r);
289285   DECLARE_CUSTOM_INPUT_MEMBER(peplus_input_r);
290286   DECLARE_WRITE8_MEMBER(peplus_crtc_mode_w);
291287   DECLARE_WRITE_LINE_MEMBER(crtc_vsync);
r241518r241519
300296   MC6845_ON_UPDATE_ADDR_CHANGED(crtc_addr);
301297   virtual void machine_reset();
302298   virtual void video_start();
303   UINT32 screen_update_peplus(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
304   void peplus_load_superdata(const char *bank_name);
305   DECLARE_PALETTE_INIT(peplus);
306   required_device<cpu_device> m_maincpu;
307   required_device<i2cmem_device> m_i2cmem;
308   required_device<gfxdecode_device> m_gfxdecode;
309   required_device<palette_device> m_palette;
310
311protected:
312   virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
299   UINT32 screen_update_peplus(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
300   void peplus_load_superdata(const char *bank_name);
301   DECLARE_PALETTE_INIT(peplus);
302   void handle_lightpen();
303 
304protected:
305   virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
313306};
314307
315308static const UINT8  id_022[8] = { 0x00, 0x01, 0x04, 0x09, 0x13, 0x16, 0x18, 0x00 };
r241518r241519
389382
390383void peplus_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
391384{
392   switch (id)
393   {
394   case TIMER_ASSERT_LP:
395      downcast<mc6845_device *>((device_t*)ptr)->assert_light_pen_input();
396      break;
397   default:
398      assert_always(FALSE, "Unknown id in peplus_state::device_timer");
385   switch (id)
386   {
387   case TIMER_ASSERT_LP:
388      m_crtc->assert_light_pen_input();
389      break;
390   default:
391      assert_always(FALSE, "Unknown id in peplus_state::device_timer");
399392   }
400}
401
402
403static void handle_lightpen( mc6845_device *device )
393}
394 
395 
396void peplus_state::handle_lightpen()
397{
398   int x_val = ioport("TOUCH_X")->read_safe(0x00);
399   int y_val = ioport("TOUCH_Y")->read_safe(0x00);
400   const rectangle &vis_area = m_screen->visible_area();
401   int xt, yt;
402 
403   xt = x_val * vis_area.width() / 1024 + vis_area.min_x;
404   yt = y_val * vis_area.height() / 1024 + vis_area.min_y;
405 
406   timer_set(m_screen->time_until_pos(yt, xt), TIMER_ASSERT_LP, 0);
407}
408 
409WRITE_LINE_MEMBER(peplus_state::crtc_vsync)
410{
411   m_maincpu->set_input_line(0, state ? ASSERT_LINE : CLEAR_LINE);
412   handle_lightpen();
413}
414 
415WRITE8_MEMBER(peplus_state::peplus_crtc_display_w)
404416{
405   peplus_state *state = device->machine().driver_data<peplus_state>();
406   int x_val = device->machine().root_device().ioport("TOUCH_X")->read_safe(0x00);
407   int y_val = device->machine().root_device().ioport("TOUCH_Y")->read_safe(0x00);
408   const rectangle &vis_area = device->screen().visible_area();
409   int xt, yt;
410
411   xt = x_val * vis_area.width() / 1024 + vis_area.min_x;
412   yt = y_val * vis_area.height() / 1024 + vis_area.min_y;
413
414   state->timer_set(device->screen().time_until_pos(yt, xt), peplus_state::TIMER_ASSERT_LP, 0, device);
415}
416
417WRITE_LINE_MEMBER(peplus_state::crtc_vsync)
418{
419   mc6845_device *device = machine().device<mc6845_device>("crtc");
420   m_maincpu->set_input_line(0, state ? ASSERT_LINE : CLEAR_LINE);
421   handle_lightpen(device);
422}
423
424WRITE8_MEMBER(peplus_state::peplus_crtc_display_w)
425{
426417   UINT8 *videoram = m_videoram;
427418   videoram[m_vid_address] = data;
428419   m_palette_ram[m_vid_address] = m_io_port[1];
429420   m_palette_ram2[m_vid_address] = m_io_port[3];
430421
431   m_bg_tilemap->mark_tile_dirty(m_vid_address);
432
433   /* An access here triggers a device read !*/
434   machine().device<mc6845_device>("crtc")->register_r(space, 0);
435}
436
437WRITE8_MEMBER(peplus_state::peplus_io_w)
422   m_bg_tilemap->mark_tile_dirty(m_vid_address);
423 
424   /* An access here triggers a device read !*/
425   m_crtc->register_r(space, 0);
426}
427 
428WRITE8_MEMBER(peplus_state::peplus_duart_w)
438429{
439   m_io_port[offset] = data;
440}
441
442WRITE8_MEMBER(peplus_state::peplus_duart_w)
443{
444430   // Used for Slot Accounting System Communication
445431}
446432
r241518r241519
455441      peplus_load_superdata(bank_name);
456442   }
457443
458   m_cmos_ram[offset] = data;
459}
460
461WRITE8_MEMBER(peplus_state::peplus_s3000_w)
462{
463   m_s3000_ram[offset] = data;
464}
465
466WRITE8_MEMBER(peplus_state::peplus_s5000_w)
467{
468   m_s5000_ram[offset] = data;
469}
470
471WRITE8_MEMBER(peplus_state::peplus_s7000_w)
472{
473   m_s7000_ram[offset] = data;
474}
475
476WRITE8_MEMBER(peplus_state::peplus_sb000_w)
477{
478   m_sb000_ram[offset] = data;
479}
480
481WRITE8_MEMBER(peplus_state::peplus_sd000_w)
482{
483   m_sd000_ram[offset] = data;
484}
485
486WRITE8_MEMBER(peplus_state::peplus_sf000_w)
487{
488   m_sf000_ram[offset] = data;
489}
490
491WRITE8_MEMBER(peplus_state::peplus_output_bank_a_w)
492{
493   output_set_value("pe_bnka0",(data >> 0) & 1); /* Coin Lockout */
444   m_cmos_ram[offset] = data;
445}
446 
447WRITE8_MEMBER(peplus_state::peplus_output_bank_a_w)
448{
449   output_set_value("pe_bnka0",(data >> 0) & 1); /* Coin Lockout */
494450   output_set_value("pe_bnka1",(data >> 1) & 1); /* Diverter */
495451   output_set_value("pe_bnka2",(data >> 2) & 1); /* Bell */
496452   output_set_value("pe_bnka3",(data >> 3) & 1); /* N/A */
r241518r241519
539495
540496
541497/****************
542* Read Handlers *
543****************/
544
545READ8_MEMBER(peplus_state::peplus_io_r)
546{
547   return m_io_port[offset];
548}
549
550READ8_MEMBER(peplus_state::peplus_duart_r)
551{
552   // Used for Slot Accounting System Communication
553   return 0x00;
554}
555
556READ8_MEMBER(peplus_state::peplus_cmos_r)
557{
558   return m_cmos_ram[offset];
559}
560
561READ8_MEMBER(peplus_state::peplus_s3000_r)
562{
563   return m_s3000_ram[offset];
564}
565
566READ8_MEMBER(peplus_state::peplus_s5000_r)
567{
568   return m_s5000_ram[offset];
569}
570
571READ8_MEMBER(peplus_state::peplus_s7000_r)
572{
573   return m_s7000_ram[offset];
574}
575
576READ8_MEMBER(peplus_state::peplus_sb000_r)
577{
578   return m_sb000_ram[offset];
579}
580
581READ8_MEMBER(peplus_state::peplus_sd000_r)
582{
583   return m_sd000_ram[offset];
584}
585
586READ8_MEMBER(peplus_state::peplus_sf000_r)
587{
588   return m_sf000_ram[offset];
589}
590
591/* Last Color in Every Palette is bgcolor */
592READ8_MEMBER(peplus_state::peplus_bgcolor_r)
593{
498* Read Handlers *
499****************/
500 
501READ8_MEMBER(peplus_state::peplus_duart_r)
502{
503   // Used for Slot Accounting System Communication
504   return 0x00;
505}
506 
507/* Last Color in Every Palette is bgcolor */
508READ8_MEMBER(peplus_state::peplus_bgcolor_r)
509{
594510   return m_palette->pen_color(15); // Return bgcolor from First Palette
595511}
596512
r241518r241519
1053969static ADDRESS_MAP_START( peplus_map, AS_PROGRAM, 8, peplus_state )
1054970   AM_RANGE(0x0000, 0xffff) AM_ROM AM_SHARE("prograram")
1055971ADDRESS_MAP_END
1056
1057static ADDRESS_MAP_START( peplus_iomap, AS_IO, 8, peplus_state )
1058   // Battery-backed RAM (0x1000-0x01fff Extended RAM for Superboards Only)
1059   AM_RANGE(0x0000, 0x1fff) AM_READWRITE(peplus_cmos_r, peplus_cmos_w) AM_SHARE("cmos")
1060
1061   // CRT Controller
1062   AM_RANGE(0x2008, 0x2008) AM_WRITE(peplus_crtc_mode_w)
972 
973static ADDRESS_MAP_START( peplus_iomap, AS_IO, 8, peplus_state )
974   // Battery-backed RAM (0x1000-0x01fff Extended RAM for Superboards Only)
975   AM_RANGE(0x0000, 0x1fff) AM_RAM_WRITE(peplus_cmos_w) AM_SHARE("cmos")
976 
977   // CRT Controller
978   AM_RANGE(0x2008, 0x2008) AM_WRITE(peplus_crtc_mode_w)
1063979   AM_RANGE(0x2080, 0x2080) AM_DEVREADWRITE("crtc", mc6845_device, status_r, address_w)
1064980   AM_RANGE(0x2081, 0x2081) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
1065   AM_RANGE(0x2083, 0x2083) AM_DEVREAD("crtc", mc6845_device, register_r) AM_WRITE(peplus_crtc_display_w)
981   AM_RANGE(0x2083, 0x2083) AM_DEVREAD("crtc", mc6845_device, register_r) AM_WRITE(peplus_crtc_display_w)
982 
983   // Superboard Data
984   AM_RANGE(0x3000, 0x3fff) AM_RAM AM_SHARE("s3000_ram")
985 
986   // Sound and Dipswitches
987   AM_RANGE(0x4000, 0x4000) AM_DEVWRITE("aysnd", ay8910_device, address_w)
988   AM_RANGE(0x4004, 0x4004) AM_READ_PORT("SW1")/* likely ay8910 input port, not direct */ AM_DEVWRITE("aysnd", ay8910_device, data_w)
989 
990   // Superboard Data
991   AM_RANGE(0x5000, 0x5fff) AM_RAM AM_SHARE("s5000_ram")
992 
993   // Background Color Latch
994   AM_RANGE(0x6000, 0x6000) AM_READ(peplus_bgcolor_r) AM_WRITE(peplus_bgcolor_w)
1066995
1067   // Superboard Data
1068   AM_RANGE(0x3000, 0x3fff) AM_READWRITE(peplus_s3000_r, peplus_s3000_w) AM_SHARE("s3000_ram")
1069
1070   // Sound and Dipswitches
1071   AM_RANGE(0x4000, 0x4000) AM_DEVWRITE("aysnd", ay8910_device, address_w)
1072   AM_RANGE(0x4004, 0x4004) AM_READ_PORT("SW1")/* likely ay8910 input port, not direct */ AM_DEVWRITE("aysnd", ay8910_device, data_w)
1073
1074   // Superboard Data
1075   AM_RANGE(0x5000, 0x5fff) AM_READWRITE(peplus_s5000_r, peplus_s5000_w) AM_SHARE("s5000_ram")
1076
1077   // Background Color Latch
1078   AM_RANGE(0x6000, 0x6000) AM_READ(peplus_bgcolor_r) AM_WRITE(peplus_bgcolor_w)
1079
1080996   // Bogus Location for Video RAM
1081   AM_RANGE(0x06001, 0x06400) AM_RAM AM_SHARE("videoram")
997   AM_RANGE(0x06001, 0x06400) AM_RAM AM_SHARE("videoram")
998 
999   // Superboard Data
1000   AM_RANGE(0x7000, 0x7fff) AM_RAM AM_SHARE("s7000_ram")
1001 
1002   // Input Bank A, Output Bank C
1003   AM_RANGE(0x8000, 0x8000) AM_READ(peplus_input_bank_a_r) AM_WRITE(peplus_output_bank_c_w)
10821004
1083   // Superboard Data
1084   AM_RANGE(0x7000, 0x7fff) AM_READWRITE(peplus_s7000_r, peplus_s7000_w) AM_SHARE("s7000_ram")
1085
1086   // Input Bank A, Output Bank C
1087   AM_RANGE(0x8000, 0x8000) AM_READ(peplus_input_bank_a_r) AM_WRITE(peplus_output_bank_c_w)
1088
10891005   // Drop Door, I2C EEPROM Writes
10901006   AM_RANGE(0x9000, 0x9000) AM_READ(peplus_dropdoor_r) AM_WRITE(i2c_nvram_w)
10911007
10921008   // Input Banks B & C, Output Bank B
1093   AM_RANGE(0xa000, 0xa000) AM_READ(peplus_input0_r) AM_WRITE(peplus_output_bank_b_w)
1094
1095   // Superboard Data
1096   AM_RANGE(0xb000, 0xbfff) AM_READWRITE(peplus_sb000_r, peplus_sb000_w) AM_SHARE("sb000_ram")
1097
1098   // Output Bank A
1099   AM_RANGE(0xc000, 0xc000) AM_READ(peplus_watchdog_r) AM_WRITE(peplus_output_bank_a_w)
1100
1101   // Superboard Data
1102   AM_RANGE(0xd000, 0xdfff) AM_READWRITE(peplus_sd000_r, peplus_sd000_w) AM_SHARE("sd000_ram")
1103
1104   // DUART
1105   AM_RANGE(0xe000, 0xe00f) AM_READWRITE(peplus_duart_r, peplus_duart_w)
1106
1107   // Superboard Data
1108   AM_RANGE(0xf000, 0xffff) AM_READWRITE(peplus_sf000_r, peplus_sf000_w) AM_SHARE("sf000_ram")
1109
1110   /* Ports start here */
1111   AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READ(peplus_io_r) AM_WRITE(peplus_io_w) AM_SHARE("io_port")
1112ADDRESS_MAP_END
1113
1114
1009   AM_RANGE(0xa000, 0xa000) AM_READ(peplus_input0_r) AM_WRITE(peplus_output_bank_b_w)
1010 
1011   // Superboard Data
1012   AM_RANGE(0xb000, 0xbfff) AM_RAM AM_SHARE("sb000_ram")
1013 
1014   // Output Bank A
1015   AM_RANGE(0xc000, 0xc000) AM_READ(peplus_watchdog_r) AM_WRITE(peplus_output_bank_a_w)
1016 
1017   // Superboard Data
1018   AM_RANGE(0xd000, 0xdfff) AM_RAM AM_SHARE("sd000_ram")
1019 
1020   // DUART
1021   AM_RANGE(0xe000, 0xe00f) AM_READWRITE(peplus_duart_r, peplus_duart_w)
1022 
1023   // Superboard Data
1024   AM_RANGE(0xf000, 0xffff) AM_RAM AM_SHARE("sf000_ram")
1025 
1026   /* Ports start here */
1027   AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_RAM AM_SHARE("io_port")
1028ADDRESS_MAP_END
1029 
1030 
11151031/*************************
11161032*      Input ports       *
11171033*************************/

https://github.com/mamedev/mame/commit/2b946e17f9e0da6bfdba5915ca81095e55695ac9

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