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r32973 Sunday 26th October, 2014 at 10:32:58 UTC by smf
Convert PSX sio to use devcb. [smf]

[src/emu/bus/psx]	ctlrport.c ctlrport.h
[src/emu/cpu]	cpu.mak
[src/emu/cpu/psx]	sio.c sio.h siodev.c siodev.h
[src/mame/drivers]	ksys573.c taitogn.c zn.c
[src/mame/machine]	cat702.c cat702.h k573cass.c k573cass.h zndip.c zndip.h
[src/mess/drivers]	psx.c

trunk/src/emu/bus/psx/ctlrport.c

r241484	r241485
37	37
38	38	const device_type PSXCONTROLLERPORTS = &device_creator<psxcontrollerports_device>;
39	39
40		psxcontrollerports_device::psxcontrollerports_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
41		psxsiodev_device(mconfig, PSXCONTROLLERPORTS, "PSXCONTROLLERPORTS", tag, owner, clock, "psxcontrollerports", __FILE__)
	40	psxcontrollerports_device::psxcontrollerports_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	41	: device_t(mconfig, PSXCONTROLLERPORTS, "PSXCONTROLLERPORTS", tag, owner, clock, "psxcontrollerports", __FILE__),
	42	m_dsr_handler(*this),
	43	m_rxd_handler(*this)
42	44	{
43	45	}
44	46
45	47	void psxcontrollerports_device::device_start()
46	48	{
	49	m_dsr_handler.resolve_safe();
	50	m_rxd_handler.resolve_safe();
	51
47	52	m_port0 = machine().device<psx_controller_port_device>("port1");
48	53	m_port1 = machine().device<psx_controller_port_device>("port2");
49	54	m_port0->setup_ack_cb(psx_controller_port_device::void_cb(FUNC(psxcontrollerports_device::ack), this));
50	55	m_port1->setup_ack_cb(psx_controller_port_device::void_cb(FUNC(psxcontrollerports_device::ack), this));
51		psxsiodev_device::device_start();
52	56	}
53	57
54	58	// add controllers to define so they can be connected to the multitap
r241484	r241485
66	70	PSX_CONTROLLERS
67	71	SLOT_INTERFACE_END
68	72
69		void psxcontrollerports_device::data_in( int data, int mask )
	73	WRITE_LINE_MEMBER(psxcontrollerports_device::write_dtr)
70	74	{
71		m_port0->sel_w((data & PSX_SIO_OUT_DTR)?1:0);
72		m_port0->tx_w((data & PSX_SIO_OUT_DATA)?1:0);
73		m_port0->clock_w((data & PSX_SIO_OUT_CLOCK)?1:0); // clock must be last
	75	m_port0->sel_w(!state);
	76	m_port1->sel_w(state);
	77	}
74	78
75		m_port1->tx_w((data & PSX_SIO_OUT_DATA)?1:0);
76		m_port1->sel_w((data & PSX_SIO_OUT_DTR)?0:1); // not dtr
77		m_port1->clock_w((data & PSX_SIO_OUT_CLOCK)?1:0);
	79	WRITE_LINE_MEMBER(psxcontrollerports_device::write_sck)
	80	{
	81	m_port0->clock_w(state);
	82	m_port1->clock_w(state);
	83	m_rxd_handler(m_port0->rx_r() && m_port1->rx_r());
	84	}
78	85
79		data_out(((m_port0->rx_r() && m_port1->rx_r()) * PSX_SIO_IN_DATA), PSX_SIO_IN_DATA);
	86	WRITE_LINE_MEMBER(psxcontrollerports_device::write_txd)
	87	{
	88	m_port0->tx_w(state);
	89	m_port1->tx_w(state);
80	90	}
81	91
82	92	void psxcontrollerports_device::ack()
83	93	{
84		data_out((!(m_port0->ack_r() && m_port1->ack_r()) * PSX_SIO_IN_DSR), PSX_SIO_IN_DSR);
	94	m_dsr_handler(m_port0->ack_r() && m_port1->ack_r());
85	95	}
86	96
87	97	device_psx_controller_interface::device_psx_controller_interface(const machine_config &mconfig, device_t &device) :

trunk/src/emu/bus/psx/ctlrport.h

r241484	r241485
3	3	#ifndef __PSXCPORT_H__
4	4	#define __PSXCPORT_H__
5	5
6		#include "cpu/psx/siodev.h"
7	6	#include "memcard.h"
8	7
9	8	#define MCFG_PSX_CTRL_PORT_ADD(_tag, _slot_intf, _def_slot) \
r241484	r241485
25	24	device_psx_controller_interface(const machine_config &mconfig, device_t &device);
26	25	virtual ~device_psx_controller_interface();
27	26
28		void clock_w(bool state) { if(m_clock && !m_sel && !state && !m_memcard) do_pad(); m_clock = state; }
	27	void clock_w(bool state) { if(!m_clock && !m_sel && state && !m_memcard) do_pad(); m_clock = state; }
29	28	void sel_w(bool state);
30	29
31	30	bool rx_r() { return m_rx; }
r241484	r241485
78	77	required_ioport m_pad1;
79	78	};
80	79
81		class psxcontrollerports_device : public psxsiodev_device
	80	#define MCFG_PSX_CONTROLLER_PORTS_DSR_HANDLER(_devcb) \
	81	devcb = &psxcontrollerports_device::set_dsr_handler(*device, DEVCB_##_devcb);
	82
	83	#define MCFG_PSX_CONTROLLER_PORTS_RXD_HANDLER(_devcb) \
	84	devcb = &psxcontrollerports_device::set_rxd_handler(*device, DEVCB_##_devcb);
	85
	86	class psxcontrollerports_device : public device_t
82	87	{
83	88	public:
84	89	psxcontrollerports_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
85	90	void ack();
86	91
	92	template<class _Object> static devcb_base &set_dsr_handler(device_t &device, _Object object) { return downcast<psxcontrollerports_device &>(device).m_dsr_handler.set_callback(object); }
	93	template<class _Object> static devcb_base &set_rxd_handler(device_t &device, _Object object) { return downcast<psxcontrollerports_device &>(device).m_rxd_handler.set_callback(object); }
	94
	95	DECLARE_WRITE_LINE_MEMBER(write_sck);
	96	DECLARE_WRITE_LINE_MEMBER(write_dtr);
	97	DECLARE_WRITE_LINE_MEMBER(write_txd);
	98
87	99	protected:
88	100	virtual void device_start();
89	101
90	102	private:
91		virtual void data_in(int data, int mask);
92
93	103	psx_controller_port_device *m_port0;
94	104	psx_controller_port_device *m_port1;
	105
	106	devcb_write_line m_dsr_handler;
	107	devcb_write_line m_rxd_handler;
95	108	};
96	109
97	110	class psx_controller_port_device :  public device_t,

trunk/src/emu/cpu/cpu.mak

r241484	r241485
1174	1174
1175	1175	ifneq ($(filter PSX,$(CPUS)),)
1176	1176	OBJDIRS += $(CPUOBJ)/psx
1177		CPUOBJS += $(CPUOBJ)/psx/psx.o $(CPUOBJ)/psx/gte.o $(CPUOBJ)/psx/dma.o $(CPUOBJ)/psx/irq.o $(CPUOBJ)/psx/mdec.o $(CPUOBJ)/psx/rcnt.o $(CPUOBJ)/psx/sio.o $(CPUOBJ)/psx/siodev.o
	1177	CPUOBJS += $(CPUOBJ)/psx/psx.o $(CPUOBJ)/psx/gte.o $(CPUOBJ)/psx/dma.o $(CPUOBJ)/psx/irq.o $(CPUOBJ)/psx/mdec.o $(CPUOBJ)/psx/rcnt.o $(CPUOBJ)/psx/sio.o
1178	1178	DASMOBJS += $(CPUOBJ)/psx/psxdasm.o
1179	1179	endif
1180	1180

trunk/src/emu/cpu/psx/sio.c

r241484	r241485
39	39
40	40	psxsio_device::psxsio_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source) :
41	41	device_t(mconfig, type, name, tag, owner, clock, shortname, source),
42		m_irq_handler(*this)
	42	m_status(SIO_STATUS_TX_EMPTY | SIO_STATUS_TX_RDY),
	43	m_rxd(1),
	44	m_irq_handler(*this),
	45	m_sck_handler(*this),
	46	m_txd_handler(*this),
	47	m_dtr_handler(*this),
	48	m_rts_handler(*this)
43	49	{
44	50	}
45	51
r241484	r241485
51	57	void psxsio_device::device_start()
52	58	{
53	59	m_irq_handler.resolve_safe();
	60	m_sck_handler.resolve_safe();
	61	m_txd_handler.resolve_safe();
	62	m_dtr_handler.resolve_safe();
	63	m_rts_handler.resolve_safe();
54	64
55	65	m_timer = timer_alloc( 0 );
56		m_status = SIO_STATUS_TX_EMPTY | SIO_STATUS_TX_RDY;
57	66	m_mode = 0;
58	67	m_control = 0;
59	68	m_baud = 0;
60		m_tx = 0;
61		m_rx = 0;
62		m_tx_prev = 0;
63		m_rx_prev = 0;
64	69	m_rx_data = 0;
65	70	m_tx_data = 0;
66	71	m_rx_shift = 0;
r241484	r241485
72	77	save_item( NAME( m_mode ) );
73	78	save_item( NAME( m_control ) );
74	79	save_item( NAME( m_baud ) );
75		save_item( NAME( m_tx ) );
76		save_item( NAME( m_rx ) );
77		save_item( NAME( m_tx_prev ) );
78		save_item( NAME( m_rx_prev ) );
	80	save_item( NAME( m_rxd ) );
79	81	save_item( NAME( m_rx_data ) );
80	82	save_item( NAME( m_tx_data ) );
81	83	save_item( NAME( m_rx_shift ) );
82	84	save_item( NAME( m_tx_shift ) );
83	85	save_item( NAME( m_rx_bits ) );
84	86	save_item( NAME( m_tx_bits ) );
85
86		deviceCount = 0;
87
88		for( device_t *device = first_subdevice(); device != NULL; device = device->next() )
89		{
90		psxsiodev_device *psxsiodev = dynamic_cast<psxsiodev_device *>(device);
91		if( psxsiodev != NULL )
92		{
93		devices[ deviceCount++ ] = psxsiodev;
94		psxsiodev->m_psxsio = this;
95		}
96		}
97
98		input_update();
99	87	}
100	88
101	89	void psxsio_device::sio_interrupt()
r241484	r241485
149	137	m_timer->adjust( n_time );
150	138	}
151	139
152		void psxsio_device::output( int data, int mask )
153		{
154		int new_outputdata = ( m_outputdata & ~mask ) | ( data & mask );
155		int new_mask = m_outputdata ^ new_outputdata;
156
157		if( new_mask != 0 )
158		{
159		m_outputdata = new_outputdata;
160
161		for( int i = 0; i < deviceCount; i++ )
162		{
163		devices[ i ]->data_in( m_outputdata, new_mask );
164		}
165		}
166		}
167
168	140	void psxsio_device::device_timer(emu_timer &timer, device_timer_id tid, int param, void *ptr)
169	141	{
170	142	verboselog( machine(), 2, "sio tick\n" );
r241484	r241485
188	160
189	161	if( m_tx_bits != 0 )
190	162	{
191		m_tx = ( m_tx & ~PSX_SIO_OUT_DATA ) | ( ( m_tx_shift & 1 ) * PSX_SIO_OUT_DATA );
	163	if( type() == PSX_SIO0 )
	164	{
	165	m_sck_handler(0);
	166	}
	167
	168	m_txd_handler( m_tx_shift & 1 );
192	169	m_tx_shift >>= 1;
193	170	m_tx_bits--;
194	171
195	172	if( type() == PSX_SIO0 )
196	173	{
197		m_tx &= ~PSX_SIO_OUT_CLOCK;
198		output( m_tx, PSX_SIO_OUT_CLOCK | PSX_SIO_OUT_DATA );
199		m_tx |= PSX_SIO_OUT_CLOCK;
	174	m_sck_handler(1);
200	175	}
201	176
202		output( m_tx, PSX_SIO_OUT_CLOCK | PSX_SIO_OUT_DATA );
203
204	177	if( m_tx_bits == 0 &&
205	178	( m_control & SIO_CONTROL_TX_IENA ) != 0 )
206	179	{
r241484	r241485
210	183
211	184	if( m_rx_bits != 0 )
212	185	{
213		m_rx_shift = ( m_rx_shift >> 1 ) | ( ( ( m_rx & PSX_SIO_IN_DATA ) / PSX_SIO_IN_DATA ) << 7 );
	186	m_rx_shift = ( m_rx_shift >> 1 ) | ( m_rxd << 7 );
214	187	m_rx_bits--;
215	188
216	189	if( m_rx_bits == 0 )
r241484	r241485
265	238	verboselog( machine(), 1, "psx_sio_w reset\n" );
266	239	m_status |= SIO_STATUS_TX_EMPTY | SIO_STATUS_TX_RDY;
267	240	m_status &= ~( SIO_STATUS_RX_RDY | SIO_STATUS_OVERRUN | SIO_STATUS_IRQ );
	241	m_irq_handler(0);
268	242
269	243	// toggle DTR to reset controllers, Star Ocean 2, at least, requires it
270	244	// the precise mechanism of the reset is unknown
271	245	// maybe it's related to the bottom 2 bits of control which are usually set
272		output( m_tx ^ PSX_SIO_OUT_DTR, PSX_SIO_OUT_DTR );
	246	m_dtr_handler(0);
	247	m_dtr_handler(1);
	248
	249	m_tx_bits = 0;
	250	m_rx_bits = 0;
	251	m_txd_handler(1);
273	252	}
274	253	if( ( m_control & SIO_CONTROL_IACK ) != 0 )
275	254	{
276	255	verboselog( machine(), 1, "psx_sio_w iack\n" );
277	256	m_status &= ~( SIO_STATUS_IRQ );
278	257	m_control &= ~( SIO_CONTROL_IACK );
	258	m_irq_handler(0);
279	259	}
280	260	if( ( m_control & SIO_CONTROL_DTR ) != 0 )
281	261	{
282		m_tx |= PSX_SIO_OUT_DTR;
	262	m_dtr_handler(0);
283	263	}
284	264	else
285	265	{
286		m_tx &= ~PSX_SIO_OUT_DTR;
	266	m_dtr_handler(1);
287	267	}
288
289		output( m_tx, PSX_SIO_OUT_DTR );
290
291		m_tx_prev = m_tx;
292
293	268	}
294	269	break;
295	270	case 3:
r241484	r241485
362	337	return data;
363	338	}
364	339
365		void psxsio_device::input_update()
	340	WRITE_LINE_MEMBER(psxsio_device::write_rxd)
366	341	{
367		int data = 0;
	342	m_rxd = state;
	343	}
368	344
369		for( int i = 0; i < deviceCount; i++ )
	345	WRITE_LINE_MEMBER(psxsio_device::write_dsr)
	346	{
	347	if (state)
370	348	{
371		data |= devices[ i ]->m_dataout;
	349	m_status &= ~SIO_STATUS_DSR;
372	350	}
373
374		int mask = data ^ m_rx;
375
376		verboselog( machine(), 1, "input_update( %s, %02x, %02x )\n", tag(), mask, data );
377
378		m_rx = data;
379
380		if( ( m_rx & PSX_SIO_IN_DSR ) != 0 )
	351	else if ((m_status & SIO_STATUS_DSR) == 0)
381	352	{
382	353	m_status |= SIO_STATUS_DSR;
383		if( ( m_rx_prev & PSX_SIO_IN_DSR ) == 0 &&
384		( m_control & SIO_CONTROL_DSR_IENA ) != 0 )
	354
	355	if( ( m_control & SIO_CONTROL_DSR_IENA ) != 0 )
385	356	{
386	357	sio_interrupt();
387	358	}
388	359	}
389		else
390		{
391		m_status &= ~SIO_STATUS_DSR;
392		}
393		m_rx_prev = m_rx;
394	360	}

trunk/src/emu/cpu/psx/sio.h

r241484	r241485
13	13	#define __PSXSIO_H__
14	14
15	15	#include "emu.h"
16		#include "siodev.h"
17	16
18	17	extern const device_type PSX_SIO0;
19	18	extern const device_type PSX_SIO1;
20	19
21	20	#define MCFG_PSX_SIO_IRQ_HANDLER(_devcb) \
22	21	devcb = &psxsio_device::set_irq_handler(*device, DEVCB_##_devcb);
	22
	23	#define MCFG_PSX_SIO_SCK_HANDLER(_devcb) \
	24	devcb = &psxsio_device::set_sck_handler(*device, DEVCB_##_devcb);
	25
	26	#define MCFG_PSX_SIO_TXD_HANDLER(_devcb) \
	27	devcb = &psxsio_device::set_txd_handler(*device, DEVCB_##_devcb);
	28
	29	#define MCFG_PSX_SIO_DTR_HANDLER(_devcb) \
	30	devcb = &psxsio_device::set_dtr_handler(*device, DEVCB_##_devcb);
	31
	32	#define MCFG_PSX_SIO_RTS_HANDLER(_devcb) \
	33	devcb = &psxsio_device::set_rts_handler(*device, DEVCB_##_devcb);
	34
23	35	#define SIO_BUF_SIZE ( 8 )
24	36
25	37	#define SIO_STATUS_TX_RDY ( 1 << 0 )
r241484	r241485
44	56
45	57	// static configuration helpers
46	58	template<class _Object> static devcb_base &set_irq_handler(device_t &device, _Object object) { return downcast<psxsio_device &>(device).m_irq_handler.set_callback(object); }
	59	template<class _Object> static devcb_base &set_sck_handler(device_t &device, _Object object) { return downcast<psxsio_device &>(device).m_sck_handler.set_callback(object); }
	60	template<class _Object> static devcb_base &set_txd_handler(device_t &device, _Object object) { return downcast<psxsio_device &>(device).m_txd_handler.set_callback(object); }
	61	template<class _Object> static devcb_base &set_dtr_handler(device_t &device, _Object object) { return downcast<psxsio_device &>(device).m_dtr_handler.set_callback(object); }
	62	template<class _Object> static devcb_base &set_rts_handler(device_t &device, _Object object) { return downcast<psxsio_device &>(device).m_rts_handler.set_callback(object); }
47	63
48	64	DECLARE_WRITE32_MEMBER( write );
49	65	DECLARE_READ32_MEMBER( read );
50	66
51		void input_update();
	67	DECLARE_WRITE_LINE_MEMBER(write_rxd);
	68	DECLARE_WRITE_LINE_MEMBER(write_dsr);
	69	DECLARE_WRITE_LINE_MEMBER(write_cts);
52	70
53	71	protected:
54	72	// device-level overrides
r241484	r241485
57	75	virtual void device_post_load();
58	76
59	77	private:
60		void output( int data, int mask );
61	78	void sio_interrupt();
62	79	void sio_timer_adjust();
63	80
r241484	r241485
65	82	UINT32 m_mode;
66	83	UINT32 m_control;
67	84	UINT32 m_baud;
68		UINT32 m_tx;
69		UINT32 m_rx;
70		UINT32 m_tx_prev;
71		UINT32 m_rx_prev;
	85	int m_rxd;
72	86	UINT32 m_tx_data;
73	87	UINT32 m_rx_data;
74	88	UINT32 m_tx_shift;
r241484	r241485
79	93	emu_timer *m_timer;
80	94
81	95	devcb_write_line m_irq_handler;
82
83		psxsiodev_device *devices[ 10 ];
84		int deviceCount;
85
86		int m_outputdata;
87		//int m_inputdata;
	96	devcb_write_line m_sck_handler;
	97	devcb_write_line m_txd_handler;
	98	devcb_write_line m_dtr_handler;
	99	devcb_write_line m_rts_handler;
88	100	};
89	101
90	102	class psxsio0_device : public psxsio_device

trunk/src/emu/cpu/psx/siodev.c

r241484	r241485
1		// license:MAME
2		// copyright-holders:smf
3		#include "sio.h"
4		#include "siodev.h"
5
6		psxsiodev_device::psxsiodev_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source) :
7		device_t(mconfig, type, name, tag, owner, clock, shortname, source),
8		m_dataout(0)
9		{
10		}
11
12		void psxsiodev_device::device_start()
13		{
14		m_dataout = 0;
15		}
16
17		void psxsiodev_device::data_out( int data, int mask )
18		{
19		m_dataout = ( m_dataout & ~mask ) | ( data & mask );
20
21		m_psxsio->input_update();
22		}

trunk/src/emu/cpu/psx/siodev.h

r241484	r241485
1		// license:MAME
2		// copyright-holders:smf
3		#pragma once
4
5		#include "emu.h"
6
7		#ifndef _PSXSIODEV_H_
8		#define _PSXSIODEV_H_
9
10		#define PSX_SIO_OUT_DATA ( 1 )  /* COMMAND */
11		#define PSX_SIO_OUT_DTR ( 2 )   /* ATT */
12		#define PSX_SIO_OUT_RTS ( 4 )
13		#define PSX_SIO_OUT_CLOCK ( 8 ) /* CLOCK */
14		#define PSX_SIO_IN_DATA ( 1 )   /* DATA */
15		#define PSX_SIO_IN_DSR ( 2 )    /* ACK */
16		#define PSX_SIO_IN_CTS ( 4 )
17
18		class psxsio_device;
19
20		class psxsiodev_device : public device_t
21		{
22		friend class psxsio_device;
23
24		public:
25		// construction/destruction
26		psxsiodev_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
27
28		protected:
29		// device-level overrides
30		virtual void device_start();
31
32		void data_out( int data, int mask );
33
34		private:
35		psxsio_device *m_psxsio;
36
37		virtual void data_in( int data, int mask ) = 0;
38		int m_dataout;
39		};
40
41		#endif

trunk/src/mame/drivers/ksys573.c

r241484	r241485
2038	2038	MCFG_SLOT_OPTION_MACHINE_CONFIG( "cr589", cr589_config )
2039	2039	MCFG_SLOT_DEFAULT_OPTION( "cr589" )
2040	2040
2041		MCFG_DEVICE_ADD( "maincpu:sio1:cassette", KONAMI573_CASSETTE_SLOT_SERIAL, 0 )
2042
2043	2041	MCFG_DEVICE_ADD( "cassette", KONAMI573_CASSETTE_SLOT, 0 )
	2042	MCFG_KONAMI573_CASSETTE_DSR_HANDLER(DEVWRITELINE( "maincpu:sio1", psxsio1_device, write_dsr ) )
2044	2043
2045	2044	// onboard flash
2046	2045	MCFG_FUJITSU_29F016A_ADD( "29f016a.31m" )

trunk/src/mame/drivers/taitogn.c

r241484	r241485
346	346	public:
347	347	taitogn_state(const machine_config &mconfig, device_type type, const char *tag) :
348	348	driver_device(mconfig, type, tag),
349		m_cat702_1(*this,"maincpu:sio0:cat702_1"),
350		m_cat702_2(*this,"maincpu:sio0:cat702_2"),
351		m_zndip(*this,"maincpu:sio0:zndip"),
	349	m_sio0(*this, "maincpu:sio0"),
	350	m_cat702_1(*this, "cat702_1"),
	351	m_cat702_2(*this, "cat702_2"),
	352	m_zndip(*this, "zndip"),
352	353	m_maincpu(*this, "maincpu"),
353	354	m_mn10200(*this, "mn10200"),
354	355	m_flashbank(*this, "flashbank"),
r241484	r241485
358	359	m_sndflash0(*this, "sndflash0"),
359	360	m_sndflash1(*this, "sndflash1"),
360	361	m_sndflash2(*this, "sndflash2"),
361		m_has_zoom(true)
	362	m_has_zoom(true),
	363	m_cat702_1_dataout(1),
	364	m_cat702_2_dataout(1),
	365	m_zndip_dataout(1)
362	366	{
363	367	}
364	368
	369	DECLARE_WRITE_LINE_MEMBER(sio0_sck){ m_cat702_1->write_clock(state);  m_cat702_2->write_clock(state); m_zndip->write_clock(state); }
	370	DECLARE_WRITE_LINE_MEMBER(sio0_txd){ m_cat702_1->write_datain(state);  m_cat702_2->write_datain(state); }
	371	DECLARE_WRITE_LINE_MEMBER(cat702_1_dataout){ m_cat702_1_dataout = state; update_sio0_rxd(); }
	372	DECLARE_WRITE_LINE_MEMBER(cat702_2_dataout){ m_cat702_2_dataout = state; update_sio0_rxd(); }
	373	DECLARE_WRITE_LINE_MEMBER(zndip_dataout){ m_zndip_dataout = state; update_sio0_rxd(); }
	374	void update_sio0_rxd() { m_sio0->write_rxd(m_cat702_1_dataout && m_cat702_2_dataout && m_zndip_dataout); }
365	375	DECLARE_READ8_MEMBER(control_r);
366	376	DECLARE_WRITE8_MEMBER(control_w);
367	377	DECLARE_WRITE16_MEMBER(control2_w);
r241484	r241485
384	394	virtual void machine_reset();
385	395
386	396	private:
	397	required_device<psxsio0_device> m_sio0;
387	398	required_device<cat702_device> m_cat702_1;
388	399	required_device<cat702_device> m_cat702_2;
389	400	required_device<zndip_device> m_zndip;
r241484	r241485
406	417	UINT8 m_n_znsecsel;
407	418
408	419	UINT8 m_coin_info;
	420
	421	int m_cat702_1_dataout;
	422	int m_cat702_2_dataout;
	423	int m_zndip_dataout;
409	424	};
410	425
411	426
r241484	r241485
511	526
512	527	WRITE8_MEMBER(taitogn_state::znsecsel_w)
513	528	{
514		m_cat702_1->select( ( data >> 2 ) & 1 );
515		m_cat702_2->select( ( data >> 3 ) & 1 );
516		m_zndip->select( ( data & 0x8c ) != 0x8c );
	529	m_cat702_1->write_select((data >> 2) & 1);
	530	m_cat702_2->write_select((data >> 3) & 1);
	531	m_zndip->write_select((data & 0x8c) != 0x8c);
517	532
518	533	m_n_znsecsel = data;
519	534	}
r241484	r241485
657	672	MCFG_RAM_MODIFY("maincpu:ram")
658	673	MCFG_RAM_DEFAULT_SIZE("4M")
659	674
660		MCFG_DEVICE_ADD("maincpu:sio0:cat702_1", CAT702, 0)
661		MCFG_DEVICE_ADD("maincpu:sio0:cat702_2", CAT702, 0)
662		MCFG_DEVICE_ADD("maincpu:sio0:zndip", ZNDIP, 0)
	675	MCFG_DEVICE_MODIFY("maincpu:sio0")
	676	MCFG_PSX_SIO_SCK_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, taitogn_state, sio0_sck))
	677	MCFG_PSX_SIO_TXD_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, taitogn_state, sio0_txd))
	678
	679	MCFG_DEVICE_ADD("cat702_1", CAT702, 0)
	680	MCFG_CAT702_DATAOUT_HANDLER(WRITELINE(taitogn_state, cat702_1_dataout))
	681
	682	MCFG_DEVICE_ADD("cat702_2", CAT702, 0)
	683	MCFG_CAT702_DATAOUT_HANDLER(WRITELINE(taitogn_state, cat702_2_dataout))
	684
	685	MCFG_DEVICE_ADD("zndip", ZNDIP, 0)
	686	MCFG_ZNDIP_DATAOUT_HANDLER(WRITELINE(taitogn_state, zndip_dataout))
	687	MCFG_ZNDIP_DSR_HANDLER(DEVWRITELINE("maincpu:sio0", psxsio0_device, write_dsr))
663	688	MCFG_ZNDIP_DATA_HANDLER(IOPORT(":DSW"))
664	689
665	690	MCFG_AT28C16_ADD( "at28c16", 0 )

trunk/src/mame/drivers/zn.c

r241484	r241485
38	38	driver_device(mconfig, type, tag),
39	39	m_gpu(*this, "gpu"),
40	40	m_gpu_screen(*this, "gpu:screen"),
41		m_cat702_1(*this,"maincpu:sio0:cat702_1"),
42		m_cat702_2(*this,"maincpu:sio0:cat702_2"),
43		m_zndip(*this,"maincpu:sio0:zndip"),
	41	m_sio0(*this, "maincpu:sio0"),
	42	m_cat702_1(*this, "cat702_1"),
	43	m_cat702_2(*this, "cat702_2"),
	44	m_zndip(*this, "zndip"),
44	45	m_maincpu(*this, "maincpu"),
45	46	m_audiocpu(*this, "audiocpu"),
46	47	m_ram(*this, "maincpu:ram"),
r241484	r241485
48	49	m_cbaj_fifo2(*this, "cbaj_fifo2"),
49	50	m_mb3773(*this, "mb3773"),
50	51	m_zoom(*this, "taito_zoom"),
51		m_vt83c461(*this, "ide")
	52	m_vt83c461(*this, "ide"),
	53	m_cat702_1_dataout(1),
	54	m_cat702_2_dataout(1),
	55	m_zndip_dataout(1)
52	56	{
53	57	}
54	58
	59	DECLARE_WRITE_LINE_MEMBER(sio0_sck){ m_cat702_1->write_clock(state);  m_cat702_2->write_clock(state); m_zndip->write_clock(state); }
	60	DECLARE_WRITE_LINE_MEMBER(sio0_txd){ m_cat702_1->write_datain(state);  m_cat702_2->write_datain(state); }
	61	DECLARE_WRITE_LINE_MEMBER(cat702_1_dataout){ m_cat702_1_dataout = state; update_sio0_rxd(); }
	62	DECLARE_WRITE_LINE_MEMBER(cat702_2_dataout){ m_cat702_2_dataout = state; update_sio0_rxd(); }
	63	DECLARE_WRITE_LINE_MEMBER(zndip_dataout){ m_zndip_dataout = state; update_sio0_rxd(); }
	64	void update_sio0_rxd() { m_sio0->write_rxd( m_cat702_1_dataout && m_cat702_2_dataout && m_zndip_dataout ); }
55	65	DECLARE_CUSTOM_INPUT_MEMBER(jdredd_gun_mux_read);
56	66	DECLARE_READ8_MEMBER(znsecsel_r);
57	67	DECLARE_WRITE8_MEMBER(znsecsel_w);
r241484	r241485
124	134
125	135	required_device<psxgpu_device> m_gpu;
126	136	required_device<screen_device> m_gpu_screen;
	137	required_device<psxsio0_device> m_sio0;
127	138	required_device<cat702_device> m_cat702_1;
128	139	required_device<cat702_device> m_cat702_2;
129	140	required_device<zndip_device> m_zndip;
r241484	r241485
135	146	optional_device<mb3773_device> m_mb3773;
136	147	optional_device<taito_zoom_device> m_zoom;
137	148	optional_device<vt83c461_device> m_vt83c461;
	149
	150	int m_cat702_1_dataout;
	151	int m_cat702_2_dataout;
	152	int m_zndip_dataout;
138	153	};
139	154
140	155	inline void ATTR_PRINTF(3,4) zn_state::verboselog( int n_level, const char *s_fmt, ... )
r241484	r241485
333	348	{
334	349	verboselog(2, "znsecsel_w( %08x, %08x, %08x )\n", offset, data, mem_mask );
335	350
336		m_cat702_1->select( ( data >> 2 ) & 1 );
337		m_cat702_2->select( ( data >> 3 ) & 1 );
338		m_zndip->select( ( data & 0x8c ) != 0x8c );
	351	m_cat702_1->write_select((data >> 2) & 1);
	352	m_cat702_2->write_select((data >> 3) & 1);
	353	m_zndip->write_select((data & 0x8c) != 0x8c);
339	354
340	355	m_n_znsecsel = data;
341	356	}
r241484	r241485
449	464	MCFG_RAM_MODIFY("maincpu:ram")
450	465	MCFG_RAM_DEFAULT_SIZE("4M")
451	466
452		MCFG_DEVICE_ADD("maincpu:sio0:cat702_1", CAT702, 0)
453		MCFG_DEVICE_ADD("maincpu:sio0:cat702_2", CAT702, 0)
454		MCFG_DEVICE_ADD("maincpu:sio0:zndip", ZNDIP, 0)
	467	MCFG_DEVICE_MODIFY("maincpu:sio0")
	468	MCFG_PSX_SIO_SCK_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, zn_state, sio0_sck))
	469	MCFG_PSX_SIO_TXD_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, zn_state, sio0_txd))
	470
	471	MCFG_DEVICE_ADD("cat702_1", CAT702, 0)
	472	MCFG_CAT702_DATAOUT_HANDLER(WRITELINE(zn_state, cat702_1_dataout))
	473
	474	MCFG_DEVICE_ADD("cat702_2", CAT702, 0)
	475	MCFG_CAT702_DATAOUT_HANDLER(WRITELINE(zn_state, cat702_2_dataout))
	476
	477	MCFG_DEVICE_ADD("zndip", ZNDIP, 0)
	478	MCFG_ZNDIP_DATAOUT_HANDLER(WRITELINE(zn_state, zndip_dataout))
	479	MCFG_ZNDIP_DSR_HANDLER(DEVWRITELINE("maincpu:sio0", psxsio0_device, write_dsr))
455	480	MCFG_ZNDIP_DATA_HANDLER(IOPORT(":DSW"))
456	481
457	482	// 5MHz NEC uPD78081 MCU:
r241484	r241485
483	508	MCFG_RAM_MODIFY("maincpu:ram")
484	509	MCFG_RAM_DEFAULT_SIZE("4M")
485	510
486		MCFG_DEVICE_ADD("maincpu:sio0:cat702_1", CAT702, 0)
487		MCFG_DEVICE_ADD("maincpu:sio0:cat702_2", CAT702, 0)
488		MCFG_DEVICE_ADD("maincpu:sio0:zndip", ZNDIP, 0)
	511	MCFG_DEVICE_MODIFY("maincpu:sio0")
	512	MCFG_PSX_SIO_SCK_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, zn_state, sio0_sck))
	513	MCFG_PSX_SIO_TXD_HANDLER(DEVWRITELINE(DEVICE_SELF_OWNER, zn_state, sio0_txd))
	514
	515	MCFG_DEVICE_ADD("cat702_1", CAT702, 0)
	516	MCFG_CAT702_DATAOUT_HANDLER(WRITELINE(zn_state, cat702_1_dataout))
	517
	518	MCFG_DEVICE_ADD("cat702_2", CAT702, 0)
	519	MCFG_CAT702_DATAOUT_HANDLER(WRITELINE(zn_state, cat702_2_dataout))
	520
	521	MCFG_DEVICE_ADD("zndip", ZNDIP, 0)
	522	MCFG_ZNDIP_DATAOUT_HANDLER(WRITELINE(zn_state, zndip_dataout))
	523	MCFG_ZNDIP_DSR_HANDLER(DEVWRITELINE("maincpu:sio0", psxsio0_device, write_dsr))
489	524	MCFG_ZNDIP_DATA_HANDLER(IOPORT(":DSW"))
490	525
491	526	// 5MHz NEC uPD78081 MCU:

trunk/src/mame/machine/cat702.c

r241484	r241485
87	87	const device_type CAT702 = &device_creator<cat702_device>;
88	88
89	89	cat702_device::cat702_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
90		psxsiodev_device(mconfig, CAT702, "CAT702", tag, owner, clock, "cat702", __FILE__)
	90	device_t(mconfig, CAT702, "CAT702", tag, owner, clock, "cat702", __FILE__),
	91	m_dataout_handler(*this)
91	92	{
92	93	}
93	94
94	95	void cat702_device::device_start()
95	96	{
96		psxsiodev_device::device_start();
	97	m_dataout_handler.resolve_safe();
97	98
98	99	save_item(NAME(m_select));
99	100	save_item(NAME(m_state));
100	101	save_item(NAME(m_bit));
	102
	103	m_dataout_handler(1);
101	104	}
102	105
103	106	// Given the value for x7..x0 and linear transform coefficients a7..a0
r241484	r241485
159	162	m_transform = transform;
160	163	}
161	164
162		void cat702_device::select(int select)
	165	WRITE_LINE_MEMBER(cat702_device::write_select)
163	166	{
164		if (m_select != select)
	167	if (m_select != state)
165	168	{
166		if (!select)
	169	if (!state)
167	170	{
168	171	m_state = 0xfc;
169	172	m_bit = 0;
170	173	}
171	174	else
172	175	{
173		data_out(0, PSX_SIO_IN_DATA);
	176	m_dataout_handler(1);
174	177	}
175	178
176		m_select = select;
	179	m_select = state;
177	180	}
178	181	}
179	182
180		void cat702_device::data_in( int data, int mask )
	183	WRITE_LINE_MEMBER(cat702_device::write_clock)
181	184	{
182	185	static const UINT8 initial_sbox[8] = { 0xff, 0xfe, 0xfc, 0xf8, 0xf0, 0xe0, 0xc0, 0x7f };
183	186
184		if ( !m_select && (mask & PSX_SIO_OUT_CLOCK) != 0 && (data & PSX_SIO_OUT_CLOCK) == 0)
	187	if (!state && m_clock && !m_select)
185	188	{
186	189	if (m_bit==0)
187	190	{
r241484	r241485
190	193	}
191	194
192	195	// Compute the output and change the state
193		data_out(((m_state >> m_bit) & 1) != 0 ? PSX_SIO_IN_DATA : 0, PSX_SIO_IN_DATA);
	196	m_dataout_handler(((m_state >> m_bit) & 1) != 0);
	197	}
194	198
195		if((data & PSX_SIO_OUT_DATA)==0)
	199	if (state && !m_clock && !m_select)
	200	{
	201	if (!m_datain)
196	202	apply_bit_sbox(m_bit);
197	203
198	204	m_bit++;
199	205	m_bit&=7;
200	206	}
	207
	208	m_clock = state;
201	209	}
	210
	211	WRITE_LINE_MEMBER(cat702_device::write_datain)
	212	{
	213	m_datain = state;
	214	}

trunk/src/mame/machine/cat702.h

r241484	r241485
1		/*  CAT702 ZN security chip */
	1	/*  CAT702 security chip */
2	2
3	3	#pragma once
4	4
5	5	#ifndef __CAT702_H__
6	6	#define __CAT702_H__
7	7
8		#include "cpu/psx/siodev.h"
	8	#include "emu.h"
9	9
10	10	extern const device_type CAT702;
11	11
12		class cat702_device : public psxsiodev_device
	12	#define MCFG_CAT702_DATAOUT_HANDLER(_devcb) \
	13	devcb = &cat702_device::set_dataout_handler(*device, DEVCB_##_devcb);
	14
	15	class cat702_device : public device_t
13	16	{
14	17	public:
15	18	cat702_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
16	19
17		void init(const UINT8 *transform);
18		void select(int select);
	20	// static configuration helpers
	21	template<class _Object> static devcb_base &set_dataout_handler(device_t &device, _Object object) { return downcast<cat702_device &>(device).m_dataout_handler.set_callback(object); }
19	22
	23	void init(const UINT8 *transform); // TODO: region
	24
	25	DECLARE_WRITE_LINE_MEMBER(write_select);
	26	DECLARE_WRITE_LINE_MEMBER(write_datain);
	27	DECLARE_WRITE_LINE_MEMBER(write_clock);
	28
20	29	protected:
21	30	virtual void device_start();
22	31
23	32	private:
24		virtual void data_in( int data, int mask );
25
26	33	UINT8 compute_sbox_coef(int sel, int bit);
27	34	void apply_bit_sbox(int sel);
28	35	void apply_sbox(const UINT8 *sbox);
29	36
30	37	const UINT8 *m_transform;
31	38	int m_select;
	39	int m_clock;
	40	int m_datain;
32	41	UINT8 m_state;
33	42	UINT8 m_bit;
	43
	44	devcb_write_line m_dataout_handler;
34	45	};
35	46
36	47	#endif

trunk/src/mame/machine/k573cass.c

r241484	r241485
7	7
8	8	#include "k573cass.h"
9	9
	10	// class konami573_cassette_interface
	11
	12	konami573_cassette_interface::konami573_cassette_interface(const machine_config &mconfig, device_t &device)
	13	: device_slot_card_interface(mconfig, device)
	14	{
	15	m_slot = dynamic_cast<konami573_cassette_slot_device *>(device.owner());
	16	}
	17
	18	konami573_cassette_interface::~konami573_cassette_interface()
	19	{
	20	}
	21
	22
	23
10	24	WRITE_LINE_MEMBER(konami573_cassette_interface::write_line_d0)
11	25	{
12	26	}
r241484	r241485
31	45	{
32	46	}
33	47
34		READ_LINE_MEMBER(konami573_cassette_interface::read_line_dsr)
35		{
36		return 1;
37		}
38
39	48	READ_LINE_MEMBER(konami573_cassette_interface::read_line_ds2401)
40	49	{
41	50	return 0;
r241484	r241485
56	65
57	66	konami573_cassette_x_device::konami573_cassette_x_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
58	67	device_t(mconfig, KONAMI573_CASSETTE_X, "Konami 573 Cassette X", tag, owner, clock, "k573cassx", __FILE__),
59		device_slot_card_interface(mconfig, *this),
	68	konami573_cassette_interface(mconfig, *this),
60	69	m_x76f041(*this, "eeprom")
61	70	{
62	71	}
63	72
64	73	konami573_cassette_x_device::konami573_cassette_x_device(const machine_config &mconfig, const device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source) :
65	74	device_t(mconfig, type, name, tag, owner, clock, shortname, __FILE__),
66		device_slot_card_interface(mconfig, *this),
	75	konami573_cassette_interface(mconfig, *this),
67	76	m_x76f041(*this, "eeprom")
68	77	{
69	78	}
r241484	r241485
79	88
80	89	void konami573_cassette_x_device::device_start()
81	90	{
	91	output_dsr(0);
82	92	}
83	93
84	94	WRITE_LINE_MEMBER(konami573_cassette_x_device::write_line_d0)
r241484	r241485
171	181
172	182	konami573_cassette_y_device::konami573_cassette_y_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
173	183	device_t(mconfig, KONAMI573_CASSETTE_Y, "Konami 573 Cassette Y", tag, owner, clock, "k573cassy", __FILE__),
174		device_slot_card_interface(mconfig, *this),
	184	konami573_cassette_interface(mconfig, *this),
175	185	m_x76f100(*this, "eeprom"),
176	186	m_d0_handler(*this),
177	187	m_d1_handler(*this),
r241484	r241485
186	196
187	197	konami573_cassette_y_device::konami573_cassette_y_device(const machine_config &mconfig, const device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source) :
188	198	device_t(mconfig, type, name, tag, owner, clock, shortname, __FILE__),
189		device_slot_card_interface(mconfig, *this),
	199	konami573_cassette_interface(mconfig, *this),
190	200	m_x76f100(*this, "eeprom"),
191	201	m_d0_handler(*this),
192	202	m_d1_handler(*this),
r241484	r241485
218	228	m_d5_handler.resolve_safe();
219	229	m_d6_handler.resolve_safe();
220	230	m_d7_handler.resolve_safe();
	231
	232	output_dsr(0);
221	233	}
222	234
223	235	READ_LINE_MEMBER(konami573_cassette_y_device::read_line_secflash_sda)
r241484	r241485
305	317
306	318	konami573_cassette_zi_device::konami573_cassette_zi_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
307	319	device_t(mconfig, KONAMI573_CASSETTE_ZI, "Konami 573 Cassette ZI", tag, owner, clock, "k573casszi", __FILE__),
308		device_slot_card_interface(mconfig, *this),
	320	konami573_cassette_interface(mconfig, *this),
309	321	m_zs01(*this,"eeprom"),
310	322	m_ds2401(*this, "id")
311	323	{
r241484	r241485
324	336
325	337	void konami573_cassette_zi_device::device_start()
326	338	{
	339	output_dsr(0);
327	340	}
328	341
329	342	WRITE_LINE_MEMBER(konami573_cassette_zi_device::write_line_d1)
r241484	r241485
362	375	}
363	376
364	377
365		const device_type KONAMI573_CASSETTE_SLOT_SERIAL = &device_creator<konami573_cassette_slot_serial_device>;
366
367		konami573_cassette_slot_serial_device::konami573_cassette_slot_serial_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
368		psxsiodev_device(mconfig, KONAMI573_CASSETTE_SLOT, "Konami 573 Cassette Slot (SERIAL)", tag, owner, clock, "k573cassslotserial", __FILE__)
369		{
370		}
371
372		void konami573_cassette_slot_serial_device::device_start()
373		{
374		psxsiodev_device::device_start();
375		}
376
377		void konami573_cassette_slot_serial_device::_data_out( int data, int mask )
378		{
379		data_out( data, mask );
380		}
381
382		void konami573_cassette_slot_serial_device::data_in( int data, int mask )
383		{
384		}
385
386
387	378	const device_type KONAMI573_CASSETTE_SLOT = &device_creator<konami573_cassette_slot_device>;
388	379
389	380	konami573_cassette_slot_device::konami573_cassette_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
390	381	device_t(mconfig, KONAMI573_CASSETTE_SLOT, "Konami 573 Cassette Slot", tag, owner, clock, "k573cassslot", __FILE__),
391	382	device_slot_interface(mconfig, *this),
392		m_serial(*this, ":maincpu:sio1:cassette") /// HACK: this shouldn't know where the actual slot is.
	383	m_dsr_handler(*this)
393	384	{
394	385	}
395	386
396	387	void konami573_cassette_slot_device::device_start()
397	388	{
398		m_cassette = dynamic_cast<konami573_cassette_interface *>(get_card_device());
	389	m_dsr_handler.resolve_safe();
399	390
400		if( m_cassette != NULL && m_cassette->read_line_dsr() )
401		{
402		m_serial->_data_out( PSX_SIO_IN_DSR, PSX_SIO_IN_DSR );
403		}
404		else
405		{
406		m_serial->_data_out( PSX_SIO_IN_DSR, 0 );
407		}
	391	m_dev = dynamic_cast<konami573_cassette_interface *>(get_card_device());
408	392	}
409	393
410	394	WRITE_LINE_MEMBER(konami573_cassette_slot_device::write_line_d0)
411	395	{
412		if( m_cassette )
	396	if( m_dev )
413	397	{
414		m_cassette->write_line_d0( state );
	398	m_dev->write_line_d0( state );
415	399	}
416	400	}
417	401
418	402	WRITE_LINE_MEMBER(konami573_cassette_slot_device::write_line_d1)
419	403	{
420		if( m_cassette )
	404	if( m_dev )
421	405	{
422		m_cassette->write_line_d1( state );
	406	m_dev->write_line_d1( state );
423	407	}
424	408	}
425	409
426	410	WRITE_LINE_MEMBER(konami573_cassette_slot_device::write_line_d2)
427	411	{
428		if( m_cassette )
	412	if( m_dev )
429	413	{
430		m_cassette->write_line_d2( state );
	414	m_dev->write_line_d2( state );
431	415	}
432	416	}
433	417
434	418	WRITE_LINE_MEMBER(konami573_cassette_slot_device::write_line_d3)
435	419	{
436		if( m_cassette )
	420	if( m_dev )
437	421	{
438		m_cassette->write_line_d3( state );
	422	m_dev->write_line_d3( state );
439	423	}
440	424	}
441	425
442	426	WRITE_LINE_MEMBER(konami573_cassette_slot_device::write_line_d4)
443	427	{
444		if( m_cassette )
	428	if( m_dev )
445	429	{
446		m_cassette->write_line_d4( state );
	430	m_dev->write_line_d4( state );
447	431	}
448	432	}
449	433
450	434	WRITE_LINE_MEMBER(konami573_cassette_slot_device::write_line_d5)
451	435	{
452		if( m_cassette )
	436	if( m_dev )
453	437	{
454		m_cassette->write_line_d5( state );
	438	m_dev->write_line_d5( state );
455	439	}
456	440	}
457	441
458	442	WRITE_LINE_MEMBER(konami573_cassette_slot_device::write_line_d6)
459	443	{
460		if( m_cassette )
	444	if( m_dev )
461	445	{
462		m_cassette->write_line_d6( state );
	446	m_dev->write_line_d6( state );
463	447	}
464	448	}
465	449
466	450	WRITE_LINE_MEMBER(konami573_cassette_slot_device::write_line_d7)
467	451	{
468		if( m_cassette )
	452	if( m_dev )
469	453	{
470		m_cassette->write_line_d7( state );
	454	m_dev->write_line_d7( state );
471	455	}
472	456	}
473	457
474	458	WRITE_LINE_MEMBER(konami573_cassette_slot_device::write_line_zs01_sda)
475	459	{
476		if( m_cassette )
	460	if( m_dev )
477	461	{
478		m_cassette->write_line_zs01_sda( state );
	462	m_dev->write_line_zs01_sda( state );
479	463	}
480	464	}
481	465
482	466	READ_LINE_MEMBER(konami573_cassette_slot_device::read_line_ds2401)
483	467	{
484		if( m_cassette )
	468	if( m_dev )
485	469	{
486		return m_cassette->read_line_ds2401();
	470	return m_dev->read_line_ds2401();
487	471	}
488	472
489	473	return 0;
r241484	r241485
491	475
492	476	READ_LINE_MEMBER(konami573_cassette_slot_device::read_line_secflash_sda)
493	477	{
494		if( m_cassette )
	478	if( m_dev )
495	479	{
496		return m_cassette->read_line_secflash_sda();
	480	return m_dev->read_line_secflash_sda();
497	481	}
498	482
499	483	return 0;
r241484	r241485
501	485
502	486	READ_LINE_MEMBER(konami573_cassette_slot_device::read_line_adc083x_do)
503	487	{
504		if( m_cassette )
	488	if( m_dev )
505	489	{
506		return m_cassette->read_line_adc083x_do();
	490	return m_dev->read_line_adc083x_do();
507	491	}
508	492
509	493	return 0;
r241484	r241485
511	495
512	496	READ_LINE_MEMBER(konami573_cassette_slot_device::read_line_adc083x_sars)
513	497	{
514		if( m_cassette )
	498	if( m_dev )
515	499	{
516		return m_cassette->read_line_adc083x_sars();
	500	return m_dev->read_line_adc083x_sars();
517	501	}
518	502
519	503	return 0;

trunk/src/mame/machine/k573cass.h

r241484	r241485
10	10	#ifndef __K573CASS_H__
11	11	#define __K573CASS_H__
12	12
13		#include "cpu/psx/siodev.h"
14	13	#include "machine/adc083x.h"
15	14	#include "machine/ds2401.h"
16	15	#include "machine/x76f041.h"
17	16	#include "machine/x76f100.h"
18	17	#include "machine/zs01.h"
19	18
20		class konami573_cassette_interface
	19	#define MCFG_KONAMI573_CASSETTE_DSR_HANDLER(_devcb) \
	20	devcb = &konami573_cassette_slot_device::set_dsr_handler(*device, DEVCB_##_devcb);
	21
	22
	23	extern const device_type KONAMI573_CASSETTE_SLOT;
	24
	25	class konami573_cassette_interface;
	26
	27	class konami573_cassette_slot_device : public device_t,
	28	public device_slot_interface
21	29	{
	30	friend class konami573_cassette_interface;
	31
22	32	public:
	33	konami573_cassette_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	34
	35	template<class _Object> static devcb_base &set_dsr_handler(device_t &device, _Object object) { return downcast<konami573_cassette_slot_device &>(device).m_dsr_handler.set_callback(object); }
	36
	37	DECLARE_WRITE_LINE_MEMBER(write_line_d0);
	38	DECLARE_WRITE_LINE_MEMBER(write_line_d1);
	39	DECLARE_WRITE_LINE_MEMBER(write_line_d2);
	40	DECLARE_WRITE_LINE_MEMBER(write_line_d3);
	41	DECLARE_WRITE_LINE_MEMBER(write_line_d4);
	42	DECLARE_WRITE_LINE_MEMBER(write_line_d5);
	43	DECLARE_WRITE_LINE_MEMBER(write_line_d6);
	44	DECLARE_WRITE_LINE_MEMBER(write_line_d7);
	45	DECLARE_WRITE_LINE_MEMBER(write_line_zs01_sda);
	46	DECLARE_READ_LINE_MEMBER(read_line_ds2401);
	47	DECLARE_READ_LINE_MEMBER(read_line_secflash_sda);
	48	DECLARE_READ_LINE_MEMBER(read_line_adc083x_do);
	49	DECLARE_READ_LINE_MEMBER(read_line_adc083x_sars);
	50
	51	protected:
	52	virtual void device_start();
	53
	54	devcb_write_line m_dsr_handler;
	55
	56	private:
	57	konami573_cassette_interface *m_dev;
	58	};
	59
	60	class konami573_cassette_interface : public device_slot_card_interface
	61	{
	62	friend class konami573_cassette_slot_device;
	63
	64	public:
	65	konami573_cassette_interface(const machine_config &mconfig, device_t &device);
	66	virtual ~konami573_cassette_interface();
	67
	68	DECLARE_WRITE_LINE_MEMBER(output_dsr) { m_slot->m_dsr_handler(state); }
	69
23	70	virtual DECLARE_WRITE_LINE_MEMBER(write_line_d0);
24	71	virtual DECLARE_WRITE_LINE_MEMBER(write_line_d1) = 0;
25	72	virtual DECLARE_WRITE_LINE_MEMBER(write_line_d2) = 0;
r241484	r241485
31	78	virtual DECLARE_WRITE_LINE_MEMBER(write_line_zs01_sda);
32	79	virtual DECLARE_READ_LINE_MEMBER(read_line_ds2401);
33	80	virtual DECLARE_READ_LINE_MEMBER(read_line_secflash_sda) = 0;
34		virtual DECLARE_READ_LINE_MEMBER(read_line_dsr);
35	81	virtual DECLARE_READ_LINE_MEMBER(read_line_adc083x_do);
36	82	virtual DECLARE_READ_LINE_MEMBER(read_line_adc083x_sars);
37	83
38		virtual ~konami573_cassette_interface() {}
	84	konami573_cassette_slot_device *m_slot;
39	85	};
40	86
41	87
42	88	extern const device_type KONAMI573_CASSETTE_X;
43	89
44	90	class konami573_cassette_x_device: public device_t,
45		public konami573_cassette_interface,
46		public device_slot_card_interface
	91	public konami573_cassette_interface
47	92	{
48	93	public:
49	94	konami573_cassette_x_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
r241484	r241485
119	164	devcb = &konami573_cassette_y_device::set_d7_handler(*device, DEVCB_##_devcb);
120	165
121	166	class konami573_cassette_y_device: public device_t,
122		public konami573_cassette_interface,
123		public device_slot_card_interface
	167	public konami573_cassette_interface
124	168	{
125	169	public:
126	170	konami573_cassette_y_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
r241484	r241485
184	228	extern const device_type KONAMI573_CASSETTE_ZI;
185	229
186	230	class konami573_cassette_zi_device: public device_t,
187		public konami573_cassette_interface,
188		public device_slot_card_interface
	231	public konami573_cassette_interface
189	232	{
190	233	public:
191	234	konami573_cassette_zi_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
r241484	r241485
208	251	};
209	252
210	253
211		extern const device_type KONAMI573_CASSETTE_SLOT_SERIAL;
212
213		class konami573_cassette_slot_serial_device : public psxsiodev_device
214		{
215		public:
216		konami573_cassette_slot_serial_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
217
218		void _data_out( int data, int mask );
219
220		protected:
221		virtual void device_start();
222
223		private:
224		virtual void data_in( int data, int mask );
225		};
226
227
228		extern const device_type KONAMI573_CASSETTE_SLOT;
229
230		class konami573_cassette_slot_device : public device_t,
231		public device_slot_interface
232		{
233		public:
234		konami573_cassette_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
235
236		DECLARE_WRITE_LINE_MEMBER(write_line_d0);
237		DECLARE_WRITE_LINE_MEMBER(write_line_d1);
238		DECLARE_WRITE_LINE_MEMBER(write_line_d2);
239		DECLARE_WRITE_LINE_MEMBER(write_line_d3);
240		DECLARE_WRITE_LINE_MEMBER(write_line_d4);
241		DECLARE_WRITE_LINE_MEMBER(write_line_d5);
242		DECLARE_WRITE_LINE_MEMBER(write_line_d6);
243		DECLARE_WRITE_LINE_MEMBER(write_line_d7);
244		DECLARE_WRITE_LINE_MEMBER(write_line_zs01_sda);
245		DECLARE_READ_LINE_MEMBER(read_line_ds2401);
246		DECLARE_READ_LINE_MEMBER(read_line_secflash_sda);
247		DECLARE_READ_LINE_MEMBER(read_line_adc083x_do);
248		DECLARE_READ_LINE_MEMBER(read_line_adc083x_sars);
249
250		protected:
251		virtual void device_start();
252
253		private:
254		required_device<konami573_cassette_slot_serial_device> m_serial;
255		konami573_cassette_interface *m_cassette;
256		};
257
258
259	254	#endif

trunk/src/mame/machine/zndip.c

r241484	r241485
5	5	const device_type ZNDIP = &device_creator<zndip_device>;
6	6
7	7	zndip_device::zndip_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
8		psxsiodev_device(mconfig, ZNDIP, "ZNDIP", tag, owner, clock, "zndip", __FILE__),
9		m_data_handler(*this)
	8	device_t(mconfig, ZNDIP, "ZNDIP", tag, owner, clock, "zndip", __FILE__),
	9	m_data_handler(*this),
	10	m_dataout_handler(*this),
	11	m_dsr_handler(*this)
10	12	{
11	13	}
12	14
13	15	void zndip_device::device_start()
14	16	{
15		psxsiodev_device::device_start();
16
17	17	m_data_handler.resolve_safe( 0 );
	18	m_dataout_handler.resolve_safe();
	19	m_dsr_handler.resolve_safe();
18	20
19	21	m_dip_timer = timer_alloc( 0 );
	22
	23	m_dataout_handler(1);
	24	m_dsr_handler(1);
20	25	}
21	26
22		void zndip_device::select(int select)
	27	WRITE_LINE_MEMBER(zndip_device::write_select)
23	28	{
24		if (m_select != select)
	29	if (!state && m_select)
25	30	{
26		if (!select)
27		{
28		m_bit = 0;
29		m_dip_timer->adjust( attotime::from_usec( 100 ), 1 );
30		}
31		else
32		{
33		data_out(0, PSX_SIO_IN_DATA | PSX_SIO_IN_DSR);
34		}
	31	m_bit = 0;
	32	m_dip_timer->adjust( attotime::from_usec( 100 ), 0 );
	33	}
	34	else
	35	{
	36	m_dataout_handler(1);
	37	m_dsr_handler(1);
	38	}
35	39
36		m_select = select;
37		}
	40	m_select = state;
38	41	}
39	42
40		void zndip_device::data_in( int data, int mask )
	43	WRITE_LINE_MEMBER(zndip_device::write_clock)
41	44	{
42		if( !m_select && ( mask & PSX_SIO_OUT_CLOCK ) != 0 && ( data & PSX_SIO_OUT_CLOCK ) == 0)
	45	if (!state && m_clock && !m_select)
43	46	{
44	47	int dip = m_data_handler();
45	48	int bit = ( ( dip >> m_bit ) & 1 );
46	49	//      verboselog( machine, 2, "read dip %02x -> %02x\n", n_data, bit * PSX_SIO_IN_DATA );
47		data_out( bit * PSX_SIO_IN_DATA, PSX_SIO_IN_DATA );
	50	m_dataout_handler(bit);
48	51	m_bit++;
49	52	m_bit &= 7;
50	53	}
	54
	55	m_clock = state;
51	56	}
52	57
53	58	void zndip_device::device_timer(emu_timer &timer, device_timer_id tid, int param, void *ptr)
54	59	{
55		data_out( param * PSX_SIO_IN_DSR, PSX_SIO_IN_DSR );
	60	m_dsr_handler(param);
56	61
57		if( param )
	62	if( !param )
58	63	{
59		m_dip_timer->adjust( attotime::from_usec( 50 ), 0 );
	64	m_dip_timer->adjust( attotime::from_usec( 50 ), 1 );
60	65	}
61	66	}

trunk/src/mame/machine/zndip.h

r241484	r241485
5	5	#ifndef __ZNDIP_H__
6	6	#define __ZNDIP_H__
7	7
8		#include "cpu/psx/siodev.h"
	8	#include "emu.h"
9	9
10	10	extern const device_type ZNDIP;
11	11
	12	#define MCFG_ZNDIP_DATAOUT_HANDLER(_devcb) \
	13	devcb = &zndip_device::set_dataout_handler(*device, DEVCB_##_devcb);
	14
	15	#define MCFG_ZNDIP_DSR_HANDLER(_devcb) \
	16	devcb = &zndip_device::set_dsr_handler(*device, DEVCB_##_devcb);
	17
12	18	#define MCFG_ZNDIP_DATA_HANDLER(_devcb) \
13	19	devcb = &zndip_device::set_data_handler(*device, DEVCB_##_devcb);
14		class zndip_device : public psxsiodev_device
	20
	21	class zndip_device : public device_t
15	22	{
16	23	public:
17	24	zndip_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
18	25
19	26	// static configuration helpers
20	27	template<class _Object> static devcb_base &set_data_handler(device_t &device, _Object object) { return downcast<zndip_device &>(device).m_data_handler.set_callback(object); }
	28	template<class _Object> static devcb_base &set_dataout_handler(device_t &device, _Object object) { return downcast<zndip_device &>(device).m_dataout_handler.set_callback(object); }
	29	template<class _Object> static devcb_base &set_dsr_handler(device_t &device, _Object object) { return downcast<zndip_device &>(device).m_dsr_handler.set_callback(object); }
21	30
22		void select(int select);
	31	WRITE_LINE_MEMBER(write_select);
	32	WRITE_LINE_MEMBER(write_clock);
23	33
24	34	protected:
25	35	virtual void device_start();
26	36	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
27	37
28	38	private:
29		virtual void data_in( int data, int mask );
30
31	39	devcb_read8 m_data_handler;
	40	devcb_write_line m_dataout_handler;
	41	devcb_write_line m_dsr_handler;
32	42
33	43	int m_select;
	44	int m_clock;
	45	int m_datain;
	46
34	47	UINT8 m_bit;
35	48	emu_timer *m_dip_timer;
36	49	};

trunk/src/mess/drivers/psx.c

r241484	r241485
493	493	MCFG_RAM_MODIFY("maincpu:ram")
494	494	MCFG_RAM_DEFAULT_SIZE("2M")
495	495
496		MCFG_DEVICE_ADD("maincpu:sio0:controllers", PSXCONTROLLERPORTS, 0)
	496	MCFG_DEVICE_ADD("controllers", PSXCONTROLLERPORTS, 0)
	497	MCFG_PSX_CONTROLLER_PORTS_RXD_HANDLER(DEVWRITELINE("maincpu:sio0", psxsio0_device, write_rxd))
	498	MCFG_PSX_CONTROLLER_PORTS_DSR_HANDLER(DEVWRITELINE("maincpu:sio0", psxsio0_device, write_dsr))
497	499	MCFG_PSX_CTRL_PORT_ADD("port1", psx_controllers, "digital_pad")
498	500	MCFG_PSX_CTRL_PORT_ADD("port2", psx_controllers, "digital_pad")
499	501
	502	MCFG_DEVICE_MODIFY("maincpu:sio0")
	503	MCFG_PSX_SIO_DTR_HANDLER(DEVWRITELINE("^controllers", psxcontrollerports_device, write_dtr))
	504	MCFG_PSX_SIO_SCK_HANDLER(DEVWRITELINE("^controllers", psxcontrollerports_device, write_sck))
	505	MCFG_PSX_SIO_TXD_HANDLER(DEVWRITELINE("^controllers", psxcontrollerports_device, write_txd))
	506
500	507	/* video hardware */
501	508	MCFG_PSXGPU_ADD( "maincpu", "gpu", CXD8561Q, 0x100000, XTAL_53_693175MHz )
502	509
r241484	r241485
534	541	MCFG_RAM_MODIFY("maincpu:ram")
535	542	MCFG_RAM_DEFAULT_SIZE("2M")
536	543
537		MCFG_DEVICE_ADD("maincpu:sio0:controllers", PSXCONTROLLERPORTS, 0)
	544	MCFG_DEVICE_ADD("controllers", PSXCONTROLLERPORTS, 0)
	545	MCFG_PSX_CONTROLLER_PORTS_RXD_HANDLER(DEVWRITELINE("maincpu:sio0", psxsio0_device, write_rxd))
	546	MCFG_PSX_CONTROLLER_PORTS_DSR_HANDLER(DEVWRITELINE("maincpu:sio0", psxsio0_device, write_dsr))
538	547	MCFG_PSX_CTRL_PORT_ADD("port1", psx_controllers, "digital_pad")
539	548	MCFG_PSX_CTRL_PORT_ADD("port2", psx_controllers, "digital_pad")
540	549
	550	MCFG_DEVICE_MODIFY("maincpu:sio0")
	551	MCFG_PSX_SIO_DTR_HANDLER(DEVWRITELINE("^controllers", psxcontrollerports_device, write_dtr))
	552	MCFG_PSX_SIO_SCK_HANDLER(DEVWRITELINE("^controllers", psxcontrollerports_device, write_sck))
	553	MCFG_PSX_SIO_TXD_HANDLER(DEVWRITELINE("^controllers", psxcontrollerports_device, write_txd))
	554
541	555	/* video hardware */
542	556	/* TODO: visible area and refresh rate */
543	557	MCFG_PSXGPU_ADD( "maincpu", "gpu", CXD8561Q, 0x100000, XTAL_53_693175MHz )

https://github.com/mamedev/mame/commit/7e7b1dc0bb5b9c2acd27fa353dce57e1a985adc9

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