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r32938 Saturday 25th October, 2014 at 06:31:27 UTC by Osso
ppc: converted remaining callbacks to delegates (nw)

[src/emu/cpu/powerpc]	ppc.h ppccom.c
[src/mame/drivers]	cobra.c firebeat.c hornet.c

trunk/src/emu/cpu/powerpc/ppc.h

r241449	r241450
159	159	#define PPCDRC_COMPATIBLE_OPTIONS   (PPCDRC_STRICT_VERIFY | PPCDRC_FLUSH_PC | PPCDRC_ACCURATE_SINGLES)
160	160	#define PPCDRC_FASTEST_OPTIONS      (0)
161	161
162
163
164		/***************************************************************************
165		STRUCTURES AND TYPEDEFS
166		***************************************************************************/
167
168		typedef void (*ppc4xx_spu_tx_handler)(device_t *device, UINT8 data);
169
170
171		typedef void (*ppc_dcstore_handler)(device_t *device, UINT32 address);
172		typedef UINT32 (*ppc4xx_dma_read_handler)(device_t *device, int width);
173		typedef void (*ppc4xx_dma_write_handler)(device_t *device, int width, UINT32 data);
174
175
176		/***************************************************************************
177		PUBLIC FUNCTIONS
178		***************************************************************************/
179
	162
	163
	164	/***************************************************************************
	165	PUBLIC FUNCTIONS
	166	***************************************************************************/
	167
180	168	#define MCFG_PPC_BUS_FREQUENCY(_frequency) \
181	169	ppc_device::set_bus_frequency(*device, _frequency);
182	170
r241449	r241450
225	213	public:
226	214	// construction/destruction
227	215	ppc_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, int address_bits, int data_bits, powerpc_flavor flavor, UINT32 cap, UINT32 tb_divisor, address_map_constructor internal_map);
	216
	217	static void set_bus_frequency(device_t &device, UINT32 bus_frequency) { downcast<ppc_device &>(device).c_bus_frequency = bus_frequency; }
	218
	219	void ppc_set_dcstore_callback(write32_delegate callback);
	220
	221	void ppcdrc_set_options(UINT32 options);
	222	void ppcdrc_add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base);
	223	void ppcdrc_add_hotspot(offs_t pc, UINT32 opcode, UINT32 cycles);
228	224
229		static void set_bus_frequency(device_t &device, UINT32 bus_frequency) { downcast<ppc_device &>(device).c_bus_frequency = bus_frequency; }
230
231		void ppc_set_dcstore_callback(ppc_dcstore_handler handler);
232
233		void ppcdrc_set_options(UINT32 options);
234		void ppcdrc_add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base);
235		void ppcdrc_add_hotspot(offs_t pc, UINT32 opcode, UINT32 cycles);
236
237	225	TIMER_CALLBACK_MEMBER(decrementer_int_callback);
238	226	TIMER_CALLBACK_MEMBER(ppc4xx_buffered_dma_callback);
239	227	TIMER_CALLBACK_MEMBER(ppc4xx_fit_callback);
r241449	r241450
491	479	UINT8           regs[9];
492	480	UINT8           txbuf;
493	481	UINT8           rxbuf;
494		emu_timer *     timer;
495		UINT8           rxbuffer[256];
496		UINT32          rxin, rxout;
497		ppc4xx_spu_tx_handler tx_handler;
498		};
499
500		ppc4xx_spu_state m_spu;
	482	emu_timer *     timer;
	483	UINT8           rxbuffer[256];
	484	UINT32          rxin, rxout;
	485	write8_delegate tx_cb;
	486	};
	487
	488	ppc4xx_spu_state m_spu;
501	489	emu_timer *     m_fit_timer;
502	490	emu_timer *     m_pit_timer;
503	491	emu_timer *     m_wdog_timer;
r241449	r241450
515	503	UINT64          m_dec_zero_cycles;
516	504	emu_timer *     m_decrementer_int_timer;
517	505
518		read32_delegate  m_dcr_read_func;
519		write32_delegate m_dcr_write_func;
520
521		ppc_dcstore_handler m_dcstore_handler;
522
523		ppc4xx_dma_read_handler m_ext_dma_read_handler[4];
524		ppc4xx_dma_write_handler m_ext_dma_write_handler[4];
525
526		/* PowerPC function pointers for memory accesses/exceptions */
527		jmp_buf m_exception_jmpbuf;
	506	read32_delegate  m_dcr_read_func;
	507	write32_delegate m_dcr_write_func;
	508
	509	write32_delegate m_dcstore_cb;
	510
	511	read32_delegate m_ext_dma_read_cb[4];
	512	write32_delegate m_ext_dma_write_cb[4];
	513
	514	/* PowerPC function pointers for memory accesses/exceptions */
	515	jmp_buf m_exception_jmpbuf;
528	516	UINT8 (*m_ppcread8)(address_space &space, offs_t address);
529	517	UINT16 (*m_ppcread16)(address_space &space, offs_t address);
530	518	UINT32 (*m_ppcread32)(address_space &space, offs_t address);
r241449	r241450
763	751
764	752	class ppc4xx_device : public ppc_device
765	753	{
766		public:
767		ppc4xx_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, powerpc_flavor flavor, UINT32 cap, UINT32 tb_divisor);
768
769		void ppc4xx_spu_set_tx_handler(ppc4xx_spu_tx_handler handler);
770		void ppc4xx_spu_receive_byte(UINT8 byteval);
771
772		void ppc4xx_set_dma_read_handler(int channel, ppc4xx_dma_read_handler handler, int rate);
773		void ppc4xx_set_dma_write_handler(int channel, ppc4xx_dma_write_handler handler, int rate);
774		void ppc4xx_set_dcr_read_handler(read32_delegate dcr_read_func);
775		void ppc4xx_set_dcr_write_handler(write32_delegate dcr_write_func);
776
	754	public:
	755	ppc4xx_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, powerpc_flavor flavor, UINT32 cap, UINT32 tb_divisor);
	756
	757	void ppc4xx_spu_set_tx_handler(write8_delegate callback);
	758	void ppc4xx_spu_receive_byte(UINT8 byteval);
	759
	760	void ppc4xx_set_dma_read_handler(int channel, read32_delegate callback, int rate);
	761	void ppc4xx_set_dma_write_handler(int channel, write32_delegate callback, int rate);
	762	void ppc4xx_set_dcr_read_handler(read32_delegate dcr_read_func);
	763	void ppc4xx_set_dcr_write_handler(write32_delegate dcr_write_func);
	764
777	765	DECLARE_READ8_MEMBER( ppc4xx_spu_r );
778	766	DECLARE_WRITE8_MEMBER( ppc4xx_spu_w );
779	767

trunk/src/emu/cpu/powerpc/ppccom.c

r241449	r241450
214	214	, m_core(NULL)
215	215	, m_bus_freq_multiplier(1)
216	216	, m_vtlb(NULL)
217		, m_flavor(flavor)
218		, m_cap(cap)
219		, m_tb_divisor(tb_divisor)
220		, m_dcstore_handler(NULL)
221		, m_cache(CACHE_SIZE + sizeof(internal_ppc_state))
222		, m_drcuml(NULL)
223		, m_drcfe(NULL)
	217	, m_flavor(flavor)
	218	, m_cap(cap)
	219	, m_tb_divisor(tb_divisor)
	220	, m_cache(CACHE_SIZE + sizeof(internal_ppc_state))
	221	, m_drcuml(NULL)
	222	, m_drcfe(NULL)
224	223	, m_drcoptions(0)
225		{
226		m_program_config.m_logaddr_width = 32;
227		m_program_config.m_page_shift = POWERPC_MIN_PAGE_SHIFT;
228		memset(m_ext_dma_read_handler, 0, sizeof(m_ext_dma_read_handler));
229		memset(m_ext_dma_write_handler, 0, sizeof(m_ext_dma_write_handler));
230		}
231
232		//ppc403_device::ppc403_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	224	{
	225	m_program_config.m_logaddr_width = 32;
	226	m_program_config.m_page_shift = POWERPC_MIN_PAGE_SHIFT;
	227	}
	228
	229	//ppc403_device::ppc403_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
233	230	//  : ppc_device(mconfig, PPC403, "PPC403", tag, owner, clock, "ppc403", 32?, 64?)
234	231	//{
235	232	//}
r241449	r241450
1241	1238	ppccom_dcstore_callback - call the dcstore
1242	1239	callback if installed
1243	1240	-------------------------------------------------*/
	1241
	1242	void ppc_device::ppccom_dcstore_callback()
	1243	{
	1244	if (!m_dcstore_cb.isnull())
	1245	{
	1246	m_dcstore_cb(*m_program, m_core->param0, 0, 0xffffffff);
	1247	}
	1248	}
	1249
1244	1250
1245		void ppc_device::ppccom_dcstore_callback()
1246		{
1247		if (m_dcstore_handler != NULL)
1248		{
1249		m_dcstore_handler(this, m_core->param0);
1250		}
1251		}
1252
1253
1254	1251	/***************************************************************************
1255	1252	TLB HANDLING
1256	1253	***************************************************************************/
r241449	r241450
2061	2058
2062	2059	/*-------------------------------------------------
2063	2060	ppc_set_dcstore_callback - installs a callback
2064		for detecting datacache stores with dcbst
2065		-------------------------------------------------*/
2066
2067		void ppc_device::ppc_set_dcstore_callback(ppc_dcstore_handler handler)
2068		{
2069		m_dcstore_handler = handler;
2070		}
2071
2072
	2061	for detecting datacache stores with dcbst
	2062	-------------------------------------------------*/
	2063
	2064	void ppc_device::ppc_set_dcstore_callback(write32_delegate callback)
	2065	{
	2066	m_dcstore_cb = callback;
	2067	}
	2068
	2069
2073	2070	void ppc_device::execute_set_input(int inputnum, int state)
2074	2071	{
2075	2072	switch (inputnum)
r241449	r241450
2288	2285	{
2289	2286	/* byte transfer */
2290	2287	case 1:
2291		do
2292		{
2293		UINT8 data = 0;
2294		if (m_ext_dma_read_handler[dmachan] != NULL)
2295		data = (*m_ext_dma_read_handler[dmachan])(this, 1);
2296		m_program->write_byte(dmaregs[DCR4XX_DMADA0], data);
2297		dmaregs[DCR4XX_DMADA0] += destinc;
2298		} while (!ppc4xx_dma_decrement_count(dmachan));
	2288	do
	2289	{
	2290	UINT8 data = 0;
	2291	if (!m_ext_dma_read_cb[dmachan].isnull())
	2292	data = (m_ext_dma_read_cb[dmachan])(*m_program, 1, 0xffffffff);
	2293	m_program->write_byte(dmaregs[DCR4XX_DMADA0], data);
	2294	dmaregs[DCR4XX_DMADA0] += destinc;
	2295	} while (!ppc4xx_dma_decrement_count(dmachan));
2299	2296	break;
2300	2297
2301	2298	/* word transfer */
2302	2299	case 2:
2303		do
2304		{
2305		UINT16 data = 0;
2306		if (m_ext_dma_read_handler[dmachan] != NULL)
2307		data = (*m_ext_dma_read_handler[dmachan])(this, 2);
2308		m_program->write_word(dmaregs[DCR4XX_DMADA0], data);
2309		dmaregs[DCR4XX_DMADA0] += destinc;
2310		} while (!ppc4xx_dma_decrement_count(dmachan));
	2300	do
	2301	{
	2302	UINT16 data = 0;
	2303	if (!m_ext_dma_read_cb[dmachan].isnull())
	2304	data = (m_ext_dma_read_cb[dmachan])(*m_program, 2, 0xffffffff);
	2305	m_program->write_word(dmaregs[DCR4XX_DMADA0], data);
	2306	dmaregs[DCR4XX_DMADA0] += destinc;
	2307	} while (!ppc4xx_dma_decrement_count(dmachan));
2311	2308	break;
2312	2309
2313	2310	/* dword transfer */
2314	2311	case 4:
2315		do
2316		{
2317		UINT32 data = 0;
2318		if (m_ext_dma_read_handler[dmachan] != NULL)
2319		data = (*m_ext_dma_read_handler[dmachan])(this, 4);
2320		m_program->write_dword(dmaregs[DCR4XX_DMADA0], data);
2321		dmaregs[DCR4XX_DMADA0] += destinc;
2322		} while (!ppc4xx_dma_decrement_count(dmachan));
	2312	do
	2313	{
	2314	UINT32 data = 0;
	2315	if (!m_ext_dma_read_cb[dmachan].isnull())
	2316	data = (m_ext_dma_read_cb[dmachan])(*m_program, 4, 0xffffffff);
	2317	m_program->write_dword(dmaregs[DCR4XX_DMADA0], data);
	2318	dmaregs[DCR4XX_DMADA0] += destinc;
	2319	} while (!ppc4xx_dma_decrement_count(dmachan));
2323	2320	break;
2324	2321	}
2325	2322	}
r241449	r241450
2332	2329	{
2333	2330	/* byte transfer */
2334	2331	case 1:
2335		do
2336		{
2337		UINT8 data = m_program->read_byte(dmaregs[DCR4XX_DMADA0]);
2338		if (m_ext_dma_write_handler[dmachan] != NULL)
2339		(*m_ext_dma_write_handler[dmachan])(this, 1, data);
2340		dmaregs[DCR4XX_DMADA0] += destinc;
2341		} while (!ppc4xx_dma_decrement_count(dmachan));
2342		break;
	2332	do
	2333	{
	2334	UINT8 data = m_program->read_byte(dmaregs[DCR4XX_DMADA0]);
	2335	if (!m_ext_dma_write_cb[dmachan].isnull())
	2336	(m_ext_dma_write_cb[dmachan])(*m_program, 1, data, 0xffffffff);
	2337	dmaregs[DCR4XX_DMADA0] += destinc;
	2338	} while (!ppc4xx_dma_decrement_count(dmachan));
	2339	break;
2343	2340
2344	2341	/* word transfer */
2345	2342	case 2:
2346		do
2347		{
2348		UINT16 data = m_program->read_word(dmaregs[DCR4XX_DMADA0]);
2349		if (m_ext_dma_write_handler[dmachan] != NULL)
2350		(*m_ext_dma_write_handler[dmachan])(this, 2, data);
2351		dmaregs[DCR4XX_DMADA0] += destinc;
2352		} while (!ppc4xx_dma_decrement_count(dmachan));
2353		break;
	2343	do
	2344	{
	2345	UINT16 data = m_program->read_word(dmaregs[DCR4XX_DMADA0]);
	2346	if (!m_ext_dma_write_cb[dmachan].isnull())
	2347	(m_ext_dma_write_cb[dmachan])(*m_program, 2, data, 0xffffffff);
	2348	dmaregs[DCR4XX_DMADA0] += destinc;
	2349	} while (!ppc4xx_dma_decrement_count(dmachan));
	2350	break;
2354	2351
2355	2352	/* dword transfer */
2356	2353	case 4:
2357		do
2358		{
2359		UINT32 data = m_program->read_dword(dmaregs[DCR4XX_DMADA0]);
2360		if (m_ext_dma_write_handler[dmachan] != NULL)
2361		(*m_ext_dma_write_handler[dmachan])(this, 4, data);
2362		dmaregs[DCR4XX_DMADA0] += destinc;
2363		} while (!ppc4xx_dma_decrement_count(dmachan));
2364		break;
	2354	do
	2355	{
	2356	UINT32 data = m_program->read_dword(dmaregs[DCR4XX_DMADA0]);
	2357	if (!m_ext_dma_write_cb[dmachan].isnull())
	2358	(m_ext_dma_write_cb[dmachan])(*m_program, 4, data, 0xffffffff);
	2359	dmaregs[DCR4XX_DMADA0] += destinc;
	2360	} while (!ppc4xx_dma_decrement_count(dmachan));
	2361	break;
2365	2362	}
2366	2363	}
2367	2364	}
r241449	r241450
2677	2674	int operation = (m_spu.regs[SPU4XX_TX_COMMAND] >> 5) & 3;
2678	2675
2679	2676	/* if we have data to transmit, do it now */
2680		if (!(m_spu.regs[SPU4XX_LINE_STATUS] & 0x04))
2681		{
2682		/* if we have a transmit handler, send it that way */
2683		if (m_spu.tx_handler != NULL)
2684		(*m_spu.tx_handler)(this, m_spu.txbuf);
2685
2686		/* indicate that we have moved it to the shift register */
2687		m_spu.regs[SPU4XX_LINE_STATUS] |= 0x04;
	2677	if (!(m_spu.regs[SPU4XX_LINE_STATUS] & 0x04))
	2678	{
	2679	/* if we have a transmit handler, send it that way */
	2680	if (!m_spu.tx_cb.isnull())
	2681	(m_spu.tx_cb)(*m_program, 0, m_spu.txbuf, 0xff);
	2682
	2683	/* indicate that we have moved it to the shift register */
	2684	m_spu.regs[SPU4XX_LINE_STATUS] |= 0x04;
2688	2685	m_spu.regs[SPU4XX_LINE_STATUS] &= ~0x02;
2689	2686	}
2690	2687
r241449	r241450
2823	2820
2824	2821	/*-------------------------------------------------
2825	2822	ppc4xx_spu_set_tx_handler - PowerPC 4XX-
2826		specific TX handler configuration
2827		-------------------------------------------------*/
2828
2829		void ppc4xx_device::ppc4xx_spu_set_tx_handler(ppc4xx_spu_tx_handler handler)
2830		{
2831		m_spu.tx_handler = handler;
2832		}
2833
2834
	2823	specific TX handler configuration
	2824	-------------------------------------------------*/
	2825
	2826	void ppc4xx_device::ppc4xx_spu_set_tx_handler(write8_delegate callback)
	2827	{
	2828	m_spu.tx_cb = callback;
	2829	}
	2830
	2831
2835	2832	/*-------------------------------------------------
2836	2833	ppc4xx_spu_receive_byte - PowerPC 4XX-
2837	2834	specific serial byte receive
r241449	r241450
2844	2841
2845	2842	/*-------------------------------------------------
2846	2843	ppc4xx_set_dma_read_handler - PowerPC 4XX-
2847		specific external DMA read handler configuration
2848		-------------------------------------------------*/
2849
2850		void ppc4xx_device::ppc4xx_set_dma_read_handler(int channel, ppc4xx_dma_read_handler handler, int rate)
2851		{
2852		m_ext_dma_read_handler[channel] = handler;
2853		m_buffered_dma_rate[channel] = rate;
2854		}
2855
	2844	specific external DMA read handler configuration
	2845	-------------------------------------------------*/
	2846
	2847	void ppc4xx_device::ppc4xx_set_dma_read_handler(int channel, read32_delegate callback, int rate)
	2848	{
	2849	m_ext_dma_read_cb[channel] = callback;
	2850	m_buffered_dma_rate[channel] = rate;
	2851	}
	2852
2856	2853	/*-------------------------------------------------
2857	2854	ppc4xx_set_dma_write_handler - PowerPC 4XX-
2858		specific external DMA write handler configuration
2859		-------------------------------------------------*/
2860
2861		void ppc4xx_device::ppc4xx_set_dma_write_handler(int channel, ppc4xx_dma_write_handler handler, int rate)
2862		{
2863		m_ext_dma_write_handler[channel] = handler;
2864		m_buffered_dma_rate[channel] = rate;
2865		}
2866
	2855	specific external DMA write handler configuration
	2856	-------------------------------------------------*/
	2857
	2858	void ppc4xx_device::ppc4xx_set_dma_write_handler(int channel, write32_delegate callback, int rate)
	2859	{
	2860	m_ext_dma_write_cb[channel] = callback;
	2861	m_buffered_dma_rate[channel] = rate;
	2862	}
	2863
2867	2864	/*-------------------------------------------------
2868	2865	ppc4xx_set_dcr_read_handler
2869	2866	-------------------------------------------------*/

trunk/src/mame/drivers/cobra.c

r241449	r241450
630	630	DECLARE_READ64_MEMBER(main_comram_r);
631	631	DECLARE_WRITE64_MEMBER(main_comram_w);
632	632	DECLARE_READ64_MEMBER(main_fifo_r);
633		DECLARE_WRITE64_MEMBER(main_fifo_w);
634		DECLARE_READ64_MEMBER(main_mpc106_r);
635		DECLARE_WRITE64_MEMBER(main_mpc106_w);
636
637		DECLARE_READ32_MEMBER(sub_comram_r);
638		DECLARE_WRITE32_MEMBER(sub_comram_w);
639		DECLARE_READ32_MEMBER(sub_sound_r);
	633	DECLARE_WRITE64_MEMBER(main_fifo_w);
	634	DECLARE_READ64_MEMBER(main_mpc106_r);
	635	DECLARE_WRITE64_MEMBER(main_mpc106_w);
	636	DECLARE_WRITE32_MEMBER(main_cpu_dc_store);
	637
	638	DECLARE_READ32_MEMBER(sub_comram_r);
	639	DECLARE_WRITE32_MEMBER(sub_comram_w);
	640	DECLARE_READ32_MEMBER(sub_sound_r);
640	641	DECLARE_WRITE32_MEMBER(sub_sound_w);
641	642	DECLARE_READ32_MEMBER(sub_unk7e_r);
642	643	DECLARE_WRITE32_MEMBER(sub_debug_w);
r241449	r241450
650	651	DECLARE_WRITE16_MEMBER(sub_ata0_w);
651	652	DECLARE_READ16_MEMBER(sub_ata1_r);
652	653	DECLARE_WRITE16_MEMBER(sub_ata1_w);
653		DECLARE_READ32_MEMBER(sub_psac2_r);
654		DECLARE_WRITE32_MEMBER(sub_psac2_w);
655		DECLARE_WRITE32_MEMBER(sub_psac_palette_w);
656
657		DECLARE_WRITE64_MEMBER(gfx_fifo0_w);
658		DECLARE_WRITE64_MEMBER(gfx_fifo1_w);
	654	DECLARE_READ32_MEMBER(sub_psac2_r);
	655	DECLARE_WRITE32_MEMBER(sub_psac2_w);
	656	DECLARE_WRITE32_MEMBER(sub_psac_palette_w);
	657	DECLARE_WRITE32_MEMBER(sub_sound_dma_w);
	658
	659	DECLARE_WRITE64_MEMBER(gfx_fifo0_w);
	660	DECLARE_WRITE64_MEMBER(gfx_fifo1_w);
659	661	DECLARE_WRITE64_MEMBER(gfx_fifo2_w);
660	662	DECLARE_WRITE64_MEMBER(gfx_debug_state_w);
661	663	DECLARE_READ64_MEMBER(gfx_unk1_r);
662		DECLARE_WRITE64_MEMBER(gfx_unk1_w);
663		DECLARE_READ64_MEMBER(gfx_fifo_r);
664		DECLARE_WRITE64_MEMBER(gfx_buf_w);
665
666		DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
667
	664	DECLARE_WRITE64_MEMBER(gfx_unk1_w);
	665	DECLARE_READ64_MEMBER(gfx_fifo_r);
	666	DECLARE_WRITE64_MEMBER(gfx_buf_w);
	667	DECLARE_WRITE32_MEMBER(gfx_cpu_dc_store);
	668
	669	DECLARE_WRITE8_MEMBER(sub_jvs_w);
	670
	671	DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
	672
668	673	cobra_renderer *m_renderer;
669	674
670	675	cobra_fifo *m_gfxfifo_in;
r241449	r241450
1596	1601	UINT32 m2 = (UINT32)(mem_mask);
1597	1602
1598	1603	m_comram[page][(offset << 1) + 0] = (w1 & ~m1) | (d1 & m1);
1599		m_comram[page][(offset << 1) + 1] = (w2 & ~m2) | (d2 & m2);
1600		}
1601
1602		static void main_cpu_dc_store(device_t *device, UINT32 address)
1603		{
1604		cobra_state *cobra = device->machine().driver_data<cobra_state>();
1605
1606		if ((address & 0xf0000000) == 0xc0000000)
1607		{
1608		// force sync when writing to GFX board main ram
1609		cobra->m_maincpu->spin_until_time(attotime::from_usec(80));
1610		}
1611		}
1612
	1604	m_comram[page][(offset << 1) + 1] = (w2 & ~m2) | (d2 & m2);
	1605	}
	1606
	1607	WRITE32_MEMBER(cobra_state::main_cpu_dc_store)
	1608	{
	1609	if ((offset & 0xf0000000) == 0xc0000000)
	1610	{
	1611	// force sync when writing to GFX board main ram
	1612	m_maincpu->spin_until_time(attotime::from_usec(80));
	1613	}
	1614	}
	1615
1613	1616	static ADDRESS_MAP_START( cobra_main_map, AS_PROGRAM, 64, cobra_state )
1614	1617	AM_RANGE(0x00000000, 0x003fffff) AM_RAM
1615	1618	AM_RANGE(0x07c00000, 0x07ffffff) AM_RAM
r241449	r241450
1885	1888	}
1886	1889
1887	1890	WRITE32_MEMBER(cobra_state::sub_psac2_w)
1888		{
1889		}
1890
1891		static void sub_sound_dma_w(device_t *device, int width, UINT32 data)
1892		{
1893		//printf("DMA write to unknown: size %d, data %08X\n", width, data);
1894
1895		/*
1896		static FILE *out;
	1891	{
	1892	}
	1893
	1894	WRITE32_MEMBER(cobra_state::sub_sound_dma_w)
	1895	{
	1896	//printf("DMA write to unknown: size %d, data %08X\n", address, data);
	1897
	1898	/*
	1899	static FILE *out;
1897	1900	if (out == NULL)
1898	1901	out = fopen("sound.bin", "wb");
1899	1902
1900	1903	fputc((data >> 24) & 0xff, out);
1901	1904	fputc((data >> 16) & 0xff, out);
1902	1905	fputc((data >> 8) & 0xff, out);
1903		fputc((data >> 0) & 0xff, out);
1904		*/
1905
1906		cobra_state *cobra = device->machine().driver_data<cobra_state>();
1907
1908		INT16 ldata = (INT16)(data >> 16);
1909		INT16 rdata = (INT16)(data);
1910
1911		cobra->m_sound_dma_buffer_l[cobra->m_sound_dma_ptr] = ldata;
1912		cobra->m_sound_dma_buffer_r[cobra->m_sound_dma_ptr] = rdata;
1913		cobra->m_sound_dma_ptr++;
1914
1915		if (cobra->m_sound_dma_ptr >= DMA_SOUND_BUFFER_SIZE)
1916		{
1917		cobra->m_sound_dma_ptr = 0;
1918
1919		dmadac_transfer(&cobra->m_dmadac[0], 1, 0, 1, DMA_SOUND_BUFFER_SIZE, cobra->m_sound_dma_buffer_l);
1920		dmadac_transfer(&cobra->m_dmadac[1], 1, 0, 1, DMA_SOUND_BUFFER_SIZE, cobra->m_sound_dma_buffer_r);
1921		}
1922		}
1923
1924		static void sub_jvs_w(device_t *device, UINT8 data)
1925		{
1926		cobra_state *cobra = device->machine().driver_data<cobra_state>();
1927		cobra_jvs_host *jvs = downcast<cobra_jvs_host *>(device->machine().device("cobra_jvs_host"));
1928
1929		#if LOG_JVS
1930		printf("sub_jvs_w: %02X\n", data);
	1906	fputc((data >> 0) & 0xff, out);
	1907	*/
	1908
	1909	INT16 ldata = (INT16)(data >> 16);
	1910	INT16 rdata = (INT16)(data);
	1911
	1912	m_sound_dma_buffer_l[m_sound_dma_ptr] = ldata;
	1913	m_sound_dma_buffer_r[m_sound_dma_ptr] = rdata;
	1914	m_sound_dma_ptr++;
	1915
	1916	if (m_sound_dma_ptr >= DMA_SOUND_BUFFER_SIZE)
	1917	{
	1918	m_sound_dma_ptr = 0;
	1919
	1920	dmadac_transfer(&m_dmadac[0], 1, 0, 1, DMA_SOUND_BUFFER_SIZE, m_sound_dma_buffer_l);
	1921	dmadac_transfer(&m_dmadac[1], 1, 0, 1, DMA_SOUND_BUFFER_SIZE, m_sound_dma_buffer_r);
	1922	}
	1923	}
	1924
	1925	WRITE8_MEMBER(cobra_state::sub_jvs_w)
	1926	{
	1927	cobra_jvs_host *jvs = machine().device<cobra_jvs_host>("cobra_jvs_host");
	1928
	1929	#if LOG_JVS
	1930	printf("sub_jvs_w: %02X\n", data);
1931	1931	#endif
1932	1932
1933	1933	const UINT8 *rec_data;
r241449	r241450
1945	1945	}
1946	1946	printf("\n");
1947	1947	#endif
	1948
	1949	for (int i=0; i < rec_size; i++)
	1950	{
	1951	m_subcpu->ppc4xx_spu_receive_byte(rec_data[i]);
	1952	}
	1953	}
	1954	}
1948	1955
1949		for (int i=0; i < rec_size; i++)
1950		{
1951		cobra->m_subcpu->ppc4xx_spu_receive_byte(rec_data[i]);
1952		}
1953		}
1954		}
1955
1956	1956	static ADDRESS_MAP_START( cobra_sub_map, AS_PROGRAM, 32, cobra_state )
1957	1957	AM_RANGE(0x00000000, 0x003fffff) AM_MIRROR(0x80000000) AM_RAM                                           // Main RAM
1958	1958	AM_RANGE(0x70000000, 0x7003ffff) AM_MIRROR(0x80000000) AM_READWRITE(sub_comram_r, sub_comram_w)         // Double buffered shared RAM between Main and Sub
r241449	r241450
2988	2988	// prc_read always expects a value...
2989	2989
2990	2990	m_gfxfifo_out->push(&space.device(), 0);
2991		}
2992		}
2993
2994		static void gfx_cpu_dc_store(device_t *device, UINT32 address)
2995		{
2996		cobra_state *cobra = device->machine().driver_data<cobra_state>();
2997
2998		UINT32 addr = address >> 24;
2999		if (addr == 0x10 || addr == 0x18 || addr == 0x1e)
3000		{
3001		UINT64 i = (UINT64)(cobra->m_gfx_fifo_cache_addr) << 32;
3002		cobra_fifo *fifo_in = cobra->m_gfxfifo_in;
3003
3004		UINT32 a = (address / 8) & 0xff;
3005
3006		fifo_in->push(device, (UINT32)(cobra->m_gfx_fifo_mem[a+0] >> 32) | i);
3007		fifo_in->push(device, (UINT32)(cobra->m_gfx_fifo_mem[a+0] >>  0) | i);
3008		fifo_in->push(device, (UINT32)(cobra->m_gfx_fifo_mem[a+1] >> 32) | i);
3009		fifo_in->push(device, (UINT32)(cobra->m_gfx_fifo_mem[a+1] >>  0) | i);
3010		fifo_in->push(device, (UINT32)(cobra->m_gfx_fifo_mem[a+2] >> 32) | i);
3011		fifo_in->push(device, (UINT32)(cobra->m_gfx_fifo_mem[a+2] >>  0) | i);
3012		fifo_in->push(device, (UINT32)(cobra->m_gfx_fifo_mem[a+3] >> 32) | i);
3013		fifo_in->push(device, (UINT32)(cobra->m_gfx_fifo_mem[a+3] >>  0) | i);
3014
3015		cobra->m_renderer->gfx_fifo_exec();
3016		}
3017		else
3018		{
3019		logerror("gfx: data cache store at %08X\n", address);
3020		}
3021		}
3022
	2991	}
	2992	}
	2993
	2994	WRITE32_MEMBER(cobra_state::gfx_cpu_dc_store)
	2995	{
	2996	UINT32 addr = offset >> 24;
	2997	if (addr == 0x10 || addr == 0x18 || addr == 0x1e)
	2998	{
	2999	UINT64 i = (UINT64)(m_gfx_fifo_cache_addr) << 32;
	3000	cobra_fifo *fifo_in = m_gfxfifo_in;
	3001
	3002	UINT32 a = (offset / 8) & 0xff;
	3003
	3004	fifo_in->push(&space.device(), (UINT32)(m_gfx_fifo_mem[a+0] >> 32) | i);
	3005	fifo_in->push(&space.device(), (UINT32)(m_gfx_fifo_mem[a+0] >>  0) | i);
	3006	fifo_in->push(&space.device(), (UINT32)(m_gfx_fifo_mem[a+1] >> 32) | i);
	3007	fifo_in->push(&space.device(), (UINT32)(m_gfx_fifo_mem[a+1] >>  0) | i);
	3008	fifo_in->push(&space.device(), (UINT32)(m_gfx_fifo_mem[a+2] >> 32) | i);
	3009	fifo_in->push(&space.device(), (UINT32)(m_gfx_fifo_mem[a+2] >>  0) | i);
	3010	fifo_in->push(&space.device(), (UINT32)(m_gfx_fifo_mem[a+3] >> 32) | i);
	3011	fifo_in->push(&space.device(), (UINT32)(m_gfx_fifo_mem[a+3] >>  0) | i);
	3012
	3013	m_renderer->gfx_fifo_exec();
	3014	}
	3015	else
	3016	{
	3017	logerror("gfx: data cache store at %08X\n", offset);
	3018	}
	3019	}
	3020
3023	3021	WRITE64_MEMBER(cobra_state::gfx_debug_state_w)
3024	3022	{
3025	3023	if (ACCESSING_BITS_40_47)
r241449	r241450
3260	3258	2048,
3261	3259	"S2MFIFO",
3262	3260	S2MFIFO_VERBOSE != 0,
3263		cobra_fifo::event_delegate(FUNC(cobra_state::s2mfifo_event_callback), this))
3264		);
3265
3266		m_maincpu->ppc_set_dcstore_callback(main_cpu_dc_store);
3267
3268		m_gfxcpu->ppc_set_dcstore_callback(gfx_cpu_dc_store);
3269
3270		m_subcpu->ppc4xx_set_dma_write_handler(0, sub_sound_dma_w, 44100);
3271		m_subcpu->ppc4xx_spu_set_tx_handler(sub_jvs_w);
3272
3273
3274		m_comram[0] = auto_alloc_array(machine(), UINT32, 0x40000/4);
	3261	cobra_fifo::event_delegate(FUNC(cobra_state::s2mfifo_event_callback), this))
	3262	);
	3263
	3264	m_maincpu->ppc_set_dcstore_callback(write32_delegate(FUNC(cobra_state::main_cpu_dc_store),this));
	3265
	3266	m_gfxcpu->ppc_set_dcstore_callback(write32_delegate(FUNC(cobra_state::gfx_cpu_dc_store), this));
	3267
	3268	m_subcpu->ppc4xx_set_dma_write_handler(0, write32_delegate(FUNC(cobra_state::sub_sound_dma_w), this), 44100);
	3269	m_subcpu->ppc4xx_spu_set_tx_handler(write8_delegate(FUNC(cobra_state::sub_jvs_w), this));
	3270
	3271
	3272	m_comram[0] = auto_alloc_array(machine(), UINT32, 0x40000/4);
3275	3273	m_comram[1] = auto_alloc_array(machine(), UINT32, 0x40000/4);
3276	3274
3277	3275	m_comram_page = 0;

trunk/src/mame/drivers/firebeat.c

r241449	r241450
256	256	void gcu_exec_display_list(bitmap_ind16 &bitmap, const rectangle &cliprect, int chip, UINT32 address);
257	257	UINT32 update_screen(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect, int chip);
258	258	UINT32 GCU_r(int chip, UINT32 offset, UINT32 mem_mask);
259		void GCU_w(int chip, UINT32 offset, UINT32 data, UINT32 mem_mask);
260		void set_ibutton(UINT8 *data);
261		int ibutton_w(UINT8 data);
262		void init_lights(write32_delegate out1, write32_delegate out2, write32_delegate out3);
263		void init_firebeat();
264		void init_keyboard();
	259	void GCU_w(int chip, UINT32 offset, UINT32 data, UINT32 mem_mask);
	260	void set_ibutton(UINT8 *data);
	261	int ibutton_w(UINT8 data);
	262	DECLARE_WRITE8_MEMBER(security_w);
	263	void init_lights(write32_delegate out1, write32_delegate out2, write32_delegate out3);
	264	void init_firebeat();
	265	void init_keyboard();
265	266	DECLARE_WRITE_LINE_MEMBER(sound_irq_callback);
266	267	DECLARE_WRITE_LINE_MEMBER(midi_uart_ch0_irq_callback);
267	268	DECLARE_WRITE_LINE_MEMBER(midi_uart_ch1_irq_callback);
r241449	r241450
1946	1947	}
1947	1948	}
1948	1949
1949		return r;
1950		}
	1950	return r;
	1951	}
	1952
	1953	WRITE8_MEMBER(firebeat_state::security_w)
	1954	{
	1955	int r = ibutton_w(data);
	1956	if (r >= 0)
	1957	m_maincpu->ppc4xx_spu_receive_byte(r);
	1958	}
	1959
	1960	/*****************************************************************************/
1951	1961
1952		static void security_w(device_t *device, UINT8 data)
1953		{
1954		firebeat_state *state = device->machine().driver_data<firebeat_state>();
1955		int r = state->ibutton_w(data);
1956		if (r >= 0)
1957		state->m_maincpu->ppc4xx_spu_receive_byte(r);
1958		}
1959
1960		/*****************************************************************************/
1961
1962	1962	void firebeat_state::init_lights(write32_delegate out1, write32_delegate out2, write32_delegate out3)
1963	1963	{
1964	1964	if(out1.isnull()) out1 = write32_delegate(FUNC(firebeat_state::lamp_output_w),this);
r241449	r241450
1979	1979
1980	1980	m_extend_board_irq_enable = 0x3f;
1981	1981	m_extend_board_irq_active = 0x00;
1982
1983		m_cur_cab_data = cab_data;
1984
1985		m_maincpu->ppc4xx_spu_set_tx_handler(security_w);
1986
1987		set_ibutton(rom);
1988
	1982
	1983	m_cur_cab_data = cab_data;
	1984
	1985	m_maincpu->ppc4xx_spu_set_tx_handler(write8_delegate(FUNC(firebeat_state::security_w), this));
	1986
	1987	set_ibutton(rom);
	1988
1989	1989	init_lights(write32_delegate(), write32_delegate(), write32_delegate());
1990	1990	}
1991	1991

trunk/src/mame/drivers/hornet.c

r241449	r241450
402	402	DECLARE_WRITE32_MEMBER(dsp_dataram1_w);
403	403	DECLARE_WRITE_LINE_MEMBER(voodoo_vblank_0);
404	404	DECLARE_WRITE_LINE_MEMBER(voodoo_vblank_1);
405		DECLARE_WRITE16_MEMBER(soundtimer_en_w);
406		DECLARE_WRITE16_MEMBER(soundtimer_count_w);
407		ADC12138_IPT_CONVERT_CB(adc12138_input_callback);
408
409		DECLARE_DRIVER_INIT(hornet);
410		DECLARE_DRIVER_INIT(hornet_2board);
	405	DECLARE_WRITE16_MEMBER(soundtimer_en_w);
	406	DECLARE_WRITE16_MEMBER(soundtimer_count_w);
	407	ADC12138_IPT_CONVERT_CB(adc12138_input_callback);
	408	DECLARE_WRITE8_MEMBER(jamma_jvs_w);
	409
	410	DECLARE_DRIVER_INIT(hornet);
	411	DECLARE_DRIVER_INIT(hornet_2board);
411	412	virtual void machine_start();
412	413	virtual void machine_reset();
413	414	DECLARE_MACHINE_RESET(hornet_2board);
r241449	r241450
1135	1136	MCFG_EEPROM_SERIAL_93C46_ADD("lan_eeprom")
1136	1137	MACHINE_CONFIG_END
1137	1138
1138
1139		/*****************************************************************************/
1140
1141		static void jamma_jvs_w(device_t *device, UINT8 data)
	1139
	1140	/*****************************************************************************/
	1141
	1142	WRITE8_MEMBER(hornet_state::jamma_jvs_w)
	1143	{
	1144	if (m_jvs_sdata_ptr == 0 && data != 0xe0)
	1145	return;
	1146	m_jvs_sdata[m_jvs_sdata_ptr] = data;
	1147	m_jvs_sdata_ptr++;
	1148
	1149	if (m_jvs_sdata_ptr >= 3 && m_jvs_sdata_ptr >= 3 + m_jvs_sdata[2])
	1150	jamma_jvs_cmd_exec();
	1151	}
	1152
	1153	int hornet_state::jvs_encode_data(UINT8 *in, int length)
1142	1154	{
1143		hornet_state *state = device->machine().driver_data<hornet_state>();
1144		if (state->m_jvs_sdata_ptr == 0 && data != 0xe0)
1145		return;
1146		state->m_jvs_sdata[state->m_jvs_sdata_ptr] = data;
1147		state->m_jvs_sdata_ptr++;
1148
1149		if (state->m_jvs_sdata_ptr >= 3 && state->m_jvs_sdata_ptr >= 3 + state->m_jvs_sdata[2])
1150		state->jamma_jvs_cmd_exec();
1151		}
1152
1153		int hornet_state::jvs_encode_data(UINT8 *in, int length)
1154		{
1155	1155	int inptr = 0;
1156	1156	int sum = 0;
1157	1157
r241449	r241450
1280	1280
1281	1281	DRIVER_INIT_MEMBER(hornet_state,hornet)
1282	1282	{
1283		m_konppc->set_cgboard_texture_bank(0, "bank5", memregion("user5")->base());
1284		m_led_reg0 = m_led_reg1 = 0x7f;
1285
1286		m_maincpu->ppc4xx_spu_set_tx_handler(jamma_jvs_w);
1287		}
1288
1289		DRIVER_INIT_MEMBER(hornet_state,hornet_2board)
	1283	m_konppc->set_cgboard_texture_bank(0, "bank5", memregion("user5")->base());
	1284	m_led_reg0 = m_led_reg1 = 0x7f;
	1285
	1286	m_maincpu->ppc4xx_spu_set_tx_handler(write8_delegate(FUNC(hornet_state::jamma_jvs_w), this));
	1287	}
	1288
	1289	DRIVER_INIT_MEMBER(hornet_state,hornet_2board)
1290	1290	{
1291	1291	m_konppc->set_cgboard_texture_bank(0, "bank5", memregion("user5")->base());
1292		m_konppc->set_cgboard_texture_bank(1, "bank6", memregion("user5")->base());
1293		m_led_reg0 = m_led_reg1 = 0x7f;
	1292	m_konppc->set_cgboard_texture_bank(1, "bank6", memregion("user5")->base());
	1293	m_led_reg0 = m_led_reg1 = 0x7f;
	1294
	1295	m_maincpu->ppc4xx_spu_set_tx_handler(write8_delegate(FUNC(hornet_state::jamma_jvs_w), this));
	1296	}
	1297
	1298	/*****************************************************************************/
1294	1299
1295		m_maincpu->ppc4xx_spu_set_tx_handler(jamma_jvs_w);
1296		}
1297
1298		/*****************************************************************************/
1299
1300	1300	ROM_START(sscope)
1301	1301	ROM_REGION32_BE(0x400000, "user1", 0)   /* PowerPC program */
1302	1302	ROM_LOAD16_WORD_SWAP("830d01.27p", 0x200000, 0x200000, CRC(de9b3dfa) SHA1(660652a5f745cb04687481c3626d8a43cd169193) )

https://github.com/mamedev/mame/commit/841c2d7b13d4550f83ddb6e4c5ae2b46d1772606

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