trunk/src/mame/drivers/maygay1b.c
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| 100 | 100 | |
| 101 | 101 | /////////////////////////////////////////////////////////////////////////// |
| 102 | 102 | |
| 103 | /* 6809 IRQ handler */ |
| 104 | void maygay1b_state::cpu0_firq(int data) |
| 105 | { |
| 106 | m_maincpu->set_input_line(M6809_FIRQ_LINE, data ? ASSERT_LINE : CLEAR_LINE); |
| 107 | } |
| 108 | |
| 109 | |
| 103 | 110 | // IRQ from Duart (hopper?) |
| 104 | 111 | WRITE_LINE_MEMBER(maygay1b_state::duart_irq_handler) |
| 105 | 112 | { |
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| 110 | 117 | // FIRQ, related to the sample playback? |
| 111 | 118 | READ8_MEMBER( maygay1b_state::m1_firq_trg_r ) |
| 112 | 119 | { |
| 113 | | static int i = 0xff; |
| 114 | | i ^= 0xff; |
| 115 | | m_maincpu->set_input_line(M6809_FIRQ_LINE, HOLD_LINE); |
| 116 | | LOG(("6809 firq\n")); |
| 117 | | return i; |
| 120 | int nar = m_msm6376->nar_r(); |
| 121 | if (nar) |
| 122 | { |
| 123 | cpu0_firq(1); |
| 124 | } |
| 125 | return nar; |
| 118 | 126 | } |
| 119 | 127 | |
| 120 | 128 | READ8_MEMBER( maygay1b_state::m1_firq_clr_r ) |
| 121 | 129 | { |
| 122 | | static int i = 0xff; |
| 123 | | i ^= 0xff; |
| 124 | | m_maincpu->set_input_line(M6809_FIRQ_LINE, CLEAR_LINE); |
| 125 | | LOG(("6809 firq clr\n")); |
| 126 | | return i; |
| 130 | cpu0_firq(0); |
| 131 | return 0; |
| 127 | 132 | } |
| 128 | 133 | |
| 129 | 134 | // NMI is periodic? or triggered by a write? |
| 130 | 135 | TIMER_DEVICE_CALLBACK_MEMBER( maygay1b_state::maygay1b_nmitimer_callback ) |
| 131 | 136 | { |
| 137 | //disabling for now |
| 132 | 138 | if (m_NMIENABLE) |
| 133 | 139 | { |
| 134 | 140 | LOG(("6809 nmi\n")); |
| 135 | | m_maincpu->set_input_line(INPUT_LINE_NMI, HOLD_LINE); |
| 141 | m_maincpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE); |
| 142 | m_NMIENABLE=0; |
| 136 | 143 | } |
| 144 | |
| 137 | 145 | } |
| 138 | 146 | |
| 139 | | |
| 140 | | |
| 147 | /* |
| 148 | void maygay1b_state::cpu0_nmi(int data) |
| 149 | { |
| 150 | m_maincpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE); |
| 151 | } |
| 152 | */ |
| 141 | 153 | /*************************************************************************** |
| 142 | 154 | 6821 PIA |
| 143 | 155 | ***************************************************************************/ |
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| 145 | 157 | // some games might differ.. |
| 146 | 158 | WRITE8_MEMBER(maygay1b_state::m1_pia_porta_w) |
| 147 | 159 | { |
| 148 | | // printf("m1_pia_porta_w %02x\n",data); |
| 149 | | |
| 150 | | m_vfd->por(!(data & 0x40)); |
| 160 | m_vfd->por(data & 0x40); |
| 151 | 161 | m_vfd->data(data & 0x10); |
| 152 | 162 | m_vfd->sclk(data & 0x20); |
| 153 | 163 | } |
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| 156 | 166 | { |
| 157 | 167 | int i; |
| 158 | 168 | for (i=0; i<8; i++) |
| 159 | | if ( data & (1 << i) ) output_set_indexed_value("triac", i, data & (1 << i)); |
| 169 | { |
| 170 | if ( data & (1 << i) ) |
| 171 | { |
| 172 | output_set_indexed_value("triac", i, data & (1 << i)); |
| 173 | } |
| 174 | } |
| 160 | 175 | } |
| 161 | 176 | |
| 162 | 177 | // input ports for M1 board //////////////////////////////////////// |
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| 361 | 376 | m_ALARMEN = (data & 1); |
| 362 | 377 | break; |
| 363 | 378 | case 2: // Enable |
| 364 | | //printf("nmi enable %02x\n",data); |
| 365 | | m_NMIENABLE = (data & 1); |
| 379 | if ( m_NMIENABLE == 0 && ( data & 1 ) ) |
| 380 | { |
| 381 | m_NMIENABLE = (data & 1); |
| 382 | //cpu0_nmi(1); |
| 383 | } |
| 366 | 384 | break; |
| 367 | 385 | case 3: // RTS |
| 368 | 386 | { |