MAME SVN History

199869 Revisions

r32761 Wednesday 15th October, 2014 at 07:19:47 UTC by Miodrag Milanović
Cleanups and version bump

[hash]	a7800.xml amiga_a3000.xml amiga_hardware.xml coleco.xml fm7_disk.xml fmtowns_cd.xml gamegear.xml gameking.xml gbcolor.xml intvecs.xml msx1_cart.xml nes.xml pencil2.xml psx.xml timex_dock.xml
[src]	version.c
[src/emu]	devcpu.c diimage.c machine.c webengine.c
[src/emu/bus/a2bus]	a2corvus.c a2lang.c corvfdc01.c corvfdc02.c corvfdc02.h laser128.c mouse.c timemasterho.c
[src/emu/bus/a7800]	a78_carts.h a78_slot.c a78_slot.h cpuwiz.c cpuwiz.h hiscore.c hiscore.h rom.c rom.h xboard.c xboard.h
[src/emu/bus/a800]	a800_carts.h a800_slot.c a800_slot.h oss.c oss.h rom.c rom.h sparta.c sparta.h
[src/emu/bus/apf]	rom.h slot.c slot.h
[src/emu/bus/arcadia]	slot.c slot.h
[src/emu/bus/c64]	dela_ep256.c rex_ep256.h
[src/emu/bus/centronics]	digiblst.h
[src/emu/bus/chanf]	rom.c rom.h slot.c slot.h
[src/emu/bus/cpc]	amdrum.h symbfac2.c symbfac2.h
[src/emu/bus/crvision]	rom.c rom.h slot.c slot.h
[src/emu/bus/gameboy]	gb_slot.h mbc.h
[src/emu/bus/gba]	gba_slot.h
[src/emu/bus/generic]	carts.c ram.c ram.h rom.c rom.h slot.c slot.h
[src/emu/bus/intv]	ecs.c ecs.h rom.c rom.h slot.c slot.h voice.h
[src/emu/bus/isa]	sb16.c svga_trident.c trident.c
[src/emu/bus/megadrive]	ggenie.c
[src/emu/bus/msx_cart]	disk.c
[src/emu/bus/msx_slot]	disk.c
[src/emu/bus/nes]	disksys.c nes_slot.c nes_slot.h
[src/emu/bus/odyssey2]	chess.h rom.c rom.h slot.c slot.h voice.c voice.h
[src/emu/bus/pet]	cb2snd.c
[src/emu/bus/rs232]	xvd701.c
[src/emu/bus/saturn]	sat_slot.c
[src/emu/bus/scv]	rom.h slot.c slot.h
[src/emu/bus/sega8]	ccatch.c mgear.h rom.c sega8_slot.c sega8_slot.h
[src/emu/bus/sms_ctrl]	graphic.c
[src/emu/bus/snes]	snes_slot.h
[src/emu/bus/vboy]	rom.h slot.c slot.h
[src/emu/bus/vc4000]	rom.c rom.h slot.c slot.h
[src/emu/bus/vcs]	compumat.c compumat.h dpc.c dpc.h rom.c rom.h scharger.c scharger.h vcs_slot.c vcs_slot.h
[src/emu/bus/vectrex]	rom.h slot.c slot.h
[src/emu/bus/vic20]	fe3.c fe3.h
[src/emu/bus/wswan]	rom.c rom.h slot.c slot.h
[src/emu/cpu/dsp56k]	dsp56k.c
[src/emu/cpu/hd61700]	hd61700.c hd61700.h
[src/emu/cpu/i86]	i186.c
[src/emu/cpu/mcs96]	mcs96.c
[src/emu/cpu/mips]	mips3drc.c
[src/emu/cpu/rsp]	rsp.c rspdrc.c
[src/emu/cpu/sh4]	sh4.c
[src/emu/cpu/tlcs90]	tlcs90.c
[src/emu/cpu/tms32031]	tms32031.h
[src/emu/cpu/tms32051]	tms32051.c tms32051.h
[src/emu/cpu/tms34010]	tms34010.c tms34010.h
[src/emu/cpu/tms7000]	tms7000.c tms7000.h
[src/emu/debug]	debugcpu.c
[src/emu/imagedev]	floppy.c
[src/emu/machine]	mb8421.c pit8253.c rp5h01.c smpc.c wozfdc.c
[src/emu/sound]	flt_rc.h k053260.c k053260.h samples.c samples.h speaker.h ymf278b.c zsg2.c
[src/emu/ui]	swlist.c ui.c
[src/emu/video]	315_5124.c epic12.c upd7220.c vooddefs.h voodoo.c
[src/lib/formats]	ap2_dsk.c dmk_dsk.c dmk_dsk.h mfi_dsk.c
[src/lib/web]	mongoose.c mongoose.h
[src/mame]	mame.lst mame.mak
[src/mame/audio]	cclimber.h leland.c mario.c
[src/mame/drivers]	20pacgal.c 4enraya.c 8080bw.c aces1.c alg.c aristmk4.c arkanoid.c atarisy4.c bartop52.c battlera.c bfm_sc1.c bfm_sc2.c bmcpokr.c btoads.c bublbobl.c calchase.c capr1.c caprcyc.c centiped.c chqflag.c coinmvga.c coolpool.c cops.c cps1.c cv1k.c dkong.c dlair.c dlair2.c dragrace.c fcrash.c foodf.c fuukifg2.c gaiden.c galaxian.c galpani3.c galpanic.c hikaru.c igs011.c igs017.c iqblock.c itech32.c jchan.c jclub2.c jeutel.c karnov.c legionna.c ltd.c macs.c mario.c maxaflex.c mazerbla.c megatech.c metro.c mgavegas.c midtunit.c midwunit.c midxunit.c midyunit.c model1.c model3.c mpu5hw.c namcops2.c namcos21.c naomi.c nmk16.c pacman.c peplus.c potgoldu.c punchout.c r2dx_v33.c raiden2.c rainbow.c rastersp.c redclash.c segac2.c segas18.c segas32.c segaybd.c simple_st0016.c skimaxx.c snesb.c snk6502.c snowbros.c speedbal.c speglsht.c splash.c srmp5.c st_mp100.c stv.c system16.c taito_z.c tatsumi.c tickee.c travrusa.c twinkle.c vamphalf.c vectrex.c warpsped.c xtheball.c
[src/mame/includes]	8080bw.h artmagic.h bfm_sc45.h cinemat.h coolpool.h cosmic.h exterm.h fuukifg2.h fuukifg3.h harddriv.h jpmimpct.h konamigx.h legionna.h meadows.h micro3d.h midtunit.h midyunit.h model1.h model3.h namcos2.h polyplay.h raiden2.h simple_st0016.h snk.h splash.h sslam.h stv.h suna8.h suprnova.h taito_f3.h tatsumi.h thepit.h tnzs.h vectrex.h
[src/mame/layout]	mgavegas.lay s11a.lay
[src/mame/machine]	315_5296.c amiga.c asic65.c atari.c awboard.h inder_vid.c inder_vid.h kaneko_calc3.h kaneko_toybox.h konppc.c model1.c nmk004.c raiden2cop.c raiden2cop.h seicop.c seicop.h st0016.c st0016.h vectrex.c
[src/mame/video]	antic.c antic.h battlera.c decmxc06.h dooyong.c fuukifg.c fuukifg.h fuukifg3.c gtia.c gtia.h k054156_k054157_k056832.c legionna.c mario.c model3.c seibuspi.c sknsspr.h skyfox.c snk.c taito_f3.c tc0480scp.c
[src/mess]	mess.mak tiny.lst
[src/mess/audio]	vc4000snd.h wswan_snd.h
[src/mess/drivers]	a2600.c a7800.c aim65.c apf.c apple2.c apple2gs.c apple3.c atari400.c atarist.c atom.c bbcbc.c beta.c casloopy.c cc40.c cgenie.c channelf.c concept.c crvision.c electron.c ep64.c exelv.c fc100.c fm7.c gameking.c gamepock.c gba.c geniusiq.c gmaster.c ibmpcjr.c intv.c itt3030.c kyocera.c laser3k.c m5.c msx.c myvision.c nc.c nes.c ngp.c pc2000.c pc6001.c pc8401a.c pc9801.c pegasus.c pencil2.c pet.c pockstat.c pokemini.c pt68k4.c pv1000.c pv2000.c rx78.c scv.c socrates.c sorcerer.c spc1000.c specpls3.c spectrum.c studio2.c supracan.c sv8000.c svision.c thomson.c ti74.c timex.c tsispch.c tutor.c tvc.c uzebox.c vboy.c vc4000.c vii.c x07.c
[src/mess/includes]	apple2.h atom.h concept.h electron.h intv.h radio86.h svi318.h
[src/mess/machine]	aim65.c amigakbd.c amstrad.c apple2.c apple3.c bbc.c concept.c electron.c gamecom.c gamepock.c intv.c lynx.c nc.c nes.c primo.c svi318.c thomson.c vtech2.c wswan.c
[src/mess/tools/imgtool/modules]	amiga.c
[src/mess/video]	advision.c apple2.c apple3.c maria.c maria.h nes.c thomson.c
[src/osd/sdl]	osdsdl.h sdlfile.c sdlptty_win32.c sdlsocket.c sdlsync_win32.c video.c
[src/osd/windows]	vconv.c video.c video.h window.c window.h winos.c winos.h winsync.c winsync.h

trunk/hash/gameking.xml
r32760	r32761
4	4	<!-- dumps are not yet verified as good, the 3-in-1 internal ROM is not yet dumped -->
5	5
6	6	<softwarelist name="gameking" description="TimeTop GameKing cartridges">
7
	7
8	8	<software name="2004">
9	9	<description>2004</description>
10	10	<year>200?</year>
r32760	r32761
25	25	<rom name="adventure legend carlo.bin" size="0x20000" crc="7d61d215" sha1="741684b5379d4be732a98beace5d09f37ff19bbf" offset="0x00000" />
26	26	</dataarea>
27	27	</part>
28		</software>
	28	</software>
29	29
30	30	<software name="aries">
31	31	<description>Aries</description>
r32760	r32761
36	36	<rom name="aries.bin" size="0x20000" crc="b854f1f2" sha1="1ad7a325aba2cf3593165b53e7ae3973388335f7" offset="0x00000" />
37	37	</dataarea>
38	38	</part>
39		</software>
	39	</software>
40	40
41	41	<software name="dinoadv">
42	42	<description>Dino Adventure Legend</description>
r32760	r32761
47	47	<rom name="dino adventure legend.bin" size="0x20000" crc="2df0c1e6" sha1="df4b5dc80a758d9e3c9b00384e3099ad8331faad" offset="0x00000" />
48	48	</dataarea>
49	49	</part>
50		</software>
	50	</software>
51	51
52	52	<software name="duckman">
53	53	<description>Duck Man</description>
r32760	r32761
58	58	<rom name="duck man.bin" size="0x20000" crc="9d12950a" sha1="376606097f66105d1a9e97e9793362f6f1e3b1a7" offset="0x00000" />
59	59	</dataarea>
60	60	</part>
61		</software>
	61	</software>
62	62
63	63	<software name="happybal">
64	64	<description>Happy Ball</description>
r32760	r32761
69	69	<rom name="happy ball.bin" size="0x20000" crc="79d4e738" sha1="fc14712260ed6e3d6313055046546d37b7c838d2" offset="0x00000" />
70	70	</dataarea>
71	71	</part>
72		</software>
	72	</software>
73	73
74	74	<software name="happykil">
75	75	<description>Happy Killer</description>
r32760	r32761
80	80	<rom name="happy killer.bin" size="0x20000" crc="9fd7ec65" sha1="705309829ee87689793c15be1f781d52471908d6" offset="0x00000" />
81	81	</dataarea>
82	82	</part>
83		</software>
	83	</software>
84	84
85	85	<software name="lanner">
86	86	<description>Lanneret</description>
r32760	r32761
91	91	<rom name="lanneret.bin" size="0x20000" crc="249df6a5" sha1="bcf92ab85cc97ffe94d6a363a87b0b5de62c3c66" offset="0x00000" />
92	92	</dataarea>
93	93	</part>
94		</software>
	94	</software>
95	95
96	96	<software name="penguin">
97	97	<description>Penguin</description>
r32760	r32761
102	102	<rom name="penguin.bin" size="0x20000" crc="8c7b81c9" sha1="2f253b6ab6f6b9fc114ffca120d13df2e1e5f860" offset="0x00000" />
103	103	</dataarea>
104	104	</part>
105		</software>
106
	105	</software>
	106
107	107	<software name="popper">
108	108	<description>Popper</description>
109	109	<year>200?</year>
r32760	r32761
113	113	<rom name="popper.bin" size="0x20000" crc="a704617b" sha1="314931548578303e5e80a2bcb03c92472cb014d9" offset="0x00000" />
114	114	</dataarea>
115	115	</part>
116		</software>
	116	</software>
117	117
118	118	<software name="sthero">
119	119	<description>Street Hero</description>
r32760	r32761
124	124	<rom name="street hero.bin" size="0x20000" crc="9e0fe489" sha1="2c442126999e4b112a48e42a82dfa9ad9d6efa22" offset="0x00000" />
125	125	</dataarea>
126	126	</part>
127		</software>
128
	127	</software>
	128
129	129	<software name="smotor">
130	130	<description>Supermotor</description>
131	131	<year>200?</year>
r32760	r32761
135	135	<rom name="supermotor.bin" size="0x20000" crc="6290b94b" sha1="0c3011da35170241637907bb23d79355db38f343" offset="0x00000" />
136	136	</dataarea>
137	137	</part>
138		</software>
	138	</software>
139	139
140	140	<software name="trojanl">
141	141	<description>Trojan Legend</description>
r32760	r32761
146	146	<rom name="trojan legend.bin" size="0x20000" crc="7ce3975e" sha1="e925e4f28efc85ce69fb504b85a98a60883aa30d" offset="0x00000" />
147	147	</dataarea>
148	148	</part>
149		</software>
	149	</software>
150	150
151
152	151
	152
153	153	</softwarelist>

trunk/hash/timex_dock.xml
r32760	r32761
235	235	</part>
236	236	</software>
237	237
238		<!-- TODO: add support for RAM in this cart (0xa000-0xffff) -->
	238	<!-- TODO: add support for RAM in this cart (0xa000-0xffff) -->
239	239	<software name="rwp32" supported="no">
240	240	<description>rWP32</description>
241	241	<year>19??</year>

trunk/hash/nes.xml
r32760	r32761
35601	35601	<feature name="pcb_model" value="NR8OV2-1" />
35602	35602	<feature name="u1" value="U1 PRG" />
35603	35603	<feature name="u2" value="U2 CHR" />
35604		<feature name="u3" value="CME-01" /> <!-- CIC clone? -->
	35604	<feature name="u3" value="CME-01" /> <!-- CIC clone? -->
35605	35605	<feature name="mirroring" value="vertical" />
35606	35606	<dataarea name="prg" size="262144">
35607	35607	<rom name="sup.adv.quest.u1" size="262144" crc="6a7bf037" sha1="22b430d7d4167f16751facd3515f7c8e1133a3d9" offset="00000" />

trunk/hash/gbcolor.xml
r32760	r32761
23639	23639	* CBA078 Shuma Baolong - Diannao Pian 数码暴龙-电脑篇
23640	23640	* CBA079 Yingxiong Tianxia 英雄天下
23641	23641	* CBA080 Sanguozhi Wudai 三国志五代
23642		* CBA083 Tai Kong Bao Bei 太空宝贝
	23642	* CBA083 Tai Kong Bao Bei 太空宝贝
23643	23643	* CBA085 Shu Ma Bao Bei - Huojian Bingtuan 数码宝贝-火箭兵团
23644	23644	* CBA086 Shu Ma Bao Bei - Chao Mengmeng Fanji Zhan 数码宝贝-超梦梦反击战
23645	23645	* CBA087 Shu Ma Bao Bei - Hai Zhi Shen 数码宝贝-海之神

trunk/hash/gamegear.xml
r32760	r32761
768	768	</software>
769	769
770	770	<!-- some disassembling performed by Paul Baker suggests that this version is a prototype
771		e.g. the mapper control register at $fffc gets set to $80, you cannot switch characters
772		on the pause screen, some messages are not displayed ("Sorry boys, no tickets, no show!"
773		to explain why it is not possible to progress beyond a certain point in the game without
	771	e.g. the mapper control register at $fffc gets set to $80, you cannot switch characters
	772	on the pause screen, some messages are not displayed ("Sorry boys, no tickets, no show!"
	773	to explain why it is not possible to progress beyond a certain point in the game without
774	774	a certain item) -->
775	775	<software name="beavisp" cloneof="beavis">
776	776	<description>Beavis and Butt-head (Prototype?)</description>
r32760	r32761
7285	7285	</software>
7286	7286
7287	7287	<software name="soniclab">
7288		<!-- A final pre-release version of this same dump was found on a proto board with 4x128K sockets and no labels -->
	7288	<!-- A final pre-release version of this same dump was found on a proto board with 4x128K sockets and no labels -->
7289	7289	<description>Sonic Labyrinth (World)</description>
7290	7290	<year>1995</year>
7291	7291	<publisher>Sega</publisher>
r32760	r32761
7594	7594	</software>
7595	7595
7596	7596	<software name="sonic2d" cloneof="sonic2">
7597		<!-- This predates the final release and contains some different tiles & sprites compared to the final game -->
	7597	<!-- This predates the final release and contains some different tiles & sprites compared to the final game -->
7598	7598	<description>Sonic The Hedgehog 2 (Rolling Demo)</description>
7599	7599	<year>1992</year>
7600	7600	<publisher>Sega</publisher>
r32760	r32761
7609	7609	<feature name="batt" value="" />
7610	7610	<feature name="sw" value="ON = 1M / OFF = 256" />
7611	7611	<dataarea name="rom" size="262144">
7612		<!-- The ROM should be split in two halves -->
	7612	<!-- The ROM should be split in two halves -->
7613	7613	<rom name="sonic_2_auto_demo_prototype_(1991-12-05)_tmr_sega_cb06_ffff.bin" size="262144" crc="15ad37a5" sha1="b780c6f059b48d1bb48ee2ad521552dab1487c88" offset="000000" />
7614	7614	</dataarea>
7615	7615	</part>
r32760	r32761
8634	8634	</software>
8635	8635
8636	8636	<software name="tailsadv">
8637		<!-- A final pre-release version of this same dump was found on a proto board with 4x128K sockets and no labels -->
	8637	<!-- A final pre-release version of this same dump was found on a proto board with 4x128K sockets and no labels -->
8638	8638	<description>Tails Adventures (World)</description>
8639	8639	<year>1995</year>
8640	8640	<publisher>Sega</publisher>

trunk/hash/a7800.xml
r32760	r32761
1318	1318	</software>
1319	1319
1320	1320	<!--
1321		The code has some race conditions for NMIs (related to input readings)
1322		and often fails to boot on real systems too. To successfully start the
	1321	The code has some race conditions for NMIs (related to input readings)
	1322	and often fails to boot on real systems too. To successfully start the
1323	1323	game, you can keep pressed Button 1 during Atari logo (thanks to Mike
1324	1324	Saarna for debugging the problem)
1325	1325	-->
r32760	r32761
2369	2369
2370	2370	<!-- This version features a lot LESS sounds than the newer version:
2371	2371	e.g. no sound in bobsled ans ski jump games!
2372		Dump is confirmed from multiple carts, and it was probably used in
	2372	Dump is confirmed from multiple carts, and it was probably used in
2373	2373	some erlier production run, until they found out the mistake and
2374	2374	replaced it with the complete version -->
2375	2375	<software name="wingameso" cloneof="wingames">

trunk/hash/amiga_hardware.xml
r32760	r32761
12	12	<dataarea name="flop" size="901120">
13	13	<rom name="370132_a570_utilities.adf" size="901120" crc="30097474" sha1="958b97674e3e99fb9b0e3117009f27d4e7a9220b" offset="0"/>
14	14	</dataarea>
15		</part>
	15	</part>
16	16	</software>
17	17
18	18	<software name="a590">
r32760	r32761
25	25	<dataarea name="flop" size="901120">
26	26	<rom name="317734-01_a590_scsi.adf" size="901120" crc="a560a938" sha1="9c6136c6580779a948cd1c0b50cb229512af415c" offset="0"/>
27	27	</dataarea>
28		</part>
	28	</part>
29	29	</software>
30	30
31	31	<software name="a590_wd" cloneof="a590">
r32760	r32761
40	40	<dataarea name="flop" size="901120">
41	41	<rom name="317734-03_a590_wd.adf" size="901120" crc="a88fda41" sha1="7424f8645e1903e3e4ec8bb824186868319be1f3" offset="0"/>
42	42	</dataarea>
43		</part>
	43	</part>
44	44	</software>
45	45
46	46	<software name="a590_seagate" cloneof="a590">
r32760	r32761
52	52	<dataarea name="flop" size="901120">
53	53	<rom name="317734-04_a590_seagate.adf" size="901120" status="nodump" offset="0"/>
54	54	</dataarea>
55		</part>
	55	</part>
56	56	</software>
57	57
58	58	<software name="a590_ram">
r32760	r32761
64	64	<dataarea name="flop" size="901120">
65	65	<rom name="317830-01_a590_ram_test.adf" size="901120" crc="6583d1d0" sha1="7779b825b8555956d341ff7e909ab71d89e2321c" offset="0"/>
66	66	</dataarea>
67		</part>
	67	</part>
68	68	</software>
69	69
70	70	<software name="a2024">
r32760	r32761
76	76	<dataarea name="flop" size="901120">
77	77	<rom name="317809-01_a2024_jumpstart.adf" size="901120" crc="dad46588" sha1="30c2c1f1d98bd008b2c67f3b23480181935d4b01" offset="0"/>
78	78	</dataarea>
79		</part>
	79	</part>
80	80	</software>
81	81
82	82	<software name="a2091">
r32760	r32761
90	90	<dataarea name="flop" size="901120">
91	91	<rom name="317806-04_a2091_setup.adf" size="901120" crc="122c8f93" sha1="603e106c1a44a209171610af8d48bc35ad31c9bc" offset="0"/>
92	92	</dataarea>
93		</part>
	93	</part>
94	94	</software>
95	95
96	96	<software name="a2058">
r32760	r32761
102	102	<dataarea name="flop" size="901120">
103	103	<rom name="317719-01_a2058_ram_test.adf" size="901120" crc="5dba7fc3" sha1="76fbce4bef7df0f6042c85376d9bdfd4d4911e74" offset="0"/>
104	104	</dataarea>
105		</part>
	105	</part>
106	106	</software>
107	107
108	108	<software name="a2232">
r32760	r32761
114	114	<dataarea name="flop" size="901120">
115	115	<rom name="317769-01_a2232_install.adf" size="901120" crc="3caa21b7" sha1="24f47f6f88712f046303b8812a598043440a5e6d" offset="0"/>
116	116	</dataarea>
117		</part>
	117	</part>
118	118	</software>
119	119
120	120	<software name="a2300">
r32760	r32761
126	126	<dataarea name="flop" size="901120">
127	127	<rom name="317718-02_a2300_genlock_demo.adf" size="901120" crc="464ff0f6" sha1="26b94e8d52d35e2746b74610bb9b65eb2f899297" offset="0"/>
128	128	</dataarea>
129		</part>
	129	</part>
130	130	</software>
131	131
132	132	<software name="a2320">
r32760	r32761
138	138	<dataarea name="flop" size="901120">
139	139	<rom name="317210-01_a2320_test_demo.adf" size="901120" crc="cff98aae" sha1="f46f7de0d908ed68abfd784d84b964cbce7dc503" offset="0"/>
140	140	</dataarea>
141		</part>
	141	</part>
142	142	</software>
143	143
144	144	</softwarelist>

trunk/hash/fmtowns_cd.xml
r32760	r32761
2	2	<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
3	3	<softwarelist name="fmtowns" description="FM Towns CD-ROMs">
4	4	<!-- skeleton test list -->
5
6		<!-- works well on fmtmarty, keyboard seems to interfere with movements on fmtowns -->
	5
	6	<!-- works well on fmtmarty, keyboard seems to interfere with movements on fmtowns -->
7	7	<software name="raiden">
8	8	<description>Raiden Densetsu / Raiden Trad</description>
9	9	<year>1991</year>

trunk/hash/pencil2.xml
r32760	r32761
2	2	<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
3	3	<softwarelist name="pencil2" description="Hanimex Pencil II cartridges">
4	4
5		<!--
	5	<!--
6	6
7	7	Undumped known carts
8	8
r32760	r32761
16	16	-->
17	17
18	18
19		<!--
	19	<!--
20	20
21	21	BASIC CART PEN-700 11-50332-31 Rev.0
22	22	SD-BASIC VERSION 2.0 FOR PENCIL II

trunk/hash/coleco.xml
r32760	r32761
437	437
438	438	<software name="choplift">
439	439	<!-- Choplifter (1984)(Coleco)[a].bin -->
440		<!-- Other available dump has corrupted gfx -->
	440	<!-- Other available dump has corrupted gfx -->
441	441	<description>Choplifter!</description>
442	442	<year>1984</year>
443	443	<publisher>Coleco / CBS</publisher>
r32760	r32761
699	699	<part name="cart" interface="coleco_cart">
700	700	<dataarea name="rom" size="16384">
701	701	<rom name="apshai.1" size="8192" crc="aa3ec181" sha1="7f79628c298ad6e410af82eeb33871869ad23de8" offset="0x0000" />
702		<!-- 2nd 8K chunk containes two copies of the same 4K data -->
	702	<!-- 2nd 8K chunk containes two copies of the same 4K data -->
703	703	<rom name="apshai.2" size="8192" crc="0e440f8f" sha1="09ffaeb79cdd8173882b77a8398a4e00ba826de1" offset="0x2000" />
704	704	</dataarea>
705	705	</part>
r32760	r32761
2262	2262	<dataarea name="rom" size="24576">
2263	2263	<rom name="subroc.1" size="8192" crc="ff56b769" sha1="612a0abd13c4c7790890cbcb265a7fd786c7ec5c" offset="0x0000" />
2264	2264	<rom name="subroc.2" size="8192" crc="e9e60d4c" sha1="bfc94db65985b7a906099465a47d900f7a9a9106" offset="0x2000" />
2265		<!-- 3rd 8K chunk containes two copies of the same 4K data -->
	2265	<!-- 3rd 8K chunk containes two copies of the same 4K data -->
2266	2266	<rom name="subroc.3" size="8192" crc="abe18f08" sha1="6ebdc68397c7b20dceba12ff754f88c955d5f98a" offset="0x4000" />
2267	2267	</dataarea>
2268	2268	</part>
r32760	r32761
2369	2369	</software>
2370	2370
2371	2371	<software name="zaxxont" cloneof="zaxxon">
2372		<!-- The Taiwan Cooper cart contains a 32K ROM, the last 8K of which was found to
2373		contain 0x4000-0x4fff from Super Action Baseball followed by 0x1000-0x1fff
2374		from Meteoric Shower! -->
	2372	<!-- The Taiwan Cooper cart contains a 32K ROM, the last 8K of which was found to
	2373	contain 0x4000-0x4fff from Super Action Baseball followed by 0x1000-0x1fff
	2374	from Meteoric Shower! -->
2375	2375	<description>Zaxxon (Taiwan Cooper)</description>
2376	2376	<year>198?</year>
2377	2377	<publisher>Taiwan Cooper</publisher>

trunk/hash/psx.xml
r32760	r32761
704	704	</part>
705	705	</software>
706	706
707		<!-- Redump.org sets -->
708
709		<software name="raidendx" supported="yes"> <!-- Hamster re-release) -->
	707	<!-- Redump.org sets -->
	708
	709	<software name="raidendx" supported="yes"> <!-- Hamster re-release) -->
710	710	<description>Raiden DX (Japan, V1.1)</description>
711	711	<year>199?</year>
712	712	<publisher>Seibu / Hamster</publisher>
r32760	r32761
717	717	</diskarea>
718	718	</part>
719	719	</software>
720
721		<software name="raidendxo" cloneof="raidendx" supported="yes"> <!-- original release) -->
	720
	721	<software name="raidendxo" cloneof="raidendx" supported="yes"> <!-- original release) -->
722	722	<description>Raiden DX (Japan, V1.0)</description>
723	723	<year>199?</year>
724	724	<publisher>Seibu</publisher>
r32760	r32761
729	729	</diskarea>
730	730	</part>
731	731	</software>
732
	732
733	733	<software name="raidenpr" supported="yes">
734	734	<description>Raiden Project (USA)</description>
735	735	<year>199?</year>
r32760	r32761
740	740	<disk name="raiden project, the (usa)" sha1="cb1e4fae25d42e70fcb3eec5e1c1afcbdc5c2af3"/>
741	741	</diskarea>
742	742	</part>
743		</software>
744
745		<!-- this image doesn't boot, some kind of copy protection? could be bad -->
	743	</software>
	744
	745	<!-- this image doesn't boot, some kind of copy protection? could be bad -->
746	746	<software name="raidenprj" cloneof="raidenpr" supported="no">
747	747	<description>Raiden Project (Japan)</description>
748	748	<year>1995</year>
r32760	r32761
753	753	<disk name="raiden project (japan)" sha1="12ec8ee3117df1f95752dc65155a611f43725251"/>
754	754	</diskarea>
755	755	</part>
756		</software>
757
	756	</software>
	757
758	758	<!-- Images below are 'low-grade' ie not dumped to any specific standard, or verified to be of any specific quality, they could have bad gaps or audio tracks etc. -->
759	759	<!-- They should be replaced with better quality images once said images are available (and verified to be the same versions) -->
760	760

trunk/hash/amiga_a3000.xml
r32760	r32761
31	31	</dataarea>
32	32	</part>
33	33	</software>
34
	34
35	35	<!-- A3000 Installation disks -->
36
	36
37	37	<software name="a3kin203">
38	38	<description>A3000 Install Disk 2.03</description>
39	39	<year>1991</year>
r32760	r32761
44	44	<rom name="335603-04_install.adf" size="901120" crc="9a3cc466" sha1="b12a225890a3957bb01dcbfba44c046c19e19c8f" offset="0"/>
45	45	</dataarea>
46	46	</part>
47		</software>
	47	</software>
48	48
49	49	<!-- Amiga UNIX System V Release 4 -->
50	50	<!-- TODO: Part numbers -->
51
	51
52	52	<software name="amix11">
53	53	<description>UNIX System V Release 4 Amiga Version 1.1</description>
54	54	<year>1990</year>

trunk/hash/fm7_disk.xml
r32760	r32761
1657	1657	</dataarea>
1658	1658	</part>
1659	1659	</software>
1660
	1660
1661	1661	<software name="mdos7_09">
1662	1662	<description>M-DOS7 Volume 9</description>
1663	1663	<year>19??</year>

trunk/hash/intvecs.xml
r32760	r32761
100	100	<dataarea name="D000" size="0x4000">
101	101	<rom name="world series major league baseball.d0" size="0x4000" crc="839fa5c7" sha1="1ef12665079d1ce50bd2419b668344a08c9a872f" offset="0x0000"/>
102	102	</dataarea>
103		<!-- two ROM pages -->
	103	<!-- two ROM pages -->
104	104	<dataarea name="F000" size="0x4000">
105	105	<rom name="world series major league baseball (page 0).f0" size="0x2000" crc="a0f2fe49" sha1="fab397b49c5a7db53a501caea42fce169da5a31a" offset="0x0000"/>
106	106	<rom name="world series major league baseball (page 1).f0" size="0x2000" crc="94d6b056" sha1="df2a8c950dd1c398db901a624c04322d2b4f2782" offset="0x2000"/>

trunk/hash/msx1_cart.xml
r32760	r32761
14536	14536	<feature name="mapper" value="NOMAPPER" />
14537	14537	<dataarea name="rom" size="131072">
14538	14538	<!--
14539		20140725:
14540		There are 3 versions of this rom floating around:
14541		930eae7057af1652abae794072b296a59decd61b - a "dirty" dump; it seems to be a direct memory copy made on an MSX and contains RAM contents at 3000-3FFF and 7000-7FFF
14542		a45692849acf29ddb653707a62747985439f6d4f - RAM areas are set to FFs
14543		36d47cf70618fdb460f97a8ceb75013ec4529063 - A dump made using an eeprom reader. This dump differs one bit with the dump above (offset 8a49, bit 3)
14544		By looking the code it is not yet possible to say which one is 100% correct, so marking it as baddump for the moment.
	14539	20140725:
	14540	There are 3 versions of this rom floating around:
	14541	930eae7057af1652abae794072b296a59decd61b - a "dirty" dump; it seems to be a direct memory copy made on an MSX and contains RAM contents at 3000-3FFF and 7000-7FFF
	14542	a45692849acf29ddb653707a62747985439f6d4f - RAM areas are set to FFs
	14543	36d47cf70618fdb460f97a8ceb75013ec4529063 - A dump made using an eeprom reader. This dump differs one bit with the dump above (offset 8a49, bit 3)
	14544	By looking the code it is not yet possible to say which one is 100% correct, so marking it as baddump for the moment.
14545	14545	-->
14546	14546	<rom name="msx audio (japan) (fs-ca1) (program).rom" size="131072" crc="78584d2e" sha1="a45692849acf29ddb653707a62747985439f6d4f" status="baddump" offset="0" />
14547	14547	</dataarea>
r32760	r32761
17109	17109	</part>
17110	17110	<!-- The package came with a copy of MSX-DOS -->
17111	17111	<!--
17112		<part name="flop1" interface="floppy_3_5">
17113		</part>
	17112	<part name="flop1" interface="floppy_3_5">
	17113	</part>
17114	17114	-->
17115	17115	</software>
17116	17116
r32760	r32761
17126	17126	</dataarea>
17127	17127	</part>
17128	17128	<!--
17129		The floppy drive was most likely bundled with a copy of MSX-DOS, but we are not 100% sure yet
17130		<part name="flop1" interface="floppy_3_5">
17131		</part>
	17129	The floppy drive was most likely bundled with a copy of MSX-DOS, but we are not 100% sure yet
	17130	<part name="flop1" interface="floppy_3_5">
	17131	</part>
17132	17132	-->
17133	17133	</software>
17134	17134

trunk/src/osd/windows/video.h
r32760	r32761
38	38	void refresh();
39	39	float get_aspect();
40	40	void set_aspect(float a) { aspect = a; }
41
	41
42	42	win_monitor_info * next; // pointer to next monitor in list
43	43	HMONITOR handle; // handle to the monitor
44		MONITORINFOEX info; // most recently retrieved info
45		private:
	44	MONITORINFOEX info; // most recently retrieved info
	45	private:
46	46	float aspect; // computed/configured aspect ratio of the physical device
47	47	int reqwidth; // requested width for this monitor
48	48	int reqheight; // requested height for this monitor

trunk/src/osd/windows/winos.c
r32760	r32761
32	32	char osd_getenv(const char name)
33	33	{
34	34	return getenv(name);
35		}
		No newline at end of file
	35	}

trunk/src/osd/windows/winos.h
r32760	r32761
29	29
30	30	pointer to value
31	31	-----------------------------------------------------------------------------*/
32		char osd_getenv(const char name);
		No newline at end of file
	32	char osd_getenv(const char name);

trunk/src/osd/windows/window.c
r32760	r32761
245	245
246	246	// set up the window list
247	247	last_window_ptr = &win_window_list;
248
	248
249	249	return true;
250	250	}
251	251
r32760	r32761
313	313	m_target(NULL),
314	314	m_targetview(0),
315	315	m_targetorient(0),
316		m_primlist(NULL),
	316	m_primlist(NULL),
317	317	m_lastclicktime(0),
318	318	m_lastclickx(0),
319	319	m_lastclicky(0),
r32760	r32761
321	321	m_machine(machine)
322	322	{
323	323	memset(m_title,0,sizeof(m_title));
324		m_non_fullscreen_bounds.left = 0;
325		m_non_fullscreen_bounds.top = 0;
326		m_non_fullscreen_bounds.right = 0;
	324	m_non_fullscreen_bounds.left = 0;
	325	m_non_fullscreen_bounds.top = 0;
	326	m_non_fullscreen_bounds.right = 0;
327	327	m_non_fullscreen_bounds.bottom = 0;
328	328	}
329	329
r32760	r32761
331	331	{
332	332	}
333	333
334
	334
335	335	//============================================================
336	336	// winwindow_process_events_periodic
337	337	// (main thread)

trunk/src/osd/windows/window.h
r32760	r32761
36	36	{
37	37	public:
38	38	win_window_info(running_machine &machine);
39		virtual ~win_window_info();
	39	virtual ~win_window_info();
40	40
41	41	running_machine &machine() const { return m_machine; }
42	42
43	43	void update();
44
	44
45	45	win_window_info * m_next;
46	46	volatile int m_init_state;
47	47

trunk/src/osd/windows/winsync.c
r32760	r32761
373	373	DeleteCriticalSection(&lock->section);
374	374	#endif
375	375	free(lock);
376		}
		No newline at end of file
	376	}

trunk/src/osd/windows/vconv.c
r32760	r32761
99	99	{ 0, "c++", "" },
100	100	{ 0, "-flto", "/GL" },
101	101	{ 0, "-fno-optimize-sibling-calls", "" },
102		{ VS2005, "-fopenmp", "/openmp" },
	102	{ VS2005, "-fopenmp", "/openmp" },
103	103	{ 0 }
104	104	};
105	105

trunk/src/osd/windows/winsync.h
r32760	r32761
197	197
198	198	void osd_scalable_lock_free(osd_scalable_lock *lock);
199	199
200		#endif /* __WINSYNC__ */
		No newline at end of file
	200	#endif /* __WINSYNC__ */

trunk/src/osd/windows/video.c
r32760	r32761
97	97	void windows_osd_interface::video_exit()
98	98	{
99	99	window_exit();
100
	100
101	101	// free all of our monitor information
102	102	while (win_monitor_list != NULL)
103	103	{
r32760	r32761
111	111
112	112	win_monitor_info::win_monitor_info()
113	113	: next(NULL),
114		handle(NULL),
115		aspect(0.0f),
116		reqwidth(0),
117		reqheight(0)
	114	handle(NULL),
	115	aspect(0.0f),
	116	reqwidth(0),
	117	reqheight(0)
118	118	{
119	119	}
120	120

trunk/src/osd/sdl/sdlsync_win32.c
r32760	r32761
9	9	//
10	10	//============================================================
11	11
12		#include "../windows/winsync.c"
		No newline at end of file
	12	#include "../windows/winsync.c"

trunk/src/osd/sdl/sdlsocket.c
r32760	r32761
192	192	osd_free(file);
193	193	return FILERR_NONE;
194	194	}
195		#endif
		No newline at end of file
	195	#endif

trunk/src/osd/sdl/osdsdl.h
r32760	r32761
83	83
84	84	#define SDLOPTVAL_OPENGL "opengl"
85	85	#define SDLOPTVAL_SOFT "soft"
86		#define SDLOPTVAL_SDL2ACCEL "accel"
	86	#define SDLOPTVAL_SDL2ACCEL "accel"
87	87
88	88	#define SDLMAME_LED(x) "led" #x
89	89

trunk/src/osd/sdl/video.c
r32760	r32761
134	134	void sdl_osd_interface::video_exit()
135	135	{
136	136	window_exit();
137
	137
138	138	// free all of our monitor information
139	139	while (sdl_monitor_list != NULL)
140	140	{

trunk/src/osd/sdl/sdlfile.c
r32760	r32761
499	499
500	500	return result;
501	501	}
502		#endif
		No newline at end of file
	502	#endif

trunk/src/osd/sdl/sdlptty_win32.c
r32760	r32761
11	11	//============================================================
12	12
13	13	#include "../windows/winptty.c"
14

trunk/src/emu/debug/debugcpu.c
r32760	r32761
1931	1931	machine.debug_view().flush_osd_updates();
1932	1932
1933	1933	machine.manager().web()->serve();
1934
	1934
1935	1935	// clear the memory modified flag and wait
1936	1936	global->memory_modified = false;
1937	1937	if (machine.debug_flags & DEBUG_FLAG_OSD_ENABLED)

trunk/src/emu/cpu/tms7000/tms7000.c
r32760	r32761
899	899	{
900	900	// init/zerofill
901	901	m_control = 0;
902
	902
903	903	// register for savestates
904	904	save_item(NAME(m_control));
905	905
r32760	r32761
910	910	{
911	911	m_control = 0;
912	912	m_io->write_byte(TMS7000_PORTE, 0xff);
913
	913
914	914	tms7000_device::device_reset();
915	915	}
916	916

trunk/src/emu/cpu/tms7000/tms7000.h
r32760	r32761
313	313
314	314	DECLARE_READ8_MEMBER(control_r);
315	315	DECLARE_WRITE8_MEMBER(control_w);
316
	316
317	317	DECLARE_READ8_MEMBER(dockbus_status_r);
318	318	DECLARE_WRITE8_MEMBER(dockbus_status_w);
319	319	DECLARE_READ8_MEMBER(dockbus_data_r);

trunk/src/emu/cpu/hd61700/hd61700.c
r32760	r32761
138	138	m_kb_write_cb.resolve_safe();
139	139	m_port_read_cb.resolve_safe(0xff);
140	140	m_port_write_cb.resolve_safe();
141
	141
142	142	// save state
143	143	save_item(NAME(m_ppc));
144	144	save_item(NAME(m_curpc));

trunk/src/emu/cpu/hd61700/hd61700.h
r32760	r32761
76	76	template<class _Object> static devcb_base &set_kb_read_callback(device_t &device, _Object object) { return downcast<hd61700_cpu_device &>(device).m_kb_read_cb.set_callback(object); }
77	77	template<class _Object> static devcb_base &set_port_write_callback(device_t &device, _Object object) { return downcast<hd61700_cpu_device &>(device).m_port_write_cb.set_callback(object); }
78	78	template<class _Object> static devcb_base &set_port_read_callback(device_t &device, _Object object) { return downcast<hd61700_cpu_device &>(device).m_port_read_cb.set_callback(object); }
79
	79
80	80	protected:
81	81	// device-level overrides
82	82	virtual void device_start();
r32760	r32761
155	155	devcb_write8 m_kb_write_cb; //keyboard matrix write
156	156	devcb_read8 m_port_read_cb; //8 bit port read
157	157	devcb_write8 m_port_write_cb; //8 bit port write
158
	158
159	159	// flag definitions
160	160	static const int FLAG_Z = 0x80;
161	161	static const int FLAG_C = 0x40;

trunk/src/emu/cpu/tms32051/tms32051.c
r32760	r32761
45	45	**************************************************************************/
46	46
47	47	static ADDRESS_MAP_START( internal_pgm, AS_PROGRAM, 16, tms32051_device )
48		// AM_RANGE(0x0000, 0x1fff) AM_ROM // ROM TODO: is off-chip if MP/_MC = 0
	48	// AM_RANGE(0x0000, 0x1fff) AM_ROM // ROM TODO: is off-chip if MP/_MC = 0
49	49	AM_RANGE(0x2000, 0x23ff) AM_RAM AM_SHARE("saram") // SARAM TODO: is off-chip if RAM bit = 0
50	50	AM_RANGE(0xfe00, 0xffff) AM_RAM AM_SHARE("daram_b0") // DARAM B0 TODO: is off-chip if CNF = 0
51	51	ADDRESS_MAP_END
r32760	r32761
406	406	case 0x1d: return m_cber2;
407	407	case 0x1e: return m_cbcr;
408	408	case 0x1f: return m_bmar;
409
	409
410	410	case 0x20: return m_serial.drr;
411	411	case 0x21: return m_serial.dxr;
412	412

trunk/src/emu/cpu/tms32051/tms32051.h
r32760	r32761
134	134	UINT16 tim;
135	135	UINT16 prd;
136	136	} m_timer;
137
	137
138	138	struct
139	139	{
140	140	UINT16 drr;

trunk/src/emu/cpu/mcs96/mcs96.c
r32760	r32761
112	112	{
113	113	internal_update(total_cycles());
114	114
115		// if(inst_substate)
116		// do_exec_partial();
	115	// if(inst_substate)
	116	// do_exec_partial();
117	117
118	118	while(icount > 0) {
119	119	while(icount > bcount) {
r32760	r32761
125	125	}
126	126	while(bcount && icount <= bcount)
127	127	internal_update(total_cycles() + icount - bcount);
128		// if(inst_substate)
129		// do_exec_partial();
	128	// if(inst_substate)
	129	// do_exec_partial();
130	130	}
131	131	}
132	132

trunk/src/emu/cpu/mips/mips3drc.c
r32760	r32761
2483	2483	void mips3_device::generate_badcop(drcuml_block *block, const int cop)
2484	2484	{
2485	2485	UML_TEST(block, CPR032(COP0_Status), SR_COP0 << cop); // test [Status], SR_COP0 << cop
2486		UML_EXHc(block, COND_Z, *m_exception[EXCEPTION_BADCOP], cop); // exh badcop,cop,Z
	2486	UML_EXHc(block, COND_Z, *m_exception[EXCEPTION_BADCOP], cop); // exh badcop,cop,Z
2487	2487	}
2488	2488
2489	2489	/*-------------------------------------------------------------------------

trunk/src/emu/cpu/dsp56k/dsp56k.c
r32760	r32761
106	106	* Internal Memory Maps
107	107	****************************************************************************/
108	108	static ADDRESS_MAP_START( dsp56156_program_map, AS_PROGRAM, 16, dsp56k_device )
109		AM_RANGE(0x0000,0x07ff) AM_READWRITE(program_r, program_w) /* 1-5 */
	109	AM_RANGE(0x0000,0x07ff) AM_READWRITE(program_r, program_w) /* 1-5 */
110	110	// AM_RANGE(0x2f00,0x2fff) AM_ROM /* 1-5 PROM reserved memory. Is this the right spot for it? */
111	111	ADDRESS_MAP_END
112	112
113	113	static ADDRESS_MAP_START( dsp56156_x_data_map, AS_DATA, 16, dsp56k_device )
114		AM_RANGE(0x0000,0x07ff) AM_RAM /* 1-5 */
115		AM_RANGE(0xffc0,0xffff) AM_READWRITE(peripheral_register_r, peripheral_register_w) /* 1-5 On-chip peripheral registers memory mapped in data space */
	114	AM_RANGE(0x0000,0x07ff) AM_RAM /* 1-5 */
	115	AM_RANGE(0xffc0,0xffff) AM_READWRITE(peripheral_register_r, peripheral_register_w) /* 1-5 On-chip peripheral registers memory mapped in data space */
116	116	ADDRESS_MAP_END
117	117
118	118
r32760	r32761
288	288	save_item(NAME(m_dsp56k_core.HI.trxh));
289	289	save_item(NAME(m_dsp56k_core.HI.trxl));
290	290	save_item(NAME(m_dsp56k_core.HI.bootstrap_offset));
291
	291
292	292	save_item(NAME(m_dsp56k_core.peripheral_ram));
293	293	save_item(NAME(m_dsp56k_core.program_ram));
294	294
r32760	r32761
514	514	extern CPU_DISASSEMBLE( dsp56k );
515	515	return CPU_DISASSEMBLE_NAME(dsp56k)(this, buffer, pc, oprom, opram, options);
516	516	}
517

trunk/src/emu/cpu/tlcs90/tlcs90.c
r32760	r32761
2415	2415	if ( (m_internal_registers[ T90_TRUN - T90_IOBASE ] & (1 << i)) == 0 )
2416	2416	return;
2417	2417
2418		timer_fired = 0;
	2418	timer_fired = 0;
2419	2419
2420	2420	mode = (m_internal_registers[ T90_TMOD - T90_IOBASE ] >> ((i & ~1) + 2)) & 0x03;
2421	2421	// Match
2422		switch (mode)
2423		{
2424		case 0x02: // 8bit PPG
2425		case 0x03: // 8bit PWM
2426		logerror("CPU Timer %d expired with unhandled mode %d\n", i, mode);
2427		// TODO: hmm...
2428		case 0x00: // 8bit
2429		m_timer_value[i]++;
2430		if ( m_timer_value[i] == m_internal_registers[ T90_TREG0+i - T90_IOBASE ] )
2431		timer_fired = 1;
2432		break;
	2422	switch (mode)
	2423	{
	2424	case 0x02: // 8bit PPG
	2425	case 0x03: // 8bit PWM
	2426	logerror("CPU Timer %d expired with unhandled mode %d\n", i, mode);
	2427	// TODO: hmm...
	2428	case 0x00: // 8bit
	2429	m_timer_value[i]++;
	2430	if ( m_timer_value[i] == m_internal_registers[ T90_TREG0+i - T90_IOBASE ] )
	2431	timer_fired = 1;
	2432	break;
2433	2433
2434		case 0x01: // 16bit
2435		if(i & 1)
2436		break;
2437		m_timer_value[i]++;
2438		if(m_timer_value[i] == 0) m_timer_value[i+1]++;
2439		if(m_timer_value[i+1] == m_internal_registers[ T90_TREG0+i+1 - T90_IOBASE ])
2440		if(m_timer_value[i] == m_internal_registers[ T90_TREG0+i - T90_IOBASE ])
2441		timer_fired = 1;
2442		break;
2443		}
	2434	case 0x01: // 16bit
	2435	if(i & 1)
	2436	break;
	2437	m_timer_value[i]++;
	2438	if(m_timer_value[i] == 0) m_timer_value[i+1]++;
	2439	if(m_timer_value[i+1] == m_internal_registers[ T90_TREG0+i+1 - T90_IOBASE ])
	2440	if(m_timer_value[i] == m_internal_registers[ T90_TREG0+i - T90_IOBASE ])
	2441	timer_fired = 1;
	2442	break;
	2443	}
2444	2444
2445		if(timer_fired) {
2446		// special stuff handling
2447		switch(mode) {
2448		case 0x02: // 8bit PPG
2449		case 0x03: // 8bit PWM
2450		// TODO: hmm...
2451		case 0x00: // 8bit
2452		if(i & 1)
2453		break;
2454		if ( (m_internal_registers[ T90_TCLK - T90_IOBASE ] & (0x0C << (i * 2))) == 0 ) // T0/T1 match signal clocks T1/T3
2455		t90_timer_callback(ptr, i+1);
2456		break;
2457		case 0x01: // 16bit, only can happen for i=0,2
2458		m_timer_value[i+1] = 0;
2459		set_irq_line(INTT0 + i+1, 1);
2460		break;
2461		}
2462		// regular handling
2463		m_timer_value[i] = 0;
2464		set_irq_line(INTT0 + i, 1);
2465		}
	2445	if(timer_fired) {
	2446	// special stuff handling
	2447	switch(mode) {
	2448	case 0x02: // 8bit PPG
	2449	case 0x03: // 8bit PWM
	2450	// TODO: hmm...
	2451	case 0x00: // 8bit
	2452	if(i & 1)
	2453	break;
	2454	if ( (m_internal_registers[ T90_TCLK - T90_IOBASE ] & (0x0C << (i * 2))) == 0 ) // T0/T1 match signal clocks T1/T3
	2455	t90_timer_callback(ptr, i+1);
	2456	break;
	2457	case 0x01: // 16bit, only can happen for i=0,2
	2458	m_timer_value[i+1] = 0;
	2459	set_irq_line(INTT0 + i+1, 1);
	2460	break;
	2461	}
	2462	// regular handling
	2463	m_timer_value[i] = 0;
	2464	set_irq_line(INTT0 + i, 1);
	2465	}
2466	2466	}
2467	2467
2468	2468	TIMER_CALLBACK_MEMBER( tlcs90_device::t90_timer4_callback )

trunk/src/emu/cpu/i86/i186.c
r32760	r32761
594	594	save_item(NAME(m_mem.middle_size));
595	595	save_item(NAME(m_mem.peripheral));
596	596	save_item(NAME(m_reloc));
597
	597
598	598	// zerofill
599	599	memset(m_timer, 0, sizeof(m_timer));
600	600	memset(m_dma, 0, sizeof(m_dma));
601	601	memset(&m_intr, 0, sizeof(intr_state));
602	602	memset(&m_mem, 0, sizeof(mem_state));
603	603	m_reloc = 0;
604
	604
605	605	m_timer[0].int_timer = timer_alloc(TIMER_INT0);
606	606	m_timer[1].int_timer = timer_alloc(TIMER_INT1);
607	607	m_timer[2].int_timer = timer_alloc(TIMER_INT2);
r32760	r32761
633	633	m_intr.poll_status = 0x0000;
634	634	m_intr.ext_state = 0x00;
635	635	m_reloc = 0x20ff;
636
	636
637	637	for (int i = 0; i < ARRAY_LENGTH(m_dma); i++)
638	638	{
639	639	m_dma[i].drq_state = false;
r32760	r32761
1477	1477	WRITE16_MEMBER(i80186_cpu_device::internal_port_w)
1478	1478	{
1479	1479	int which;
1480
	1480
1481	1481	switch (offset)
1482	1482	{
1483	1483	case 0x11:

trunk/src/emu/cpu/tms34010/tms34010.c
r32760	r32761
37	37	, m_program_config("program", ENDIANNESS_LITTLE, 16, 32, 3)
38	38	, m_reset_deferred(FALSE)
39	39	, m_pixclock(0)
40		, m_pixperclock(0)
	40	, m_pixperclock(0)
41	41	, m_output_int_cb(*this)
42	42	{
43	43	}
r32760	r32761
574	574	m_output_int_cb.resolve();
575	575	m_to_shiftreg_cb.bind_relative_to(*owner());
576	576	m_from_shiftreg_cb.bind_relative_to(*owner());
577
	577
578	578	m_external_host_access = FALSE;
579	579
580	580	m_program = &space(AS_PROGRAM);

trunk/src/emu/cpu/tms34010/tms34010.h
r32760	r32761
190	190
191	191	#define MCFG_TMS340X0_HALT_ON_RESET(_value) \
192	192	tms340x0_device::set_halt_on_reset(*device, _value);
193
	193
194	194	#define MCFG_TMS340X0_PIXEL_CLOCK(_value) \
195	195	tms340x0_device::set_pixel_clock(*device, _value);
196
	196
197	197	#define MCFG_TMS340X0_PIXELS_PER_CLOCK(_value) \
198	198	tms340x0_device::set_pixels_per_clock(*device, _value);
199
	199
200	200	typedef device_delegate<void (screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params)> scanline_ind16_cb_delegate;
201	201
202	202	#define TMS340X0_SCANLINE_IND16_CB_MEMBER(_name) void _name(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params)
203
	203
204	204	#define MCFG_TMS340X0_SCANLINE_IND16_CB(_class, _method) \
205		tms340x0_device::set_scanline_ind16_callback(device, scanline_ind16_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class >(owner)));
206
	205	tms340x0_device::set_scanline_ind16_callback(device, scanline_ind16_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class >(owner)));
207	206
	207
208	208	typedef device_delegate<void (screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params)> scanline_rgb32_cb_delegate;
209	209
210	210	#define TMS340X0_SCANLINE_RGB32_CB_MEMBER(_name) void _name(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params)
211	211
212	212	#define MCFG_TMS340X0_SCANLINE_RGB32_CB(_class, _method) \
213		tms340x0_device::set_scanline_rgb32_callback(device, scanline_rgb32_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class >(owner)));
	213	tms340x0_device::set_scanline_rgb32_callback(device, scanline_rgb32_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class >(owner)));
214	214
215
	215
216	216	#define MCFG_TMS340X0_OUTPUT_INT_CB(_devcb) \
217	217	devcb = &tms340x0_device::set_output_int_callback(*device, DEVCB_##_devcb);
218	218
r32760	r32761
220	220	typedef device_delegate<void (address_space &space, offs_t address, UINT16 *shiftreg)> to_shiftreg_cb_delegate;
221	221
222	222	#define TMS340X0_TO_SHIFTREG_CB_MEMBER(_name) void _name(address_space &space, offs_t address, UINT16 *shiftreg)
223
	223
224	224	#define MCFG_TMS340X0_TO_SHIFTREG_CB(_class, _method) \
225		tms340x0_device::set_to_shiftreg_callback(device, to_shiftreg_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class >(owner)));
226
	225	tms340x0_device::set_to_shiftreg_callback(device, to_shiftreg_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class >(owner)));
227	226
	227
228	228	typedef device_delegate<void (address_space &space, offs_t address, UINT16 *shiftreg)> from_shiftreg_cb_delegate;
229	229
230	230	#define TMS340X0_FROM_SHIFTREG_CB_MEMBER(_name) void _name(address_space &space, offs_t address, UINT16 *shiftreg)
231	231
232	232	#define MCFG_TMS340X0_FROM_SHIFTREG_CB(_class, _method) \
233		tms340x0_device::set_from_shiftreg_callback(device, from_shiftreg_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class >(owner)));
	233	tms340x0_device::set_from_shiftreg_callback(device, from_shiftreg_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class >(owner)));
234	234
235
	235
236	236	class tms340x0_device : public cpu_device,
237		public device_video_interface
	237	public device_video_interface
238	238	{
239	239	public:
240	240	// construction/destruction
r32760	r32761
337	337	int m_pixperclock; /* pixels per clock */
338	338	emu_timer *m_scantimer;
339	339	int m_icount;
340
341		scanline_ind16_cb_delegate m_scanline_ind16_cb;
342		scanline_rgb32_cb_delegate m_scanline_rgb32_cb;
	340
	341	scanline_ind16_cb_delegate m_scanline_ind16_cb;
	342	scanline_rgb32_cb_delegate m_scanline_rgb32_cb;
343	343	devcb_write_line m_output_int_cb; /* output interrupt callback */
344	344	to_shiftreg_cb_delegate m_to_shiftreg_cb; /* shift register write */
345	345	from_shiftreg_cb_delegate m_from_shiftreg_cb; /* shift register read */

trunk/src/emu/cpu/tms32031/tms32031.h
r32760	r32761
775	775	devcb_write8 m_xf0_cb;
776	776	devcb_write8 m_xf1_cb;
777	777	devcb_write8 m_iack_cb;
778
	778
779	779	// tables
780	780	static void (tms3203x_device::*const s_tms32031ops[])(UINT32 op);
781	781	static UINT32 (tms3203x_device::*const s_indirect_d[0x20])(UINT32, UINT8);

trunk/src/emu/cpu/rsp/rspdrc.c
r32760	r32761
9029	9029	block->append_comment("%08X: %s", pc, buffer); // comment
9030	9030	#endif
9031	9031	}
9032

trunk/src/emu/cpu/rsp/rsp.c
r32760	r32761
466	466	m_regmap[regnum] = (regnum == 0) ? uml::parameter(0) : uml::parameter::make_memory(&m_rsp_state->r[regnum]);
467	467	}
468	468
469		/*
470		drcbe_info beinfo;
471		m_drcuml->get_backend_info(beinfo);
472		if (beinfo.direct_iregs > 2)
473		{
474		m_regmap[30] = I2;
475		}
476		if (beinfo.direct_iregs > 3)
477		{
478		m_regmap[31] = I3;
479		}
480		if (beinfo.direct_iregs > 4)
481		{
482		m_regmap[2] = I4;
483		}
484		if (beinfo.direct_iregs > 5)
485		{
486		m_regmap[3] = I5;
487		}
488		if (beinfo.direct_iregs > 6)
489		{
490		m_regmap[4] = I6;
491		}
492		*/
	469	/*
	470	drcbe_info beinfo;
	471	m_drcuml->get_backend_info(beinfo);
	472	if (beinfo.direct_iregs > 2)
	473	{
	474	m_regmap[30] = I2;
	475	}
	476	if (beinfo.direct_iregs > 3)
	477	{
	478	m_regmap[31] = I3;
	479	}
	480	if (beinfo.direct_iregs > 4)
	481	{
	482	m_regmap[2] = I4;
	483	}
	484	if (beinfo.direct_iregs > 5)
	485	{
	486	m_regmap[3] = I5;
	487	}
	488	if (beinfo.direct_iregs > 6)
	489	{
	490	m_regmap[4] = I6;
	491	}
	492	*/
493	493
494	494	/* mark the cache dirty so it is updated on next execute */
495	495	m_cache_dirty = TRUE;
r32760	r32761
870	870	}
871	871	if (m_drcfe )
872	872	{
873		auto_free(machine(), m_drcfe);
	873	auto_free(machine(), m_drcfe);
874	874	}
875	875	}
876	876
r32760	r32761
3565	3565
3566	3566	}
3567	3567	}
3568
3569

trunk/src/emu/cpu/sh4/sh4.c
r32760	r32761
3080	3080
3081	3081	inline void sh34_base_device::execute_one_0000(const UINT16 opcode)
3082	3082	{
3083		switch(opcode & 0xff)
3084		{
	3083	switch(opcode & 0xff)
	3084	{
3085	3085	// 0x00
3086	3086	case 0x00: NOP(opcode); break;
3087	3087	case 0x10: NOP(opcode); break;

trunk/src/emu/video/vooddefs.h
r32760	r32761
1726	1726	raster_info rasterizer[MAX_RASTERIZERS]; /* array of rasterizers */
1727	1727	raster_info * raster_hash[RASTER_HASH_SIZE]; /* hash table of rasterizers */
1728	1728
1729		bool send_config;
1730		UINT32 tmu_config;
	1729	bool send_config;
	1730	UINT32 tmu_config;
1731	1731	};
1732	1732
1733	1733
r32760	r32761
3646	3646	/* result in texel */ \
3647	3647	/* note that they set LOD min to 8 to "disable" a TMU */ \
3648	3648	if (TMUS >= 1 && v->tmu[0].lodmin < (8 << 8)) \
3649		{ \
	3649	{ \
3650	3650	if (!v->send_config) \
3651		{ \
	3651	{ \
3652	3652	TEXTURE_PIPELINE(&v->tmu[0], x, dither4, TEXMODE0, texel, \
3653	3653	v->tmu[0].lookup, extra->lodbase0, \
3654	3654	iters0, itert0, iterw0, texel); \
3655		} \
3656		else \
3657		{ \
	3655	} \
	3656	else \
	3657	{ \
3658	3658	texel.u=v->tmu_config; \
3659		} \
3660		} \
	3659	} \
	3660	} \
3661	3661	\
3662	3662	/* colorpath pipeline selects source colors and does blending */ \
3663	3663	CLAMPED_ARGB(iterr, iterg, iterb, itera, FBZCOLORPATH, iterargb); \

trunk/src/emu/video/upd7220.c
r32760	r32761
764	764	UINT8 data = readbyte(addr);
765	765	UINT8 new_pixel = (xi & 8 ? tile_data >> 8 : tile_data & 0xff) & (0x80 >> (xi & 7));
766	766	new_pixel = new_pixel ? (0xff & (0x80 >> (x & 7))) : 0;
767
	767
768	768	switch(m_bitmap_mod)
769	769	{
770	770	case 0: //replace

trunk/src/emu/video/epic12.c
r32760	r32761
41	41	m_bitmaps = auto_bitmap_rgb32_alloc(machine(), 0x2000, 0x1000);
42	42	m_clip = m_bitmaps->cliprect();
43	43	m_clip.set(0, 0x2000-1, 0, 0x1000-1);
44
	44
45	45	m_ram16_copy = auto_alloc_array(machine(), UINT16, m_main_ramsize/2);
46	46
47	47	m_blitter_delay_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(epic12_device::blitter_delay_callback),this));

trunk/src/emu/video/voodoo.c
r32760	r32761
4915	4915	}
4916	4916	}
4917	4917
4918		v->tmu_config = 0x11; // revision 1
	4918	v->tmu_config = 0x11; // revision 1
4919	4919
4920	4920	/* configure type-specific values */
4921	4921	switch (v->type)
r32760	r32761
4969	4969	assert_always(v->cpu != NULL, "Unable to find CPU attached to voodoo");
4970	4970
4971	4971	if (m_tmumem1 != 0)
4972		v->tmu_config \|= 0xc0; // two TMUs
	4972	v->tmu_config \|= 0xc0; // two TMUs
4973	4973
4974	4974	v->chipmask = 0x01;
4975	4975	v->attoseconds_per_cycle = ATTOSECONDS_PER_SECOND / v->freq;

trunk/src/emu/video/315_5124.c
r32760	r32761
677	677	reg_num = data & 0x0f;
678	678	m_reg[reg_num] = m_addr & 0xff;
679	679	//logerror("%s: %s: setting register %x to %02x\n", machine().describe_context(), tag(), reg_num, m_addr & 0xf );
680
	680
681	681	switch (reg_num)
682	682	{
683	683	case 0:

trunk/src/emu/diimage.c
r32760	r32761
1229	1229
1230	1230	if (swinfo_name == swlistdev->list_name())
1231	1231	{
1232		// ad hoc handling for the case path = swlist_name:swinfo_name (e.g.
1233		// gameboy:sml) which is not handled properly by software_name_split
1234		// since the function cannot distinguish between this and the case
	1232	// ad hoc handling for the case path = swlist_name:swinfo_name (e.g.
	1233	// gameboy:sml) which is not handled properly by software_name_split
	1234	// since the function cannot distinguish between this and the case
1235	1235	// path = swinfo_name:swpart_name
1236	1236	software_info *info = swlistdev->find(swpart_name);
1237	1237	if (info != NULL)

trunk/src/emu/machine.c
r32760	r32761
379	379	#endif
380	380
381	381	manager().web()->serve();
382
	382
383	383	// execute CPUs if not paused
384	384	if (!m_paused)
385	385	m_scheduler.timeslice();

trunk/src/emu/sound/samples.c
r32760	r32761
264	264
265	265	// initialize any custom handlers
266	266	m_samples_start_cb.bind_relative_to(*owner());
267
	267
268	268	if (!m_samples_start_cb.isnull())
269	269	m_samples_start_cb();
270	270	}

trunk/src/emu/sound/samples.h
r32760	r32761
23	23
24	24	#define MCFG_SAMPLES_NAMES(_names) \
25	25	samples_device::static_set_samples_names(*device, _names);
26
	26
27	27	typedef device_delegate<void ()> samples_start_cb_delegate;
28	28
29	29	#define SAMPLES_START_CB_MEMBER(_name) void _name()
30
	30
31	31	#define MCFG_SAMPLES_START_CB(_class, _method) \
32	32	samples_device::set_samples_start_callback(device, samples_start_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class >(owner)));
33	33
r32760	r32761
74	74	dynamic_array<INT16> data; // 16-bit signed data
75	75	};
76	76	static bool read_sample(emu_file &file, sample_t &sample);
77
	77
78	78	// interface
79	79	UINT8 m_channels; // number of discrete audio channels needed
80	80	const char const m_names; // array of sample names

trunk/src/emu/sound/ymf278b.c
r32760	r32761
75	75
76	76	// default address map
77	77	static ADDRESS_MAP_START( ymf278b, AS_0, 8, ymf278b_device )
78		AM_RANGE(0x000000, 0x3fffff) AM_ROM
	78	AM_RANGE(0x000000, 0x3fffff) AM_ROM
79	79	ADDRESS_MAP_END
80	80
81	81

trunk/src/emu/sound/k053260.c
r32760	r32761
385	385
386	386	else if (m_start + m_length >= m_device->m_rom_size)
387	387	logerror("K053260: Attempting to play past the end of the ROM ( start = %06x, length = %06x )\n",
388		m_start, m_length);
	388	m_start, m_length);
389	389
390	390	else
391	391	{
r32760	r32761
464	464	if (offs >= m_device->m_rom_size)
465	465	{
466	466	logerror("%s: K053260: Attempting to read past the end of the ROM (offs = %06x, size = %06x)\n",
467		m_device->machine().describe_context(), offs, m_device->m_rom_size);
	467	m_device->machine().describe_context(), offs, m_device->m_rom_size);
468	468	return 0;
469	469	}
470	470

trunk/src/emu/sound/k053260.h
r32760	r32761
60	60	UINT32 m_rom_size;
61	61
62	62	// live state
63		UINT8 m_portdata[4];
	63	UINT8 m_portdata[4];
64	64	UINT8 m_keyon;
65	65	UINT8 m_mode;
66	66

trunk/src/emu/sound/speaker.h
r32760	r32761
26	26	public:
27	27	speaker_sound_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
28	28	~speaker_sound_device() {}
29
	29
30	30	// static configuration
31	31	static void static_set_levels(device_t &device, int num_levels, const INT16 *levels) { downcast<speaker_sound_device &>(device).m_num_levels = num_levels; downcast<speaker_sound_device &>(device).m_levels = levels;}
32	32
r32760	r32761
80	80
81	81	// DC blocker state
82	82	double m_prevx, m_prevy;
83
	83
84	84	int m_num_levels; /* optional: number of levels (if not two) */
85	85	const INT16 m_levels; / optional: pointer to level lookup table */
86	86	};

trunk/src/emu/sound/flt_rc.h
r32760	r32761
73	73
74	74	// static configuration
75	75	static void static_set_rc(device_t &device, int type, double R1, double R2, double R3, double C);
76
	76
77	77	void filter_rc_set_RC(int type, double R1, double R2, double R3, double C);
78	78
79	79	protected:
r32760	r32761
91	91	int m_k;
92	92	int m_memory;
93	93	int m_type;
94		double m_R1;
95		double m_R2;
96		double m_R3;
97		double m_C;
	94	double m_R1;
	95	double m_R2;
	96	double m_R3;
	97	double m_C;
98	98	};
99	99
100	100	extern const device_type FILTER_RC;

trunk/src/emu/sound/zsg2.c
r32760	r32761
142	142	prepare_samples(i);
143	143
144	144	FILE* f;
145
	145
146	146	f = fopen("zoom_samples.bin","wb");
147	147	fwrite(m_mem_copy,1,m_mem_blocks*4,f);
148	148	fclose(f);

trunk/src/emu/bus/chanf/rom.c
r32760	r32761
164	164	m_data0 = m_ram[m_addr] & 1;
165	165	return (m_latch[0] & 0x7f) \| (m_data0 << 7);
166	166	}
167
	167
168	168	return m_latch[0];
169	169	}
170	170	else
r32760	r32761
176	176	if (offset == 0)
177	177	{
178	178	m_latch[0] = data;
179
	179
180	180	m_read_write = BIT(data, 0);
181	181
182		m_addr_latch = (m_addr_latch & 0x3f3) \| (BIT(data, 2) << 2) \| (BIT(data, 1) << 3); // bits 2,3 come from this write!
	182	m_addr_latch = (m_addr_latch & 0x3f3) \| (BIT(data, 2) << 2) \| (BIT(data, 1) << 3); // bits 2,3 come from this write!
183	183	m_addr = m_addr_latch;
184	184
185	185	m_data0 = BIT(data, 3);
r32760	r32761
199	199
200	200	// These are shared among Schach & Multigame cart types (not directly used by base chanf_rom_device)
201	201	UINT8 chanf_rom_device::common_read_3853(UINT32 offset)
202		{
	202	{
203	203	if (offset < m_ram.count())
204	204	return m_ram[offset];
205	205	else
r32760	r32761
207	207	}
208	208
209	209	void chanf_rom_device::common_write_3853(UINT32 offset, UINT8 data)
210		{
	210	{
211	211	if (offset < m_ram.count())
212	212	m_ram[offset] = data;
213	213	}
r32760	r32761
240	240	m_base_bank = data & 0x1f;
241	241	m_half_bank = BIT(data, 5);
242	242	}
243

trunk/src/emu/bus/chanf/slot.c
r32760	r32761
178	178	// we default to "chess" slot because some homebrew programs have been written to run
179	179	// on PCBs with RAM at $2000-$2800 as Saba Schach!
180	180	if (len == 0x40000)
181		m_type = CF_MULTI; // TODO1: differentiate multicart final and earlier from fullpath
	181	m_type = CF_MULTI; // TODO1: differentiate multicart final and earlier from fullpath
182	182	else
183		m_type = CF_CHESS; // TODO2: is there any way to detect Maze and Hangman from fullpath?
	183	m_type = CF_CHESS; // TODO2: is there any way to detect Maze and Hangman from fullpath?
184	184
185	185	m_cart->ram_alloc(0x800);
186	186	}
r32760	r32761
226	226	const char *slot_string = "chess";
227	227	UINT32 len = core_fsize(m_file);
228	228	int type;
229
	229
230	230	if (len == 0x40000)
231	231	type = CF_MULTI;
232	232	else
233		type = CF_CHESS; // is there any way to detect the other carts from fullpath?
234
	233	type = CF_CHESS; // is there any way to detect the other carts from fullpath?
	234
235	235	slot_string = chanf_get_slot(type);
236
	236
237	237	//printf("type: %s\n", slot_string);
238	238	clear();
239
	239
240	240	result.cpy(slot_string);
241	241	return;
242	242	}

trunk/src/emu/bus/chanf/rom.h
r32760	r32761
24	24	UINT8 common_read_3853(UINT32 offset);
25	25	void common_write_2102(UINT32 offset, UINT8 data);
26	26	void common_write_3853(UINT32 offset, UINT8 data);
27
	27
28	28	// reading and writing
29	29	virtual DECLARE_READ8_MEMBER(read_rom);
30	30
31
	31
32	32	protected:
33	33	// used for RAM chip in Hangman & Maze
34		UINT8 m_latch[2]; // PORT A & PORT B
	34	UINT8 m_latch[2]; // PORT A & PORT B
35	35	UINT16 m_addr_latch, m_addr;
36	36	int m_read_write, m_data0;
37	37	};
r32760	r32761
43	43	public:
44	44	// construction/destruction
45	45	chanf_maze_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
46
	46
47	47	// device-level overrides
48	48	virtual void device_start();
49	49	virtual void device_reset();
50
	50
51	51	// reading and writing
52	52	virtual DECLARE_READ8_MEMBER(read_ram) { return common_read_2102(offset); }
53	53	virtual DECLARE_WRITE8_MEMBER(write_ram) { common_write_2102(offset, data); }
r32760	r32761
61	61	public:
62	62	// construction/destruction
63	63	chanf_hangman_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
64
	64
65	65	// device-level overrides
66	66	virtual void device_start();
67	67	virtual void device_reset();
68
	68
69	69	// reading and writing
70	70	virtual DECLARE_READ8_MEMBER(read_ram) { return common_read_2102(offset); }
71	71	virtual DECLARE_WRITE8_MEMBER(write_ram) { common_write_2102(offset, data); }
r32760	r32761
79	79	public:
80	80	// construction/destruction
81	81	chanf_chess_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
82
	82
83	83	// reading and writing
84	84	virtual DECLARE_READ8_MEMBER(read_ram) { return common_read_3853(offset); }
85	85	virtual DECLARE_WRITE8_MEMBER(write_ram) { common_write_3853(offset, data); }
r32760	r32761
93	93	public:
94	94	// construction/destruction
95	95	chanf_multi_old_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
96
	96
97	97	// device-level overrides
98	98	virtual void device_start();
99	99	virtual void device_reset();
100
	100
101	101	// reading and writing
102	102	virtual DECLARE_READ8_MEMBER(read_rom);
103	103	virtual DECLARE_READ8_MEMBER(read_ram) { return common_read_3853(offset); }
r32760	r32761
116	116	public:
117	117	// construction/destruction
118	118	chanf_multi_final_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
119
	119
120	120	// device-level overrides
121	121	virtual void device_start();
122	122	virtual void device_reset();
123
	123
124	124	// reading and writing
125	125	virtual DECLARE_READ8_MEMBER(read_rom);
126	126	virtual DECLARE_READ8_MEMBER(read_ram) { return common_read_3853(offset); }
127	127	virtual DECLARE_WRITE8_MEMBER(write_ram) { common_write_3853(offset, data); }
128	128	virtual DECLARE_WRITE8_MEMBER(write_bank);
129
	129
130	130	private:
131	131	int m_base_bank, m_half_bank;
132	132	};

trunk/src/emu/bus/chanf/slot.h
r32760	r32761
42	42	UINT32 get_rom_size() { return m_rom_size; }
43	43	UINT32 get_ram_size() { return m_ram.count(); }
44	44
45		void save_ram() { device().save_item(NAME(m_ram)); }
	45	void save_ram() { device().save_item(NAME(m_ram)); }
46	46
47	47	protected:
48	48	// internal state
r32760	r32761
74	74
75	75	int get_type() { return m_type; }
76	76
77		void save_ram() { if (m_cart && m_cart->get_ram_size()) m_cart->save_ram(); }
	77	void save_ram() { if (m_cart && m_cart->get_ram_size()) m_cart->save_ram(); }
78	78
79	79	virtual iodevice_t image_type() const { return IO_CARTSLOT; }
80	80	virtual bool is_readable() const { return 1; }
r32760	r32761
115	115
116	116	#define MCFG_CHANNELF_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
117	117	MCFG_DEVICE_ADD(_tag, CHANF_CART_SLOT, 0) \
118		MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
119
	118	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false)
120	119	#endif

trunk/src/emu/bus/vic20/fe3.c
r32760	r32761
11	11
12	12	/*
13	13
14		TODO:
	14	TODO:
15	15
16		- fe3diag register error#2 hp=5592 (same error in VICE)
17		- SD card
18		- RTC
	16	- fe3diag register error#2 hp=5592 (same error in VICE)
	17	- SD card
	18	- RTC
19	19
20	20	*/
21	21
r32760	r32761
32	32	#define ATF1504AS_TAG "ic4"
33	33
34	34	#define REG1_BANK \
35		((m_reg1 & 0x7f) << 15)
	35	((m_reg1 & 0x7f) << 15)
36	36
37	37	#define LORAM_HIDDEN \
38		(m_reg2 & REG2_BLK0)
	38	(m_reg2 & REG2_BLK0)
39	39
40	40	#define BLK1_HIDDEN \
41		(m_reg2 & REG2_BLK1)
	41	(m_reg2 & REG2_BLK1)
42	42
43	43	#define BLK2_HIDDEN \
44		(m_reg2 & REG2_BLK2)
	44	(m_reg2 & REG2_BLK2)
45	45
46	46	#define BLK3_HIDDEN \
47		(m_reg2 & REG2_BLK3)
	47	(m_reg2 & REG2_BLK3)
48	48
49	49	#define BLK5_HIDDEN \
50		(m_reg2 & REG2_BLK5)
	50	(m_reg2 & REG2_BLK5)
51	51
52	52	#define REGISTERS_HIDDEN \
53		((m_lockbit && ((m_reg1 & REG1_MODE_MASK) == REG1_START)) \|\| (m_reg2 & REG2_IO3))
	53	((m_lockbit && ((m_reg1 & REG1_MODE_MASK) == REG1_START)) \|\| (m_reg2 & REG2_IO3))
54	54
55	55
56	56
r32760	r32761
178	178	{
179	179	data = m_ram[get_address(0, 0, offset)];
180	180	}
181
	181
182	182	// read from ROM
183	183	if (!blk1 && !BLK1_HIDDEN)
184	184	{
r32760	r32761
203	203	data = read_register(BIT(offset, 0));
204	204	}
205	205	break;
206
	206
207	207	case REG1_RAM_1:
208	208	// read from RAM bank 0
209	209	if ((!ram1 \|\| !ram2 \|\| !ram3) && !LORAM_HIDDEN)
r32760	r32761
235	235	data = read_register(BIT(offset, 0));
236	236	}
237	237	break;
238
	238
239	239	case REG1_RAM_2:
240	240	// read from RAM bank 0
241	241	if ((!ram1 \|\| !ram2 \|\| !ram3) && !LORAM_HIDDEN)
r32760	r32761
267	267	data = read_register(BIT(offset, 0));
268	268	}
269	269	break;
270
	270
271	271	case REG1_SUPER_RAM:
272	272	// read from RAM bank 0
273	273	if ((!ram1 \|\| !ram2 \|\| !ram3) && !LORAM_HIDDEN)
r32760	r32761
299	299	data = read_register(BIT(offset, 0));
300	300	}
301	301	break;
302
	302
303	303	case REG1_RAM_ROM:
304	304	// read from RAM bank 0
305	305	if ((!ram1 \|\| !ram2 \|\| !ram3) && !LORAM_HIDDEN)
306	306	{
307	307	data = m_ram[get_address(0, 0, offset)];
308	308	}
309
	309
310	310	// read from ROM bank 0 or RAM bank 1
311	311	if (!blk1 && !BLK1_HIDDEN)
312	312	{
r32760	r32761
331	331	data = read_register(BIT(offset, 0));
332	332	}
333	333	break;
334
	334
335	335	case REG1_FLASH:
336	336	// read from RAM bank 0
337	337	if ((!ram1 \|\| !ram2 \|\| !ram3) && !LORAM_HIDDEN)
r32760	r32761
392	392	write_register(BIT(offset, 0), data);
393	393	}
394	394	break;
395
	395
396	396	case REG1_SUPER_ROM:
397	397	// write to RAM bank 0
398	398	if ((!ram1 \|\| !ram2 \|\| !ram3) && !LORAM_HIDDEN)
r32760	r32761
424	424	write_register(BIT(offset, 0), data);
425	425	}
426	426	break;
427
	427
428	428	case REG1_RAM_1:
429	429	// write to RAM bank 0
430	430	if ((!ram1 \|\| !ram2 \|\| !ram3) && !LORAM_HIDDEN && REG1_BLK0)
r32760	r32761
456	456	write_register(BIT(offset, 0), data);
457	457	}
458	458	break;
459
	459
460	460	case REG1_RAM_2:
461	461	// write to RAM bank 0
462	462	if ((!ram1 \|\| !ram2 \|\| !ram3) && !LORAM_HIDDEN && REG1_BLK0)
r32760	r32761
488	488	write_register(BIT(offset, 0), data);
489	489	}
490	490	break;
491
	491
492	492	case REG1_SUPER_RAM:
493	493	// write to RAM bank 0
494	494	if ((!ram1 \|\| !ram2 \|\| !ram3) && !LORAM_HIDDEN)
r32760	r32761
520	520	write_register(BIT(offset, 0), data);
521	521	}
522	522	break;
523
	523
524	524	case REG1_RAM_ROM:
525	525	// write to RAM bank 0
526	526	if ((!ram1 \|\| !ram2 \|\| !ram3) && !LORAM_HIDDEN && REG1_BLK0)
r32760	r32761
552	552	write_register(BIT(offset, 0), data);
553	553	}
554	554	break;
555
	555
556	556	case REG1_FLASH:
557	557	// write to RAM bank 0
558	558	if ((!ram1 \|\| !ram2 \|\| !ram3) && !LORAM_HIDDEN)

trunk/src/emu/bus/vic20/fe3.h
r32760	r32761
27	27	// ======================> vic20_final_expansion_3_t
28	28
29	29	class vic20_final_expansion_3_t : public device_t,
30		public device_vic20_expansion_card_interface
	30	public device_vic20_expansion_card_interface
31	31	{
32	32	public:
33	33	// construction/destruction

trunk/src/emu/bus/gameboy/mbc.h
r32760	r32761
183	183	public:
184	184	// construction/destruction
185	185	gb_rom_188in1_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
186
	186
187	187	// device-level overrides
188	188	virtual void device_start() { shared_start(); save_item(NAME(m_game_base)); };
189	189	virtual void device_reset() { shared_reset(); m_game_base = 0; };
190
	190
191	191	// reading and writing
192	192	virtual DECLARE_READ8_MEMBER(read_rom);
193	193	virtual DECLARE_WRITE8_MEMBER(write_bank);

trunk/src/emu/bus/gameboy/gb_slot.h
r32760	r32761
71	71	void set_has_battery(bool val) { has_battery = val; }
72	72	bool get_has_battery() { return has_battery; }
73	73
74		void save_ram() { device().save_item(NAME(m_ram)); }
75
	74	void save_ram() { device().save_item(NAME(m_ram)); }
	75
76	76	// internal state
77	77	UINT8 *m_rom;
78	78	UINT32 m_rom_size;
r32760	r32761
122	122
123	123	void setup_ram(UINT8 banks);
124	124	void internal_header_logging(UINT8 *ROM, UINT32 len);
125		void save_ram() { if (m_cart && m_cart->get_ram_size()) m_cart->save_ram(); }
126
	125	void save_ram() { if (m_cart && m_cart->get_ram_size()) m_cart->save_ram(); }
	126
127	127	virtual iodevice_t image_type() const { return IO_CARTSLOT; }
128	128	virtual bool is_readable() const { return 1; }
129	129	virtual bool is_writeable() const { return 0; }

trunk/src/emu/bus/sega8/sega8_slot.c
r32760	r32761
873	873	SLOT_INTERFACE_INTERNAL("codemasters", SEGA8_ROM_CODEMASTERS)
874	874	SLOT_INTERFACE_INTERNAL("mgear", SEGA8_ROM_MGEAR)
875	875	SLOT_INTERFACE_END
876

trunk/src/emu/bus/sega8/rom.c
r32760	r32761
752	752	{
753	753	int bank = offset / 0x4000;
754	754
755		return m_rom[m_rom_bank_base[bank] * 0x4000 + (offset & 0x3fff)];
	755	return m_rom[m_rom_bank_base[bank] * 0x4000 + (offset & 0x3fff)];
756	756	}
757	757
758	758

trunk/src/emu/bus/sega8/sega8_slot.h
r32760	r32761
121	121	int verify_cart(UINT8 *magic, int size);
122	122	void set_lphaser_xoffset(UINT8 *rom, int size);
123	123
124		void save_ram() { if (m_cart && m_cart->get_ram_size()) m_cart->save_ram(); }
	124	void save_ram() { if (m_cart && m_cart->get_ram_size()) m_cart->save_ram(); }
125	125
126	126	void set_mandatory(bool val) { m_must_be_loaded = val; }
127	127	void set_intf(const char * interface) { m_interface = interface; }

trunk/src/emu/bus/sega8/mgear.h
r32760	r32761
12	12	public:
13	13	// construction/destruction
14	14	sega8_mgear_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
15
	15
16	16	// device-level overrides
17	17	virtual void device_start();
18	18	virtual void device_reset();
19
	19
20	20	// reading and writing
21	21	virtual DECLARE_READ8_MEMBER(read_cart) { return m_subslot->read_cart(space, offset); }
22	22	virtual DECLARE_WRITE8_MEMBER(write_cart) { m_subslot->write_cart(space, offset, data); }

trunk/src/emu/bus/sega8/ccatch.c
r32760	r32761
1	1	/***********************************************************************************************************
2	2
3	3	SG-1000 Card Catcher emulation
4
	4
5	5	Sega Card Catcher is a passthrough adapter for
6	6	SG-1000 to load games in MyCard format into the
7		main cartslot
	7	main cartslot
8	8
9	9	***********************************************************************************************************/
10	10

trunk/src/emu/bus/a800/a800_slot.h
r32760	r32761
20	20	A800_OSSM091,
21	21	A800_OSS8K,
22	22	A800_PHOENIX,
23		A800_XEGS,
24		A800_BBSB,
	23	A800_XEGS,
	24	A800_BBSB,
25	25	A800_DIAMOND,
26	26	A800_WILLIAMS,
27		A800_EXPRESS,
	27	A800_EXPRESS,
28	28	A800_SPARTADOS,
29	29	A800_BLIZZARD,
30	30	A800_TURBO64,
r32760	r32761
71	71	UINT8 *m_rom;
72	72	UINT32 m_rom_size;
73	73	dynamic_buffer m_ram;
74		dynamic_buffer m_nvram; // HiScore cart can save scores!
	74	dynamic_buffer m_nvram; // HiScore cart can save scores!
75	75	// helpers
76	76	int m_bank_mask;
77	77	};
r32760	r32761
101	101	int get_cart_type() { return m_type; };
102	102	int identify_cart_type(UINT8 *header);
103	103	bool has_cart() { return m_cart != NULL; }
104
	104
105	105	virtual iodevice_t image_type() const { return IO_CARTSLOT; }
106	106	virtual bool is_readable() const { return 1; }
107	107	virtual bool is_writeable() const { return 0; }
r32760	r32761
120	120	virtual DECLARE_READ8_MEMBER(read_d5xx);
121	121	virtual DECLARE_WRITE8_MEMBER(write_80xx);
122	122	virtual DECLARE_WRITE8_MEMBER(write_d5xx);
123
	123
124	124	private:
125	125	device_a800_cart_interface* m_cart;
126	126	int m_type;
r32760	r32761
138	138	// construction/destruction
139	139	a5200_cart_slot_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
140	140	virtual ~a5200_cart_slot_device();
141
	141
142	142	virtual const char *file_extensions() const { return "bin,rom,car,a52"; }
143
	143
144	144	// slot interface overrides
145	145	virtual void get_default_card_software(astring &result);
146	146	};
r32760	r32761
155	155	virtual ~xegs_cart_slot_device();
156	156
157	157	virtual const char *file_extensions() const { return "bin,rom,car"; }
158
	158
159	159	// slot interface overrides
160	160	virtual void get_default_card_software(astring &result);
161	161	};

trunk/src/emu/bus/a800/sparta.h
r32760	r32761
13	13	public:
14	14	// construction/destruction
15	15	a800_rom_spartados_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
16
	16
17	17	// device-level overrides
18	18	virtual void device_start();
19	19	virtual void device_reset();
20
	20
21	21	virtual DECLARE_READ8_MEMBER(read_80xx);
22	22	virtual DECLARE_WRITE8_MEMBER(write_d5xx);
23
	23
24	24	protected:
25	25	int m_bank, m_subslot_enabled;
26	26	};

trunk/src/emu/bus/a800/rom.h
r32760	r32761
31	31	public:
32	32	// construction/destruction
33	33	a800_rom_bbsb_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
34
	34
35	35	// device-level overrides
36	36	virtual void device_start();
37	37	virtual void device_reset();
38
	38
39	39	virtual DECLARE_READ8_MEMBER(read_80xx);
40	40	virtual DECLARE_WRITE8_MEMBER(write_80xx);
41
	41
42	42	protected:
43	43	int m_banks[2];
44	44	};
r32760	r32761
51	51	public:
52	52	// construction/destruction
53	53	a800_rom_williams_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
54
	54
55	55	// device-level overrides
56	56	virtual void device_start();
57	57	virtual void device_reset();
58
	58
59	59	virtual DECLARE_READ8_MEMBER(read_80xx);
60	60	virtual DECLARE_WRITE8_MEMBER(write_d5xx);
61
	61
62	62	protected:
63	63	int m_bank;
64	64	};
r32760	r32761
71	71	public:
72	72	// construction/destruction
73	73	a800_rom_express_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
74
	74
75	75	// device-level overrides
76	76	virtual void device_start();
77	77	virtual void device_reset();
78
	78
79	79	virtual DECLARE_READ8_MEMBER(read_80xx);
80	80	virtual DECLARE_WRITE8_MEMBER(write_d5xx);
81
	81
82	82	protected:
83	83	int m_bank;
84	84	};
r32760	r32761
91	91	public:
92	92	// construction/destruction
93	93	a800_rom_blizzard_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
94
	94
95	95	// device-level overrides
96	96	virtual void device_start();
97	97	virtual void device_reset();
98
	98
99	99	virtual DECLARE_READ8_MEMBER(read_80xx);
100	100	};
101	101
r32760	r32761
107	107	public:
108	108	// construction/destruction
109	109	a800_rom_turbo_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
110
	110
111	111	// device-level overrides
112	112	virtual void device_start();
113	113	virtual void device_reset();
114
	114
115	115	virtual DECLARE_READ8_MEMBER(read_80xx);
116	116	virtual DECLARE_WRITE8_MEMBER(write_d5xx);
117
	117
118	118	protected:
119	119	int m_bank;
120	120	};
r32760	r32761
127	127	public:
128	128	// construction/destruction
129	129	a800_rom_telelink2_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
130
	130
131	131	virtual DECLARE_READ8_MEMBER(read_80xx);
132	132	virtual DECLARE_WRITE8_MEMBER(write_80xx);
133	133	virtual DECLARE_READ8_MEMBER(read_d5xx);
r32760	r32761
142	142	public:
143	143	// construction/destruction
144	144	a800_rom_microcalc_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
145
	145
146	146	// device-level overrides
147	147	virtual void device_start();
148	148	virtual void device_reset();
149
	149
150	150	virtual DECLARE_READ8_MEMBER(read_80xx);
151	151	virtual DECLARE_WRITE8_MEMBER(write_d5xx);
152
	152
153	153	protected:
154	154	int m_bank;
155	155	};
r32760	r32761
162	162	public:
163	163	// construction/destruction
164	164	xegs_rom_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
165
	165
166	166	// device-level overrides
167	167	virtual void device_start();
168	168	virtual void device_reset();
169
	169
170	170	virtual DECLARE_READ8_MEMBER(read_80xx);
171	171	virtual DECLARE_WRITE8_MEMBER(write_d5xx);
172
	172
173	173	protected:
174	174	int m_bank;
175	175	};
r32760	r32761
182	182	public:
183	183	// construction/destruction
184	184	a5200_rom_2chips_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
185
	185
186	186	virtual DECLARE_READ8_MEMBER(read_80xx);
187	187	};
188	188
r32760	r32761
194	194	public:
195	195	// construction/destruction
196	196	a5200_rom_bbsb_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
197
	197
198	198	// device-level overrides
199	199	virtual void device_start();
200	200	virtual void device_reset();
201
	201
202	202	virtual DECLARE_READ8_MEMBER(read_80xx);
203	203	virtual DECLARE_WRITE8_MEMBER(write_80xx);
204
	204
205	205	protected:
206	206	int m_banks[2];
207	207	};

trunk/src/emu/bus/a800/oss.c
r32760	r32761
95	95	-------------------------------------------------*/
96	96
97	97	/*-------------------------------------------------
98
	98
99	99	OSS 8K
100
	100
101	101	This is used by The Writer's Tool only.
102
	102
103	103	-------------------------------------------------*/
104	104
105	105	READ8_MEMBER(a800_rom_oss8k_device::read_80xx)
r32760	r32761
128	128
129	129
130	130	/*-------------------------------------------------
131
	131
132	132	OSS 034M
133
	133
134	134	This apparently comes from a dump with the wrong bank order...
135	135	investigate whether we should remove it!
136
	136
137	137	-------------------------------------------------*/
138	138
139	139	READ8_MEMBER(a800_rom_oss34_device::read_80xx)
r32760	r32761
156	156	break;
157	157	case 2:
158	158	case 6:
159		m_bank = 3; // in this case the ROM gets disabled and 0xff is returned in 0xa000-0xafff
	159	m_bank = 3; // in this case the ROM gets disabled and 0xff is returned in 0xa000-0xafff
160	160	break;
161	161	case 3:
162	162	case 7:
r32760	r32761
173	173
174	174
175	175	/*-------------------------------------------------
176
	176
177	177	OSS 043M
178
	178
179	179	Same as above but with correct bank order
180
	180
181	181	-------------------------------------------------*/
182	182
183	183	READ8_MEMBER(a800_rom_oss43_device::read_80xx)
r32760	r32761
200	200	break;
201	201	case 2:
202	202	case 6:
203		m_bank = 3; // in this case the ROM gets disabled and 0xff is returned in 0xa000-0xafff
	203	m_bank = 3; // in this case the ROM gets disabled and 0xff is returned in 0xa000-0xafff
204	204	break;
205	205	case 3:
206	206	case 7:
r32760	r32761
217	217
218	218
219	219	/*-------------------------------------------------
220
	220
221	221	OSS M091
222
223		Simplified banking system which only uses two
	222
	223	Simplified banking system which only uses two
224	224	address lines (A0 & A3)
225
	225
226	226	-------------------------------------------------*/
227	227
228	228	READ8_MEMBER(a800_rom_oss91_device::read_80xx)
r32760	r32761
250	250	break;
251	251	}
252	252	}
253

trunk/src/emu/bus/a800/a800_carts.h
r32760	r32761
14	14	SLOT_INTERFACE_INTERNAL("a800_8k", A800_ROM)
15	15	SLOT_INTERFACE_INTERNAL("a800_8k_right", A800_ROM)
16	16	SLOT_INTERFACE_INTERNAL("a800_16k", A800_ROM)
17		SLOT_INTERFACE_INTERNAL("a800_phoenix", A800_ROM) // not really emulated at this stage
	17	SLOT_INTERFACE_INTERNAL("a800_phoenix", A800_ROM) // not really emulated at this stage
18	18	SLOT_INTERFACE_INTERNAL("a800_bbsb", A800_ROM_BBSB)
19	19	SLOT_INTERFACE_INTERNAL("a800_oss8k", A800_ROM_OSS8K)
20	20	SLOT_INTERFACE_INTERNAL("a800_oss034m", A800_ROM_OSS34)
r32760	r32761
23	23	SLOT_INTERFACE_INTERNAL("a800_williams", A800_ROM_WILLIAMS)
24	24	SLOT_INTERFACE_INTERNAL("a800_diamond", A800_ROM_EXPRESS)
25	25	SLOT_INTERFACE_INTERNAL("a800_express", A800_ROM_EXPRESS)
26		SLOT_INTERFACE_INTERNAL("a800_sparta", A800_ROM_SPARTADOS) // this is a passthru cart with unemulated (atm) subslot
	26	SLOT_INTERFACE_INTERNAL("a800_sparta", A800_ROM_SPARTADOS) // this is a passthru cart with unemulated (atm) subslot
27	27	SLOT_INTERFACE_INTERNAL("a800_blizzard", A800_ROM)
28	28	SLOT_INTERFACE_INTERNAL("a800_turbo64", A800_ROM_TURBO)
29	29	SLOT_INTERFACE_INTERNAL("a800_turbo128", A800_ROM_TURBO)
30	30	SLOT_INTERFACE_INTERNAL("a800_tlink2", A800_ROM_TELELINK2)
31	31	SLOT_INTERFACE_INTERNAL("a800_sitsa", A800_ROM_MICROCALC)
32		SLOT_INTERFACE_INTERNAL("a800_corina", A800_ROM) // NOT SUPPORTED YET!
	32	SLOT_INTERFACE_INTERNAL("a800_corina", A800_ROM) // NOT SUPPORTED YET!
33	33	SLOT_INTERFACE_INTERNAL("xegs", XEGS_ROM)
34	34	SLOT_INTERFACE_END
35	35

trunk/src/emu/bus/a800/a800_slot.c
r32760	r32761
6	6	Atari 8 bit cart emulation
7	7	(through slot devices)
8	8
9		Emulation of the cartslot(s) for Atari 8bit series of home computers
10
	9	Emulation of the cartslot(s) for Atari 8bit series of home computers
	10
11	11	Accessors to ROM are typically given in the area 0xa000-0xbfff, but some
12	12	carts (and the right slot in A800) maps ROM to 0x8000-0x9fff too
13	13	Bankswitch typically happens by accessing addresses in 0xd500-0xd5ff
14
	14
15	15	Accordingly, this device offers the following handlers
16	16	- read_80xx/write_80xx
17	17	- read_d5xx/write_d5xx
r32760	r32761
67	67	tempstring.cat(A800SLOT_ROM_REGION_TAG);
68	68	m_rom = device().machine().memory().region_alloc(tempstring, size, 1, ENDIANNESS_LITTLE)->base();
69	69	m_rom_size = size;
70
	70
71	71	// setup other helpers
72		m_bank_mask = (size / 0x2000) - 1; // code for XEGS carts makes use of this to simplify banking
	72	m_bank_mask = (size / 0x2000) - 1; // code for XEGS carts makes use of this to simplify banking
73	73	}
74	74	}
75	75
r32760	r32761
243	243	if (m_cart)
244	244	{
245	245	UINT32 len;
246
	246
247	247	if (software_entry() != NULL)
248	248	{
249	249	const char *pcb_name;
250	250	len = get_software_region_length("rom");
251
	251
252	252	m_cart->rom_alloc(len, tag());
253	253	memcpy(m_cart->get_rom_base(), get_software_region("rom"), len);
254
	254
255	255	if ((pcb_name = get_feature("slot")) != NULL)
256	256	m_type = a800_get_pcb_id(pcb_name);
257	257	else
r32760	r32761
267	267	UINT8 header[16];
268	268	fread(header, 0x10);
269	269	m_type = identify_cart_type(header);
270		len -= 0x10; // in identify_cart_type the first 0x10 bytes are read, so we need to adjust here
	270	len -= 0x10; // in identify_cart_type the first 0x10 bytes are read, so we need to adjust here
271	271	}
272		else // otherwise try to guess based on size
	272	else // otherwise try to guess based on size
273	273	{
274	274	if (len == 0x8000)
275	275	m_type = A5200_32K;
r32760	r32761
323	323	// check CART format
324	324	if (strncmp((const char *)header, "CART", 4))
325	325	fatalerror("Invalid header detected!\n");
326
	326
327	327	switch ((header[4] << 24) + (header[5] << 16) + (header[6] << 8) + (header[7] << 0))
328	328	{
329	329	case 1:
r32760	r32761
400	400	osd_printf_info("Cart type \"%d\" is currently unsupported.\n", (header[4] << 24) + (header[5] << 16) + (header[6] << 8) + (header[7] << 0));
401	401	break;
402	402	}
403
	403
404	404	return type;
405	405	}
406	406
r32760	r32761
420	420	// check whether there is an header, to identify the cart type
421	421	if ((len % 0x1000) == 0x10)
422	422	{
423		core_fread(m_file, head, 0x10);
	423	core_fread(m_file, head, 0x10);
424	424	type = identify_cart_type(head);
425	425	}
426		else // otherwise try to guess based on size
	426	else // otherwise try to guess based on size
427	427	{
428	428	if (len == 0x4000)
429	429	type = A800_16K;
r32760	r32761
435	435	osd_printf_info("This game is not designed for A800. You might want to run it in A5200.\n");
436	436
437	437	slot_string = a800_get_slot(type);
438
	438
439	439	clear();
440
	440
441	441	result.cpy(slot_string);
442	442	}
443	443	else
r32760	r32761
453	453	dynamic_buffer head(0x10);
454	454	UINT32 len = core_fsize(m_file);
455	455	int type = A5200_8K;
456
	456
457	457	// check whether there is an header, to identify the cart type
458	458	if ((len % 0x1000) == 0x10)
459	459	{
460		core_fread(m_file, head, 0x10);
	460	core_fread(m_file, head, 0x10);
461	461	type = identify_cart_type(head);
462	462
463	463	astring info;
r32760	r32761
466	466	}
467	467	if (type < A5200_4K)
468	468	osd_printf_info("This game is not designed for A5200. You might want to run it in A800 or A800XL.\n");
469
	469
470	470	slot_string = a800_get_slot(type);
471
	471
472	472	clear();
473
	473
474	474	result.cpy(slot_string);
475	475	}
476	476	else
r32760	r32761
486	486	dynamic_buffer head(0x10);
487	487	UINT32 len = core_fsize(m_file);
488	488	int type = A800_8K;
489
	489
490	490	// check whether there is an header, to identify the cart type
491	491	if ((len % 0x1000) == 0x10)
492	492	{
493		core_fread(m_file, head, 0x10);
	493	core_fread(m_file, head, 0x10);
494	494	type = identify_cart_type(head);
495	495	}
496	496	if (type != A800_XEGS)
r32760	r32761
501	501	else
502	502	osd_printf_info("You might want to run it in A800 or A800XL.\n");
503	503	}
504
	504
505	505	slot_string = a800_get_slot(type);
506
	506
507	507	clear();
508
	508
509	509	result.cpy(slot_string);
510	510	}
511	511	else
r32760	r32761
549	549	if (m_cart)
550	550	m_cart->write_d5xx(space, offset, data, mem_mask);
551	551	}
552

trunk/src/emu/bus/a800/oss.h
r32760	r32761
13	13	public:
14	14	// construction/destruction
15	15	a800_rom_oss8k_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
16
	16
17	17	// device-level overrides
18	18	virtual void device_start();
19	19	virtual void device_reset();
20
	20
21	21	virtual DECLARE_READ8_MEMBER(read_80xx);
22	22	virtual DECLARE_WRITE8_MEMBER(write_d5xx);
23
	23
24	24	protected:
25	25	int m_bank;
26	26	};
r32760	r32761
53	53	public:
54	54	// construction/destruction
55	55	a800_rom_oss43_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
56
	56
57	57	// device-level overrides
58	58	virtual void device_start();
59	59	virtual void device_reset();
60
	60
61	61	virtual DECLARE_READ8_MEMBER(read_80xx);
62	62	virtual DECLARE_WRITE8_MEMBER(write_d5xx);
63
	63
64	64	protected:
65	65	int m_bank;
66	66	};
r32760	r32761
73	73	public:
74	74	// construction/destruction
75	75	a800_rom_oss91_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
76
	76
77	77	// device-level overrides
78	78	virtual void device_start();
79	79	virtual void device_reset();
80	80
81	81	virtual DECLARE_READ8_MEMBER(read_80xx);
82	82	virtual DECLARE_WRITE8_MEMBER(write_d5xx);
83
	83
84	84	protected:
85	85	int m_bank;
86	86	};

trunk/src/emu/bus/a800/sparta.c
r32760	r32761
43	43	-------------------------------------------------*/
44	44
45	45	/*-------------------------------------------------
46
	46
47	47	SpartaDOS 64K carts
48
49		Similar to Express / Diamond carts, because
50		bankswitch is controlled by writing to 7 diff
51		offsets in reverse order, but writes to offsets
	48
	49	Similar to Express / Diamond carts, because
	50	bankswitch is controlled by writing to 7 diff
	51	offsets in reverse order, but writes to offsets
52	52	0x8-0xf also enable/disable subslot
53
	53
54	54	-------------------------------------------------*/
55	55
56	56	READ8_MEMBER(a800_rom_spartados_device::read_80xx)
r32760	r32761
58	58	if (!m_subslot_enabled)
59	59	return m_rom[(offset & 0x1fff) + (m_bank * 0x2000)];
60	60	else
61		return 0xff; // subslot, currently not implemented
	61	return 0xff; // subslot, currently not implemented
62	62	}
63	63
64	64	WRITE8_MEMBER(a800_rom_spartados_device::write_d5xx)
r32760	r32761
69	69	m_bank = (offset ^ 0x07) & 0x0f;
70	70
71	71	}
72

trunk/src/emu/bus/a800/rom.c
r32760	r32761
3	3	/***********************************************************************************************************
4	4
5	5	A800/A5200/XEGS ROM cart emulation
6
	6
7	7	Basic carts work the same (in addition of being mostly compatible) for all these systems
8	8	and thus we deal with them in a single file
9	9
r32760	r32761
196	196	/*-------------------------------------------------
197	197
198	198	Carts with no bankswitch (8K, 16K)
199
	199
200	200	The cart accessors are mapped in the correct
201	201	range at driver start
202	202
r32760	r32761
210	210
211	211
212	212	/*-------------------------------------------------
213
	213
214	214	Bounty Bob Strikes Back! cart (40K)
215
	215
216	216	Area 0xa000-0xbfff always point to last 8K bank
217		Areas 0x8000-0x8fff and 0x9000-0x9fff are
	217	Areas 0x8000-0x8fff and 0x9000-0x9fff are
218	218	separate banks of 4K mapped either in the first
219	219	16K chunk or in the second 16K chunk
220		Bankswitch is controlled by data written in
	220	Bankswitch is controlled by data written in
221	221	0x8000-0x8fff and 0x9000-0x9fff respectively
222	222
223	223	-------------------------------------------------*/
r32760	r32761
240	240	}
241	241
242	242	/*-------------------------------------------------
243
	243
244	244	XEGS carts (32K, 64K or 128K)
245
246		Bankswitch is controlled by data written in
	245
	246	Bankswitch is controlled by data written in
247	247	0xd500-0xd5ff
248
	248
249	249	-------------------------------------------------*/
250	250
251	251	READ8_MEMBER(xegs_rom_device::read_80xx)
r32760	r32761
253	253	if (offset < 0x2000)
254	254	return m_rom[(offset & 0x1fff) + (m_bank * 0x2000)];
255	255	else
256		return m_rom[(offset & 0x1fff) + (m_bank_mask * 0x2000)]; // always last 8K bank
257
	256	return m_rom[(offset & 0x1fff) + (m_bank_mask * 0x2000)]; // always last 8K bank
	257
258	258	}
259	259
260	260	WRITE8_MEMBER(xegs_rom_device::write_d5xx)
r32760	r32761
264	264
265	265
266	266	/*-------------------------------------------------
267
	267
268	268	Williams 64K
269
	269
270	270	The rom is accessed in 8K chunks at 0xa000-0xbfff
271	271	Bankswitch is controlled by writing to 7 diff
272		offsets (their location varies with the cart type):
273		offs 0 points to bank 0, offs 1 points to bank 1,
274		and so on... the rom can be disabled by writing to
	272	offsets (their location varies with the cart type):
	273	offs 0 points to bank 0, offs 1 points to bank 1,
	274	and so on... the rom can be disabled by writing to
275	275	the offsets 0x8-0xf of the same range as the bankswitch
276
	276
277	277	-------------------------------------------------*/
278	278
279	279	READ8_MEMBER(a800_rom_williams_device::read_80xx)
r32760	r32761
287	287	}
288	288
289	289	/*-------------------------------------------------
290
	290
291	291	Express 64K / Diamond 64K carts
292
	292
293	293	The rom is accessed in 8K chunks at 0xa000-0xbfff
294		Bankswitch is the same as above, but writes trigger
295		banks in reverse order: offs 7 points to bank 0, offs 6
	294	Bankswitch is the same as above, but writes trigger
	295	banks in reverse order: offs 7 points to bank 0, offs 6
296	296	points to bank 1, and so on... the rom can be disabled
297	297	by writing to the offsets 0x8-0xf of the same range
298	298	as the bankswitch
299
	299
300	300	-------------------------------------------------*/
301	301
302	302	READ8_MEMBER(a800_rom_express_device::read_80xx)
r32760	r32761
311	311
312	312
313	313	/*-------------------------------------------------
314
	314
315	315	Turbosoft 64K / 128K
316
317
	316
	317
318	318	-------------------------------------------------*/
319	319
320	320	READ8_MEMBER(a800_rom_turbo_device::read_80xx)
r32760	r32761
329	329
330	330
331	331	/*-------------------------------------------------
332
	332
333	333	Telelink II
334
335
	334
	335
336	336	-------------------------------------------------*/
337	337
338	338	READ8_MEMBER(a800_rom_telelink2_device::read_80xx)
r32760	r32761
347	347
348	348	WRITE8_MEMBER(a800_rom_telelink2_device::write_80xx)
349	349	{
350		m_nvram[offset & 0xff] = data \| 0xf0; // low 4bits only
	350	m_nvram[offset & 0xff] = data \| 0xf0; // low 4bits only
351	351	}
352	352
353	353	READ8_MEMBER(a800_rom_telelink2_device::read_d5xx)
r32760	r32761
364	364
365	365
366	366	/*-------------------------------------------------
367
	367
368	368	SITSA Microcalc
369
370
	369
	370
371	371	-------------------------------------------------*/
372	372
373	373	READ8_MEMBER(a800_rom_microcalc_device::read_80xx)
r32760	r32761
386	386
387	387
388	388	/*-------------------------------------------------
389
	389
390	390	Carts with no bankswitch (4K, 8K, 16K, 32K)
391
	391
392	392	Same as base carts above
393
	393
394	394	-------------------------------------------------*/
395	395
396	396	/*-------------------------------------------------
397
	397
398	398	Carts with 2x8K (16K) with A13 line not connected
399
	399
400	400	Range 0x4000-0x7fff contains two copies of the low
401	401	8K, range 0x8000-0xbfff contains two copies of the
402	402	high 8K
403
	403
404	404	-------------------------------------------------*/
405	405
406	406	READ8_MEMBER(a5200_rom_2chips_device::read_80xx)
r32760	r32761
413	413
414	414
415	415	/*-------------------------------------------------
416
	416
417	417	Bounty Bob Strikes Back! cart (40K)
418
	418
419	419	Similar to the A800 version, but:
420	420	Area 0x8000-0xbfff always point to last 8K bank
421	421	(repeated twice)
422		Areas 0x4000-0x4fff and 0x5000-0x5fff are
	422	Areas 0x4000-0x4fff and 0x5000-0x5fff are
423	423	separate banks of 4K mapped either in the first
424	424	16K chunk or in the second 16K chunk
425		Bankswitch is controlled by data written in
	425	Bankswitch is controlled by data written in
426	426	0x4000-0x4fff and 0x5000-0x5fff respectively
427
	427
428	428	-------------------------------------------------*/
429	429
430	430	READ8_MEMBER(a5200_rom_bbsb_device::read_80xx)
r32760	r32761
445	445	if (addr >= 0xff6 && addr <= 0xff9)
446	446	m_banks[BIT(offset, 12)] = (addr - 0xff6);
447	447	}
448

trunk/src/emu/bus/vc4000/rom.c
r32760	r32761
10	10
11	11
12	12	/* Game List and Emulation Status
13
	13
14	14	When you load a game it will normally appear to be unresponsive. Most carts contain a number of variants
15	15	of each game (e.g. Difficulty, Player1 vs Player2 or Player1 vs Computer, etc).
16
	16
17	17	Press F2 (if needed) to select which game variant you would like to play. The variant number will increment
18	18	on-screen. When you've made your choice, press F1 to start. The main keys are unlabelled, because an overlay
19	19	is provided with each cart. See below for a guide. You need to read the instructions that come with each game.
20
	20
21	21	In some games, the joystick is used like 4 buttons, and other games like a paddle. The two modes are
22	22	incompatible when using a keyboard. Therefore (in the emulation) a config dipswitch is used. The preferred
23	23	setting is listed below.
24
	24
25	25	(AC = Auto-centre, NAC = no auto-centre, 90 = turn controller 90 degrees).
26
	26
27	27	The list is rather incomplete, information will be added as it becomes available.
28
	28
29	29	The game names and numbers were obtained from the Amigan Software site.
30
	30
31	31	Cart Num Name
32	32	----------------------------------------------
33	33	1. Grand Prix / Car Races / Autosport / Motor Racing / Road Race
34	34	Config: Paddle, NAC
35	35	Status: Working
36	36	Controls: Left-Right: Steer; Up: Accelerate
37
	37
38	38	2. Black Jack
39	39	Status: Not working (some digits missing; indicator missing; dealer's cards missing)
40	40	Controls: set bet with S and D; A to deal; 1 to hit, 2 to stay; Q accept insurance, E to decline; double-up (unknown key)
41	41	Indicator: E make a bet then deal; I choose insurance; - you lost; + you won; X hit or stay
42
	42
43	43	3. Olympics / Paddle Games / Bat & Ball / Pro Sport 60 / Sportsworld
44	44	Config: Paddle, NAC
45	45	Status: Working
46
	46
47	47	4. Tank Battle / Combat
48	48	Config: Button, 90
49	49	Status: Working
50	50	Controls: Left-Right: Steer; Up: Accelerate; Fire: Shoot
51
	51
52	52	5. Maths 1
53	53	Status: Working
54	54	Controls: Z difficulty; X = addition or subtraction; C ask question; A=1;S=2;D=3;Q=4;W=5;E=6;1=7;2=8;3=9;0=0; C enter
55
	55
56	56	6. Maths 2
57	57	Status: Not working
58	58	Controls: Same as above.
59
	59
60	60	7. Air Sea Attack / Air Sea Battle
61	61	Config: Button, 90
62	62	Status: Working
63	63	Controls: Left-Right: Move; Fire: Shoot
64
	64
65	65	8. Treasure Hunt / Capture the Flag / Concentration / Memory Match
66	66	Config: Buttons
67	67	Status: Working
68
	68
69	69	9. Labyrinth / Maze / Intelligence 1
70	70	Config: Buttons
71	71	Status: Working
72
	72
73	73	10. Winter Sports
74	74	Notes: Background colours should be Cyan and White instead of Red and Black
75
	75
76	76	11. Hippodrome / Horse Race
77
	77
78	78	12. Hunting / Shooting Gallery
79
	79
80	80	13. Chess 1
81	81	Status: Can't see what you're typing, wrong colours
82
	82
83	83	14. Moto-cros
84
	84
85	85	15. Four in a row / Intelligence 2
86	86	Config: Buttons
87	87	Status: Working
88	88	Notes: Seems the unused squares should be black. The screen jumps about while the computer is "thinking".
89
	89
90	90	16. Code Breaker / Master Mind / Intelligence 3 / Challenge
91
	91
92	92	17. Circus
93	93	STatus: severe gfx issues
94
	94
95	95	18. Boxing / Prize Fight
96
	96
97	97	19. Outer Space / Spacewar / Space Attack / Outer Space Combat
98
	98
99	99	20. Melody Simon / Musical Memory / Follow the Leader / Musical Games / Electronic Music / Face the Music
100
	100
101	101	21. Capture / Othello / Reversi / Attack / Intelligence 4
102	102	Config: Buttons
103	103	Status: Working
104	104	Notes: Seems the unused squares should be black
105
	105
106	106	22. Chess 2
107	107	Status: Can't see what you're typing, wrong colours
108
	108
109	109	23. Pinball / Flipper / Arcade
110	110	Status: gfx issues
111
	111
112	112	24. Soccer
113
	113
114	114	25. Bowling / NinePins
115	115	Config: Paddle, rotated 90 degrees, up/down autocentre, left-right does not
116	116	Status: Working
117
	117
118	118	26. Draughts
119
	119
120	120	27. Golf
121	121	Status: gfx issues
122
	122
123	123	28. Cockpit
124	124	Status: gfx issues
125
	125
126	126	29. Metropolis / Hangman
127	127	Status: gfx issues
128
	128
129	129	30. Solitaire
130
	130
131	131	31. Casino
132	132	Status: gfx issues, items missing and unplayable
133	133	Controls: 1 or 3=START; q=GO; E=STOP; D=$; Z=^; X=tens; C=units
134
	134
135	135	32. Invaders / Alien Invasion / Earth Invasion
136	136	Status: Works
137	137	Config: Buttons
138
	138
139	139	33. Super Invaders
140	140	Status: Stars are missing, colours are wrong
141	141	Config: Buttons (90)
142
	142
143	143	36. BackGammon
144	144	Status: Not all counters are visible, Dice & game number not visible.
145	145	Controls: Fire=Exec; 1=D+; 3=D-; Q,W,E=4,5,6; A,S,D=1,2,3; Z=CL; X=STOP; C=SET
146
	146
147	147	37. Monster Man / Spider's Web
148	148	Status: Works
149	149	Config: Buttons
150
	150
151	151	38. Hyperspace
152	152	Status: Works
153	153	Config: Buttons (90)
154	154	Controls: 3 - status button; Q,W,E,A,S,D,Z,X,C selects which galaxy to visit
155
156
	155
	156
157	157	40. Super Space
158	158	Status: Works, some small gfx issues near the bottom
159	159	Config: Buttons
160
161
162
	160
	161
	162
163	163	Acetronic: (dumps are compatible)
164	164	------------
165
	165
166	166	* Shooting Gallery
167	167	Status: works but screen flickers
168	168	Config: Buttons
169
	169
170	170	* Planet Defender
171	171	Status: Works
172	172	Config: Paddle (NAC)
173
	173
174	174	* Laser Attack
175	175	Status: Works
176	176	Config: Buttons
177
178
179
	177
	178
	179
180	180	Public Domain: (written for emulators, may not work on real hardware)
181	181	---------------
182	182	* Picture (no controls) - works

trunk/src/emu/bus/vc4000/slot.c
r32760	r32761
169	169	seterror(IMAGE_ERROR_UNSPECIFIED, "Image extends beyond the expected size for a VC4000 cart");
170	170	return IMAGE_INIT_FAIL;
171	171	}
172
	172
173	173	m_cart->rom_alloc(size, tag());
174
	174
175	175	if (software_entry() == NULL)
176	176	fread(m_cart->get_rom_base(), size);
177	177	else
r32760	r32761
236	236	type = VC4000_CHESS2;
237	237	else if (size > 0x0800) // some 4k roms have 1k of mirrored ram
238	238	type = VC4000_RAM1K;
239
	239
240	240	slot_string = vc4000_get_slot(type);
241	241
242	242	//printf("type: %s\n", slot_string);
r32760	r32761
294	294	if (m_cart)
295	295	m_cart->write_ram(space, offset, data);
296	296	}
297
298

trunk/src/emu/bus/vc4000/rom.h
r32760	r32761
31	31	public:
32	32	// construction/destruction
33	33	vc4000_ram1k_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
34
	34
35	35	// reading and writing
36	36	virtual DECLARE_READ8_MEMBER(read_ram);
37	37	virtual DECLARE_WRITE8_MEMBER(write_ram);
r32760	r32761
44	44	public:
45	45	// construction/destruction
46	46	vc4000_chess2_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
47
	47
48	48	// reading and writing
49	49	virtual DECLARE_READ8_MEMBER(extra_rom);
50	50	virtual DECLARE_READ8_MEMBER(read_ram);

trunk/src/emu/bus/vc4000/slot.h
r32760	r32761
39	39	UINT32 get_rom_size() { return m_rom_size; }
40	40	UINT32 get_ram_size() { return m_ram.count(); }
41	41
42		void save_ram() { device().save_item(NAME(m_ram)); }
	42	void save_ram() { device().save_item(NAME(m_ram)); }
43	43
44	44	protected:
45	45	// internal state
r32760	r32761
71	71
72	72	int get_type() { return m_type; }
73	73
74		void save_ram() { if (m_cart && m_cart->get_ram_size()) m_cart->save_ram(); }
	74	void save_ram() { if (m_cart && m_cart->get_ram_size()) m_cart->save_ram(); }
75	75
76	76	virtual iodevice_t image_type() const { return IO_CARTSLOT; }
77	77	virtual bool is_readable() const { return 1; }
r32760	r32761
112	112
113	113	#define MCFG_VC4000_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
114	114	MCFG_DEVICE_ADD(_tag, VC4000_CART_SLOT, 0) \
115		MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
116
	115	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false)
117	116	#endif

trunk/src/emu/bus/vboy/slot.c
r32760	r32761
151	151	if (slot_list[i].pcb_id == type)
152	152	return slot_list[i].slot_option;
153	153	}
154
	154
155	155	return "vb_rom";
156	156	}
157	157	#endif
r32760	r32761
179	179	m_cart->rom_alloc(0x200000, tag());
180	180	if (has_eeprom)
181	181	m_cart->eeprom_alloc(get_software_region_length("eeprom"));
182
	182
183	183	ROM = (UINT8 *)m_cart->get_rom_base();
184	184
185	185	if (software_entry() == NULL)
r32760	r32761
190	190	if (len < 0x080000) { memcpy(ROM + 0x040000, ROM, 0x040000); }
191	191	if (len < 0x100000) { memcpy(ROM + 0x080000, ROM, 0x080000); }
192	192	if (len < 0x200000) { memcpy(ROM + 0x100000, ROM, 0x100000); }
193
	193
194	194	if (software_entry() == NULL)
195	195	m_type = vboy_get_pcb_id("vb_rom");
196	196	else

trunk/src/emu/bus/vboy/rom.h
r32760	r32761
15	15	// construction/destruction
16	16	vboy_rom_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source);
17	17	vboy_rom_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
18
	18
19	19	// device-level overrides
20	20	virtual void device_start() {}
21
	21
22	22	// reading and writing
23	23	virtual DECLARE_READ32_MEMBER(read_cart);
24	24	};

trunk/src/emu/bus/vboy/slot.h
r32760	r32761
37	37	UINT32 get_rom_size() { return m_rom_size; }
38	38	UINT32 get_eeprom_size() { return m_eeprom.count(); }
39	39
40		void save_eeprom() { device().save_item(NAME(m_eeprom)); }
	40	void save_eeprom() { device().save_item(NAME(m_eeprom)); }
41	41
42	42	protected:
43	43	// internal state
r32760	r32761
71	71	int get_type() { return m_type; }
72	72	int get_cart_type(UINT8 *ROM, UINT32 len);
73	73
74		void save_eeprom() { if (m_cart && m_cart->get_eeprom_size()) m_cart->save_eeprom(); }
	74	void save_eeprom() { if (m_cart && m_cart->get_eeprom_size()) m_cart->save_eeprom(); }
75	75
76	76	virtual iodevice_t image_type() const { return IO_CARTSLOT; }
77	77	virtual bool is_readable() const { return 1; }
r32760	r32761
111	111
112	112	#define MCFG_VBOY_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
113	113	MCFG_DEVICE_ADD(_tag, VBOY_CART_SLOT, 0) \
114		MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
115
	114	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false)
116	115	#endif

trunk/src/emu/bus/gba/gba_slot.h
r32760	r32761
42	42	UINT32 get_nvram_size() { return m_nvram.bytes(); }
43	43	void set_rom_size(UINT32 val) { m_rom_size = val; }
44	44
45		void save_nvram() { device().save_item(NAME(m_nvram)); }
	45	void save_nvram() { device().save_item(NAME(m_nvram)); }
46	46
47	47	// internal state
48	48	UINT32 *m_rom; // this points to the cart rom region
r32760	r32761
77	77	void setup_ram(UINT8 banks);
78	78	void internal_header_logging(UINT8 *ROM, UINT32 len);
79	79
80		void save_nvram() { if (m_cart && m_cart->get_nvram_size()) m_cart->save_nvram(); }
	80	void save_nvram() { if (m_cart && m_cart->get_nvram_size()) m_cart->save_nvram(); }
81	81
82	82	virtual iodevice_t image_type() const { return IO_CARTSLOT; }
83	83	virtual bool is_readable() const { return 1; }
r32760	r32761
175	175	{ "BR4J", GBA_CHIP_FLASH }, // 1586 - Rockman EXE 4.5 - Real Operation (JPN)
176	176	{ "BG8J", GBA_CHIP_EEPROM_64K }, // 1853 - Ganbare! Dodge Fighters (JPN)
177	177	{ "AROP", GBA_CHIP_EEPROM_4K }, // 1862 - Rocky (EUR)
178		// "A2YE" - 1906 - Top Gun - Combat Zones (USA) - multiple NVRAM chips detected, but none present (protection against emu?)
	178	// "A2YE" - 1906 - Top Gun - Combat Zones (USA) - multiple NVRAM chips detected, but none present (protection against emu?)
179	179	{ "BKMJ", GBA_CHIP_EEPROM_4K }, // 2039 - Kim Possible (JPN)
180	180	{ "BKEJ", GBA_CHIP_EEPROM_64K }, // 2047 - Konjiki no Gashbell - The Card Battle for GBA (JPN)
181	181	{ "BKMP", GBA_CHIP_EEPROM_4K }, // 2297 - Kim Possible 2 - Drakken's Demise (EUR)

trunk/src/emu/bus/vcs/vcs_slot.h
r32760	r32761
18	18	A26_F8SW,
19	19	A26_FA,
20	20	A26_FE,
21		A26_3E, // to test
	21	A26_3E, // to test
22	22	A26_3F,
23	23	A26_E0,
24	24	A26_E7,
r32760	r32761
26	26	A26_DC,
27	27	A26_CV,
28	28	A26_FV,
29		A26_JVP, // to test
	29	A26_JVP, // to test
30	30	A26_32IN1,
31	31	A26_8IN1,
32	32	A26_4IN1,
r32760	r32761
49	49	virtual DECLARE_READ8_MEMBER(read_rom) { return 0xff; }
50	50	// writing to RAM chips (sometimes it is in a different range than write_bank!)
51	51	virtual DECLARE_WRITE8_MEMBER(write_ram) {}
52
	52
53	53	// read/write to bankswitch address
54	54	virtual DECLARE_READ8_MEMBER(read_bank) { return 0xff; }
55	55	virtual DECLARE_WRITE8_MEMBER(write_bank) {}

trunk/src/emu/bus/vcs/rom.h
r32760	r32761
30	30	public:
31	31	// construction/destruction
32	32	a26_rom_4k_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
33
	33
34	34	// reading and writing
35	35
36	36	// accesses just use the 2K ones, since it is just direct access to ROM/RAM
r32760	r32761
46	46	// construction/destruction
47	47	a26_rom_f6_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source);
48	48	a26_rom_f6_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
49
	49
50	50	// device-level overrides
51	51	virtual void device_start();
52	52	virtual void device_reset();
53
	53
54	54	// reading and writing
55	55	virtual DECLARE_READ8_MEMBER(read_rom);
56	56	virtual DECLARE_WRITE8_MEMBER(write_bank);
57	57	virtual DECLARE_DIRECT_UPDATE_MEMBER(cart_opbase);
58
	58
59	59	protected:
60	60	int m_base_bank;
61	61	};
r32760	r32761
68	68	public:
69	69	// construction/destruction
70	70	a26_rom_f4_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
71
	71
72	72	// device-level overrides
73	73	virtual void device_reset();
74
	74
75	75	// reading and writing
76	76	virtual DECLARE_READ8_MEMBER(read_rom);
77	77	virtual DECLARE_WRITE8_MEMBER(write_bank);
r32760	r32761
86	86	// construction/destruction
87	87	a26_rom_f8_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source);
88	88	a26_rom_f8_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
89
	89
90	90	// reading and writing
91	91	virtual DECLARE_READ8_MEMBER(read_rom);
92	92	virtual DECLARE_WRITE8_MEMBER(write_bank);
r32760	r32761
100	100	public:
101	101	// construction/destruction
102	102	a26_rom_f8_sw_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
103
	103
104	104	// device-level overrides
105	105	virtual void device_reset();
106	106	};
r32760	r32761
113	113	public:
114	114	// construction/destruction
115	115	a26_rom_fa_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
116
	116
117	117	// reading and writing
118	118	virtual DECLARE_READ8_MEMBER(read_rom);
119	119	virtual DECLARE_WRITE8_MEMBER(write_bank);
r32760	r32761
127	127	public:
128	128	// construction/destruction
129	129	a26_rom_fe_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
130
	130
131	131	// device-level overrides
132	132	virtual void device_start();
133	133	virtual void device_reset();
134
	134
135	135	// reading and writing
136	136	virtual DECLARE_READ8_MEMBER(read_rom);
137	137	virtual DECLARE_READ8_MEMBER(read_bank);
138	138	virtual DECLARE_WRITE8_MEMBER(write_ram);
139	139	virtual DECLARE_WRITE8_MEMBER(write_bank);
140
	140
141	141	protected:
142	142	int m_base_bank;
143	143	int m_trigger_on_next_access;
r32760	r32761
151	151	public:
152	152	// construction/destruction
153	153	a26_rom_3e_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
154
	154
155	155	// device-level overrides
156	156	virtual void device_start();
157	157	virtual void device_reset();
158
	158
159	159	// reading and writing
160	160	virtual DECLARE_READ8_MEMBER(read_rom);
161	161	virtual DECLARE_WRITE8_MEMBER(write_bank);
162	162	virtual DECLARE_WRITE8_MEMBER(write_ram);
163
	163
164	164	protected:
165	165	int m_num_bank;
166	166	int m_ram_bank;
r32760	r32761
175	175	public:
176	176	// construction/destruction
177	177	a26_rom_3f_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
178
	178
179	179	// device-level overrides
180	180	virtual void device_reset();
181
	181
182	182	// reading and writing
183	183	virtual DECLARE_READ8_MEMBER(read_rom);
184	184	virtual DECLARE_WRITE8_MEMBER(write_bank);
185
	185
186	186	protected:
187	187	int m_num_bank;
188	188	};
r32760	r32761
195	195	public:
196	196	// construction/destruction
197	197	a26_rom_e0_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
198
	198
199	199	// device-level overrides
200	200	virtual void device_start();
201	201	virtual void device_reset();
202
	202
203	203	// reading and writing
204	204	virtual DECLARE_READ8_MEMBER(read_rom);
205	205	virtual DECLARE_WRITE8_MEMBER(write_bank);
206
	206
207	207	protected:
208	208	int m_base_banks[4];
209	209	};
r32760	r32761
216	216	public:
217	217	// construction/destruction
218	218	a26_rom_e7_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
219
	219
220	220	// device-level overrides
221	221	virtual void device_start();
222	222	virtual void device_reset();
223
	223
224	224	// reading and writing
225	225	virtual DECLARE_READ8_MEMBER(read_rom);
226	226	virtual DECLARE_WRITE8_MEMBER(write_bank);
227
	227
228	228	protected:
229	229	int m_ram_bank;
230	230	};
r32760	r32761
237	237	public:
238	238	// construction/destruction
239	239	a26_rom_ua_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
240
	240
241	241	// device-level overrides
242	242	virtual void device_reset();
243
	243
244	244	// reading and writing
245	245	virtual DECLARE_READ8_MEMBER(read_rom);
246	246	virtual DECLARE_READ8_MEMBER(read_bank);
r32760	r32761
255	255	public:
256	256	// construction/destruction
257	257	a26_rom_cv_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
258
	258
259	259	// reading and writing
260	260	virtual DECLARE_READ8_MEMBER(read_rom);
261	261	virtual DECLARE_WRITE8_MEMBER(write_bank);
r32760	r32761
269	269	public:
270	270	// construction/destruction
271	271	a26_rom_dc_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
272
	272
273	273	// reading and writing
274	274	virtual DECLARE_READ8_MEMBER(read_rom);
275	275	virtual DECLARE_WRITE8_MEMBER(write_bank);
r32760	r32761
283	283	public:
284	284	// construction/destruction
285	285	a26_rom_fv_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
286
	286
287	287	// device-level overrides
288	288	virtual void device_start();
289	289	virtual void device_reset();
290
	290
291	291	// reading and writing
292	292	virtual DECLARE_READ8_MEMBER(read_rom);
293	293	virtual DECLARE_WRITE8_MEMBER(write_bank);
294
	294
295	295	protected:
296	296	int m_locked;
297	297	};
r32760	r32761
304	304	public:
305	305	// construction/destruction
306	306	a26_rom_jvp_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
307
	307
308	308	// reading and writing
309	309	virtual DECLARE_READ8_MEMBER(read_rom);
310	310	virtual DECLARE_WRITE8_MEMBER(write_bank);
r32760	r32761
318	318	public:
319	319	// construction/destruction
320	320	a26_rom_4in1_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
321
	321
322	322	// device-level overrides
323	323	virtual void device_reset();
324
	324
325	325	// reading and writing
326	326	virtual DECLARE_READ8_MEMBER(read_rom);
327	327	};
r32760	r32761
334	334	public:
335	335	// construction/destruction
336	336	a26_rom_8in1_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
337
	337
338	338	// device-level overrides
339	339	virtual void device_start();
340	340	virtual void device_reset();
341
	341
342	342	// reading and writing
343	343	virtual DECLARE_READ8_MEMBER(read_rom);
344	344
r32760	r32761
354	354	public:
355	355	// construction/destruction
356	356	a26_rom_32in1_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
357
	357
358	358	// device-level overrides
359	359	virtual void device_reset();
360
	360
361	361	// reading and writing
362	362	virtual DECLARE_READ8_MEMBER(read_rom);
363	363	};

trunk/src/emu/bus/vcs/scharger.h
r32760	r32761
22	22	virtual void device_reset();
23	23
24	24	required_device<cassette_image_device> m_cassette;
25
	25
26	26	// reading and writing
27	27	virtual DECLARE_READ8_MEMBER(read_rom);
28
	28
29	29	private:
30	30	cpu_device *m_maincpu;
31	31	inline UINT8 read_byte(UINT32 offset);
32
	32
33	33	int m_base_banks[2];
34	34	UINT8 m_reg;
35	35	UINT8 m_write_delay, m_ram_write_enabled, m_rom_enabled;

trunk/src/emu/bus/vcs/compumat.c
r32760	r32761
1	1	/***************************************************************************
2	2
3		Atari 2600 cart Spectravideo Compumate (Cart + keyboard!)
	3	Atari 2600 cart Spectravideo Compumate (Cart + keyboard!)
4	4
5	5	This is tricky to implement and it is only a skeleton ATM.
6	6	The device needs to interface with both the TIA and the RIOT.
7
	7
8	8	***************************************************************************/
9	9
10	10

trunk/src/emu/bus/vcs/dpc.c
r32760	r32761
37	37	m_df[data_fetcher].music_mode = 0;
38	38	}
39	39	m_oscillator->adjust(attotime::from_hz(18400), 0, attotime::from_hz(18400));
40
	40
41	41	}
42	42
43	43	void dpc_device::check_flag(UINT8 data_fetcher)
r32760	r32761
60	60	if (data_fetcher > 4 && m_df[data_fetcher].music_mode)
61	61	m_df[data_fetcher].low = m_df[data_fetcher].top;
62	62	}
63
	63
64	64	check_flag(data_fetcher);
65	65	}
66	66
r32760	r32761
149	149	data = m_df[data_fetcher].flag ? 0xff : 0x00;
150	150	break;
151	151	}
152
	152
153	153	if (data_fetcher < 5 \|\| !m_df[data_fetcher].osc_clk)
154	154	{
155	155	decrement_counter(data_fetcher);
r32760	r32761
161	161	WRITE8_MEMBER(dpc_device::write)
162	162	{
163	163	UINT8 data_fetcher = offset & 0x07;
164
	164
165	165	switch (offset & 0x38)
166	166	{
167	167	case 0x00: // Top count
r32760	r32761
235	235	m_base_bank = 0;
236	236	}
237	237
238		void a26_rom_dpc_device::setup_addon_ptr(UINT8 *ptr)
	238	void a26_rom_dpc_device::setup_addon_ptr(UINT8 *ptr)
239	239	{
240	240	m_dpc->set_display_data(ptr);
241	241	}
r32760	r32761
279	279	}
280	280	return address;
281	281	}
282

trunk/src/emu/bus/vcs/compumat.h
r32760	r32761
19	19	virtual void device_start();
20	20	virtual ioport_constructor device_input_ports() const;
21	21	virtual void device_reset();
22
	22
23	23	// reading and writing
24	24	virtual DECLARE_READ8_MEMBER(read_rom);
25
	25
26	26	private:
27	27	};
28	28

trunk/src/emu/bus/vcs/dpc.h
r32760	r32761
19	19	UINT8 osc_clk; /* Only used by data fetchers 5,6, and 7 */
20	20	};
21	21
22		// m_dpc.oscillator = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(a2600_state::modeDPC_timer_callback),this));
	22	// m_dpc.oscillator = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(a2600_state::modeDPC_timer_callback),this));
23	23
24	24	class dpc_device : public device_t
25	25	{
r32760	r32761
74	74	virtual void device_reset();
75	75
76	76	required_device<dpc_device> m_dpc;
77
	77
78	78	// reading and writing
79	79	virtual DECLARE_READ8_MEMBER(read_rom);
80	80	virtual DECLARE_WRITE8_MEMBER(write_bank);
81	81	virtual DECLARE_DIRECT_UPDATE_MEMBER(cart_opbase);
82	82
83	83	virtual void setup_addon_ptr(UINT8 *ptr);
84
	84
85	85	protected:
86		// int m_reset_bank;
	86	// int m_reset_bank;
87	87	};
88	88
89	89

trunk/src/emu/bus/vcs/vcs_slot.c
r32760	r32761
186	186	{
187	187	UINT8 *ROM;
188	188	UINT32 len;
189
	189
190	190	if (software_entry() != NULL)
191	191	len = get_software_region_length("rom");
192	192	else
193	193	len = length();
194
	194
195	195	//printf("Size: 0x%X\n", len);
196
	196
197	197	// check that filesize is among the supported ones
198	198	switch (len)
199	199	{
r32760	r32761
208	208	case 0x10000:
209	209	case 0x80000:
210	210	break;
211
	211
212	212	default:
213	213	seterror(IMAGE_ERROR_UNSUPPORTED, "Invalid rom file size" );
214	214	return IMAGE_INIT_FAIL;
215	215	}
216
	216
217	217	m_cart->rom_alloc(len, tag());
218	218	ROM = m_cart->get_rom_base();
219
	219
220	220	if (software_entry() != NULL)
221	221	{
222	222	const char *pcb_name;
223	223	bool has_ram = get_software_region("ram") ? TRUE : FALSE;
224	224	memcpy(ROM, get_software_region("rom"), len);
225
	225
226	226	if ((pcb_name = get_feature("slot")) != NULL)
227	227	m_type = vcs_get_pcb_id(pcb_name);
228	228	else
r32760	r32761
272	272	{
273	273	fread(ROM, len);
274	274	m_type = identify_cart_type(ROM, len);
275
	275
276	276	// check for Special Chip (128bytes of RAM)
277	277	if (len == 0x2000 \|\| len == 0x4000 \|\| len == 0x8000)
278	278	if (detect_super_chip(ROM, len))
r32760	r32761
284	284	// dig dig, crystal castles, millipede, stargate, defender ii, jr. Pac Man,
285	285	// desert falcon, dark chambers, super football, sprintmaster, fatal run,
286	286	// off the wall, shooting arcade, secret quest, radar lock, save mary, klax
287
	287
288	288	// add CBS RAM+ (256bytes of RAM)
289	289	if (m_type == A26_FA)
290	290	m_cart->ram_alloc(0x100);
r32760	r32761
301	301	else if (m_type == A26_3E)
302	302	m_cart->ram_alloc(0x8000);
303	303	}
304
	304
305	305	//printf("Type: %s\n", vcs_get_slot(m_type));
306
	306
307	307	// pass a pointer to the now allocated ROM for the DPC chip
308	308	if (m_type == A26_DPC)
309	309	m_cart->setup_addon_ptr((UINT8 *)m_cart->get_rom_base() + 0x2000);
310
	310
311	311	return IMAGE_INIT_PASS;
312	312	}
313
	313
314	314	return IMAGE_INIT_PASS;
315	315	}
316	316
r32760	r32761
356	356	}
357	357	}
358	358	}
359		if (numfound)
	359	if (numfound)
360	360	return 1;
361	361	return 0;
362	362	}
r32760	r32761
376	376	}
377	377	}
378	378	}
379		if (numfound)
	379	if (numfound)
380	380	return 1;
381	381	return 0;
382	382	}
r32760	r32761
408	408	}
409	409	}
410	410	}
411		if (numfound)
	411	if (numfound)
412	412	return 1;
413	413	return 0;
414	414	}
r32760	r32761
428	428	}
429	429	}
430	430	}
431		if (numfound)
	431	if (numfound)
432	432	return 1;
433	433	return 0;
434	434	}
r32760	r32761
456	456	}
457	457	}
458	458	}
459		if (numfound)
	459	if (numfound)
460	460	return 1;
461	461	return 0;
462	462	}
r32760	r32761
486	486	}
487	487	}
488	488	}
489		if (numfound)
	489	if (numfound)
490	490	return 1;
491	491	return 0;
492	492	}
r32760	r32761
512	512	}
513	513	}
514	514	}
515		if (numfound)
	515	if (numfound)
516	516	return 1;
517	517	return 0;
518	518	}
r32760	r32761
535	535	}
536	536	}
537	537	}
538		if (numfound)
	538	if (numfound)
539	539	return 1;
540	540	return 0;
541	541	}
r32760	r32761
561	561	}
562	562	}
563	563	}
564		if (numfound)
	564	if (numfound)
565	565	return 1;
566	566	return 0;
567	567	}
r32760	r32761
587	587	}
588	588	}
589	589	}
590		if (numfound)
	590	if (numfound)
591	591	return 1;
592	592	return 0;
593	593	}
r32760	r32761
607	607	}
608	608	}
609	609	}
610		if (numfound)
	610	if (numfound)
611	611	return 1;
612	612	return 0;
613	613	}
r32760	r32761
633	633	}
634	634	}
635	635	}
636		if (numfound == 0x03)
	636	if (numfound == 0x03)
637	637	return 1;
638	638	return 0;
639	639	}
r32760	r32761
653	653	}
654	654	}
655	655	}
656		if (numfound > 1)
	656	if (numfound > 1)
657	657	return 1;
658	658	return 0;
659	659	}
r32760	r32761
705	705	int type = 0xff;
706	706
707	707	// auto-detect bank mode
708		if (detect_modeDC(ROM, len))
	708	if (detect_modeDC(ROM, len))
709	709	type = A26_DC;
710		else if (detect_mode3E(ROM, len))
	710	else if (detect_mode3E(ROM, len))
711	711	type = A26_3E;
712		else if (detect_modeFE(ROM, len))
	712	else if (detect_modeFE(ROM, len))
713	713	type = A26_FE;
714		else if (detect_modeSS(ROM, len))
	714	else if (detect_modeSS(ROM, len))
715	715	type = A26_SS;
716		else if (detect_modeE0(ROM, len))
	716	else if (detect_modeE0(ROM, len))
717	717	type = A26_E0;
718	718	else if (detect_modeCV(ROM, len))
719	719	type = A26_CV;
720		else if (detect_modeFV(ROM, len))
	720	else if (detect_modeFV(ROM, len))
721	721	type = A26_FV;
722		else if (detect_modeJVP(ROM, len))
	722	else if (detect_modeJVP(ROM, len))
723	723	type = A26_JVP;
724		else if (detect_modeUA(ROM, len))
	724	else if (detect_modeUA(ROM, len))
725	725	type = A26_UA;
726		else if (detect_8K_mode3F(ROM, len))
	726	else if (detect_8K_mode3F(ROM, len))
727	727	type = A26_3F;
728		else if (detect_32K_mode3F(ROM, len))
	728	else if (detect_32K_mode3F(ROM, len))
729	729	type = A26_3F;
730		else if (detect_modeE7(ROM, len))
	730	else if (detect_modeE7(ROM, len))
731	731	type = A26_E7;
732	732	else if (detect_snowhite(ROM, len))
733	733	type = A26_F8SW;
734
	734
735	735	// otherwise, choose based on size
736	736	if (type == 0xff)
737	737	{
r32760	r32761
771	771	break;
772	772	}
773	773	}
774
	774
775	775	return type;
776	776	}
777	777
r32760	r32761
787	787	UINT32 len = core_fsize(m_file);
788	788	dynamic_buffer rom(len);
789	789	int type;
790
	790
791	791	core_fread(m_file, rom, len);
792
	792
793	793	type = identify_cart_type(rom, len);
794	794	slot_string = vcs_get_slot(type);
795
	795
796	796	clear();
797
	797
798	798	result.cpy(slot_string);
799	799	}
800	800	else

trunk/src/emu/bus/vcs/rom.c
r32760	r32761
62	62
63	63	a26_rom_f6_device::a26_rom_f6_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source)
64	64	: a26_rom_2k_device(mconfig, type, name, tag, owner, clock, shortname, source),
65		m_base_bank(-1) // set to -1 to help the Xin1 multicart...
	65	m_base_bank(-1) // set to -1 to help the Xin1 multicart...
66	66	{
67	67	}
68	68
69	69	a26_rom_f6_device::a26_rom_f6_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
70	70	: a26_rom_2k_device(mconfig, A26_ROM_F6, "Atari VCS 2600 ROM Carts w/F6 bankswitch", tag, owner, clock, "vcs_f6", __FILE__),
71		m_base_bank(-1) // set to -1 to help the Xin1 multicart...
	71	m_base_bank(-1) // set to -1 to help the Xin1 multicart...
72	72	{
73	73	}
74	74
r32760	r32761
337	337
338	338	/*-------------------------------------------------
339	339	"F4 Bankswitch" Carts:
340		read/write access to 0x1ff4-0x1ffb determines the
	340	read/write access to 0x1ff4-0x1ffb determines the
341	341	4K ROM bank to be read
342	342
343	343	GAMES: Fatal Run
r32760	r32761
350	350	{
351	351	return m_ram[offset & (m_ram.count() - 1)];
352	352	}
353
	353
354	354	// update banks
355	355	if (!space.debugger_access())
356	356	{
r32760	r32761
368	368	break;
369	369	}
370	370	}
371
	371
372	372	return m_rom[offset + (m_base_bank * 0x1000)];
373	373	}
374	374
r32760	r32761
380	380	m_ram[offset & (m_ram.count() - 1)] = data;
381	381	return;
382	382	}
383
	383
384	384	switch (offset)
385	385	{
386	386	case 0x0ff4:
r32760	r32761
401	401
402	402	/*-------------------------------------------------
403	403	"F6 Bankswitch" Carts:
404		read/write access to 0x1ff6-0x1ff9 determines the
	404	read/write access to 0x1ff6-0x1ff9 determines the
405	405	4K ROM bank to be read
406	406
407		GAMES: Atari 16K games, like Crossbow, Crystal
	407	GAMES: Atari 16K games, like Crossbow, Crystal
408	408	Castles and the 2-in-1 carts
409	409
410	410	-------------------------------------------------*/
r32760	r32761
469	469
470	470	/*-------------------------------------------------
471	471	"F8 Bankswitch" Carts:
472		read/write access to 0x1ff8-0x1ff9 determines the
	472	read/write access to 0x1ff8-0x1ff9 determines the
473	473	4K ROM bank to be read
474	474
475	475	GAMES: Atari 8K games, like Asteroids, Battlezone
r32760	r32761
484	484	{
485	485	return m_ram[offset & (m_ram.count() - 1)];
486	486	}
487
	487
488	488	// update banks
489	489	if (!space.debugger_access())
490	490	{
r32760	r32761
496	496	break;
497	497	}
498	498	}
499
	499
500	500	return m_rom[offset + (m_base_bank * 0x1000)];
501	501	}
502	502
r32760	r32761
508	508	m_ram[offset & (m_ram.count() - 1)] = data;
509	509	return;
510	510	}
511
	511
512	512	switch (offset)
513	513	{
514	514	case 0x0ff8:
r32760	r32761
523	523
524	524	/*-------------------------------------------------
525	525	"FA Bankswitch" Carts:
526		read/write access to 0x1ff8-0x1ffa determines the
	526	read/write access to 0x1ff8-0x1ffa determines the
527	527	4K ROM bank to be read
528		These games contained the CBS RAM+ chip (256bytes
	528	These games contained the CBS RAM+ chip (256bytes
529	529	of RAM)
530
531		GAMES: CBS RAM Plus games like Omega Race and Tunnel
	530
	531	GAMES: CBS RAM Plus games like Omega Race and Tunnel
532	532	Runner
533	533
534	534	-------------------------------------------------*/
r32760	r32761
540	540	{
541	541	return m_ram[offset & (m_ram.count() - 1)];
542	542	}
543
	543
544	544	// update banks
545	545	if (!space.debugger_access())
546	546	{
r32760	r32761
553	553	break;
554	554	}
555	555	}
556
	556
557	557	return m_rom[offset + (m_base_bank * 0x1000)];
558	558	}
559	559
r32760	r32761
563	563	if (m_ram && offset < 0x100)
564	564	{
565	565	m_ram[offset & (m_ram.count() - 1)] = data;
566		}
567
	566	}
	567
568	568	switch (offset)
569	569	{
570	570	case 0x0ff8:
r32760	r32761
580	580
581	581	/*-------------------------------------------------
582	582	"FE Bankswitch" Carts:
583		read/write access to 0x01fe-0x1ff determines the
	583	read/write access to 0x01fe-0x1ff determines the
584	584	4K ROM bank to be read
585
	585
586	586	GAMES: Activision 8K games like Decathlon
587	587
588	588	-------------------------------------------------*/
589	589	/*
590
	590
591	591	There seems to be a kind of lag between the writing to address 0x1FE and the
592	592	Activision switcher springing into action. It waits for the next byte to arrive
593	593	on the data bus, which is the new PCH in the case of a JSR, and the PCH of the
594	594	stored PC on the stack in the case of an RTS.
595
	595
596	596	depending on last byte & 0x20 -> 0x00 -> switch to bank #1
597	597	-> 0x20 -> switch to bank #0
598
	598
599	599	*/
600	600
601	601	READ8_MEMBER(a26_rom_fe_device::read_rom)
r32760	r32761
607	607	{
608	608	return m_ram[offset & (m_ram.count() - 1)];
609	609	}
610
	610
611	611	data = m_rom[offset + (m_base_bank * 0x1000)];
612
	612
613	613	if (!space.debugger_access())
614	614	{
615	615	if (m_trigger_on_next_access)
r32760	r32761
618	618	m_trigger_on_next_access = 0;
619	619	}
620	620	}
621
	621
622	622	return data;
623	623	}
624	624
r32760	r32761
634	634	READ8_MEMBER(a26_rom_fe_device::read_bank)
635	635	{
636	636	UINT8 data = space.read_byte(0xfe + offset);
637
	637
638	638	if (!space.debugger_access())
639	639	{
640	640	switch (offset & 1)
r32760	r32761
643	643	// The next byte on the data bus determines which bank to switch to
644	644	m_trigger_on_next_access = 1;
645	645	break;
646
	646
647	647	case 1:
648	648	if (m_trigger_on_next_access)
649	649	{
r32760	r32761
667	667	}
668	668
669	669	/*-------------------------------------------------
670		"3E Bankswitch" Carts:
671		write access to 0x3e determines the 2K ROM bank to
672		be read, write access to 0x3f determines the RAM bank
	670	"3E Bankswitch" Carts:
	671	write access to 0x3e determines the 2K ROM bank to
	672	be read, write access to 0x3f determines the RAM bank
673	673	to be read
674
	674
675	675	GAMES: Boulder Dash (Homebrew)
676	676
677	677	-------------------------------------------------*/
r32760	r32761
680	680	{
681	681	if (m_ram && m_ram_enable && offset < 0x400)
682	682	return m_ram[offset + (m_ram_bank * 0x400)];
683
	683
684	684	if (offset >= 0x800)
685	685	return m_rom[(offset & 0x7ff) + (m_num_bank - 1) * 0x800];
686	686	else
r32760	r32761
709	709
710	710
711	711	/*-------------------------------------------------
712		"3F Bankswitch" Carts:
713		write access to 0x00-0x3f determines the 2K ROM bank
	712	"3F Bankswitch" Carts:
	713	write access to 0x00-0x3f determines the 2K ROM bank
714	714	to be read
715	715
716		GAMES: Tigervision 8K games like Espial and Miner
	716	GAMES: Tigervision 8K games like Espial and Miner
717	717	2049er. Extended version with bankswitch up to 512K
718	718	shall be supported as well (but we lack a test case)
719	719
r32760	r32761
733	733	}
734	734
735	735	/*-------------------------------------------------
736		"E0 Bankswitch" Carts:
737		read/write access to 0x1fe0-0x1ff8 determines the
	736	"E0 Bankswitch" Carts:
	737	read/write access to 0x1fe0-0x1ff8 determines the
738	738	1K ROM bank to be read in each 1K chunk (0x1c00-0x1fff
739	739	always points to the last 1K of the ROM)
740	740
r32760	r32761
769	769	1800-19ff is RAM
770	770	1a00-1fff is fixed to the last 0x600 of ROM
771	771
772		The selectable bank can be ROM (if selected by
773		0x1fe0-0x1fe6 access) or a first 1K of RAM (if
	772	The selectable bank can be ROM (if selected by
	773	0x1fe0-0x1fe6 access) or a first 1K of RAM (if
774	774	selected by 0x1fe7 access).
775		The other 256byte RAM bank can be one of the
	775	The other 256byte RAM bank can be one of the
776	776	four different chunks forming the other 1K of RAM
777	777	(the bank is selected by accessing 0x1fe8-0x1feb)
778	778
779		GAMES: M Network 16K games like Burgertime and
	779	GAMES: M Network 16K games like Burgertime and
780	780	Bump'n Jump
781
	781
782	782	-------------------------------------------------*/
783	783
784	784	READ8_MEMBER(a26_rom_e7_device::read_rom)
r32760	r32761
833	833	}
834	834
835	835	/*-------------------------------------------------
836		"UA Bankswitch" Carts:
837		read/write access to 0x200-0x27f determines the
	836	"UA Bankswitch" Carts:
	837	read/write access to 0x200-0x27f determines the
838	838	4K ROM bank to be read (0x220-0x23f for low 4K,
839	839	0x240-0x27f for high 4K)
840	840
841		GAMES: UA Ltd. 8K games like Funky Flash and
	841	GAMES: UA Ltd. 8K games like Funky Flash and
842	842	Pleaides
843	843
844	844	-------------------------------------------------*/
r32760	r32761
863	863
864	864
865	865	/*-------------------------------------------------
866		Commavid Carts:
	866	Commavid Carts:
867	867	It allows for both ROM and RAM on the cartridge,
868		without using bankswitching. There's 2K of ROM
	868	without using bankswitching. There's 2K of ROM
869	869	and 1K of RAM.
870	870
871	871	GAMES: Magicard and Video Life by Commavid
r32760	r32761
894	894
895	895
896	896	/*-------------------------------------------------
897		Dynacom Megaboy Carts (aka "F0 Banswitch"):
898		read/write access to 0x1ff0 determines the 4K ROM
	897	Dynacom Megaboy Carts (aka "F0 Banswitch"):
	898	read/write access to 0x1ff0 determines the 4K ROM
899	899	bank to be read (each access increases the bank index
900	900	up to 16, since the cart was 64K wide)
901	901
r32760	r32761
925	925
926	926
927	927	/*-------------------------------------------------
928		"FV Bankswitch" Carts:
929		The first access to 0x1fd0 switch the bank, but
	928	"FV Bankswitch" Carts:
	929	The first access to 0x1fd0 switch the bank, but
930	930	only if pc() & 0x1f00 == 0x1f00!
931	931
932	932	GAMES: Challenge by HES
r32760	r32761
964	964
965	965
966	966	/*-------------------------------------------------
967		"JVP Bankswitch" Carts:
968		read/write access to 0x0fa0-0x0fc0 determines the
	967	"JVP Bankswitch" Carts:
	968	read/write access to 0x0fa0-0x0fc0 determines the
969	969	4K ROM bank to be read (notice that this overlaps
970	970	the RIOT, currently handled in the main driver until
971	971	I can better investigate the behavior)
972
	972
973	973	GAMES: No test case!?!
974
	974
975	975	-------------------------------------------------*/
976	976
977	977	READ8_MEMBER(a26_rom_jvp_device::read_rom)
r32760	r32761
997	997	/*-------------------------------------------------
998	998	4 in 1 Carts (Reset based):
999	999	the 4K bank changes at each reset
1000
	1000
1001	1001	GAMES: 4 in 1 carts
1002
	1002
1003	1003	-------------------------------------------------*/
1004	1004
1005	1005	READ8_MEMBER(a26_rom_4in1_device::read_rom)
r32760	r32761
1012	1012	8 in 1 Carts (Reset based):
1013	1013	the 8K banks change at each reset, and internally
1014	1014	each game runs as a F8-bankswitched cart
1015
	1015
1016	1016	GAMES: 8 in 1 cart
1017
	1017
1018	1018	-------------------------------------------------*/
1019	1019
1020	1020	READ8_MEMBER(a26_rom_8in1_device::read_rom)
r32760	r32761
1029	1029	break;
1030	1030	}
1031	1031	}
1032
	1032
1033	1033	return m_rom[offset + (m_base_bank * 0x1000) + (m_reset_bank * 0x2000)];
1034	1034	}
1035	1035
r32760	r32761
1037	1037	/*-------------------------------------------------
1038	1038	32 in 1 Carts (Reset based):
1039	1039	the 2K banks change at each reset
1040
	1040
1041	1041	GAMES: 32 in 1 cart
1042
	1042
1043	1043	-------------------------------------------------*/
1044	1044
1045	1045	READ8_MEMBER(a26_rom_32in1_device::read_rom)
1046	1046	{
1047	1047	return m_rom[(offset & 0x7ff) + (m_base_bank * 0x800)];
1048	1048	}
1049

trunk/src/emu/bus/vcs/scharger.c
r32760	r32761
2	2
3	3	Atari 2600 cart Starpath Supercharger (Cart + Tape drive!)
4	4
5
6
	5
	6
7	7	From kevtris notes ( http://blog.kevtris.org/blogfiles/Atari%202600%20Mappers.txt ):
8	8
9
	9
10	10	- Control register [0x1ff8]
11
	11
12	12	7 0
13	13	---------
14	14	1FF8: DDDB BBWE
15
	15
16	16	D: write delay (see below)
17	17	B: bankswitching mode (see below)
18	18	W: RAM write enable (1 = enabled, 0 = disabled)
19	19	E: ROM power enable (0 = enabled, 1 = turn off ROM)
20
	20
21	21	- Audio input register [0x1ff9]
22
	22
23	23	7 0
24		---------
	24	---------
25	25	1FF9: 0000 000A
26
	26
27	27	A: Supercharger audio data. 0 = low input, 1 = high input.
28
29
	28
	29
30	30	***************************************************************************/
31	31
32	32
r32760	r32761
83	83	MCFG_CASSETTE_DEFAULT_STATE(CASSETTE_STOPPED \| CASSETTE_MOTOR_ENABLED \| CASSETTE_SPEAKER_ENABLED)
84	84	MCFG_CASSETTE_INTERFACE("a2600_cass")
85	85
86		// MCFG_SOUND_WAVE_ADD(WAVE_TAG, "cassette")
87		// MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
	86	// MCFG_SOUND_WAVE_ADD(WAVE_TAG, "cassette")
	87	// MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
88	88	MACHINE_CONFIG_END
89	89
90	90	machine_config_constructor a26_rom_ss_device::device_mconfig_additions() const
r32760	r32761
109	109	if (space.debugger_access())
110	110	return read_byte(offset);
111	111
112		// Bankswitch
	112	// Bankswitch
113	113	if (offset == 0xff8)
114	114	{
115	115	//logerror("%04X: Access to control register data = %02X\n", m_maincpu->pc(), m_modeSS_byte);
116	116	m_write_delay = m_reg >> 5;
117	117	m_ram_write_enabled = BIT(m_reg, 1);
118	118	m_rom_enabled = !BIT(m_reg, 0);
119
	119
120	120	// compensate time spent in this access to avoid spurious RAM write
121	121	m_byte_started -= 5;
122
	122
123	123	// handle bankswitch
124	124	switch (m_reg & 0x1c)
125	125	{
r32760	r32761
164	164	{
165	165	//logerror("%04X: Cassette port read, tap_val = %f\n", m_maincpu->pc(), tap_val);
166	166	double tap_val = m_cassette->input();
167
	167
168	168	// compensate time spent in this access to avoid spurious RAM write
169	169	m_byte_started -= 5;
170
	170
171	171	if (tap_val < 0)
172	172	return 0x00;
173	173	else
r32760	r32761
181	181	/* Check for dummy read from same address */
182	182	if (m_last_address == offset)
183	183	m_diff_adjust++;
184
	184
185	185	int diff = m_maincpu->total_cycles() - m_byte_started;
186	186	//logerror("%04X: offset = %04X, %d\n", m_maincpu->pc(), offset, diff);
187	187

trunk/src/emu/bus/wswan/slot.h
r32760	r32761
40	40	UINT32 get_rom_size() { return m_rom_size; }
41	41	UINT32 get_nvram_size() { return m_nvram.count(); }
42	42
43		void save_nvram() { device().save_item(NAME(m_nvram)); }
	43	void save_nvram() { device().save_item(NAME(m_nvram)); }
44	44	void set_has_rtc(bool val) { m_has_rtc = val; }
45	45	void set_is_rotated(bool val) { m_is_rotated = val; }
46	46	int get_is_rotated() { return m_is_rotated ? 1 : 0; }
r32760	r32761
81	81	int get_cart_type(UINT8 *ROM, UINT32 len, UINT32 &nvram_len);
82	82	void internal_header_logging(UINT8 *ROM, UINT32 offs, UINT32 len);
83	83
84		void save_nvram() { if (m_cart && m_cart->get_nvram_size()) m_cart->save_nvram(); }
	84	void save_nvram() { if (m_cart && m_cart->get_nvram_size()) m_cart->save_nvram(); }
85	85
86	86	virtual iodevice_t image_type() const { return IO_CARTSLOT; }
87	87	virtual bool is_readable() const { return 1; }
r32760	r32761
125	125
126	126	#define MCFG_WSWAN_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
127	127	MCFG_DEVICE_ADD(_tag, WS_CART_SLOT, 0) \
128		MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
129
	128	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false)
130	129	#endif

trunk/src/emu/bus/wswan/rom.c
r32760	r32761
154	154	m_rtc_second++;
155	155	if ((m_rtc_second & 0x0f) > 9)
156	156	m_rtc_second = (m_rtc_second & 0xf0) + 0x10;
157
	157
158	158	// check for minute passed
159	159	if (m_rtc_second >= 0x60)
160	160	{
r32760	r32761
163	163	if ((m_rtc_minute & 0x0f) > 9)
164	164	m_rtc_minute = (m_rtc_minute & 0xf0) + 0x10;
165	165	}
166
	166
167	167	// check for hour passed
168	168	if (m_rtc_minute >= 0x60)
169	169	{
r32760	r32761
174	174	if (m_rtc_hour == 0x12)
175	175	m_rtc_hour \|= 0x80;
176	176	}
177
	177
178	178	// check for day passed
179	179	if (m_rtc_hour >= 0x24)
180	180	{
r32760	r32761
217	217	case 0x0b: // RTC data
218	218	if (!m_has_rtc)
219	219	break;
220
	220
221	221	if (m_io_regs[0x0a] == 0x95 && (m_rtc_index < 7))
222	222	{
223	223	switch (m_rtc_index)
r32760	r32761
307	307	case 0x0b: // RTC Data
308	308	if (!m_has_rtc)
309	309	break;
310
	310
311	311	if (m_io_regs[0x0a] == 0x94 && m_rtc_index < 7)
312	312	{
313	313	switch (m_rtc_index)
r32760	r32761
339	339	}
340	340
341	341	WRITE8_MEMBER(ws_rom_sram_device::write_io)
342		{
	342	{
343	343	switch (offset)
344	344	{
345	345	case 0x01: // SRAM bank to select
r32760	r32761
354	354	READ8_MEMBER(ws_rom_eeprom_device::read_io)
355	355	{
356	356	UINT8 value = m_io_regs[offset];
357
	357
358	358	switch (offset)
359	359	{
360	360	case 0x04:
r32760	r32761
368	368	value = ws_rom_device::read_io(space, offset);
369	369	break;
370	370	}
371
	371
372	372	return value;
373	373	}
374	374
375	375	WRITE8_MEMBER(ws_rom_eeprom_device::write_io)
376		{
	376	{
377	377	switch (offset)
378	378	{
379	379	case 0x06: /* EEPROM address lower bits port/EEPROM address and command port
380		1KBit EEPROM:
381		Bit 0-5 - EEPROM address bit 1-6
382		Bit 6-7 - Command
383		00 - Extended command address bit 4-5:
384		00 - Write disable
385		01 - Write all
386		10 - Erase all
387		11 - Write enable
388		01 - Write
389		10 - Read
390		11 - Erase
391		16KBit EEPROM:
392		Bit 0-7 - EEPROM address bit 1-8
393		*/
	380	1KBit EEPROM:
	381	Bit 0-5 - EEPROM address bit 1-6
	382	Bit 6-7 - Command
	383	00 - Extended command address bit 4-5:
	384	00 - Write disable
	385	01 - Write all
	386	10 - Erase all
	387	11 - Write enable
	388	01 - Write
	389	10 - Read
	390	11 - Erase
	391	16KBit EEPROM:
	392	Bit 0-7 - EEPROM address bit 1-8
	393	*/
394	394	switch (m_eeprom_mode)
395	395	{
396	396	case EEPROM_1K:
r32760	r32761
412	412	break;
413	413
414	414	case 0x07: /* EEPROM higher bits/command bits port
415		1KBit EEPROM:
416		Bit 0 - Start
417		Bit 1-7 - Unknown
418		16KBit EEPROM:
419		Bit 0-1 - EEPROM address bit 9-10
420		Bit 2-3 - Command
421		00 - Extended command address bit 0-1:
422		00 - Write disable
423		01 - Write all
424		10 - Erase all
425		11 - Write enable
426		01 - Write
427		10 - Read
428		11 - Erase
429		Bit 4 - Start
430		Bit 5-7 - Unknown
431		*/
	415	1KBit EEPROM:
	416	Bit 0 - Start
	417	Bit 1-7 - Unknown
	418	16KBit EEPROM:
	419	Bit 0-1 - EEPROM address bit 9-10
	420	Bit 2-3 - Command
	421	00 - Extended command address bit 0-1:
	422	00 - Write disable
	423	01 - Write all
	424	10 - Erase all
	425	11 - Write enable
	426	01 - Write
	427	10 - Read
	428	11 - Erase
	429	Bit 4 - Start
	430	Bit 5-7 - Unknown
	431	*/
432	432	switch (m_eeprom_mode)
433	433	{
434	434	case EEPROM_1K:
r32760	r32761
450	450	m_eeprom_command = m_eeprom_command & 0x0c;
451	451	m_eeprom_start = (data >> 4) & 0x01;
452	452	break;
453
	453
454	454	default:
455	455	logerror( "Write EEPROM address/command register C7 for unsupported EEPROM type\n" );
456	456	break;
r32760	r32761
458	458	break;
459	459
460	460	case 0x08: /* EEPROM command
461		Bit 0 - Read complete (read only)
462		Bit 1 - Write complete (read only)
463		Bit 2-3 - Unknown
464		Bit 4 - Read
465		Bit 5 - Write
466		Bit 6 - Protect
467		Bit 7 - Initialize
468		*/
469		if (data & 0x80) // Initialize
	461	Bit 0 - Read complete (read only)
	462	Bit 1 - Write complete (read only)
	463	Bit 2-3 - Unknown
	464	Bit 4 - Read
	465	Bit 5 - Write
	466	Bit 6 - Protect
	467	Bit 7 - Initialize
	468	*/
	469	if (data & 0x80) // Initialize
470	470	logerror("Unsupported EEPROM command 'Initialize'\n");
471	471
472		if (data & 0x40) // Protect
473		{
	472	if (data & 0x40) // Protect
	473	{
474	474	switch (m_eeprom_command)
475	475	{
476	476	case 0x00:
r32760	r32761
487	487	}
488	488	}
489	489
490		if (data & 0x20) // Write
	490	if (data & 0x20) // Write
491	491	{
492	492	if (m_eeprom_write_enabled)
493	493	{
r32760	r32761
505	505	}
506	506	}
507	507
508		if (data & 0x10) // Read
	508	if (data & 0x10) // Read
509	509	{
510	510	m_io_regs[0x04] = m_nvram[(m_eeprom_address << 1) + 1];
511	511	m_io_regs[0x05] = m_nvram[m_eeprom_address << 1];

trunk/src/emu/bus/wswan/slot.c
r32760	r32761
167	167	UINT8 *ROM;
168	168	UINT32 size = (software_entry() == NULL) ? length() : get_software_region_length("rom");
169	169	UINT32 nvram_size = 0;
170
	170
171	171	m_cart->rom_alloc(size, tag());
172	172	ROM = m_cart->get_rom_base();
173
	173
174	174	if (software_entry() == NULL)
175	175	fread(ROM, size);
176	176	else
r32760	r32761
261	261	{
262	262	case 0x00:
263	263	break;
264		case 0x01: // SRAM 64Kbit
	264	case 0x01: // SRAM 64Kbit
265	265	type = WS_SRAM;
266	266	nvram_len = 0x2000;
267	267	break;
268		case 0x02: // SRAM 256Kbit
	268	case 0x02: // SRAM 256Kbit
269	269	type = WS_SRAM;
270	270	nvram_len = 0x8000;
271	271	break;
272		case 0x05: // SRAM 512Kbit
	272	case 0x05: // SRAM 512Kbit
273	273	type = WS_SRAM;
274	274	nvram_len = 0x10000;
275	275	break;
276		case 0x03: // SRAM 1Mbit
	276	case 0x03: // SRAM 1Mbit
277	277	type = WS_SRAM;
278	278	nvram_len = 0x20000;
279	279	break;
280		case 0x04: // SRAM 2Mbit
	280	case 0x04: // SRAM 2Mbit
281	281	type = WS_SRAM;
282	282	nvram_len = 0x40000;
283	283	break;
284		case 0x10: // EEPROM 1Kbit
	284	case 0x10: // EEPROM 1Kbit
285	285	type = WS_EEPROM;
286	286	nvram_len = 0x80;
287	287	break;
288		case 0x50: // EEPROM 8Kbit
	288	case 0x50: // EEPROM 8Kbit
289	289	type = WS_EEPROM;
290	290	nvram_len = 0x400;
291	291	break;
292		case 0x20: // EEPROM 16Kbit
	292	case 0x20: // EEPROM 16Kbit
293	293	type = WS_EEPROM;
294	294	nvram_len = 0x800;
295	295	break;
r32760	r32761
298	298	logerror("Unknown RAM size [0x%X]\n", ROM[(chunks - 1) * 0x10000 + 0xfffb]);
299	299	break;
300	300	}
301
	301
302	302	return type;
303	303	}
304	304
r32760	r32761
315	315	dynamic_buffer rom(size);
316	316	int type;
317	317	UINT32 nvram;
318
	318
319	319	core_fread(m_file, rom, size);
320	320
321	321	// nvram size is not really used here, but we set it up nevertheless
r32760	r32761
427	427	int sum = 0, banks = len / 0x10000;
428	428	UINT8 romsize, ramtype, ramsize;
429	429	romsize = ROM[offs + 0xfffa];
430		ramtype = (ROM[offs + 0xfffb] & 0xf0) ? 1 : 0; // 1 = EEPROM, 0 = SRAM
	430	ramtype = (ROM[offs + 0xfffb] & 0xf0) ? 1 : 0; // 1 = EEPROM, 0 = SRAM
431	431	ramsize = ramtype ? ((ROM[offs + 0xfffb] & 0xf0) >> 4) : (ROM[offs + 0xfffb] & 0x0f);
432
433	432
	433
434	434	logerror( "ROM DETAILS\n" );
435	435	logerror( "===========\n\n" );
436	436	logerror("\tDeveloper ID: %X\n", ROM[offs + 0xfff6]);

trunk/src/emu/bus/wswan/rom.h
r32760	r32761
53	53	public:
54	54	// construction/destruction
55	55	ws_rom_sram_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
56
	56
57	57	// device-level overrides
58	58	virtual void device_start();
59	59	virtual void device_reset();
60
	60
61	61	// reading and writing
62	62	virtual DECLARE_READ8_MEMBER(read_ram);
63	63	virtual DECLARE_WRITE8_MEMBER(write_ram);
r32760	r32761
75	75	public:
76	76	// construction/destruction
77	77	ws_rom_eeprom_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
78
	78
79	79	// device-level overrides
80	80	virtual void device_start();
81	81	virtual void device_reset();
82
	82
83	83	// reading and writing
84	84	virtual DECLARE_READ8_MEMBER(read_io);
85	85	virtual DECLARE_WRITE8_MEMBER(write_io);

trunk/src/emu/bus/megadrive/ggenie.c
r32760	r32761
5	5
6	6
7	7	based on Charles MacDonald's docs: http://cgfm2.emuviews.com/txt/genie.txt
8
9	8
	9
10	10	There is an interesting difference between Rev.0 and Rev.A
11		After the codes has been entered, the former just performs
12		a last write to the MODE register (m_gg_regs[0]) which both
13		sets the enable bits for the 6 available cheats (in the low
14		8 bits) and locks the GG so that later reads goes to the
	11	After the codes has been entered, the former just performs
	12	a last write to the MODE register (m_gg_regs[0]) which both
	13	sets the enable bits for the 6 available cheats (in the low
	14	8 bits) and locks the GG so that later reads goes to the
15	15	piggyback cart. The latter revision, instead, performs the
16		same operations in two subsequent 8bit writes, accessing
	16	same operations in two subsequent 8bit writes, accessing
17	17	separately the low and high bits of the register.
18
	18
19	19	***********************************************************************************************************/
20	20
21	21	#include "emu.h"
r32760	r32761
86	86	return m_gg_data[5];
87	87	else
88	88	return m_exp->m_cart->read(space, offset);
89		}
	89	}
90	90	else
91	91	return 0xffff;
92	92	}
r32760	r32761
114	114	else
115	115	{
116	116	m_gg_bypass = 0;
117
	117
118	118	// bit9 set = read goes to ASIC registers
119	119	if (data & 0x200)
120	120	m_reg_enable = 1;
r32760	r32761
122	122	else
123	123	m_reg_enable = 0;
124	124	}
125
	125
126	126	// LOCK bit
127	127	if (data & 0x100)
128	128	{
r32760	r32761
133	133	m_gg_addr[3] = ((m_gg_regs[11] & 0x3f) << 16) \| m_gg_regs[12];
134	134	m_gg_addr[4] = ((m_gg_regs[14] & 0x3f) << 16) \| m_gg_regs[15];
135	135	m_gg_addr[5] = ((m_gg_regs[17] & 0x3f) << 16) \| m_gg_regs[18];
136
	136
137	137	// data
138	138	m_gg_data[0] = m_gg_regs[4];
139	139	m_gg_data[1] = m_gg_regs[7];
r32760	r32761
144	144
145	145	//printf("mode %X\n", data);
146	146	//for (int i = 0; i < 6; i++)
147		// printf("addr %d = 0x%X - data 0x%X\n", i, m_gg_addr[i], m_gg_data[i]);
	147	// printf("addr %d = 0x%X - data 0x%X\n", i, m_gg_addr[i], m_gg_data[i]);
148	148	}
149		}
	149	}
150	150	else if (offset == 1)
151	151	{
152	152	// RESET

trunk/src/emu/bus/centronics/digiblst.h
r32760	r32761
1	1	/*
2	2	* digiblst.h
3	3	*
4		* Digiblaster - a DIY printer port DAC for the Amstrad CPC
5		* Printed in the German magazine CPC Amstrad International issue 8-9/1991
6		* Uses Strobe (inverted on the CPC) for the 8th bit (CPCs only have 7-bit printer ports)
	4	* Digiblaster - a DIY printer port DAC for the Amstrad CPC
	5	* Printed in the German magazine CPC Amstrad International issue 8-9/1991
	6	* Uses Strobe (inverted on the CPC) for the 8th bit (CPCs only have 7-bit printer ports)
7	7	*
8		* Code borrows from the Covox Speech Thing device.
	8	* Code borrows from the Covox Speech Thing device.
9	9	*
10	10	* Created on: 23/08/2014
11	11	*/

trunk/src/emu/bus/snes/snes_slot.h
r32760	r32761
125	125	UINT32 get_rtc_ram_size() { return m_rtc_ram.count(); };
126	126
127	127	void rom_map_setup(UINT32 size);
128		void save_nvram() { device().save_item(NAME(m_nvram)); }
129		void save_rtc_ram() { device().save_item(NAME(m_rtc_ram)); }
	128	void save_nvram() { device().save_item(NAME(m_nvram)); }
	129	void save_rtc_ram() { device().save_item(NAME(m_rtc_ram)); }
130	130
131	131	// internal state
132	132	UINT8 *m_rom;
r32760	r32761
166	166	void setup_nvram();
167	167	void internal_header_logging(UINT8 *ROM, UINT32 len);
168	168
169		void save_ram() { if (m_cart && m_cart->get_nvram_size()) m_cart->save_nvram();
	169	void save_ram() { if (m_cart && m_cart->get_nvram_size()) m_cart->save_nvram();
170	170	if (m_cart && m_cart->get_rtc_ram_size()) m_cart->save_rtc_ram(); }
171	171
172	172	virtual iodevice_t image_type() const { return IO_CARTSLOT; }

trunk/src/emu/bus/a2bus/mouse.c
r32760	r32761
3	3	mouse.c
4	4
5	5	Implemention of the Apple II Mouse Card
6
	6
7	7	Apple II Mouse Interface PCB
8		Apple 1983
	8	Apple 1983
9	9
10		This is a mouse interface for the Apple II
	10	This is a mouse interface for the Apple II
11	11
12		PCB Layout
13		----------
14		apple computer
15		MOUSE INTERFACE
16		670-0030-C (C) 1983
17		Printed on back side - MOUSE INTERFACE 820-0104-B (C) 1983 APPLE COMPUTER
	12	PCB Layout
	13	----------
	14	apple computer
	15	MOUSE INTERFACE
	16	670-0030-C (C) 1983
	17	Printed on back side - MOUSE INTERFACE 820-0104-B (C) 1983 APPLE COMPUTER
18	18	\|-----------------------------------\|
19	19	\| PAL16R4 6821 \|
20	20	\| \|
r32760	r32761
25	25	\|-------------------\| \|-\|
26	26	\|-------------\|
27	27
28		Notes:
29		J1 - 9 pin flat cable with female DB9 connector
30		68705P3 - Motorola MC68705P3 microcontroller (DIP28) labelled '341-0269 (C) APPLE'
31		PCB printed '(C) APPLE 1983 341-0269 or 342-0285'
32		8516 - Fujitsu MB8516 2k x8-bit EPROM (DIP24) labelled '341-0270-C (C) APPLE 1983'
33		PCB printed '(C) APPLE 1983 342-0270'
34		PAL16R4 - MMI PAL16R4ACN (DIP20) marked '341-0268-A'
35		PCB printed '(C) APPLE 1983 342-0268'
36		6821 - AMI 6821 Peripheral Interface Adapter (DIP40)
37		X1/X2 - Jumper pads. X1 is open, X2 is closed.
38
39
	28	Notes:
	29	J1 - 9 pin flat cable with female DB9 connector
	30	68705P3 - Motorola MC68705P3 microcontroller (DIP28) labelled '341-0269 (C) APPLE'
	31	PCB printed '(C) APPLE 1983 341-0269 or 342-0285'
	32	8516 - Fujitsu MB8516 2k x8-bit EPROM (DIP24) labelled '341-0270-C (C) APPLE 1983'
	33	PCB printed '(C) APPLE 1983 342-0270'
	34	PAL16R4 - MMI PAL16R4ACN (DIP20) marked '341-0268-A'
	35	PCB printed '(C) APPLE 1983 342-0268'
	36	6821 - AMI 6821 Peripheral Interface Adapter (DIP40)
	37	X1/X2 - Jumper pads. X1 is open, X2 is closed.
	38
	39
40	40	Hookup notes:
41		PIA port A connects to 68705 port A in its entirety (bi-directional)
42		PIA PB4-PB7 connects to 68705 PC0-3 (bi-directional)
43		PIA PB0 is 'sync latch'
44		PIA PB1 is A8 on the EPROM
45		PIA PB2 is A9 on the EPROM
46		PIA PB3 is A10 on the EPROM
47
48		68705 PB0 is mouse X1
49		68705 PB1 is mouse X0
50		68705 PB2 is mouse Y0
51		68705 PB3 is mouse Y1
52		68705 PB4 and 5 are N/C
53		68705 PB6 is IRQ for the slot
54		68705 PB7 is the mouse button
55
56		68705 is clocked at 2M
57		PIA is clocked at 1M
58
	41	PIA port A connects to 68705 port A in its entirety (bi-directional)
	42	PIA PB4-PB7 connects to 68705 PC0-3 (bi-directional)
	43	PIA PB0 is 'sync latch'
	44	PIA PB1 is A8 on the EPROM
	45	PIA PB2 is A9 on the EPROM
	46	PIA PB3 is A10 on the EPROM
	47
	48	68705 PB0 is mouse X1
	49	68705 PB1 is mouse X0
	50	68705 PB2 is mouse Y0
	51	68705 PB3 is mouse Y1
	52	68705 PB4 and 5 are N/C
	53	68705 PB6 is IRQ for the slot
	54	68705 PB7 is the mouse button
	55
	56	68705 is clocked at 2M
	57	PIA is clocked at 1M
	58
59	59	See the schematic at:
60		http://mirrors.apple2.org.za/Apple%20II%20Documentation%20Project/Interface%20Cards/Digitizers/Apple%20Mouse%20Interface%20Card/Schematics/
61
	60	http://mirrors.apple2.org.za/Apple%20II%20Documentation%20Project/Interface%20Cards/Digitizers/Apple%20Mouse%20Interface%20Card/Schematics/
	61
62	62	*********************************************************************/
63	63
64	64	#include "mouse.h"
r32760	r32761
73	73
74	74	const device_type A2BUS_MOUSE = &device_creator<a2bus_mouse_device>;
75	75
76		#define MOUSE_ROM_REGION "a2mse_rom"
77		#define MOUSE_PIA_TAG "a2mse_pia"
78		#define MOUSE_MCU_TAG "a2mse_mcu"
79		#define MOUSE_MCU_ROM "a2mse_mcurom"
	76	#define MOUSE_ROM_REGION "a2mse_rom"
	77	#define MOUSE_PIA_TAG "a2mse_pia"
	78	#define MOUSE_MCU_TAG "a2mse_mcu"
	79	#define MOUSE_MCU_ROM "a2mse_mcurom"
80	80
81		#define MOUSE_BUTTON_TAG "a2mse_button"
82		#define MOUSE_XAXIS_TAG "a2mse_x"
83		#define MOUSE_YAXIS_TAG "a2mse_y"
	81	#define MOUSE_BUTTON_TAG "a2mse_button"
	82	#define MOUSE_XAXIS_TAG "a2mse_x"
	83	#define MOUSE_YAXIS_TAG "a2mse_y"
84	84
85		#define TIMER_68705 0
86		#define TIMER_QUADRATURE 1
	85	#define TIMER_68705 0
	86	#define TIMER_QUADRATURE 1
87	87
88	88	static ADDRESS_MAP_START( mcu_mem, AS_PROGRAM, 8, a2bus_mouse_device )
89	89	ADDRESS_MAP_GLOBAL_MASK(0x7ff)
r32760	r32761
113	113
114	114	ROM_START( mouse )
115	115	ROM_REGION(0x800, MOUSE_ROM_REGION, 0)
116		ROM_LOAD( "341-0270-c.4b", 0x000000, 0x000800, CRC(0bcd1e8e) SHA1(3a9d881a8a8d30f55b9719aceebbcf717f829d6f) )
	116	ROM_LOAD( "341-0270-c.4b", 0x000000, 0x000800, CRC(0bcd1e8e) SHA1(3a9d881a8a8d30f55b9719aceebbcf717f829d6f) )
117	117
118	118	ROM_REGION(0x800, MOUSE_MCU_ROM, 0)
119		ROM_LOAD( "341-0269.2b", 0x000000, 0x000800, CRC(94067f16) SHA1(3a2baa6648efe4456d3ec3721216e57c64f7acfc) )
	119	ROM_LOAD( "341-0269.2b", 0x000000, 0x000800, CRC(94067f16) SHA1(3a2baa6648efe4456d3ec3721216e57c64f7acfc) )
120	120
121	121	ROM_REGION(0xc00, "pal", 0)
122		ROM_LOAD( "mmi_pal16r4a(jedec).2a", 0x000000, 0x000b04, CRC(1d620ee5) SHA1(5aa9a515c919ff7a18878649cac5d44f0c2abf28) )
123		ROM_LOAD( "mmi_pal16r4a(binary).2a", 0x000000, 0x000100, CRC(1da5c745) SHA1(ba267b69a2fda2a2348b140979ece562411bb37b) )
	122	ROM_LOAD( "mmi_pal16r4a(jedec).2a", 0x000000, 0x000b04, CRC(1d620ee5) SHA1(5aa9a515c919ff7a18878649cac5d44f0c2abf28) )
	123	ROM_LOAD( "mmi_pal16r4a(binary).2a", 0x000000, 0x000100, CRC(1da5c745) SHA1(ba267b69a2fda2a2348b140979ece562411bb37b) )
124	124	ROM_END
125	125
126	126	static INPUT_PORTS_START( mouse )
r32760	r32761
241	241	m_rom_bank = 0;
242	242	last_mx = last_my = count_x = count_y = 0;
243	243	m_timer_cnt = 0xff;
244		m_timer_ctl = 0x40; // disable interrupt, everything else clear
	244	m_timer_ctl = 0x40; // disable interrupt, everything else clear
245	245	m_port_a_in = 0;
246	246	m_port_b_in = 0x80;
247	247	m_port_c_in = 0;
r32760	r32761
261	261
262	262	UINT8 a2bus_mouse_device::read_c0nx(address_space &space, UINT8 offset)
263	263	{
264		return m_pia->read(space, offset & 3);
	264	return m_pia->read(space, offset & 3);
265	265	}
266	266
267	267
r32760	r32761
394	394	m_timer_cnt = data;
395	395	recalc = true;
396	396	}
397		// offset 1 = timer control: b7 = IRQ, b6 = IRQ mask (1=suppress),
398		// b5 = input select (0=CPU clk, 1=ext),
399		// b4 = enable external timer input,
400		// b3 = clear, b2-b0 = scaler (1/2/4/8/16/32/64/128)
	397	// offset 1 = timer control: b7 = IRQ, b6 = IRQ mask (1=suppress),
	398	// b5 = input select (0=CPU clk, 1=ext),
	399	// b4 = enable external timer input,
	400	// b3 = clear, b2-b0 = scaler (1/2/4/8/16/32/64/128)
401	401	else
402	402	{
403	403	// clearing the interrupt?
r32760	r32761
425	425	recalc = true;
426	426	}
427	427
428		m_timer_ctl = data;
	428	m_timer_ctl = data;
429	429	}
430	430
431	431	}
r32760	r32761
445	445	X1 = gate, must go 0/1 for each pixel moved
446	446	Y0 = direction, 0 = up, 1 = down
447	447	Y1 = gate, must go 0/1 for each pixel moved
448
	448
449	449	The direction must stay constant for a given train of gate pulses or the MCU will get confused.
450	450	*/
451	451	void a2bus_mouse_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
452	452	{
453		if (id == TIMER_68705) // 68705's built-in timer
	453	if (id == TIMER_68705) // 68705's built-in timer
454	454	{
455	455	m_timer_ctl \|= 0x80; // indicate timer expired
456		if (!(m_timer_ctl & 0x40)) // if interrupt not suppressed, fire!
	456	if (!(m_timer_ctl & 0x40)) // if interrupt not suppressed, fire!
457	457	{
458	458	m_mcu->set_input_line(M68705_INT_TIMER, ASSERT_LINE);
459	459	}
r32760	r32761
509	509	else
510	510	{
511	511	count_x--;
512		m_port_b_in \|= 0x01; // X1
	512	m_port_b_in \|= 0x01; // X1
513	513	}
514		m_port_b_in \|= 0x02; // X0
	514	m_port_b_in \|= 0x02; // X0
515	515	}
516	516	else if (count_y)
517	517	{
r32760	r32761
522	522	else
523	523	{
524	524	count_y--;
525		m_port_b_in \|= 0x04; // Y0
	525	m_port_b_in \|= 0x04; // Y0
526	526	}
527		m_port_b_in \|= 0x08; // Y1
	527	m_port_b_in \|= 0x08; // Y1
528	528	}
529	529	}
530	530	}

trunk/src/emu/bus/a2bus/corvfdc02.c
r32760	r32761
4	4
5	5	Implemention of the Corvus Systems CORVUS02 floppy controller
6	6	aka the "Buffered Floppy Controller"
7
	7
8	8	Boot PROM 0.8 says 8" SSDD or 5.25" DSDD; we stick with 5.25" here
9	9	and let the FDC01 handle 8".
10
	10
11	11	*********************************************************************/
12	12
13	13	#include "corvfdc02.h"
r32760	r32761
23	23
24	24	const device_type A2BUS_CORVFDC02 = &device_creator<a2bus_corvfdc02_device>;
25	25
26		#define FDC02_ROM_REGION "fdc02_rom"
27		#define FDC02_FDC_TAG "fdc02_fdc"
	26	#define FDC02_ROM_REGION "fdc02_rom"
	27	#define FDC02_FDC_TAG "fdc02_fdc"
28	28
29	29	FLOPPY_FORMATS_MEMBER( a2bus_corvfdc02_device::corv_floppy_formats )
30	30	FLOPPY_CONCEPT_525DSDD_FORMAT,
r32760	r32761
86	86	m_con3(*this, FDC02_FDC_TAG":2"),
87	87	m_con4(*this, FDC02_FDC_TAG":3")
88	88	{
89
90	89	}
91	90
92	91	a2bus_corvfdc02_device::a2bus_corvfdc02_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock) :
r32760	r32761
143	142	{
144	143	switch (offset)
145	144	{
146		case 0: // 765 FIFO
	145	case 0: // 765 FIFO
147	146	return m_fdc->fifo_r(space, 0);
148	147
149		case 1: // 765 MSR
	148	case 1: // 765 MSR
150	149	return m_fdc->msr_r(space, 0);
151	150
152		case 2: // buffer address
	151	case 2: // buffer address
153	152	return (m_bufptr>>1) & 0xff;
154	153
155		case 3:
156		// printf("Read buffer @ %x = %02x\n", m_bufptr, m_buffer[m_bufptr]);
	154	case 3:
	155	// printf("Read buffer @ %x = %02x\n", m_bufptr, m_buffer[m_bufptr]);
157	156	return m_buffer[m_bufptr--];
158	157
159		case 4: // local status
	158	case 4: // local status
160	159	if (m_curfloppy)
161	160	{
162	161	m_fdc_local_status &= ~(1 \| 0x40);
r32760	r32761
188	187	case 1: // FDC ???
189	188	break;
190	189
191		case 2: // buffer address
	190	case 2: // buffer address
192	191	m_bufptr = (data << 1) \| (data & 1);
193		// printf("%02x to buffer address yields %x\n", data, m_bufptr);
	192	// printf("%02x to buffer address yields %x\n", data, m_bufptr);
194	193	break;
195	194
196		case 3: // buffer write
197		// printf("%02x to buffer[%x]\n", data, m_bufptr);
	195	case 3: // buffer write
	196	// printf("%02x to buffer[%x]\n", data, m_bufptr);
198	197	m_buffer[m_bufptr--] = data;
199	198	break;
200	199
r32760	r32761
233	232	{
234	233	// motor control (active low)
235	234	m_curfloppy->mon_w((data & 8) ? 1 : 0);
236		// printf("Cur drive %p motor %s\n", m_curfloppy, (data & 8) ? "OFF" : "ON");
	235	// printf("Cur drive %p motor %s\n", m_curfloppy, (data & 8) ? "OFF" : "ON");
237	236	}
238	237
239	238	if (data & 0x80)
240	239	{
241		// printf("Reset NEC765\n");
	240	// printf("Reset NEC765\n");
242	241	m_fdc->reset();
243	242	}
244	243	break;
r32760	r32761
266	265	}
267	266	else
268	267	{
269		m_fdc_local_status \|= 2; // clear IRQ
	268	m_fdc_local_status \|= 2; // clear IRQ
270	269	lower_slot_irq();
271	270	}
272	271	}
r32760	r32761
279	278	if (m_fdc_local_command & 0x40)
280	279	{
281	280	m_buffer[m_bufptr] = m_fdc->dma_r();
282		// printf("DMA %02x to buffer[%x]\n", m_buffer[m_bufptr], m_bufptr);
	281	// printf("DMA %02x to buffer[%x]\n", m_buffer[m_bufptr], m_bufptr);
283	282
284	283	if (!m_bufptr)
285	284	{
r32760	r32761
296	295	}
297	296	}
298	297	}
299

trunk/src/emu/bus/a2bus/corvfdc02.h
r32760	r32761
56	56	UINT8 *m_rom;
57	57	UINT8 m_fdc_local_status, m_fdc_local_command;
58	58	UINT16 m_bufptr;
59		UINT8 m_buffer[2048]; // 1x6116 SRAM
	59	UINT8 m_buffer[2048]; // 1x6116 SRAM
60	60	floppy_image_device *m_curfloppy;
61	61	bool m_in_drq;
62	62	emu_timer *m_timer;

trunk/src/emu/bus/a2bus/timemasterho.c
r32760	r32761
20	20	\|____________________________ _\|
21	21	\| \|
22	22	\|______________________\|
23
24
	23
	24
25	25	DIPS: 1:SET 2:MODE 3:NMI 4:IRQ
26	26	1 & 4 are on by default.
27
	27
28	28	J1: 8 pins for X10 home control functions (top to bottom)
29	29	1: ADJ 2: 5V 3: MODE 4: GND
30	30	5: A 6: 5V 7: B 8: GND
31
	31
32	32	X10 functions not supported.
33
	33
34	34	*********************************************************************/
35	35
36	36	#include "timemasterho.h"
r32760	r32761
45	45
46	46	const device_type A2BUS_TIMEMASTERHO = &device_creator<a2bus_timemasterho_device>;
47	47
48		#define TIMEMASTER_ROM_REGION "timemst_rom"
49		#define TIMEMASTER_PIA_TAG "timemst_pia"
50		#define TIMEMASTER_M5832_TAG "timemst_msm"
	48	#define TIMEMASTER_ROM_REGION "timemst_rom"
	49	#define TIMEMASTER_PIA_TAG "timemst_pia"
	50	#define TIMEMASTER_M5832_TAG "timemst_msm"
51	51
52	52	MACHINE_CONFIG_FRAGMENT( timemaster )
53	53	MCFG_DEVICE_ADD(TIMEMASTER_PIA_TAG, PIA6821, 1021800)
r32760	r32761
61	61
62	62	ROM_START( timemaster )
63	63	ROM_REGION(0x1000, TIMEMASTER_ROM_REGION, 0)
64		ROM_LOAD( "ae timemaster ii h.o. rom rev. 5.bin", 0x000000, 0x001000, CRC(ff5bd644) SHA1(ae0173da61581a06188c1bee89e95a0aa536c411) )
	64	ROM_LOAD( "ae timemaster ii h.o. rom rev. 5.bin", 0x000000, 0x001000, CRC(ff5bd644) SHA1(ae0173da61581a06188c1bee89e95a0aa536c411) )
65	65	ROM_END
66	66
67	67	static INPUT_PORTS_START( tmho )
68	68	PORT_START("DSW1")
69	69	PORT_DIPNAME( 0x01, 0x01, "Set")
70		PORT_DIPSETTING( 0x00, "Apple can't set clock")
71		PORT_DIPSETTING( 0x01, "Apple can set clock")
	70	PORT_DIPSETTING( 0x00, "Apple can't set clock")
	71	PORT_DIPSETTING( 0x01, "Apple can set clock")
72	72
73	73	PORT_DIPNAME( 0x02, 0x00, "Mode")
74		PORT_DIPSETTING( 0x00, "TimeMaster")
75		PORT_DIPSETTING( 0x02, "Mountain AppleClock")
	74	PORT_DIPSETTING( 0x00, "TimeMaster")
	75	PORT_DIPSETTING( 0x02, "Mountain AppleClock")
76	76
77	77	PORT_DIPNAME( 0x04, 0x00, "NMI")
78		PORT_DIPSETTING( 0x00, DEF_STR(Off))
79		PORT_DIPSETTING( 0x04, DEF_STR(On))
	78	PORT_DIPSETTING( 0x00, DEF_STR(Off))
	79	PORT_DIPSETTING( 0x04, DEF_STR(On))
80	80
81	81	PORT_DIPNAME( 0x08, 0x08, "IRQ")
82		PORT_DIPSETTING( 0x00, DEF_STR(Off))
83		PORT_DIPSETTING( 0x08, DEF_STR(On))
	82	PORT_DIPSETTING( 0x00, DEF_STR(Off))
	83	PORT_DIPSETTING( 0x08, DEF_STR(On))
84	84	INPUT_PORTS_END
85	85
86	86	/***************************************************************************
r32760	r32761
154	154
155	155	void a2bus_timemasterho_device::device_reset()
156	156	{
157		m_msm5832->cs_w(ASSERT_LINE); // CS is tied to Vcc
	157	m_msm5832->cs_w(ASSERT_LINE); // CS is tied to Vcc
158	158	m_started = true;
159	159	}
160	160
r32760	r32761
167	167	{
168	168	if (offset <= 3)
169	169	{
170		return m_pia->read(space, offset);
	170	return m_pia->read(space, offset);
171	171	}
172	172
173	173	return 0xff;
r32760	r32761
194	194	{
195	195	if (m_started)
196	196	{
197		if (!(m_dsw1->read() & 2)) // TimeMaster native
	197	if (!(m_dsw1->read() & 2)) // TimeMaster native
198	198	{
199	199	return m_rom[offset+0xc00];
200	200	}
r32760	r32761
228	228	{
229	229	if (m_dsw1->read() & 1)
230	230	{
231		m_msm5832->write_w((data >> 6) & 1 ? ASSERT_LINE : CLEAR_LINE);
	231	m_msm5832->write_w((data >> 6) & 1 ? ASSERT_LINE : CLEAR_LINE);
232	232	}
233	233	}
234	234
r32760	r32761
277	277	m_irqb = state;
278	278	update_irqs();
279	279	}
280

trunk/src/emu/bus/a2bus/a2lang.c
r32760	r32761
112	112	// likely to be interrupt-safe.
113	113	if (state->m_machinetype == APPLE_II)
114	114	{
115		switch (offset & 0x03)
	115	switch (offset & 0x03)
116	116	{
117	117	case 1:
118	118	case 3:

trunk/src/emu/bus/a2bus/corvfdc01.c
r32760	r32761
3	3	corvfdc01.c
4	4
5	5	Implemention of the Corvus Systems CORVUS01 floppy controller
6
	6
7	7	Boot PROM 0.8 fixes this at: 8", 500 blocks total, 128 bytes/block,
8		26 sectors/track, 77 tracks.
9
	8	26 sectors/track, 77 tracks.
	9
10	10	*********************************************************************/
11	11
12	12	#include "corvfdc01.h"
r32760	r32761
21	21
22	22	const device_type A2BUS_CORVFDC01 = &device_creator<a2bus_corvfdc01_device>;
23	23
24		#define FDC01_ROM_REGION "fdc01_rom"
25		#define FDC01_FDC_TAG "fdc01_fdc"
	24	#define FDC01_ROM_REGION "fdc01_rom"
	25	#define FDC01_FDC_TAG "fdc01_fdc"
26	26
27	27	FLOPPY_FORMATS_MEMBER( a2bus_corvfdc01_device::corv_floppy_formats )
28	28	FLOPPY_IMD_FORMAT
r32760	r32761
161	161	{
162	162	switch (offset)
163	163	{
164		case 0: // local status
	164	case 0: // local status
165	165	if (m_curfloppy)
166	166	{
167	167	m_fdc_local_status &= ~LS_DSKCHG_mask;
r32760	r32761
169	169	}
170	170	return m_fdc_local_status \| LS_8IN_mask;
171	171
172		case 8: // WD1793 at 8-11
	172	case 8: // WD1793 at 8-11
173	173	return m_wdfdc->status_r(space, offset);
174	174
175	175	case 9:
r32760	r32761
225	225	if (m_curfloppy != NULL)
226	226	{
227	227	// side select
228		m_curfloppy->ss_w((data & LC_FLPSD1_mask) != 0);
	228	m_curfloppy->ss_w((data & LC_FLPSD1_mask) != 0);
229	229
230	230	// motor control (active low)
231	231	m_curfloppy->mon_w((data & LC_MOTOROF_mask) ? 1 : 0);
r32760	r32761
278	278	else
279	279	m_fdc_local_status &= ~LS_DRQ_mask;
280	280	}
281

trunk/src/emu/bus/a2bus/laser128.c
r32760	r32761
108	108	{
109	109	return m_slot7_ram[offset];
110	110	}
111		return m_rom[(offset & 0x3ff) + 0x6000 + m_slot7_bank];
	111	return m_rom[(offset & 0x3ff) + 0x6000 + m_slot7_bank];
112	112	}
113	113
114	114	return 0xff;
r32760	r32761
124	124	// UDCREG
125	125	if ((m_slot == 7) && (offset == 0x7f8))
126	126	{
127		// printf("%02x to UDCREG\n", data);
	127	// printf("%02x to UDCREG\n", data);
128	128
129	129	m_slot7_ram_bank = (data & 0x8) ? 0x400 : 0;
130	130	m_slot7_bank = (((data >> 4) & 0x7) * 0x400);
131	131
132		// printf("\tRAM bank %x, ROM bank %x\n", m_slot7_ram_bank, m_slot7_bank);
	132	// printf("\tRAM bank %x, ROM bank %x\n", m_slot7_ram_bank, m_slot7_bank);
133	133	}
134	134	}
135	135

trunk/src/emu/bus/a2bus/a2corvus.c
r32760	r32761
32	32	7) When the format completes, type "RUN APPLESOFT BOOT PREP" and press Enter.
33	33	8) Once it finishes, quit MESS. Remove the diskii(ng) from slot 7 and
34	34	the system will boot into DOS 3.3 from the Corvus HD.
35
	35
36	36	TODO: but there are no Corvus drivers present after that, only
37	37	Disk II?
38	38

trunk/src/emu/bus/generic/carts.c
r32760	r32761
1	1	// license:BSD-3-Clause
2	2	// copyright-holders:etabeta
3	3	/**********************************************************************
4
	4
5	5	Generic ROM / RAM socket slots
6
	6
7	7	**********************************************************************/
8	8
9	9

trunk/src/emu/bus/generic/rom.c
r32760	r32761
4	4
5	5
6	6	Generic ROM emulation (for carts and ROM sockets)
7
	7
8	8	This offers generic access to a ROM
9
	9
10	10	generic_rom_plain : returns 0xff when the system reads beyond the end of the ROM
11	11	generic_rom_linear : maps linearly the ROM in the accessed area (i.e., read offset is masked with (ROM size - 1) )
12	12
13	13	generic_romram_plain : allows support for carts always containing ROM + RAM (e.g. X07)
14	14
15
	15
16	16	TODO:
17	17	- possibly support linear mapping when non-power of 2 ROMs are mapped
18
	18
19	19	***********************************************************************************************************/
20	20
21	21
r32760	r32761
120	120	if (offset < m_ram.bytes())
121	121	m_ram[offset] = data;
122	122	}
123

trunk/src/emu/bus/generic/ram.c
r32760	r32761
1	1	// license:BSD-3-Clause
2	2	// copyright-holders:etabeta
3	3	/***********************************************************************************************************
4
5
	4
	5
6	6	Generic RAM socket emulation
7
	7
8	8	This offers generic access to RAM
9
	9
10	10	generic_ram_plain : returns 0xff when the system reads beyond the end of the RAM
11		generic_ram_linear : maps linearly the RAM in the accessed area (i.e., read/write offset is masked with
	11	generic_ram_linear : maps linearly the RAM in the accessed area (i.e., read/write offset is masked with
12	12	(RAM size - 1) )
13
	13
14	14	TODO:
15	15	- support variable RAM size
16	16	- possibly support linear mapping when non-power of 2 RAMs are mapped
17	17	- add support for 16bit & 32bit RAM access
18
	18
19	19	***********************************************************************************************************/
20	20
21	21
r32760	r32761
121	121	{
122	122	m_ram[offset % m_ram.bytes()] = data;
123	123	}
124

trunk/src/emu/bus/generic/slot.c
r32760	r32761
3	3	/***********************************************************************************************************
4	4
5	5	Generic ROM / RAM Socket and Cartslot device
6
	6
7	7	This device offers basic RAM / ROM allocation and access
8	8
9	9	The available handlers are suited for any situation where a system opens a
r32760	r32761
12	12	This device is not suited whenever the system exposes additional lines to
13	13	the socket/slot: e.g. whenever input/output lines are present, whenever
14	14	there are lines controlling bankswitch / paging, and whenever different
15		cart configurations have to be supported (like some PCBs containing ROM
	15	cart configurations have to be supported (like some PCBs containing ROM
16	16	only, and other containing both ROM and RAM)
17	17	In the latter situations, per-system slot devices have to be created (see
18	18	e.g. APF cart slot device for an example of a simple device with multiple
19	19	pcbs supported)
20
	20
21	21	***********************************************************************************************************/
22	22
23	23
r32760	r32761
136	136	bool generic_slot_device::call_load()
137	137	{
138	138	if (m_cart)
139		{
	139	{
140	140	if (!m_device_image_load.isnull())
141	141	return m_device_image_load(*this);
142	142	else
143	143	{
144	144	UINT32 len = common_get_size("rom");
145
	145
146	146	rom_alloc(len, m_width, m_endianness);
147		common_load_rom(get_rom_base(), len, "rom");
	147	common_load_rom(get_rom_base(), len, "rom");
148	148
149	149	return IMAGE_INIT_PASS;
150	150	}
r32760	r32761
189	189
190	190	/**************************************************
191	191
192		Implementation
193
	192	Implementation
	193
194	194	**************************************************/
195	195
196	196
197	197	/*-------------------------------------------------
198		common_get_size - it gets image file size both
	198	common_get_size - it gets image file size both
199	199	for fullpath and for softlist
200	200	-------------------------------------------------*/
201	201
r32760	r32761
208	208	}
209	209
210	210	/*-------------------------------------------------
211		common_load_rom - it loads from image file both
	211	common_load_rom - it loads from image file both
212	212	for fullpath and for softlist
213	213	-------------------------------------------------*/
214	214
r32760	r32761
283	283	if (m_cart)
284	284	m_cart->write_ram(space, offset, data);
285	285	}
286

trunk/src/emu/bus/generic/rom.h
r32760	r32761
14	14	public:
15	15	// construction/destruction
16	16	generic_rom_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source);
17
	17
18	18	// device-level overrides
19	19	virtual void device_start() {}
20	20	};
r32760	r32761
28	28	// construction/destruction
29	29	generic_rom_plain_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source);
30	30	generic_rom_plain_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
31
	31
32	32	// reading and writing
33	33	virtual DECLARE_READ8_MEMBER(read_rom);
34	34	virtual DECLARE_READ16_MEMBER(read16_rom);
r32760	r32761
43	43	public:
44	44	// construction/destruction
45	45	generic_romram_plain_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
46
	46
47	47	// reading and writing
48	48	virtual DECLARE_READ8_MEMBER(read_ram);
49	49	virtual DECLARE_WRITE8_MEMBER(write_ram);
r32760	r32761
57	57	public:
58	58	// construction/destruction
59	59	generic_rom_linear_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
60
	60
61	61	// reading and writing
62	62	virtual DECLARE_READ8_MEMBER(read_rom);
63	63	virtual DECLARE_READ16_MEMBER(read16_rom);

trunk/src/emu/bus/generic/ram.h
r32760	r32761
14	14	public:
15	15	// construction/destruction
16	16	generic_ram_plain_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, UINT32 size, const char shortname, const char *source);
17
	17
18	18	// device-level overrides
19	19	virtual void device_start();
20
	20
21	21	// reading and writing
22	22	virtual DECLARE_READ8_MEMBER(read_ram);
23	23	virtual DECLARE_WRITE8_MEMBER(write_ram);
24
	24
25	25	private:
26	26	UINT32 m_size;
27	27	};
r32760	r32761
35	35	public:
36	36	// construction/destruction
37	37	generic_ram_linear_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, UINT32 size, const char shortname, const char *source);
38
	38
39	39	// device-level overrides
40	40	virtual void device_start();
41
	41
42	42	// reading and writing
43	43	virtual DECLARE_READ8_MEMBER(read_ram);
44	44	virtual DECLARE_WRITE8_MEMBER(write_ram);
45
	45
46	46	private:
47	47	UINT32 m_size;
48	48	};

trunk/src/emu/bus/generic/slot.h
r32760	r32761
93	93
94	94	static void static_set_device_load(device_t &device, device_image_load_delegate callback) { downcast<generic_slot_device &>(device).m_device_image_load = callback; }
95	95	static void static_set_device_unload(device_t &device, device_image_func_delegate callback) { downcast<generic_slot_device &>(device).m_device_image_unload = callback; }
96
	96
97	97	void set_interface(const char * interface) { m_interface = interface; }
98	98	void set_default_card(const char * def) { m_default_card = def; }
99	99	void set_extensions(const char * exts) { m_extensions = exts; }
100	100	void set_must_be_loaded(bool mandatory) { m_must_be_loaded = mandatory; }
101	101	void set_width(int width) { m_width = width; }
102	102	void set_endian(endianness_t end) { m_endianness = end; }
103
	103
104	104	// device-level overrides
105	105	virtual void device_start();
106	106	virtual void device_config_complete();
r32760	r32761
168	168	#define MCFG_GENERIC_CARTSLOT_ADD(_tag, _slot_intf, _dev_intf) \
169	169	MCFG_DEVICE_ADD(_tag, GENERIC_SOCKET, 0) \
170	170	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, NULL, false) \
171		MCFG_GENERIC_INTERFACE(_dev_intf) \
172
	171	MCFG_GENERIC_INTERFACE(_dev_intf)
173	172	#define MCFG_GENERIC_SOCKET_ADD(_tag, _slot_intf, _dev_intf) \
174	173	MCFG_DEVICE_ADD(_tag, GENERIC_SOCKET, 0) \
175	174	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, NULL, false) \
176		MCFG_GENERIC_INTERFACE(_dev_intf) \
177
	175	MCFG_GENERIC_INTERFACE(_dev_intf)
178	176	#endif

trunk/src/emu/bus/saturn/sat_slot.c
r32760	r32761
156	156	// from fullpath, only ROM carts
157	157	UINT32 len = (software_entry() != NULL) ? get_software_region_length("rom") : length();
158	158	UINT32 *ROM;
159
	159
160	160	m_cart->rom_alloc(len, tag());
161	161	ROM = m_cart->get_rom_base();
162
	162
163	163	if (software_entry() != NULL)
164	164	memcpy(ROM, get_software_region("rom"), len);
165	165	else
166	166	fread(ROM, len);
167
	167
168	168	// fix endianness....
169	169	for (int i = 0; i < len/4; i ++)
170	170	ROM[i] = BITSWAP32(ROM[i],7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8,23,22,21,20,19,18,17,16,31,30,29,28,27,26,25,24);

trunk/src/emu/bus/vectrex/slot.c
r32760	r32761
156	156	{
157	157	UINT32 size = (software_entry() == NULL) ? length() : get_software_region_length("rom");
158	158	UINT8 *ROM;
159
	159
160	160	if (size > 0x10000)
161	161	{
162	162	seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
163	163	return IMAGE_INIT_FAIL;
164	164	}
165
	165
166	166	m_cart->rom_alloc((size < 0x1000) ? 0x1000 : size, tag());
167	167	ROM = m_cart->get_rom_base();
168
	168
169	169	if (software_entry() == NULL)
170	170	fread(ROM, size);
171	171	else
172	172	memcpy(ROM, get_software_region("rom"), size);
173
	173
174	174	// Verify the file is accepted by the Vectrex bios
175	175	if (memcmp(ROM, "g GCE", 5))
176	176	{
177	177	seterror(IMAGE_ERROR_UNSPECIFIED, "Invalid image");
178	178	return IMAGE_INIT_FAIL;
179	179	}
180
	180
181	181	// determine type
182	182	m_type = VECTREX_STD;
183	183	if (!memcmp(ROM + 0x06, "SRAM", 4))
184		m_type = VECTREX_SRAM;
	184	m_type = VECTREX_SRAM;
185	185	if (size > 0x8000)
186	186	m_type = VECTREX_64K;
187
	187
188	188	//printf("Type: %s\n", vectrex_get_slot(m_type));
189	189
190	190	// determine 3D setup (to help video setup at machine_start)
191	191	if (!memcmp(ROM + 0x11, "NARROW", 6) && (ROM[0x39] == 0x0c))
192	192	m_vec3d = VEC3D_NARROW;
193
	193
194	194	if (!memcmp(ROM + 0x11, "CRAZY COASTER", 13))
195	195	m_vec3d = VEC3D_CCOAST;
196
	196
197	197	if (!memcmp(ROM + 0x11, "3D MINE STORM", 13))
198	198	m_vec3d = VEC3D_MINEST;
199	199
r32760	r32761
229	229	int type = VECTREX_STD;
230	230
231	231	core_fread(m_file, rom, size);
232
	232
233	233	if (!memcmp(rom + 0x06, "SRAM", 4))
234		type = VECTREX_SRAM;
	234	type = VECTREX_SRAM;
235	235	if (size > 0x8000)
236	236	type = VECTREX_64K;
237	237
r32760	r32761
278	278	if (m_cart)
279	279	m_cart->write_bank(space, offset, data);
280	280	}
281
282

trunk/src/emu/bus/vectrex/rom.h
r32760	r32761
31	31	public:
32	32	// construction/destruction
33	33	vectrex_rom64k_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
34
	34
35	35	// device-level overrides
36	36	virtual void device_start();
37	37	virtual void device_reset();
38
	38
39	39	// reading and writing
40	40	virtual DECLARE_READ8_MEMBER(read_rom);
41	41	virtual DECLARE_WRITE8_MEMBER(write_bank);
r32760	r32761
51	51	public:
52	52	// construction/destruction
53	53	vectrex_sram_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
54
	54
55	55	// reading and writing
56	56	virtual DECLARE_WRITE8_MEMBER(write_ram);
57	57	};

trunk/src/emu/bus/vectrex/slot.h
r32760	r32761
111	111
112	112	#define MCFG_VECTREX_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
113	113	MCFG_DEVICE_ADD(_tag, VECTREX_CART_SLOT, 0) \
114		MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
115
	114	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false)
116	115	#endif

trunk/src/emu/bus/odyssey2/voice.c
r32760	r32761
33	33
34	34
35	35	void o2_voice_device::device_start()
36		{
	36	{
37	37	save_item(NAME(m_lrq_state));
38	38	}
39	39

trunk/src/emu/bus/odyssey2/slot.h
r32760	r32761
92	92	virtual DECLARE_WRITE8_MEMBER(io_write);
93	93	virtual DECLARE_READ8_MEMBER(t0_read) { if (m_cart) return m_cart->t0_read(space, offset); else return 0; }
94	94
95		virtual void write_bank(int bank) { if (m_cart) m_cart->write_bank(bank); }
	95	virtual void write_bank(int bank) { if (m_cart) m_cart->write_bank(bank); }
96	96
97	97	protected:
98	98
r32760	r32761
114	114
115	115	#define MCFG_O2_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
116	116	MCFG_DEVICE_ADD(_tag, O2_CART_SLOT, 0) \
117		MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
	117	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false)
118	118
119
120	119	SLOT_INTERFACE_EXTERN(o2_cart);
121	120
122	121	#endif

trunk/src/emu/bus/odyssey2/chess.h
r32760	r32761
12	12
13	13	class o2_chess_device : public o2_rom_device
14	14	{
15
16	15	virtual machine_config_constructor device_mconfig_additions() const;
17		// virtual const rom_entry *device_rom_region() const;
18
	16	// virtual const rom_entry *device_rom_region() const;
	17
19	18	public:
20	19	// construction/destruction
21	20	o2_chess_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);

trunk/src/emu/bus/odyssey2/voice.h
r32760	r32761
27	27	virtual DECLARE_READ8_MEMBER(read_rom04) { if (m_subslot->exists()) return m_subslot->read_rom04(space, offset); else return 0xff; }
28	28	virtual DECLARE_READ8_MEMBER(read_rom0c) { if (m_subslot->exists()) return m_subslot->read_rom0c(space, offset); else return 0xff; }
29	29
30		virtual void write_bank(int bank) { if (m_subslot->exists()) m_subslot->write_bank(bank); }
	30	virtual void write_bank(int bank) { if (m_subslot->exists()) m_subslot->write_bank(bank); }
31	31
32	32	DECLARE_WRITE_LINE_MEMBER(lrq_callback);
33	33	DECLARE_WRITE8_MEMBER(io_write);

trunk/src/emu/bus/odyssey2/rom.c
r32760	r32761
50	50	//-------------------------------------------------
51	51
52	52	void o2_rom_device::device_start()
53		{
	53	{
54	54	save_item(NAME(m_bank_base));
55	55	}
56	56
57	57	void o2_rom_device::device_reset()
58		{
	58	{
59	59	m_bank_base = 0;
60	60	}
61	61
r32760	r32761
94	94	{
95	95	return m_rom[offset + 0xc00 + (m_bank_base & 0x03) * 0x1000];
96	96	}
97

trunk/src/emu/bus/odyssey2/slot.c
r32760	r32761
166	166	{
167	167	UINT32 size = (software_entry() == NULL) ? length() : get_software_region_length("rom");
168	168	m_cart->rom_alloc(size, tag());
169
	169
170	170	if (software_entry() == NULL)
171	171	fread(m_cart->get_rom_base(), size);
172	172	else
r32760	r32761
223	223	type = O2_ROM12;
224	224	if (size == 16384)
225	225	type = O2_ROM16;
226
	226
227	227	slot_string = o2_get_slot(type);
228	228
229	229	//printf("type: %s\n", slot_string);
r32760	r32761
278	278	SLOT_INTERFACE_INTERNAL("o2_chess", O2_ROM_CHESS)
279	279	SLOT_INTERFACE_INTERNAL("o2_voice", O2_ROM_VOICE)
280	280	SLOT_INTERFACE_END
281

trunk/src/emu/bus/odyssey2/rom.h
r32760	r32761
15	15	// construction/destruction
16	16	o2_rom_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source);
17	17	o2_rom_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
18
	18
19	19	// device-level overrides
20	20	virtual void device_start();
21	21	virtual void device_reset();
22
	22
23	23	// reading and writing
24	24	virtual DECLARE_READ8_MEMBER(read_rom04);
25	25	virtual DECLARE_READ8_MEMBER(read_rom0c);
26
	26
27	27	virtual void write_bank(int bank);
28
	28
29	29	protected:
30	30	int m_bank_base;
31	31	};
r32760	r32761
37	37	public:
38	38	// construction/destruction
39	39	o2_rom12_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
40
	40
41	41	// reading and writing
42	42	virtual DECLARE_READ8_MEMBER(read_rom04);
43	43	virtual DECLARE_READ8_MEMBER(read_rom0c);
r32760	r32761
50	50	public:
51	51	// construction/destruction
52	52	o2_rom16_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
53
	53
54	54	// reading and writing
55	55	virtual DECLARE_READ8_MEMBER(read_rom04);
56	56	virtual DECLARE_READ8_MEMBER(read_rom0c);

trunk/src/emu/bus/arcadia/slot.h
r32760	r32761
99	99
100	100	#define MCFG_ARCADIA_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
101	101	MCFG_DEVICE_ADD(_tag, EA2001_CART_SLOT, 0) \
102		MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
103
	102	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false)
104	103	#endif

trunk/src/emu/bus/arcadia/slot.c
r32760	r32761
155	155	UINT32 len = (software_entry() == NULL) ? length() : get_software_region_length("rom");
156	156
157	157	m_cart->rom_alloc(len, tag());
158
	158
159	159	if (software_entry() == NULL)
160	160	fread(m_cart->get_rom_base(), len);
161	161	else
r32760	r32761
260	260	else
261	261	return 0xff;
262	262	}
263

trunk/src/emu/bus/sms_ctrl/graphic.c
r32760	r32761
9	9	0x20 \| 0x7f
10	10	0x00 \| 0x3f
11	11	0x30 \| 0xff
12
	12
13	13	Typical sequence:
14	14	- 3f write 0x20
15	15	- read dc
16	16	- 3f write 0x00
17		- read dc
	17	- read dc
18	18	- 3f write 0x20
19	19	- read dc
20	20	- 3f write 0x30
21	21	Suspect from kind of counter that is reset by a 0x30 write to I/O port 0x3f.
22	22	Once reset reads from i/O port dc expect to see 0xE0.
23		And then any write with differing bits goes through several internal I/O ports
	23	And then any write with differing bits goes through several internal I/O ports
24	24	with the first port being the one with the buttons
25	25
26	26	In the reset/start state the lower four/five bits are 0.
r32760	r32761
45	45
46	46
47	47	static INPUT_PORTS_START( sms_graphic )
48		PORT_START("BUTTONS")
49		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) // MENU
50		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) // DO
51		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) // PEN
52		PORT_BIT( 0xf8, IP_ACTIVE_LOW, IPT_UNUSED )
	48	PORT_START("BUTTONS")
	49	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) // MENU
	50	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) // DO
	51	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) // PEN
	52	PORT_BIT( 0xf8, IP_ACTIVE_LOW, IPT_UNUSED )
53	53
54	54	PORT_START("X")
55	55	PORT_BIT( 0xff, 0x00, IPT_LIGHTGUN_X) PORT_CROSSHAIR(X, 1.0, 0.0, 0) PORT_SENSITIVITY(50) PORT_KEYDELTA(15)
r32760	r32761
110	110	{
111	111	case 0: // Initial state / "I am a board"
112	112	// If any regular button is pressed raise/lower TL ?
113		// if ((m_buttons->read() & 0x07) != 0x07)
114		// return 0xf0;
	113	// if ((m_buttons->read() & 0x07) != 0x07)
	114	// return 0xf0;
115	115	return 0xd0;
116	116
117	117	case 1: // Read buttons (active low)
r32760	r32761
155	155
156	156	m_previous_write = data;
157	157	}
158

trunk/src/emu/bus/crvision/rom.h
r32760	r32761
43	43	public:
44	44	// construction/destruction
45	45	crvision_rom8k_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
46
	46
47	47	// reading and writing
48	48	virtual DECLARE_READ8_MEMBER(read_rom80);
49	49	};
r32760	r32761
55	55	public:
56	56	// construction/destruction
57	57	crvision_rom10k_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
58
	58
59	59	// reading and writing
60	60	virtual DECLARE_READ8_MEMBER(read_rom40);
61	61	virtual DECLARE_READ8_MEMBER(read_rom80);
r32760	r32761
68	68	public:
69	69	// construction/destruction
70	70	crvision_rom12k_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
71
	71
72	72	// reading and writing
73	73	virtual DECLARE_READ8_MEMBER(read_rom40);
74	74	virtual DECLARE_READ8_MEMBER(read_rom80);
r32760	r32761
81	81	public:
82	82	// construction/destruction
83	83	crvision_rom16k_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
84
	84
85	85	// reading and writing
86	86	virtual DECLARE_READ8_MEMBER(read_rom80);
87	87	};
r32760	r32761
93	93	public:
94	94	// construction/destruction
95	95	crvision_rom18k_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
96
	96
97	97	// reading and writing
98	98	virtual DECLARE_READ8_MEMBER(read_rom40);
99	99	virtual DECLARE_READ8_MEMBER(read_rom80);

trunk/src/emu/bus/crvision/slot.h
r32760	r32761
104	104
105	105	#define MCFG_CRVISION_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
106	106	MCFG_DEVICE_ADD(_tag, CRVISION_CART_SLOT, 0) \
107		MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
108
	107	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false)
109	108	#endif

trunk/src/emu/bus/crvision/rom.c
r32760	r32761
88	88	offset &= 0x1fff;
89	89	if (offset < 0x1000)
90	90	return m_rom[0x1000 + (offset & 0x7ff)];
91
	91
92	92	return m_rom[offset & 0xfff];
93	93	}
94	94

trunk/src/emu/bus/crvision/slot.c
r32760	r32761
163	163	seterror(IMAGE_ERROR_UNSPECIFIED, "Image extends beyond the expected size for an APF cart");
164	164	return IMAGE_INIT_FAIL;
165	165	}
166
	166
167	167	m_cart->rom_alloc(size, tag());
168
	168
169	169	if (software_entry() == NULL)
170	170	fread(m_cart->get_rom_base(), size);
171	171	else
r32760	r32761
295	295	else
296	296	return 0xff;
297	297	}
298

trunk/src/emu/bus/c64/rex_ep256.h
r32760	r32761
49	49
50	50	private:
51	51	generic_slot_device *m_eproms[8];
52
	52
53	53	UINT8 m_bank, m_socket;
54	54	int m_reset;
55	55	};

trunk/src/emu/bus/c64/dela_ep256.c
r32760	r32761
73	73	char str[6];
74	74	sprintf(str, "rom%i", i + 1);
75	75	m_eproms[i] = subdevice<generic_slot_device>(str);
76		}
	76	}
77	77	}
78	78
79	79

trunk/src/emu/bus/a7800/xboard.h
r32760	r32761
17	17	// construction/destruction
18	18	a78_xboard_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source);
19	19	a78_xboard_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
20
	20
21	21	// device-level overrides
22	22	virtual void device_start();
23	23	virtual machine_config_constructor device_mconfig_additions() const;
24	24	virtual void device_reset();
25
	25
26	26	// reading and writing
27	27	virtual DECLARE_READ8_MEMBER(read_04xx);
28	28	virtual DECLARE_WRITE8_MEMBER(write_04xx);
r32760	r32761
43	43	public:
44	44	// construction/destruction
45	45	a78_xm_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
46
	46
47	47	// device-level overrides
48	48	virtual void device_start();
49	49	virtual machine_config_constructor device_mconfig_additions() const;
50	50	virtual void device_reset();
51
	51
52	52	// reading and writing
53	53	virtual DECLARE_READ8_MEMBER(read_04xx);
54	54	virtual DECLARE_WRITE8_MEMBER(write_04xx);
55	55	virtual DECLARE_READ8_MEMBER(read_10xx);
56	56	virtual DECLARE_WRITE8_MEMBER(write_10xx);
57	57	virtual DECLARE_READ8_MEMBER(read_30xx);
58
	58
59	59	protected:
60	60	required_device<ym2151_device> m_ym;
61	61	int m_ym_enabled;

trunk/src/emu/bus/a7800/a78_slot.h
r32760	r32761
12	12	/* PCB */
13	13	enum
14	14	{
15		A78_TYPE0 = 0, // standard 8K/16K/32K games, no bankswitch
16		A78_TYPE1, // as TYPE0 + POKEY chip on the PCB
17		A78_TYPE2, // Atari SuperGame pcb (8x16K banks with bankswitch)
18		A78_TYPE3, // as TYPE1 + POKEY chip on the PCB
19		A78_TYPE6, // as TYPE1 + RAM IC on the PCB
20		A78_TYPEA, // Alien Brigade, Crossbow (9x16K banks with diff bankswitch)
21		A78_ABSOLUTE, // F18 Hornet
22		A78_ACTIVISION, // Double Dragon, Rampage
23		A78_HSC, // Atari HighScore cart
24		A78_XB_BOARD, // A7800 Expansion Board (it shall more or less apply to the Expansion Module too, but this is not officially released yet)
25		A78_XM_BOARD, // A7800 XM Expansion Module (theoretical specs only, since this is not officially released yet)
26		A78_MEGACART, // Homebrew by CPUWIZ, consists of SuperGame bank up to 512K + 32K RAM banked
27		A78_VERSABOARD = 0x10, // Homebrew by CPUWIZ, consists of SuperGame bank up to 256K + 32K RAM banked
	15	A78_TYPE0 = 0, // standard 8K/16K/32K games, no bankswitch
	16	A78_TYPE1, // as TYPE0 + POKEY chip on the PCB
	17	A78_TYPE2, // Atari SuperGame pcb (8x16K banks with bankswitch)
	18	A78_TYPE3, // as TYPE1 + POKEY chip on the PCB
	19	A78_TYPE6, // as TYPE1 + RAM IC on the PCB
	20	A78_TYPEA, // Alien Brigade, Crossbow (9x16K banks with diff bankswitch)
	21	A78_ABSOLUTE, // F18 Hornet
	22	A78_ACTIVISION, // Double Dragon, Rampage
	23	A78_HSC, // Atari HighScore cart
	24	A78_XB_BOARD, // A7800 Expansion Board (it shall more or less apply to the Expansion Module too, but this is not officially released yet)
	25	A78_XM_BOARD, // A7800 XM Expansion Module (theoretical specs only, since this is not officially released yet)
	26	A78_MEGACART, // Homebrew by CPUWIZ, consists of SuperGame bank up to 512K + 32K RAM banked
	27	A78_VERSABOARD = 0x10, // Homebrew by CPUWIZ, consists of SuperGame bank up to 256K + 32K RAM banked
28	28	// VersaBoard variants configured as Type 1/3/A or VersaBoard + POKEY at $0450
29	29	A78_TYPE0_POK450 = 0x20,
30	30	A78_TYPE1_POK450 = 0x21,
r32760	r32761
68	68	UINT8 *m_rom;
69	69	UINT32 m_rom_size;
70	70	dynamic_buffer m_ram;
71		dynamic_buffer m_nvram; // HiScore cart can save scores!
	71	dynamic_buffer m_nvram; // HiScore cart can save scores!
72	72	// helpers
73	73	UINT32 m_base_rom;
74	74	int m_bank_mask;
r32760	r32761
101	101	int get_cart_type() { return m_type; };
102	102	int identify_cart_type(UINT8 *ROM, UINT32 len);
103	103	bool has_cart() { return m_cart != NULL; }
104
	104
105	105	virtual iodevice_t image_type() const { return IO_CARTSLOT; }
106	106	virtual bool is_readable() const { return 1; }
107	107	virtual bool is_writeable() const { return 0; }
r32760	r32761
125	125	virtual DECLARE_WRITE8_MEMBER(write_10xx);
126	126	virtual DECLARE_WRITE8_MEMBER(write_30xx);
127	127	virtual DECLARE_WRITE8_MEMBER(write_40xx);
128
	128
129	129	private:
130	130	device_a78_cart_interface* m_cart;
131	131	int m_type;

trunk/src/emu/bus/a7800/cpuwiz.h
r32760	r32761
15	15	// construction/destruction
16	16	a78_versaboard_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source);
17	17	a78_versaboard_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
18
	18
19	19	// device-level overrides
20	20	virtual void device_start();
21	21	virtual void device_reset();
22
	22
23	23	// reading and writing
24	24	virtual DECLARE_READ8_MEMBER(read_40xx);
25	25	virtual DECLARE_WRITE8_MEMBER(write_40xx);
26
	26
27	27	protected:
28	28	int m_ram_bank;
29	29	};
r32760	r32761
36	36	public:
37	37	// construction/destruction
38	38	a78_megacart_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
39
	39
40	40	// reading and writing
41	41	virtual DECLARE_WRITE8_MEMBER(write_40xx);
42	42	};
r32760	r32761
51	51	public:
52	52	// construction/destruction
53	53	a78_rom_p450_vb_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
54
	54
55	55	// device-level overrides
56	56	virtual machine_config_constructor device_mconfig_additions() const;
57
	57
58	58	// reading and writing
59	59	virtual DECLARE_READ8_MEMBER(read_04xx) { if (offset >= 0x50 && offset < 0x60) return m_pokey450->read(space, offset & 0x0f); else return 0xff; }
60	60	virtual DECLARE_WRITE8_MEMBER(write_04xx) { if (offset >= 0x50 && offset < 0x60) m_pokey450->write(space, offset & 0x0f, data); }
61
	61
62	62	protected:
63	63	required_device<pokey_device> m_pokey450;
64	64	};

trunk/src/emu/bus/a7800/hiscore.c
r32760	r32761
3	3	/***********************************************************************************************************
4	4
5	5	A7800 HighScore passthrough cart emulation
6
7	6
	7
8	8	***********************************************************************************************************/
9	9
10	10
r32760	r32761
75	75	{
76	76	m_hscslot->write_40xx(space, offset, data);
77	77	}
78

trunk/src/emu/bus/a7800/rom.c
r32760	r32761
10	10	- 9 banks or not
11	11	etc...
12	12	But we might merge many of these if they become too many
13
	13
14	14	TODO:
15	15	- Are POKEY regs readable somewhere in SG 144K + POKEY homebrew? How do they detect
16	16	the POKEY otherwise?!?
r32760	r32761
232	232	/*-------------------------------------------------
233	233
234	234	Carts with no bankswitch + POKEY chip
235		The Pokey chips is accessed by writing at
	235	The Pokey chips is accessed by writing at
236	236	0x4000-0x7fff.
237
	237
238	238	GAMES: Ballblazer, Beef Drop (homebrew)
239
	239
240	240	-------------------------------------------------*/
241	241
242	242	READ8_MEMBER(a78_rom_pokey_device::read_40xx)
r32760	r32761
274	274	some test is run)
275	275	Note that the code is written so that also
276	276	homebrew games with larger ROMs work!
277
	277
278	278	GAMES: Crack'd, Fatal Run, Ikari Warriors...
279
	279
280	280	-------------------------------------------------*/
281	281
282	282	READ8_MEMBER(a78_rom_sg_device::read_40xx)
283	283	{
284	284	if (offset < 0x4000)
285		return m_rom[(offset & 0x3fff) + ((m_bank_mask - 1) * 0x4000)]; // second to last bank (is this always ok?!?)
	285	return m_rom[(offset & 0x3fff) + ((m_bank_mask - 1) * 0x4000)]; // second to last bank (is this always ok?!?)
286	286	else if (offset < 0x8000)
287	287	return m_rom[(offset & 0x3fff) + (m_bank * 0x4000)];
288	288	else
289		return m_rom[(offset & 0x3fff) + (m_bank_mask * 0x4000)]; // last bank
	289	return m_rom[(offset & 0x3fff) + (m_bank_mask * 0x4000)]; // last bank
290	290	}
291	291
292	292	WRITE8_MEMBER(a78_rom_sg_device::write_40xx)
r32760	r32761
300	300
301	301	Carts with SuperGame bankswitch + POKEY chip
302	302	As above + Pokey chip access
303
	303
304	304	GAMES: Commando
305
	305
306	306	-------------------------------------------------*/
307	307
308	308	READ8_MEMBER(a78_rom_sg_pokey_device::read_40xx)
r32760	r32761
312	312	else if (offset < 0x8000)
313	313	return m_rom[(offset & 0x3fff) + (m_bank * 0x4000)];
314	314	else
315		return m_rom[(offset & 0x3fff) + (m_bank_mask * 0x4000)]; // last bank
	315	return m_rom[(offset & 0x3fff) + (m_bank_mask * 0x4000)]; // last bank
316	316	}
317	317
318	318	WRITE8_MEMBER(a78_rom_sg_pokey_device::write_40xx)
r32760	r32761
332	332	/*-------------------------------------------------
333	333
334	334	Carts with SuperGame bankswitch + 16K RAM
335		FIXME: Some games contained only 8K of RAM, but
	335	FIXME: Some games contained only 8K of RAM, but
336	336	for the moment we treat all as 16K of RAM even if
337	337	from softlist we shall differentiate between them.
338
	338
339	339	GAMES: Impossible Mission, Jinks and some protos
340
	340
341	341	-------------------------------------------------*/
342	342
343	343	READ8_MEMBER(a78_rom_sg_ram_device::read_40xx)
r32760	r32761
347	347	else if (offset < 0x8000)
348	348	return m_rom[(offset & 0x3fff) + (m_bank * 0x4000)];
349	349	else
350		return m_rom[(offset & 0x3fff) + (m_bank_mask * 0x4000)]; // last bank
	350	return m_rom[(offset & 0x3fff) + (m_bank_mask * 0x4000)]; // last bank
351	351	}
352	352
353	353	WRITE8_MEMBER(a78_rom_sg_ram_device::write_40xx)
r32760	r32761
364	364	Carts with SuperGame bankswitch 9banks:
365	365	9 x 16K banks mappable in 0x8000-0xbfff
366	366	bank 7 is always mapped in 0xc000-0xffff
367
368		GAMES: Alien Brigade & Crossbow + some homebrew
369		like Donkey Kong XM demo, Bentley Bear's Crystal
	367
	368	GAMES: Alien Brigade & Crossbow + some homebrew
	369	like Donkey Kong XM demo, Bentley Bear's Crystal
370	370	Quest
371
	371
372	372	-------------------------------------------------*/
373	373
374	374	READ8_MEMBER(a78_rom_sg9_device::read_40xx)
r32760	r32761
378	378	else if (offset < 0x8000)
379	379	return m_rom[(offset & 0x3fff) + (m_bank * 0x4000)];
380	380	else
381		return m_rom[(offset & 0x3fff) + ((m_bank_mask + 1) * 0x4000)]; // last bank
	381	return m_rom[(offset & 0x3fff) + ((m_bank_mask + 1) * 0x4000)]; // last bank
382	382	}
383	383
384	384	WRITE8_MEMBER(a78_rom_sg9_device::write_40xx)
r32760	r32761
388	388	}
389	389
390	390	/*-------------------------------------------------
391
	391
392	392	Carts with Absolute bankswitch:
393	393	64K games. Lower 32K are 2 banks of 16K to be mapped
394	394	in 0x4000-0x7fff, depending on the value written
395	395	at 0x8000. Higher 32K are fixed in 0x8000-0xffff
396
	396
397	397	GAMES: F-18 Hornet
398
	398
399	399	-------------------------------------------------*/
400	400
401	401	READ8_MEMBER(a78_rom_abs_device::read_40xx)
r32760	r32761
431	431	0x6000-0x7fff first 8kb of bank 6
432	432	0x8000-0x9fff second 8kb of bank 7
433	433	0xe000-0xffff first 8kb of bank 7
434
	434
435	435	GAMES: Double Dragon, Rampage.
436
	436
437	437	-------------------------------------------------*/
438	438
439	439	READ8_MEMBER(a78_rom_act_device::read_40xx)
r32760	r32761
495	495	{
496	496	return MACHINE_CONFIG_NAME( a78_pokey450 );
497	497	}
498

trunk/src/emu/bus/a7800/xboard.c
r32760	r32761
3	3	/***********************************************************************************************************
4	4
5	5	A7800 XBoarD & XM expansions emulation
6
	6
7	7	The XBoarD should be socketed in the A7800 pcb in place of the Maria chip.
8	8	It adds to the system additional 128K of RAM and an onboard pokey.
9	9	The XM seems to work the same as XBoarD, but it also features HighScore savings
r32760	r32761
12	12
13	13	Currently, we emulate both of these as a passthru cart, even if not 100% accurate for the XBoarD
14	14
15
	15
16	16	Memory map:
17	17
18	18	POKEY1 $0450 $045F 16 bytes
19	19	POKEY2* $0460 $046F 16 bytes
20	20	XCTRL $0470 $047F 1 byte
21	21	RAM $4000 $7FFF 16384 bytes
22
	22
23	23	XCTRL Bit Description
24
	24
25	25	+-------------------------------+
26	26	\| 7 \| 6 \| 5 \| 4 \| 3 \| 2 \| 1 \| 0 \|
27	27	+-------------------------------+
28	28	\| \| \| \| \| \| \| \|
29	29	\| \| \| \| \| \| \| +-- Bank select bit 0 \
30	30	\| \| \| \| \| \| +------ Bank select bit 1 \| Totally 128 KByte in 16 KByte banks
31		\| \| \| \| \| +---------- Bank select bit 2 /
	31	\| \| \| \| \| +---------- Bank select bit 2 /
32	32	\| \| \| \| +-------------- Enable memory bit (1 = Memory enabled, 0 after power on)
33	33	\| \| \| +------------------ Enable POKEY bit** (1 = POKEY enabled, 0 after power on)
34	34	\| \| \|
35	35	NA NA NA = Not Available or Not Used
36
	36
37	37	* = Can be mounted piggy back on the first POKEY. Description how to do this will come when i have tried it out.
38	38	** This bit controls both POKEY chip select signals.
39
	39
40	40	TODO:
41	41	- verify what happens when 2 POKEYs are present
42	42
r32760	r32761
142	142	-------------------------------------------------*/
143	143
144	144	/*-------------------------------------------------
145
	145
146	146	XBoarD: passthru + 128K RAM + POKEY
147
	147
148	148	-------------------------------------------------*/
149	149
150	150	READ8_MEMBER(a78_xboard_device::read_40xx)
r32760	r32761
168	168	if (BIT(m_reg, 4) && offset >= 0x50 && offset < 0x60)
169	169	return m_pokey->read(space, offset & 0x0f);
170	170	else if (BIT(m_reg, 4) && offset >= 0x60 && offset < 0x70)
171		return m_xbslot->read_04xx(space, offset - 0x10); // access second POKEY
	171	return m_xbslot->read_04xx(space, offset - 0x10); // access second POKEY
172	172	else
173	173	return 0xff;
174	174	}
r32760	r32761
178	178	if (BIT(m_reg, 4) && offset >= 0x50 && offset < 0x60)
179	179	m_pokey->write(space, offset & 0x0f, data);
180	180	else if (BIT(m_reg, 4) && offset >= 0x60 && offset < 0x70)
181		m_xbslot->write_04xx(space, offset - 0x10, data); // access second POKEY
	181	m_xbslot->write_04xx(space, offset - 0x10, data); // access second POKEY
182	182	else if (offset >= 0x70 && offset < 0x80)
183	183	{
184	184	m_reg = data;
r32760	r32761
188	188
189	189
190	190	/*-------------------------------------------------
191
	191
192	192	XM: Same as above but also featuring High Score savings
193
	193
194	194	-------------------------------------------------*/
195	195
196	196	READ8_MEMBER(a78_xm_device::read_10xx)
r32760	r32761
215	215	else if (m_ym_enabled && offset >= 0x60 && offset <= 0x61)
216	216	return m_ym->read(space, offset & 1);
217	217	else if (BIT(m_reg, 4) && offset >= 0x60 && offset < 0x70)
218		return m_xbslot->read_04xx(space, offset - 0x10); // access second POKEY
	218	return m_xbslot->read_04xx(space, offset - 0x10); // access second POKEY
219	219	else
220	220	return 0xff;
221	221	}
r32760	r32761
227	227	else if (m_ym_enabled && offset >= 0x60 && offset <= 0x61)
228	228	m_ym->write(space, offset & 1, data);
229	229	else if (BIT(m_reg, 4) && offset >= 0x60 && offset < 0x70)
230		m_xbslot->write_04xx(space, offset - 0x10, data); // access second POKEY
	230	m_xbslot->write_04xx(space, offset - 0x10, data); // access second POKEY
231	231	else if (offset >= 0x70 && offset < 0x80)
232	232	{
233	233	//printf("regs 0x%X\n", data);

trunk/src/emu/bus/a7800/a78_carts.h
r32760	r32761
20	20	SLOT_INTERFACE_INTERNAL("a78_abs", A78_ROM_ABSOLUTE)
21	21	SLOT_INTERFACE_INTERNAL("a78_act", A78_ROM_ACTIVISION)
22	22	SLOT_INTERFACE_INTERNAL("a78_hsc", A78_HISCORE)
23		SLOT_INTERFACE_INTERNAL("a78_xboard", A78_XBOARD) // the actual XBoarD expansion (as passthru)
24		SLOT_INTERFACE_INTERNAL("a78_xm", A78_XM) // the actual XM expansion (as passthru)
25		SLOT_INTERFACE_INTERNAL("a78_megacart", A78_ROM_MEGACART)
26		SLOT_INTERFACE_INTERNAL("a78_versa", A78_ROM_VERSABOARD)
	23	SLOT_INTERFACE_INTERNAL("a78_xboard", A78_XBOARD) // the actual XBoarD expansion (as passthru)
	24	SLOT_INTERFACE_INTERNAL("a78_xm", A78_XM) // the actual XM expansion (as passthru)
	25	SLOT_INTERFACE_INTERNAL("a78_megacart", A78_ROM_MEGACART)
	26	SLOT_INTERFACE_INTERNAL("a78_versa", A78_ROM_VERSABOARD)
27	27	// cart variants with a POKEY at 0x0450 (typically a VersaBoard variant, or an homebrew pcb)
28	28	SLOT_INTERFACE_INTERNAL("a78_p450_t0", A78_ROM_P450)
29	29	SLOT_INTERFACE_INTERNAL("a78_p450_t1", A78_ROM_P450_POKEY)

trunk/src/emu/bus/a7800/a78_slot.c
r32760	r32761
21	21	- read_40xx/write_40xx for accesses in the $4000 to $ffff range
22	22	even if not all carts use all of them (in particular no cart type
23	23	seems to use access to the ranges $0500 to $0fff and $2800 to $2fff)
24
25	24
	25
26	26	***********************************************************************************************************/
27	27
28	28
r32760	r32761
70	70	tempstring.cat(A78SLOT_ROM_REGION_TAG);
71	71	m_rom = device().machine().memory().region_alloc(tempstring, size, 1, ENDIANNESS_LITTLE)->base();
72	72	m_rom_size = size;
73
	73
74	74	// setup other helpers
75	75	if ((size / 0x4000) & 1) // compensate for SuperGame carts with 9 x 16K banks (to my knowledge no other cart has m_bank_mask != power of 2)
76	76	m_bank_mask = (size / 0x4000) - 2;
77	77	else
78	78	m_bank_mask = (size / 0x4000) - 1;
79
	79
80	80	// the rom is mapped to the top of the memory area
81		// so we store the starting point of data to simplify
	81	// so we store the starting point of data to simplify
82	82	// the access handling
83	83	m_base_rom = 0x10000 - size;
84	84	}
r32760	r32761
272	272	}
273	273	head &= 0xff00;
274	274	}
275
	275
276	276	if ((head & 0xff00) > 0x300)
277	277	{
278	278	if (log)
r32760	r32761
282	282	}
283	283	head &= 0x00ff;
284	284	}
285
	285
286	286	return head;
287	287	}
288	288
r32760	r32761
329	329	if (!core_stricmp(slot_list[i].slot_option, slot))
330	330	return slot_list[i].pcb_id;
331	331	}
332
	332
333	333	return 0;
334	334	}
335	335
r32760	r32761
340	340	if (slot_list[i].pcb_id == type)
341	341	return slot_list[i].slot_option;
342	342	}
343
	343
344	344	return "a78_rom";
345	345	}
346	346
r32760	r32761
349	349	if (m_cart)
350	350	{
351	351	UINT32 len;
352
	352
353	353	if (software_entry() != NULL)
354	354	{
355	355	const char *pcb_name;
356	356	bool has_ram = get_software_region("ram") ? TRUE : FALSE;
357	357	bool has_nvram = get_software_region("nvram") ? TRUE : FALSE;
358	358	len = get_software_region_length("rom");
359
	359
360	360	m_cart->rom_alloc(len, tag());
361	361	memcpy(m_cart->get_rom_base(), get_software_region("rom"), len);
362
	362
363	363	if ((pcb_name = get_feature("slot")) != NULL)
364	364	m_type = a78_get_pcb_id(pcb_name);
365	365	else
r32760	r32761
377	377	{
378	378	// Load and check the header
379	379	int mapper;
380		char head[128];
	380	char head[128];
381	381	fread(head, 128);
382
	382
383	383	if (verify_header((char *)head) == IMAGE_VERIFY_FAIL)
384	384	return IMAGE_INIT_FAIL;
385
	385
386	386	len = (head[49] << 24) \| (head[50] << 16) \| (head[51] << 8) \| head[52];
387	387	if (len + 128 > length())
388	388	{
389	389	logerror("Invalid length in the header. The game might be corrupted.\n");
390	390	len = length() - 128;
391	391	}
392
	392
393	393	// let's try to auto-fix some common errors in the header
394	394	mapper = validate_header((head[53] << 8) \| head[54], TRUE);
395	395
r32760	r32761
415	415	m_type = A78_VERSABOARD;
416	416	break;
417	417	}
418
	418
419	419	// check if cart has a POKEY at $0450 (typically a VersaBoard variant)!
420	420	if (mapper & 0x40)
421	421	{
r32760	r32761
425	425	m_type += A78_POKEY0450;
426	426	}
427	427	}
428
	428
429	429	// check special bits, which override the previous
430	430	if ((mapper & 0xff00) == 0x0100)
431	431	m_type = A78_ACTIVISION;
r32760	r32761
452	452	}
453	453
454	454	internal_header_logging((UINT8 *)head, length());
455
	455
456	456	m_cart->rom_alloc(len, tag());
457	457	fread(m_cart->get_rom_base(), len);
458
	458
459	459	if (m_type == A78_TYPE6)
460	460	m_cart->ram_alloc(0x4000);
461	461	if (m_type == A78_MEGACART \|\| (m_type >= A78_VERSABOARD && m_type <= A78_VERSA_POK450))
r32760	r32761
468	468	battery_load(m_cart->get_nvram_base(), 0x800, 0xff);
469	469	}
470	470	}
471
	471
472	472	//printf("Type: %s\n", a78_get_slot(m_type));
473	473	}
474	474	return IMAGE_INIT_PASS;
r32760	r32761
476	476
477	477
478	478	void a78_partialhash(hash_collection &dest, const unsigned char *data,
479		unsigned long length, const char *functions)
	479	unsigned long length, const char *functions)
480	480	{
481	481	if (length <= 128)
482	482	return;
r32760	r32761
537	537	const char *slot_string = "a78_rom";
538	538	dynamic_buffer head(128);
539	539	int type = A78_TYPE0, mapper;
540
	540
541	541	// Load and check the header
542		core_fread(m_file, head, 128);
	542	core_fread(m_file, head, 128);
543	543
544	544	// let's try to auto-fix some common errors in the header
545	545	mapper = validate_header((head[53] << 8) \| head[54], FALSE);
546
	546
547	547	switch (mapper & 0x2e)
548	548	{
549	549	case 0x0000:
r32760	r32761
566	566	type = A78_VERSABOARD;
567	567	break;
568	568	}
569
	569
570	570	// check if cart has a POKEY at $0450 (typically a VersaBoard variant)!
571	571	if (mapper & 0x40)
572	572	{
r32760	r32761
576	576	type += A78_POKEY0450;
577	577	}
578	578	}
579
	579
580	580	// check special bits, which override the previous
581	581	if ((mapper & 0xff00) == 0x0100)
582	582	type = A78_ACTIVISION;
583	583	else if ((mapper & 0xff00) == 0x0200)
584	584	type = A78_ABSOLUTE;
585
	585
586	586	logerror("Cart type: %x\n", type);
587	587	slot_string = a78_get_slot(type);
588
	588
589	589	clear();
590
	590
591	591	result.cpy(slot_string);
592	592	}
593	593	else
r32760	r32761
663	663
664	664	/*-------------------------------------------------
665	665	A78 header logging
666
	666
667	667	A78 HEADER FORMAT
668
	668
669	669	Bytes \| Content \| Length
670	670	========================================
671	671	0 \| Header version \| 1 byte
r32760	r32761
679	679	53..54 \| Cart type [*] \| 2 bytes
680	680	-------\|-------------------\|------------
681	681	55 \| Controller 1 type \| 1 byte
682		\| \|
	682	\| \|
683	683	\| 0 = None \|
684	684	\| 1 = Joystick \|
685	685	\| 2 = Light Gun \|
r32760	r32761
690	690	-------\|-------------------\|------------
691	691	57 \| TV System \| 1 byte
692	692	\| \|
693		\| 0 = NTSC/1 = PAL \|
	693	\| 0 = NTSC/1 = PAL \|
694	694	-------\|-------------------\|------------
695	695	58 \| Save data \| 1 byte
696	696	\| \| (only v2)
697	697	\| 0 = None / Unk \|
698	698	\| 1 = High Score \|
699	699	\| 2 = Savekey \|
700		-------\|-------------------\|-----------
	700	-------\|-------------------\|-----------
701	701	63 \| Expansion module \| 1 byte
702	702	\| \|
703	703	\| 0 = No expansion \|
704	704	\| module \|
705	705	\| 1 = Expansion \|
706	706	\| required \|
707		-------\|-------------------\|-----------
708
709
	707	-------\|-------------------\|-----------
	708
	709
710	710	[*] Cart type:
711	711
712	712	bit 0-7 - Hardware "flags"
r32760	r32761
716	716	bit 3 [0x08] - bank 0 of 144K ROM at $4000
717	717	bit 4 [0x10] - bank 6 at $4000
718	718	bit 5 [0x20] - banked RAM at $4000
719
	719
720	720	bit 8-15 - Special values
721	721	0 = Normal cart
722	722	1 = Absolute (F18 Hornet)
723	723	2 = Activision (Double Dragon & Rampage)
724	724	3 = POKEY at $0450
725
	725
726	726	-------------------------------------------------*/
727	727
728	728	void a78_cart_slot_device::internal_header_logging(UINT8 *header, UINT32 len)
r32760	r32761
788	788	ctrl1.cpy("Unknown controller");
789	789	break;
790	790	}
791
	791
792	792	switch (head_ctrl2)
793	793	{
794	794	case 0x00:
r32760	r32761
804	804	ctrl2.cpy("Unknown controller");
805	805	break;
806	806	}
807
	807
808	808	logerror( "ROM DETAILS\n" );
809	809	logerror( "===========\n\n" );
810		logerror( "\tTotal length (with header): 0x%x (%dK + 128b header)\n\n", len, len/0x400);
	810	logerror( "\tTotal length (with header): 0x%x (%dK + 128b header)\n\n", len, len/0x400);
811	811	logerror( "HEADER DETAILS\n" );
812	812	logerror( "==============\n\n" );
813	813	logerror( "\tTitle: %.32s\n", head_title);
r32760	r32761
829	829	logerror( "\n");
830	830	logerror( "\tController 1: 0x%.2X [%s]\n", head_ctrl1, ctrl1.cstr());
831	831	logerror( "\tController 2: 0x%.2X [%s]\n", head_ctrl2, ctrl2.cstr());
832		logerror( "\tVideo: %s\n", (head_ispal) ? "PAL" : "NTSC");
	832	logerror( "\tVideo: %s\n", (head_ispal) ? "PAL" : "NTSC");
833	833	}

trunk/src/emu/bus/a7800/cpuwiz.c
r32760	r32761
3	3	/***********************************************************************************************************
4	4
5	5	A7800 CPUWIZ's homebrew boards (MegaCart+ and VersaBoard)
6
	6
7	7	Here we emulate the base configurations of these two boards:
8	8
9	9	MegaCart+ = up to 512K (31 banks at $8000, 1 at $C000) of ROM and 2 x 16K RAM @ $4000
10	10	VersaBoard = up to 256K of ROM and 2 x 16K RAM
11
12		Plus, for the moment, a VersaBoard with POKEY mapped at 0x0450 and support for 144K ROM,
13		since a few demo homebrew programs seems to use this to combine compatibility with
	11
	12	Plus, for the moment, a VersaBoard with POKEY mapped at 0x0450 and support for 144K ROM,
	13	since a few demo homebrew programs seems to use this to combine compatibility with
14	14	XBoarD & XM expansions
15	15
16	16	Note that the VersaBoard can be configured to work with different banking hardware
17	17	e.g. with SG 9bank games or with SG + RAM (so to allow reproduction of games which
18		could have worked on old carts without sacrifying original carts), but games running
	18	could have worked on old carts without sacrifying original carts), but games running
19	19	on those "standard" variants can be emulated with the standard code from rom.c ;-)
20
21
	20
	21
22	22	TO DO:
23	23	- investigate whether the POKEY detection routines in homebrew do fail due to emulation
24	24	issues or not
25
	25
26	26	***********************************************************************************************************/
27	27
28	28
r32760	r32761
86	86	else if (offset < 0x8000)
87	87	return m_rom[(offset & 0x3fff) + (m_bank * 0x4000)];
88	88	else
89		return m_rom[(offset & 0x3fff) + (m_bank_mask * 0x4000)]; // last bank
	89	return m_rom[(offset & 0x3fff) + (m_bank_mask * 0x4000)]; // last bank
90	90	}
91	91
92	92	WRITE8_MEMBER(a78_versaboard_device::write_40xx)
r32760	r32761
130	130	{
131	131	return MACHINE_CONFIG_NAME( a78_pokeyvb );
132	132	}
133
134

trunk/src/emu/bus/a7800/hiscore.h
r32760	r32761
14	14	public:
15	15	// construction/destruction
16	16	a78_hiscore_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
17
	17
18	18	// device-level overrides
19	19	virtual machine_config_constructor device_mconfig_additions() const;
20
	20
21	21	// reading and writing
22	22	virtual DECLARE_READ8_MEMBER(read_04xx);
23	23	virtual DECLARE_WRITE8_MEMBER(write_04xx);

trunk/src/emu/bus/a7800/rom.h
r32760	r32761
34	34	// construction/destruction
35	35	a78_rom_pokey_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source);
36	36	a78_rom_pokey_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
37
	37
38	38	// device-level overrides
39	39	virtual machine_config_constructor device_mconfig_additions() const;
40
	40
41	41	// reading and writing
42	42	virtual DECLARE_READ8_MEMBER(read_40xx);
43	43	virtual DECLARE_WRITE8_MEMBER(write_40xx);
44
	44
45	45	protected:
46	46	required_device<pokey_device> m_pokey;
47	47	};
r32760	r32761
55	55	// construction/destruction
56	56	a78_rom_sg_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source);
57	57	a78_rom_sg_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
58
	58
59	59	// device-level overrides
60	60	virtual void device_start();
61	61	virtual void device_reset();
62
	62
63	63	// reading and writing
64	64	virtual DECLARE_READ8_MEMBER(read_40xx);
65	65	virtual DECLARE_WRITE8_MEMBER(write_40xx);
r32760	r32761
76	76	public:
77	77	// construction/destruction
78	78	a78_rom_sg_pokey_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
79
	79
80	80	// device-level overrides
81	81	virtual machine_config_constructor device_mconfig_additions() const;
82
	82
83	83	// reading and writing
84	84	virtual DECLARE_READ8_MEMBER(read_40xx);
85	85	virtual DECLARE_WRITE8_MEMBER(write_40xx);
86
	86
87	87	protected:
88	88	required_device<pokey_device> m_pokey;
89	89	};
r32760	r32761
97	97	// construction/destruction
98	98	a78_rom_sg_ram_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source);
99	99	a78_rom_sg_ram_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
100
	100
101	101	// reading and writing
102	102	virtual DECLARE_READ8_MEMBER(read_40xx);
103	103	virtual DECLARE_WRITE8_MEMBER(write_40xx);
r32760	r32761
112	112	// construction/destruction
113	113	a78_rom_sg9_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source);
114	114	a78_rom_sg9_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
115
	115
116	116	// reading and writing
117	117	virtual DECLARE_READ8_MEMBER(read_40xx);
118	118	virtual DECLARE_WRITE8_MEMBER(write_40xx);
r32760	r32761
126	126	public:
127	127	// construction/destruction
128	128	a78_rom_abs_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
129
	129
130	130	// device-level overrides
131	131	virtual void device_start();
132	132	virtual void device_reset();
133
	133
134	134	// reading and writing
135	135	virtual DECLARE_READ8_MEMBER(read_40xx);
136	136	virtual DECLARE_WRITE8_MEMBER(write_40xx);
137
	137
138	138	protected:
139	139	int m_bank;
140	140	};
r32760	r32761
147	147	public:
148	148	// construction/destruction
149	149	a78_rom_act_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
150
	150
151	151	// device-level overrides
152	152	virtual void device_start();
153	153	virtual void device_reset();
154
	154
155	155	// reading and writing
156	156	virtual DECLARE_READ8_MEMBER(read_40xx);
157	157	virtual DECLARE_WRITE8_MEMBER(write_40xx);
158
	158
159	159	protected:
160	160	int m_bank;
161	161	};
r32760	r32761
170	170	public:
171	171	// construction/destruction
172	172	a78_rom_p450_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
173
	173
174	174	virtual machine_config_constructor device_mconfig_additions() const;
175
	175
176	176	// reading and writing
177	177	virtual DECLARE_READ8_MEMBER(read_04xx) { if (offset >= 0x50 && offset < 0x60) return m_pokey450->read(space, offset & 0x0f); else return 0xff; }
178	178	virtual DECLARE_WRITE8_MEMBER(write_04xx) { if (offset >= 0x50 && offset < 0x60) m_pokey450->write(space, offset & 0x0f, data); }
179
	179
180	180	protected:
181	181	required_device<pokey_device> m_pokey450;
182	182	};
r32760	r32761
189	189	public:
190	190	// construction/destruction
191	191	a78_rom_p450_pokey_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
192
	192
193	193	virtual machine_config_constructor device_mconfig_additions() const;
194
	194
195	195	// reading and writing
196	196	virtual DECLARE_READ8_MEMBER(read_04xx) { if (offset >= 0x50 && offset < 0x60) return m_pokey450->read(space, offset & 0x0f); else return 0xff; }
197	197	virtual DECLARE_WRITE8_MEMBER(write_04xx) { if (offset >= 0x50 && offset < 0x60) m_pokey450->write(space, offset & 0x0f, data); }
198
	198
199	199	protected:
200	200	required_device<pokey_device> m_pokey450;
201	201	};
r32760	r32761
208	208	public:
209	209	// construction/destruction
210	210	a78_rom_p450_sg_ram_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
211
	211
212	212	virtual machine_config_constructor device_mconfig_additions() const;
213
	213
214	214	// reading and writing
215	215	virtual DECLARE_READ8_MEMBER(read_04xx) { if (offset >= 0x50 && offset < 0x60) return m_pokey450->read(space, offset & 0x0f); else return 0xff; }
216	216	virtual DECLARE_WRITE8_MEMBER(write_04xx) { if (offset >= 0x50 && offset < 0x60) m_pokey450->write(space, offset & 0x0f, data); }
217
	217
218	218	protected:
219	219	required_device<pokey_device> m_pokey450;
220	220	};
r32760	r32761
227	227	public:
228	228	// construction/destruction
229	229	a78_rom_p450_sg9_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
230
	230
231	231	virtual machine_config_constructor device_mconfig_additions() const;
232	232
233	233	// reading and writing
234	234	virtual DECLARE_READ8_MEMBER(read_04xx) { if (offset >= 0x50 && offset < 0x60) return m_pokey450->read(space, offset & 0x0f); else return 0xff; }
235	235	virtual DECLARE_WRITE8_MEMBER(write_04xx) { if (offset >= 0x50 && offset < 0x60) m_pokey450->write(space, offset & 0x0f, data); }
236
	236
237	237	protected:
238	238	required_device<pokey_device> m_pokey450;
239	239	};

trunk/src/emu/bus/msx_slot/disk.c
r32760	r32761
677	677
678	678	void msx_slot_disk6_device::select_drive()
679	679	{
680		if (m_drive_select1)
	680	if (m_drive_select1)
681	681	{
682	682	m_floppy = m_floppy1 ? m_floppy1->get_device() : NULL;
683	683	if (!m_floppy)
r32760	r32761
809	809	break;
810	810	}
811	811	}
812

trunk/src/emu/bus/isa/trident.c
r32760	r32761
45	45	UINT16 trident_vga_device::READPIXEL15(INT16 x, INT16 y)
46	46	{
47	47	return (vga.memory[((y & 0xfff)offset() + (x & 0xfff)2) % vga.svga_intf.vram_size] \|
48		(vga.memory[((y & 0xfff)offset() + ((x & 0xfff)2)+1) % vga.svga_intf.vram_size] << 8));
	48	(vga.memory[((y & 0xfff)offset() + ((x & 0xfff)2)+1) % vga.svga_intf.vram_size] << 8));
49	49	}
50	50
51	51	UINT16 trident_vga_device::READPIXEL16(INT16 x, INT16 y)
52	52	{
53	53	return (vga.memory[((y & 0xfff)offset() + (x & 0xfff)2) % vga.svga_intf.vram_size] \|
54		(vga.memory[((y & 0xfff)offset() + ((x & 0xfff)2)+1) % vga.svga_intf.vram_size] << 8));
	54	(vga.memory[((y & 0xfff)offset() + ((x & 0xfff)2)+1) % vga.svga_intf.vram_size] << 8));
55	55	}
56	56
57	57	UINT32 trident_vga_device::READPIXEL32(INT16 x, INT16 y)
58	58	{
59	59	return (vga.memory[((y & 0xfff)offset() + (x & 0xfff)4) % vga.svga_intf.vram_size] \|
60		(vga.memory[((y & 0xfff)offset() + ((x & 0xfff)4)+1) % vga.svga_intf.vram_size] << 8) \|
61		(vga.memory[((y & 0xfff)offset() + ((x & 0xfff)4)+2) % vga.svga_intf.vram_size] << 16) \|
62		(vga.memory[((y & 0xfff)offset() + ((x & 0xfff)4)+3) % vga.svga_intf.vram_size] << 24));
	60	(vga.memory[((y & 0xfff)offset() + ((x & 0xfff)4)+1) % vga.svga_intf.vram_size] << 8) \|
	61	(vga.memory[((y & 0xfff)offset() + ((x & 0xfff)4)+2) % vga.svga_intf.vram_size] << 16) \|
	62	(vga.memory[((y & 0xfff)offset() + ((x & 0xfff)4)+3) % vga.svga_intf.vram_size] << 24));
63	63	}
64	64
65	65	void trident_vga_device::WRITEPIXEL8(INT16 x, INT16 y, UINT8 data)
r32760	r32761
249	249	for(x=0;x<cursor_size;x++)
250	250	{
251	251	UINT32 bitb = (vga.memory[(src+3) % vga.svga_intf.vram_size]
252		\| ((vga.memory[(src+2) % vga.svga_intf.vram_size]) << 8)
253		\| ((vga.memory[(src+1) % vga.svga_intf.vram_size]) << 16)
254		\| ((vga.memory[(src+0) % vga.svga_intf.vram_size]) << 24));
	252	\| ((vga.memory[(src+2) % vga.svga_intf.vram_size]) << 8)
	253	\| ((vga.memory[(src+1) % vga.svga_intf.vram_size]) << 16)
	254	\| ((vga.memory[(src+0) % vga.svga_intf.vram_size]) << 24));
255	255	UINT32 bita = (vga.memory[(src+7) % vga.svga_intf.vram_size]
256	256	\| ((vga.memory[(src+6) % vga.svga_intf.vram_size]) << 8)
257	257	\| ((vga.memory[(src+5) % vga.svga_intf.vram_size]) << 16)
r32760	r32761
1131	1131	/*
1132	1132	Graphics Engine for 9440/9660/9680
1133	1133
1134		#define GER_STATUS 0x2120
1135		#define GE_BUSY 0x80
1136		#define GER_OPERMODE 0x2122 Byte for 9440, Word for 96xx
1137		#define DST_ENABLE 0x200 // Destination Transparency
1138		#define GER_COMMAND 0x2124
1139		#define GE_NOP 0x00 // No Operation
1140		#define GE_BLT 0x01 // BitBLT ROP3 only
1141		#define GE_BLT_ROP4 0x02 // BitBLT ROP4 (96xx only)
1142		#define GE_SCANLINE 0x03 // Scan Line
1143		#define GE_BRESLINE 0x04 // Bresenham Line
1144		#define GE_SHVECTOR 0x05 // Short Vector
1145		#define GE_FASTLINE 0x06 // Fast Line (96xx only)
1146		#define GE_TRAPEZ 0x07 // Trapezoidal fill (96xx only)
1147		#define GE_ELLIPSE 0x08 // Ellipse (96xx only) (RES)
1148		#define GE_ELLIP_FILL 0x09 // Ellipse Fill (96xx only) (RES)
1149		#define GER_FMIX 0x2127
1150		#define GER_DRAWFLAG 0x2128 // long
1151		#define FASTMODE 1<<28
1152		#define STENCIL 0x8000
1153		#define SOLIDFILL 0x4000
1154		#define TRANS_ENABLE 0x1000
1155		#define TRANS_REVERSE 0x2000
1156		#define YMAJ 0x0400
1157		#define XNEG 0x0200
1158		#define YNEG 0x0100
1159		#define SRCMONO 0x0040
1160		#define PATMONO 0x0020
1161		#define SCR2SCR 0x0004
1162		#define PAT2SCR 0x0002
1163		#define GER_FCOLOUR 0x212C // Word for 9440, long for 96xx
1164		#define GER_BCOLOUR 0x2130 // Word for 9440, long for 96xx
1165		#define GER_PATLOC 0x2134 // Word
1166		#define GER_DEST_XY 0x2138
1167		#define GER_DEST_X 0x2138 // Word
1168		#define GER_DEST_Y 0x213A // Word
1169		#define GER_SRC_XY 0x213C
1170		#define GER_SRC_X 0x213C // Word
1171		#define GER_SRC_Y 0x213E // Word
1172		#define GER_DIM_XY 0x2140
1173		#define GER_DIM_X 0x2140 // Word
1174		#define GER_DIM_Y 0x2142 // Word
1175		#define GER_STYLE 0x2144 // Long
1176		#define GER_CKEY 0x2168 // Long
1177		#define GER_FPATCOL 0x2178
1178		#define GER_BPATCOL 0x217C
1179		#define GER_PATTERN 0x2180 // from 0x2180 to 0x21FF
	1134	#define GER_STATUS 0x2120
	1135	#define GE_BUSY 0x80
	1136	#define GER_OPERMODE 0x2122 Byte for 9440, Word for 96xx
	1137	#define DST_ENABLE 0x200 // Destination Transparency
	1138	#define GER_COMMAND 0x2124
	1139	#define GE_NOP 0x00 // No Operation
	1140	#define GE_BLT 0x01 // BitBLT ROP3 only
	1141	#define GE_BLT_ROP4 0x02 // BitBLT ROP4 (96xx only)
	1142	#define GE_SCANLINE 0x03 // Scan Line
	1143	#define GE_BRESLINE 0x04 // Bresenham Line
	1144	#define GE_SHVECTOR 0x05 // Short Vector
	1145	#define GE_FASTLINE 0x06 // Fast Line (96xx only)
	1146	#define GE_TRAPEZ 0x07 // Trapezoidal fill (96xx only)
	1147	#define GE_ELLIPSE 0x08 // Ellipse (96xx only) (RES)
	1148	#define GE_ELLIP_FILL 0x09 // Ellipse Fill (96xx only) (RES)
	1149	#define GER_FMIX 0x2127
	1150	#define GER_DRAWFLAG 0x2128 // long
	1151	#define FASTMODE 1<<28
	1152	#define STENCIL 0x8000
	1153	#define SOLIDFILL 0x4000
	1154	#define TRANS_ENABLE 0x1000
	1155	#define TRANS_REVERSE 0x2000
	1156	#define YMAJ 0x0400
	1157	#define XNEG 0x0200
	1158	#define YNEG 0x0100
	1159	#define SRCMONO 0x0040
	1160	#define PATMONO 0x0020
	1161	#define SCR2SCR 0x0004
	1162	#define PAT2SCR 0x0002
	1163	#define GER_FCOLOUR 0x212C // Word for 9440, long for 96xx
	1164	#define GER_BCOLOUR 0x2130 // Word for 9440, long for 96xx
	1165	#define GER_PATLOC 0x2134 // Word
	1166	#define GER_DEST_XY 0x2138
	1167	#define GER_DEST_X 0x2138 // Word
	1168	#define GER_DEST_Y 0x213A // Word
	1169	#define GER_SRC_XY 0x213C
	1170	#define GER_SRC_X 0x213C // Word
	1171	#define GER_SRC_Y 0x213E // Word
	1172	#define GER_DIM_XY 0x2140
	1173	#define GER_DIM_X 0x2140 // Word
	1174	#define GER_DIM_Y 0x2142 // Word
	1175	#define GER_STYLE 0x2144 // Long
	1176	#define GER_CKEY 0x2168 // Long
	1177	#define GER_FPATCOL 0x2178
	1178	#define GER_BPATCOL 0x217C
	1179	#define GER_PATTERN 0x2180 // from 0x2180 to 0x21FF
1180	1180
1181	1181	Additional - Graphics Engine for 96xx
1182		#define GER_SRCCLIP_XY 0x2148
1183		#define GER_SRCCLIP_X 0x2148 // Word
1184		#define GER_SRCCLIP_Y 0x214A // Word
1185		#define GER_DSTCLIP_XY 0x214C
1186		#define GER_DSTCLIP_X 0x214C // Word
1187		#define GER_DSTCLIP_Y 0x214E // Word
	1182	#define GER_SRCCLIP_XY 0x2148
	1183	#define GER_SRCCLIP_X 0x2148 // Word
	1184	#define GER_SRCCLIP_Y 0x214A // Word
	1185	#define GER_DSTCLIP_XY 0x214C
	1186	#define GER_DSTCLIP_X 0x214C // Word
	1187	#define GER_DSTCLIP_Y 0x214E // Word
1188	1188	*/
1189	1189
1190	1190	READ8_MEMBER(trident_vga_device::accel_r)

trunk/src/emu/bus/isa/svga_trident.c
r32760	r32761
87	87	m_isa->install_memory(0xa0000, 0xbffff, 0, 0, read8_delegate(FUNC(trident_vga_device::mem_r),m_vga), write8_delegate(FUNC(trident_vga_device::mem_w),m_vga));
88	88
89	89	// uncomment to test Windows 3.1 TGUI9440AGi driver
90		// m_isa->install_memory(0x4400000, 0x45fffff, 0, 0, read8_delegate(FUNC(trident_vga_device::vram_r),m_vga), write8_delegate(FUNC(trident_vga_device::vram_w),m_vga));
	90	// m_isa->install_memory(0x4400000, 0x45fffff, 0, 0, read8_delegate(FUNC(trident_vga_device::vram_r),m_vga), write8_delegate(FUNC(trident_vga_device::vram_w),m_vga));
91	91
92	92	// win95 drivers
93		// m_isa->install_memory(0x4000000, 0x41fffff, 0, 0, read8_delegate(FUNC(trident_vga_device::vram_r),m_vga), write8_delegate(FUNC(trident_vga_device::vram_w),m_vga));
	93	// m_isa->install_memory(0x4000000, 0x41fffff, 0, 0, read8_delegate(FUNC(trident_vga_device::vram_r),m_vga), write8_delegate(FUNC(trident_vga_device::vram_w),m_vga));
94	94
95	95	// acceleration ports
96	96	m_isa->install_device(0x2120, 0x21ff, 0, 0, read8_delegate(FUNC(trident_vga_device::accel_r),m_vga), write8_delegate(FUNC(trident_vga_device::accel_w),m_vga));

trunk/src/emu/bus/isa/sb16.c
r32760	r32761
370	370
371	371	static ADDRESS_MAP_START(sb16_io, AS_IO, 8, sb16_lle_device)
372	372	AM_RANGE(0x0000, 0x0000) AM_MIRROR(0xff00) AM_READWRITE(dsp_data_r, dsp_data_w)
373		// AM_RANGE(0x0001, 0x0001) // MIDI related?
374		// AM_RANGE(0x0002, 0x0002)
	373	// AM_RANGE(0x0001, 0x0001) // MIDI related?
	374	// AM_RANGE(0x0002, 0x0002)
375	375	AM_RANGE(0x0004, 0x0004) AM_MIRROR(0xff00) AM_READWRITE(mode_r, mode_w)
376	376	AM_RANGE(0x0005, 0x0005) AM_MIRROR(0xff00) AM_READWRITE(dac_ctrl_r, dac_ctrl_w)
377	377	AM_RANGE(0x0006, 0x0006) AM_MIRROR(0xff00) AM_READ(dma_stat_r)
378		// AM_RANGE(0x0007, 0x0007) // unknown
	378	// AM_RANGE(0x0007, 0x0007) // unknown
379	379	AM_RANGE(0x0008, 0x0008) AM_MIRROR(0xff00) AM_READWRITE(ctrl8_r, ctrl8_w)
380	380	AM_RANGE(0x0009, 0x0009) AM_MIRROR(0xff00) AM_WRITE(rate_w)
381	381	AM_RANGE(0x000A, 0x000A) AM_MIRROR(0xff00) AM_READ(dma8_cnt_lo_r)
r32760	r32761
393	393	AM_RANGE(0x001B, 0x001B) AM_MIRROR(0xff00) AM_READ(adc_data_r)
394	394	AM_RANGE(0x001D, 0x001D) AM_MIRROR(0xff00) AM_WRITE(dma8_w)
395	395	AM_RANGE(0x001F, 0x001F) AM_MIRROR(0xff00) AM_READ(dma8_r)
396		// AM_RANGE(0x0080, 0x0080) // ASP comms
397		// AM_RANGE(0x0081, 0x0081)
398		// AM_RANGE(0x0082, 0x0082)
	396	// AM_RANGE(0x0080, 0x0080) // ASP comms
	397	// AM_RANGE(0x0081, 0x0081)
	398	// AM_RANGE(0x0082, 0x0082)
399	399	AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READWRITE(p1_r, p1_w)
400	400	AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_READWRITE(p2_r, p2_w)
401	401	ADDRESS_MAP_END

trunk/src/emu/bus/msx_cart/disk.c
r32760	r32761
164	164
165	165
166	166	msx_cart_fscf351::msx_cart_fscf351(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
167		: msx_cart_disk_type2(mconfig, MSX_CART_FSCF351, "MSX Cartridge - FS-CF351", tag, owner, clock, "msx_cart_fscf351")
	167	: msx_cart_disk_type2(mconfig, MSX_CART_FSCF351, "MSX Cartridge - FS-CF351", tag, owner, clock, "msx_cart_fscf351")
168	168	{
169	169	}
170	170
r32760	r32761
624	624	break;
625	625	}
626	626	}
627

trunk/src/emu/bus/intv/rom.c
r32760	r32761
47	47	: intv_rom_device(mconfig, INTV_ROM_WSMLB, "Intellivision World Series Baseball Cart", tag, owner, clock, "intv_wsmlb", __FILE__)
48	48	{
49	49	}
50

trunk/src/emu/bus/intv/ecs.h
r32760	r32761
14	14	public:
15	15	// construction/destruction
16	16	intv_ecs_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
17
	17
18	18	// device-level overrides
19	19	virtual void device_start();
20	20	virtual void device_reset();
21	21	virtual machine_config_constructor device_mconfig_additions() const;
22	22	virtual ioport_constructor device_input_ports() const;
23	23	virtual const rom_entry *device_rom_region() const;
24
	24
25	25	// reading and writing
26	26
27	27	// actual ECS accesses
r32760	r32761
32	32	virtual DECLARE_READ16_MEMBER(read_romf0);
33	33	// RAM
34	34	virtual DECLARE_READ16_MEMBER(read_ram) { return (int)m_ram[offset & (m_ram.count() - 1)]; }
35		virtual DECLARE_WRITE16_MEMBER(write_ram) { m_ram[offset & (m_ram.count() - 1)] = data & 0xff; }
	35	virtual DECLARE_WRITE16_MEMBER(write_ram) { m_ram[offset & (m_ram.count() - 1)] = data & 0xff; }
36	36	// AY8914
37	37	virtual DECLARE_READ16_MEMBER(read_ay);
38	38	virtual DECLARE_WRITE16_MEMBER(write_ay);
39	39	DECLARE_READ8_MEMBER(ay_porta_r);
40	40	DECLARE_READ8_MEMBER(ay_portb_r);
41	41	DECLARE_WRITE8_MEMBER(ay_porta_w);
42
	42
43	43	// passthru accesses
44	44	virtual DECLARE_READ16_MEMBER(read_rom04) { return m_subslot->read_rom04(space, offset, mem_mask); }
45	45	virtual DECLARE_READ16_MEMBER(read_rom40) { return m_subslot->read_rom40(space, offset, mem_mask); }
r32760	r32761
47	47	virtual DECLARE_READ16_MEMBER(read_rom50) { return m_subslot->read_rom50(space, offset, mem_mask); }
48	48	virtual DECLARE_READ16_MEMBER(read_rom60) { return m_subslot->read_rom60(space, offset, mem_mask); }
49	49	virtual DECLARE_READ16_MEMBER(read_rom80)
50		{
	50	{
51	51	if (m_ram88_enabled && offset >= 0x800)
52		return m_subslot->read_ram(space, offset & 0x7ff, mem_mask);
	52	return m_subslot->read_ram(space, offset & 0x7ff, mem_mask);
53	53	else
54		return m_subslot->read_rom80(space, offset, mem_mask);
	54	return m_subslot->read_rom80(space, offset, mem_mask);
55	55	}
56	56	virtual DECLARE_READ16_MEMBER(read_rom90) { return m_subslot->read_rom90(space, offset, mem_mask); }
57	57	virtual DECLARE_READ16_MEMBER(read_roma0) { return m_subslot->read_roma0(space, offset, mem_mask); }
58	58	virtual DECLARE_READ16_MEMBER(read_romb0) { return m_subslot->read_romb0(space, offset, mem_mask); }
59	59	virtual DECLARE_READ16_MEMBER(read_romc0) { return m_subslot->read_romc0(space, offset, mem_mask); }
60		virtual DECLARE_READ16_MEMBER(read_romd0)
61		{
	60	virtual DECLARE_READ16_MEMBER(read_romd0)
	61	{
62	62	if (m_ramd0_enabled && offset < 0x800)
63		return m_subslot->read_ram(space, offset, mem_mask);
	63	return m_subslot->read_ram(space, offset, mem_mask);
64	64	else
65		return m_subslot->read_romd0(space, offset, mem_mask);
	65	return m_subslot->read_romd0(space, offset, mem_mask);
66	66	}
67	67
68	68	// paged ROM banking
69		virtual DECLARE_WRITE16_MEMBER(write_rom20)
70		{
	69	virtual DECLARE_WRITE16_MEMBER(write_rom20)
	70	{
71	71	if (offset == 0xfff)
72	72	{
73	73	if (data == 0x2a50)
r32760	r32761
76	76	m_bank_base[2] = 1;
77	77	}
78	78	}
79		virtual DECLARE_WRITE16_MEMBER(write_rom70)
80		{
	79	virtual DECLARE_WRITE16_MEMBER(write_rom70)
	80	{
81	81	if (offset == 0xfff)
82	82	{
83	83	if (data == 0x7a50)
r32760	r32761
86	86	m_bank_base[7] = 1;
87	87	}
88	88	}
89		virtual DECLARE_WRITE16_MEMBER(write_rome0)
90		{
	89	virtual DECLARE_WRITE16_MEMBER(write_rome0)
	90	{
91	91	if (offset == 0xfff)
92	92	{
93	93	if (data == 0xea50)
r32760	r32761
96	96	m_bank_base[14] = 1;
97	97	}
98	98	}
99		virtual DECLARE_WRITE16_MEMBER(write_romf0)
100		{
	99	virtual DECLARE_WRITE16_MEMBER(write_romf0)
	100	{
101	101	if (offset == 0xfff)
102	102	{
103	103	if (data == 0xfa50)
r32760	r32761
112	112	// IntelliVoice passthru
113	113	virtual DECLARE_READ16_MEMBER(read_speech) { if (m_voice_enabled) return m_subslot->read_speech(space, offset, mem_mask); else return 0xffff; }
114	114	virtual DECLARE_WRITE16_MEMBER(write_speech) { if (m_voice_enabled) m_subslot->write_speech(space, offset, data, mem_mask); }
115
	115
116	116	virtual void late_subslot_setup();
117	117
118	118	UINT8 intv_control_r(int hand);
119
	119
120	120	private:
121	121
122	122	required_device<ay8914_device> m_snd;

trunk/src/emu/bus/intv/slot.c
r32760	r32761
3	3	Mattel Intellivision cart emulation
4	4	(through slot devices)
5	5
6
	6
7	7	This is a strange beast, because INTV carts had potentially access to
8	8	a LOT of memory ranges!
9	9	Quoting Joe Zbiciak's documentation for his emu (jzIntv):
10
11
	10
	11
12	12	The Intellivision leaves many addresses available to cartridges. However,
13	13	several address ranges come with caveats, such as interactions with other
14		devices in the system, or incompatibilities with various peripherals.
15
	14	devices in the system, or incompatibilities with various peripherals.
	15
16	16	Below is a summary.
17
	17
18	18	ADDRESSES NOTES
19	19	-------------- --------------------------------------------------------------
20	20	$0400 - $04FF RAM/ROM ok on all but Intellivision 2.
r32760	r32761
26	26	$4800 ROM ok. RAM ok only if boot ROM at $7000.
27	27	$4801 - $4FFF RAM/ROM ok.
28	28	$5000 - $5014 ROM ok. RAM ok only if boot ROM at $7000 or $4800.
29		$5015 - $6FFF RAM/ROM ok.
	29	$5015 - $6FFF RAM/ROM ok.
30	30	$7000 ROM ok if no ECS. RAM at $7000 confuses EXEC boot sequence.
31	31	$7001 - $77FF RAM/ROM ok if no ECS.
32	32	$7800 - $7FFF ROM ok if no ECS. Do not map RAM here due to GRAM alias.
r32760	r32761
38	38	$E000 - $EFFF RAM/ROM ok if no ECS.
39	39	$F000 - $F7FF RAM/ROM ok.
40	40	$F800 - $FFFF ROM ok. Do not map RAM here due to GRAM alias.
41
42
	41
	42
43	43	We handle this, by always creating a 0x10000 wide ROM region to load the
44	44	cart image and exposing the following (long list of) read handlers:
45	45	read_rom04
r32760	r32761
58	58	read_rome0
59	59	read_romf0
60	60	Each pcb types will then use the correct ones for its wiring setup.
61
	61
62	62	The BIN+CFG format introduced by INTVPC emulator includes metadata about where to
63	63	load ROM into memory in the CFG file, but we don't support it (because we don't parse
64	64	the CFG at all) and we rely instead on the intv.hsi metadata for fullpath loading of
r32760	r32761
69	69	TODO:
70	70	- Convert also the keyboard component to be a passthru slot device
71	71	- Merge some of the ROM accessor above, once it is clear which ones can be merged
72
	72
73	73	***********************************************************************************************************/
74	74
75	75
r32760	r32761
239	239	UINT8 num_segments;
240	240	UINT8 start_seg;
241	241	UINT8 end_seg;
242
	242
243	243	UINT32 current_address;
244	244	UINT32 end_address;
245
	245
246	246	UINT8 high_byte;
247	247	UINT8 low_byte;
248
	248
249	249	UINT8 *ROM;
250	250	const char *file_type = filetype();
251
	251
252	252	/* if it is in .rom format, we enter here */
253	253	if (!core_stricmp (file_type, "rom"))
254	254	{
r32760	r32761
256	256	fread(&temp, 1);
257	257	if (temp != 0xa8)
258	258	return IMAGE_INIT_FAIL;
259
	259
260	260	fread(&num_segments, 1);
261
	261
262	262	fread(&temp, 1);
263	263	if (temp != (num_segments ^ 0xff))
264	264	return IMAGE_INIT_FAIL;
r32760	r32761
270	270	{
271	271	fread(&start_seg, 1);
272	272	current_address = start_seg * 0x100;
273
	273
274	274	fread(&end_seg, 1);
275	275	end_address = end_seg * 0x100 + 0xff;
276
	276
277	277	while (current_address <= end_address)
278	278	{
279	279	fread(&low_byte, 1);
r32760	r32761
282	282	ROM[current_address << 1] = high_byte;
283	283	current_address++;
284	284	}
285
	285
286	286	// Here we should calculate and compare the CRC16...
287	287	fread(&temp, 1);
288	288	fread(&temp, 1);
289	289	}
290
	290
291	291	// Access tables and fine address restriction tables are not supported ATM
292	292	for (int i = 0; i < (16 + 32 + 2); i++)
293	293	{
r32760	r32761
300	300	{
301	301	// This code is a blatant hack, due to impossibility to load a separate .cfg file in MESS.
302	302	// It shall be eventually replaced by the .xml loading
303
	303
304	304	// extrainfo format
305	305	// 1. mapper number (to deal with bankswitch). no bankswitch is mapper 0 (most games).
306	306	// 2.->5. current images have at most 4 chunks of data. we store here block size and location to load
r32760	r32761
314	314
315	315	m_cart->rom_alloc(0x20000, tag());
316	316	ROM = (UINT8 *)m_cart->get_rom_base();
317
	317
318	318	if (!hashfile_extrainfo(*this, extrainfo))
319	319	{
320	320	// If no extrainfo, we assume a single 0x2000 chunk at 0x5000
r32760	r32761
329	329	else
330	330	{
331	331	sscanf(extrainfo.cstr() ,"%d %d %d %d %d %d %d", &mapper, &rom[0], &rom[1], &rom[2],
332		&rom[3], &ram, &extra);
	332	&rom[3], &ram, &extra);
333	333	//printf("extrainfo: %d %d %d %d %d %d %d \n", mapper, rom[0], rom[1], rom[2], rom[3], ram, extra);
334
	334
335	335	if (mapper)
336	336	logerror("Bankswitch not yet implemented!\n");
337
	337
338	338	if (ram)
339	339	{
340	340	start = ((ram & 0xf0) >> 4) * 0x1000;
r32760	r32761
355	355	}
356	356	if (extra & INTELLIVOICE_MASK)
357	357	{
358		printf("WARNING: This game requires emulation of the IntelliVoice module.\n");
	358	printf("WARNING: This game requires emulation of the IntelliVoice module.\n");
359	359	}
360
	360
361	361	if (extra & ECS_MASK)
362	362	{
363	363	printf("WARNING: This game requires emulation of the ECS module.\n");
364	364	}
365
	365
366	366	for (int j = 0; j < 4; j++)
367	367	{
368	368	start = ((rom[j] & 0xf0) >> 4) * 0x1000;
369	369	size = (rom[j] & 0x0f) * 0x800;
370	370
371		// some cart has to be loaded to 0x4800, but none of the available ones goes to 0x4000.
	371	// some cart has to be loaded to 0x4800, but none of the available ones goes to 0x4000.
372	372	// Hence, we use 0x04 << 4 in extrainfo (to reduce the stored values) and fix the value here.
373	373	if (start == 0x4000) start += 0x800;
374
	374
375	375	// logerror("step %d: %d %d \n", j, start / 0x1000, size / 0x1000);
376
	376
377	377	for (int i = 0; i < size; i++)
378	378	{
379	379	fread(&low_byte, 1);
r32760	r32761
383	383	}
384	384	}
385	385	}
386
	386
387	387	return IMAGE_INIT_PASS;
388	388	}
389	389	}
r32760	r32761
408	408	// so if we are loading one of these, we allocate additional 0x2000 bytes for the paged bank
409	409	if (m_type == INTV_WSMLB)
410	410	extra_bank = true;
411
	411
412	412	UINT32 size = 0;
413	413	UINT16 address = 0;
414	414	UINT8 ROM, region;
r32760	r32761
423	423	if (size)
424	424	{
425	425	region = get_software_region(region_name[i]);
426
	426
427	427	for (int j = 0; j < size / 2; j++)
428	428	{
429	429	ROM[((address + j) << 1) + 1] = region[2 * j];
r32760	r32761
467	467	UINT32 len = core_fsize(m_file);
468	468	dynamic_buffer rom(len);
469	469	int type = INTV_STD;
470
	470
471	471	core_fread(m_file, rom, len);
472	472
473	473	if (rom[0] == 0xa8 && (rom[1] == (rom[2] ^ 0xff)))
r32760	r32761
480	480	int start;
481	481	int mapper, rom[5], ram, extra;
482	482	astring extrainfo;
483
	483
484	484	if (hashfile_extrainfo(*this, extrainfo))
485	485	{
486	486	sscanf(extrainfo.cstr() ,"%d %d %d %d %d %d %d", &mapper, &rom[0], &rom[1], &rom[2],
487		&rom[3], &ram, &extra);
488
	487	&rom[3], &ram, &extra);
	488
489	489	if (ram)
490	490	{
491	491	start = ((ram & 0xf0) >> 4) * 0x1000;
r32760	r32761
495	495	type = INTV_GFACT;
496	496	}
497	497	}
498
	498
499	499	}
500	500
501	501	slot_string = intv_get_slot(type);
r32760	r32761
567	567	SLOT_INTERFACE_INTERNAL("intv_wsmlb", INTV_ROM_WSMLB)
568	568	SLOT_INTERFACE_INTERNAL("intv_voice", INTV_ROM_VOICE)
569	569	SLOT_INTERFACE_INTERNAL("intv_ecs", INTV_ROM_ECS)
570		// SLOT_INTERFACE_INTERNAL("intv_keycomp", INTV_ROM_KEYCOMP)
	570	// SLOT_INTERFACE_INTERNAL("intv_keycomp", INTV_ROM_KEYCOMP)
571	571	SLOT_INTERFACE_END
572

trunk/src/emu/bus/intv/rom.h
r32760	r32761
13	13	// construction/destruction
14	14	intv_rom_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname, const char *source);
15	15	intv_rom_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
16
	16
17	17	// reading and writing
18	18	virtual DECLARE_READ16_MEMBER(read_rom04) { return INTV_ROM16_READ(offset + 0x0400); }
19	19	virtual DECLARE_READ16_MEMBER(read_rom20) { return INTV_ROM16_READ(offset + 0x2000); }
r32760	r32761
30	30	virtual DECLARE_READ16_MEMBER(read_romd0) { return INTV_ROM16_READ(offset + 0xd000); }
31	31	virtual DECLARE_READ16_MEMBER(read_rome0) { return INTV_ROM16_READ(offset + 0xe000); }
32	32	virtual DECLARE_READ16_MEMBER(read_romf0) { return INTV_ROM16_READ(offset + 0xf000); }
33
	33
34	34	// device-level overrides
35	35	virtual void device_start() {}
36	36	virtual void device_reset() {}
r32760	r32761
43	43	public:
44	44	// construction/destruction
45	45	intv_ram_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
46
	46
47	47	// reading and writing
48	48	virtual DECLARE_READ16_MEMBER(read_ram) { return (int)m_ram[offset & (m_ram.count() - 1)]; }
49	49	virtual DECLARE_WRITE16_MEMBER(write_ram) { m_ram[offset & (m_ram.count() - 1)] = data & 0xff; }
r32760	r32761
56	56	public:
57	57	// construction/destruction
58	58	intv_gfact_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
59
	59
60	60	// reading and writing
61	61	virtual DECLARE_READ16_MEMBER(read_ram) { return (int)m_ram[offset & (m_ram.count() - 1)]; }
62	62	virtual DECLARE_WRITE16_MEMBER(write_ram) { m_ram[offset & (m_ram.count() - 1)] = data & 0xff; }

trunk/src/emu/bus/intv/slot.h
r32760	r32761
11	11	{
12	12	INTV_STD = 0,
13	13	INTV_RAM,
14		INTV_GFACT, // has RAM too but at diff offset
	14	INTV_GFACT, // has RAM too but at diff offset
15	15	INTV_WSMLB,
16	16	INTV_VOICE,
17	17	INTV_ECS,
r32760	r32761
51	51
52	52	virtual DECLARE_READ16_MEMBER(read_ram) { return 0xffff; }
53	53	virtual DECLARE_WRITE16_MEMBER(write_ram) {}
54
	54
55	55	// Used by IntelliVoice & ECS
56	56	virtual DECLARE_READ16_MEMBER(read_ay) { return 0xffff; }
57	57	virtual DECLARE_WRITE16_MEMBER(write_ay) {}
r32760	r32761
71	71	UINT32 get_rom_size() { return m_rom_size; }
72	72	UINT32 get_ram_size() { return m_ram.count(); }
73	73
74		void save_ram() { device().save_item(NAME(m_ram)); }
	74	void save_ram() { device().save_item(NAME(m_ram)); }
75	75	virtual void late_subslot_setup() {}
76	76
77	77	protected:
r32760	r32761
105	105	int get_type() { return m_type; }
106	106	int load_fullpath();
107	107
108		void save_ram() { if (m_cart && m_cart->get_ram_size()) m_cart->save_ram(); }
	108	void save_ram() { if (m_cart && m_cart->get_ram_size()) m_cart->save_ram(); }
109	109
110	110	virtual iodevice_t image_type() const { return IO_CARTSLOT; }
111	111	virtual bool is_readable() const { return 1; }
r32760	r32761
136	136	virtual DECLARE_READ16_MEMBER(read_romd0) { if (m_cart) return m_cart->read_romd0(space, offset, mem_mask); else return 0xffff; }
137	137	virtual DECLARE_READ16_MEMBER(read_rome0) { if (m_cart) return m_cart->read_rome0(space, offset, mem_mask); else return 0xffff; }
138	138	virtual DECLARE_READ16_MEMBER(read_romf0) { if (m_cart) return m_cart->read_romf0(space, offset, mem_mask); else return 0xffff; }
139
	139
140	140	virtual DECLARE_READ16_MEMBER(read_ay);
141	141	virtual DECLARE_WRITE16_MEMBER(write_ay);
142	142	virtual DECLARE_READ16_MEMBER(read_speech);
r32760	r32761
176	176
177	177	#define MCFG_INTV_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
178	178	MCFG_DEVICE_ADD(_tag, INTV_CART_SLOT, 0) \
179		MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
	179	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false)
180	180
181
182	181	SLOT_INTERFACE_EXTERN(intv_cart);
183	182
184	183	#endif

trunk/src/emu/bus/intv/ecs.c
r32760	r32761
4	4	Mattel Intellivision Entertainment Computer System expansion emulation
5	5
6	6	TODO:
7		- Make paged rom emulation more accurate (according to
	7	- Make paged rom emulation more accurate (according to
8	8	http://spatula-city.org/~im14u2c/intv/tech/ecs.html
9		writes to $xa5y should be available for every x and every y, i.e. we shall
10		have writes to every 4K chunk of the memory map, and there shall be 16 pages
	9	writes to $xa5y should be available for every x and every y, i.e. we shall
	10	have writes to every 4K chunk of the memory map, and there shall be 16 pages
11	11	for each)
12	12	Current emulation is instead tailored around the minimal usage necessary to
13	13	make the main expansion and World Series Major League Baseball happy
r32760	r32761
67	67	}
68	68
69	69	void intv_ecs_device::device_reset()
70		{
	70	{
71	71	memset(m_bank_base, 0, sizeof(m_bank_base));
72	72	}
73	73
74	74	void intv_ecs_device::late_subslot_setup()
75		{
	75	{
76	76	switch (m_subslot->get_type())
77	77	{
78	78	case INTV_RAM:
r32760	r32761
107	107	0xFF, 0x3F, 0x9F, 0x5F, 0xD7, 0xB7, 0x77, 0xDB,
108	108	0xBB, 0x7B, 0xDD, 0xBD, 0x7D, 0xDE, 0xBE, 0x7E
109	109	};
110
	110
111	111	static const UINT8 disc_table[] =
112	112	{
113	113	0xF3, 0xE3, 0xE7, 0xF7, 0xF6, 0xE6, 0xEE, 0xFE,
114	114	0xFC, 0xEC, 0xED, 0xFD, 0xF9, 0xE9, 0xEB, 0xFB
115	115	};
116
	116
117	117	static const UINT8 discyx_table[5][5] =
118	118	{
119	119	{ 0xE3, 0xF3, 0xFB, 0xEB, 0xE9 },
r32760	r32761
122	122	{ 0xF6, 0xE6, 0xFE, 0xEC, 0xED },
123	123	{ 0xE6, 0xEE, 0xFE, 0xFC, 0xEC }
124	124	};
125
	125
126	126	int x, y;
127	127	UINT8 val = 0xff;
128
	128
129	129	/* keypad */
130	130	x = m_keypad[hand]->read();
131	131	for (y = 0; y < 16; y++)
r32760	r32761
135	135	val &= keypad_table[y];
136	136	}
137	137	}
138
	138
139	139	switch ((m_options->read() >> hand) & 4)
140	140	{
141	141	case 0: /* disc == digital */
142	142	default:
143
	143
144	144	x = m_disc[hand]->read();
145	145	for (y = 0; y < 16; y++)
146	146	{
r32760	r32761
150	150	}
151	151	}
152	152	break;
153
	153
154	154	case 1: /* disc == _fake_ analog */
155
	155
156	156	x = m_discx[hand]->read();
157	157	y = m_discy[hand]->read();
158	158	val &= discyx_table[y / 32][x / 32];
159	159	}
160
	160
161	161	return val;
162	162	}
163	163
r32760	r32761
252	252	Bit 4 D E 2 3 W S Z X
253	253	Bit 5 A CTL (right) 1 Q (up) (down) (space)
254	254	Bit 6 SHIFT NC NC NC NC NC NC NC
255
	255
256	256	Shifted keys that differ from pc:
257	257	Key : 1 2 5 6 7 (left) (right) (up) (down)
258	258	Shift + key: = " + - / % ' ^ ?
r32760	r32761
530	530	Paged ROM handling
531	531	-------------------------------------------------*/
532	532
533		READ16_MEMBER(intv_ecs_device::read_rom20)
534		{
	533	READ16_MEMBER(intv_ecs_device::read_rom20)
	534	{
535	535	if (m_bank_base[2])
536		return INTV_ROM16_READ(offset + 0x2000);
	536	return INTV_ROM16_READ(offset + 0x2000);
537	537	else
538	538	return 0xffff;
539	539	}
540	540
541		READ16_MEMBER(intv_ecs_device::read_rom70)
542		{
	541	READ16_MEMBER(intv_ecs_device::read_rom70)
	542	{
543	543	if (m_bank_base[7])
544	544	return 0xffff;
545	545	else
546		return INTV_ROM16_READ(offset + 0x7000);
	546	return INTV_ROM16_READ(offset + 0x7000);
547	547	}
548	548
549		READ16_MEMBER(intv_ecs_device::read_rome0)
550		{
	549	READ16_MEMBER(intv_ecs_device::read_rome0)
	550	{
551	551	if (m_bank_base[14])
552		return INTV_ROM16_READ(offset + 0xe000);
553		else // if WSMLB is loaded, it shall go here, otherwise 0xffff
	552	return INTV_ROM16_READ(offset + 0xe000);
	553	else // if WSMLB is loaded, it shall go here, otherwise 0xffff
554	554	return m_subslot->read_rome0(space, offset, mem_mask);
555	555	}
556	556
557		READ16_MEMBER(intv_ecs_device::read_romf0)
558		{
	557	READ16_MEMBER(intv_ecs_device::read_romf0)
	558	{
559	559	// only WSMLB should come here with bank_base = 1
560	560	if (m_bank_base[15])
561	561	return m_subslot->read_romf0(space, offset + 0x1000, mem_mask);
r32760	r32761
585	585	if (ACCESSING_BITS_0_7)
586	586	return m_snd->write(space, offset, data, mem_mask);
587	587	}
588

trunk/src/emu/bus/intv/voice.h
r32760	r32761
13	13	public:
14	14	// construction/destruction
15	15	intv_voice_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
16
	16
17	17	// device-level overrides
18	18	virtual void device_start();
19	19	virtual machine_config_constructor device_mconfig_additions() const;
r32760	r32761
23	23	// actual IntelliVoice access
24	24	virtual DECLARE_READ16_MEMBER(read_speech);
25	25	virtual DECLARE_WRITE16_MEMBER(write_speech);
26
	26
27	27	// passthru access
28	28	virtual DECLARE_READ16_MEMBER(read_rom04) { return m_subslot->read_rom04(space, offset, mem_mask); }
29	29	virtual DECLARE_READ16_MEMBER(read_rom20) { return m_subslot->read_rom20(space, offset, mem_mask); }
r32760	r32761
33	33	virtual DECLARE_READ16_MEMBER(read_rom60) { return m_subslot->read_rom60(space, offset, mem_mask); }
34	34	virtual DECLARE_READ16_MEMBER(read_rom70) { return m_subslot->read_rom70(space, offset, mem_mask); }
35	35	virtual DECLARE_READ16_MEMBER(read_rom80)
36		{
	36	{
37	37	if (m_ram88_enabled && offset >= 0x800)
38		return m_subslot->read_ram(space, offset & 0x7ff, mem_mask);
	38	return m_subslot->read_ram(space, offset & 0x7ff, mem_mask);
39	39	else
40		return m_subslot->read_rom80(space, offset, mem_mask);
	40	return m_subslot->read_rom80(space, offset, mem_mask);
41	41	}
42	42	virtual DECLARE_READ16_MEMBER(read_rom90) { return m_subslot->read_rom90(space, offset, mem_mask); }
43	43	virtual DECLARE_READ16_MEMBER(read_roma0) { return m_subslot->read_roma0(space, offset, mem_mask); }
44	44	virtual DECLARE_READ16_MEMBER(read_romb0) { return m_subslot->read_romb0(space, offset, mem_mask); }
45	45	virtual DECLARE_READ16_MEMBER(read_romc0) { return m_subslot->read_romc0(space, offset, mem_mask); }
46		virtual DECLARE_READ16_MEMBER(read_romd0)
47		{
	46	virtual DECLARE_READ16_MEMBER(read_romd0)
	47	{
48	48	if (m_ramd0_enabled && offset < 0x800)
49		return m_subslot->read_ram(space, offset, mem_mask);
	49	return m_subslot->read_ram(space, offset, mem_mask);
50	50	else
51		return m_subslot->read_romd0(space, offset, mem_mask);
	51	return m_subslot->read_romd0(space, offset, mem_mask);
52	52	}
53	53	virtual DECLARE_READ16_MEMBER(read_rome0) { return m_subslot->read_rome0(space, offset, mem_mask); }
54	54	virtual DECLARE_READ16_MEMBER(read_romf0) { return m_subslot->read_romf0(space, offset, mem_mask); }
55
	55
56	56	// RAM passthru write
57	57	virtual DECLARE_WRITE16_MEMBER(write_88) { if (m_ram88_enabled) m_subslot->write_ram(space, offset, data, mem_mask); }
58	58	virtual DECLARE_WRITE16_MEMBER(write_d0) { if (m_ramd0_enabled) m_subslot->write_ram(space, offset, data, mem_mask); }
59	59	virtual DECLARE_READ16_MEMBER(read_ram) { return m_subslot->read_ram(space, offset, mem_mask); }
60	60	virtual DECLARE_WRITE16_MEMBER(write_ram) { m_subslot->write_ram(space, offset, data, mem_mask); }
61
	61
62	62	virtual void late_subslot_setup();
63
	63
64	64	private:
65	65	required_device<sp0256_device> m_speech;
66	66	required_device<intv_cart_slot_device> m_subslot;

trunk/src/emu/bus/nes/disksys.c
r32760	r32761
11	11	Famicom Disk System.
12	12
13	13	Based on info from NESDev wiki ( http://wiki.nesdev.com/w/index.php/Family_Computer_Disk_System )
14
	14
15	15	TODO:
16	16	- convert floppy drive + fds format to modern code!
17	17	- add sound bits
r32760	r32761
124	124
125	125	irq_timer = timer_alloc(TIMER_IRQ);
126	126	irq_timer->adjust(attotime::zero, 0, machine().device<cpu_device>("maincpu")->cycles_to_attotime(1));
127
	127
128	128	save_item(NAME(m_fds_motor_on));
129	129	save_item(NAME(m_fds_door_closed));
130	130	save_item(NAME(m_fds_current_side));
131	131	save_item(NAME(m_fds_head_position));
132	132	save_item(NAME(m_fds_status0));
133	133	save_item(NAME(m_read_mode));
134		save_item(NAME(m_drive_ready));
	134	save_item(NAME(m_drive_ready));
135	135	save_item(NAME(m_irq_enable));
136	136	save_item(NAME(m_irq_transfer));
137	137	save_item(NAME(m_irq_count));
r32760	r32761
173	173
174	174	RAM is in 0x6000-0xdfff (32K)
175	175	ROM is in 0xe000-0xffff (8K)
176
177		registers + disk drive are accessed in
	176
	177	registers + disk drive are accessed in
178	178	0x4020-0x403f (read_ex/write_ex below)
179	179
180	180	-------------------------------------------------*/
r32760	r32761
210	210	}
211	211
212	212	void nes_disksys_device::hblank_irq(int scanline, int vblank, int blanked)
213		{
	213	{
214	214	if (m_irq_transfer)
215	215	m_maincpu->set_input_line(M6502_IRQ_LINE, HOLD_LINE);
216	216	}
r32760	r32761
218	218	WRITE8_MEMBER(nes_disksys_device::write_ex)
219	219	{
220	220	LOG_MMC(("Famicom Disk System write_ex, offset: %04x, data: %02x\n", offset, data));
221
	221
222	222	if (offset >= 0x20 && offset < 0x60)
223	223	{
224	224	// wavetable
r32760	r32761
255	255	// bit4 - CRC control (set during CRC calculation of transfer)
256	256	// bit5 - Always set to '1'
257	257	// bit6 - Read/Write Start (Set to 1 when the drive becomes ready for read/write)
258		// bit7 - Interrupt Transfer (0: Transfer without using IRQ; 1: Enable IRQ when
	258	// bit7 - Interrupt Transfer (0: Transfer without using IRQ; 1: Enable IRQ when
259	259	// the drive becomes ready)
260	260	m_fds_motor_on = BIT(data, 0);
261
	261
262	262	if (BIT(data, 1))
263	263	m_fds_head_position = 0;
264
	264
265	265	if (!(data & 0x40) && m_drive_ready && m_fds_head_position > 2)
266	266	m_fds_head_position -= 2; // ??? is this some sort of compensation??
267
	267
268	268	m_read_mode = BIT(data, 2);
269		set_nt_mirroring(BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	269	set_nt_mirroring(BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
270	270	m_drive_ready = data & 0x40;
271	271	m_irq_transfer = BIT(data, 7);
272	272	break;
273	273	case 0x06:
274	274	// external connector
275	275	break;
276		case 0x60: // $4080 - Volume envelope - read through $4090
277		case 0x62: // $4082 - Frequency low
278		case 0x63: // $4083 - Frequency high
279		case 0x64: // $4084 - Mod envelope - read through $4092
280		case 0x65: // $4085 - Mod counter
281		case 0x66: // $4086 - Mod frequency low
282		case 0x67: // $4087 - Mod frequency high
283		case 0x68: // $4088 - Mod table write
284		case 0x69: // $4089 - Wave write / master volume
285		case 0x6a: // $408a - Envelope speed
	276	case 0x60: // $4080 - Volume envelope - read through $4090
	277	case 0x62: // $4082 - Frequency low
	278	case 0x63: // $4083 - Frequency high
	279	case 0x64: // $4084 - Mod envelope - read through $4092
	280	case 0x65: // $4085 - Mod counter
	281	case 0x66: // $4086 - Mod frequency low
	282	case 0x67: // $4087 - Mod frequency high
	283	case 0x68: // $4088 - Mod table write
	284	case 0x69: // $4089 - Wave write / master volume
	285	case 0x6a: // $408a - Envelope speed
286	286	break;
287	287	}
288	288	}
r32760	r32761
299	299
300	300	switch (offset)
301	301	{
302		case 0x10:
	302	case 0x10:
303	303	// $4030 - disk status 0
304	304	// bit0 - Timer Interrupt (1: an IRQ occurred)
305		// bit1 - Byte transfer flag (Set to 1 every time 8 bits have been transfered between
306		// the RAM adaptor & disk drive through $4024/$4031; Reset to 0 when $4024,
	305	// bit1 - Byte transfer flag (Set to 1 every time 8 bits have been transfered between
	306	// the RAM adaptor & disk drive through $4024/$4031; Reset to 0 when $4024,
307	307	// $4031, or $4030 has been serviced)
308	308	// bit4 - CRC control (0: CRC passed; 1: CRC error)
309	309	// bit6 - End of Head (1 when disk head is on the most inner track)
r32760	r32761
312	312	// clear the disk IRQ detect flag
313	313	m_fds_status0 &= ~0x01;
314	314	break;
315		case 0x11:
	315	case 0x11:
316	316	// $4031 - data latch
317	317	// don't read data if disk is unloaded
318	318	if (!m_fds_data)
r32760	r32761
330	330	else
331	331	ret = 0;
332	332	break;
333		case 0x12:
334		// $4032 - disk status 1:
	333	case 0x12:
	334	// $4032 - disk status 1:
335	335	// bit0 - Disk flag (0: Disk inserted; 1: Disk not inserted)
336	336	// bit1 - Ready flag (0: Disk ready; 1: Disk not ready)
337	337	// bit2 - Protect flag (0: Not write protected; 1: Write protected or disk ejected)
r32760	r32761
351	351	else
352	352	ret = (m_fds_current_side == 0) ? 1 : 0; // 0 if a disk is inserted
353	353	break;
354		case 0x13:
	354	case 0x13:
355	355	// $4033 - external connector (bits 0-6) + battery status (bit 7)
356	356	ret = 0x80;
357	357	break;
358		case 0x70: // $4090 - Volume gain - write through $4080
359		case 0x72: // $4092 - Mod gain - read through $4084
	358	case 0x70: // $4090 - Volume gain - write through $4080
	359	case 0x72: // $4092 - Mod gain - read through $4084
360	360	default:
361	361	ret = 0x00;
362	362	break;
363	363	}
364
	364
365	365	return ret;
366	366	}
367	367
r32760	r32761
372	372	void nes_disksys_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
373	373	{
374	374	if (id == TIMER_IRQ)
375		{
	375	{
376	376	if (m_irq_enable && m_irq_count)
377	377	{
378	378	m_irq_count--;
r32760	r32761
381	381	m_maincpu->set_input_line(M6502_IRQ_LINE, HOLD_LINE);
382	382	m_irq_enable = 0;
383	383	m_fds_status0 \|= 0x01;
384		m_irq_count_latch = 0; // used in Kaettekita Mario Bros
	384	m_irq_count_latch = 0; // used in Kaettekita Mario Bros
385	385	}
386	386	}
387	387	}
r32760	r32761
399	399	if (m_fds_current_side == 0)
400	400	popmessage("No disk inserted.");
401	401	else
402		popmessage("Disk set to side %d", m_fds_current_side);
	402	popmessage("Disk set to side %d", m_fds_current_side);
403	403	}
404	404
405	405
r32760	r32761
410	410	{
411	411	int header = 0;
412	412	m_fds_sides = 0;
413
	413
414	414	if (image.length() % 65500)
415	415	header = 0x10;
416
	416
417	417	m_fds_sides = (image.length() - header) / 65500;
418
	418
419	419	if (!m_fds_data)
420	420	m_fds_data = auto_alloc_array(machine(), UINT8, m_fds_sides * 65500);
421
	421
422	422	// if there is an header, skip it
423	423	image.fseek(header, SEEK_SET);
424	424	image.fread(m_fds_data, 65500 * m_fds_sides);
r32760	r32761
430	430	/* TODO: should write out changes here as well */
431	431	m_fds_sides = 0;
432	432	}
433

trunk/src/emu/bus/nes/nes_slot.c
r32760	r32761
161	161	printf("Warning! The loaded PRG has size not a multiple of 8KB (0x%X)\n", (UINT32)size);
162	162	m_prg_chunks--;
163	163	}
164
	164
165	165	m_prg_mask = ((m_prg_chunks << 1) - 1);
166
	166
167	167	// printf("first mask %x!\n", m_prg_mask);
168	168	if ((m_prg_chunks << 1) & m_prg_mask)
169	169	{
r32760	r32761
172	172	// only half a dozen of NES carts have PRG which is not a power of 2
173	173	// so we use this bank_map only as an exception
174	174	// printf("uneven rom!\n");
175
	175
176	176	// 1. redefine mask as (next power of 2)-1
177	177	for (; temp; )
178	178	{
r32760	r32761
182	182	m_prg_mask = (1 << mask_bits) - 1;
183	183	// printf("new mask %x!\n", m_prg_mask);
184	184	mapsize = (1 << mask_bits)/2;
185
	185
186	186	// 2. create a bank_map for banks in the range mask/2 -> mask
187	187	m_prg_bank_map.resize(mapsize);
188
	188
189	189	// 3. fill the bank_map accounting for mirrors
190	190	int j;
191	191	for (j = mapsize; j < (m_prg_chunks << 1); j++)
192	192	m_prg_bank_map[j - mapsize] = j;
193
	193
194	194	while (j % mapsize)
195	195	{
196	196	int k = 0, repeat_banks;
r32760	r32761
201	201	m_prg_bank_map[(j - mapsize) + l] = m_prg_bank_map[(j - mapsize) + l - repeat_banks];
202	202	j += repeat_banks;
203	203	}
204
	204
205	205	// check bank map!
206	206	// for (int i = 0; i < mapsize; i++)
207	207	// {
r32760	r32761
674	674	// main NES CPU here, even if it does not belong to this device.
675	675	m_maincpu = machine.device<cpu_device>("maincpu");
676	676
677		if (cart_mounted) // disksys expansion can arrive here without the memory banks!
	677	if (cart_mounted) // disksys expansion can arrive here without the memory banks!
678	678	{
679	679	// Setup PRG
680	680	m_prg_bank_mem[0] = machine.root_device().membank("prg0");
r32760	r32761
691	691	}
692	692	}
693	693	}
694
	694
695	695	// Setup CHR (VRAM can be present also without PRG rom)
696	696	m_chr_source = m_vrom_chunks ? CHRROM : CHRRAM;
697	697	chr8(0, m_chr_source);
698
	698
699	699	// Setup NT
700	700	m_ciram = ciram_ptr;
701	701

trunk/src/emu/bus/nes/nes_slot.h
r32760	r32761
376	376	virtual DECLARE_WRITE8_MEMBER(write_m);
377	377	virtual DECLARE_WRITE8_MEMBER(write_h);
378	378	virtual DECLARE_WRITE8_MEMBER(write_ex);
379
	379
380	380	// hack until disk system is made modern!
381	381	virtual void disk_flip_side() { if (m_cart) m_cart->disk_flip_side(); }
382
	382
383	383	int get_pcb_id() { return m_pcb_id; };
384	384
385	385	void pcb_start(UINT8 *ciram_ptr);

trunk/src/emu/bus/pet/cb2snd.c
r32760	r32761
65	65	{
66	66	m_dac->write_unsigned8(state ? 0xff : 0x00);
67	67	}
68

trunk/src/emu/bus/scv/slot.c
r32760	r32761
175	175	seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
176	176	return IMAGE_INIT_FAIL;
177	177	}
178
	178
179	179	m_cart->rom_alloc(len, tag());
180	180	if (has_ram)
181	181	m_cart->ram_alloc(get_software_region_length("ram"));
182
	182
183	183	ROM = m_cart->get_rom_base();
184	184
185	185	if (software_entry() == NULL)
r32760	r32761
317	317	if (m_cart)
318	318	m_cart->write_bank(space, offset, data);
319	319	}
320

trunk/src/emu/bus/scv/rom.h
r32760	r32761
79	79	public:
80	80	// construction/destruction
81	81	scv_rom64_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
82
	82
83	83	// device-level overrides
84	84	virtual void device_start();
85	85	virtual void device_reset();
86
	86
87	87	// reading and writing
88	88	virtual DECLARE_READ8_MEMBER(read_cart);
89	89	virtual DECLARE_WRITE8_MEMBER(write_bank);
r32760	r32761
100	100	public:
101	101	// construction/destruction
102	102	scv_rom128_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
103
	103
104	104	// device-level overrides
105	105	virtual void device_start();
106	106	virtual void device_reset();
107
	107
108	108	// reading and writing
109	109	virtual DECLARE_READ8_MEMBER(read_cart);
110	110	virtual DECLARE_WRITE8_MEMBER(write_bank);
111
	111
112	112	private:
113	113	UINT8 m_bank_base;
114	114	};
r32760	r32761
121	121	public:
122	122	// construction/destruction
123	123	scv_rom128ram4_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
124
	124
125	125	// device-level overrides
126	126	virtual void device_start();
127	127	virtual void device_reset();
128
	128
129	129	// reading and writing
130	130	virtual DECLARE_READ8_MEMBER(read_cart);
131	131	virtual DECLARE_WRITE8_MEMBER(write_cart);
132	132	virtual DECLARE_WRITE8_MEMBER(write_bank);
133
	133
134	134	private:
135	135	UINT8 m_bank_base, m_ram_enabled;
136	136	};

trunk/src/emu/bus/scv/slot.h
r32760	r32761
42	42	UINT32 get_rom_size() { return m_rom_size; }
43	43	UINT32 get_ram_size() { return m_ram.count(); }
44	44
45		void save_ram() { device().save_item(NAME(m_ram)); }
	45	void save_ram() { device().save_item(NAME(m_ram)); }
46	46
47	47	protected:
48	48	// internal state
r32760	r32761
75	75	int get_type() { return m_type; }
76	76	int get_cart_type(UINT8 *ROM, UINT32 len);
77	77
78		void save_ram() { if (m_cart && m_cart->get_ram_size()) m_cart->save_ram(); }
	78	void save_ram() { if (m_cart && m_cart->get_ram_size()) m_cart->save_ram(); }
79	79
80	80	virtual iodevice_t image_type() const { return IO_CARTSLOT; }
81	81	virtual bool is_readable() const { return 1; }
r32760	r32761
115	115
116	116	#define MCFG_SCV_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
117	117	MCFG_DEVICE_ADD(_tag, SCV_CART_SLOT, 0) \
118		MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
119
	118	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false)
120	119	#endif

trunk/src/emu/bus/cpc/symbfac2.c
r32760	r32761
47	47	PORT_BIT(0x00000010, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("PS/2 Mouse forward button") PORT_CODE(MOUSECODE_BUTTON5) PORT_CHANGED_MEMBER(DEVICE_SELF,cpc_symbiface2_device,mouse_change_x,NULL)
48	48
49	49	// TODO: mouse scroll wheel support
50		// PORT_START("sf2_mouse_scroll")
51		// PORT_BIT(0x1f , 0, IPT_TRACKBALL_Y)
52		// PORT_SENSITIVITY(100)
53		// PORT_KEYDELTA(10)
54		// PORT_PLAYER(1)
	50	// PORT_START("sf2_mouse_scroll")
	51	// PORT_BIT(0x1f , 0, IPT_TRACKBALL_Y)
	52	// PORT_SENSITIVITY(100)
	53	// PORT_KEYDELTA(10)
	54	// PORT_PLAYER(1)
55	55	INPUT_PORTS_END
56	56
57	57
r32760	r32761
189	189	// PS/2 Mouse connector
190	190	// #FD10 (read only) read mouse status
191	191	/*
192		Status byte
193		Bit 76543210
194		Use mmDDDDDD
	192	Status byte
	193	Bit 76543210
	194	Use mmDDDDDD
195	195
196		m: Mode
197		D: Use-Data
	196	m: Mode
	197	D: Use-Data
198	198
199		If read and...
	199	If read and...
200	200
201		m = 00 -> no more data available, you can stop reading the status for a while
202		m = 01 -> D = X offset (signed); you will receive positive values, if the user
203		is moving the mouse to the right
204		m = 10 -> D = Y offset (signed); you will receive positive values, if the user
205		is moving the mouse upwards
206		m = 11 -> D[bit5] = 0 -> D[bit0] = left button
207		D[bit1] = right button
208		D[bit2] = middle button
209		D[bit3] = forward button
210		D[bit4] = backward button
211		D[bit5] = 1 -> D[bit0-4] = scroll wheel offset (signed)
	201	m = 00 -> no more data available, you can stop reading the status for a while
	202	m = 01 -> D = X offset (signed); you will receive positive values, if the user
	203	is moving the mouse to the right
	204	m = 10 -> D = Y offset (signed); you will receive positive values, if the user
	205	is moving the mouse upwards
	206	m = 11 -> D[bit5] = 0 -> D[bit0] = left button
	207	D[bit1] = right button
	208	D[bit2] = middle button
	209	D[bit3] = forward button
	210	D[bit4] = backward button
	211	D[bit5] = 1 -> D[bit0-4] = scroll wheel offset (signed)
212	212	*/
213	213	READ8_MEMBER(cpc_symbiface2_device::mouse_r)
214	214	{

trunk/src/emu/bus/cpc/symbfac2.h
r32760	r32761
14	14	#include "cpcexp.h"
15	15
16	16	class cpc_symbiface2_device : public device_t,
17		public device_cpc_expansion_card_interface
	17	public device_cpc_expansion_card_interface
18	18	{
19	19	public:
20	20	// construction/destruction

trunk/src/emu/bus/cpc/amdrum.h
r32760	r32761
18	18	#include "sound/dac.h"
19	19
20	20	class cpc_amdrum_device : public device_t,
21		public device_cpc_expansion_card_interface
	21	public device_cpc_expansion_card_interface
22	22	{
23	23	public:
24	24	// construction/destruction

trunk/src/emu/bus/apf/slot.c
r32760	r32761
169	169	seterror(IMAGE_ERROR_UNSPECIFIED, "Image extends beyond the expected size for an APF cart");
170	170	return IMAGE_INIT_FAIL;
171	171	}
172
	172
173	173	m_cart->rom_alloc(size, tag());
174
	174
175	175	if (software_entry() == NULL)
176	176	fread(m_cart->get_rom_base(), size);
177	177	else
r32760	r32761
294	294	if (m_cart)
295	295	m_cart->write_ram(space, offset, data);
296	296	}
297
298

trunk/src/emu/bus/apf/rom.h
r32760	r32761
43	43	public:
44	44	// construction/destruction
45	45	apf_spacedst_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
46
	46
47	47	// reading and writing
48	48	virtual DECLARE_READ8_MEMBER(read_ram);
49	49	virtual DECLARE_WRITE8_MEMBER(write_ram);

trunk/src/emu/bus/apf/slot.h
r32760	r32761
39	39	UINT32 get_rom_size() { return m_rom_size; }
40	40	UINT32 get_ram_size() { return m_ram.count(); }
41	41
42		void save_ram() { device().save_item(NAME(m_ram)); }
	42	void save_ram() { device().save_item(NAME(m_ram)); }
43	43
44	44	protected:
45	45	// internal state
r32760	r32761
71	71
72	72	int get_type() { return m_type; }
73	73
74		void save_ram() { if (m_cart && m_cart->get_ram_size()) m_cart->save_ram(); }
	74	void save_ram() { if (m_cart && m_cart->get_ram_size()) m_cart->save_ram(); }
75	75
76	76	virtual iodevice_t image_type() const { return IO_CARTSLOT; }
77	77	virtual bool is_readable() const { return 1; }
r32760	r32761
112	112
113	113	#define MCFG_APF_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
114	114	MCFG_DEVICE_ADD(_tag, APF_CART_SLOT, 0) \
115		MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
116
	115	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false)
117	116	#endif

trunk/src/emu/bus/rs232/xvd701.c
r32760	r32761
93	93	{
94	94	if (m_response_index < sizeof(m_response) && is_transmit_register_empty())
95	95	{
96		// printf("sending %02x\n", m_response[m_response_index]);
	96	// printf("sending %02x\n", m_response[m_response_index]);
97	97	transmit_register_setup(m_response[m_response_index++]);
98	98	}
99	99	}
r32760	r32761
115	115	// printf("xvd701");
116	116
117	117	//for (int i = 0; i < sizeof(m_command); i++)
118		// printf(" %02x", m_command[i]);
	118	// printf(" %02x", m_command[i]);
119	119
120	120	//printf("\n");
121	121

trunk/src/emu/ui/ui.c
r32760	r32761
1554	1554	machine.pause();
1555	1555	return machine.ui().set_handler(ui_gfx_ui_handler, is_paused);
1556	1556	}
1557
	1557
1558	1558	// handle a tape control key
1559	1559	if (ui_input_pressed(machine, IPT_UI_TAPE_START))
1560	1560	{
r32760	r32761
1574	1574	return 0;
1575	1575	}
1576	1576	}
1577
	1577
1578	1578	// handle a save state request
1579	1579	if (ui_input_pressed(machine, IPT_UI_SAVE_STATE))
1580	1580	{

trunk/src/emu/ui/swlist.c
r32760	r32761
68	68	entry2->part = 0;
69	69	item_append("[file manager]", 0, 0, entry2);
70	70
71
	71
72	72	software_part_menu_entry entry3 = (software_part_menu_entry ) m_pool_alloc(sizeof(*entry3));
73	73	entry3->type = T_SWLIST;
74	74	entry3->part = 0;

trunk/src/emu/imagedev/floppy.c
r32760	r32761
885	885	input_filename = filename;
886	886	input_format = static_cast<floppy_image_device *>(image)->identify(filename);
887	887
888		if (!input_format)
	888	if (!input_format)
889	889	{
890	890	popmessage("Error: %s\n", image->error());
891	891	ui_menu::stack_pop(machine());

trunk/src/emu/devcpu.c
r32760	r32761
38	38	cpu_device::~cpu_device()
39	39	{
40	40	}
41

trunk/src/emu/webengine.c
r32760	r32761
133	133	}
134	134
135	135	void reg_string(struct lua_State L, const char name, const char *val) {
136		lua_pushstring(L, name);
137		lua_pushstring(L, val);
138		lua_rawset(L, -3);
	136	lua_pushstring(L, name);
	137	lua_pushstring(L, val);
	138	lua_rawset(L, -3);
139	139	}
140	140
141	141	void reg_int(struct lua_State L, const char name, int val) {
142		lua_pushstring(L, name);
143		lua_pushinteger(L, val);
144		lua_rawset(L, -3);
	142	lua_pushstring(L, name);
	143	lua_pushinteger(L, val);
	144	lua_rawset(L, -3);
145	145	}
146	146
147	147	void reg_function(struct lua_State L, const char name,
148		lua_CFunction func, struct mg_connection *conn) {
149		lua_pushstring(L, name);
150		lua_pushlightuserdata(L, conn);
151		lua_pushcclosure(L, func, 1);
152		lua_rawset(L, -3);
	148	lua_CFunction func, struct mg_connection *conn) {
	149	lua_pushstring(L, name);
	150	lua_pushlightuserdata(L, conn);
	151	lua_pushcclosure(L, func, 1);
	152	lua_rawset(L, -3);
153	153	}
154	154
155	155	static int lua_write(lua_State *L) {
156		int i, num_args;
157		const char *str;
158		size_t size;
159		struct mg_connection conn = (struct mg_connection )
160		lua_touserdata(L, lua_upvalueindex(1));
	156	int i, num_args;
	157	const char *str;
	158	size_t size;
	159	struct mg_connection conn = (struct mg_connection )
	160	lua_touserdata(L, lua_upvalueindex(1));
161	161
162		num_args = lua_gettop(L);
163		for (i = 1; i <= num_args; i++) {
164		if (lua_isstring(L, i)) {
165		str = lua_tolstring(L, i, &size);
166		mg_send_data(conn, str, size);
167		}
168		}
	162	num_args = lua_gettop(L);
	163	for (i = 1; i <= num_args; i++) {
	164	if (lua_isstring(L, i)) {
	165	str = lua_tolstring(L, i, &size);
	166	mg_send_data(conn, str, size);
	167	}
	168	}
169	169
170		return 0;
	170	return 0;
171	171	}
172	172
173	173	static int lua_header(lua_State *L) {
174		struct mg_connection conn = (struct mg_connection )
175		lua_touserdata(L, lua_upvalueindex(1));
	174	struct mg_connection conn = (struct mg_connection )
	175	lua_touserdata(L, lua_upvalueindex(1));
176	176
177		const char *header = luaL_checkstring(L,1);
178		const char *value = luaL_checkstring(L,2);
179
180		mg_send_header(conn, header, value);
	177	const char *header = luaL_checkstring(L,1);
	178	const char *value = luaL_checkstring(L,2);
181	179
182		return 0;
	180	mg_send_header(conn, header, value);
	181
	182	return 0;
183	183	}
184	184
185	185
186	186	static void prepare_lua_environment(struct mg_connection ri, lua_State L) {
187		extern void luaL_openlibs(lua_State *);
188		int i;
	187	extern void luaL_openlibs(lua_State *);
	188	int i;
189	189
190		luaL_openlibs(L);
	190	luaL_openlibs(L);
191	191
192		if (ri == NULL) return;
	192	if (ri == NULL) return;
193	193
194		// Register mg module
195		lua_newtable(L);
196		reg_function(L, "write", lua_write, ri);
197		reg_function(L, "header", lua_header, ri);
	194	// Register mg module
	195	lua_newtable(L);
	196	reg_function(L, "write", lua_write, ri);
	197	reg_function(L, "header", lua_header, ri);
198	198
199		// Export request_info
200		lua_pushstring(L, "request_info");
201		lua_newtable(L);
202		reg_string(L, "request_method", ri->request_method);
203		reg_string(L, "uri", ri->uri);
204		reg_string(L, "http_version", ri->http_version);
205		reg_string(L, "query_string", ri->query_string);
206		reg_string(L, "remote_ip", ri->remote_ip);
207		reg_int(L, "remote_port", ri->remote_port);
208		reg_string(L, "local_ip", ri->local_ip);
209		reg_int(L, "local_port", ri->local_port);
210		lua_pushstring(L, "content");
211		lua_pushlstring(L, ri->content == NULL ? "" : ri->content, ri->content_len);
212		lua_rawset(L, -3);
213		reg_int(L, "num_headers", ri->num_headers);
214		lua_pushstring(L, "http_headers");
215		lua_newtable(L);
216		for (i = 0; i < ri->num_headers; i++) {
217		reg_string(L, ri->http_headers[i].name, ri->http_headers[i].value);
218		}
219		lua_rawset(L, -3);
220		lua_rawset(L, -3);
	199	// Export request_info
	200	lua_pushstring(L, "request_info");
	201	lua_newtable(L);
	202	reg_string(L, "request_method", ri->request_method);
	203	reg_string(L, "uri", ri->uri);
	204	reg_string(L, "http_version", ri->http_version);
	205	reg_string(L, "query_string", ri->query_string);
	206	reg_string(L, "remote_ip", ri->remote_ip);
	207	reg_int(L, "remote_port", ri->remote_port);
	208	reg_string(L, "local_ip", ri->local_ip);
	209	reg_int(L, "local_port", ri->local_port);
	210	lua_pushstring(L, "content");
	211	lua_pushlstring(L, ri->content == NULL ? "" : ri->content, ri->content_len);
	212	lua_rawset(L, -3);
	213	reg_int(L, "num_headers", ri->num_headers);
	214	lua_pushstring(L, "http_headers");
	215	lua_newtable(L);
	216	for (i = 0; i < ri->num_headers; i++) {
	217	reg_string(L, ri->http_headers[i].name, ri->http_headers[i].value);
	218	}
	219	lua_rawset(L, -3);
	220	lua_rawset(L, -3);
221	221
222		lua_setglobal(L, "mg");
	222	lua_setglobal(L, "mg");
223	223
224	224	}
225	225
226	226
227	227	static void lsp(struct mg_connection conn, const char p, int len, lua_State *L) {
228		int i, j, pos = 0;
229		for (i = 0; i < len; i++) {
230		if (p[i] == '<' && p[i + 1] == '?') {
231		for (j = i + 1; j < len ; j++) {
232		if (p[j] == '?' && p[j + 1] == '>') {
233		if (i-pos!=0) mg_send_data(conn, p + pos, i - pos);
234		if (luaL_loadbuffer(L, p + (i + 2), j - (i + 2), "") == 0) {
235		lua_pcall(L, 0, LUA_MULTRET, 0);
236		}
237		pos = j + 2;
238		i = pos - 1;
239		break;
240		}
241		}
242		}
243		}
244		if (i > pos) {
	228	int i, j, pos = 0;
	229	for (i = 0; i < len; i++) {
	230	if (p[i] == '<' && p[i + 1] == '?') {
	231	for (j = i + 1; j < len ; j++) {
	232	if (p[j] == '?' && p[j + 1] == '>') {
	233	if (i-pos!=0) mg_send_data(conn, p + pos, i - pos);
	234	if (luaL_loadbuffer(L, p + (i + 2), j - (i + 2), "") == 0) {
	235	lua_pcall(L, 0, LUA_MULTRET, 0);
	236	}
	237	pos = j + 2;
	238	i = pos - 1;
	239	break;
	240	}
	241	}
	242	}
	243	}
	244	if (i > pos) {
245	245	mg_send_data(conn, p + pos, i - pos);
246		}
	246	}
247	247	}
248	248
249	249	static int filename_endswith(const char str, const char suffix)
250	250	{
251		if (!str \|\| !suffix)
252		return 0;
253		size_t lenstr = strlen(str);
254		size_t lensuffix = strlen(suffix);
255		if (lensuffix > lenstr)
256		return 0;
257		return strncmp(str + lenstr - lensuffix, suffix, lensuffix) == 0;
	251	if (!str \|\| !suffix)
	252	return 0;
	253	size_t lenstr = strlen(str);
	254	size_t lensuffix = strlen(suffix);
	255	if (lensuffix > lenstr)
	256	return 0;
	257	return strncmp(str + lenstr - lensuffix, suffix, lensuffix) == 0;
258	258	}
259	259
260	260	// This function will be called by mongoose on every new request.
r32760	r32761
263	263	astring file_path(mg_get_option(m_server, "document_root"), PATH_SEPARATOR, conn->uri);
264	264	if (filename_endswith(file_path,".lp"))
265	265	{
266		FILE *fp = NULL;
267		if ((fp = fopen(file_path, "rb")) != NULL) {
268		fseek (fp, 0, SEEK_END);
	266	FILE *fp = NULL;
	267	if ((fp = fopen(file_path, "rb")) != NULL) {
	268	fseek (fp, 0, SEEK_END);
269	269	size_t size = ftell(fp);
270		fseek (fp, 0, SEEK_SET);
	270	fseek (fp, 0, SEEK_SET);
271	271	char data = (char)mg_mmap(fp,size);
272	272
273	273	lua_State *L = luaL_newstate();
274		prepare_lua_environment(conn, L);
	274	prepare_lua_environment(conn, L);
275	275	lsp(conn, data, (int) size, L);
276	276	if (L != NULL) lua_close(L);
277	277	mg_munmap(data,size);
278		fclose(fp);
279		return MG_TRUE;
280		} else {
281		return MG_FALSE;
282		}
283		}
	278	fclose(fp);
	279	return MG_TRUE;
	280	} else {
	281	return MG_FALSE;
	282	}
	283	}
284	284	else if (!strncmp(conn->uri, "/json/",6))
285	285	{
286	286	if (!strcmp(conn->uri, "/json/game"))
r32760	r32761
295	295	else if (!strncmp(conn->uri, "/keypost",8))
296	296	{
297	297	// Is there any sane way to determine the length of the buffer before getting it?
298		// A request for a way was previously filed with the mongoose devs,
	298	// A request for a way was previously filed with the mongoose devs,
299	299	// but it looks like it was never implemented.
300
301		// For now, we'll allow a paste buffer of 32k.
	300
	301	// For now, we'll allow a paste buffer of 32k.
302	302	// To-do: Send an error if the paste is too big?
303	303	char cmd_val[32768];
304
	304
305	305	int pastelength = mg_get_var(conn, "val", cmd_val, sizeof(cmd_val));
306	306	if (pastelength > 0) {
307	307	machine().ioport().natkeyboard().post_utf8(cmd_val);
r32760	r32761
326	326	while ((ofs = mg_parse_multipart(conn->content + ofs, conn->content_len - ofs, var_name, sizeof(var_name), file_name, sizeof(file_name), (const char **)&upload_data, &data_length)) > 0) {
327	327	mg_printf_data(conn, "File: %s, size: %d bytes", file_name, data_length);
328	328	}
329
	329
330	330	// That upload_data contains more than we need. It also has the headers.
331	331	// We'll need to strip it down to just what we want.
332
	332
333	333	if ((&data_length > 0) && (sizeof(file_name) > 0))
334	334	{
335	335	// MSVC doesn't yet support variable-length arrays, so chop the string the old-fashioned way

trunk/src/emu/machine/mb8421.c
r32760	r32761
4	4
5	5	Fujitsu MB8421/22/31/32-90/-90L/-90LL/-12/-12L/-12LL
6	6	CMOS 16K-bit (2KB) dual-port SRAM
7
	7
8	8	MB84x2 lacks interrupt pins, it's basically as simple as AM_RAM AM_SHARE("x")
9	9	MB843x is same as MB842x, except that it supports slave mode. It makes
10	10	sure there are no clashes, with the _BUSY pin.
r32760	r32761
70	70
71	71	if (offset == 0x7fe && !space.debugger_access())
72	72	m_intl_handler(0);
73
	73
74	74	return m_ram[offset];
75	75	}
76	76
r32760	r32761
89	89
90	90	if (offset == 0x7ff && !space.debugger_access())
91	91	m_intr_handler(0);
92
	92
93	93	return m_ram[offset];
94	94	}

trunk/src/emu/machine/rp5h01.c
r32760	r32761
7	7	with a mask of %1010111. For example if the 8 dummy bits are $7c,
8	8	bits 64 to 127 are read as $7c $7c $00 $00 $7c $7c $00 $00.
9	9	To simplify this, our emulation expects 'overdumps', 128bits total.
10
	10
11	11	TODO:
12	12	- not sure if the polarity of our PROM dumps (playch10) is correct,
13	13	same goes for the bit order (note: does not require new dumps)

trunk/src/emu/machine/smpc.c
r32760	r32761
172	172	memcpy(memregion("abus")->base(), m_cart_reg[gameno]->base(), 0x3000000);
173	173	else
174	174	memset(memregion("abus")->base(), 0x00, 0x3000000);
175
	175
176	176	m_prev_bankswitch = gameno;
177	177	}
178	178	}

trunk/src/emu/machine/wozfdc.c
r32760	r32761
80	80	save_item(NAME(cur_lss.data_reg));
81	81	save_item(NAME(cur_lss.address));
82	82	save_item(NAME(cur_lss.write_start_time));
83		// save_item(NAME(cur_lss.write_buffer));
	83	// save_item(NAME(cur_lss.write_buffer));
84	84	save_item(NAME(cur_lss.write_position));
85	85	save_item(NAME(cur_lss.write_line_active));
86	86	save_item(NAME(predicted_lss.tm));
r32760	r32761
88	88	save_item(NAME(predicted_lss.data_reg));
89	89	save_item(NAME(predicted_lss.address));
90	90	save_item(NAME(predicted_lss.write_start_time));
91		// save_item(NAME(predicted_lss.write_buffer));
	91	// save_item(NAME(predicted_lss.write_buffer));
92	92	save_item(NAME(predicted_lss.write_position));
93	93	save_item(NAME(predicted_lss.write_line_active));
94	94	save_item(NAME(drvsel));
r32760	r32761
582	582
583	583	if (offset < 8)
584	584	{
585		a3_update_drive_sel();
	585	a3_update_drive_sel();
586	586	}
587	587	}

trunk/src/emu/machine/pit8253.c
r32760	r32761
103	103	for (int timerno = 0; timerno < PIT8253_MAX_TIMER; timerno++)
104	104	{
105	105	pit8253_timer *timer = get_timer(timerno);
106
	106
107	107	/* initialize timer */
108	108	timer->updatetimer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(pit8253_device::update_timer_cb),this));
109	109	timer->updatetimer->adjust(attotime::never, timerno);

trunk/src/lib/formats/mfi_dsk.c
r32760	r32761
99	99
100	100	io_generic_read(io, &h, 0, sizeof(header));
101	101	if(memcmp( h.sign, sign, 16 ) == 0 &&
102		(h.cyl_count & CYLINDER_MASK) <= 84 &&
103		(h.cyl_count >> RESOLUTION_SHIFT) < 3 &&
	102	(h.cyl_count & CYLINDER_MASK) <= 84 &&
	103	(h.cyl_count >> RESOLUTION_SHIFT) < 3 &&
104	104	h.head_count <= 2 &&
105	105	(!form_factor \|\| !h.form_factor \|\| h.form_factor == form_factor))
106	106	return 100;

trunk/src/lib/formats/dmk_dsk.c
r32760	r32761
226	226
227	227
228	228	const floppy_format_type FLOPPY_DMK_FORMAT = &floppy_image_format_creator<dmk_format>;
229

trunk/src/lib/formats/dmk_dsk.h
r32760	r32761
31	31	extern const floppy_format_type FLOPPY_DMK_FORMAT;
32	32
33	33	#endif /* DMK_DSK_H */
34

trunk/src/lib/formats/ap2_dsk.c
r32760	r32761
624	624	if (!memcmp("PRODOS", &sector_data[0x103], 6))
625	625	{
626	626	m_prodos_order = true;
627		} // check for alternate version ProDOS boot block
	627	} // check for alternate version ProDOS boot block
628	628	if (!memcmp("PRODOS", &sector_data[0x121], 6))
629	629	{
630	630	m_prodos_order = true;
r32760	r32761
654	654	else if (!memcmp(dos33_block1, &sector_data[0x100], 4))
655	655	{
656	656	m_prodos_order = true;
657		} // check for a later version of the Pascal boot block
	657	} // check for a later version of the Pascal boot block
658	658	else if (!memcmp(pascal2_block1, &sector_data[0x100], 4))
659	659	{
660	660	m_prodos_order = true;

trunk/src/lib/web/mongoose.c
r32760	r32761
128	128
129	129	#ifdef NS_ENABLE_DEBUG
130	130	#define DBG(x) do { printf("%-20s ", __func__); printf x; putchar('\n'); \
131		fflush(stdout); } while(0)
	131	fflush(stdout); } while(0)
132	132	#else
133	133	#define DBG(x)
134	134	#endif
r32760	r32761
150	150	#endif // __cplusplus
151	151
152	152	union socket_address {
153		struct sockaddr sa;
154		struct sockaddr_in sin;
	153	struct sockaddr sa;
	154	struct sockaddr_in sin;
155	155	#ifdef NS_ENABLE_IPV6
156		struct sockaddr_in6 sin6;
	156	struct sockaddr_in6 sin6;
157	157	#else
158		struct sockaddr sin6;
	158	struct sockaddr sin6;
159	159	#endif
160	160	};
161	161
162	162	// IO buffers interface
163	163	struct iobuf {
164		char *buf;
165		size_t len;
166		size_t size;
	164	char *buf;
	165	size_t len;
	166	size_t size;
167	167	};
168	168
169	169	void iobuf_init(struct iobuf *, size_t initial_size);
r32760	r32761
174	174	// Net skeleton interface
175	175	// Events. Meaning of event parameter (evp) is given in the comment.
176	176	enum ns_event {
177		NS_POLL, // Sent to each connection on each call to ns_server_poll()
178		NS_ACCEPT, // New connection accept()-ed. union socket_address *remote_addr
179		NS_CONNECT, // connect() succeeded or failed. int *success_status
180		NS_RECV, // Data has benn received. int *num_bytes
181		NS_SEND, // Data has been written to a socket. int *num_bytes
182		NS_CLOSE // Connection is closed. NULL
	177	NS_POLL, // Sent to each connection on each call to ns_server_poll()
	178	NS_ACCEPT, // New connection accept()-ed. union socket_address *remote_addr
	179	NS_CONNECT, // connect() succeeded or failed. int *success_status
	180	NS_RECV, // Data has benn received. int *num_bytes
	181	NS_SEND, // Data has been written to a socket. int *num_bytes
	182	NS_CLOSE // Connection is closed. NULL
183	183	};
184	184
185	185	// Callback function (event handler) prototype, must be defined by user.
r32760	r32761
188	188	typedef void (ns_callback_t)(struct ns_connection , enum ns_event, void *evp);
189	189
190	190	struct ns_server {
191		void *server_data;
192		sock_t listening_sock;
193		struct ns_connection *active_connections;
194		ns_callback_t callback;
195		SSL_CTX *ssl_ctx;
196		SSL_CTX *client_ssl_ctx;
197		const char *hexdump_file;
198		sock_t ctl[2];
	191	void *server_data;
	192	sock_t listening_sock;
	193	struct ns_connection *active_connections;
	194	ns_callback_t callback;
	195	SSL_CTX *ssl_ctx;
	196	SSL_CTX *client_ssl_ctx;
	197	const char *hexdump_file;
	198	sock_t ctl[2];
199	199	};
200	200
201	201	struct ns_connection {
202		struct ns_connection prev, next;
203		struct ns_server *server;
204		sock_t sock;
205		union socket_address sa;
206		struct iobuf recv_iobuf;
207		struct iobuf send_iobuf;
208		SSL *ssl;
209		void *connection_data;
210		time_t last_io_time;
211		unsigned int flags;
	202	struct ns_connection prev, next;
	203	struct ns_server *server;
	204	sock_t sock;
	205	union socket_address sa;
	206	struct iobuf recv_iobuf;
	207	struct iobuf send_iobuf;
	208	SSL *ssl;
	209	void *connection_data;
	210	time_t last_io_time;
	211	unsigned int flags;
212	212	#define NSF_FINISHED_SENDING_DATA (1 << 0)
213	213	#define NSF_BUFFER_BUT_DONT_SEND (1 << 1)
214	214	#define NSF_SSL_HANDSHAKE_DONE (1 << 2)
r32760	r32761
239	239	int ns_set_ssl_cert(struct ns_server , const char ssl_cert);
240	240	int ns_set_ssl_ca_cert(struct ns_server , const char ssl_ca_cert);
241	241	struct ns_connection ns_connect(struct ns_server , const char *host,
242		int port, int ssl, void *connection_param);
	242	int port, int ssl, void *connection_param);
243	243
244	244	int ns_send(struct ns_connection , const void buf, int len);
245	245	int ns_printf(struct ns_connection , const char fmt, ...);
r32760	r32761
289	289	#endif
290	290
291	291	struct ctl_msg {
292		ns_callback_t callback;
293		char message[1024 * 8];
	292	ns_callback_t callback;
	293	char message[1024 * 8];
294	294	};
295	295
296	296	void iobuf_init(struct iobuf *iobuf, size_t size) {
297		iobuf->len = iobuf->size = 0;
298		iobuf->buf = NULL;
	297	iobuf->len = iobuf->size = 0;
	298	iobuf->buf = NULL;
299	299
300		if (size > 0 && (iobuf->buf = (char *) NS_MALLOC(size)) != NULL) {
301		iobuf->size = size;
302		}
	300	if (size > 0 && (iobuf->buf = (char *) NS_MALLOC(size)) != NULL) {
	301	iobuf->size = size;
	302	}
303	303	}
304	304
305	305	void iobuf_free(struct iobuf *iobuf) {
306		if (iobuf != NULL) {
307		if (iobuf->buf != NULL) NS_FREE(iobuf->buf);
308		iobuf_init(iobuf, 0);
309		}
	306	if (iobuf != NULL) {
	307	if (iobuf->buf != NULL) NS_FREE(iobuf->buf);
	308	iobuf_init(iobuf, 0);
	309	}
310	310	}
311	311
312	312	size_t iobuf_append(struct iobuf io, const void buf, size_t len) {
313		char *p = NULL;
	313	char *p = NULL;
314	314
315		assert(io != NULL);
316		assert(io->len <= io->size);
	315	assert(io != NULL);
	316	assert(io->len <= io->size);
317	317
318		if (len <= 0) {
319		} else if (io->len + len <= io->size) {
320		memcpy(io->buf + io->len, buf, len);
321		io->len += len;
322		} else if ((p = (char *) NS_REALLOC(io->buf, io->len + len)) != NULL) {
323		io->buf = p;
324		memcpy(io->buf + io->len, buf, len);
325		io->len += len;
326		io->size = io->len;
327		} else {
328		len = 0;
329		}
	318	if (len <= 0) {
	319	} else if (io->len + len <= io->size) {
	320	memcpy(io->buf + io->len, buf, len);
	321	io->len += len;
	322	} else if ((p = (char *) NS_REALLOC(io->buf, io->len + len)) != NULL) {
	323	io->buf = p;
	324	memcpy(io->buf + io->len, buf, len);
	325	io->len += len;
	326	io->size = io->len;
	327	} else {
	328	len = 0;
	329	}
330	330
331		return len;
	331	return len;
332	332	}
333	333
334	334	void iobuf_remove(struct iobuf *io, size_t n) {
335		if (n > 0 && n <= io->len) {
336		memmove(io->buf, io->buf + n, io->len - n);
337		io->len -= n;
338		}
	335	if (n > 0 && n <= io->len) {
	336	memmove(io->buf, io->buf + n, io->len - n);
	337	io->len -= n;
	338	}
339	339	}
340	340
341	341	#ifndef NS_DISABLE_THREADS
342	342	void ns_start_thread(void (f)(void ), void *p) {
343	343	#ifdef _WIN32
344		return (void ) _beginthread((void (__cdecl )(void *)) f, 0, p);
	344	return (void ) _beginthread((void (__cdecl )(void *)) f, 0, p);
345	345	#else
346		pthread_t thread_id = (pthread_t) 0;
347		pthread_attr_t attr;
	346	pthread_t thread_id = (pthread_t) 0;
	347	pthread_attr_t attr;
348	348
349		(void) pthread_attr_init(&attr);
350		(void) pthread_attr_setdetachstate(&attr, PTHREAD_CREATE_DETACHED);
	349	(void) pthread_attr_init(&attr);
	350	(void) pthread_attr_setdetachstate(&attr, PTHREAD_CREATE_DETACHED);
351	351
352	352	#if defined(NS_STACK_SIZE) && NS_STACK_SIZE > 1
353		(void) pthread_attr_setstacksize(&attr, NS_STACK_SIZE);
	353	(void) pthread_attr_setstacksize(&attr, NS_STACK_SIZE);
354	354	#endif
355	355
356		pthread_create(&thread_id, &attr, f, p);
357		pthread_attr_destroy(&attr);
	356	pthread_create(&thread_id, &attr, f, p);
	357	pthread_attr_destroy(&attr);
358	358
359		return (void *) thread_id;
	359	return (void *) thread_id;
360	360	#endif
361	361	}
362	362	#endif // NS_DISABLE_THREADS
363	363
364	364	static void ns_add_conn(struct ns_server server, struct ns_connection c) {
365		c->next = server->active_connections;
366		server->active_connections = c;
367		c->prev = NULL;
368		if (c->next != NULL) c->next->prev = c;
	365	c->next = server->active_connections;
	366	server->active_connections = c;
	367	c->prev = NULL;
	368	if (c->next != NULL) c->next->prev = c;
369	369	}
370	370
371	371	static void ns_remove_conn(struct ns_connection *conn) {
372		if (conn->prev == NULL) conn->server->active_connections = conn->next;
373		if (conn->prev) conn->prev->next = conn->next;
374		if (conn->next) conn->next->prev = conn->prev;
	372	if (conn->prev == NULL) conn->server->active_connections = conn->next;
	373	if (conn->prev) conn->prev->next = conn->next;
	374	if (conn->next) conn->next->prev = conn->prev;
375	375	}
376	376
377	377	// Print message to buffer. If buffer is large enough to hold the message,
378	378	// return buffer. If buffer is to small, allocate large enough buffer on heap,
379	379	// and return allocated buffer.
380	380	int ns_avprintf(char *buf, size_t size, const char fmt, va_list ap) {
381		va_list ap_copy;
382		int len;
	381	va_list ap_copy;
	382	int len;
383	383
384		va_copy(ap_copy, ap);
385		len = vsnprintf(*buf, size, fmt, ap_copy);
386		va_end(ap_copy);
	384	va_copy(ap_copy, ap);
	385	len = vsnprintf(*buf, size, fmt, ap_copy);
	386	va_end(ap_copy);
387	387
388		if (len < 0) {
389		// eCos and Windows are not standard-compliant and return -1 when
390		// the buffer is too small. Keep allocating larger buffers until we
391		// succeed or out of memory.
392		*buf = NULL;
393		while (len < 0) {
394		if (buf) free(buf);
395		size *= 2;
396		if ((buf = (char ) NS_MALLOC(size)) == NULL) break;
397		va_copy(ap_copy, ap);
398		len = vsnprintf(*buf, size, fmt, ap_copy);
399		va_end(ap_copy);
400		}
401		} else if (len > (int) size) {
402		// Standard-compliant code path. Allocate a buffer that is large enough.
403		if ((buf = (char ) NS_MALLOC(len + 1)) == NULL) {
404		len = -1;
405		} else {
406		va_copy(ap_copy, ap);
407		len = vsnprintf(*buf, len + 1, fmt, ap_copy);
408		va_end(ap_copy);
409		}
410		}
	388	if (len < 0) {
	389	// eCos and Windows are not standard-compliant and return -1 when
	390	// the buffer is too small. Keep allocating larger buffers until we
	391	// succeed or out of memory.
	392	*buf = NULL;
	393	while (len < 0) {
	394	if (buf) free(buf);
	395	size *= 2;
	396	if ((buf = (char ) NS_MALLOC(size)) == NULL) break;
	397	va_copy(ap_copy, ap);
	398	len = vsnprintf(*buf, size, fmt, ap_copy);
	399	va_end(ap_copy);
	400	}
	401	} else if (len > (int) size) {
	402	// Standard-compliant code path. Allocate a buffer that is large enough.
	403	if ((buf = (char ) NS_MALLOC(len + 1)) == NULL) {
	404	len = -1;
	405	} else {
	406	va_copy(ap_copy, ap);
	407	len = vsnprintf(*buf, len + 1, fmt, ap_copy);
	408	va_end(ap_copy);
	409	}
	410	}
411	411
412		return len;
	412	return len;
413	413	}
414	414
415	415	int ns_vprintf(struct ns_connection conn, const char fmt, va_list ap) {
416		char mem[2000], *buf = mem;
417		int len;
	416	char mem[2000], *buf = mem;
	417	int len;
418	418
419		if ((len = ns_avprintf(&buf, sizeof(mem), fmt, ap)) > 0) {
420		iobuf_append(&conn->send_iobuf, buf, len);
421		}
422		if (buf != mem && buf != NULL) {
423		free(buf);
424		}
	419	if ((len = ns_avprintf(&buf, sizeof(mem), fmt, ap)) > 0) {
	420	iobuf_append(&conn->send_iobuf, buf, len);
	421	}
	422	if (buf != mem && buf != NULL) {
	423	free(buf);
	424	}
425	425
426		return len;
	426	return len;
427	427	}
428	428
429	429	int ns_printf(struct ns_connection conn, const char fmt, ...) {
430		int len;
431		va_list ap;
432		va_start(ap, fmt);
433		len = ns_vprintf(conn, fmt, ap);
434		va_end(ap);
435		return len;
	430	int len;
	431	va_list ap;
	432	va_start(ap, fmt);
	433	len = ns_vprintf(conn, fmt, ap);
	434	va_end(ap);
	435	return len;
436	436	}
437	437
438	438	static void hexdump(struct ns_connection nc, const char path,
439		int num_bytes, enum ns_event ev) {
440		const struct iobuf *io = ev == NS_SEND ? &nc->send_iobuf : &nc->recv_iobuf;
441		FILE *fp;
442		char *buf, src[60], dst[60];
443		int buf_size = num_bytes * 5 + 100;
	439	int num_bytes, enum ns_event ev) {
	440	const struct iobuf *io = ev == NS_SEND ? &nc->send_iobuf : &nc->recv_iobuf;
	441	FILE *fp;
	442	char *buf, src[60], dst[60];
	443	int buf_size = num_bytes * 5 + 100;
444	444
445		if ((fp = fopen(path, "a")) != NULL) {
446		ns_sock_to_str(nc->sock, src, sizeof(src), 3);
447		ns_sock_to_str(nc->sock, dst, sizeof(dst), 7);
448		fprintf(fp, "%lu %p %s %s %s %d\n", (unsigned long) time(NULL),
449		nc->connection_data, src,
450		ev == NS_RECV ? "<-" : ev == NS_SEND ? "->" :
451		ev == NS_ACCEPT ? "<A" : ev == NS_CONNECT ? "C>" : "XX",
452		dst, num_bytes);
453		if (num_bytes > 0 && (buf = (char *) malloc(buf_size)) != NULL) {
454		ns_hexdump(io->buf + (ev == NS_SEND ? 0 : io->len) -
455		(ev == NS_SEND ? 0 : num_bytes), num_bytes, buf, buf_size);
456		fprintf(fp, "%s", buf);
457		free(buf);
458		}
459		fclose(fp);
460		}
	445	if ((fp = fopen(path, "a")) != NULL) {
	446	ns_sock_to_str(nc->sock, src, sizeof(src), 3);
	447	ns_sock_to_str(nc->sock, dst, sizeof(dst), 7);
	448	fprintf(fp, "%lu %p %s %s %s %d\n", (unsigned long) time(NULL),
	449	nc->connection_data, src,
	450	ev == NS_RECV ? "<-" : ev == NS_SEND ? "->" :
	451	ev == NS_ACCEPT ? "<A" : ev == NS_CONNECT ? "C>" : "XX",
	452	dst, num_bytes);
	453	if (num_bytes > 0 && (buf = (char *) malloc(buf_size)) != NULL) {
	454	ns_hexdump(io->buf + (ev == NS_SEND ? 0 : io->len) -
	455	(ev == NS_SEND ? 0 : num_bytes), num_bytes, buf, buf_size);
	456	fprintf(fp, "%s", buf);
	457	free(buf);
	458	}
	459	fclose(fp);
	460	}
461	461	}
462	462
463	463	static void ns_call(struct ns_connection conn, enum ns_event ev, void p) {
464		if (conn->server->hexdump_file != NULL && ev != NS_POLL) {
465		int len = (ev == NS_RECV \|\| ev == NS_SEND) ? * (int *) p : 0;
466		hexdump(conn, conn->server->hexdump_file, len, ev);
467		}
468		if (conn->server->callback) conn->server->callback(conn, ev, p);
	464	if (conn->server->hexdump_file != NULL && ev != NS_POLL) {
	465	int len = (ev == NS_RECV \|\| ev == NS_SEND) ? * (int *) p : 0;
	466	hexdump(conn, conn->server->hexdump_file, len, ev);
	467	}
	468	if (conn->server->callback) conn->server->callback(conn, ev, p);
469	469	}
470	470
471	471	static void ns_close_conn(struct ns_connection *conn) {
472		DBG(("%p %d", conn, conn->flags));
473		ns_call(conn, NS_CLOSE, NULL);
474		ns_remove_conn(conn);
475		closesocket(conn->sock);
476		iobuf_free(&conn->recv_iobuf);
477		iobuf_free(&conn->send_iobuf);
	472	DBG(("%p %d", conn, conn->flags));
	473	ns_call(conn, NS_CLOSE, NULL);
	474	ns_remove_conn(conn);
	475	closesocket(conn->sock);
	476	iobuf_free(&conn->recv_iobuf);
	477	iobuf_free(&conn->send_iobuf);
478	478	#ifdef NS_ENABLE_SSL
479		if (conn->ssl != NULL) {
480		SSL_free(conn->ssl);
481		}
	479	if (conn->ssl != NULL) {
	480	SSL_free(conn->ssl);
	481	}
482	482	#endif
483		NS_FREE(conn);
	483	NS_FREE(conn);
484	484	}
485	485
486	486	void ns_set_close_on_exec(sock_t sock) {
487	487	#ifdef _WIN32
488		(void) SetHandleInformation((HANDLE) sock, HANDLE_FLAG_INHERIT, 0);
	488	(void) SetHandleInformation((HANDLE) sock, HANDLE_FLAG_INHERIT, 0);
489	489	#else
490		fcntl(sock, F_SETFD, FD_CLOEXEC);
	490	fcntl(sock, F_SETFD, FD_CLOEXEC);
491	491	#endif
492	492	}
493	493
494	494	static void ns_set_non_blocking_mode(sock_t sock) {
495	495	#ifdef _WIN32
496		unsigned long on = 1;
497		ioctlsocket(sock, FIONBIO, &on);
	496	unsigned long on = 1;
	497	ioctlsocket(sock, FIONBIO, &on);
498	498	#else
499		int flags = fcntl(sock, F_GETFL, 0);
500		fcntl(sock, F_SETFL, flags \| O_NONBLOCK);
	499	int flags = fcntl(sock, F_GETFL, 0);
	500	fcntl(sock, F_SETFL, flags \| O_NONBLOCK);
501	501	#endif
502	502	}
503	503
504	504	#ifndef NS_DISABLE_SOCKETPAIR
505	505	int ns_socketpair2(sock_t sp[2], int sock_type) {
506		union socket_address sa;
507		sock_t sock;
508		socklen_t len = sizeof(sa.sin);
509		int ret = 0;
	506	union socket_address sa;
	507	sock_t sock;
	508	socklen_t len = sizeof(sa.sin);
	509	int ret = 0;
510	510
511		sp[0] = sp[1] = INVALID_SOCKET;
	511	sp[0] = sp[1] = INVALID_SOCKET;
512	512
513		(void) memset(&sa, 0, sizeof(sa));
514		sa.sin.sin_family = AF_INET;
515		sa.sin.sin_port = htons(0);
516		sa.sin.sin_addr.s_addr = htonl(0x7f000001);
	513	(void) memset(&sa, 0, sizeof(sa));
	514	sa.sin.sin_family = AF_INET;
	515	sa.sin.sin_port = htons(0);
	516	sa.sin.sin_addr.s_addr = htonl(0x7f000001);
517	517
518		if ((sock = socket(AF_INET, sock_type, 0)) != INVALID_SOCKET &&
519		!bind(sock, &sa.sa, len) &&
520		(sock_type == SOCK_DGRAM \|\| !listen(sock, 1)) &&
521		!getsockname(sock, &sa.sa, &len) &&
522		(sp[0] = socket(AF_INET, sock_type, 0)) != INVALID_SOCKET &&
523		!connect(sp[0], &sa.sa, len) &&
524		(sock_type == SOCK_STREAM \|\|
525		(!getsockname(sp[0], &sa.sa, &len) && !connect(sock, &sa.sa, len))) &&
526		(sp[1] = (sock_type == SOCK_DGRAM ? sock :
527		accept(sock, &sa.sa, &len))) != INVALID_SOCKET) {
528		ns_set_close_on_exec(sp[0]);
529		ns_set_close_on_exec(sp[1]);
530		ret = 1;
531		} else {
532		if (sp[0] != INVALID_SOCKET) closesocket(sp[0]);
533		if (sp[1] != INVALID_SOCKET) closesocket(sp[1]);
534		sp[0] = sp[1] = INVALID_SOCKET;
535		}
536		if (sock_type != SOCK_DGRAM) closesocket(sock);
	518	if ((sock = socket(AF_INET, sock_type, 0)) != INVALID_SOCKET &&
	519	!bind(sock, &sa.sa, len) &&
	520	(sock_type == SOCK_DGRAM \|\| !listen(sock, 1)) &&
	521	!getsockname(sock, &sa.sa, &len) &&
	522	(sp[0] = socket(AF_INET, sock_type, 0)) != INVALID_SOCKET &&
	523	!connect(sp[0], &sa.sa, len) &&
	524	(sock_type == SOCK_STREAM \|\|
	525	(!getsockname(sp[0], &sa.sa, &len) && !connect(sock, &sa.sa, len))) &&
	526	(sp[1] = (sock_type == SOCK_DGRAM ? sock :
	527	accept(sock, &sa.sa, &len))) != INVALID_SOCKET) {
	528	ns_set_close_on_exec(sp[0]);
	529	ns_set_close_on_exec(sp[1]);
	530	ret = 1;
	531	} else {
	532	if (sp[0] != INVALID_SOCKET) closesocket(sp[0]);
	533	if (sp[1] != INVALID_SOCKET) closesocket(sp[1]);
	534	sp[0] = sp[1] = INVALID_SOCKET;
	535	}
	536	if (sock_type != SOCK_DGRAM) closesocket(sock);
537	537
538		return ret;
	538	return ret;
539	539	}
540	540
541	541	int ns_socketpair(sock_t sp[2]) {
542		return ns_socketpair2(sp, SOCK_STREAM);
	542	return ns_socketpair2(sp, SOCK_STREAM);
543	543	}
544	544	#endif // NS_DISABLE_SOCKETPAIR
545	545
546	546	// Valid listening port spec is: [ip_address:]port, e.g. "80", "127.0.0.1:3128"
547	547	static int ns_parse_port_string(const char str, union socket_address sa) {
548		unsigned int a, b, c, d, port;
549		int len = 0;
	548	unsigned int a, b, c, d, port;
	549	int len = 0;
550	550	#ifdef NS_ENABLE_IPV6
551		char buf[100];
	551	char buf[100];
552	552	#endif
553	553
554		// MacOS needs that. If we do not zero it, subsequent bind() will fail.
555		// Also, all-zeroes in the socket address means binding to all addresses
556		// for both IPv4 and IPv6 (INADDR_ANY and IN6ADDR_ANY_INIT).
557		memset(sa, 0, sizeof(*sa));
558		sa->sin.sin_family = AF_INET;
	554	// MacOS needs that. If we do not zero it, subsequent bind() will fail.
	555	// Also, all-zeroes in the socket address means binding to all addresses
	556	// for both IPv4 and IPv6 (INADDR_ANY and IN6ADDR_ANY_INIT).
	557	memset(sa, 0, sizeof(*sa));
	558	sa->sin.sin_family = AF_INET;
559	559
560		if (sscanf(str, "%u.%u.%u.%u:%u%n", &a, &b, &c, &d, &port, &len) == 5) {
561		// Bind to a specific IPv4 address, e.g. 192.168.1.5:8080
562		sa->sin.sin_addr.s_addr = htonl((a << 24) \| (b << 16) \| (c << 8) \| d);
563		sa->sin.sin_port = htons((uint16_t) port);
	560	if (sscanf(str, "%u.%u.%u.%u:%u%n", &a, &b, &c, &d, &port, &len) == 5) {
	561	// Bind to a specific IPv4 address, e.g. 192.168.1.5:8080
	562	sa->sin.sin_addr.s_addr = htonl((a << 24) \| (b << 16) \| (c << 8) \| d);
	563	sa->sin.sin_port = htons((uint16_t) port);
564	564	#ifdef NS_ENABLE_IPV6
565		} else if (sscanf(str, "[%49[^]]]:%u%n", buf, &port, &len) == 2 &&
566		inet_pton(AF_INET6, buf, &sa->sin6.sin6_addr)) {
567		// IPv6 address, e.g. [3ffe:2a00:100:7031::1]:8080
568		sa->sin6.sin6_family = AF_INET6;
569		sa->sin6.sin6_port = htons((uint16_t) port);
	565	} else if (sscanf(str, "[%49[^]]]:%u%n", buf, &port, &len) == 2 &&
	566	inet_pton(AF_INET6, buf, &sa->sin6.sin6_addr)) {
	567	// IPv6 address, e.g. [3ffe:2a00:100:7031::1]:8080
	568	sa->sin6.sin6_family = AF_INET6;
	569	sa->sin6.sin6_port = htons((uint16_t) port);
570	570	#endif
571		} else if (sscanf(str, "%u%n", &port, &len) == 1) {
572		// If only port is specified, bind to IPv4, INADDR_ANY
573		sa->sin.sin_port = htons((uint16_t) port);
574		} else {
575		port = 0; // Parsing failure. Make port invalid.
576		}
	571	} else if (sscanf(str, "%u%n", &port, &len) == 1) {
	572	// If only port is specified, bind to IPv4, INADDR_ANY
	573	sa->sin.sin_port = htons((uint16_t) port);
	574	} else {
	575	port = 0; // Parsing failure. Make port invalid.
	576	}
577	577
578		return port <= 0xffff && str[len] == '\0';
	578	return port <= 0xffff && str[len] == '\0';
579	579	}
580	580
581	581	// 'sa' must be an initialized address to bind to
582	582	static sock_t ns_open_listening_socket(union socket_address *sa) {
583		socklen_t len = sizeof(*sa);
584		sock_t sock = INVALID_SOCKET;
	583	socklen_t len = sizeof(*sa);
	584	sock_t sock = INVALID_SOCKET;
585	585	#ifndef _WIN32
586		int on = 1;
	586	int on = 1;
587	587	#endif
588	588
589		if ((sock = socket(sa->sa.sa_family, SOCK_STREAM, 6)) != INVALID_SOCKET &&
	589	if ((sock = socket(sa->sa.sa_family, SOCK_STREAM, 6)) != INVALID_SOCKET &&
590	590	#ifndef _WIN32
591		// SO_RESUSEADDR is not enabled on Windows because the semantics of
592		// SO_REUSEADDR on UNIX and Windows is different. On Windows,
593		// SO_REUSEADDR allows to bind a socket to a port without error even if
594		// the port is already open by another program. This is not the behavior
595		// SO_REUSEADDR was designed for, and leads to hard-to-track failure
596		// scenarios. Therefore, SO_REUSEADDR was disabled on Windows.
597		!setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, (void *) &on, sizeof(on)) &&
	591	// SO_RESUSEADDR is not enabled on Windows because the semantics of
	592	// SO_REUSEADDR on UNIX and Windows is different. On Windows,
	593	// SO_REUSEADDR allows to bind a socket to a port without error even if
	594	// the port is already open by another program. This is not the behavior
	595	// SO_REUSEADDR was designed for, and leads to hard-to-track failure
	596	// scenarios. Therefore, SO_REUSEADDR was disabled on Windows.
	597	!setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, (void *) &on, sizeof(on)) &&
598	598	#endif
599		!bind(sock, &sa->sa, sa->sa.sa_family == AF_INET ?
600		sizeof(sa->sin) : sizeof(sa->sin6)) &&
601		!listen(sock, SOMAXCONN)) {
602		ns_set_non_blocking_mode(sock);
603		// In case port was set to 0, get the real port number
604		(void) getsockname(sock, &sa->sa, &len);
605		} else if (sock != INVALID_SOCKET) {
606		closesocket(sock);
607		sock = INVALID_SOCKET;
608		}
	599	!bind(sock, &sa->sa, sa->sa.sa_family == AF_INET ?
	600	sizeof(sa->sin) : sizeof(sa->sin6)) &&
	601	!listen(sock, SOMAXCONN)) {
	602	ns_set_non_blocking_mode(sock);
	603	// In case port was set to 0, get the real port number
	604	(void) getsockname(sock, &sa->sa, &len);
	605	} else if (sock != INVALID_SOCKET) {
	606	closesocket(sock);
	607	sock = INVALID_SOCKET;
	608	}
609	609
610		return sock;
	610	return sock;
611	611	}
612	612
613	613	// Certificate generation script is at
614	614	// https://github.com/cesanta/net_skeleton/blob/master/examples/gen_certs.sh
615	615	int ns_set_ssl_ca_cert(struct ns_server server, const char cert) {
616	616	#ifdef NS_ENABLE_SSL
617		STACK_OF(X509_NAME) *list = SSL_load_client_CA_file(cert);
618		if (cert != NULL && server->ssl_ctx != NULL && list != NULL) {
619		SSL_CTX_set_client_CA_list(server->ssl_ctx, list);
620		SSL_CTX_set_verify(server->ssl_ctx, SSL_VERIFY_PEER \|
621		SSL_VERIFY_FAIL_IF_NO_PEER_CERT, NULL);
622		return 0;
623		}
	617	STACK_OF(X509_NAME) *list = SSL_load_client_CA_file(cert);
	618	if (cert != NULL && server->ssl_ctx != NULL && list != NULL) {
	619	SSL_CTX_set_client_CA_list(server->ssl_ctx, list);
	620	SSL_CTX_set_verify(server->ssl_ctx, SSL_VERIFY_PEER \|
	621	SSL_VERIFY_FAIL_IF_NO_PEER_CERT, NULL);
	622	return 0;
	623	}
624	624	#endif
625		return server != NULL && cert == NULL ? 0 : -1;
	625	return server != NULL && cert == NULL ? 0 : -1;
626	626	}
627	627
628	628	int ns_set_ssl_cert(struct ns_server server, const char cert) {
629	629	#ifdef NS_ENABLE_SSL
630		if (cert != NULL &&
631		(server->ssl_ctx = SSL_CTX_new(SSLv23_server_method())) == NULL) {
632		return -1;
633		} else if (SSL_CTX_use_certificate_file(server->ssl_ctx, cert, 1) == 0 \|\|
634		SSL_CTX_use_PrivateKey_file(server->ssl_ctx, cert, 1) == 0) {
635		return -2;
636		} else {
637		SSL_CTX_set_mode(server->ssl_ctx, SSL_MODE_ACCEPT_MOVING_WRITE_BUFFER);
638		SSL_CTX_use_certificate_chain_file(server->ssl_ctx, cert);
639		return 0;
640		}
	630	if (cert != NULL &&
	631	(server->ssl_ctx = SSL_CTX_new(SSLv23_server_method())) == NULL) {
	632	return -1;
	633	} else if (SSL_CTX_use_certificate_file(server->ssl_ctx, cert, 1) == 0 \|\|
	634	SSL_CTX_use_PrivateKey_file(server->ssl_ctx, cert, 1) == 0) {
	635	return -2;
	636	} else {
	637	SSL_CTX_set_mode(server->ssl_ctx, SSL_MODE_ACCEPT_MOVING_WRITE_BUFFER);
	638	SSL_CTX_use_certificate_chain_file(server->ssl_ctx, cert);
	639	return 0;
	640	}
641	641	#endif
642		return server != NULL && cert == NULL ? 0 : -3;
	642	return server != NULL && cert == NULL ? 0 : -3;
643	643	}
644	644
645	645	int ns_bind(struct ns_server server, const char str) {
646		union socket_address sa;
647		ns_parse_port_string(str, &sa);
648		if (server->listening_sock != INVALID_SOCKET) {
649		closesocket(server->listening_sock);
650		}
651		server->listening_sock = ns_open_listening_socket(&sa);
652		return server->listening_sock == INVALID_SOCKET ? -1 :
653		(int) ntohs(sa.sin.sin_port);
	646	union socket_address sa;
	647	ns_parse_port_string(str, &sa);
	648	if (server->listening_sock != INVALID_SOCKET) {
	649	closesocket(server->listening_sock);
	650	}
	651	server->listening_sock = ns_open_listening_socket(&sa);
	652	return server->listening_sock == INVALID_SOCKET ? -1 :
	653	(int) ntohs(sa.sin.sin_port);
654	654	}
655	655
656	656
657	657	static struct ns_connection accept_conn(struct ns_server server) {
658		struct ns_connection *c = NULL;
659		union socket_address sa;
660		socklen_t len = sizeof(sa);
661		sock_t sock = INVALID_SOCKET;
	658	struct ns_connection *c = NULL;
	659	union socket_address sa;
	660	socklen_t len = sizeof(sa);
	661	sock_t sock = INVALID_SOCKET;
662	662
663		// NOTE(lsm): on Windows, sock is always > FD_SETSIZE
664		if ((sock = accept(server->listening_sock, &sa.sa, &len)) == INVALID_SOCKET) {
665		} else if ((c = (struct ns_connection ) NS_MALLOC(sizeof(c))) == NULL \|\|
666		memset(c, 0, sizeof(*c)) == NULL) {
667		closesocket(sock);
	663	// NOTE(lsm): on Windows, sock is always > FD_SETSIZE
	664	if ((sock = accept(server->listening_sock, &sa.sa, &len)) == INVALID_SOCKET) {
	665	} else if ((c = (struct ns_connection ) NS_MALLOC(sizeof(c))) == NULL \|\|
	666	memset(c, 0, sizeof(*c)) == NULL) {
	667	closesocket(sock);
668	668	#ifdef NS_ENABLE_SSL
669		} else if (server->ssl_ctx != NULL &&
670		((c->ssl = SSL_new(server->ssl_ctx)) == NULL \|\|
671		SSL_set_fd(c->ssl, sock) != 1)) {
672		DBG(("SSL error"));
673		closesocket(sock);
674		free(c);
675		c = NULL;
	669	} else if (server->ssl_ctx != NULL &&
	670	((c->ssl = SSL_new(server->ssl_ctx)) == NULL \|\|
	671	SSL_set_fd(c->ssl, sock) != 1)) {
	672	DBG(("SSL error"));
	673	closesocket(sock);
	674	free(c);
	675	c = NULL;
676	676	#endif
677		} else {
678		ns_set_close_on_exec(sock);
679		ns_set_non_blocking_mode(sock);
680		c->server = server;
681		c->sock = sock;
682		c->flags \|= NSF_ACCEPTED;
	677	} else {
	678	ns_set_close_on_exec(sock);
	679	ns_set_non_blocking_mode(sock);
	680	c->server = server;
	681	c->sock = sock;
	682	c->flags \|= NSF_ACCEPTED;
683	683
684		ns_add_conn(server, c);
685		ns_call(c, NS_ACCEPT, &sa);
686		DBG(("%p %d %p %p", c, c->sock, c->ssl, server->ssl_ctx));
687		}
	684	ns_add_conn(server, c);
	685	ns_call(c, NS_ACCEPT, &sa);
	686	DBG(("%p %d %p %p", c, c->sock, c->ssl, server->ssl_ctx));
	687	}
688	688
689		return c;
	689	return c;
690	690	}
691	691
692	692	static int ns_is_error(int n) {
693		return n == 0 \|\|
694		(n < 0 && errno != EINTR && errno != EINPROGRESS &&
695		errno != EAGAIN && errno != EWOULDBLOCK
	693	return n == 0 \|\|
	694	(n < 0 && errno != EINTR && errno != EINPROGRESS &&
	695	errno != EAGAIN && errno != EWOULDBLOCK
696	696	#ifdef _WIN32
697		&& WSAGetLastError() != WSAEINTR && WSAGetLastError() != WSAEWOULDBLOCK
	697	&& WSAGetLastError() != WSAEINTR && WSAGetLastError() != WSAEWOULDBLOCK
698	698	#endif
699		);
	699	);
700	700	}
701	701
702	702	void ns_sock_to_str(sock_t sock, char *buf, size_t len, int flags) {
703		union socket_address sa;
704		socklen_t slen = sizeof(sa);
	703	union socket_address sa;
	704	socklen_t slen = sizeof(sa);
705	705
706		if (buf != NULL && len > 0) {
707		buf[0] = '\0';
708		memset(&sa, 0, sizeof(sa));
709		if (flags & 4) {
710		getpeername(sock, &sa.sa, &slen);
711		} else {
712		getsockname(sock, &sa.sa, &slen);
713		}
714		if (flags & 1) {
	706	if (buf != NULL && len > 0) {
	707	buf[0] = '\0';
	708	memset(&sa, 0, sizeof(sa));
	709	if (flags & 4) {
	710	getpeername(sock, &sa.sa, &slen);
	711	} else {
	712	getsockname(sock, &sa.sa, &slen);
	713	}
	714	if (flags & 1) {
715	715	#if defined(NS_ENABLE_IPV6)
716		inet_ntop(sa.sa.sa_family, sa.sa.sa_family == AF_INET ?
717		(void *) &sa.sin.sin_addr :
718		(void *) &sa.sin6.sin6_addr, buf, len);
	716	inet_ntop(sa.sa.sa_family, sa.sa.sa_family == AF_INET ?
	717	(void *) &sa.sin.sin_addr :
	718	(void *) &sa.sin6.sin6_addr, buf, len);
719	719	#elif defined(_WIN32)
720		// Only Windoze Vista (and newer) have inet_ntop()
721		strncpy(buf, inet_ntoa(sa.sin.sin_addr), len);
	720	// Only Windoze Vista (and newer) have inet_ntop()
	721	strncpy(buf, inet_ntoa(sa.sin.sin_addr), len);
722	722	#else
723		inet_ntop(sa.sa.sa_family, (void *) &sa.sin.sin_addr, buf, len);
	723	inet_ntop(sa.sa.sa_family, (void *) &sa.sin.sin_addr, buf, len);
724	724	#endif
725		}
726		if (flags & 2) {
727		snprintf(buf + strlen(buf), len - (strlen(buf) + 1), "%s%d",
728		flags & 1 ? ":" : "", (int) ntohs(sa.sin.sin_port));
729		}
730		}
	725	}
	726	if (flags & 2) {
	727	snprintf(buf + strlen(buf), len - (strlen(buf) + 1), "%s%d",
	728	flags & 1 ? ":" : "", (int) ntohs(sa.sin.sin_port));
	729	}
	730	}
731	731	}
732	732
733	733	int ns_hexdump(const void buf, int len, char dst, int dst_len) {
734		const unsigned char p = (const unsigned char ) buf;
735		char ascii[17] = "";
736		int i, idx, n = 0;
	734	const unsigned char p = (const unsigned char ) buf;
	735	char ascii[17] = "";
	736	int i, idx, n = 0;
737	737
738		for (i = 0; i < len; i++) {
739		idx = i % 16;
740		if (idx == 0) {
741		if (i > 0) n += snprintf(dst + n, dst_len - n, " %s\n", ascii);
742		n += snprintf(dst + n, dst_len - n, "%04x ", i);
743		}
744		n += snprintf(dst + n, dst_len - n, " %02x", p[i]);
745		ascii[idx] = p[i] < 0x20 \|\| p[i] > 0x7e ? '.' : p[i];
746		ascii[idx + 1] = '\0';
747		}
	738	for (i = 0; i < len; i++) {
	739	idx = i % 16;
	740	if (idx == 0) {
	741	if (i > 0) n += snprintf(dst + n, dst_len - n, " %s\n", ascii);
	742	n += snprintf(dst + n, dst_len - n, "%04x ", i);
	743	}
	744	n += snprintf(dst + n, dst_len - n, " %02x", p[i]);
	745	ascii[idx] = p[i] < 0x20 \|\| p[i] > 0x7e ? '.' : p[i];
	746	ascii[idx + 1] = '\0';
	747	}
748	748
749		while (i++ % 16) n += snprintf(dst + n, dst_len - n, "%s", " ");
750		n += snprintf(dst + n, dst_len - n, " %s\n\n", ascii);
	749	while (i++ % 16) n += snprintf(dst + n, dst_len - n, "%s", " ");
	750	n += snprintf(dst + n, dst_len - n, " %s\n\n", ascii);
751	751
752		return n;
	752	return n;
753	753	}
754	754
755	755	#ifdef NS_ENABLE_SSL
756	756	static int ns_ssl_err(struct ns_connection *conn, int res) {
757		int ssl_err = SSL_get_error(conn->ssl, res);
758		if (ssl_err == SSL_ERROR_WANT_READ) conn->flags \|= NSF_WANT_READ;
759		if (ssl_err == SSL_ERROR_WANT_WRITE) conn->flags \|= NSF_WANT_WRITE;
760		return ssl_err;
	757	int ssl_err = SSL_get_error(conn->ssl, res);
	758	if (ssl_err == SSL_ERROR_WANT_READ) conn->flags \|= NSF_WANT_READ;
	759	if (ssl_err == SSL_ERROR_WANT_WRITE) conn->flags \|= NSF_WANT_WRITE;
	760	return ssl_err;
761	761	}
762	762	#endif
763	763
764	764	static void ns_read_from_socket(struct ns_connection *conn) {
765		char buf[2048];
766		int n = 0;
	765	char buf[2048];
	766	int n = 0;
767	767
768		if (conn->flags & NSF_CONNECTING) {
769		int ok = 1, ret;
770		socklen_t len = sizeof(ok);
	768	if (conn->flags & NSF_CONNECTING) {
	769	int ok = 1, ret;
	770	socklen_t len = sizeof(ok);
771	771
772		ret = getsockopt(conn->sock, SOL_SOCKET, SO_ERROR, (char *) &ok, &len);
773		(void) ret;
	772	ret = getsockopt(conn->sock, SOL_SOCKET, SO_ERROR, (char *) &ok, &len);
	773	(void) ret;
774	774	#ifdef NS_ENABLE_SSL
775		if (ret == 0 && ok == 0 && conn->ssl != NULL) {
776		int res = SSL_connect(conn->ssl);
777		int ssl_err = ns_ssl_err(conn, res);
778		if (res == 1) {
779		conn->flags \|= NSF_SSL_HANDSHAKE_DONE;
780		} else if (ssl_err == SSL_ERROR_WANT_READ \|\|
781		ssl_err == SSL_ERROR_WANT_WRITE) {
782		return; // Call us again
783		} else {
784		ok = 1;
785		}
786		}
	775	if (ret == 0 && ok == 0 && conn->ssl != NULL) {
	776	int res = SSL_connect(conn->ssl);
	777	int ssl_err = ns_ssl_err(conn, res);
	778	if (res == 1) {
	779	conn->flags \|= NSF_SSL_HANDSHAKE_DONE;
	780	} else if (ssl_err == SSL_ERROR_WANT_READ \|\|
	781	ssl_err == SSL_ERROR_WANT_WRITE) {
	782	return; // Call us again
	783	} else {
	784	ok = 1;
	785	}
	786	}
787	787	#endif
788		conn->flags &= ~NSF_CONNECTING;
789		DBG(("%p ok=%d", conn, ok));
790		if (ok != 0) {
791		conn->flags \|= NSF_CLOSE_IMMEDIATELY;
792		}
793		ns_call(conn, NS_CONNECT, &ok);
794		return;
795		}
	788	conn->flags &= ~NSF_CONNECTING;
	789	DBG(("%p ok=%d", conn, ok));
	790	if (ok != 0) {
	791	conn->flags \|= NSF_CLOSE_IMMEDIATELY;
	792	}
	793	ns_call(conn, NS_CONNECT, &ok);
	794	return;
	795	}
796	796
797	797	#ifdef NS_ENABLE_SSL
798		if (conn->ssl != NULL) {
799		if (conn->flags & NSF_SSL_HANDSHAKE_DONE) {
800		// SSL library may have more bytes ready to read then we ask to read.
801		// Therefore, read in a loop until we read everything. Without the loop,
802		// we skip to the next select() cycle which can just timeout.
803		while ((n = SSL_read(conn->ssl, buf, sizeof(buf))) > 0) {
804		DBG(("%p %d <- %d bytes (SSL)", conn, conn->flags, n));
805		iobuf_append(&conn->recv_iobuf, buf, n);
806		ns_call(conn, NS_RECV, &n);
807		}
808		ns_ssl_err(conn, n);
809		} else {
810		int res = SSL_accept(conn->ssl);
811		int ssl_err = ns_ssl_err(conn, res);
812		if (res == 1) {
813		conn->flags \|= NSF_SSL_HANDSHAKE_DONE;
814		} else if (ssl_err == SSL_ERROR_WANT_READ \|\|
815		ssl_err == SSL_ERROR_WANT_WRITE) {
816		return; // Call us again
817		} else {
818		conn->flags \|= NSF_CLOSE_IMMEDIATELY;
819		}
820		return;
821		}
822		} else
	798	if (conn->ssl != NULL) {
	799	if (conn->flags & NSF_SSL_HANDSHAKE_DONE) {
	800	// SSL library may have more bytes ready to read then we ask to read.
	801	// Therefore, read in a loop until we read everything. Without the loop,
	802	// we skip to the next select() cycle which can just timeout.
	803	while ((n = SSL_read(conn->ssl, buf, sizeof(buf))) > 0) {
	804	DBG(("%p %d <- %d bytes (SSL)", conn, conn->flags, n));
	805	iobuf_append(&conn->recv_iobuf, buf, n);
	806	ns_call(conn, NS_RECV, &n);
	807	}
	808	ns_ssl_err(conn, n);
	809	} else {
	810	int res = SSL_accept(conn->ssl);
	811	int ssl_err = ns_ssl_err(conn, res);
	812	if (res == 1) {
	813	conn->flags \|= NSF_SSL_HANDSHAKE_DONE;
	814	} else if (ssl_err == SSL_ERROR_WANT_READ \|\|
	815	ssl_err == SSL_ERROR_WANT_WRITE) {
	816	return; // Call us again
	817	} else {
	818	conn->flags \|= NSF_CLOSE_IMMEDIATELY;
	819	}
	820	return;
	821	}
	822	} else
823	823	#endif
824		{
825		while ((n = recv(conn->sock, buf, sizeof(buf), 0)) > 0) {
826		DBG(("%p %d <- %d bytes (PLAIN)", conn, conn->flags, n));
827		iobuf_append(&conn->recv_iobuf, buf, n);
828		ns_call(conn, NS_RECV, &n);
829		}
830		}
	824	{
	825	while ((n = recv(conn->sock, buf, sizeof(buf), 0)) > 0) {
	826	DBG(("%p %d <- %d bytes (PLAIN)", conn, conn->flags, n));
	827	iobuf_append(&conn->recv_iobuf, buf, n);
	828	ns_call(conn, NS_RECV, &n);
	829	}
	830	}
831	831
832		if (ns_is_error(n)) {
833		conn->flags \|= NSF_CLOSE_IMMEDIATELY;
834		}
	832	if (ns_is_error(n)) {
	833	conn->flags \|= NSF_CLOSE_IMMEDIATELY;
	834	}
835	835	}
836	836
837	837	static void ns_write_to_socket(struct ns_connection *conn) {
838		struct iobuf *io = &conn->send_iobuf;
839		int n = 0;
	838	struct iobuf *io = &conn->send_iobuf;
	839	int n = 0;
840	840
841	841	#ifdef NS_ENABLE_SSL
842		if (conn->ssl != NULL) {
843		n = SSL_write(conn->ssl, io->buf, io->len);
844		if (n <= 0) {
845		int ssl_err = ns_ssl_err(conn, n);
846		if (ssl_err == SSL_ERROR_WANT_READ \|\| ssl_err == SSL_ERROR_WANT_WRITE) {
847		return; // Call us again
848		} else {
849		conn->flags \|= NSF_CLOSE_IMMEDIATELY;
850		}
851		}
852		} else
	842	if (conn->ssl != NULL) {
	843	n = SSL_write(conn->ssl, io->buf, io->len);
	844	if (n <= 0) {
	845	int ssl_err = ns_ssl_err(conn, n);
	846	if (ssl_err == SSL_ERROR_WANT_READ \|\| ssl_err == SSL_ERROR_WANT_WRITE) {
	847	return; // Call us again
	848	} else {
	849	conn->flags \|= NSF_CLOSE_IMMEDIATELY;
	850	}
	851	}
	852	} else
853	853	#endif
854		{ n = send(conn->sock, io->buf, io->len, 0); }
	854	{ n = send(conn->sock, io->buf, io->len, 0); }
855	855
856		DBG(("%p %d -> %d bytes", conn, conn->flags, n));
	856	DBG(("%p %d -> %d bytes", conn, conn->flags, n));
857	857
858		ns_call(conn, NS_SEND, &n);
859		if (ns_is_error(n)) {
860		conn->flags \|= NSF_CLOSE_IMMEDIATELY;
861		} else if (n > 0) {
862		iobuf_remove(io, n);
863		}
	858	ns_call(conn, NS_SEND, &n);
	859	if (ns_is_error(n)) {
	860	conn->flags \|= NSF_CLOSE_IMMEDIATELY;
	861	} else if (n > 0) {
	862	iobuf_remove(io, n);
	863	}
864	864	}
865	865
866	866	int ns_send(struct ns_connection conn, const void buf, int len) {
867		return iobuf_append(&conn->send_iobuf, buf, len);
	867	return iobuf_append(&conn->send_iobuf, buf, len);
868	868	}
869	869
870	870	static void ns_add_to_set(sock_t sock, fd_set set, sock_t max_fd) {
871		if (sock != INVALID_SOCKET) {
872		FD_SET(sock, set);
873		if (max_fd == INVALID_SOCKET \|\| sock > max_fd) {
874		*max_fd = sock;
875		}
876		}
	871	if (sock != INVALID_SOCKET) {
	872	FD_SET(sock, set);
	873	if (max_fd == INVALID_SOCKET \|\| sock > max_fd) {
	874	*max_fd = sock;
	875	}
	876	}
877	877	}
878	878
879	879	int ns_server_poll(struct ns_server *server, int milli) {
880		struct ns_connection conn, tmp_conn;
881		struct timeval tv;
882		fd_set read_set, write_set;
883		int num_active_connections = 0;
884		sock_t max_fd = INVALID_SOCKET;
885		time_t current_time = time(NULL);
	880	struct ns_connection conn, tmp_conn;
	881	struct timeval tv;
	882	fd_set read_set, write_set;
	883	int num_active_connections = 0;
	884	sock_t max_fd = INVALID_SOCKET;
	885	time_t current_time = time(NULL);
886	886
887		if (server->listening_sock == INVALID_SOCKET &&
888		server->active_connections == NULL) return 0;
	887	if (server->listening_sock == INVALID_SOCKET &&
	888	server->active_connections == NULL) return 0;
889	889
890		FD_ZERO(&read_set);
891		FD_ZERO(&write_set);
892		ns_add_to_set(server->listening_sock, &read_set, &max_fd);
893		ns_add_to_set(server->ctl[1], &read_set, &max_fd);
	890	FD_ZERO(&read_set);
	891	FD_ZERO(&write_set);
	892	ns_add_to_set(server->listening_sock, &read_set, &max_fd);
	893	ns_add_to_set(server->ctl[1], &read_set, &max_fd);
894	894
895		for (conn = server->active_connections; conn != NULL; conn = tmp_conn) {
896		tmp_conn = conn->next;
897		ns_call(conn, NS_POLL, &current_time);
898		if (!(conn->flags & NSF_WANT_WRITE)) {
899		//DBG(("%p read_set", conn));
900		ns_add_to_set(conn->sock, &read_set, &max_fd);
901		}
902		if (((conn->flags & NSF_CONNECTING) && !(conn->flags & NSF_WANT_READ)) \|\|
903		(conn->send_iobuf.len > 0 && !(conn->flags & NSF_CONNECTING) &&
904		!(conn->flags & NSF_BUFFER_BUT_DONT_SEND))) {
905		//DBG(("%p write_set", conn));
906		ns_add_to_set(conn->sock, &write_set, &max_fd);
907		}
908		if (conn->flags & NSF_CLOSE_IMMEDIATELY) {
909		ns_close_conn(conn);
910		}
911		}
	895	for (conn = server->active_connections; conn != NULL; conn = tmp_conn) {
	896	tmp_conn = conn->next;
	897	ns_call(conn, NS_POLL, &current_time);
	898	if (!(conn->flags & NSF_WANT_WRITE)) {
	899	//DBG(("%p read_set", conn));
	900	ns_add_to_set(conn->sock, &read_set, &max_fd);
	901	}
	902	if (((conn->flags & NSF_CONNECTING) && !(conn->flags & NSF_WANT_READ)) \|\|
	903	(conn->send_iobuf.len > 0 && !(conn->flags & NSF_CONNECTING) &&
	904	!(conn->flags & NSF_BUFFER_BUT_DONT_SEND))) {
	905	//DBG(("%p write_set", conn));
	906	ns_add_to_set(conn->sock, &write_set, &max_fd);
	907	}
	908	if (conn->flags & NSF_CLOSE_IMMEDIATELY) {
	909	ns_close_conn(conn);
	910	}
	911	}
912	912
913		tv.tv_sec = milli / 1000;
914		tv.tv_usec = (milli % 1000) * 1000;
	913	tv.tv_sec = milli / 1000;
	914	tv.tv_usec = (milli % 1000) * 1000;
915	915
916		if (select((int) max_fd + 1, &read_set, &write_set, NULL, &tv) > 0) {
917		// select() might have been waiting for a long time, reset current_time
918		// now to prevent last_io_time being set to the past.
919		current_time = time(NULL);
	916	if (select((int) max_fd + 1, &read_set, &write_set, NULL, &tv) > 0) {
	917	// select() might have been waiting for a long time, reset current_time
	918	// now to prevent last_io_time being set to the past.
	919	current_time = time(NULL);
920	920
921		// Accept new connections
922		if (server->listening_sock != INVALID_SOCKET &&
923		FD_ISSET(server->listening_sock, &read_set)) {
924		// We're not looping here, and accepting just one connection at
925		// a time. The reason is that eCos does not respect non-blocking
926		// flag on a listening socket and hangs in a loop.
927		if ((conn = accept_conn(server)) != NULL) {
928		conn->last_io_time = current_time;
929		}
930		}
	921	// Accept new connections
	922	if (server->listening_sock != INVALID_SOCKET &&
	923	FD_ISSET(server->listening_sock, &read_set)) {
	924	// We're not looping here, and accepting just one connection at
	925	// a time. The reason is that eCos does not respect non-blocking
	926	// flag on a listening socket and hangs in a loop.
	927	if ((conn = accept_conn(server)) != NULL) {
	928	conn->last_io_time = current_time;
	929	}
	930	}
931	931
932		// Read wakeup messages
933		if (server->ctl[1] != INVALID_SOCKET &&
934		FD_ISSET(server->ctl[1], &read_set)) {
935		struct ctl_msg ctl_msg;
936		int len = recv(server->ctl[1], (char *) &ctl_msg, sizeof(ctl_msg), 0);
937		send(server->ctl[1], ctl_msg.message, 1, 0);
938		if (len >= (int) sizeof(ctl_msg.callback) && ctl_msg.callback != NULL) {
939		ns_iterate(server, ctl_msg.callback, ctl_msg.message);
940		}
941		}
	932	// Read wakeup messages
	933	if (server->ctl[1] != INVALID_SOCKET &&
	934	FD_ISSET(server->ctl[1], &read_set)) {
	935	struct ctl_msg ctl_msg;
	936	int len = recv(server->ctl[1], (char *) &ctl_msg, sizeof(ctl_msg), 0);
	937	send(server->ctl[1], ctl_msg.message, 1, 0);
	938	if (len >= (int) sizeof(ctl_msg.callback) && ctl_msg.callback != NULL) {
	939	ns_iterate(server, ctl_msg.callback, ctl_msg.message);
	940	}
	941	}
942	942
943		for (conn = server->active_connections; conn != NULL; conn = tmp_conn) {
944		tmp_conn = conn->next;
945		if (FD_ISSET(conn->sock, &read_set)) {
946		conn->last_io_time = current_time;
947		ns_read_from_socket(conn);
948		}
949		if (FD_ISSET(conn->sock, &write_set)) {
950		if (conn->flags & NSF_CONNECTING) {
951		ns_read_from_socket(conn);
952		} else if (!(conn->flags & NSF_BUFFER_BUT_DONT_SEND)) {
953		conn->last_io_time = current_time;
954		ns_write_to_socket(conn);
955		}
956		}
957		}
958		}
	943	for (conn = server->active_connections; conn != NULL; conn = tmp_conn) {
	944	tmp_conn = conn->next;
	945	if (FD_ISSET(conn->sock, &read_set)) {
	946	conn->last_io_time = current_time;
	947	ns_read_from_socket(conn);
	948	}
	949	if (FD_ISSET(conn->sock, &write_set)) {
	950	if (conn->flags & NSF_CONNECTING) {
	951	ns_read_from_socket(conn);
	952	} else if (!(conn->flags & NSF_BUFFER_BUT_DONT_SEND)) {
	953	conn->last_io_time = current_time;
	954	ns_write_to_socket(conn);
	955	}
	956	}
	957	}
	958	}
959	959
960		for (conn = server->active_connections; conn != NULL; conn = tmp_conn) {
961		tmp_conn = conn->next;
962		num_active_connections++;
963		if ((conn->flags & NSF_CLOSE_IMMEDIATELY) \|\|
964		(conn->send_iobuf.len == 0 &&
965		(conn->flags & NSF_FINISHED_SENDING_DATA))) {
966		ns_close_conn(conn);
967		}
968		}
969		//DBG(("%d active connections", num_active_connections));
	960	for (conn = server->active_connections; conn != NULL; conn = tmp_conn) {
	961	tmp_conn = conn->next;
	962	num_active_connections++;
	963	if ((conn->flags & NSF_CLOSE_IMMEDIATELY) \|\|
	964	(conn->send_iobuf.len == 0 &&
	965	(conn->flags & NSF_FINISHED_SENDING_DATA))) {
	966	ns_close_conn(conn);
	967	}
	968	}
	969	//DBG(("%d active connections", num_active_connections));
970	970
971		return num_active_connections;
	971	return num_active_connections;
972	972	}
973	973
974	974	struct ns_connection ns_connect(struct ns_server server, const char *host,
975		int port, int use_ssl, void *param) {
976		sock_t sock = INVALID_SOCKET;
977		struct sockaddr_in sin;
978		struct hostent *he = NULL;
979		struct ns_connection *conn = NULL;
980		int connect_ret_val;
	975	int port, int use_ssl, void *param) {
	976	sock_t sock = INVALID_SOCKET;
	977	struct sockaddr_in sin;
	978	struct hostent *he = NULL;
	979	struct ns_connection *conn = NULL;
	980	int connect_ret_val;
981	981
982		(void) use_ssl;
	982	(void) use_ssl;
983	983
984		if (host == NULL \|\| (he = gethostbyname(host)) == NULL \|\|
985		(sock = socket(AF_INET, SOCK_STREAM, 0)) == INVALID_SOCKET) {
986		DBG(("gethostbyname(%s) failed: %s", host, strerror(errno)));
987		return NULL;
988		}
	984	if (host == NULL \|\| (he = gethostbyname(host)) == NULL \|\|
	985	(sock = socket(AF_INET, SOCK_STREAM, 0)) == INVALID_SOCKET) {
	986	DBG(("gethostbyname(%s) failed: %s", host, strerror(errno)));
	987	return NULL;
	988	}
989	989
990		sin.sin_family = AF_INET;
991		sin.sin_port = htons((uint16_t) port);
992		sin.sin_addr = * (struct in_addr *) he->h_addr_list[0];
993		ns_set_non_blocking_mode(sock);
	990	sin.sin_family = AF_INET;
	991	sin.sin_port = htons((uint16_t) port);
	992	sin.sin_addr = * (struct in_addr *) he->h_addr_list[0];
	993	ns_set_non_blocking_mode(sock);
994	994
995		connect_ret_val = connect(sock, (struct sockaddr *) &sin, sizeof(sin));
996		if (ns_is_error(connect_ret_val)) {
997		closesocket(sock);
998		return NULL;
999		} else if ((conn = (struct ns_connection *)
1000		NS_MALLOC(sizeof(*conn))) == NULL) {
1001		closesocket(sock);
1002		return NULL;
1003		}
	995	connect_ret_val = connect(sock, (struct sockaddr *) &sin, sizeof(sin));
	996	if (ns_is_error(connect_ret_val)) {
	997	closesocket(sock);
	998	return NULL;
	999	} else if ((conn = (struct ns_connection *)
	1000	NS_MALLOC(sizeof(*conn))) == NULL) {
	1001	closesocket(sock);
	1002	return NULL;
	1003	}
1004	1004
1005		memset(conn, 0, sizeof(*conn));
1006		conn->server = server;
1007		conn->sock = sock;
1008		conn->connection_data = param;
1009		conn->flags = NSF_CONNECTING;
1010		conn->last_io_time = time(NULL);
	1005	memset(conn, 0, sizeof(*conn));
	1006	conn->server = server;
	1007	conn->sock = sock;
	1008	conn->connection_data = param;
	1009	conn->flags = NSF_CONNECTING;
	1010	conn->last_io_time = time(NULL);
1011	1011
1012	1012	#ifdef NS_ENABLE_SSL
1013		if (use_ssl &&
1014		(conn->ssl = SSL_new(server->client_ssl_ctx)) != NULL) {
1015		SSL_set_fd(conn->ssl, sock);
1016		}
	1013	if (use_ssl &&
	1014	(conn->ssl = SSL_new(server->client_ssl_ctx)) != NULL) {
	1015	SSL_set_fd(conn->ssl, sock);
	1016	}
1017	1017	#endif
1018	1018
1019		ns_add_conn(server, conn);
1020		DBG(("%p %s:%d %d %p", conn, host, port, conn->sock, conn->ssl));
	1019	ns_add_conn(server, conn);
	1020	DBG(("%p %s:%d %d %p", conn, host, port, conn->sock, conn->ssl));
1021	1021
1022		return conn;
	1022	return conn;
1023	1023	}
1024	1024
1025	1025	struct ns_connection ns_add_sock(struct ns_server s, sock_t sock, void *p) {
1026		struct ns_connection *conn;
1027		if ((conn = (struct ns_connection ) NS_MALLOC(sizeof(conn))) != NULL) {
1028		memset(conn, 0, sizeof(*conn));
1029		ns_set_non_blocking_mode(sock);
1030		conn->sock = sock;
1031		conn->connection_data = p;
1032		conn->server = s;
1033		conn->last_io_time = time(NULL);
1034		ns_add_conn(s, conn);
1035		DBG(("%p %d", conn, sock));
1036		}
1037		return conn;
	1026	struct ns_connection *conn;
	1027	if ((conn = (struct ns_connection ) NS_MALLOC(sizeof(conn))) != NULL) {
	1028	memset(conn, 0, sizeof(*conn));
	1029	ns_set_non_blocking_mode(sock);
	1030	conn->sock = sock;
	1031	conn->connection_data = p;
	1032	conn->server = s;
	1033	conn->last_io_time = time(NULL);
	1034	ns_add_conn(s, conn);
	1035	DBG(("%p %d", conn, sock));
	1036	}
	1037	return conn;
1038	1038	}
1039	1039
1040	1040	struct ns_connection ns_next(struct ns_server s, struct ns_connection *conn) {
1041		return conn == NULL ? s->active_connections : conn->next;
	1041	return conn == NULL ? s->active_connections : conn->next;
1042	1042	}
1043	1043
1044	1044	void ns_iterate(struct ns_server server, ns_callback_t cb, void param) {
1045		struct ns_connection conn, tmp_conn;
	1045	struct ns_connection conn, tmp_conn;
1046	1046
1047		for (conn = server->active_connections; conn != NULL; conn = tmp_conn) {
1048		tmp_conn = conn->next;
1049		cb(conn, NS_POLL, param);
1050		}
	1047	for (conn = server->active_connections; conn != NULL; conn = tmp_conn) {
	1048	tmp_conn = conn->next;
	1049	cb(conn, NS_POLL, param);
	1050	}
1051	1051	}
1052	1052
1053	1053	void ns_server_wakeup_ex(struct ns_server *server, ns_callback_t cb,
1054		void *data, size_t len) {
1055		struct ctl_msg ctl_msg;
1056		if (server->ctl[0] != INVALID_SOCKET && data != NULL &&
1057		len < sizeof(ctl_msg.message)) {
1058		ctl_msg.callback = cb;
1059		memcpy(ctl_msg.message, data, len);
1060		send(server->ctl[0], (char *) &ctl_msg,
1061		offsetof(struct ctl_msg, message) + len, 0);
1062		recv(server->ctl[0], (char *) &len, 1, 0);
1063		}
	1054	void *data, size_t len) {
	1055	struct ctl_msg ctl_msg;
	1056	if (server->ctl[0] != INVALID_SOCKET && data != NULL &&
	1057	len < sizeof(ctl_msg.message)) {
	1058	ctl_msg.callback = cb;
	1059	memcpy(ctl_msg.message, data, len);
	1060	send(server->ctl[0], (char *) &ctl_msg,
	1061	offsetof(struct ctl_msg, message) + len, 0);
	1062	recv(server->ctl[0], (char *) &len, 1, 0);
	1063	}
1064	1064	}
1065	1065
1066	1066	void ns_server_wakeup(struct ns_server *server) {
1067		ns_server_wakeup_ex(server, NULL, (void *) "", 0);
	1067	ns_server_wakeup_ex(server, NULL, (void *) "", 0);
1068	1068	}
1069	1069
1070	1070	void ns_server_init(struct ns_server s, void server_data, ns_callback_t cb) {
1071		memset(s, 0, sizeof(*s));
1072		s->listening_sock = s->ctl[0] = s->ctl[1] = INVALID_SOCKET;
1073		s->server_data = server_data;
1074		s->callback = cb;
	1071	memset(s, 0, sizeof(*s));
	1072	s->listening_sock = s->ctl[0] = s->ctl[1] = INVALID_SOCKET;
	1073	s->server_data = server_data;
	1074	s->callback = cb;
1075	1075
1076	1076	#ifdef _WIN32
1077		{ WSADATA data; WSAStartup(MAKEWORD(2, 2), &data); }
	1077	{ WSADATA data; WSAStartup(MAKEWORD(2, 2), &data); }
1078	1078	#else
1079		// Ignore SIGPIPE signal, so if client cancels the request, it
1080		// won't kill the whole process.
1081		signal(SIGPIPE, SIG_IGN);
	1079	// Ignore SIGPIPE signal, so if client cancels the request, it
	1080	// won't kill the whole process.
	1081	signal(SIGPIPE, SIG_IGN);
1082	1082	#endif
1083	1083
1084	1084	#ifndef NS_DISABLE_SOCKETPAIR
1085		do {
1086		ns_socketpair2(s->ctl, SOCK_DGRAM);
1087		} while (s->ctl[0] == INVALID_SOCKET);
	1085	do {
	1086	ns_socketpair2(s->ctl, SOCK_DGRAM);
	1087	} while (s->ctl[0] == INVALID_SOCKET);
1088	1088	#endif
1089	1089
1090	1090	#ifdef NS_ENABLE_SSL
1091		{static int init_done; if (!init_done) { SSL_library_init(); init_done++; }}
1092		s->client_ssl_ctx = SSL_CTX_new(SSLv23_client_method());
	1091	{static int init_done; if (!init_done) { SSL_library_init(); init_done++; }}
	1092	s->client_ssl_ctx = SSL_CTX_new(SSLv23_client_method());
1093	1093	#endif
1094	1094	}
1095	1095
1096	1096	void ns_server_free(struct ns_server *s) {
1097		struct ns_connection conn, tmp_conn;
	1097	struct ns_connection conn, tmp_conn;
1098	1098
1099		DBG(("%p", s));
1100		if (s == NULL) return;
1101		// Do one last poll, see https://github.com/cesanta/mongoose/issues/286
1102		ns_server_poll(s, 0);
	1099	DBG(("%p", s));
	1100	if (s == NULL) return;
	1101	// Do one last poll, see https://github.com/cesanta/mongoose/issues/286
	1102	ns_server_poll(s, 0);
1103	1103
1104		if (s->listening_sock != INVALID_SOCKET) closesocket(s->listening_sock);
1105		if (s->ctl[0] != INVALID_SOCKET) closesocket(s->ctl[0]);
1106		if (s->ctl[1] != INVALID_SOCKET) closesocket(s->ctl[1]);
1107		s->listening_sock = s->ctl[0] = s->ctl[1] = INVALID_SOCKET;
	1104	if (s->listening_sock != INVALID_SOCKET) closesocket(s->listening_sock);
	1105	if (s->ctl[0] != INVALID_SOCKET) closesocket(s->ctl[0]);
	1106	if (s->ctl[1] != INVALID_SOCKET) closesocket(s->ctl[1]);
	1107	s->listening_sock = s->ctl[0] = s->ctl[1] = INVALID_SOCKET;
1108	1108
1109		for (conn = s->active_connections; conn != NULL; conn = tmp_conn) {
1110		tmp_conn = conn->next;
1111		ns_close_conn(conn);
1112		}
	1109	for (conn = s->active_connections; conn != NULL; conn = tmp_conn) {
	1110	tmp_conn = conn->next;
	1111	ns_close_conn(conn);
	1112	}
1113	1113
1114	1114	#ifdef NS_ENABLE_SSL
1115		if (s->ssl_ctx != NULL) SSL_CTX_free(s->ssl_ctx);
1116		if (s->client_ssl_ctx != NULL) SSL_CTX_free(s->client_ssl_ctx);
1117		s->ssl_ctx = s->client_ssl_ctx = NULL;
	1115	if (s->ssl_ctx != NULL) SSL_CTX_free(s->ssl_ctx);
	1116	if (s->client_ssl_ctx != NULL) SSL_CTX_free(s->client_ssl_ctx);
	1117	s->ssl_ctx = s->client_ssl_ctx = NULL;
1118	1118	#endif
1119	1119	}
1120	1120	// net_skeleton end
r32760	r32761
1219	1219	#endif
1220	1220
1221	1221	struct vec {
1222		const char *ptr;
1223		int len;
	1222	const char *ptr;
	1223	int len;
1224	1224	};
1225	1225
1226	1226	// For directory listing and WevDAV support
1227	1227	struct dir_entry {
1228		struct connection *conn;
1229		char *file_name;
1230		file_stat_t st;
	1228	struct connection *conn;
	1229	char *file_name;
	1230	file_stat_t st;
1231	1231	};
1232	1232
1233	1233	// NOTE(lsm): this enum shoulds be in sync with the config_options.
1234	1234	enum {
1235		ACCESS_CONTROL_LIST,
	1235	ACCESS_CONTROL_LIST,
1236	1236	#ifndef MONGOOSE_NO_FILESYSTEM
1237		ACCESS_LOG_FILE,
	1237	ACCESS_LOG_FILE,
1238	1238	#ifndef MONGOOSE_NO_AUTH
1239		AUTH_DOMAIN,
	1239	AUTH_DOMAIN,
1240	1240	#endif
1241	1241	#ifndef MONGOOSE_NO_CGI
1242		CGI_INTERPRETER,
1243		CGI_PATTERN,
	1242	CGI_INTERPRETER,
	1243	CGI_PATTERN,
1244	1244	#endif
1245		DAV_AUTH_FILE,
1246		DOCUMENT_ROOT,
	1245	DAV_AUTH_FILE,
	1246	DOCUMENT_ROOT,
1247	1247	#ifndef MONGOOSE_NO_DIRECTORY_LISTING
1248		ENABLE_DIRECTORY_LISTING,
	1248	ENABLE_DIRECTORY_LISTING,
1249	1249	#endif
1250	1250	#endif
1251		ENABLE_PROXY,
1252		EXTRA_MIME_TYPES,
	1251	ENABLE_PROXY,
	1252	EXTRA_MIME_TYPES,
1253	1253	#if !defined(MONGOOSE_NO_FILESYSTEM) && !defined(MONGOOSE_NO_AUTH)
1254		GLOBAL_AUTH_FILE,
	1254	GLOBAL_AUTH_FILE,
1255	1255	#endif
1256	1256	#ifndef MONGOOSE_NO_FILESYSTEM
1257		HIDE_FILES_PATTERN,
1258		HEXDUMP_FILE,
1259		INDEX_FILES,
	1257	HIDE_FILES_PATTERN,
	1258	HEXDUMP_FILE,
	1259	INDEX_FILES,
1260	1260	#endif
1261		LISTENING_PORT,
	1261	LISTENING_PORT,
1262	1262	#ifndef _WIN32
1263		RUN_AS_USER,
	1263	RUN_AS_USER,
1264	1264	#endif
1265	1265	#ifndef MONGOOSE_NO_SSI
1266		SSI_PATTERN,
	1266	SSI_PATTERN,
1267	1267	#endif
1268	1268	#ifdef NS_ENABLE_SSL
1269		SSL_CERTIFICATE,
1270		SSL_CA_CERTIFICATE,
1271		SSL_MITM_CERTS,
	1269	SSL_CERTIFICATE,
	1270	SSL_CA_CERTIFICATE,
	1271	SSL_MITM_CERTS,
1272	1272	#endif
1273		URL_REWRITES,
1274		NUM_OPTIONS
	1273	URL_REWRITES,
	1274	NUM_OPTIONS
1275	1275	};
1276	1276
1277	1277	static const char *static_config_options[] = {
1278		"access_control_list", NULL,
	1278	"access_control_list", NULL,
1279	1279	#ifndef MONGOOSE_NO_FILESYSTEM
1280		"access_log_file", NULL,
	1280	"access_log_file", NULL,
1281	1281	#ifndef MONGOOSE_NO_AUTH
1282		"auth_domain", "mydomain.com",
	1282	"auth_domain", "mydomain.com",
1283	1283	#endif
1284	1284	#ifndef MONGOOSE_NO_CGI
1285		"cgi_interpreter", NULL,
1286		"cgi_pattern", DEFAULT_CGI_PATTERN,
	1285	"cgi_interpreter", NULL,
	1286	"cgi_pattern", DEFAULT_CGI_PATTERN,
1287	1287	#endif
1288		"dav_auth_file", NULL,
1289		"document_root", NULL,
	1288	"dav_auth_file", NULL,
	1289	"document_root", NULL,
1290	1290	#ifndef MONGOOSE_NO_DIRECTORY_LISTING
1291		"enable_directory_listing", "yes",
	1291	"enable_directory_listing", "yes",
1292	1292	#endif
1293	1293	#endif
1294		"enable_proxy", NULL,
1295		"extra_mime_types", NULL,
	1294	"enable_proxy", NULL,
	1295	"extra_mime_types", NULL,
1296	1296	#if !defined(MONGOOSE_NO_FILESYSTEM) && !defined(MONGOOSE_NO_AUTH)
1297		"global_auth_file", NULL,
	1297	"global_auth_file", NULL,
1298	1298	#endif
1299	1299	#ifndef MONGOOSE_NO_FILESYSTEM
1300		"hide_files_patterns", NULL,
1301		"hexdump_file", NULL,
1302		"index_files","index.html,index.htm,index.shtml,index.cgi,index.php,index.lp",
	1300	"hide_files_patterns", NULL,
	1301	"hexdump_file", NULL,
	1302	"index_files","index.html,index.htm,index.shtml,index.cgi,index.php,index.lp",
1303	1303	#endif
1304		"listening_port", NULL,
	1304	"listening_port", NULL,
1305	1305	#ifndef _WIN32
1306		"run_as_user", NULL,
	1306	"run_as_user", NULL,
1307	1307	#endif
1308	1308	#ifndef MONGOOSE_NO_SSI
1309		"ssi_pattern", ".shtml$\|.shtm$",
	1309	"ssi_pattern", ".shtml$\|.shtm$",
1310	1310	#endif
1311	1311	#ifdef NS_ENABLE_SSL
1312		"ssl_certificate", NULL,
1313		"ssl_ca_certificate", NULL,
1314		"ssl_mitm_certs", NULL,
	1312	"ssl_certificate", NULL,
	1313	"ssl_ca_certificate", NULL,
	1314	"ssl_mitm_certs", NULL,
1315	1315	#endif
1316		"url_rewrites", NULL,
1317		NULL
	1316	"url_rewrites", NULL,
	1317	NULL
1318	1318	};
1319	1319
1320	1320	struct mg_server {
1321		struct ns_server ns_server;
1322		union socket_address lsa; // Listening socket address
1323		mg_handler_t event_handler;
1324		char *config_options[NUM_OPTIONS];
	1321	struct ns_server ns_server;
	1322	union socket_address lsa; // Listening socket address
	1323	mg_handler_t event_handler;
	1324	char *config_options[NUM_OPTIONS];
1325	1325	};
1326	1326
1327	1327	// Local endpoint representation
1328	1328	union endpoint {
1329		int fd; // Opened regular local file
1330		struct ns_connection *nc; // CGI or proxy->target connection
	1329	int fd; // Opened regular local file
	1330	struct ns_connection *nc; // CGI or proxy->target connection
1331	1331	};
1332	1332
1333	1333	enum endpoint_type {
1334		EP_NONE, EP_FILE, EP_CGI, EP_USER, EP_PUT, EP_CLIENT, EP_PROXY
	1334	EP_NONE, EP_FILE, EP_CGI, EP_USER, EP_PUT, EP_CLIENT, EP_PROXY
1335	1335	};
1336	1336
1337	1337	#define MG_HEADERS_SENT NSF_USER_1
r32760	r32761
1341	1341	#define MG_PROXY_DONT_PARSE NSF_USER_5
1342	1342
1343	1343	struct connection {
1344		struct ns_connection *ns_conn; // NOTE(lsm): main.c depends on this order
1345		struct mg_connection mg_conn;
1346		struct mg_server *server;
1347		union endpoint endpoint;
1348		enum endpoint_type endpoint_type;
1349		char *path_info;
1350		char *request;
1351		int64_t num_bytes_recv; // Total number of bytes received
1352		int64_t cl; // Reply content length, for Range support
1353		int request_len; // Request length, including last \r\n after last header
	1344	struct ns_connection *ns_conn; // NOTE(lsm): main.c depends on this order
	1345	struct mg_connection mg_conn;
	1346	struct mg_server *server;
	1347	union endpoint endpoint;
	1348	enum endpoint_type endpoint_type;
	1349	char *path_info;
	1350	char *request;
	1351	int64_t num_bytes_recv; // Total number of bytes received
	1352	int64_t cl; // Reply content length, for Range support
	1353	int request_len; // Request length, including last \r\n after last header
1354	1354	};
1355	1355
1356	1356	#define MG_CONN_2_CONN(c) ((struct connection ) ((char ) (c) - \
1357		offsetof(struct connection, mg_conn)))
	1357	offsetof(struct connection, mg_conn)))
1358	1358
1359	1359	static void open_local_endpoint(struct connection *conn, int skip_user);
1360	1360	static void close_local_endpoint(struct connection *conn);
1361	1361
1362	1362	static const struct {
1363		const char *extension;
1364		size_t ext_len;
1365		const char *mime_type;
	1363	const char *extension;
	1364	size_t ext_len;
	1365	const char *mime_type;
1366	1366	} static_builtin_mime_types[] = {
1367		{".html", 5, "text/html"},
1368		{".htm", 4, "text/html"},
1369		{".shtm", 5, "text/html"},
1370		{".shtml", 6, "text/html"},
1371		{".css", 4, "text/css"},
1372		{".js", 3, "application/x-javascript"},
1373		{".ico", 4, "image/x-icon"},
1374		{".gif", 4, "image/gif"},
1375		{".jpg", 4, "image/jpeg"},
1376		{".jpeg", 5, "image/jpeg"},
1377		{".png", 4, "image/png"},
1378		{".svg", 4, "image/svg+xml"},
1379		{".txt", 4, "text/plain"},
1380		{".torrent", 8, "application/x-bittorrent"},
1381		{".wav", 4, "audio/x-wav"},
1382		{".mp3", 4, "audio/x-mp3"},
1383		{".mid", 4, "audio/mid"},
1384		{".m3u", 4, "audio/x-mpegurl"},
1385		{".ogg", 4, "application/ogg"},
1386		{".ram", 4, "audio/x-pn-realaudio"},
1387		{".xml", 4, "text/xml"},
1388		{".json", 5, "application/json"},
1389		{".xslt", 5, "application/xml"},
1390		{".xsl", 4, "application/xml"},
1391		{".ra", 3, "audio/x-pn-realaudio"},
1392		{".doc", 4, "application/msword"},
1393		{".exe", 4, "application/octet-stream"},
1394		{".zip", 4, "application/x-zip-compressed"},
1395		{".xls", 4, "application/excel"},
1396		{".tgz", 4, "application/x-tar-gz"},
1397		{".tar", 4, "application/x-tar"},
1398		{".gz", 3, "application/x-gunzip"},
1399		{".arj", 4, "application/x-arj-compressed"},
1400		{".rar", 4, "application/x-rar-compressed"},
1401		{".rtf", 4, "application/rtf"},
1402		{".pdf", 4, "application/pdf"},
1403		{".swf", 4, "application/x-shockwave-flash"},
1404		{".mpg", 4, "video/mpeg"},
1405		{".webm", 5, "video/webm"},
1406		{".mpeg", 5, "video/mpeg"},
1407		{".mov", 4, "video/quicktime"},
1408		{".mp4", 4, "video/mp4"},
1409		{".m4v", 4, "video/x-m4v"},
1410		{".asf", 4, "video/x-ms-asf"},
1411		{".avi", 4, "video/x-msvideo"},
1412		{".bmp", 4, "image/bmp"},
1413		{".ttf", 4, "application/x-font-ttf"},
1414		{NULL, 0, NULL}
	1367	{".html", 5, "text/html"},
	1368	{".htm", 4, "text/html"},
	1369	{".shtm", 5, "text/html"},
	1370	{".shtml", 6, "text/html"},
	1371	{".css", 4, "text/css"},
	1372	{".js", 3, "application/x-javascript"},
	1373	{".ico", 4, "image/x-icon"},
	1374	{".gif", 4, "image/gif"},
	1375	{".jpg", 4, "image/jpeg"},
	1376	{".jpeg", 5, "image/jpeg"},
	1377	{".png", 4, "image/png"},
	1378	{".svg", 4, "image/svg+xml"},
	1379	{".txt", 4, "text/plain"},
	1380	{".torrent", 8, "application/x-bittorrent"},
	1381	{".wav", 4, "audio/x-wav"},
	1382	{".mp3", 4, "audio/x-mp3"},
	1383	{".mid", 4, "audio/mid"},
	1384	{".m3u", 4, "audio/x-mpegurl"},
	1385	{".ogg", 4, "application/ogg"},
	1386	{".ram", 4, "audio/x-pn-realaudio"},
	1387	{".xml", 4, "text/xml"},
	1388	{".json", 5, "application/json"},
	1389	{".xslt", 5, "application/xml"},
	1390	{".xsl", 4, "application/xml"},
	1391	{".ra", 3, "audio/x-pn-realaudio"},
	1392	{".doc", 4, "application/msword"},
	1393	{".exe", 4, "application/octet-stream"},
	1394	{".zip", 4, "application/x-zip-compressed"},
	1395	{".xls", 4, "application/excel"},
	1396	{".tgz", 4, "application/x-tar-gz"},
	1397	{".tar", 4, "application/x-tar"},
	1398	{".gz", 3, "application/x-gunzip"},
	1399	{".arj", 4, "application/x-arj-compressed"},
	1400	{".rar", 4, "application/x-rar-compressed"},
	1401	{".rtf", 4, "application/rtf"},
	1402	{".pdf", 4, "application/pdf"},
	1403	{".swf", 4, "application/x-shockwave-flash"},
	1404	{".mpg", 4, "video/mpeg"},
	1405	{".webm", 5, "video/webm"},
	1406	{".mpeg", 5, "video/mpeg"},
	1407	{".mov", 4, "video/quicktime"},
	1408	{".mp4", 4, "video/mp4"},
	1409	{".m4v", 4, "video/x-m4v"},
	1410	{".asf", 4, "video/x-ms-asf"},
	1411	{".avi", 4, "video/x-msvideo"},
	1412	{".bmp", 4, "image/bmp"},
	1413	{".ttf", 4, "application/x-font-ttf"},
	1414	{NULL, 0, NULL}
1415	1415	};
1416	1416
1417	1417	#ifndef MONGOOSE_NO_THREADS
1418	1418	void mg_start_thread(void (f)(void ), void *p) {
1419		return ns_start_thread(f, p);
	1419	return ns_start_thread(f, p);
1420	1420	}
1421	1421	#endif // MONGOOSE_NO_THREADS
1422	1422
r32760	r32761
1424	1424	// Encode 'path' which is assumed UTF-8 string, into UNICODE string.
1425	1425	// wbuf and wbuf_len is a target buffer and its length.
1426	1426	static void to_wchar(const char path, wchar_t wbuf, size_t wbuf_len) {
1427		char buf[MAX_PATH_SIZE * 2], buf2[MAX_PATH_SIZE * 2], *p;
	1427	char buf[MAX_PATH_SIZE * 2], buf2[MAX_PATH_SIZE * 2], *p;
1428	1428
1429		strncpy(buf, path, sizeof(buf));
1430		buf[sizeof(buf) - 1] = '\0';
	1429	strncpy(buf, path, sizeof(buf));
	1430	buf[sizeof(buf) - 1] = '\0';
1431	1431
1432		// Trim trailing slashes. Leave backslash for paths like "X:\"
1433		p = buf + strlen(buf) - 1;
1434		while (p > buf && p[-1] != ':' && (p[0] == '\\' \|\| p[0] == '/')) *p-- = '\0';
	1432	// Trim trailing slashes. Leave backslash for paths like "X:\"
	1433	p = buf + strlen(buf) - 1;
	1434	while (p > buf && p[-1] != ':' && (p[0] == '\\' \|\| p[0] == '/')) *p-- = '\0';
1435	1435
1436		// Convert to Unicode and back. If doubly-converted string does not
1437		// match the original, something is fishy, reject.
1438		memset(wbuf, 0, wbuf_len * sizeof(wchar_t));
1439		MultiByteToWideChar(CP_UTF8, 0, buf, -1, wbuf, (int) wbuf_len);
1440		WideCharToMultiByte(CP_UTF8, 0, wbuf, (int) wbuf_len, buf2, sizeof(buf2),
1441		NULL, NULL);
1442		if (strcmp(buf, buf2) != 0) {
1443		wbuf[0] = L'\0';
1444		}
	1436	// Convert to Unicode and back. If doubly-converted string does not
	1437	// match the original, something is fishy, reject.
	1438	memset(wbuf, 0, wbuf_len * sizeof(wchar_t));
	1439	MultiByteToWideChar(CP_UTF8, 0, buf, -1, wbuf, (int) wbuf_len);
	1440	WideCharToMultiByte(CP_UTF8, 0, wbuf, (int) wbuf_len, buf2, sizeof(buf2),
	1441	NULL, NULL);
	1442	if (strcmp(buf, buf2) != 0) {
	1443	wbuf[0] = L'\0';
	1444	}
1445	1445	}
1446	1446
1447	1447	static int mg_stat(const char path, file_stat_t st) {
1448		wchar_t wpath[MAX_PATH_SIZE];
1449		to_wchar(path, wpath, ARRAY_SIZE(wpath));
1450		DBG(("[%ls] -> %d", wpath, _wstati64(wpath, st)));
1451		return _wstati64(wpath, st);
	1448	wchar_t wpath[MAX_PATH_SIZE];
	1449	to_wchar(path, wpath, ARRAY_SIZE(wpath));
	1450	DBG(("[%ls] -> %d", wpath, _wstati64(wpath, st)));
	1451	return _wstati64(wpath, st);
1452	1452	}
1453	1453
1454	1454	static FILE mg_fopen(const char path, const char *mode) {
1455		wchar_t wpath[MAX_PATH_SIZE], wmode[10];
1456		to_wchar(path, wpath, ARRAY_SIZE(wpath));
1457		to_wchar(mode, wmode, ARRAY_SIZE(wmode));
1458		return _wfopen(wpath, wmode);
	1455	wchar_t wpath[MAX_PATH_SIZE], wmode[10];
	1456	to_wchar(path, wpath, ARRAY_SIZE(wpath));
	1457	to_wchar(mode, wmode, ARRAY_SIZE(wmode));
	1458	return _wfopen(wpath, wmode);
1459	1459	}
1460	1460
1461	1461	static int mg_open(const char *path, int flag) {
1462		wchar_t wpath[MAX_PATH_SIZE];
1463		to_wchar(path, wpath, ARRAY_SIZE(wpath));
1464		return _wopen(wpath, flag);
	1462	wchar_t wpath[MAX_PATH_SIZE];
	1463	to_wchar(path, wpath, ARRAY_SIZE(wpath));
	1464	return _wopen(wpath, flag);
1465	1465	}
1466	1466	#endif // _WIN32 && !MONGOOSE_NO_FILESYSTEM
1467	1467
r32760	r32761
1472	1472	// vector is initialized to point to the "y" part, and val vector length
1473	1473	// is adjusted to point only to "x".
1474	1474	static const char next_option(const char list, struct vec *val,
1475		struct vec *eq_val) {
1476		if (list == NULL \|\| *list == '\0') {
1477		// End of the list
1478		list = NULL;
1479		} else {
1480		val->ptr = list;
1481		if ((list = strchr(val->ptr, ',')) != NULL) {
1482		// Comma found. Store length and shift the list ptr
1483		val->len = list - val->ptr;
1484		list++;
1485		} else {
1486		// This value is the last one
1487		list = val->ptr + strlen(val->ptr);
1488		val->len = list - val->ptr;
1489		}
	1475	struct vec *eq_val) {
	1476	if (list == NULL \|\| *list == '\0') {
	1477	// End of the list
	1478	list = NULL;
	1479	} else {
	1480	val->ptr = list;
	1481	if ((list = strchr(val->ptr, ',')) != NULL) {
	1482	// Comma found. Store length and shift the list ptr
	1483	val->len = list - val->ptr;
	1484	list++;
	1485	} else {
	1486	// This value is the last one
	1487	list = val->ptr + strlen(val->ptr);
	1488	val->len = list - val->ptr;
	1489	}
1490	1490
1491		if (eq_val != NULL) {
1492		// Value has form "x=y", adjust pointers and lengths
1493		// so that val points to "x", and eq_val points to "y".
1494		eq_val->len = 0;
1495		eq_val->ptr = (const char *) memchr(val->ptr, '=', val->len);
1496		if (eq_val->ptr != NULL) {
1497		eq_val->ptr++; // Skip over '=' character
1498		eq_val->len = val->ptr + val->len - eq_val->ptr;
1499		val->len = (eq_val->ptr - val->ptr) - 1;
1500		}
1501		}
1502		}
	1491	if (eq_val != NULL) {
	1492	// Value has form "x=y", adjust pointers and lengths
	1493	// so that val points to "x", and eq_val points to "y".
	1494	eq_val->len = 0;
	1495	eq_val->ptr = (const char *) memchr(val->ptr, '=', val->len);
	1496	if (eq_val->ptr != NULL) {
	1497	eq_val->ptr++; // Skip over '=' character
	1498	eq_val->len = val->ptr + val->len - eq_val->ptr;
	1499	val->len = (eq_val->ptr - val->ptr) - 1;
	1500	}
	1501	}
	1502	}
1503	1503
1504		return list;
	1504	return list;
1505	1505	}
1506	1506
1507	1507	// Like snprintf(), but never returns negative value, or a value
1508	1508	// that is larger than a supplied buffer.
1509	1509	static int mg_vsnprintf(char buf, size_t buflen, const char fmt, va_list ap) {
1510		int n;
1511		if (buflen < 1) return 0;
1512		n = vsnprintf(buf, buflen, fmt, ap);
1513		if (n < 0) {
1514		n = 0;
1515		} else if (n >= (int) buflen) {
1516		n = (int) buflen - 1;
1517		}
1518		buf[n] = '\0';
1519		return n;
	1510	int n;
	1511	if (buflen < 1) return 0;
	1512	n = vsnprintf(buf, buflen, fmt, ap);
	1513	if (n < 0) {
	1514	n = 0;
	1515	} else if (n >= (int) buflen) {
	1516	n = (int) buflen - 1;
	1517	}
	1518	buf[n] = '\0';
	1519	return n;
1520	1520	}
1521	1521
1522	1522	static int mg_snprintf(char buf, size_t buflen, const char fmt, ...) {
1523		va_list ap;
1524		int n;
1525		va_start(ap, fmt);
1526		n = mg_vsnprintf(buf, buflen, fmt, ap);
1527		va_end(ap);
1528		return n;
	1523	va_list ap;
	1524	int n;
	1525	va_start(ap, fmt);
	1526	n = mg_vsnprintf(buf, buflen, fmt, ap);
	1527	va_end(ap);
	1528	return n;
1529	1529	}
1530	1530
1531	1531	// Check whether full request is buffered. Return:
r32760	r32761
1533	1533	// 0 if request is not yet fully buffered
1534	1534	// >0 actual request length, including last \r\n\r\n
1535	1535	static int get_request_len(const char *s, int buf_len) {
1536		const unsigned char buf = (unsigned char ) s;
1537		int i;
	1536	const unsigned char buf = (unsigned char ) s;
	1537	int i;
1538	1538
1539		for (i = 0; i < buf_len; i++) {
1540		// Control characters are not allowed but >=128 are.
1541		// Abort scan as soon as one malformed character is found.
1542		if (!isprint(buf[i]) && buf[i] != '\r' && buf[i] != '\n' && buf[i] < 128) {
1543		return -1;
1544		} else if (buf[i] == '\n' && i + 1 < buf_len && buf[i + 1] == '\n') {
1545		return i + 2;
1546		} else if (buf[i] == '\n' && i + 2 < buf_len && buf[i + 1] == '\r' &&
1547		buf[i + 2] == '\n') {
1548		return i + 3;
1549		}
1550		}
	1539	for (i = 0; i < buf_len; i++) {
	1540	// Control characters are not allowed but >=128 are.
	1541	// Abort scan as soon as one malformed character is found.
	1542	if (!isprint(buf[i]) && buf[i] != '\r' && buf[i] != '\n' && buf[i] < 128) {
	1543	return -1;
	1544	} else if (buf[i] == '\n' && i + 1 < buf_len && buf[i + 1] == '\n') {
	1545	return i + 2;
	1546	} else if (buf[i] == '\n' && i + 2 < buf_len && buf[i + 1] == '\r' &&
	1547	buf[i + 2] == '\n') {
	1548	return i + 3;
	1549	}
	1550	}
1551	1551
1552		return 0;
	1552	return 0;
1553	1553	}
1554	1554
1555	1555	// Skip the characters until one of the delimiters characters found.
1556	1556	// 0-terminate resulting word. Skip the rest of the delimiters if any.
1557	1557	// Advance pointer to buffer to the next word. Return found 0-terminated word.
1558	1558	static char skip(char buf, const char delimiters) {
1559		char p, begin_word, end_word, end_delimiters;
	1559	char p, begin_word, end_word, end_delimiters;
1560	1560
1561		begin_word = *buf;
1562		end_word = begin_word + strcspn(begin_word, delimiters);
1563		end_delimiters = end_word + strspn(end_word, delimiters);
	1561	begin_word = *buf;
	1562	end_word = begin_word + strcspn(begin_word, delimiters);
	1563	end_delimiters = end_word + strspn(end_word, delimiters);
1564	1564
1565		for (p = end_word; p < end_delimiters; p++) {
1566		*p = '\0';
1567		}
	1565	for (p = end_word; p < end_delimiters; p++) {
	1566	*p = '\0';
	1567	}
1568	1568
1569		*buf = end_delimiters;
	1569	*buf = end_delimiters;
1570	1570
1571		return begin_word;
	1571	return begin_word;
1572	1572	}
1573	1573
1574	1574	// Parse HTTP headers from the given buffer, advance buffer to the point
1575	1575	// where parsing stopped.
1576	1576	static void parse_http_headers(char *buf, struct mg_connection ri) {
1577		size_t i;
	1577	size_t i;
1578	1578
1579		for (i = 0; i < ARRAY_SIZE(ri->http_headers); i++) {
1580		ri->http_headers[i].name = skip(buf, ": ");
1581		ri->http_headers[i].value = skip(buf, "\r\n");
1582		if (ri->http_headers[i].name[0] == '\0')
1583		break;
1584		ri->num_headers = i + 1;
1585		}
	1579	for (i = 0; i < ARRAY_SIZE(ri->http_headers); i++) {
	1580	ri->http_headers[i].name = skip(buf, ": ");
	1581	ri->http_headers[i].value = skip(buf, "\r\n");
	1582	if (ri->http_headers[i].name[0] == '\0')
	1583	break;
	1584	ri->num_headers = i + 1;
	1585	}
1586	1586	}
1587	1587
1588	1588	static const char *status_code_to_str(int status_code) {
1589		switch (status_code) {
	1589	switch (status_code) {
	1590	case 100: return "Continue";
	1591	case 101: return "Switching Protocols";
	1592	case 102: return "Processing";
1590	1593
1591		case 100: return "Continue";
1592		case 101: return "Switching Protocols";
1593		case 102: return "Processing";
	1594	case 200: return "OK";
	1595	case 201: return "Created";
	1596	case 202: return "Accepted";
	1597	case 203: return "Non-Authoritative Information";
	1598	case 204: return "No Content";
	1599	case 205: return "Reset Content";
	1600	case 206: return "Partial Content";
	1601	case 207: return "Multi-Status";
	1602	case 208: return "Already Reported";
	1603	case 226: return "IM Used";
1594	1604
1595		case 200: return "OK";
1596		case 201: return "Created";
1597		case 202: return "Accepted";
1598		case 203: return "Non-Authoritative Information";
1599		case 204: return "No Content";
1600		case 205: return "Reset Content";
1601		case 206: return "Partial Content";
1602		case 207: return "Multi-Status";
1603		case 208: return "Already Reported";
1604		case 226: return "IM Used";
	1605	case 300: return "Multiple Choices";
	1606	case 301: return "Moved Permanently";
	1607	case 302: return "Found";
	1608	case 303: return "See Other";
	1609	case 304: return "Not Modified";
	1610	case 305: return "Use Proxy";
	1611	case 306: return "Switch Proxy";
	1612	case 307: return "Temporary Redirect";
	1613	case 308: return "Permanent Redirect";
1605	1614
1606		case 300: return "Multiple Choices";
1607		case 301: return "Moved Permanently";
1608		case 302: return "Found";
1609		case 303: return "See Other";
1610		case 304: return "Not Modified";
1611		case 305: return "Use Proxy";
1612		case 306: return "Switch Proxy";
1613		case 307: return "Temporary Redirect";
1614		case 308: return "Permanent Redirect";
	1615	case 400: return "Bad Request";
	1616	case 401: return "Unauthorized";
	1617	case 402: return "Payment Required";
	1618	case 403: return "Forbidden";
	1619	case 404: return "Not Found";
	1620	case 405: return "Method Not Allowed";
	1621	case 406: return "Not Acceptable";
	1622	case 407: return "Proxy Authentication Required";
	1623	case 408: return "Request Timeout";
	1624	case 409: return "Conflict";
	1625	case 410: return "Gone";
	1626	case 411: return "Length Required";
	1627	case 412: return "Precondition Failed";
	1628	case 413: return "Payload Too Large";
	1629	case 414: return "URI Too Long";
	1630	case 415: return "Unsupported Media Type";
	1631	case 416: return "Requested Range Not Satisfiable";
	1632	case 417: return "Expectation Failed";
	1633	case 418: return "I\'m a teapot";
	1634	case 422: return "Unprocessable Entity";
	1635	case 423: return "Locked";
	1636	case 424: return "Failed Dependency";
	1637	case 426: return "Upgrade Required";
	1638	case 428: return "Precondition Required";
	1639	case 429: return "Too Many Requests";
	1640	case 431: return "Request Header Fields Too Large";
	1641	case 451: return "Unavailable For Legal Reasons";
1615	1642
1616		case 400: return "Bad Request";
1617		case 401: return "Unauthorized";
1618		case 402: return "Payment Required";
1619		case 403: return "Forbidden";
1620		case 404: return "Not Found";
1621		case 405: return "Method Not Allowed";
1622		case 406: return "Not Acceptable";
1623		case 407: return "Proxy Authentication Required";
1624		case 408: return "Request Timeout";
1625		case 409: return "Conflict";
1626		case 410: return "Gone";
1627		case 411: return "Length Required";
1628		case 412: return "Precondition Failed";
1629		case 413: return "Payload Too Large";
1630		case 414: return "URI Too Long";
1631		case 415: return "Unsupported Media Type";
1632		case 416: return "Requested Range Not Satisfiable";
1633		case 417: return "Expectation Failed";
1634		case 418: return "I\'m a teapot";
1635		case 422: return "Unprocessable Entity";
1636		case 423: return "Locked";
1637		case 424: return "Failed Dependency";
1638		case 426: return "Upgrade Required";
1639		case 428: return "Precondition Required";
1640		case 429: return "Too Many Requests";
1641		case 431: return "Request Header Fields Too Large";
1642		case 451: return "Unavailable For Legal Reasons";
	1643	case 500: return "Internal Server Error";
	1644	case 501: return "Not Implemented";
	1645	case 502: return "Bad Gateway";
	1646	case 503: return "Service Unavailable";
	1647	case 504: return "Gateway Timeout";
	1648	case 505: return "HTTP Version Not Supported";
	1649	case 506: return "Variant Also Negotiates";
	1650	case 507: return "Insufficient Storage";
	1651	case 508: return "Loop Detected";
	1652	case 510: return "Not Extended";
	1653	case 511: return "Network Authentication Required";
1643	1654
1644		case 500: return "Internal Server Error";
1645		case 501: return "Not Implemented";
1646		case 502: return "Bad Gateway";
1647		case 503: return "Service Unavailable";
1648		case 504: return "Gateway Timeout";
1649		case 505: return "HTTP Version Not Supported";
1650		case 506: return "Variant Also Negotiates";
1651		case 507: return "Insufficient Storage";
1652		case 508: return "Loop Detected";
1653		case 510: return "Not Extended";
1654		case 511: return "Network Authentication Required";
1655
1656		default: return "Server Error";
1657		}
	1655	default: return "Server Error";
	1656	}
1658	1657	}
1659	1658
1660	1659	static int call_user(struct connection *conn, enum mg_event ev) {
1661		return conn != NULL && conn->server != NULL &&
1662		conn->server->event_handler != NULL ?
1663		conn->server->event_handler(&conn->mg_conn, ev) : MG_FALSE;
	1660	return conn != NULL && conn->server != NULL &&
	1661	conn->server->event_handler != NULL ?
	1662	conn->server->event_handler(&conn->mg_conn, ev) : MG_FALSE;
1664	1663	}
1665	1664
1666	1665	static void send_http_error(struct connection *conn, int code,
1667		const char *fmt, ...) {
1668		const char *message = status_code_to_str(code);
1669		const char *rewrites = conn->server->config_options[URL_REWRITES];
1670		char headers[200], body[200];
1671		struct vec a, b;
1672		va_list ap;
1673		int body_len, headers_len, match_code;
	1666	const char *fmt, ...) {
	1667	const char *message = status_code_to_str(code);
	1668	const char *rewrites = conn->server->config_options[URL_REWRITES];
	1669	char headers[200], body[200];
	1670	struct vec a, b;
	1671	va_list ap;
	1672	int body_len, headers_len, match_code;
1674	1673
1675		conn->mg_conn.status_code = code;
	1674	conn->mg_conn.status_code = code;
1676	1675
1677		// Invoke error handler if it is set
1678		if (call_user(conn, MG_HTTP_ERROR) == MG_TRUE) {
1679		close_local_endpoint(conn);
1680		return;
1681		}
	1676	// Invoke error handler if it is set
	1677	if (call_user(conn, MG_HTTP_ERROR) == MG_TRUE) {
	1678	close_local_endpoint(conn);
	1679	return;
	1680	}
1682	1681
1683		// Handle error code rewrites
1684		while ((rewrites = next_option(rewrites, &a, &b)) != NULL) {
1685		if ((match_code = atoi(a.ptr)) > 0 && match_code == code) {
1686		struct mg_connection *c = &conn->mg_conn;
1687		c->status_code = 302;
1688		mg_printf(c, "HTTP/1.1 %d Moved\r\n"
1689		"Location: %.*s?code=%d&orig_uri=%s&query_string=%s\r\n\r\n",
1690		c->status_code, b.len, b.ptr, code, c->uri,
1691		c->query_string == NULL ? "" : c->query_string);
1692		close_local_endpoint(conn);
1693		return;
1694		}
1695		}
	1682	// Handle error code rewrites
	1683	while ((rewrites = next_option(rewrites, &a, &b)) != NULL) {
	1684	if ((match_code = atoi(a.ptr)) > 0 && match_code == code) {
	1685	struct mg_connection *c = &conn->mg_conn;
	1686	c->status_code = 302;
	1687	mg_printf(c, "HTTP/1.1 %d Moved\r\n"
	1688	"Location: %.*s?code=%d&orig_uri=%s&query_string=%s\r\n\r\n",
	1689	c->status_code, b.len, b.ptr, code, c->uri,
	1690	c->query_string == NULL ? "" : c->query_string);
	1691	close_local_endpoint(conn);
	1692	return;
	1693	}
	1694	}
1696	1695
1697		body_len = mg_snprintf(body, sizeof(body), "%d %s\n", code, message);
1698		if (fmt != NULL) {
1699		va_start(ap, fmt);
1700		body_len += mg_vsnprintf(body + body_len, sizeof(body) - body_len, fmt, ap);
1701		va_end(ap);
1702		}
1703		if ((code >= 300 && code <= 399) \|\| code == 204) {
1704		// 3xx errors do not have body
1705		body_len = 0;
1706		}
1707		headers_len = mg_snprintf(headers, sizeof(headers),
1708		"HTTP/1.1 %d %s\r\nContent-Length: %d\r\n"
1709		"Content-Type: text/plain\r\n\r\n",
1710		code, message, body_len);
1711		ns_send(conn->ns_conn, headers, headers_len);
1712		ns_send(conn->ns_conn, body, body_len);
1713		close_local_endpoint(conn); // This will write to the log file
	1696	body_len = mg_snprintf(body, sizeof(body), "%d %s\n", code, message);
	1697	if (fmt != NULL) {
	1698	va_start(ap, fmt);
	1699	body_len += mg_vsnprintf(body + body_len, sizeof(body) - body_len, fmt, ap);
	1700	va_end(ap);
	1701	}
	1702	if ((code >= 300 && code <= 399) \|\| code == 204) {
	1703	// 3xx errors do not have body
	1704	body_len = 0;
	1705	}
	1706	headers_len = mg_snprintf(headers, sizeof(headers),
	1707	"HTTP/1.1 %d %s\r\nContent-Length: %d\r\n"
	1708	"Content-Type: text/plain\r\n\r\n",
	1709	code, message, body_len);
	1710	ns_send(conn->ns_conn, headers, headers_len);
	1711	ns_send(conn->ns_conn, body, body_len);
	1712	close_local_endpoint(conn); // This will write to the log file
1714	1713	}
1715	1714
1716	1715	static void write_chunk(struct connection conn, const char buf, int len) {
1717		char chunk_size[50];
1718		int n = mg_snprintf(chunk_size, sizeof(chunk_size), "%X\r\n", len);
1719		ns_send(conn->ns_conn, chunk_size, n);
1720		ns_send(conn->ns_conn, buf, len);
1721		ns_send(conn->ns_conn, "\r\n", 2);
	1716	char chunk_size[50];
	1717	int n = mg_snprintf(chunk_size, sizeof(chunk_size), "%X\r\n", len);
	1718	ns_send(conn->ns_conn, chunk_size, n);
	1719	ns_send(conn->ns_conn, buf, len);
	1720	ns_send(conn->ns_conn, "\r\n", 2);
1722	1721	}
1723	1722
1724	1723	size_t mg_printf(struct mg_connection conn, const char fmt, ...) {
1725		struct connection *c = MG_CONN_2_CONN(conn);
1726		va_list ap;
	1724	struct connection *c = MG_CONN_2_CONN(conn);
	1725	va_list ap;
1727	1726
1728		va_start(ap, fmt);
1729		ns_vprintf(c->ns_conn, fmt, ap);
1730		va_end(ap);
	1727	va_start(ap, fmt);
	1728	ns_vprintf(c->ns_conn, fmt, ap);
	1729	va_end(ap);
1731	1730
1732		return c->ns_conn->send_iobuf.len;
	1731	return c->ns_conn->send_iobuf.len;
1733	1732	}
1734	1733
1735	1734	static void ns_forward(struct ns_connection from, struct ns_connection to) {
1736		DBG(("%p -> %p %lu bytes", from, to, (unsigned long)from->recv_iobuf.len));
1737		ns_send(to, from->recv_iobuf.buf, from->recv_iobuf.len);
1738		iobuf_remove(&from->recv_iobuf, from->recv_iobuf.len);
	1735	DBG(("%p -> %p %lu bytes", from, to, (unsigned long)from->recv_iobuf.len));
	1736	ns_send(to, from->recv_iobuf.buf, from->recv_iobuf.len);
	1737	iobuf_remove(&from->recv_iobuf, from->recv_iobuf.len);
1739	1738	}
1740	1739
1741	1740	#ifndef MONGOOSE_NO_CGI
1742	1741	#ifdef _WIN32
1743	1742	struct threadparam {
1744		sock_t s;
1745		HANDLE hPipe;
	1743	sock_t s;
	1744	HANDLE hPipe;
1746	1745	};
1747	1746
1748	1747	static int wait_until_ready(sock_t sock, int for_read) {
1749		fd_set set;
1750		FD_ZERO(&set);
1751		FD_SET(sock, &set);
1752		select(sock + 1, for_read ? &set : 0, for_read ? 0 : &set, 0, 0);
1753		return 1;
	1748	fd_set set;
	1749	FD_ZERO(&set);
	1750	FD_SET(sock, &set);
	1751	select(sock + 1, for_read ? &set : 0, for_read ? 0 : &set, 0, 0);
	1752	return 1;
1754	1753	}
1755	1754
1756	1755	static void push_to_stdin(void arg) {
1757		struct threadparam tp = (struct threadparam )arg;
1758		int n, sent, stop = 0;
1759		DWORD k;
1760		char buf[IOBUF_SIZE];
	1756	struct threadparam tp = (struct threadparam )arg;
	1757	int n, sent, stop = 0;
	1758	DWORD k;
	1759	char buf[IOBUF_SIZE];
1761	1760
1762		while (!stop && wait_until_ready(tp->s, 1) &&
1763		(n = recv(tp->s, buf, sizeof(buf), 0)) > 0) {
1764		if (n == -1 && GetLastError() == WSAEWOULDBLOCK) continue;
1765		for (sent = 0; !stop && sent < n; sent += k) {
1766		if (!WriteFile(tp->hPipe, buf + sent, n - sent, &k, 0)) stop = 1;
1767		}
1768		}
1769		DBG(("%s", "FORWARED EVERYTHING TO CGI"));
1770		CloseHandle(tp->hPipe);
1771		free(tp);
1772		_endthread();
1773		return NULL;
	1761	while (!stop && wait_until_ready(tp->s, 1) &&
	1762	(n = recv(tp->s, buf, sizeof(buf), 0)) > 0) {
	1763	if (n == -1 && GetLastError() == WSAEWOULDBLOCK) continue;
	1764	for (sent = 0; !stop && sent < n; sent += k) {
	1765	if (!WriteFile(tp->hPipe, buf + sent, n - sent, &k, 0)) stop = 1;
	1766	}
	1767	}
	1768	DBG(("%s", "FORWARED EVERYTHING TO CGI"));
	1769	CloseHandle(tp->hPipe);
	1770	free(tp);
	1771	_endthread();
	1772	return NULL;
1774	1773	}
1775	1774
1776	1775	static void pull_from_stdout(void arg) {
1777		struct threadparam tp = (struct threadparam )arg;
1778		int k = 0, stop = 0;
1779		DWORD n, sent;
1780		char buf[IOBUF_SIZE];
	1776	struct threadparam tp = (struct threadparam )arg;
	1777	int k = 0, stop = 0;
	1778	DWORD n, sent;
	1779	char buf[IOBUF_SIZE];
1781	1780
1782		while (!stop && ReadFile(tp->hPipe, buf, sizeof(buf), &n, NULL)) {
1783		for (sent = 0; !stop && sent < n; sent += k) {
1784		if (wait_until_ready(tp->s, 0) &&
1785		(k = send(tp->s, buf + sent, n - sent, 0)) <= 0) stop = 1;
1786		}
1787		}
1788		DBG(("%s", "EOF FROM CGI"));
1789		CloseHandle(tp->hPipe);
1790		shutdown(tp->s, 2); // Without this, IO thread may get truncated data
1791		closesocket(tp->s);
1792		free(tp);
1793		_endthread();
1794		return NULL;
	1781	while (!stop && ReadFile(tp->hPipe, buf, sizeof(buf), &n, NULL)) {
	1782	for (sent = 0; !stop && sent < n; sent += k) {
	1783	if (wait_until_ready(tp->s, 0) &&
	1784	(k = send(tp->s, buf + sent, n - sent, 0)) <= 0) stop = 1;
	1785	}
	1786	}
	1787	DBG(("%s", "EOF FROM CGI"));
	1788	CloseHandle(tp->hPipe);
	1789	shutdown(tp->s, 2); // Without this, IO thread may get truncated data
	1790	closesocket(tp->s);
	1791	free(tp);
	1792	_endthread();
	1793	return NULL;
1795	1794	}
1796	1795
1797	1796	static void spawn_stdio_thread(sock_t sock, HANDLE hPipe,
1798		void (func)(void *)) {
1799		struct threadparam tp = (struct threadparam )malloc(sizeof(*tp));
1800		if (tp != NULL) {
1801		tp->s = sock;
1802		tp->hPipe = hPipe;
1803		mg_start_thread(func, tp);
1804		}
	1797	void (func)(void *)) {
	1798	struct threadparam tp = (struct threadparam )malloc(sizeof(*tp));
	1799	if (tp != NULL) {
	1800	tp->s = sock;
	1801	tp->hPipe = hPipe;
	1802	mg_start_thread(func, tp);
	1803	}
1805	1804	}
1806	1805
1807	1806	static void abs_path(const char utf8_path, char abs_path, size_t len) {
1808		wchar_t buf[MAX_PATH_SIZE], buf2[MAX_PATH_SIZE];
1809		to_wchar(utf8_path, buf, ARRAY_SIZE(buf));
1810		GetFullPathNameW(buf, ARRAY_SIZE(buf2), buf2, NULL);
1811		WideCharToMultiByte(CP_UTF8, 0, buf2, wcslen(buf2) + 1, abs_path, len, 0, 0);
	1807	wchar_t buf[MAX_PATH_SIZE], buf2[MAX_PATH_SIZE];
	1808	to_wchar(utf8_path, buf, ARRAY_SIZE(buf));
	1809	GetFullPathNameW(buf, ARRAY_SIZE(buf2), buf2, NULL);
	1810	WideCharToMultiByte(CP_UTF8, 0, buf2, wcslen(buf2) + 1, abs_path, len, 0, 0);
1812	1811	}
1813	1812
1814	1813	static process_id_t start_process(char interp, const char cmd,
1815		const char env, const char envp[],
1816		const char *dir, sock_t sock) {
1817		STARTUPINFOW si;
1818		PROCESS_INFORMATION pi;
1819		HANDLE a[2], b[2], me = GetCurrentProcess();
1820		wchar_t wcmd[MAX_PATH_SIZE], full_dir[MAX_PATH_SIZE];
1821		char buf[MAX_PATH_SIZE], buf4[MAX_PATH_SIZE], buf5[MAX_PATH_SIZE],
1822		cmdline[MAX_PATH_SIZE], *p;
1823		DWORD flags = DUPLICATE_CLOSE_SOURCE \| DUPLICATE_SAME_ACCESS;
1824		FILE *fp;
	1814	const char env, const char envp[],
	1815	const char *dir, sock_t sock) {
	1816	STARTUPINFOW si;
	1817	PROCESS_INFORMATION pi;
	1818	HANDLE a[2], b[2], me = GetCurrentProcess();
	1819	wchar_t wcmd[MAX_PATH_SIZE], full_dir[MAX_PATH_SIZE];
	1820	char buf[MAX_PATH_SIZE], buf4[MAX_PATH_SIZE], buf5[MAX_PATH_SIZE],
	1821	cmdline[MAX_PATH_SIZE], *p;
	1822	DWORD flags = DUPLICATE_CLOSE_SOURCE \| DUPLICATE_SAME_ACCESS;
	1823	FILE *fp;
1825	1824
1826		memset(&si, 0, sizeof(si));
1827		memset(&pi, 0, sizeof(pi));
	1825	memset(&si, 0, sizeof(si));
	1826	memset(&pi, 0, sizeof(pi));
1828	1827
1829		si.cb = sizeof(si);
1830		si.dwFlags = STARTF_USESTDHANDLES \| STARTF_USESHOWWINDOW;
1831		si.wShowWindow = SW_HIDE;
1832		si.hStdError = GetStdHandle(STD_ERROR_HANDLE);
	1828	si.cb = sizeof(si);
	1829	si.dwFlags = STARTF_USESTDHANDLES \| STARTF_USESHOWWINDOW;
	1830	si.wShowWindow = SW_HIDE;
	1831	si.hStdError = GetStdHandle(STD_ERROR_HANDLE);
1833	1832
1834		CreatePipe(&a[0], &a[1], NULL, 0);
1835		CreatePipe(&b[0], &b[1], NULL, 0);
1836		DuplicateHandle(me, a[0], me, &si.hStdInput, 0, TRUE, flags);
1837		DuplicateHandle(me, b[1], me, &si.hStdOutput, 0, TRUE, flags);
	1833	CreatePipe(&a[0], &a[1], NULL, 0);
	1834	CreatePipe(&b[0], &b[1], NULL, 0);
	1835	DuplicateHandle(me, a[0], me, &si.hStdInput, 0, TRUE, flags);
	1836	DuplicateHandle(me, b[1], me, &si.hStdOutput, 0, TRUE, flags);
1838	1837
1839		if (interp == NULL && (fp = fopen(cmd, "r")) != NULL) {
1840		buf[0] = buf[1] = '\0';
1841		fgets(buf, sizeof(buf), fp);
1842		buf[sizeof(buf) - 1] = '\0';
1843		if (buf[0] == '#' && buf[1] == '!') {
1844		interp = buf + 2;
1845		for (p = interp + strlen(interp);
1846		isspace(* (uint8_t ) p) && p > interp; p--) p = '\0';
1847		}
1848		fclose(fp);
1849		}
	1838	if (interp == NULL && (fp = fopen(cmd, "r")) != NULL) {
	1839	buf[0] = buf[1] = '\0';
	1840	fgets(buf, sizeof(buf), fp);
	1841	buf[sizeof(buf) - 1] = '\0';
	1842	if (buf[0] == '#' && buf[1] == '!') {
	1843	interp = buf + 2;
	1844	for (p = interp + strlen(interp);
	1845	isspace(* (uint8_t ) p) && p > interp; p--) p = '\0';
	1846	}
	1847	fclose(fp);
	1848	}
1850	1849
1851		if (interp != NULL) {
1852		abs_path(interp, buf4, ARRAY_SIZE(buf4));
1853		interp = buf4;
1854		}
1855		abs_path(dir, buf5, ARRAY_SIZE(buf5));
1856		to_wchar(dir, full_dir, ARRAY_SIZE(full_dir));
1857		mg_snprintf(cmdline, sizeof(cmdline), "%s%s\"%s\"",
1858		interp ? interp : "", interp ? " " : "", cmd);
1859		to_wchar(cmdline, wcmd, ARRAY_SIZE(wcmd));
	1850	if (interp != NULL) {
	1851	abs_path(interp, buf4, ARRAY_SIZE(buf4));
	1852	interp = buf4;
	1853	}
	1854	abs_path(dir, buf5, ARRAY_SIZE(buf5));
	1855	to_wchar(dir, full_dir, ARRAY_SIZE(full_dir));
	1856	mg_snprintf(cmdline, sizeof(cmdline), "%s%s\"%s\"",
	1857	interp ? interp : "", interp ? " " : "", cmd);
	1858	to_wchar(cmdline, wcmd, ARRAY_SIZE(wcmd));
1860	1859
1861		if (CreateProcessW(NULL, wcmd, NULL, NULL, TRUE, CREATE_NEW_PROCESS_GROUP,
1862		(void *) env, full_dir, &si, &pi) != 0) {
1863		spawn_stdio_thread(sock, a[1], push_to_stdin);
1864		spawn_stdio_thread(sock, b[0], pull_from_stdout);
1865		} else {
1866		CloseHandle(a[1]);
1867		CloseHandle(b[0]);
1868		closesocket(sock);
1869		}
1870		DBG(("CGI command: [%ls] -> %p", wcmd, pi.hProcess));
	1860	if (CreateProcessW(NULL, wcmd, NULL, NULL, TRUE, CREATE_NEW_PROCESS_GROUP,
	1861	(void *) env, full_dir, &si, &pi) != 0) {
	1862	spawn_stdio_thread(sock, a[1], push_to_stdin);
	1863	spawn_stdio_thread(sock, b[0], pull_from_stdout);
	1864	} else {
	1865	CloseHandle(a[1]);
	1866	CloseHandle(b[0]);
	1867	closesocket(sock);
	1868	}
	1869	DBG(("CGI command: [%ls] -> %p", wcmd, pi.hProcess));
1871	1870
1872		// Not closing a[0] and b[1] because we've used DUPLICATE_CLOSE_SOURCE
1873		CloseHandle(si.hStdOutput);
1874		CloseHandle(si.hStdInput);
1875		//CloseHandle(pi.hThread);
1876		//CloseHandle(pi.hProcess);
	1871	// Not closing a[0] and b[1] because we've used DUPLICATE_CLOSE_SOURCE
	1872	CloseHandle(si.hStdOutput);
	1873	CloseHandle(si.hStdInput);
	1874	//CloseHandle(pi.hThread);
	1875	//CloseHandle(pi.hProcess);
1877	1876
1878		return pi.hProcess;
	1877	return pi.hProcess;
1879	1878	}
1880	1879	#else
1881	1880	static process_id_t start_process(const char interp, const char cmd,
1882		const char env, const char envp[],
1883		const char *dir, sock_t sock) {
1884		char buf[500];
1885		process_id_t pid = fork();
1886		(void) env;
	1881	const char env, const char envp[],
	1882	const char *dir, sock_t sock) {
	1883	char buf[500];
	1884	process_id_t pid = fork();
	1885	(void) env;
1887	1886
1888		if (pid == 0) {
1889		(void) chdir(dir);
1890		(void) dup2(sock, 0);
1891		(void) dup2(sock, 1);
1892		closesocket(sock);
	1887	if (pid == 0) {
	1888	(void) chdir(dir);
	1889	(void) dup2(sock, 0);
	1890	(void) dup2(sock, 1);
	1891	closesocket(sock);
1893	1892
1894		// After exec, all signal handlers are restored to their default values,
1895		// with one exception of SIGCHLD. According to POSIX.1-2001 and Linux's
1896		// implementation, SIGCHLD's handler will leave unchanged after exec
1897		// if it was set to be ignored. Restore it to default action.
1898		signal(SIGCHLD, SIG_DFL);
	1893	// After exec, all signal handlers are restored to their default values,
	1894	// with one exception of SIGCHLD. According to POSIX.1-2001 and Linux's
	1895	// implementation, SIGCHLD's handler will leave unchanged after exec
	1896	// if it was set to be ignored. Restore it to default action.
	1897	signal(SIGCHLD, SIG_DFL);
1899	1898
1900		if (interp == NULL) {
1901		execle(cmd, cmd, (char ) 0, envp); // Using (char ) 0 to avoid warning
1902		} else {
1903		execle(interp, interp, cmd, (char *) 0, envp);
1904		}
1905		snprintf(buf, sizeof(buf), "Status: 500\r\n\r\n"
1906		"500 Server Error: %s%s%s: %s", interp == NULL ? "" : interp,
1907		interp == NULL ? "" : " ", cmd, strerror(errno));
1908		send(1, buf, strlen(buf), 0);
1909		exit(EXIT_FAILURE); // exec call failed
1910		}
	1899	if (interp == NULL) {
	1900	execle(cmd, cmd, (char ) 0, envp); // Using (char ) 0 to avoid warning
	1901	} else {
	1902	execle(interp, interp, cmd, (char *) 0, envp);
	1903	}
	1904	snprintf(buf, sizeof(buf), "Status: 500\r\n\r\n"
	1905	"500 Server Error: %s%s%s: %s", interp == NULL ? "" : interp,
	1906	interp == NULL ? "" : " ", cmd, strerror(errno));
	1907	send(1, buf, strlen(buf), 0);
	1908	exit(EXIT_FAILURE); // exec call failed
	1909	}
1911	1910
1912		return pid;
	1911	return pid;
1913	1912	}
1914	1913	#endif // _WIN32
1915	1914
r32760	r32761
1922	1921	// We satisfy both worlds: we create an envp array (which is vars), all
1923	1922	// entries are actually pointers inside buf.
1924	1923	struct cgi_env_block {
1925		struct mg_connection *conn;
1926		char buf[CGI_ENVIRONMENT_SIZE]; // Environment buffer
1927		const char vars[MAX_CGI_ENVIR_VARS]; // char envp[]
1928		int len; // Space taken
1929		int nvars; // Number of variables in envp[]
	1924	struct mg_connection *conn;
	1925	char buf[CGI_ENVIRONMENT_SIZE]; // Environment buffer
	1926	const char vars[MAX_CGI_ENVIR_VARS]; // char envp[]
	1927	int len; // Space taken
	1928	int nvars; // Number of variables in envp[]
1930	1929	};
1931	1930
1932	1931	// Append VARIABLE=VALUE\0 string to the buffer, and add a respective
1933	1932	// pointer into the vars array.
1934	1933	static char addenv(struct cgi_env_block block, const char *fmt, ...) {
1935		int n, space;
1936		char *added;
1937		va_list ap;
	1934	int n, space;
	1935	char *added;
	1936	va_list ap;
1938	1937
1939		// Calculate how much space is left in the buffer
1940		space = sizeof(block->buf) - block->len - 2;
1941		assert(space >= 0);
	1938	// Calculate how much space is left in the buffer
	1939	space = sizeof(block->buf) - block->len - 2;
	1940	assert(space >= 0);
1942	1941
1943		// Make a pointer to the free space int the buffer
1944		added = block->buf + block->len;
	1942	// Make a pointer to the free space int the buffer
	1943	added = block->buf + block->len;
1945	1944
1946		// Copy VARIABLE=VALUE\0 string into the free space
1947		va_start(ap, fmt);
1948		n = mg_vsnprintf(added, (size_t) space, fmt, ap);
1949		va_end(ap);
	1945	// Copy VARIABLE=VALUE\0 string into the free space
	1946	va_start(ap, fmt);
	1947	n = mg_vsnprintf(added, (size_t) space, fmt, ap);
	1948	va_end(ap);
1950	1949
1951		// Make sure we do not overflow buffer and the envp array
1952		if (n > 0 && n + 1 < space &&
1953		block->nvars < (int) ARRAY_SIZE(block->vars) - 2) {
1954		// Append a pointer to the added string into the envp array
1955		block->vars[block->nvars++] = added;
1956		// Bump up used length counter. Include \0 terminator
1957		block->len += n + 1;
1958		}
	1950	// Make sure we do not overflow buffer and the envp array
	1951	if (n > 0 && n + 1 < space &&
	1952	block->nvars < (int) ARRAY_SIZE(block->vars) - 2) {
	1953	// Append a pointer to the added string into the envp array
	1954	block->vars[block->nvars++] = added;
	1955	// Bump up used length counter. Include \0 terminator
	1956	block->len += n + 1;
	1957	}
1959	1958
1960		return added;
	1959	return added;
1961	1960	}
1962	1961
1963	1962	static void addenv2(struct cgi_env_block blk, const char name) {
1964		const char *s;
1965		if ((s = getenv(name)) != NULL) addenv(blk, "%s=%s", name, s);
	1963	const char *s;
	1964	if ((s = getenv(name)) != NULL) addenv(blk, "%s=%s", name, s);
1966	1965	}
1967	1966
1968	1967	static void prepare_cgi_environment(struct connection *conn,
1969		const char *prog,
1970		struct cgi_env_block *blk) {
1971		struct mg_connection *ri = &conn->mg_conn;
1972		const char s, slash;
1973		char p, *opts = conn->server->config_options;
1974		int i;
	1968	const char *prog,
	1969	struct cgi_env_block *blk) {
	1970	struct mg_connection *ri = &conn->mg_conn;
	1971	const char s, slash;
	1972	char p, *opts = conn->server->config_options;
	1973	int i;
1975	1974
1976		blk->len = blk->nvars = 0;
1977		blk->conn = ri;
	1975	blk->len = blk->nvars = 0;
	1976	blk->conn = ri;
1978	1977
1979		if ((s = getenv("SERVER_NAME")) != NULL) {
1980		addenv(blk, "SERVER_NAME=%s", s);
1981		} else {
1982		addenv(blk, "SERVER_NAME=%s", ri->local_ip);
1983		}
1984		addenv(blk, "SERVER_ROOT=%s", opts[DOCUMENT_ROOT]);
1985		addenv(blk, "DOCUMENT_ROOT=%s", opts[DOCUMENT_ROOT]);
1986		addenv(blk, "SERVER_SOFTWARE=%s/%s", "Mongoose", MONGOOSE_VERSION);
	1978	if ((s = getenv("SERVER_NAME")) != NULL) {
	1979	addenv(blk, "SERVER_NAME=%s", s);
	1980	} else {
	1981	addenv(blk, "SERVER_NAME=%s", ri->local_ip);
	1982	}
	1983	addenv(blk, "SERVER_ROOT=%s", opts[DOCUMENT_ROOT]);
	1984	addenv(blk, "DOCUMENT_ROOT=%s", opts[DOCUMENT_ROOT]);
	1985	addenv(blk, "SERVER_SOFTWARE=%s/%s", "Mongoose", MONGOOSE_VERSION);
1987	1986
1988		// Prepare the environment block
1989		addenv(blk, "%s", "GATEWAY_INTERFACE=CGI/1.1");
1990		addenv(blk, "%s", "SERVER_PROTOCOL=HTTP/1.1");
1991		addenv(blk, "%s", "REDIRECT_STATUS=200"); // For PHP
	1987	// Prepare the environment block
	1988	addenv(blk, "%s", "GATEWAY_INTERFACE=CGI/1.1");
	1989	addenv(blk, "%s", "SERVER_PROTOCOL=HTTP/1.1");
	1990	addenv(blk, "%s", "REDIRECT_STATUS=200"); // For PHP
1992	1991
1993		// TODO(lsm): fix this for IPv6 case
1994		//addenv(blk, "SERVER_PORT=%d", ri->remote_port);
	1992	// TODO(lsm): fix this for IPv6 case
	1993	//addenv(blk, "SERVER_PORT=%d", ri->remote_port);
1995	1994
1996		addenv(blk, "REQUEST_METHOD=%s", ri->request_method);
1997		addenv(blk, "REMOTE_ADDR=%s", ri->remote_ip);
1998		addenv(blk, "REMOTE_PORT=%d", ri->remote_port);
1999		addenv(blk, "REQUEST_URI=%s%s%s", ri->uri,
2000		ri->query_string == NULL ? "" : "?",
2001		ri->query_string == NULL ? "" : ri->query_string);
	1995	addenv(blk, "REQUEST_METHOD=%s", ri->request_method);
	1996	addenv(blk, "REMOTE_ADDR=%s", ri->remote_ip);
	1997	addenv(blk, "REMOTE_PORT=%d", ri->remote_port);
	1998	addenv(blk, "REQUEST_URI=%s%s%s", ri->uri,
	1999	ri->query_string == NULL ? "" : "?",
	2000	ri->query_string == NULL ? "" : ri->query_string);
2002	2001
2003		// SCRIPT_NAME
2004		if (conn->path_info != NULL) {
2005		addenv(blk, "SCRIPT_NAME=%.*s",
2006		(int) (strlen(ri->uri) - strlen(conn->path_info)), ri->uri);
2007		addenv(blk, "PATH_INFO=%s", conn->path_info);
2008		} else {
2009		s = strrchr(prog, '/');
2010		slash = strrchr(ri->uri, '/');
2011		addenv(blk, "SCRIPT_NAME=%.*s%s",
2012		slash == NULL ? 0 : (int) (slash - ri->uri), ri->uri,
2013		s == NULL ? prog : s);
2014		}
	2002	// SCRIPT_NAME
	2003	if (conn->path_info != NULL) {
	2004	addenv(blk, "SCRIPT_NAME=%.*s",
	2005	(int) (strlen(ri->uri) - strlen(conn->path_info)), ri->uri);
	2006	addenv(blk, "PATH_INFO=%s", conn->path_info);
	2007	} else {
	2008	s = strrchr(prog, '/');
	2009	slash = strrchr(ri->uri, '/');
	2010	addenv(blk, "SCRIPT_NAME=%.*s%s",
	2011	slash == NULL ? 0 : (int) (slash - ri->uri), ri->uri,
	2012	s == NULL ? prog : s);
	2013	}
2015	2014
2016		addenv(blk, "SCRIPT_FILENAME=%s", prog);
2017		addenv(blk, "PATH_TRANSLATED=%s", prog);
2018		addenv(blk, "HTTPS=%s", conn->ns_conn->ssl != NULL ? "on" : "off");
	2015	addenv(blk, "SCRIPT_FILENAME=%s", prog);
	2016	addenv(blk, "PATH_TRANSLATED=%s", prog);
	2017	addenv(blk, "HTTPS=%s", conn->ns_conn->ssl != NULL ? "on" : "off");
2019	2018
2020		if ((s = mg_get_header(ri, "Content-Type")) != NULL)
2021		addenv(blk, "CONTENT_TYPE=%s", s);
	2019	if ((s = mg_get_header(ri, "Content-Type")) != NULL)
	2020	addenv(blk, "CONTENT_TYPE=%s", s);
2022	2021
2023		if (ri->query_string != NULL)
2024		addenv(blk, "QUERY_STRING=%s", ri->query_string);
	2022	if (ri->query_string != NULL)
	2023	addenv(blk, "QUERY_STRING=%s", ri->query_string);
2025	2024
2026		if ((s = mg_get_header(ri, "Content-Length")) != NULL)
2027		addenv(blk, "CONTENT_LENGTH=%s", s);
	2025	if ((s = mg_get_header(ri, "Content-Length")) != NULL)
	2026	addenv(blk, "CONTENT_LENGTH=%s", s);
2028	2027
2029		addenv2(blk, "PATH");
2030		addenv2(blk, "TMP");
2031		addenv2(blk, "TEMP");
2032		addenv2(blk, "TMPDIR");
2033		addenv2(blk, "PERLLIB");
2034		addenv2(blk, ENV_EXPORT_TO_CGI);
	2028	addenv2(blk, "PATH");
	2029	addenv2(blk, "TMP");
	2030	addenv2(blk, "TEMP");
	2031	addenv2(blk, "TMPDIR");
	2032	addenv2(blk, "PERLLIB");
	2033	addenv2(blk, ENV_EXPORT_TO_CGI);
2035	2034
2036	2035	#if defined(_WIN32)
2037		addenv2(blk, "COMSPEC");
2038		addenv2(blk, "SYSTEMROOT");
2039		addenv2(blk, "SystemDrive");
2040		addenv2(blk, "ProgramFiles");
2041		addenv2(blk, "ProgramFiles(x86)");
2042		addenv2(blk, "CommonProgramFiles(x86)");
	2036	addenv2(blk, "COMSPEC");
	2037	addenv2(blk, "SYSTEMROOT");
	2038	addenv2(blk, "SystemDrive");
	2039	addenv2(blk, "ProgramFiles");
	2040	addenv2(blk, "ProgramFiles(x86)");
	2041	addenv2(blk, "CommonProgramFiles(x86)");
2043	2042	#else
2044		addenv2(blk, "LD_LIBRARY_PATH");
	2043	addenv2(blk, "LD_LIBRARY_PATH");
2045	2044	#endif // _WIN32
2046	2045
2047		// Add all headers as HTTP_* variables
2048		for (i = 0; i < ri->num_headers; i++) {
2049		p = addenv(blk, "HTTP_%s=%s",
2050		ri->http_headers[i].name, ri->http_headers[i].value);
	2046	// Add all headers as HTTP_* variables
	2047	for (i = 0; i < ri->num_headers; i++) {
	2048	p = addenv(blk, "HTTP_%s=%s",
	2049	ri->http_headers[i].name, ri->http_headers[i].value);
2051	2050
2052		// Convert variable name into uppercase, and change - to _
2053		for (; p != '=' && p != '\0'; p++) {
2054		if (*p == '-')
2055		*p = '_';
2056		p = (char) toupper( (unsigned char *) p);
2057		}
2058		}
	2051	// Convert variable name into uppercase, and change - to _
	2052	for (; p != '=' && p != '\0'; p++) {
	2053	if (*p == '-')
	2054	*p = '_';
	2055	p = (char) toupper( (unsigned char *) p);
	2056	}
	2057	}
2059	2058
2060		blk->vars[blk->nvars++] = NULL;
2061		blk->buf[blk->len++] = '\0';
	2059	blk->vars[blk->nvars++] = NULL;
	2060	blk->buf[blk->len++] = '\0';
2062	2061
2063		assert(blk->nvars < (int) ARRAY_SIZE(blk->vars));
2064		assert(blk->len > 0);
2065		assert(blk->len < (int) sizeof(blk->buf));
	2062	assert(blk->nvars < (int) ARRAY_SIZE(blk->vars));
	2063	assert(blk->len > 0);
	2064	assert(blk->len < (int) sizeof(blk->buf));
2066	2065	}
2067	2066
2068	2067	static const char cgi_status[] = "HTTP/1.1 200 OK\r\n";
2069	2068
2070	2069	static void open_cgi_endpoint(struct connection conn, const char prog) {
2071		struct cgi_env_block blk;
2072		char dir[MAX_PATH_SIZE];
2073		const char *p;
2074		sock_t fds[2];
	2070	struct cgi_env_block blk;
	2071	char dir[MAX_PATH_SIZE];
	2072	const char *p;
	2073	sock_t fds[2];
2075	2074
2076		prepare_cgi_environment(conn, prog, &blk);
2077		// CGI must be executed in its own directory. 'dir' must point to the
2078		// directory containing executable program, 'p' must point to the
2079		// executable program name relative to 'dir'.
2080		if ((p = strrchr(prog, '/')) == NULL) {
2081		mg_snprintf(dir, sizeof(dir), "%s", ".");
2082		} else {
2083		mg_snprintf(dir, sizeof(dir), "%.*s", (int) (p - prog), prog);
2084		}
	2075	prepare_cgi_environment(conn, prog, &blk);
	2076	// CGI must be executed in its own directory. 'dir' must point to the
	2077	// directory containing executable program, 'p' must point to the
	2078	// executable program name relative to 'dir'.
	2079	if ((p = strrchr(prog, '/')) == NULL) {
	2080	mg_snprintf(dir, sizeof(dir), "%s", ".");
	2081	} else {
	2082	mg_snprintf(dir, sizeof(dir), "%.*s", (int) (p - prog), prog);
	2083	}
2085	2084
2086		// Try to create socketpair in a loop until success. ns_socketpair()
2087		// can be interrupted by a signal and fail.
2088		// TODO(lsm): use sigaction to restart interrupted syscall
2089		do {
2090		ns_socketpair(fds);
2091		} while (fds[0] == INVALID_SOCKET);
	2085	// Try to create socketpair in a loop until success. ns_socketpair()
	2086	// can be interrupted by a signal and fail.
	2087	// TODO(lsm): use sigaction to restart interrupted syscall
	2088	do {
	2089	ns_socketpair(fds);
	2090	} while (fds[0] == INVALID_SOCKET);
2092	2091
2093		if (start_process(conn->server->config_options[CGI_INTERPRETER],
2094		prog, blk.buf, blk.vars, dir, fds[1]) != 0) {
2095		conn->endpoint_type = EP_CGI;
2096		conn->endpoint.nc = ns_add_sock(&conn->server->ns_server, fds[0], conn);
2097		conn->endpoint.nc->flags \|= MG_CGI_CONN;
2098		ns_send(conn->ns_conn, cgi_status, sizeof(cgi_status) - 1);
2099		conn->mg_conn.status_code = 200;
2100		conn->ns_conn->flags \|= NSF_BUFFER_BUT_DONT_SEND;
2101		// Pass POST data to the CGI process
2102		conn->endpoint.nc->send_iobuf = conn->ns_conn->recv_iobuf;
2103		iobuf_init(&conn->ns_conn->recv_iobuf, 0);
2104		} else {
2105		closesocket(fds[0]);
2106		send_http_error(conn, 500, "start_process(%s) failed", prog);
2107		}
	2092	if (start_process(conn->server->config_options[CGI_INTERPRETER],
	2093	prog, blk.buf, blk.vars, dir, fds[1]) != 0) {
	2094	conn->endpoint_type = EP_CGI;
	2095	conn->endpoint.nc = ns_add_sock(&conn->server->ns_server, fds[0], conn);
	2096	conn->endpoint.nc->flags \|= MG_CGI_CONN;
	2097	ns_send(conn->ns_conn, cgi_status, sizeof(cgi_status) - 1);
	2098	conn->mg_conn.status_code = 200;
	2099	conn->ns_conn->flags \|= NSF_BUFFER_BUT_DONT_SEND;
	2100	// Pass POST data to the CGI process
	2101	conn->endpoint.nc->send_iobuf = conn->ns_conn->recv_iobuf;
	2102	iobuf_init(&conn->ns_conn->recv_iobuf, 0);
	2103	} else {
	2104	closesocket(fds[0]);
	2105	send_http_error(conn, 500, "start_process(%s) failed", prog);
	2106	}
2108	2107
2109	2108	#ifndef _WIN32
2110		closesocket(fds[1]); // On Windows, CGI stdio thread closes that socket
	2109	closesocket(fds[1]); // On Windows, CGI stdio thread closes that socket
2111	2110	#endif
2112	2111	}
2113	2112
2114	2113	static void on_cgi_data(struct ns_connection *nc) {
2115		struct connection conn = (struct connection ) nc->connection_data;
2116		const char *status = "500";
2117		struct mg_connection c;
	2114	struct connection conn = (struct connection ) nc->connection_data;
	2115	const char *status = "500";
	2116	struct mg_connection c;
2118	2117
2119		if (!conn) return;
	2118	if (!conn) return;
2120	2119
2121		// Copy CGI data from CGI socket to the client send buffer
2122		ns_forward(nc, conn->ns_conn);
	2120	// Copy CGI data from CGI socket to the client send buffer
	2121	ns_forward(nc, conn->ns_conn);
2123	2122
2124		// If reply has not been parsed yet, parse it
2125		if (conn->ns_conn->flags & NSF_BUFFER_BUT_DONT_SEND) {
2126		struct iobuf *io = &conn->ns_conn->send_iobuf;
2127		int s_len = sizeof(cgi_status) - 1;
2128		int len = get_request_len(io->buf + s_len, io->len - s_len);
2129		char buf[MAX_REQUEST_SIZE], *s = buf;
	2123	// If reply has not been parsed yet, parse it
	2124	if (conn->ns_conn->flags & NSF_BUFFER_BUT_DONT_SEND) {
	2125	struct iobuf *io = &conn->ns_conn->send_iobuf;
	2126	int s_len = sizeof(cgi_status) - 1;
	2127	int len = get_request_len(io->buf + s_len, io->len - s_len);
	2128	char buf[MAX_REQUEST_SIZE], *s = buf;
2130	2129
2131		if (len == 0) return;
	2130	if (len == 0) return;
2132	2131
2133		if (len < 0 \|\| len > (int) sizeof(buf)) {
2134		len = io->len;
2135		iobuf_remove(io, io->len);
2136		send_http_error(conn, 500, "CGI program sent malformed headers: [%.*s]",
2137		len, io->buf);
2138		} else {
2139		memset(&c, 0, sizeof(c));
2140		memcpy(buf, io->buf + s_len, len);
2141		buf[len - 1] = '\0';
2142		parse_http_headers(&s, &c);
2143		if (mg_get_header(&c, "Location") != NULL) {
2144		status = "302";
2145		} else if ((status = (char *) mg_get_header(&c, "Status")) == NULL) {
2146		status = "200";
2147		}
2148		memcpy(io->buf + 9, status, 3);
2149		conn->mg_conn.status_code = atoi(status);
2150		}
2151		conn->ns_conn->flags &= ~NSF_BUFFER_BUT_DONT_SEND;
2152		}
	2132	if (len < 0 \|\| len > (int) sizeof(buf)) {
	2133	len = io->len;
	2134	iobuf_remove(io, io->len);
	2135	send_http_error(conn, 500, "CGI program sent malformed headers: [%.*s]",
	2136	len, io->buf);
	2137	} else {
	2138	memset(&c, 0, sizeof(c));
	2139	memcpy(buf, io->buf + s_len, len);
	2140	buf[len - 1] = '\0';
	2141	parse_http_headers(&s, &c);
	2142	if (mg_get_header(&c, "Location") != NULL) {
	2143	status = "302";
	2144	} else if ((status = (char *) mg_get_header(&c, "Status")) == NULL) {
	2145	status = "200";
	2146	}
	2147	memcpy(io->buf + 9, status, 3);
	2148	conn->mg_conn.status_code = atoi(status);
	2149	}
	2150	conn->ns_conn->flags &= ~NSF_BUFFER_BUT_DONT_SEND;
	2151	}
2153	2152	}
2154	2153	#endif // !MONGOOSE_NO_CGI
2155	2154
2156	2155	static char mg_strdup(const char str) {
2157		char copy = (char ) malloc(strlen(str) + 1);
2158		if (copy != NULL) {
2159		strcpy(copy, str);
2160		}
2161		return copy;
	2156	char copy = (char ) malloc(strlen(str) + 1);
	2157	if (copy != NULL) {
	2158	strcpy(copy, str);
	2159	}
	2160	return copy;
2162	2161	}
2163	2162
2164	2163	static int isbyte(int n) {
2165		return n >= 0 && n <= 255;
	2164	return n >= 0 && n <= 255;
2166	2165	}
2167	2166
2168	2167	static int parse_net(const char spec, uint32_t net, uint32_t *mask) {
2169		int n, a, b, c, d, slash = 32, len = 0;
	2168	int n, a, b, c, d, slash = 32, len = 0;
2170	2169
2171		if ((sscanf(spec, "%d.%d.%d.%d/%d%n", &a, &b, &c, &d, &slash, &n) == 5 \|\|
2172		sscanf(spec, "%d.%d.%d.%d%n", &a, &b, &c, &d, &n) == 4) &&
2173		isbyte(a) && isbyte(b) && isbyte(c) && isbyte(d) &&
2174		slash >= 0 && slash < 33) {
2175		len = n;
2176		*net = ((uint32_t)a << 24) \| ((uint32_t)b << 16) \| ((uint32_t)c << 8) \| d;
2177		*mask = slash ? 0xffffffffU << (32 - slash) : 0;
2178		}
	2170	if ((sscanf(spec, "%d.%d.%d.%d/%d%n", &a, &b, &c, &d, &slash, &n) == 5 \|\|
	2171	sscanf(spec, "%d.%d.%d.%d%n", &a, &b, &c, &d, &n) == 4) &&
	2172	isbyte(a) && isbyte(b) && isbyte(c) && isbyte(d) &&
	2173	slash >= 0 && slash < 33) {
	2174	len = n;
	2175	*net = ((uint32_t)a << 24) \| ((uint32_t)b << 16) \| ((uint32_t)c << 8) \| d;
	2176	*mask = slash ? 0xffffffffU << (32 - slash) : 0;
	2177	}
2179	2178
2180		return len;
	2179	return len;
2181	2180	}
2182	2181
2183	2182	// Verify given socket address against the ACL.
2184	2183	// Return -1 if ACL is malformed, 0 if address is disallowed, 1 if allowed.
2185	2184	static int check_acl(const char *acl, uint32_t remote_ip) {
2186		int allowed, flag;
2187		uint32_t net, mask;
2188		struct vec vec;
	2185	int allowed, flag;
	2186	uint32_t net, mask;
	2187	struct vec vec;
2189	2188
2190		// If any ACL is set, deny by default
2191		allowed = acl == NULL ? '+' : '-';
	2189	// If any ACL is set, deny by default
	2190	allowed = acl == NULL ? '+' : '-';
2192	2191
2193		while ((acl = next_option(acl, &vec, NULL)) != NULL) {
2194		flag = vec.ptr[0];
2195		if ((flag != '+' && flag != '-') \|\|
2196		parse_net(&vec.ptr[1], &net, &mask) == 0) {
2197		return -1;
2198		}
	2192	while ((acl = next_option(acl, &vec, NULL)) != NULL) {
	2193	flag = vec.ptr[0];
	2194	if ((flag != '+' && flag != '-') \|\|
	2195	parse_net(&vec.ptr[1], &net, &mask) == 0) {
	2196	return -1;
	2197	}
2199	2198
2200		if (net == (remote_ip & mask)) {
2201		allowed = flag;
2202		}
2203		}
	2199	if (net == (remote_ip & mask)) {
	2200	allowed = flag;
	2201	}
	2202	}
2204	2203
2205		return allowed == '+';
	2204	return allowed == '+';
2206	2205	}
2207	2206
2208	2207	// Protect against directory disclosure attack by removing '..',
2209	2208	// excessive '/' and '\' characters
2210	2209	static void remove_double_dots_and_double_slashes(char *s) {
2211		char *p = s;
	2210	char *p = s;
2212	2211
2213		while (*s != '\0') {
2214		p++ = s++;
2215		if (s[-1] == '/' \|\| s[-1] == '\\') {
2216		// Skip all following slashes, backslashes and double-dots
2217		while (s[0] != '\0') {
2218		if (s[0] == '/' \|\| s[0] == '\\') { s++; }
2219		else if (s[0] == '.' && s[1] == '.') { s += 2; }
2220		else { break; }
2221		}
2222		}
2223		}
2224		*p = '\0';
	2212	while (*s != '\0') {
	2213	p++ = s++;
	2214	if (s[-1] == '/' \|\| s[-1] == '\\') {
	2215	// Skip all following slashes, backslashes and double-dots
	2216	while (s[0] != '\0') {
	2217	if (s[0] == '/' \|\| s[0] == '\\') { s++; }
	2218	else if (s[0] == '.' && s[1] == '.') { s += 2; }
	2219	else { break; }
	2220	}
	2221	}
	2222	}
	2223	*p = '\0';
2225	2224	}
2226	2225
2227	2226	int mg_url_decode(const char src, int src_len, char dst,
2228		int dst_len, int is_form_url_encoded) {
2229		int i, j, a, b;
	2227	int dst_len, int is_form_url_encoded) {
	2228	int i, j, a, b;
2230	2229	#define HEXTOI(x) (isdigit(x) ? x - '0' : x - 'W')
2231	2230
2232		for (i = j = 0; i < src_len && j < dst_len - 1; i++, j++) {
2233		if (src[i] == '%' && i < src_len - 2 &&
2234		isxdigit(* (const unsigned char *) (src + i + 1)) &&
2235		isxdigit(* (const unsigned char *) (src + i + 2))) {
2236		a = tolower(* (const unsigned char *) (src + i + 1));
2237		b = tolower(* (const unsigned char *) (src + i + 2));
2238		dst[j] = (char) ((HEXTOI(a) << 4) \| HEXTOI(b));
2239		i += 2;
2240		} else if (is_form_url_encoded && src[i] == '+') {
2241		dst[j] = ' ';
2242		} else {
2243		dst[j] = src[i];
2244		}
2245		}
	2231	for (i = j = 0; i < src_len && j < dst_len - 1; i++, j++) {
	2232	if (src[i] == '%' && i < src_len - 2 &&
	2233	isxdigit(* (const unsigned char *) (src + i + 1)) &&
	2234	isxdigit(* (const unsigned char *) (src + i + 2))) {
	2235	a = tolower(* (const unsigned char *) (src + i + 1));
	2236	b = tolower(* (const unsigned char *) (src + i + 2));
	2237	dst[j] = (char) ((HEXTOI(a) << 4) \| HEXTOI(b));
	2238	i += 2;
	2239	} else if (is_form_url_encoded && src[i] == '+') {
	2240	dst[j] = ' ';
	2241	} else {
	2242	dst[j] = src[i];
	2243	}
	2244	}
2246	2245
2247		dst[j] = '\0'; // Null-terminate the destination
	2246	dst[j] = '\0'; // Null-terminate the destination
2248	2247
2249		return i >= src_len ? j : -1;
	2248	return i >= src_len ? j : -1;
2250	2249	}
2251	2250
2252	2251	static int is_valid_http_method(const char *s) {
2253		return !strcmp(s, "GET") \|\| !strcmp(s, "POST") \|\| !strcmp(s, "HEAD") \|\|
2254		!strcmp(s, "CONNECT") \|\| !strcmp(s, "PUT") \|\| !strcmp(s, "DELETE") \|\|
2255		!strcmp(s, "OPTIONS") \|\| !strcmp(s, "PROPFIND") \|\| !strcmp(s, "MKCOL");
	2252	return !strcmp(s, "GET") \|\| !strcmp(s, "POST") \|\| !strcmp(s, "HEAD") \|\|
	2253	!strcmp(s, "CONNECT") \|\| !strcmp(s, "PUT") \|\| !strcmp(s, "DELETE") \|\|
	2254	!strcmp(s, "OPTIONS") \|\| !strcmp(s, "PROPFIND") \|\| !strcmp(s, "MKCOL");
2256	2255	}
2257	2256
2258	2257	// Parse HTTP request, fill in mg_request structure.
r32760	r32761
2260	2259	// HTTP request components, header names and header values.
2261	2260	// Note that len must point to the last \n of HTTP headers.
2262	2261	static int parse_http_message(char buf, int len, struct mg_connection ri) {
2263		int is_request, n;
	2262	int is_request, n;
2264	2263
2265		// Reset the connection. Make sure that we don't touch fields that are
2266		// set elsewhere: remote_ip, remote_port, server_param
2267		ri->request_method = ri->uri = ri->http_version = ri->query_string = NULL;
2268		ri->num_headers = ri->status_code = ri->is_websocket = ri->content_len = 0;
	2264	// Reset the connection. Make sure that we don't touch fields that are
	2265	// set elsewhere: remote_ip, remote_port, server_param
	2266	ri->request_method = ri->uri = ri->http_version = ri->query_string = NULL;
	2267	ri->num_headers = ri->status_code = ri->is_websocket = ri->content_len = 0;
2269	2268
2270		buf[len - 1] = '\0';
	2269	buf[len - 1] = '\0';
2271	2270
2272		// RFC says that all initial whitespaces should be ingored
2273		while (buf != '\0' && isspace( (unsigned char *) buf)) {
2274		buf++;
2275		}
2276		ri->request_method = skip(&buf, " ");
2277		ri->uri = skip(&buf, " ");
2278		ri->http_version = skip(&buf, "\r\n");
	2271	// RFC says that all initial whitespaces should be ingored
	2272	while (buf != '\0' && isspace( (unsigned char *) buf)) {
	2273	buf++;
	2274	}
	2275	ri->request_method = skip(&buf, " ");
	2276	ri->uri = skip(&buf, " ");
	2277	ri->http_version = skip(&buf, "\r\n");
2279	2278
2280		// HTTP message could be either HTTP request or HTTP response, e.g.
2281		// "GET / HTTP/1.0 ...." or "HTTP/1.0 200 OK ..."
2282		is_request = is_valid_http_method(ri->request_method);
2283		if ((is_request && memcmp(ri->http_version, "HTTP/", 5) != 0) \|\|
2284		(!is_request && memcmp(ri->request_method, "HTTP/", 5) != 0)) {
2285		len = -1;
2286		} else {
2287		if (is_request) {
2288		ri->http_version += 5;
2289		}
2290		parse_http_headers(&buf, ri);
	2279	// HTTP message could be either HTTP request or HTTP response, e.g.
	2280	// "GET / HTTP/1.0 ...." or "HTTP/1.0 200 OK ..."
	2281	is_request = is_valid_http_method(ri->request_method);
	2282	if ((is_request && memcmp(ri->http_version, "HTTP/", 5) != 0) \|\|
	2283	(!is_request && memcmp(ri->request_method, "HTTP/", 5) != 0)) {
	2284	len = -1;
	2285	} else {
	2286	if (is_request) {
	2287	ri->http_version += 5;
	2288	}
	2289	parse_http_headers(&buf, ri);
2291	2290
2292		if ((ri->query_string = strchr(ri->uri, '?')) != NULL) {
2293		(char ) ri->query_string++ = '\0';
2294		}
2295		n = (int) strlen(ri->uri);
2296		mg_url_decode(ri->uri, n, (char *) ri->uri, n + 1, 0);
2297		if (ri->uri == '/' \|\| ri->uri == '.') {
2298		remove_double_dots_and_double_slashes((char *) ri->uri);
2299		}
2300		}
	2291	if ((ri->query_string = strchr(ri->uri, '?')) != NULL) {
	2292	(char ) ri->query_string++ = '\0';
	2293	}
	2294	n = (int) strlen(ri->uri);
	2295	mg_url_decode(ri->uri, n, (char *) ri->uri, n + 1, 0);
	2296	if (ri->uri == '/' \|\| ri->uri == '.') {
	2297	remove_double_dots_and_double_slashes((char *) ri->uri);
	2298	}
	2299	}
2301	2300
2302		return len;
	2301	return len;
2303	2302	}
2304	2303
2305	2304	static int lowercase(const char *s) {
2306		return tolower(* (const unsigned char *) s);
	2305	return tolower(* (const unsigned char *) s);
2307	2306	}
2308	2307
2309	2308	static int mg_strcasecmp(const char s1, const char s2) {
2310		int diff;
	2309	int diff;
2311	2310
2312		do {
2313		diff = lowercase(s1++) - lowercase(s2++);
2314		} while (diff == 0 && s1[-1] != '\0');
	2311	do {
	2312	diff = lowercase(s1++) - lowercase(s2++);
	2313	} while (diff == 0 && s1[-1] != '\0');
2315	2314
2316		return diff;
	2315	return diff;
2317	2316	}
2318	2317
2319	2318	static int mg_strncasecmp(const char s1, const char s2, size_t len) {
2320		int diff = 0;
	2319	int diff = 0;
2321	2320
2322		if (len > 0)
2323		do {
2324		diff = lowercase(s1++) - lowercase(s2++);
2325		} while (diff == 0 && s1[-1] != '\0' && --len > 0);
	2321	if (len > 0)
	2322	do {
	2323	diff = lowercase(s1++) - lowercase(s2++);
	2324	} while (diff == 0 && s1[-1] != '\0' && --len > 0);
2326	2325
2327		return diff;
	2326	return diff;
2328	2327	}
2329	2328
2330	2329	// Return HTTP header value, or NULL if not found.
2331	2330	const char mg_get_header(const struct mg_connection ri, const char *s) {
2332		int i;
	2331	int i;
2333	2332
2334		for (i = 0; i < ri->num_headers; i++)
2335		if (!mg_strcasecmp(s, ri->http_headers[i].name))
2336		return ri->http_headers[i].value;
	2333	for (i = 0; i < ri->num_headers; i++)
	2334	if (!mg_strcasecmp(s, ri->http_headers[i].name))
	2335	return ri->http_headers[i].value;
2337	2336
2338		return NULL;
	2337	return NULL;
2339	2338	}
2340	2339
2341	2340	// Perform case-insensitive match of string against pattern
2342	2341	int mg_match_prefix(const char pattern, int pattern_len, const char str) {
2343		const char *or_str;
2344		int len, res, i = 0, j = 0;
	2342	const char *or_str;
	2343	int len, res, i = 0, j = 0;
2345	2344
2346		if ((or_str = (const char *) memchr(pattern, '\|', pattern_len)) != NULL) {
2347		res = mg_match_prefix(pattern, or_str - pattern, str);
2348		return res > 0 ? res : mg_match_prefix(or_str + 1,
2349		(pattern + pattern_len) - (or_str + 1), str);
2350		}
	2345	if ((or_str = (const char *) memchr(pattern, '\|', pattern_len)) != NULL) {
	2346	res = mg_match_prefix(pattern, or_str - pattern, str);
	2347	return res > 0 ? res : mg_match_prefix(or_str + 1,
	2348	(pattern + pattern_len) - (or_str + 1), str);
	2349	}
2351	2350
2352		for (; i < pattern_len; i++, j++) {
2353		if (pattern[i] == '?' && str[j] != '\0') {
2354		continue;
2355		} else if (pattern[i] == '$') {
2356		return str[j] == '\0' ? j : -1;
2357		} else if (pattern[i] == '*') {
2358		i++;
2359		if (pattern[i] == '*') {
2360		i++;
2361		len = (int) strlen(str + j);
2362		} else {
2363		len = (int) strcspn(str + j, "/");
2364		}
2365		if (i == pattern_len) {
2366		return j + len;
2367		}
2368		do {
2369		res = mg_match_prefix(pattern + i, pattern_len - i, str + j + len);
2370		} while (res == -1 && len-- > 0);
2371		return res == -1 ? -1 : j + res + len;
2372		} else if (lowercase(&pattern[i]) != lowercase(&str[j])) {
2373		return -1;
2374		}
2375		}
2376		return j;
	2351	for (; i < pattern_len; i++, j++) {
	2352	if (pattern[i] == '?' && str[j] != '\0') {
	2353	continue;
	2354	} else if (pattern[i] == '$') {
	2355	return str[j] == '\0' ? j : -1;
	2356	} else if (pattern[i] == '*') {
	2357	i++;
	2358	if (pattern[i] == '*') {
	2359	i++;
	2360	len = (int) strlen(str + j);
	2361	} else {
	2362	len = (int) strcspn(str + j, "/");
	2363	}
	2364	if (i == pattern_len) {
	2365	return j + len;
	2366	}
	2367	do {
	2368	res = mg_match_prefix(pattern + i, pattern_len - i, str + j + len);
	2369	} while (res == -1 && len-- > 0);
	2370	return res == -1 ? -1 : j + res + len;
	2371	} else if (lowercase(&pattern[i]) != lowercase(&str[j])) {
	2372	return -1;
	2373	}
	2374	}
	2375	return j;
2377	2376	}
2378	2377
2379	2378	// This function prints HTML pages, and expands "{{something}}" blocks
r32760	r32761
2381	2380	// Note that {{@path/to/file}} construct outputs embedded file's contents,
2382	2381	// which provides SSI-like functionality.
2383	2382	void mg_template(struct mg_connection conn, const char s,
2384		struct mg_expansion *expansions) {
2385		int i, j, pos = 0, inside_marker = 0;
	2383	struct mg_expansion *expansions) {
	2384	int i, j, pos = 0, inside_marker = 0;
2386	2385
2387		for (i = 0; s[i] != '\0'; i++) {
2388		if (inside_marker == 0 && !memcmp(&s[i], "{{", 2)) {
2389		if (i > pos) {
2390		mg_send_data(conn, &s[pos], i - pos);
2391		}
2392		pos = i;
2393		inside_marker = 1;
2394		}
2395		if (inside_marker == 1 && !memcmp(&s[i], "}}", 2)) {
2396		for (j = 0; expansions[j].keyword != NULL; j++) {
2397		const char *kw = expansions[j].keyword;
2398		if ((int) strlen(kw) == i - (pos + 2) &&
2399		memcmp(kw, &s[pos + 2], i - (pos + 2)) == 0) {
2400		expansions[j].handler(conn);
2401		pos = i + 2;
2402		break;
2403		}
2404		}
2405		inside_marker = 0;
2406		}
2407		}
2408		if (i > pos) {
2409		mg_send_data(conn, &s[pos], i - pos);
2410		}
	2386	for (i = 0; s[i] != '\0'; i++) {
	2387	if (inside_marker == 0 && !memcmp(&s[i], "{{", 2)) {
	2388	if (i > pos) {
	2389	mg_send_data(conn, &s[pos], i - pos);
	2390	}
	2391	pos = i;
	2392	inside_marker = 1;
	2393	}
	2394	if (inside_marker == 1 && !memcmp(&s[i], "}}", 2)) {
	2395	for (j = 0; expansions[j].keyword != NULL; j++) {
	2396	const char *kw = expansions[j].keyword;
	2397	if ((int) strlen(kw) == i - (pos + 2) &&
	2398	memcmp(kw, &s[pos + 2], i - (pos + 2)) == 0) {
	2399	expansions[j].handler(conn);
	2400	pos = i + 2;
	2401	break;
	2402	}
	2403	}
	2404	inside_marker = 0;
	2405	}
	2406	}
	2407	if (i > pos) {
	2408	mg_send_data(conn, &s[pos], i - pos);
	2409	}
2411	2410	}
2412	2411
2413	2412	#ifndef MONGOOSE_NO_FILESYSTEM
2414	2413	static int must_hide_file(struct connection conn, const char path) {
2415		const char pw_pattern = "*" PASSWORDS_FILE_NAME "$";
2416		const char *pattern = conn->server->config_options[HIDE_FILES_PATTERN];
2417		return mg_match_prefix(pw_pattern, strlen(pw_pattern), path) > 0 \|\|
2418		(pattern != NULL && mg_match_prefix(pattern, strlen(pattern), path) > 0);
	2414	const char pw_pattern = "*" PASSWORDS_FILE_NAME "$";
	2415	const char *pattern = conn->server->config_options[HIDE_FILES_PATTERN];
	2416	return mg_match_prefix(pw_pattern, strlen(pw_pattern), path) > 0 \|\|
	2417	(pattern != NULL && mg_match_prefix(pattern, strlen(pattern), path) > 0);
2419	2418	}
2420	2419
2421	2420	// Return 1 if real file has been found, 0 otherwise
2422	2421	static int convert_uri_to_file_name(struct connection conn, char buf,
2423		size_t buf_len, file_stat_t *st) {
2424		struct vec a, b;
2425		const char *rewrites = conn->server->config_options[URL_REWRITES];
2426		const char *root = conn->server->config_options[DOCUMENT_ROOT];
	2422	size_t buf_len, file_stat_t *st) {
	2423	struct vec a, b;
	2424	const char *rewrites = conn->server->config_options[URL_REWRITES];
	2425	const char *root = conn->server->config_options[DOCUMENT_ROOT];
2427	2426	#ifndef MONGOOSE_NO_CGI
2428		const char *cgi_pat = conn->server->config_options[CGI_PATTERN];
2429		char *p;
	2427	const char *cgi_pat = conn->server->config_options[CGI_PATTERN];
	2428	char *p;
2430	2429	#endif
2431		const char *uri = conn->mg_conn.uri;
2432		const char *domain = mg_get_header(&conn->mg_conn, "Host");
2433		int match_len, root_len = root == NULL ? 0 : strlen(root);
	2430	const char *uri = conn->mg_conn.uri;
	2431	const char *domain = mg_get_header(&conn->mg_conn, "Host");
	2432	int match_len, root_len = root == NULL ? 0 : strlen(root);
2434	2433
2435		// Perform virtual hosting rewrites
2436		if (rewrites != NULL && domain != NULL) {
2437		const char *colon = strchr(domain, ':');
2438		int domain_len = colon == NULL ? (int) strlen(domain) : colon - domain;
	2434	// Perform virtual hosting rewrites
	2435	if (rewrites != NULL && domain != NULL) {
	2436	const char *colon = strchr(domain, ':');
	2437	int domain_len = colon == NULL ? (int) strlen(domain) : colon - domain;
2439	2438
2440		while ((rewrites = next_option(rewrites, &a, &b)) != NULL) {
2441		if (a.len > 1 && a.ptr[0] == '@' && a.len == domain_len + 1 &&
2442		mg_strncasecmp(a.ptr + 1, domain, domain_len) == 0) {
2443		root = b.ptr;
2444		root_len = b.len;
2445		break;
2446		}
2447		}
2448		}
	2439	while ((rewrites = next_option(rewrites, &a, &b)) != NULL) {
	2440	if (a.len > 1 && a.ptr[0] == '@' && a.len == domain_len + 1 &&
	2441	mg_strncasecmp(a.ptr + 1, domain, domain_len) == 0) {
	2442	root = b.ptr;
	2443	root_len = b.len;
	2444	break;
	2445	}
	2446	}
	2447	}
2449	2448
2450		// No filesystem access
2451		if (root == NULL \|\| root_len == 0) return 0;
	2449	// No filesystem access
	2450	if (root == NULL \|\| root_len == 0) return 0;
2452	2451
2453		// Handle URL rewrites
2454		mg_snprintf(buf, buf_len, "%.*s%s", root_len, root, uri);
2455		rewrites = conn->server->config_options[URL_REWRITES]; // Re-initialize!
2456		while ((rewrites = next_option(rewrites, &a, &b)) != NULL) {
2457		if ((match_len = mg_match_prefix(a.ptr, a.len, uri)) > 0) {
2458		mg_snprintf(buf, buf_len, "%.*s%s", (int) b.len, b.ptr, uri + match_len);
2459		break;
2460		}
2461		}
	2452	// Handle URL rewrites
	2453	mg_snprintf(buf, buf_len, "%.*s%s", root_len, root, uri);
	2454	rewrites = conn->server->config_options[URL_REWRITES]; // Re-initialize!
	2455	while ((rewrites = next_option(rewrites, &a, &b)) != NULL) {
	2456	if ((match_len = mg_match_prefix(a.ptr, a.len, uri)) > 0) {
	2457	mg_snprintf(buf, buf_len, "%.*s%s", (int) b.len, b.ptr, uri + match_len);
	2458	break;
	2459	}
	2460	}
2462	2461
2463		if (stat(buf, st) == 0) return 1;
	2462	if (stat(buf, st) == 0) return 1;
2464	2463
2465	2464	#ifndef MONGOOSE_NO_CGI
2466		// Support PATH_INFO for CGI scripts.
2467		for (p = buf + strlen(root) + 2; *p != '\0'; p++) {
2468		if (*p == '/') {
2469		*p = '\0';
2470		if (mg_match_prefix(cgi_pat, strlen(cgi_pat), buf) > 0 &&
2471		!stat(buf, st)) {
2472		DBG(("!!!! [%s]", buf));
2473		*p = '/';
2474		conn->path_info = mg_strdup(p);
2475		*p = '\0';
2476		return 1;
2477		}
2478		*p = '/';
2479		}
2480		}
	2465	// Support PATH_INFO for CGI scripts.
	2466	for (p = buf + strlen(root) + 2; *p != '\0'; p++) {
	2467	if (*p == '/') {
	2468	*p = '\0';
	2469	if (mg_match_prefix(cgi_pat, strlen(cgi_pat), buf) > 0 &&
	2470	!stat(buf, st)) {
	2471	DBG(("!!!! [%s]", buf));
	2472	*p = '/';
	2473	conn->path_info = mg_strdup(p);
	2474	*p = '\0';
	2475	return 1;
	2476	}
	2477	*p = '/';
	2478	}
	2479	}
2481	2480	#endif
2482	2481
2483		return 0;
	2482	return 0;
2484	2483	}
2485	2484	#endif // MONGOOSE_NO_FILESYSTEM
2486	2485
2487	2486	static int should_keep_alive(const struct mg_connection *conn) {
2488		struct connection *c = MG_CONN_2_CONN(conn);
2489		const char *method = conn->request_method;
2490		const char *http_version = conn->http_version;
2491		const char *header = mg_get_header(conn, "Connection");
2492		return method != NULL &&
2493		(!strcmp(method, "GET") \|\| c->endpoint_type == EP_USER) &&
2494		((header != NULL && !mg_strcasecmp(header, "keep-alive")) \|\|
2495		(header == NULL && http_version && !strcmp(http_version, "1.1")));
	2487	struct connection *c = MG_CONN_2_CONN(conn);
	2488	const char *method = conn->request_method;
	2489	const char *http_version = conn->http_version;
	2490	const char *header = mg_get_header(conn, "Connection");
	2491	return method != NULL &&
	2492	(!strcmp(method, "GET") \|\| c->endpoint_type == EP_USER) &&
	2493	((header != NULL && !mg_strcasecmp(header, "keep-alive")) \|\|
	2494	(header == NULL && http_version && !strcmp(http_version, "1.1")));
2496	2495	}
2497	2496
2498	2497	size_t mg_write(struct mg_connection c, const void buf, int len) {
2499		struct connection *conn = MG_CONN_2_CONN(c);
2500		ns_send(conn->ns_conn, buf, len);
2501		return conn->ns_conn->send_iobuf.len;
	2498	struct connection *conn = MG_CONN_2_CONN(c);
	2499	ns_send(conn->ns_conn, buf, len);
	2500	return conn->ns_conn->send_iobuf.len;
2502	2501	}
2503	2502
2504	2503	void mg_send_status(struct mg_connection *c, int status) {
2505		if (c->status_code == 0) {
2506		c->status_code = status;
2507		mg_printf(c, "HTTP/1.1 %d %s\r\n", status, status_code_to_str(status));
2508		}
	2504	if (c->status_code == 0) {
	2505	c->status_code = status;
	2506	mg_printf(c, "HTTP/1.1 %d %s\r\n", status, status_code_to_str(status));
	2507	}
2509	2508	}
2510	2509
2511	2510	void mg_send_header(struct mg_connection c, const char name, const char *v) {
2512		if (c->status_code == 0) {
2513		c->status_code = 200;
2514		mg_printf(c, "HTTP/1.1 %d %s\r\n", 200, status_code_to_str(200));
2515		}
2516		mg_printf(c, "%s: %s\r\n", name, v);
	2511	if (c->status_code == 0) {
	2512	c->status_code = 200;
	2513	mg_printf(c, "HTTP/1.1 %d %s\r\n", 200, status_code_to_str(200));
	2514	}
	2515	mg_printf(c, "%s: %s\r\n", name, v);
2517	2516	}
2518	2517
2519	2518	static void terminate_headers(struct mg_connection *c) {
2520		struct connection *conn = MG_CONN_2_CONN(c);
2521		if (!(conn->ns_conn->flags & MG_HEADERS_SENT)) {
2522		mg_send_header(c, "Transfer-Encoding", "chunked");
2523		mg_write(c, "\r\n", 2);
2524		conn->ns_conn->flags \|= MG_HEADERS_SENT;
2525		}
	2519	struct connection *conn = MG_CONN_2_CONN(c);
	2520	if (!(conn->ns_conn->flags & MG_HEADERS_SENT)) {
	2521	mg_send_header(c, "Transfer-Encoding", "chunked");
	2522	mg_write(c, "\r\n", 2);
	2523	conn->ns_conn->flags \|= MG_HEADERS_SENT;
	2524	}
2526	2525	}
2527	2526
2528	2527	size_t mg_send_data(struct mg_connection c, const void data, int data_len) {
2529		struct connection *conn = MG_CONN_2_CONN(c);
2530		terminate_headers(c);
2531		write_chunk(MG_CONN_2_CONN(c), (const char *) data, data_len);
2532		return conn->ns_conn->send_iobuf.len;
	2528	struct connection *conn = MG_CONN_2_CONN(c);
	2529	terminate_headers(c);
	2530	write_chunk(MG_CONN_2_CONN(c), (const char *) data, data_len);
	2531	return conn->ns_conn->send_iobuf.len;
2533	2532	}
2534	2533
2535	2534	size_t mg_printf_data(struct mg_connection c, const char fmt, ...) {
2536		struct connection *conn = MG_CONN_2_CONN(c);
2537		va_list ap;
2538		int len;
2539		char mem[IOBUF_SIZE], *buf = mem;
	2535	struct connection *conn = MG_CONN_2_CONN(c);
	2536	va_list ap;
	2537	int len;
	2538	char mem[IOBUF_SIZE], *buf = mem;
2540	2539
2541		terminate_headers(c);
	2540	terminate_headers(c);
2542	2541
2543		va_start(ap, fmt);
2544		len = ns_avprintf(&buf, sizeof(mem), fmt, ap);
2545		va_end(ap);
	2542	va_start(ap, fmt);
	2543	len = ns_avprintf(&buf, sizeof(mem), fmt, ap);
	2544	va_end(ap);
2546	2545
2547		if (len >= 0) {
2548		write_chunk((struct connection *) conn, buf, len);
2549		}
2550		if (buf != mem && buf != NULL) {
2551		free(buf);
2552		}
2553		return conn->ns_conn->send_iobuf.len;
	2546	if (len >= 0) {
	2547	write_chunk((struct connection *) conn, buf, len);
	2548	}
	2549	if (buf != mem && buf != NULL) {
	2550	free(buf);
	2551	}
	2552	return conn->ns_conn->send_iobuf.len;
2554	2553	}
2555	2554
2556	2555	#if !defined(MONGOOSE_NO_WEBSOCKET) \|\| !defined(MONGOOSE_NO_AUTH)
2557	2556	static int is_big_endian(void) {
2558		static const int n = 1;
2559		return ((char *) &n)[0] == 0;
	2557	static const int n = 1;
	2558	return ((char *) &n)[0] == 0;
2560	2559	}
2561	2560	#endif
2562	2561
r32760	r32761
2573	2572	#define rol(value, bits) (((value) << (bits)) \| ((value) >> (32 - (bits))))
2574	2573
2575	2574	static uint32_t blk0(union char64long16 *block, int i) {
2576		// Forrest: SHA expect BIG_ENDIAN, swap if LITTLE_ENDIAN
2577		if (!is_big_endian()) {
2578		block->l[i] = (rol(block->l[i], 24) & 0xFF00FF00) \|
2579		(rol(block->l[i], 8) & 0x00FF00FF);
2580		}
2581		return block->l[i];
	2575	// Forrest: SHA expect BIG_ENDIAN, swap if LITTLE_ENDIAN
	2576	if (!is_big_endian()) {
	2577	block->l[i] = (rol(block->l[i], 24) & 0xFF00FF00) \|
	2578	(rol(block->l[i], 8) & 0x00FF00FF);
	2579	}
	2580	return block->l[i];
2582	2581	}
2583	2582
2584	2583	#define blk(i) (block->l[i&15] = rol(block->l[(i+13)&15]^block->l[(i+8)&15] \
2585		^block->l[(i+2)&15]^block->l[i&15],1))
	2584	^block->l[(i+2)&15]^block->l[i&15],1))
2586	2585	#define R0(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk0(block, i)+0x5A827999+rol(v,5);w=rol(w,30);
2587	2586	#define R1(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk(i)+0x5A827999+rol(v,5);w=rol(w,30);
2588	2587	#define R2(v,w,x,y,z,i) z+=(w^x^y)+blk(i)+0x6ED9EBA1+rol(v,5);w=rol(w,30);
r32760	r32761
2590	2589	#define R4(v,w,x,y,z,i) z+=(w^x^y)+blk(i)+0xCA62C1D6+rol(v,5);w=rol(w,30);
2591	2590
2592	2591	typedef struct {
2593		uint32_t state[5];
2594		uint32_t count[2];
2595		unsigned char buffer[64];
	2592	uint32_t state[5];
	2593	uint32_t count[2];
	2594	unsigned char buffer[64];
2596	2595	} SHA1_CTX;
2597	2596
2598	2597	static void SHA1Transform(uint32_t state[5], const unsigned char buffer[64]) {
2599		uint32_t a, b, c, d, e;
2600		union char64long16 block[1];
	2598	uint32_t a, b, c, d, e;
	2599	union char64long16 block[1];
2601	2600
2602		memcpy(block, buffer, 64);
2603		a = state[0];
2604		b = state[1];
2605		c = state[2];
2606		d = state[3];
2607		e = state[4];
2608		R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3);
2609		R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7);
2610		R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11);
2611		R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15);
2612		R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19);
2613		R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23);
2614		R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27);
2615		R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31);
2616		R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35);
2617		R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39);
2618		R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43);
2619		R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47);
2620		R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51);
2621		R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55);
2622		R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59);
2623		R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63);
2624		R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67);
2625		R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71);
2626		R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75);
2627		R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79);
2628		state[0] += a;
2629		state[1] += b;
2630		state[2] += c;
2631		state[3] += d;
2632		state[4] += e;
2633		// Erase working structures. The order of operations is important,
2634		// used to ensure that compiler doesn't optimize those out.
2635		memset(block, 0, sizeof(block));
2636		a = b = c = d = e = 0;
2637		(void) a; (void) b; (void) c; (void) d; (void) e;
	2601	memcpy(block, buffer, 64);
	2602	a = state[0];
	2603	b = state[1];
	2604	c = state[2];
	2605	d = state[3];
	2606	e = state[4];
	2607	R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3);
	2608	R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7);
	2609	R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11);
	2610	R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15);
	2611	R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19);
	2612	R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23);
	2613	R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27);
	2614	R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31);
	2615	R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35);
	2616	R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39);
	2617	R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43);
	2618	R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47);
	2619	R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51);
	2620	R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55);
	2621	R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59);
	2622	R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63);
	2623	R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67);
	2624	R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71);
	2625	R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75);
	2626	R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79);
	2627	state[0] += a;
	2628	state[1] += b;
	2629	state[2] += c;
	2630	state[3] += d;
	2631	state[4] += e;
	2632	// Erase working structures. The order of operations is important,
	2633	// used to ensure that compiler doesn't optimize those out.
	2634	memset(block, 0, sizeof(block));
	2635	a = b = c = d = e = 0;
	2636	(void) a; (void) b; (void) c; (void) d; (void) e;
2638	2637	}
2639	2638
2640	2639	static void SHA1Init(SHA1_CTX *context) {
2641		context->state[0] = 0x67452301;
2642		context->state[1] = 0xEFCDAB89;
2643		context->state[2] = 0x98BADCFE;
2644		context->state[3] = 0x10325476;
2645		context->state[4] = 0xC3D2E1F0;
2646		context->count[0] = context->count[1] = 0;
	2640	context->state[0] = 0x67452301;
	2641	context->state[1] = 0xEFCDAB89;
	2642	context->state[2] = 0x98BADCFE;
	2643	context->state[3] = 0x10325476;
	2644	context->state[4] = 0xC3D2E1F0;
	2645	context->count[0] = context->count[1] = 0;
2647	2646	}
2648	2647
2649	2648	static void SHA1Update(SHA1_CTX context, const unsigned char data,
2650		uint32_t len) {
2651		uint32_t i, j;
	2649	uint32_t len) {
	2650	uint32_t i, j;
2652	2651
2653		j = context->count[0];
2654		if ((context->count[0] += len << 3) < j)
2655		context->count[1]++;
2656		context->count[1] += (len>>29);
2657		j = (j >> 3) & 63;
2658		if ((j + len) > 63) {
2659		memcpy(&context->buffer[j], data, (i = 64-j));
2660		SHA1Transform(context->state, context->buffer);
2661		for ( ; i + 63 < len; i += 64) {
2662		SHA1Transform(context->state, &data[i]);
2663		}
2664		j = 0;
2665		}
2666		else i = 0;
2667		memcpy(&context->buffer[j], &data[i], len - i);
	2652	j = context->count[0];
	2653	if ((context->count[0] += len << 3) < j)
	2654	context->count[1]++;
	2655	context->count[1] += (len>>29);
	2656	j = (j >> 3) & 63;
	2657	if ((j + len) > 63) {
	2658	memcpy(&context->buffer[j], data, (i = 64-j));
	2659	SHA1Transform(context->state, context->buffer);
	2660	for ( ; i + 63 < len; i += 64) {
	2661	SHA1Transform(context->state, &data[i]);
	2662	}
	2663	j = 0;
	2664	}
	2665	else i = 0;
	2666	memcpy(&context->buffer[j], &data[i], len - i);
2668	2667	}
2669	2668
2670	2669	static void SHA1Final(unsigned char digest[20], SHA1_CTX *context) {
2671		unsigned i;
2672		unsigned char finalcount[8], c;
	2670	unsigned i;
	2671	unsigned char finalcount[8], c;
2673	2672
2674		for (i = 0; i < 8; i++) {
2675		finalcount[i] = (unsigned char)((context->count[(i >= 4 ? 0 : 1)]
2676		>> ((3-(i & 3)) * 8) ) & 255);
2677		}
2678		c = 0200;
2679		SHA1Update(context, &c, 1);
2680		while ((context->count[0] & 504) != 448) {
2681		c = 0000;
2682		SHA1Update(context, &c, 1);
2683		}
2684		SHA1Update(context, finalcount, 8);
2685		for (i = 0; i < 20; i++) {
2686		digest[i] = (unsigned char)
2687		((context->state[i>>2] >> ((3-(i & 3)) * 8) ) & 255);
2688		}
2689		memset(context, '\0', sizeof(*context));
2690		memset(&finalcount, '\0', sizeof(finalcount));
	2673	for (i = 0; i < 8; i++) {
	2674	finalcount[i] = (unsigned char)((context->count[(i >= 4 ? 0 : 1)]
	2675	>> ((3-(i & 3)) * 8) ) & 255);
	2676	}
	2677	c = 0200;
	2678	SHA1Update(context, &c, 1);
	2679	while ((context->count[0] & 504) != 448) {
	2680	c = 0000;
	2681	SHA1Update(context, &c, 1);
	2682	}
	2683	SHA1Update(context, finalcount, 8);
	2684	for (i = 0; i < 20; i++) {
	2685	digest[i] = (unsigned char)
	2686	((context->state[i>>2] >> ((3-(i & 3)) * 8) ) & 255);
	2687	}
	2688	memset(context, '\0', sizeof(*context));
	2689	memset(&finalcount, '\0', sizeof(finalcount));
2691	2690	}
2692	2691	// END OF SHA1 CODE
2693	2692
2694	2693	static void base64_encode(const unsigned char src, int src_len, char dst) {
2695		static const char *b64 =
2696		"ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/";
2697		int i, j, a, b, c;
	2694	static const char *b64 =
	2695	"ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/";
	2696	int i, j, a, b, c;
2698	2697
2699		for (i = j = 0; i < src_len; i += 3) {
2700		a = src[i];
2701		b = i + 1 >= src_len ? 0 : src[i + 1];
2702		c = i + 2 >= src_len ? 0 : src[i + 2];
	2698	for (i = j = 0; i < src_len; i += 3) {
	2699	a = src[i];
	2700	b = i + 1 >= src_len ? 0 : src[i + 1];
	2701	c = i + 2 >= src_len ? 0 : src[i + 2];
2703	2702
2704		dst[j++] = b64[a >> 2];
2705		dst[j++] = b64[((a & 3) << 4) \| (b >> 4)];
2706		if (i + 1 < src_len) {
2707		dst[j++] = b64[(b & 15) << 2 \| (c >> 6)];
2708		}
2709		if (i + 2 < src_len) {
2710		dst[j++] = b64[c & 63];
2711		}
2712		}
2713		while (j % 4 != 0) {
2714		dst[j++] = '=';
2715		}
2716		dst[j++] = '\0';
	2703	dst[j++] = b64[a >> 2];
	2704	dst[j++] = b64[((a & 3) << 4) \| (b >> 4)];
	2705	if (i + 1 < src_len) {
	2706	dst[j++] = b64[(b & 15) << 2 \| (c >> 6)];
	2707	}
	2708	if (i + 2 < src_len) {
	2709	dst[j++] = b64[c & 63];
	2710	}
	2711	}
	2712	while (j % 4 != 0) {
	2713	dst[j++] = '=';
	2714	}
	2715	dst[j++] = '\0';
2717	2716	}
2718	2717
2719	2718	static void send_websocket_handshake(struct mg_connection *conn,
2720		const char *key) {
2721		static const char *magic = "258EAFA5-E914-47DA-95CA-C5AB0DC85B11";
2722		char buf[500], sha[20], b64_sha[sizeof(sha) * 2];
2723		SHA1_CTX sha_ctx;
	2719	const char *key) {
	2720	static const char *magic = "258EAFA5-E914-47DA-95CA-C5AB0DC85B11";
	2721	char buf[500], sha[20], b64_sha[sizeof(sha) * 2];
	2722	SHA1_CTX sha_ctx;
2724	2723
2725		mg_snprintf(buf, sizeof(buf), "%s%s", key, magic);
2726		SHA1Init(&sha_ctx);
2727		SHA1Update(&sha_ctx, (unsigned char *) buf, strlen(buf));
2728		SHA1Final((unsigned char *) sha, &sha_ctx);
2729		base64_encode((unsigned char *) sha, sizeof(sha), b64_sha);
2730		mg_snprintf(buf, sizeof(buf), "%s%s%s",
2731		"HTTP/1.1 101 Switching Protocols\r\n"
2732		"Upgrade: websocket\r\n"
2733		"Connection: Upgrade\r\n"
2734		"Sec-WebSocket-Accept: ", b64_sha, "\r\n\r\n");
	2724	mg_snprintf(buf, sizeof(buf), "%s%s", key, magic);
	2725	SHA1Init(&sha_ctx);
	2726	SHA1Update(&sha_ctx, (unsigned char *) buf, strlen(buf));
	2727	SHA1Final((unsigned char *) sha, &sha_ctx);
	2728	base64_encode((unsigned char *) sha, sizeof(sha), b64_sha);
	2729	mg_snprintf(buf, sizeof(buf), "%s%s%s",
	2730	"HTTP/1.1 101 Switching Protocols\r\n"
	2731	"Upgrade: websocket\r\n"
	2732	"Connection: Upgrade\r\n"
	2733	"Sec-WebSocket-Accept: ", b64_sha, "\r\n\r\n");
2735	2734
2736		mg_write(conn, buf, strlen(buf));
	2735	mg_write(conn, buf, strlen(buf));
2737	2736	}
2738	2737
2739	2738	static int deliver_websocket_frame(struct connection *conn) {
2740		// Having buf unsigned char * is important, as it is used below in arithmetic
2741		unsigned char buf = (unsigned char ) conn->ns_conn->recv_iobuf.buf;
2742		int i, len, buf_len = conn->ns_conn->recv_iobuf.len, frame_len = 0,
2743		mask_len = 0, header_len = 0, data_len = 0, buffered = 0;
	2739	// Having buf unsigned char * is important, as it is used below in arithmetic
	2740	unsigned char buf = (unsigned char ) conn->ns_conn->recv_iobuf.buf;
	2741	int i, len, buf_len = conn->ns_conn->recv_iobuf.len, frame_len = 0,
	2742	mask_len = 0, header_len = 0, data_len = 0, buffered = 0;
2744	2743
2745		if (buf_len >= 2) {
2746		len = buf[1] & 127;
2747		mask_len = buf[1] & 128 ? 4 : 0;
2748		if (len < 126 && buf_len >= mask_len) {
2749		data_len = len;
2750		header_len = 2 + mask_len;
2751		} else if (len == 126 && buf_len >= 4 + mask_len) {
2752		header_len = 4 + mask_len;
2753		data_len = ((((int) buf[2]) << 8) + buf[3]);
2754		} else if (buf_len >= 10 + mask_len) {
2755		header_len = 10 + mask_len;
2756		data_len = (int) (((uint64_t) htonl(* (uint32_t *) &buf[2])) << 32) +
2757		htonl(* (uint32_t *) &buf[6]);
2758		}
2759		}
	2744	if (buf_len >= 2) {
	2745	len = buf[1] & 127;
	2746	mask_len = buf[1] & 128 ? 4 : 0;
	2747	if (len < 126 && buf_len >= mask_len) {
	2748	data_len = len;
	2749	header_len = 2 + mask_len;
	2750	} else if (len == 126 && buf_len >= 4 + mask_len) {
	2751	header_len = 4 + mask_len;
	2752	data_len = ((((int) buf[2]) << 8) + buf[3]);
	2753	} else if (buf_len >= 10 + mask_len) {
	2754	header_len = 10 + mask_len;
	2755	data_len = (int) (((uint64_t) htonl(* (uint32_t *) &buf[2])) << 32) +
	2756	htonl(* (uint32_t *) &buf[6]);
	2757	}
	2758	}
2760	2759
2761		frame_len = header_len + data_len;
2762		buffered = frame_len > 0 && frame_len <= buf_len;
	2760	frame_len = header_len + data_len;
	2761	buffered = frame_len > 0 && frame_len <= buf_len;
2763	2762
2764		if (buffered) {
2765		conn->mg_conn.content_len = data_len;
2766		conn->mg_conn.content = (char *) buf + header_len;
2767		conn->mg_conn.wsbits = buf[0];
	2763	if (buffered) {
	2764	conn->mg_conn.content_len = data_len;
	2765	conn->mg_conn.content = (char *) buf + header_len;
	2766	conn->mg_conn.wsbits = buf[0];
2768	2767
2769		// Apply mask if necessary
2770		if (mask_len > 0) {
2771		for (i = 0; i < data_len; i++) {
2772		buf[i + header_len] ^= (buf + header_len - mask_len)[i % 4];
2773		}
2774		}
	2768	// Apply mask if necessary
	2769	if (mask_len > 0) {
	2770	for (i = 0; i < data_len; i++) {
	2771	buf[i + header_len] ^= (buf + header_len - mask_len)[i % 4];
	2772	}
	2773	}
2775	2774
2776		// Call the handler and remove frame from the iobuf
2777		if (call_user(conn, MG_REQUEST) == MG_FALSE) {
2778		conn->ns_conn->flags \|= NSF_FINISHED_SENDING_DATA;
2779		}
2780		iobuf_remove(&conn->ns_conn->recv_iobuf, frame_len);
2781		}
	2775	// Call the handler and remove frame from the iobuf
	2776	if (call_user(conn, MG_REQUEST) == MG_FALSE) {
	2777	conn->ns_conn->flags \|= NSF_FINISHED_SENDING_DATA;
	2778	}
	2779	iobuf_remove(&conn->ns_conn->recv_iobuf, frame_len);
	2780	}
2782	2781
2783		return buffered;
	2782	return buffered;
2784	2783	}
2785	2784
2786	2785	size_t mg_websocket_write(struct mg_connection *conn, int opcode,
2787		const char *data, size_t data_len) {
2788		unsigned char mem[4192], *copy = mem;
2789		size_t copy_len = 0;
	2786	const char *data, size_t data_len) {
	2787	unsigned char mem[4192], *copy = mem;
	2788	size_t copy_len = 0;
2790	2789
2791		if (data_len + 10 > sizeof(mem) &&
2792		(copy = (unsigned char *) malloc(data_len + 10)) == NULL) {
2793		return 0;
2794		}
	2790	if (data_len + 10 > sizeof(mem) &&
	2791	(copy = (unsigned char *) malloc(data_len + 10)) == NULL) {
	2792	return 0;
	2793	}
2795	2794
2796		copy[0] = 0x80 + (opcode & 0x0f);
	2795	copy[0] = 0x80 + (opcode & 0x0f);
2797	2796
2798		// Frame format: http://tools.ietf.org/html/rfc6455#section-5.2
2799		if (data_len < 126) {
2800		// Inline 7-bit length field
2801		copy[1] = data_len;
2802		memcpy(copy + 2, data, data_len);
2803		copy_len = 2 + data_len;
2804		} else if (data_len <= 0xFFFF) {
2805		// 16-bit length field
2806		copy[1] = 126;
2807		* (uint16_t *) (copy + 2) = (uint16_t) htons((uint16_t) data_len);
2808		memcpy(copy + 4, data, data_len);
2809		copy_len = 4 + data_len;
2810		} else {
2811		// 64-bit length field
2812		copy[1] = 127;
2813		* (uint32_t *) (copy + 2) = (uint32_t)
2814		htonl((uint32_t) ((uint64_t) data_len >> 32));
2815		* (uint32_t *) (copy + 6) = (uint32_t) htonl(data_len & 0xffffffff);
2816		memcpy(copy + 10, data, data_len);
2817		copy_len = 10 + data_len;
2818		}
	2797	// Frame format: http://tools.ietf.org/html/rfc6455#section-5.2
	2798	if (data_len < 126) {
	2799	// Inline 7-bit length field
	2800	copy[1] = data_len;
	2801	memcpy(copy + 2, data, data_len);
	2802	copy_len = 2 + data_len;
	2803	} else if (data_len <= 0xFFFF) {
	2804	// 16-bit length field
	2805	copy[1] = 126;
	2806	* (uint16_t *) (copy + 2) = (uint16_t) htons((uint16_t) data_len);
	2807	memcpy(copy + 4, data, data_len);
	2808	copy_len = 4 + data_len;
	2809	} else {
	2810	// 64-bit length field
	2811	copy[1] = 127;
	2812	* (uint32_t *) (copy + 2) = (uint32_t)
	2813	htonl((uint32_t) ((uint64_t) data_len >> 32));
	2814	* (uint32_t *) (copy + 6) = (uint32_t) htonl(data_len & 0xffffffff);
	2815	memcpy(copy + 10, data, data_len);
	2816	copy_len = 10 + data_len;
	2817	}
2819	2818
2820		if (copy_len > 0) {
2821		mg_write(conn, copy, copy_len);
2822		}
2823		if (copy != mem) {
2824		free(copy);
2825		}
	2819	if (copy_len > 0) {
	2820	mg_write(conn, copy, copy_len);
	2821	}
	2822	if (copy != mem) {
	2823	free(copy);
	2824	}
2826	2825
2827		// If we send closing frame, schedule a connection to be closed after
2828		// data is drained to the client.
2829		if (opcode == WEBSOCKET_OPCODE_CONNECTION_CLOSE) {
2830		MG_CONN_2_CONN(conn)->ns_conn->flags \|= NSF_FINISHED_SENDING_DATA;
2831		}
	2826	// If we send closing frame, schedule a connection to be closed after
	2827	// data is drained to the client.
	2828	if (opcode == WEBSOCKET_OPCODE_CONNECTION_CLOSE) {
	2829	MG_CONN_2_CONN(conn)->ns_conn->flags \|= NSF_FINISHED_SENDING_DATA;
	2830	}
2832	2831
2833		return MG_CONN_2_CONN(conn)->ns_conn->send_iobuf.len;
	2832	return MG_CONN_2_CONN(conn)->ns_conn->send_iobuf.len;
2834	2833	}
2835	2834
2836	2835	size_t mg_websocket_printf(struct mg_connection *conn, int opcode,
2837		const char *fmt, ...) {
2838		char mem[4192], *buf = mem;
2839		va_list ap;
2840		int len;
	2836	const char *fmt, ...) {
	2837	char mem[4192], *buf = mem;
	2838	va_list ap;
	2839	int len;
2841	2840
2842		va_start(ap, fmt);
2843		if ((len = ns_avprintf(&buf, sizeof(mem), fmt, ap)) > 0) {
2844		mg_websocket_write(conn, opcode, buf, len);
2845		}
2846		va_end(ap);
	2841	va_start(ap, fmt);
	2842	if ((len = ns_avprintf(&buf, sizeof(mem), fmt, ap)) > 0) {
	2843	mg_websocket_write(conn, opcode, buf, len);
	2844	}
	2845	va_end(ap);
2847	2846
2848		if (buf != mem && buf != NULL) {
2849		free(buf);
2850		}
	2847	if (buf != mem && buf != NULL) {
	2848	free(buf);
	2849	}
2851	2850
2852		return MG_CONN_2_CONN(conn)->ns_conn->send_iobuf.len;
	2851	return MG_CONN_2_CONN(conn)->ns_conn->send_iobuf.len;
2853	2852	}
2854	2853
2855	2854	static void send_websocket_handshake_if_requested(struct mg_connection *conn) {
2856		const char *ver = mg_get_header(conn, "Sec-WebSocket-Version"),
2857		*key = mg_get_header(conn, "Sec-WebSocket-Key");
2858		if (ver != NULL && key != NULL) {
2859		conn->is_websocket = 1;
2860		if (call_user(MG_CONN_2_CONN(conn), MG_WS_HANDSHAKE) == MG_FALSE) {
2861		send_websocket_handshake(conn, key);
2862		}
2863		call_user(MG_CONN_2_CONN(conn), MG_WS_CONNECT);
2864		}
	2855	const char *ver = mg_get_header(conn, "Sec-WebSocket-Version"),
	2856	*key = mg_get_header(conn, "Sec-WebSocket-Key");
	2857	if (ver != NULL && key != NULL) {
	2858	conn->is_websocket = 1;
	2859	if (call_user(MG_CONN_2_CONN(conn), MG_WS_HANDSHAKE) == MG_FALSE) {
	2860	send_websocket_handshake(conn, key);
	2861	}
	2862	call_user(MG_CONN_2_CONN(conn), MG_WS_CONNECT);
	2863	}
2865	2864	}
2866	2865
2867	2866	static void ping_idle_websocket_connection(struct connection *conn, time_t t) {
2868		if (t - conn->ns_conn->last_io_time > MONGOOSE_USE_WEBSOCKET_PING_INTERVAL) {
2869		mg_websocket_write(&conn->mg_conn, WEBSOCKET_OPCODE_PING, "", 0);
2870		}
	2867	if (t - conn->ns_conn->last_io_time > MONGOOSE_USE_WEBSOCKET_PING_INTERVAL) {
	2868	mg_websocket_write(&conn->mg_conn, WEBSOCKET_OPCODE_PING, "", 0);
	2869	}
2871	2870	}
2872	2871	#else
2873	2872	#define ping_idle_websocket_connection(conn, t)
2874	2873	#endif // !MONGOOSE_NO_WEBSOCKET
2875	2874
2876	2875	static void write_terminating_chunk(struct connection *conn) {
2877		mg_write(&conn->mg_conn, "0\r\n\r\n", 5);
	2876	mg_write(&conn->mg_conn, "0\r\n\r\n", 5);
2878	2877	}
2879	2878
2880	2879	static int call_request_handler(struct connection *conn) {
2881		int result;
2882		conn->mg_conn.content = conn->ns_conn->recv_iobuf.buf;
2883		if ((result = call_user(conn, MG_REQUEST)) == MG_TRUE) {
2884		if (conn->ns_conn->flags & MG_HEADERS_SENT) {
2885		write_terminating_chunk(conn);
2886		}
2887		close_local_endpoint(conn);
2888		}
2889		return result;
	2880	int result;
	2881	conn->mg_conn.content = conn->ns_conn->recv_iobuf.buf;
	2882	if ((result = call_user(conn, MG_REQUEST)) == MG_TRUE) {
	2883	if (conn->ns_conn->flags & MG_HEADERS_SENT) {
	2884	write_terminating_chunk(conn);
	2885	}
	2886	close_local_endpoint(conn);
	2887	}
	2888	return result;
2890	2889	}
2891	2890
2892	2891	const char mg_get_mime_type(const char path, const char *default_mime_type) {
2893		const char *ext;
2894		size_t i, path_len;
	2892	const char *ext;
	2893	size_t i, path_len;
2895	2894
2896		path_len = strlen(path);
	2895	path_len = strlen(path);
2897	2896
2898		for (i = 0; static_builtin_mime_types[i].extension != NULL; i++) {
2899		ext = path + (path_len - static_builtin_mime_types[i].ext_len);
2900		if (path_len > static_builtin_mime_types[i].ext_len &&
2901		mg_strcasecmp(ext, static_builtin_mime_types[i].extension) == 0) {
2902		return static_builtin_mime_types[i].mime_type;
2903		}
2904		}
	2897	for (i = 0; static_builtin_mime_types[i].extension != NULL; i++) {
	2898	ext = path + (path_len - static_builtin_mime_types[i].ext_len);
	2899	if (path_len > static_builtin_mime_types[i].ext_len &&
	2900	mg_strcasecmp(ext, static_builtin_mime_types[i].extension) == 0) {
	2901	return static_builtin_mime_types[i].mime_type;
	2902	}
	2903	}
2905	2904
2906		return default_mime_type;
	2905	return default_mime_type;
2907	2906	}
2908	2907
2909	2908	#ifndef MONGOOSE_NO_FILESYSTEM
2910	2909	// Convert month to the month number. Return -1 on error, or month number
2911	2910	static int get_month_index(const char *s) {
2912		static const char *month_names[] = {
2913		"Jan", "Feb", "Mar", "Apr", "May", "Jun",
2914		"Jul", "Aug", "Sep", "Oct", "Nov", "Dec"
2915		};
2916		int i;
	2911	static const char *month_names[] = {
	2912	"Jan", "Feb", "Mar", "Apr", "May", "Jun",
	2913	"Jul", "Aug", "Sep", "Oct", "Nov", "Dec"
	2914	};
	2915	int i;
2917	2916
2918		for (i = 0; i < (int) ARRAY_SIZE(month_names); i++)
2919		if (!strcmp(s, month_names[i]))
2920		return i;
	2917	for (i = 0; i < (int) ARRAY_SIZE(month_names); i++)
	2918	if (!strcmp(s, month_names[i]))
	2919	return i;
2921	2920
2922		return -1;
	2921	return -1;
2923	2922	}
2924	2923
2925	2924	static int num_leap_years(int year) {
2926		return year / 4 - year / 100 + year / 400;
	2925	return year / 4 - year / 100 + year / 400;
2927	2926	}
2928	2927
2929	2928	// Parse UTC date-time string, and return the corresponding time_t value.
2930	2929	static time_t parse_date_string(const char *datetime) {
2931		static const unsigned short days_before_month[] = {
2932		0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334
2933		};
2934		char month_str[32];
2935		int second, minute, hour, day, month, year, leap_days, days;
2936		time_t result = (time_t) 0;
	2930	static const unsigned short days_before_month[] = {
	2931	0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334
	2932	};
	2933	char month_str[32];
	2934	int second, minute, hour, day, month, year, leap_days, days;
	2935	time_t result = (time_t) 0;
2937	2936
2938		if (((sscanf(datetime, "%d/%3s/%d %d:%d:%d",
2939		&day, month_str, &year, &hour, &minute, &second) == 6) \|\|
2940		(sscanf(datetime, "%d %3s %d %d:%d:%d",
2941		&day, month_str, &year, &hour, &minute, &second) == 6) \|\|
2942		(sscanf(datetime, "%*3s, %d %3s %d %d:%d:%d",
2943		&day, month_str, &year, &hour, &minute, &second) == 6) \|\|
2944		(sscanf(datetime, "%d-%3s-%d %d:%d:%d",
2945		&day, month_str, &year, &hour, &minute, &second) == 6)) &&
2946		year > 1970 &&
2947		(month = get_month_index(month_str)) != -1) {
2948		leap_days = num_leap_years(year) - num_leap_years(1970);
2949		year -= 1970;
2950		days = year * 365 + days_before_month[month] + (day - 1) + leap_days;
2951		result = days * 24 * 3600 + hour * 3600 + minute * 60 + second;
2952		}
	2937	if (((sscanf(datetime, "%d/%3s/%d %d:%d:%d",
	2938	&day, month_str, &year, &hour, &minute, &second) == 6) \|\|
	2939	(sscanf(datetime, "%d %3s %d %d:%d:%d",
	2940	&day, month_str, &year, &hour, &minute, &second) == 6) \|\|
	2941	(sscanf(datetime, "%*3s, %d %3s %d %d:%d:%d",
	2942	&day, month_str, &year, &hour, &minute, &second) == 6) \|\|
	2943	(sscanf(datetime, "%d-%3s-%d %d:%d:%d",
	2944	&day, month_str, &year, &hour, &minute, &second) == 6)) &&
	2945	year > 1970 &&
	2946	(month = get_month_index(month_str)) != -1) {
	2947	leap_days = num_leap_years(year) - num_leap_years(1970);
	2948	year -= 1970;
	2949	days = year * 365 + days_before_month[month] + (day - 1) + leap_days;
	2950	result = days * 24 * 3600 + hour * 3600 + minute * 60 + second;
	2951	}
2953	2952
2954		return result;
	2953	return result;
2955	2954	}
2956	2955
2957	2956	// Look at the "path" extension and figure what mime type it has.
2958	2957	// Store mime type in the vector.
2959	2958	static void get_mime_type(const struct mg_server server, const char path,
2960		struct vec *vec) {
2961		struct vec ext_vec, mime_vec;
2962		const char list, ext;
2963		size_t path_len;
	2959	struct vec *vec) {
	2960	struct vec ext_vec, mime_vec;
	2961	const char list, ext;
	2962	size_t path_len;
2964	2963
2965		path_len = strlen(path);
	2964	path_len = strlen(path);
2966	2965
2967		// Scan user-defined mime types first, in case user wants to
2968		// override default mime types.
2969		list = server->config_options[EXTRA_MIME_TYPES];
2970		while ((list = next_option(list, &ext_vec, &mime_vec)) != NULL) {
2971		// ext now points to the path suffix
2972		ext = path + path_len - ext_vec.len;
2973		if (mg_strncasecmp(ext, ext_vec.ptr, ext_vec.len) == 0) {
2974		*vec = mime_vec;
2975		return;
2976		}
2977		}
	2966	// Scan user-defined mime types first, in case user wants to
	2967	// override default mime types.
	2968	list = server->config_options[EXTRA_MIME_TYPES];
	2969	while ((list = next_option(list, &ext_vec, &mime_vec)) != NULL) {
	2970	// ext now points to the path suffix
	2971	ext = path + path_len - ext_vec.len;
	2972	if (mg_strncasecmp(ext, ext_vec.ptr, ext_vec.len) == 0) {
	2973	*vec = mime_vec;
	2974	return;
	2975	}
	2976	}
2978	2977
2979		vec->ptr = mg_get_mime_type(path, "text/plain");
2980		vec->len = strlen(vec->ptr);
	2978	vec->ptr = mg_get_mime_type(path, "text/plain");
	2979	vec->len = strlen(vec->ptr);
2981	2980	}
2982	2981
2983	2982	static const char suggest_connection_header(const struct mg_connection conn) {
2984		return should_keep_alive(conn) ? "keep-alive" : "close";
	2983	return should_keep_alive(conn) ? "keep-alive" : "close";
2985	2984	}
2986	2985
2987	2986	static void construct_etag(char buf, size_t buf_len, const file_stat_t st) {
2988		mg_snprintf(buf, buf_len, "\"%lx.%" INT64_FMT "\"",
2989		(unsigned long) st->st_mtime, (int64_t) st->st_size);
	2987	mg_snprintf(buf, buf_len, "\"%lx.%" INT64_FMT "\"",
	2988	(unsigned long) st->st_mtime, (int64_t) st->st_size);
2990	2989	}
2991	2990
2992	2991	// Return True if we should reply 304 Not Modified.
2993	2992	static int is_not_modified(const struct connection *conn,
2994		const file_stat_t *stp) {
2995		char etag[64];
2996		const char *ims = mg_get_header(&conn->mg_conn, "If-Modified-Since");
2997		const char *inm = mg_get_header(&conn->mg_conn, "If-None-Match");
2998		construct_etag(etag, sizeof(etag), stp);
2999		return (inm != NULL && !mg_strcasecmp(etag, inm)) \|\|
3000		(ims != NULL && stp->st_mtime <= parse_date_string(ims));
	2993	const file_stat_t *stp) {
	2994	char etag[64];
	2995	const char *ims = mg_get_header(&conn->mg_conn, "If-Modified-Since");
	2996	const char *inm = mg_get_header(&conn->mg_conn, "If-None-Match");
	2997	construct_etag(etag, sizeof(etag), stp);
	2998	return (inm != NULL && !mg_strcasecmp(etag, inm)) \|\|
	2999	(ims != NULL && stp->st_mtime <= parse_date_string(ims));
3001	3000	}
3002	3001
3003	3002	// For given directory path, substitute it to valid index file.
3004	3003	// Return 0 if index file has been found, -1 if not found.
3005	3004	// If the file is found, it's stats is returned in stp.
3006	3005	static int find_index_file(struct connection conn, char path,
3007		size_t path_len, file_stat_t *stp) {
3008		const char *list = conn->server->config_options[INDEX_FILES];
3009		file_stat_t st;
3010		struct vec filename_vec;
3011		size_t n = strlen(path), found = 0;
	3006	size_t path_len, file_stat_t *stp) {
	3007	const char *list = conn->server->config_options[INDEX_FILES];
	3008	file_stat_t st;
	3009	struct vec filename_vec;
	3010	size_t n = strlen(path), found = 0;
3012	3011
3013		// The 'path' given to us points to the directory. Remove all trailing
3014		// directory separator characters from the end of the path, and
3015		// then append single directory separator character.
3016		while (n > 0 && path[n - 1] == '/') {
3017		n--;
3018		}
3019		path[n] = '/';
	3012	// The 'path' given to us points to the directory. Remove all trailing
	3013	// directory separator characters from the end of the path, and
	3014	// then append single directory separator character.
	3015	while (n > 0 && path[n - 1] == '/') {
	3016	n--;
	3017	}
	3018	path[n] = '/';
3020	3019
3021		// Traverse index files list. For each entry, append it to the given
3022		// path and see if the file exists. If it exists, break the loop
3023		while ((list = next_option(list, &filename_vec, NULL)) != NULL) {
	3020	// Traverse index files list. For each entry, append it to the given
	3021	// path and see if the file exists. If it exists, break the loop
	3022	while ((list = next_option(list, &filename_vec, NULL)) != NULL) {
	3023	// Ignore too long entries that may overflow path buffer
	3024	if (filename_vec.len > (int) (path_len - (n + 2)))
	3025	continue;
3024	3026
3025		// Ignore too long entries that may overflow path buffer
3026		if (filename_vec.len > (int) (path_len - (n + 2)))
3027		continue;
	3027	// Prepare full path to the index file
	3028	strncpy(path + n + 1, filename_vec.ptr, filename_vec.len);
	3029	path[n + 1 + filename_vec.len] = '\0';
3028	3030
3029		// Prepare full path to the index file
3030		strncpy(path + n + 1, filename_vec.ptr, filename_vec.len);
3031		path[n + 1 + filename_vec.len] = '\0';
	3031	//DBG(("[%s]", path));
3032	3032
3033		//DBG(("[%s]", path));
	3033	// Does it exist?
	3034	if (!stat(path, &st)) {
	3035	// Yes it does, break the loop
	3036	*stp = st;
	3037	found = 1;
	3038	break;
	3039	}
	3040	}
3034	3041
3035		// Does it exist?
3036		if (!stat(path, &st)) {
3037		// Yes it does, break the loop
3038		*stp = st;
3039		found = 1;
3040		break;
3041		}
3042		}
	3042	// If no index file exists, restore directory path
	3043	if (!found) {
	3044	path[n] = '\0';
	3045	}
3043	3046
3044		// If no index file exists, restore directory path
3045		if (!found) {
3046		path[n] = '\0';
3047		}
3048
3049		return found;
	3047	return found;
3050	3048	}
3051	3049
3052	3050	static int parse_range_header(const char header, int64_t a, int64_t *b) {
3053		return sscanf(header, "bytes=%" INT64_FMT "-%" INT64_FMT, a, b);
	3051	return sscanf(header, "bytes=%" INT64_FMT "-%" INT64_FMT, a, b);
3054	3052	}
3055	3053
3056	3054	static void gmt_time_string(char buf, size_t buf_len, time_t t) {
3057		strftime(buf, buf_len, "%a, %d %b %Y %H:%M:%S GMT", gmtime(t));
	3055	strftime(buf, buf_len, "%a, %d %b %Y %H:%M:%S GMT", gmtime(t));
3058	3056	}
3059	3057
3060	3058	static void open_file_endpoint(struct connection conn, const char path,
3061		file_stat_t *st) {
3062		char date[64], lm[64], etag[64], range[64], headers[500];
3063		const char msg = "OK", hdr;
3064		time_t curtime = time(NULL);
3065		int64_t r1, r2;
3066		struct vec mime_vec;
3067		int n;
	3059	file_stat_t *st) {
	3060	char date[64], lm[64], etag[64], range[64], headers[500];
	3061	const char msg = "OK", hdr;
	3062	time_t curtime = time(NULL);
	3063	int64_t r1, r2;
	3064	struct vec mime_vec;
	3065	int n;
3068	3066
3069		conn->endpoint_type = EP_FILE;
3070		ns_set_close_on_exec(conn->endpoint.fd);
3071		conn->mg_conn.status_code = 200;
	3067	conn->endpoint_type = EP_FILE;
	3068	ns_set_close_on_exec(conn->endpoint.fd);
	3069	conn->mg_conn.status_code = 200;
3072	3070
3073		get_mime_type(conn->server, path, &mime_vec);
3074		conn->cl = st->st_size;
3075		range[0] = '\0';
	3071	get_mime_type(conn->server, path, &mime_vec);
	3072	conn->cl = st->st_size;
	3073	range[0] = '\0';
3076	3074
3077		// If Range: header specified, act accordingly
3078		r1 = r2 = 0;
3079		hdr = mg_get_header(&conn->mg_conn, "Range");
3080		if (hdr != NULL && (n = parse_range_header(hdr, &r1, &r2)) > 0 &&
3081		r1 >= 0 && r2 >= 0) {
3082		conn->mg_conn.status_code = 206;
3083		conn->cl = n == 2 ? (r2 > conn->cl ? conn->cl : r2) - r1 + 1: conn->cl - r1;
3084		mg_snprintf(range, sizeof(range), "Content-Range: bytes "
3085		"%" INT64_FMT "-%" INT64_FMT "/%" INT64_FMT "\r\n",
3086		r1, r1 + conn->cl - 1, (int64_t) st->st_size);
3087		msg = "Partial Content";
3088		lseek(conn->endpoint.fd, r1, SEEK_SET);
3089		}
	3075	// If Range: header specified, act accordingly
	3076	r1 = r2 = 0;
	3077	hdr = mg_get_header(&conn->mg_conn, "Range");
	3078	if (hdr != NULL && (n = parse_range_header(hdr, &r1, &r2)) > 0 &&
	3079	r1 >= 0 && r2 >= 0) {
	3080	conn->mg_conn.status_code = 206;
	3081	conn->cl = n == 2 ? (r2 > conn->cl ? conn->cl : r2) - r1 + 1: conn->cl - r1;
	3082	mg_snprintf(range, sizeof(range), "Content-Range: bytes "
	3083	"%" INT64_FMT "-%" INT64_FMT "/%" INT64_FMT "\r\n",
	3084	r1, r1 + conn->cl - 1, (int64_t) st->st_size);
	3085	msg = "Partial Content";
	3086	lseek(conn->endpoint.fd, r1, SEEK_SET);
	3087	}
3090	3088
3091		// Prepare Etag, Date, Last-Modified headers. Must be in UTC, according to
3092		// http://www.w3.org/Protocols/rfc2616/rfc2616-sec3.html#sec3.3
3093		gmt_time_string(date, sizeof(date), &curtime);
3094		gmt_time_string(lm, sizeof(lm), &st->st_mtime);
3095		construct_etag(etag, sizeof(etag), st);
	3089	// Prepare Etag, Date, Last-Modified headers. Must be in UTC, according to
	3090	// http://www.w3.org/Protocols/rfc2616/rfc2616-sec3.html#sec3.3
	3091	gmt_time_string(date, sizeof(date), &curtime);
	3092	gmt_time_string(lm, sizeof(lm), &st->st_mtime);
	3093	construct_etag(etag, sizeof(etag), st);
3096	3094
3097		n = mg_snprintf(headers, sizeof(headers),
3098		"HTTP/1.1 %d %s\r\n"
3099		"Date: %s\r\n"
3100		"Last-Modified: %s\r\n"
3101		"Etag: %s\r\n"
3102		"Content-Type: %.*s\r\n"
3103		"Content-Length: %" INT64_FMT "\r\n"
3104		"Connection: %s\r\n"
3105		"Accept-Ranges: bytes\r\n"
3106		"%s%s\r\n",
3107		conn->mg_conn.status_code, msg, date, lm, etag,
3108		(int) mime_vec.len, mime_vec.ptr, conn->cl,
3109		suggest_connection_header(&conn->mg_conn),
3110		range, MONGOOSE_USE_EXTRA_HTTP_HEADERS);
3111		ns_send(conn->ns_conn, headers, n);
	3095	n = mg_snprintf(headers, sizeof(headers),
	3096	"HTTP/1.1 %d %s\r\n"
	3097	"Date: %s\r\n"
	3098	"Last-Modified: %s\r\n"
	3099	"Etag: %s\r\n"
	3100	"Content-Type: %.*s\r\n"
	3101	"Content-Length: %" INT64_FMT "\r\n"
	3102	"Connection: %s\r\n"
	3103	"Accept-Ranges: bytes\r\n"
	3104	"%s%s\r\n",
	3105	conn->mg_conn.status_code, msg, date, lm, etag,
	3106	(int) mime_vec.len, mime_vec.ptr, conn->cl,
	3107	suggest_connection_header(&conn->mg_conn),
	3108	range, MONGOOSE_USE_EXTRA_HTTP_HEADERS);
	3109	ns_send(conn->ns_conn, headers, n);
3112	3110
3113		if (!strcmp(conn->mg_conn.request_method, "HEAD")) {
3114		conn->ns_conn->flags \|= NSF_FINISHED_SENDING_DATA;
3115		close(conn->endpoint.fd);
3116		conn->endpoint_type = EP_NONE;
3117		}
	3111	if (!strcmp(conn->mg_conn.request_method, "HEAD")) {
	3112	conn->ns_conn->flags \|= NSF_FINISHED_SENDING_DATA;
	3113	close(conn->endpoint.fd);
	3114	conn->endpoint_type = EP_NONE;
	3115	}
3118	3116	}
3119	3117
3120	3118	void mg_send_file_data(struct mg_connection *c, int fd) {
3121		struct connection *conn = MG_CONN_2_CONN(c);
3122		conn->endpoint_type = EP_FILE;
3123		conn->endpoint.fd = fd;
3124		ns_set_close_on_exec(conn->endpoint.fd);
	3119	struct connection *conn = MG_CONN_2_CONN(c);
	3120	conn->endpoint_type = EP_FILE;
	3121	conn->endpoint.fd = fd;
	3122	ns_set_close_on_exec(conn->endpoint.fd);
3125	3123	}
3126	3124	#endif // MONGOOSE_NO_FILESYSTEM
3127	3125
3128	3126	static void call_request_handler_if_data_is_buffered(struct connection *conn) {
3129	3127	#ifndef MONGOOSE_NO_WEBSOCKET
3130		if (conn->mg_conn.is_websocket) {
3131		do { } while (deliver_websocket_frame(conn));
3132		} else
	3128	if (conn->mg_conn.is_websocket) {
	3129	do { } while (deliver_websocket_frame(conn));
	3130	} else
3133	3131	#endif
3134		if (conn->num_bytes_recv >= (conn->cl + conn->request_len) &&
3135		call_request_handler(conn) == MG_FALSE) {
3136		open_local_endpoint(conn, 1);
3137		}
	3132	if (conn->num_bytes_recv >= (conn->cl + conn->request_len) &&
	3133	call_request_handler(conn) == MG_FALSE) {
	3134	open_local_endpoint(conn, 1);
	3135	}
3138	3136	}
3139	3137
3140	3138	#if !defined(MONGOOSE_NO_DIRECTORY_LISTING) \|\| !defined(MONGOOSE_NO_DAV)
3141	3139
3142	3140	#ifdef _WIN32
3143	3141	struct dirent {
3144		char d_name[MAX_PATH_SIZE];
	3142	char d_name[MAX_PATH_SIZE];
3145	3143	};
3146	3144
3147	3145	typedef struct DIR {
3148		HANDLE handle;
3149		WIN32_FIND_DATAW info;
3150		struct dirent result;
	3146	HANDLE handle;
	3147	WIN32_FIND_DATAW info;
	3148	struct dirent result;
3151	3149	} DIR;
3152	3150
3153	3151	// Implementation of POSIX opendir/closedir/readdir for Windows.
3154	3152	static DIR opendir(const char name) {
3155		DIR *dir = NULL;
3156		wchar_t wpath[MAX_PATH_SIZE];
3157		DWORD attrs;
	3153	DIR *dir = NULL;
	3154	wchar_t wpath[MAX_PATH_SIZE];
	3155	DWORD attrs;
3158	3156
3159		if (name == NULL) {
3160		SetLastError(ERROR_BAD_ARGUMENTS);
3161		} else if ((dir = (DIR ) malloc(sizeof(dir))) == NULL) {
3162		SetLastError(ERROR_NOT_ENOUGH_MEMORY);
3163		} else {
3164		to_wchar(name, wpath, ARRAY_SIZE(wpath));
3165		attrs = GetFileAttributesW(wpath);
3166		if (attrs != 0xFFFFFFFF &&
3167		((attrs & FILE_ATTRIBUTE_DIRECTORY) == FILE_ATTRIBUTE_DIRECTORY)) {
3168		(void) wcscat(wpath, L"\\*");
3169		dir->handle = FindFirstFileW(wpath, &dir->info);
3170		dir->result.d_name[0] = '\0';
3171		} else {
3172		free(dir);
3173		dir = NULL;
3174		}
3175		}
	3157	if (name == NULL) {
	3158	SetLastError(ERROR_BAD_ARGUMENTS);
	3159	} else if ((dir = (DIR ) malloc(sizeof(dir))) == NULL) {
	3160	SetLastError(ERROR_NOT_ENOUGH_MEMORY);
	3161	} else {
	3162	to_wchar(name, wpath, ARRAY_SIZE(wpath));
	3163	attrs = GetFileAttributesW(wpath);
	3164	if (attrs != 0xFFFFFFFF &&
	3165	((attrs & FILE_ATTRIBUTE_DIRECTORY) == FILE_ATTRIBUTE_DIRECTORY)) {
	3166	(void) wcscat(wpath, L"\\*");
	3167	dir->handle = FindFirstFileW(wpath, &dir->info);
	3168	dir->result.d_name[0] = '\0';
	3169	} else {
	3170	free(dir);
	3171	dir = NULL;
	3172	}
	3173	}
3176	3174
3177		return dir;
	3175	return dir;
3178	3176	}
3179	3177
3180	3178	static int closedir(DIR *dir) {
3181		int result = 0;
	3179	int result = 0;
3182	3180
3183		if (dir != NULL) {
3184		if (dir->handle != INVALID_HANDLE_VALUE)
3185		result = FindClose(dir->handle) ? 0 : -1;
	3181	if (dir != NULL) {
	3182	if (dir->handle != INVALID_HANDLE_VALUE)
	3183	result = FindClose(dir->handle) ? 0 : -1;
3186	3184
3187		free(dir);
3188		} else {
3189		result = -1;
3190		SetLastError(ERROR_BAD_ARGUMENTS);
3191		}
	3185	free(dir);
	3186	} else {
	3187	result = -1;
	3188	SetLastError(ERROR_BAD_ARGUMENTS);
	3189	}
3192	3190
3193		return result;
	3191	return result;
3194	3192	}
3195	3193
3196	3194	static struct dirent readdir(DIR dir) {
3197		struct dirent *result = 0;
	3195	struct dirent *result = 0;
3198	3196
3199		if (dir) {
3200		if (dir->handle != INVALID_HANDLE_VALUE) {
3201		result = &dir->result;
3202		(void) WideCharToMultiByte(CP_UTF8, 0,
3203		dir->info.cFileName, -1, result->d_name,
3204		sizeof(result->d_name), NULL, NULL);
	3197	if (dir) {
	3198	if (dir->handle != INVALID_HANDLE_VALUE) {
	3199	result = &dir->result;
	3200	(void) WideCharToMultiByte(CP_UTF8, 0,
	3201	dir->info.cFileName, -1, result->d_name,
	3202	sizeof(result->d_name), NULL, NULL);
3205	3203
3206		if (!FindNextFileW(dir->handle, &dir->info)) {
3207		(void) FindClose(dir->handle);
3208		dir->handle = INVALID_HANDLE_VALUE;
3209		}
	3204	if (!FindNextFileW(dir->handle, &dir->info)) {
	3205	(void) FindClose(dir->handle);
	3206	dir->handle = INVALID_HANDLE_VALUE;
	3207	}
3210	3208
3211		} else {
3212		SetLastError(ERROR_FILE_NOT_FOUND);
3213		}
3214		} else {
3215		SetLastError(ERROR_BAD_ARGUMENTS);
3216		}
	3209	} else {
	3210	SetLastError(ERROR_FILE_NOT_FOUND);
	3211	}
	3212	} else {
	3213	SetLastError(ERROR_BAD_ARGUMENTS);
	3214	}
3217	3215
3218		return result;
	3216	return result;
3219	3217	}
3220	3218	#endif // _WIN32 POSIX opendir/closedir/readdir implementation
3221	3219
3222	3220	static int scan_directory(struct connection conn, const char dir,
3223		struct dir_entry **arr) {
3224		char path[MAX_PATH_SIZE];
3225		struct dir_entry *p;
3226		struct dirent *dp;
3227		int arr_size = 0, arr_ind = 0, inc = 100;
3228		DIR *dirp;
	3221	struct dir_entry **arr) {
	3222	char path[MAX_PATH_SIZE];
	3223	struct dir_entry *p;
	3224	struct dirent *dp;
	3225	int arr_size = 0, arr_ind = 0, inc = 100;
	3226	DIR *dirp;
3229	3227
3230		*arr = NULL;
3231		if ((dirp = (opendir(dir))) == NULL) return 0;
	3228	*arr = NULL;
	3229	if ((dirp = (opendir(dir))) == NULL) return 0;
3232	3230
3233		while ((dp = readdir(dirp)) != NULL) {
3234		// Do not show current dir and hidden files
3235		if (!strcmp(dp->d_name, ".") \|\|
3236		!strcmp(dp->d_name, "..") \|\|
3237		must_hide_file(conn, dp->d_name)) {
3238		continue;
3239		}
3240		mg_snprintf(path, sizeof(path), "%s%c%s", dir, '/', dp->d_name);
	3231	while ((dp = readdir(dirp)) != NULL) {
	3232	// Do not show current dir and hidden files
	3233	if (!strcmp(dp->d_name, ".") \|\|
	3234	!strcmp(dp->d_name, "..") \|\|
	3235	must_hide_file(conn, dp->d_name)) {
	3236	continue;
	3237	}
	3238	mg_snprintf(path, sizeof(path), "%s%c%s", dir, '/', dp->d_name);
3241	3239
3242		// Resize the array if nesessary
3243		if (arr_ind >= arr_size) {
3244		if ((p = (struct dir_entry *)
3245		realloc(arr, (inc + arr_size) sizeof(**arr))) != NULL) {
3246		// Memset new chunk to zero, otherwize st_mtime will have garbage which
3247		// can make strftime() segfault, see
3248		// http://code.google.com/p/mongoose/issues/detail?id=79
3249		memset(p + arr_size, 0, sizeof(*arr) inc);
	3240	// Resize the array if nesessary
	3241	if (arr_ind >= arr_size) {
	3242	if ((p = (struct dir_entry *)
	3243	realloc(arr, (inc + arr_size) sizeof(**arr))) != NULL) {
	3244	// Memset new chunk to zero, otherwize st_mtime will have garbage which
	3245	// can make strftime() segfault, see
	3246	// http://code.google.com/p/mongoose/issues/detail?id=79
	3247	memset(p + arr_size, 0, sizeof(*arr) inc);
3250	3248
3251		*arr = p;
3252		arr_size += inc;
3253		}
3254		}
	3249	*arr = p;
	3250	arr_size += inc;
	3251	}
	3252	}
3255	3253
3256		if (arr_ind < arr_size) {
3257		(*arr)[arr_ind].conn = conn;
3258		(*arr)[arr_ind].file_name = strdup(dp->d_name);
3259		stat(path, &(*arr)[arr_ind].st);
3260		arr_ind++;
3261		}
3262		}
3263		closedir(dirp);
	3254	if (arr_ind < arr_size) {
	3255	(*arr)[arr_ind].conn = conn;
	3256	(*arr)[arr_ind].file_name = strdup(dp->d_name);
	3257	stat(path, &(*arr)[arr_ind].st);
	3258	arr_ind++;
	3259	}
	3260	}
	3261	closedir(dirp);
3264	3262
3265		return arr_ind;
	3263	return arr_ind;
3266	3264	}
3267	3265
3268	3266	int mg_url_encode(const char src, size_t s_len, char dst, size_t dst_len) {
3269		static const char *dont_escape = "._-$,;~()";
3270		static const char *hex = "0123456789abcdef";
3271		size_t i = 0, j = 0;
	3267	static const char *dont_escape = "._-$,;~()";
	3268	static const char *hex = "0123456789abcdef";
	3269	size_t i = 0, j = 0;
3272	3270
3273		for (i = j = 0; dst_len > 0 && i < s_len && j + 2 < dst_len - 1; i++, j++) {
3274		if (isalnum(* (const unsigned char *) (src + i)) \|\|
3275		strchr(dont_escape, * (const unsigned char *) (src + i)) != NULL) {
3276		dst[j] = src[i];
3277		} else if (j + 3 < dst_len) {
3278		dst[j] = '%';
3279		dst[j + 1] = hex[(* (const unsigned char *) (src + i)) >> 4];
3280		dst[j + 2] = hex[(* (const unsigned char *) (src + i)) & 0xf];
3281		j += 2;
3282		}
3283		}
	3271	for (i = j = 0; dst_len > 0 && i < s_len && j + 2 < dst_len - 1; i++, j++) {
	3272	if (isalnum(* (const unsigned char *) (src + i)) \|\|
	3273	strchr(dont_escape, * (const unsigned char *) (src + i)) != NULL) {
	3274	dst[j] = src[i];
	3275	} else if (j + 3 < dst_len) {
	3276	dst[j] = '%';
	3277	dst[j + 1] = hex[(* (const unsigned char *) (src + i)) >> 4];
	3278	dst[j + 2] = hex[(* (const unsigned char *) (src + i)) & 0xf];
	3279	j += 2;
	3280	}
	3281	}
3284	3282
3285		dst[j] = '\0';
3286		return j;
	3283	dst[j] = '\0';
	3284	return j;
3287	3285	}
3288	3286	#endif // !NO_DIRECTORY_LISTING \|\| !MONGOOSE_NO_DAV
3289	3287
3290	3288	#ifndef MONGOOSE_NO_DIRECTORY_LISTING
3291	3289
3292	3290	static void print_dir_entry(const struct dir_entry *de) {
3293		char size[64], mod[64], href[MAX_PATH_SIZE * 3];
3294		int64_t fsize = de->st.st_size;
3295		int is_dir = S_ISDIR(de->st.st_mode);
3296		const char *slash = is_dir ? "/" : "";
	3291	char size[64], mod[64], href[MAX_PATH_SIZE * 3];
	3292	int64_t fsize = de->st.st_size;
	3293	int is_dir = S_ISDIR(de->st.st_mode);
	3294	const char *slash = is_dir ? "/" : "";
3297	3295
3298		if (is_dir) {
3299		mg_snprintf(size, sizeof(size), "%s", "[DIRECTORY]");
3300		} else {
3301		// We use (signed) cast below because MSVC 6 compiler cannot
3302		// convert unsigned __int64 to double.
3303		if (fsize < 1024) {
3304		mg_snprintf(size, sizeof(size), "%d", (int) fsize);
3305		} else if (fsize < 0x100000) {
3306		mg_snprintf(size, sizeof(size), "%.1fk", (double) fsize / 1024.0);
3307		} else if (fsize < 0x40000000) {
3308		mg_snprintf(size, sizeof(size), "%.1fM", (double) fsize / 1048576);
3309		} else {
3310		mg_snprintf(size, sizeof(size), "%.1fG", (double) fsize / 1073741824);
3311		}
3312		}
3313		strftime(mod, sizeof(mod), "%d-%b-%Y %H:%M", localtime(&de->st.st_mtime));
3314		mg_url_encode(de->file_name, strlen(de->file_name), href, sizeof(href));
3315		mg_printf_data(&de->conn->mg_conn,
3316		"<tr><td><a href=\"%s%s\">%s%s</a></td>"
3317		"<td> %s</td><td>  %s</td></tr>\n",
3318		href, slash, de->file_name, slash, mod, size);
	3296	if (is_dir) {
	3297	mg_snprintf(size, sizeof(size), "%s", "[DIRECTORY]");
	3298	} else {
	3299	// We use (signed) cast below because MSVC 6 compiler cannot
	3300	// convert unsigned __int64 to double.
	3301	if (fsize < 1024) {
	3302	mg_snprintf(size, sizeof(size), "%d", (int) fsize);
	3303	} else if (fsize < 0x100000) {
	3304	mg_snprintf(size, sizeof(size), "%.1fk", (double) fsize / 1024.0);
	3305	} else if (fsize < 0x40000000) {
	3306	mg_snprintf(size, sizeof(size), "%.1fM", (double) fsize / 1048576);
	3307	} else {
	3308	mg_snprintf(size, sizeof(size), "%.1fG", (double) fsize / 1073741824);
	3309	}
	3310	}
	3311	strftime(mod, sizeof(mod), "%d-%b-%Y %H:%M", localtime(&de->st.st_mtime));
	3312	mg_url_encode(de->file_name, strlen(de->file_name), href, sizeof(href));
	3313	mg_printf_data(&de->conn->mg_conn,
	3314	"<tr><td><a href=\"%s%s\">%s%s</a></td>"
	3315	"<td> %s</td><td>  %s</td></tr>\n",
	3316	href, slash, de->file_name, slash, mod, size);
3319	3317	}
3320	3318
3321	3319	// Sort directory entries by size, or name, or modification time.
3322	3320	// On windows, __cdecl specification is needed in case if project is built
3323	3321	// with __stdcall convention. qsort always requires __cdels callback.
3324	3322	static int __cdecl compare_dir_entries(const void p1, const void p2) {
3325		const struct dir_entry a = (const struct dir_entry ) p1,
3326		b = (const struct dir_entry ) p2;
3327		const char *qs = a->conn->mg_conn.query_string ?
3328		a->conn->mg_conn.query_string : "na";
3329		int cmp_result = 0;
	3323	const struct dir_entry a = (const struct dir_entry ) p1,
	3324	b = (const struct dir_entry ) p2;
	3325	const char *qs = a->conn->mg_conn.query_string ?
	3326	a->conn->mg_conn.query_string : "na";
	3327	int cmp_result = 0;
3330	3328
3331		if (S_ISDIR(a->st.st_mode) && !S_ISDIR(b->st.st_mode)) {
3332		return -1; // Always put directories on top
3333		} else if (!S_ISDIR(a->st.st_mode) && S_ISDIR(b->st.st_mode)) {
3334		return 1; // Always put directories on top
3335		} else if (*qs == 'n') {
3336		cmp_result = strcmp(a->file_name, b->file_name);
3337		} else if (*qs == 's') {
3338		cmp_result = a->st.st_size == b->st.st_size ? 0 :
3339		a->st.st_size > b->st.st_size ? 1 : -1;
3340		} else if (*qs == 'd') {
3341		cmp_result = a->st.st_mtime == b->st.st_mtime ? 0 :
3342		a->st.st_mtime > b->st.st_mtime ? 1 : -1;
3343		}
	3329	if (S_ISDIR(a->st.st_mode) && !S_ISDIR(b->st.st_mode)) {
	3330	return -1; // Always put directories on top
	3331	} else if (!S_ISDIR(a->st.st_mode) && S_ISDIR(b->st.st_mode)) {
	3332	return 1; // Always put directories on top
	3333	} else if (*qs == 'n') {
	3334	cmp_result = strcmp(a->file_name, b->file_name);
	3335	} else if (*qs == 's') {
	3336	cmp_result = a->st.st_size == b->st.st_size ? 0 :
	3337	a->st.st_size > b->st.st_size ? 1 : -1;
	3338	} else if (*qs == 'd') {
	3339	cmp_result = a->st.st_mtime == b->st.st_mtime ? 0 :
	3340	a->st.st_mtime > b->st.st_mtime ? 1 : -1;
	3341	}
3344	3342
3345		return qs[1] == 'd' ? -cmp_result : cmp_result;
	3343	return qs[1] == 'd' ? -cmp_result : cmp_result;
3346	3344	}
3347	3345
3348	3346	static void send_directory_listing(struct connection conn, const char dir) {
3349		struct dir_entry *arr = NULL;
3350		int i, num_entries, sort_direction = conn->mg_conn.query_string != NULL &&
3351		conn->mg_conn.query_string[1] == 'd' ? 'a' : 'd';
	3347	struct dir_entry *arr = NULL;
	3348	int i, num_entries, sort_direction = conn->mg_conn.query_string != NULL &&
	3349	conn->mg_conn.query_string[1] == 'd' ? 'a' : 'd';
3352	3350
3353		mg_send_header(&conn->mg_conn, "Transfer-Encoding", "chunked");
3354		mg_send_header(&conn->mg_conn, "Content-Type", "text/html; charset=utf-8");
	3351	mg_send_header(&conn->mg_conn, "Transfer-Encoding", "chunked");
	3352	mg_send_header(&conn->mg_conn, "Content-Type", "text/html; charset=utf-8");
3355	3353
3356		mg_printf_data(&conn->mg_conn,
3357		"<html><head><title>Index of %s</title>"
3358		"<style>th {text-align: left;}</style></head>"
3359		"<body><h1>Index of %s</h1><pre><table cellpadding=\"0\">"
3360		"<tr><th><a href=\"?n%c\">Name</a></th>"
3361		"<th><a href=\"?d%c\">Modified</a></th>"
3362		"<th><a href=\"?s%c\">Size</a></th></tr>"
3363		"<tr><td colspan=\"3\"><hr></td></tr>",
3364		conn->mg_conn.uri, conn->mg_conn.uri,
3365		sort_direction, sort_direction, sort_direction);
	3354	mg_printf_data(&conn->mg_conn,
	3355	"<html><head><title>Index of %s</title>"
	3356	"<style>th {text-align: left;}</style></head>"
	3357	"<body><h1>Index of %s</h1><pre><table cellpadding=\"0\">"
	3358	"<tr><th><a href=\"?n%c\">Name</a></th>"
	3359	"<th><a href=\"?d%c\">Modified</a></th>"
	3360	"<th><a href=\"?s%c\">Size</a></th></tr>"
	3361	"<tr><td colspan=\"3\"><hr></td></tr>",
	3362	conn->mg_conn.uri, conn->mg_conn.uri,
	3363	sort_direction, sort_direction, sort_direction);
3366	3364
3367		num_entries = scan_directory(conn, dir, &arr);
3368		qsort(arr, num_entries, sizeof(arr[0]), compare_dir_entries);
3369		for (i = 0; i < num_entries; i++) {
3370		print_dir_entry(&arr[i]);
3371		free(arr[i].file_name);
3372		}
3373		free(arr);
	3365	num_entries = scan_directory(conn, dir, &arr);
	3366	qsort(arr, num_entries, sizeof(arr[0]), compare_dir_entries);
	3367	for (i = 0; i < num_entries; i++) {
	3368	print_dir_entry(&arr[i]);
	3369	free(arr[i].file_name);
	3370	}
	3371	free(arr);
3374	3372
3375		write_terminating_chunk(conn);
3376		close_local_endpoint(conn);
	3373	write_terminating_chunk(conn);
	3374	close_local_endpoint(conn);
3377	3375	}
3378	3376	#endif // MONGOOSE_NO_DIRECTORY_LISTING
3379	3377
3380	3378	#ifndef MONGOOSE_NO_DAV
3381	3379	static void print_props(struct connection conn, const char uri,
3382		file_stat_t *stp) {
3383		char mtime[64];
	3380	file_stat_t *stp) {
	3381	char mtime[64];
3384	3382
3385		gmt_time_string(mtime, sizeof(mtime), &stp->st_mtime);
3386		mg_printf(&conn->mg_conn,
3387		"<d:response>"
3388		"<d:href>%s</d:href>"
3389		"<d:propstat>"
3390		"<d:prop>"
3391		"<d:resourcetype>%s</d:resourcetype>"
3392		"<d:getcontentlength>%" INT64_FMT "</d:getcontentlength>"
3393		"<d:getlastmodified>%s</d:getlastmodified>"
3394		"</d:prop>"
3395		"<d:status>HTTP/1.1 200 OK</d:status>"
3396		"</d:propstat>"
3397		"</d:response>\n",
3398		uri, S_ISDIR(stp->st_mode) ? "<d:collection/>" : "",
3399		(int64_t) stp->st_size, mtime);
	3383	gmt_time_string(mtime, sizeof(mtime), &stp->st_mtime);
	3384	mg_printf(&conn->mg_conn,
	3385	"<d:response>"
	3386	"<d:href>%s</d:href>"
	3387	"<d:propstat>"
	3388	"<d:prop>"
	3389	"<d:resourcetype>%s</d:resourcetype>"
	3390	"<d:getcontentlength>%" INT64_FMT "</d:getcontentlength>"
	3391	"<d:getlastmodified>%s</d:getlastmodified>"
	3392	"</d:prop>"
	3393	"<d:status>HTTP/1.1 200 OK</d:status>"
	3394	"</d:propstat>"
	3395	"</d:response>\n",
	3396	uri, S_ISDIR(stp->st_mode) ? "<d:collection/>" : "",
	3397	(int64_t) stp->st_size, mtime);
3400	3398	}
3401	3399
3402	3400	static void handle_propfind(struct connection conn, const char path,
3403		file_stat_t *stp, int exists) {
3404		static const char header[] = "HTTP/1.1 207 Multi-Status\r\n"
3405		"Connection: close\r\n"
3406		"Content-Type: text/xml; charset=utf-8\r\n\r\n"
3407		"<?xml version=\"1.0\" encoding=\"utf-8\"?>"
3408		"<d:multistatus xmlns:d='DAV:'>\n";
3409		static const char footer[] = "</d:multistatus>";
3410		const char *depth = mg_get_header(&conn->mg_conn, "Depth"),
3411		*list_dir = conn->server->config_options[ENABLE_DIRECTORY_LISTING];
	3401	file_stat_t *stp, int exists) {
	3402	static const char header[] = "HTTP/1.1 207 Multi-Status\r\n"
	3403	"Connection: close\r\n"
	3404	"Content-Type: text/xml; charset=utf-8\r\n\r\n"
	3405	"<?xml version=\"1.0\" encoding=\"utf-8\"?>"
	3406	"<d:multistatus xmlns:d='DAV:'>\n";
	3407	static const char footer[] = "</d:multistatus>";
	3408	const char *depth = mg_get_header(&conn->mg_conn, "Depth"),
	3409	*list_dir = conn->server->config_options[ENABLE_DIRECTORY_LISTING];
3412	3410
3413		conn->mg_conn.status_code = 207;
	3411	conn->mg_conn.status_code = 207;
3414	3412
3415		// Print properties for the requested resource itself
3416		if (!exists) {
3417		conn->mg_conn.status_code = 404;
3418		mg_printf(&conn->mg_conn, "%s", "HTTP/1.1 404 Not Found\r\n\r\n");
3419		} else if (S_ISDIR(stp->st_mode) && mg_strcasecmp(list_dir, "yes") != 0) {
3420		conn->mg_conn.status_code = 403;
3421		mg_printf(&conn->mg_conn, "%s",
3422		"HTTP/1.1 403 Directory Listing Denied\r\n\r\n");
3423		} else {
3424		ns_send(conn->ns_conn, header, sizeof(header) - 1);
3425		print_props(conn, conn->mg_conn.uri, stp);
	3413	// Print properties for the requested resource itself
	3414	if (!exists) {
	3415	conn->mg_conn.status_code = 404;
	3416	mg_printf(&conn->mg_conn, "%s", "HTTP/1.1 404 Not Found\r\n\r\n");
	3417	} else if (S_ISDIR(stp->st_mode) && mg_strcasecmp(list_dir, "yes") != 0) {
	3418	conn->mg_conn.status_code = 403;
	3419	mg_printf(&conn->mg_conn, "%s",
	3420	"HTTP/1.1 403 Directory Listing Denied\r\n\r\n");
	3421	} else {
	3422	ns_send(conn->ns_conn, header, sizeof(header) - 1);
	3423	print_props(conn, conn->mg_conn.uri, stp);
3426	3424
3427		if (S_ISDIR(stp->st_mode) &&
3428		(depth == NULL \|\| strcmp(depth, "0") != 0)) {
3429		struct dir_entry *arr = NULL;
3430		int i, num_entries = scan_directory(conn, path, &arr);
	3425	if (S_ISDIR(stp->st_mode) &&
	3426	(depth == NULL \|\| strcmp(depth, "0") != 0)) {
	3427	struct dir_entry *arr = NULL;
	3428	int i, num_entries = scan_directory(conn, path, &arr);
3431	3429
3432		for (i = 0; i < num_entries; i++) {
3433		char buf[MAX_PATH_SIZE * 3];
3434		struct dir_entry *de = &arr[i];
3435		mg_url_encode(de->file_name, strlen(de->file_name), buf, sizeof(buf));
3436		print_props(conn, buf, &de->st);
3437		free(de->file_name);
3438		}
3439		free(arr);
3440		}
3441		ns_send(conn->ns_conn, footer, sizeof(footer) - 1);
3442		}
	3430	for (i = 0; i < num_entries; i++) {
	3431	char buf[MAX_PATH_SIZE * 3];
	3432	struct dir_entry *de = &arr[i];
	3433	mg_url_encode(de->file_name, strlen(de->file_name), buf, sizeof(buf));
	3434	print_props(conn, buf, &de->st);
	3435	free(de->file_name);
	3436	}
	3437	free(arr);
	3438	}
	3439	ns_send(conn->ns_conn, footer, sizeof(footer) - 1);
	3440	}
3443	3441
3444		close_local_endpoint(conn);
	3442	close_local_endpoint(conn);
3445	3443	}
3446	3444
3447	3445	static void handle_mkcol(struct connection conn, const char path) {
3448		int status_code = 500;
	3446	int status_code = 500;
3449	3447
3450		if (conn->mg_conn.content_len > 0) {
3451		status_code = 415;
3452		} else if (!mkdir(path, 0755)) {
3453		status_code = 201;
3454		} else if (errno == EEXIST) {
3455		status_code = 405;
3456		} else if (errno == EACCES) {
3457		status_code = 403;
3458		} else if (errno == ENOENT) {
3459		status_code = 409;
3460		}
3461		send_http_error(conn, status_code, NULL);
	3448	if (conn->mg_conn.content_len > 0) {
	3449	status_code = 415;
	3450	} else if (!mkdir(path, 0755)) {
	3451	status_code = 201;
	3452	} else if (errno == EEXIST) {
	3453	status_code = 405;
	3454	} else if (errno == EACCES) {
	3455	status_code = 403;
	3456	} else if (errno == ENOENT) {
	3457	status_code = 409;
	3458	}
	3459	send_http_error(conn, status_code, NULL);
3462	3460	}
3463	3461
3464	3462	static int remove_directory(const char *dir) {
3465		char path[MAX_PATH_SIZE];
3466		struct dirent *dp;
3467		file_stat_t st;
3468		DIR *dirp;
	3463	char path[MAX_PATH_SIZE];
	3464	struct dirent *dp;
	3465	file_stat_t st;
	3466	DIR *dirp;
3469	3467
3470		if ((dirp = opendir(dir)) == NULL) return 0;
	3468	if ((dirp = opendir(dir)) == NULL) return 0;
3471	3469
3472		while ((dp = readdir(dirp)) != NULL) {
3473		if (!strcmp(dp->d_name, ".") \|\| !strcmp(dp->d_name, "..")) continue;
3474		mg_snprintf(path, sizeof(path), "%s%c%s", dir, '/', dp->d_name);
3475		stat(path, &st);
3476		if (S_ISDIR(st.st_mode)) {
3477		remove_directory(path);
3478		} else {
3479		remove(path);
3480		}
3481		}
3482		closedir(dirp);
3483		rmdir(dir);
	3470	while ((dp = readdir(dirp)) != NULL) {
	3471	if (!strcmp(dp->d_name, ".") \|\| !strcmp(dp->d_name, "..")) continue;
	3472	mg_snprintf(path, sizeof(path), "%s%c%s", dir, '/', dp->d_name);
	3473	stat(path, &st);
	3474	if (S_ISDIR(st.st_mode)) {
	3475	remove_directory(path);
	3476	} else {
	3477	remove(path);
	3478	}
	3479	}
	3480	closedir(dirp);
	3481	rmdir(dir);
3484	3482
3485		return 1;
	3483	return 1;
3486	3484	}
3487	3485
3488	3486	static void handle_delete(struct connection conn, const char path) {
3489		file_stat_t st;
	3487	file_stat_t st;
3490	3488
3491		if (stat(path, &st) != 0) {
3492		send_http_error(conn, 404, NULL);
3493		} else if (S_ISDIR(st.st_mode)) {
3494		remove_directory(path);
3495		send_http_error(conn, 204, NULL);
3496		} else if (remove(path) == 0) {
3497		send_http_error(conn, 204, NULL);
3498		} else {
3499		send_http_error(conn, 423, NULL);
3500		}
	3489	if (stat(path, &st) != 0) {
	3490	send_http_error(conn, 404, NULL);
	3491	} else if (S_ISDIR(st.st_mode)) {
	3492	remove_directory(path);
	3493	send_http_error(conn, 204, NULL);
	3494	} else if (remove(path) == 0) {
	3495	send_http_error(conn, 204, NULL);
	3496	} else {
	3497	send_http_error(conn, 423, NULL);
	3498	}
3501	3499	}
3502	3500
3503	3501	// For a given PUT path, create all intermediate subdirectories
3504	3502	// for given path. Return 0 if the path itself is a directory,
3505	3503	// or -1 on error, 1 if OK.
3506	3504	static int put_dir(const char *path) {
3507		char buf[MAX_PATH_SIZE];
3508		const char s, p;
3509		file_stat_t st;
	3505	char buf[MAX_PATH_SIZE];
	3506	const char s, p;
	3507	file_stat_t st;
3510	3508
3511		// Create intermediate directories if they do not exist
3512		for (s = p = path + 1; (p = strchr(s, '/')) != NULL; s = ++p) {
3513		if (p - path >= (int) sizeof(buf)) return -1; // Buffer overflow
3514		memcpy(buf, path, p - path);
3515		buf[p - path] = '\0';
3516		if (stat(buf, &st) != 0 && mkdir(buf, 0755) != 0) return -1;
3517		if (p[1] == '\0') return 0; // Path is a directory itself
3518		}
	3509	// Create intermediate directories if they do not exist
	3510	for (s = p = path + 1; (p = strchr(s, '/')) != NULL; s = ++p) {
	3511	if (p - path >= (int) sizeof(buf)) return -1; // Buffer overflow
	3512	memcpy(buf, path, p - path);
	3513	buf[p - path] = '\0';
	3514	if (stat(buf, &st) != 0 && mkdir(buf, 0755) != 0) return -1;
	3515	if (p[1] == '\0') return 0; // Path is a directory itself
	3516	}
3519	3517
3520		return 1;
	3518	return 1;
3521	3519	}
3522	3520
3523	3521	static void handle_put(struct connection conn, const char path) {
3524		file_stat_t st;
3525		const char range, cl_hdr = mg_get_header(&conn->mg_conn, "Content-Length");
3526		int64_t r1, r2;
3527		int rc;
	3522	file_stat_t st;
	3523	const char range, cl_hdr = mg_get_header(&conn->mg_conn, "Content-Length");
	3524	int64_t r1, r2;
	3525	int rc;
3528	3526
3529		conn->mg_conn.status_code = !stat(path, &st) ? 200 : 201;
3530		if ((rc = put_dir(path)) == 0) {
3531		mg_printf(&conn->mg_conn, "HTTP/1.1 %d OK\r\n\r\n",
3532		conn->mg_conn.status_code);
3533		close_local_endpoint(conn);
3534		} else if (rc == -1) {
3535		send_http_error(conn, 500, "put_dir: %s", strerror(errno));
3536		} else if (cl_hdr == NULL) {
3537		send_http_error(conn, 411, NULL);
	3527	conn->mg_conn.status_code = !stat(path, &st) ? 200 : 201;
	3528	if ((rc = put_dir(path)) == 0) {
	3529	mg_printf(&conn->mg_conn, "HTTP/1.1 %d OK\r\n\r\n",
	3530	conn->mg_conn.status_code);
	3531	close_local_endpoint(conn);
	3532	} else if (rc == -1) {
	3533	send_http_error(conn, 500, "put_dir: %s", strerror(errno));
	3534	} else if (cl_hdr == NULL) {
	3535	send_http_error(conn, 411, NULL);
3538	3536	#ifdef _WIN32
3539		//On Windows, open() is a macro with 2 params
3540		} else if ((conn->endpoint.fd =
3541		open(path, O_RDWR \| O_CREAT \| O_TRUNC)) < 0) {
	3537	//On Windows, open() is a macro with 2 params
	3538	} else if ((conn->endpoint.fd =
	3539	open(path, O_RDWR \| O_CREAT \| O_TRUNC)) < 0) {
3542	3540	#else
3543		} else if ((conn->endpoint.fd =
3544		open(path, O_RDWR \| O_CREAT \| O_TRUNC, 0644)) < 0) {
	3541	} else if ((conn->endpoint.fd =
	3542	open(path, O_RDWR \| O_CREAT \| O_TRUNC, 0644)) < 0) {
3545	3543	#endif
3546		send_http_error(conn, 500, "open(%s): %s", path, strerror(errno));
3547		} else {
3548		DBG(("PUT [%s] %lu", path, (unsigned long) conn->ns_conn->recv_iobuf.len));
3549		conn->endpoint_type = EP_PUT;
3550		ns_set_close_on_exec(conn->endpoint.fd);
3551		range = mg_get_header(&conn->mg_conn, "Content-Range");
3552		conn->cl = to64(cl_hdr);
3553		r1 = r2 = 0;
3554		if (range != NULL && parse_range_header(range, &r1, &r2) > 0) {
3555		conn->mg_conn.status_code = 206;
3556		lseek(conn->endpoint.fd, r1, SEEK_SET);
3557		conn->cl = r2 > r1 ? r2 - r1 + 1: conn->cl - r1;
3558		}
3559		mg_printf(&conn->mg_conn, "HTTP/1.1 %d OK\r\nContent-Length: 0\r\n\r\n",
3560		conn->mg_conn.status_code);
3561		}
	3544	send_http_error(conn, 500, "open(%s): %s", path, strerror(errno));
	3545	} else {
	3546	DBG(("PUT [%s] %lu", path, (unsigned long) conn->ns_conn->recv_iobuf.len));
	3547	conn->endpoint_type = EP_PUT;
	3548	ns_set_close_on_exec(conn->endpoint.fd);
	3549	range = mg_get_header(&conn->mg_conn, "Content-Range");
	3550	conn->cl = to64(cl_hdr);
	3551	r1 = r2 = 0;
	3552	if (range != NULL && parse_range_header(range, &r1, &r2) > 0) {
	3553	conn->mg_conn.status_code = 206;
	3554	lseek(conn->endpoint.fd, r1, SEEK_SET);
	3555	conn->cl = r2 > r1 ? r2 - r1 + 1: conn->cl - r1;
	3556	}
	3557	mg_printf(&conn->mg_conn, "HTTP/1.1 %d OK\r\nContent-Length: 0\r\n\r\n",
	3558	conn->mg_conn.status_code);
	3559	}
3562	3560	}
3563	3561
3564	3562	static void forward_put_data(struct connection *conn) {
3565		struct iobuf *io = &conn->ns_conn->recv_iobuf;
3566		size_t k = conn->cl < (int64_t) io->len ? conn->cl : (int64_t) io->len; // To write
3567		int n = write(conn->endpoint.fd, io->buf, k); // Write them!
3568		if (n > 0) {
3569		iobuf_remove(io, n);
3570		conn->cl -= n;
3571		}
3572		if (conn->cl <= 0) {
3573		close_local_endpoint(conn);
3574		}
	3563	struct iobuf *io = &conn->ns_conn->recv_iobuf;
	3564	size_t k = conn->cl < (int64_t) io->len ? conn->cl : (int64_t) io->len; // To write
	3565	int n = write(conn->endpoint.fd, io->buf, k); // Write them!
	3566	if (n > 0) {
	3567	iobuf_remove(io, n);
	3568	conn->cl -= n;
	3569	}
	3570	if (conn->cl <= 0) {
	3571	close_local_endpoint(conn);
	3572	}
3575	3573	}
3576	3574	#endif // MONGOOSE_NO_DAV
3577	3575
3578	3576	static void send_options(struct connection *conn) {
3579		conn->mg_conn.status_code = 200;
3580		mg_printf(&conn->mg_conn, "%s",
3581		"HTTP/1.1 200 OK\r\nAllow: GET, POST, HEAD, CONNECT, PUT, "
3582		"DELETE, OPTIONS, PROPFIND, MKCOL\r\nDAV: 1\r\n\r\n");
3583		close_local_endpoint(conn);
	3577	conn->mg_conn.status_code = 200;
	3578	mg_printf(&conn->mg_conn, "%s",
	3579	"HTTP/1.1 200 OK\r\nAllow: GET, POST, HEAD, CONNECT, PUT, "
	3580	"DELETE, OPTIONS, PROPFIND, MKCOL\r\nDAV: 1\r\n\r\n");
	3581	close_local_endpoint(conn);
3584	3582	}
3585	3583
3586	3584	#ifndef MONGOOSE_NO_AUTH
3587	3585	void mg_send_digest_auth_request(struct mg_connection *c) {
3588		struct connection *conn = MG_CONN_2_CONN(c);
3589		c->status_code = 401;
3590		mg_printf(c,
3591		"HTTP/1.1 401 Unauthorized\r\n"
3592		"WWW-Authenticate: Digest qop=\"auth\", "
3593		"realm=\"%s\", nonce=\"%lu\"\r\n\r\n",
3594		conn->server->config_options[AUTH_DOMAIN],
3595		(unsigned long) time(NULL));
3596		close_local_endpoint(conn);
	3586	struct connection *conn = MG_CONN_2_CONN(c);
	3587	c->status_code = 401;
	3588	mg_printf(c,
	3589	"HTTP/1.1 401 Unauthorized\r\n"
	3590	"WWW-Authenticate: Digest qop=\"auth\", "
	3591	"realm=\"%s\", nonce=\"%lu\"\r\n\r\n",
	3592	conn->server->config_options[AUTH_DOMAIN],
	3593	(unsigned long) time(NULL));
	3594	close_local_endpoint(conn);
3597	3595	}
3598	3596
3599	3597	// Use the global passwords file, if specified by auth_gpass option,
3600	3598	// or search for .htpasswd in the requested directory.
3601	3599	static FILE open_auth_file(struct connection conn, const char *path,
3602		int is_directory) {
3603		char name[MAX_PATH_SIZE];
3604		const char p, gpass = conn->server->config_options[GLOBAL_AUTH_FILE];
3605		FILE *fp = NULL;
	3600	int is_directory) {
	3601	char name[MAX_PATH_SIZE];
	3602	const char p, gpass = conn->server->config_options[GLOBAL_AUTH_FILE];
	3603	FILE *fp = NULL;
3606	3604
3607		if (gpass != NULL) {
3608		// Use global passwords file
3609		fp = fopen(gpass, "r");
3610		} else if (is_directory) {
3611		mg_snprintf(name, sizeof(name), "%s%c%s", path, '/', PASSWORDS_FILE_NAME);
3612		fp = fopen(name, "r");
3613		} else {
3614		// Try to find .htpasswd in requested directory.
3615		if ((p = strrchr(path, '/')) == NULL) p = path;
3616		mg_snprintf(name, sizeof(name), "%.*s%c%s",
3617		(int) (p - path), path, '/', PASSWORDS_FILE_NAME);
3618		fp = fopen(name, "r");
3619		}
	3605	if (gpass != NULL) {
	3606	// Use global passwords file
	3607	fp = fopen(gpass, "r");
	3608	} else if (is_directory) {
	3609	mg_snprintf(name, sizeof(name), "%s%c%s", path, '/', PASSWORDS_FILE_NAME);
	3610	fp = fopen(name, "r");
	3611	} else {
	3612	// Try to find .htpasswd in requested directory.
	3613	if ((p = strrchr(path, '/')) == NULL) p = path;
	3614	mg_snprintf(name, sizeof(name), "%.*s%c%s",
	3615	(int) (p - path), path, '/', PASSWORDS_FILE_NAME);
	3616	fp = fopen(name, "r");
	3617	}
3620	3618
3621		return fp;
	3619	return fp;
3622	3620	}
3623	3621
3624	3622	#if !defined(HAVE_MD5) && !defined(MONGOOSE_NO_AUTH)
3625	3623	typedef struct MD5Context {
3626		uint32_t buf[4];
3627		uint32_t bits[2];
3628		unsigned char in[64];
	3624	uint32_t buf[4];
	3625	uint32_t bits[2];
	3626	unsigned char in[64];
3629	3627	} MD5_CTX;
3630	3628
3631	3629	static void byteReverse(unsigned char *buf, unsigned longs) {
3632		uint32_t t;
	3630	uint32_t t;
3633	3631
3634		// Forrest: MD5 expect LITTLE_ENDIAN, swap if BIG_ENDIAN
3635		if (is_big_endian()) {
3636		do {
3637		t = (uint32_t) ((unsigned) buf[3] << 8 \| buf[2]) << 16 \|
3638		((unsigned) buf[1] << 8 \| buf[0]);
3639		* (uint32_t *) buf = t;
3640		buf += 4;
3641		} while (--longs);
3642		}
	3632	// Forrest: MD5 expect LITTLE_ENDIAN, swap if BIG_ENDIAN
	3633	if (is_big_endian()) {
	3634	do {
	3635	t = (uint32_t) ((unsigned) buf[3] << 8 \| buf[2]) << 16 \|
	3636	((unsigned) buf[1] << 8 \| buf[0]);
	3637	* (uint32_t *) buf = t;
	3638	buf += 4;
	3639	} while (--longs);
	3640	}
3643	3641	}
3644	3642
3645	3643	#define F1(x, y, z) (z ^ (x & (y ^ z)))
r32760	r32761
3648	3646	#define F4(x, y, z) (y ^ (x \| ~z))
3649	3647
3650	3648	#define MD5STEP(f, w, x, y, z, data, s) \
3651		( w += f(x, y, z) + data, w = w<<s \| w>>(32-s), w += x )
	3649	( w += f(x, y, z) + data, w = w<<s \| w>>(32-s), w += x )
3652	3650
3653	3651	// Start MD5 accumulation. Set bit count to 0 and buffer to mysterious
3654	3652	// initialization constants.
3655	3653	static void MD5Init(MD5_CTX *ctx) {
3656		ctx->buf[0] = 0x67452301;
3657		ctx->buf[1] = 0xefcdab89;
3658		ctx->buf[2] = 0x98badcfe;
3659		ctx->buf[3] = 0x10325476;
	3654	ctx->buf[0] = 0x67452301;
	3655	ctx->buf[1] = 0xefcdab89;
	3656	ctx->buf[2] = 0x98badcfe;
	3657	ctx->buf[3] = 0x10325476;
3660	3658
3661		ctx->bits[0] = 0;
3662		ctx->bits[1] = 0;
	3659	ctx->bits[0] = 0;
	3660	ctx->bits[1] = 0;
3663	3661	}
3664	3662
3665	3663	static void MD5Transform(uint32_t buf[4], uint32_t const in[16]) {
3666		register uint32_t a, b, c, d;
	3664	register uint32_t a, b, c, d;
3667	3665
3668		a = buf[0];
3669		b = buf[1];
3670		c = buf[2];
3671		d = buf[3];
	3666	a = buf[0];
	3667	b = buf[1];
	3668	c = buf[2];
	3669	d = buf[3];
3672	3670
3673		MD5STEP(F1, a, b, c, d, in[0] + 0xd76aa478, 7);
3674		MD5STEP(F1, d, a, b, c, in[1] + 0xe8c7b756, 12);
3675		MD5STEP(F1, c, d, a, b, in[2] + 0x242070db, 17);
3676		MD5STEP(F1, b, c, d, a, in[3] + 0xc1bdceee, 22);
3677		MD5STEP(F1, a, b, c, d, in[4] + 0xf57c0faf, 7);
3678		MD5STEP(F1, d, a, b, c, in[5] + 0x4787c62a, 12);
3679		MD5STEP(F1, c, d, a, b, in[6] + 0xa8304613, 17);
3680		MD5STEP(F1, b, c, d, a, in[7] + 0xfd469501, 22);
3681		MD5STEP(F1, a, b, c, d, in[8] + 0x698098d8, 7);
3682		MD5STEP(F1, d, a, b, c, in[9] + 0x8b44f7af, 12);
3683		MD5STEP(F1, c, d, a, b, in[10] + 0xffff5bb1, 17);
3684		MD5STEP(F1, b, c, d, a, in[11] + 0x895cd7be, 22);
3685		MD5STEP(F1, a, b, c, d, in[12] + 0x6b901122, 7);
3686		MD5STEP(F1, d, a, b, c, in[13] + 0xfd987193, 12);
3687		MD5STEP(F1, c, d, a, b, in[14] + 0xa679438e, 17);
3688		MD5STEP(F1, b, c, d, a, in[15] + 0x49b40821, 22);
	3671	MD5STEP(F1, a, b, c, d, in[0] + 0xd76aa478, 7);
	3672	MD5STEP(F1, d, a, b, c, in[1] + 0xe8c7b756, 12);
	3673	MD5STEP(F1, c, d, a, b, in[2] + 0x242070db, 17);
	3674	MD5STEP(F1, b, c, d, a, in[3] + 0xc1bdceee, 22);
	3675	MD5STEP(F1, a, b, c, d, in[4] + 0xf57c0faf, 7);
	3676	MD5STEP(F1, d, a, b, c, in[5] + 0x4787c62a, 12);
	3677	MD5STEP(F1, c, d, a, b, in[6] + 0xa8304613, 17);
	3678	MD5STEP(F1, b, c, d, a, in[7] + 0xfd469501, 22);
	3679	MD5STEP(F1, a, b, c, d, in[8] + 0x698098d8, 7);
	3680	MD5STEP(F1, d, a, b, c, in[9] + 0x8b44f7af, 12);
	3681	MD5STEP(F1, c, d, a, b, in[10] + 0xffff5bb1, 17);
	3682	MD5STEP(F1, b, c, d, a, in[11] + 0x895cd7be, 22);
	3683	MD5STEP(F1, a, b, c, d, in[12] + 0x6b901122, 7);
	3684	MD5STEP(F1, d, a, b, c, in[13] + 0xfd987193, 12);
	3685	MD5STEP(F1, c, d, a, b, in[14] + 0xa679438e, 17);
	3686	MD5STEP(F1, b, c, d, a, in[15] + 0x49b40821, 22);
3689	3687
3690		MD5STEP(F2, a, b, c, d, in[1] + 0xf61e2562, 5);
3691		MD5STEP(F2, d, a, b, c, in[6] + 0xc040b340, 9);
3692		MD5STEP(F2, c, d, a, b, in[11] + 0x265e5a51, 14);
3693		MD5STEP(F2, b, c, d, a, in[0] + 0xe9b6c7aa, 20);
3694		MD5STEP(F2, a, b, c, d, in[5] + 0xd62f105d, 5);
3695		MD5STEP(F2, d, a, b, c, in[10] + 0x02441453, 9);
3696		MD5STEP(F2, c, d, a, b, in[15] + 0xd8a1e681, 14);
3697		MD5STEP(F2, b, c, d, a, in[4] + 0xe7d3fbc8, 20);
3698		MD5STEP(F2, a, b, c, d, in[9] + 0x21e1cde6, 5);
3699		MD5STEP(F2, d, a, b, c, in[14] + 0xc33707d6, 9);
3700		MD5STEP(F2, c, d, a, b, in[3] + 0xf4d50d87, 14);
3701		MD5STEP(F2, b, c, d, a, in[8] + 0x455a14ed, 20);
3702		MD5STEP(F2, a, b, c, d, in[13] + 0xa9e3e905, 5);
3703		MD5STEP(F2, d, a, b, c, in[2] + 0xfcefa3f8, 9);
3704		MD5STEP(F2, c, d, a, b, in[7] + 0x676f02d9, 14);
3705		MD5STEP(F2, b, c, d, a, in[12] + 0x8d2a4c8a, 20);
	3688	MD5STEP(F2, a, b, c, d, in[1] + 0xf61e2562, 5);
	3689	MD5STEP(F2, d, a, b, c, in[6] + 0xc040b340, 9);
	3690	MD5STEP(F2, c, d, a, b, in[11] + 0x265e5a51, 14);
	3691	MD5STEP(F2, b, c, d, a, in[0] + 0xe9b6c7aa, 20);
	3692	MD5STEP(F2, a, b, c, d, in[5] + 0xd62f105d, 5);
	3693	MD5STEP(F2, d, a, b, c, in[10] + 0x02441453, 9);
	3694	MD5STEP(F2, c, d, a, b, in[15] + 0xd8a1e681, 14);
	3695	MD5STEP(F2, b, c, d, a, in[4] + 0xe7d3fbc8, 20);
	3696	MD5STEP(F2, a, b, c, d, in[9] + 0x21e1cde6, 5);
	3697	MD5STEP(F2, d, a, b, c, in[14] + 0xc33707d6, 9);
	3698	MD5STEP(F2, c, d, a, b, in[3] + 0xf4d50d87, 14);
	3699	MD5STEP(F2, b, c, d, a, in[8] + 0x455a14ed, 20);
	3700	MD5STEP(F2, a, b, c, d, in[13] + 0xa9e3e905, 5);
	3701	MD5STEP(F2, d, a, b, c, in[2] + 0xfcefa3f8, 9);
	3702	MD5STEP(F2, c, d, a, b, in[7] + 0x676f02d9, 14);
	3703	MD5STEP(F2, b, c, d, a, in[12] + 0x8d2a4c8a, 20);
3706	3704
3707		MD5STEP(F3, a, b, c, d, in[5] + 0xfffa3942, 4);
3708		MD5STEP(F3, d, a, b, c, in[8] + 0x8771f681, 11);
3709		MD5STEP(F3, c, d, a, b, in[11] + 0x6d9d6122, 16);
3710		MD5STEP(F3, b, c, d, a, in[14] + 0xfde5380c, 23);
3711		MD5STEP(F3, a, b, c, d, in[1] + 0xa4beea44, 4);
3712		MD5STEP(F3, d, a, b, c, in[4] + 0x4bdecfa9, 11);
3713		MD5STEP(F3, c, d, a, b, in[7] + 0xf6bb4b60, 16);
3714		MD5STEP(F3, b, c, d, a, in[10] + 0xbebfbc70, 23);
3715		MD5STEP(F3, a, b, c, d, in[13] + 0x289b7ec6, 4);
3716		MD5STEP(F3, d, a, b, c, in[0] + 0xeaa127fa, 11);
3717		MD5STEP(F3, c, d, a, b, in[3] + 0xd4ef3085, 16);
3718		MD5STEP(F3, b, c, d, a, in[6] + 0x04881d05, 23);
3719		MD5STEP(F3, a, b, c, d, in[9] + 0xd9d4d039, 4);
3720		MD5STEP(F3, d, a, b, c, in[12] + 0xe6db99e5, 11);
3721		MD5STEP(F3, c, d, a, b, in[15] + 0x1fa27cf8, 16);
3722		MD5STEP(F3, b, c, d, a, in[2] + 0xc4ac5665, 23);
	3705	MD5STEP(F3, a, b, c, d, in[5] + 0xfffa3942, 4);
	3706	MD5STEP(F3, d, a, b, c, in[8] + 0x8771f681, 11);
	3707	MD5STEP(F3, c, d, a, b, in[11] + 0x6d9d6122, 16);
	3708	MD5STEP(F3, b, c, d, a, in[14] + 0xfde5380c, 23);
	3709	MD5STEP(F3, a, b, c, d, in[1] + 0xa4beea44, 4);
	3710	MD5STEP(F3, d, a, b, c, in[4] + 0x4bdecfa9, 11);
	3711	MD5STEP(F3, c, d, a, b, in[7] + 0xf6bb4b60, 16);
	3712	MD5STEP(F3, b, c, d, a, in[10] + 0xbebfbc70, 23);
	3713	MD5STEP(F3, a, b, c, d, in[13] + 0x289b7ec6, 4);
	3714	MD5STEP(F3, d, a, b, c, in[0] + 0xeaa127fa, 11);
	3715	MD5STEP(F3, c, d, a, b, in[3] + 0xd4ef3085, 16);
	3716	MD5STEP(F3, b, c, d, a, in[6] + 0x04881d05, 23);
	3717	MD5STEP(F3, a, b, c, d, in[9] + 0xd9d4d039, 4);
	3718	MD5STEP(F3, d, a, b, c, in[12] + 0xe6db99e5, 11);
	3719	MD5STEP(F3, c, d, a, b, in[15] + 0x1fa27cf8, 16);
	3720	MD5STEP(F3, b, c, d, a, in[2] + 0xc4ac5665, 23);
3723	3721
3724		MD5STEP(F4, a, b, c, d, in[0] + 0xf4292244, 6);
3725		MD5STEP(F4, d, a, b, c, in[7] + 0x432aff97, 10);
3726		MD5STEP(F4, c, d, a, b, in[14] + 0xab9423a7, 15);
3727		MD5STEP(F4, b, c, d, a, in[5] + 0xfc93a039, 21);
3728		MD5STEP(F4, a, b, c, d, in[12] + 0x655b59c3, 6);
3729		MD5STEP(F4, d, a, b, c, in[3] + 0x8f0ccc92, 10);
3730		MD5STEP(F4, c, d, a, b, in[10] + 0xffeff47d, 15);
3731		MD5STEP(F4, b, c, d, a, in[1] + 0x85845dd1, 21);
3732		MD5STEP(F4, a, b, c, d, in[8] + 0x6fa87e4f, 6);
3733		MD5STEP(F4, d, a, b, c, in[15] + 0xfe2ce6e0, 10);
3734		MD5STEP(F4, c, d, a, b, in[6] + 0xa3014314, 15);
3735		MD5STEP(F4, b, c, d, a, in[13] + 0x4e0811a1, 21);
3736		MD5STEP(F4, a, b, c, d, in[4] + 0xf7537e82, 6);
3737		MD5STEP(F4, d, a, b, c, in[11] + 0xbd3af235, 10);
3738		MD5STEP(F4, c, d, a, b, in[2] + 0x2ad7d2bb, 15);
3739		MD5STEP(F4, b, c, d, a, in[9] + 0xeb86d391, 21);
	3722	MD5STEP(F4, a, b, c, d, in[0] + 0xf4292244, 6);
	3723	MD5STEP(F4, d, a, b, c, in[7] + 0x432aff97, 10);
	3724	MD5STEP(F4, c, d, a, b, in[14] + 0xab9423a7, 15);
	3725	MD5STEP(F4, b, c, d, a, in[5] + 0xfc93a039, 21);
	3726	MD5STEP(F4, a, b, c, d, in[12] + 0x655b59c3, 6);
	3727	MD5STEP(F4, d, a, b, c, in[3] + 0x8f0ccc92, 10);
	3728	MD5STEP(F4, c, d, a, b, in[10] + 0xffeff47d, 15);
	3729	MD5STEP(F4, b, c, d, a, in[1] + 0x85845dd1, 21);
	3730	MD5STEP(F4, a, b, c, d, in[8] + 0x6fa87e4f, 6);
	3731	MD5STEP(F4, d, a, b, c, in[15] + 0xfe2ce6e0, 10);
	3732	MD5STEP(F4, c, d, a, b, in[6] + 0xa3014314, 15);
	3733	MD5STEP(F4, b, c, d, a, in[13] + 0x4e0811a1, 21);
	3734	MD5STEP(F4, a, b, c, d, in[4] + 0xf7537e82, 6);
	3735	MD5STEP(F4, d, a, b, c, in[11] + 0xbd3af235, 10);
	3736	MD5STEP(F4, c, d, a, b, in[2] + 0x2ad7d2bb, 15);
	3737	MD5STEP(F4, b, c, d, a, in[9] + 0xeb86d391, 21);
3740	3738
3741		buf[0] += a;
3742		buf[1] += b;
3743		buf[2] += c;
3744		buf[3] += d;
	3739	buf[0] += a;
	3740	buf[1] += b;
	3741	buf[2] += c;
	3742	buf[3] += d;
3745	3743	}
3746	3744
3747	3745	static void MD5Update(MD5_CTX ctx, unsigned char const buf, unsigned len) {
3748		uint32_t t;
	3746	uint32_t t;
3749	3747
3750		t = ctx->bits[0];
3751		if ((ctx->bits[0] = t + ((uint32_t) len << 3)) < t)
3752		ctx->bits[1]++;
3753		ctx->bits[1] += len >> 29;
	3748	t = ctx->bits[0];
	3749	if ((ctx->bits[0] = t + ((uint32_t) len << 3)) < t)
	3750	ctx->bits[1]++;
	3751	ctx->bits[1] += len >> 29;
3754	3752
3755		t = (t >> 3) & 0x3f;
	3753	t = (t >> 3) & 0x3f;
3756	3754
3757		if (t) {
3758		unsigned char p = (unsigned char ) ctx->in + t;
	3755	if (t) {
	3756	unsigned char p = (unsigned char ) ctx->in + t;
3759	3757
3760		t = 64 - t;
3761		if (len < t) {
3762		memcpy(p, buf, len);
3763		return;
3764		}
3765		memcpy(p, buf, t);
3766		byteReverse(ctx->in, 16);
3767		MD5Transform(ctx->buf, (uint32_t *) ctx->in);
3768		buf += t;
3769		len -= t;
3770		}
	3758	t = 64 - t;
	3759	if (len < t) {
	3760	memcpy(p, buf, len);
	3761	return;
	3762	}
	3763	memcpy(p, buf, t);
	3764	byteReverse(ctx->in, 16);
	3765	MD5Transform(ctx->buf, (uint32_t *) ctx->in);
	3766	buf += t;
	3767	len -= t;
	3768	}
3771	3769
3772		while (len >= 64) {
3773		memcpy(ctx->in, buf, 64);
3774		byteReverse(ctx->in, 16);
3775		MD5Transform(ctx->buf, (uint32_t *) ctx->in);
3776		buf += 64;
3777		len -= 64;
3778		}
	3770	while (len >= 64) {
	3771	memcpy(ctx->in, buf, 64);
	3772	byteReverse(ctx->in, 16);
	3773	MD5Transform(ctx->buf, (uint32_t *) ctx->in);
	3774	buf += 64;
	3775	len -= 64;
	3776	}
3779	3777
3780		memcpy(ctx->in, buf, len);
	3778	memcpy(ctx->in, buf, len);
3781	3779	}
3782	3780
3783	3781	static void MD5Final(unsigned char digest[16], MD5_CTX *ctx) {
3784		unsigned count;
3785		unsigned char *p;
3786		uint32_t *a;
	3782	unsigned count;
	3783	unsigned char *p;
	3784	uint32_t *a;
3787	3785
3788		count = (ctx->bits[0] >> 3) & 0x3F;
	3786	count = (ctx->bits[0] >> 3) & 0x3F;
3789	3787
3790		p = ctx->in + count;
3791		*p++ = 0x80;
3792		count = 64 - 1 - count;
3793		if (count < 8) {
3794		memset(p, 0, count);
3795		byteReverse(ctx->in, 16);
3796		MD5Transform(ctx->buf, (uint32_t *) ctx->in);
3797		memset(ctx->in, 0, 56);
3798		} else {
3799		memset(p, 0, count - 8);
3800		}
3801		byteReverse(ctx->in, 14);
	3788	p = ctx->in + count;
	3789	*p++ = 0x80;
	3790	count = 64 - 1 - count;
	3791	if (count < 8) {
	3792	memset(p, 0, count);
	3793	byteReverse(ctx->in, 16);
	3794	MD5Transform(ctx->buf, (uint32_t *) ctx->in);
	3795	memset(ctx->in, 0, 56);
	3796	} else {
	3797	memset(p, 0, count - 8);
	3798	}
	3799	byteReverse(ctx->in, 14);
3802	3800
3803		a = (uint32_t *)ctx->in;
3804		a[14] = ctx->bits[0];
3805		a[15] = ctx->bits[1];
	3801	a = (uint32_t *)ctx->in;
	3802	a[14] = ctx->bits[0];
	3803	a[15] = ctx->bits[1];
3806	3804
3807		MD5Transform(ctx->buf, (uint32_t *) ctx->in);
3808		byteReverse((unsigned char *) ctx->buf, 4);
3809		memcpy(digest, ctx->buf, 16);
3810		memset((char ) ctx, 0, sizeof(ctx));
	3805	MD5Transform(ctx->buf, (uint32_t *) ctx->in);
	3806	byteReverse((unsigned char *) ctx->buf, 4);
	3807	memcpy(digest, ctx->buf, 16);
	3808	memset((char ) ctx, 0, sizeof(ctx));
3811	3809	}
3812	3810	#endif // !HAVE_MD5
3813	3811
r32760	r32761
3816	3814	// Stringify binary data. Output buffer must be twice as big as input,
3817	3815	// because each byte takes 2 bytes in string representation
3818	3816	static void bin2str(char to, const unsigned char p, size_t len) {
3819		static const char *hex = "0123456789abcdef";
	3817	static const char *hex = "0123456789abcdef";
3820	3818
3821		for (; len--; p++) {
3822		*to++ = hex[p[0] >> 4];
3823		*to++ = hex[p[0] & 0x0f];
3824		}
3825		*to = '\0';
	3819	for (; len--; p++) {
	3820	*to++ = hex[p[0] >> 4];
	3821	*to++ = hex[p[0] & 0x0f];
	3822	}
	3823	*to = '\0';
3826	3824	}
3827	3825
3828	3826	// Return stringified MD5 hash for list of strings. Buffer must be 33 bytes.
3829	3827	char *mg_md5(char buf[33], ...) {
3830		unsigned char hash[16];
3831		const char *p;
3832		va_list ap;
3833		MD5_CTX ctx;
	3828	unsigned char hash[16];
	3829	const char *p;
	3830	va_list ap;
	3831	MD5_CTX ctx;
3834	3832
3835		MD5Init(&ctx);
	3833	MD5Init(&ctx);
3836	3834
3837		va_start(ap, buf);
3838		while ((p = va_arg(ap, const char *)) != NULL) {
3839		MD5Update(&ctx, (const unsigned char *) p, (unsigned) strlen(p));
3840		}
3841		va_end(ap);
	3835	va_start(ap, buf);
	3836	while ((p = va_arg(ap, const char *)) != NULL) {
	3837	MD5Update(&ctx, (const unsigned char *) p, (unsigned) strlen(p));
	3838	}
	3839	va_end(ap);
3842	3840
3843		MD5Final(hash, &ctx);
3844		bin2str(buf, hash, sizeof(hash));
3845		return buf;
	3841	MD5Final(hash, &ctx);
	3842	bin2str(buf, hash, sizeof(hash));
	3843	return buf;
3846	3844	}
3847	3845
3848	3846	// Check the user's password, return 1 if OK
3849	3847	static int check_password(const char method, const char ha1, const char *uri,
3850		const char nonce, const char nc, const char *cnonce,
3851		const char qop, const char response) {
3852		char ha2[32 + 1], expected_response[32 + 1];
	3848	const char nonce, const char nc, const char *cnonce,
	3849	const char qop, const char response) {
	3850	char ha2[32 + 1], expected_response[32 + 1];
3853	3851
3854	3852	#if 0
3855		// Check for authentication timeout
3856		if ((unsigned long) time(NULL) - (unsigned long) to64(nonce) > 3600 * 2) {
3857		return 0;
3858		}
	3853	// Check for authentication timeout
	3854	if ((unsigned long) time(NULL) - (unsigned long) to64(nonce) > 3600 * 2) {
	3855	return 0;
	3856	}
3859	3857	#endif
3860	3858
3861		mg_md5(ha2, method, ":", uri, NULL);
3862		mg_md5(expected_response, ha1, ":", nonce, ":", nc,
3863		":", cnonce, ":", qop, ":", ha2, NULL);
	3859	mg_md5(ha2, method, ":", uri, NULL);
	3860	mg_md5(expected_response, ha1, ":", nonce, ":", nc,
	3861	":", cnonce, ":", qop, ":", ha2, NULL);
3864	3862
3865		return mg_strcasecmp(response, expected_response) == 0 ? MG_TRUE : MG_FALSE;
	3863	return mg_strcasecmp(response, expected_response) == 0 ? MG_TRUE : MG_FALSE;
3866	3864	}
3867	3865
3868	3866
3869	3867	// Authorize against the opened passwords file. Return 1 if authorized.
3870	3868	int mg_authorize_digest(struct mg_connection c, FILE fp) {
3871		struct connection *conn = MG_CONN_2_CONN(c);
3872		const char *hdr;
3873		char line[256], f_user[256], ha1[256], f_domain[256], user[100], nonce[100],
3874		uri[MAX_REQUEST_SIZE], cnonce[100], resp[100], qop[100], nc[100];
	3869	struct connection *conn = MG_CONN_2_CONN(c);
	3870	const char *hdr;
	3871	char line[256], f_user[256], ha1[256], f_domain[256], user[100], nonce[100],
	3872	uri[MAX_REQUEST_SIZE], cnonce[100], resp[100], qop[100], nc[100];
3875	3873
3876		if (c == NULL \|\| fp == NULL) return 0;
3877		if ((hdr = mg_get_header(c, "Authorization")) == NULL \|\|
3878		mg_strncasecmp(hdr, "Digest ", 7) != 0) return 0;
3879		if (!mg_parse_header(hdr, "username", user, sizeof(user))) return 0;
3880		if (!mg_parse_header(hdr, "cnonce", cnonce, sizeof(cnonce))) return 0;
3881		if (!mg_parse_header(hdr, "response", resp, sizeof(resp))) return 0;
3882		if (!mg_parse_header(hdr, "uri", uri, sizeof(uri))) return 0;
3883		if (!mg_parse_header(hdr, "qop", qop, sizeof(qop))) return 0;
3884		if (!mg_parse_header(hdr, "nc", nc, sizeof(nc))) return 0;
3885		if (!mg_parse_header(hdr, "nonce", nonce, sizeof(nonce))) return 0;
	3874	if (c == NULL \|\| fp == NULL) return 0;
	3875	if ((hdr = mg_get_header(c, "Authorization")) == NULL \|\|
	3876	mg_strncasecmp(hdr, "Digest ", 7) != 0) return 0;
	3877	if (!mg_parse_header(hdr, "username", user, sizeof(user))) return 0;
	3878	if (!mg_parse_header(hdr, "cnonce", cnonce, sizeof(cnonce))) return 0;
	3879	if (!mg_parse_header(hdr, "response", resp, sizeof(resp))) return 0;
	3880	if (!mg_parse_header(hdr, "uri", uri, sizeof(uri))) return 0;
	3881	if (!mg_parse_header(hdr, "qop", qop, sizeof(qop))) return 0;
	3882	if (!mg_parse_header(hdr, "nc", nc, sizeof(nc))) return 0;
	3883	if (!mg_parse_header(hdr, "nonce", nonce, sizeof(nonce))) return 0;
3886	3884
3887		while (fgets(line, sizeof(line), fp) != NULL) {
3888		if (sscanf(line, "%[^:]:%[^:]:%s", f_user, f_domain, ha1) == 3 &&
3889		!strcmp(user, f_user) &&
3890		// NOTE(lsm): due to a bug in MSIE, we do not compare URIs
3891		!strcmp(conn->server->config_options[AUTH_DOMAIN], f_domain))
3892		return check_password(c->request_method, ha1, uri,
3893		nonce, nc, cnonce, qop, resp);
3894		}
3895		return MG_FALSE;
	3885	while (fgets(line, sizeof(line), fp) != NULL) {
	3886	if (sscanf(line, "%[^:]:%[^:]:%s", f_user, f_domain, ha1) == 3 &&
	3887	!strcmp(user, f_user) &&
	3888	// NOTE(lsm): due to a bug in MSIE, we do not compare URIs
	3889	!strcmp(conn->server->config_options[AUTH_DOMAIN], f_domain))
	3890	return check_password(c->request_method, ha1, uri,
	3891	nonce, nc, cnonce, qop, resp);
	3892	}
	3893	return MG_FALSE;
3896	3894	}
3897	3895
3898	3896
3899	3897	// Return 1 if request is authorised, 0 otherwise.
3900	3898	static int is_authorized(struct connection conn, const char path,
3901		int is_directory) {
3902		FILE *fp;
3903		int authorized = MG_TRUE;
	3899	int is_directory) {
	3900	FILE *fp;
	3901	int authorized = MG_TRUE;
3904	3902
3905		if ((fp = open_auth_file(conn, path, is_directory)) != NULL) {
3906		authorized = mg_authorize_digest(&conn->mg_conn, fp);
3907		fclose(fp);
3908		}
	3903	if ((fp = open_auth_file(conn, path, is_directory)) != NULL) {
	3904	authorized = mg_authorize_digest(&conn->mg_conn, fp);
	3905	fclose(fp);
	3906	}
3909	3907
3910		return authorized;
	3908	return authorized;
3911	3909	}
3912	3910
3913	3911	static int is_authorized_for_dav(struct connection *conn) {
3914		const char *auth_file = conn->server->config_options[DAV_AUTH_FILE];
3915		const char *method = conn->mg_conn.request_method;
3916		FILE *fp;
3917		int authorized = MG_FALSE;
	3912	const char *auth_file = conn->server->config_options[DAV_AUTH_FILE];
	3913	const char *method = conn->mg_conn.request_method;
	3914	FILE *fp;
	3915	int authorized = MG_FALSE;
3918	3916
3919		// If dav_auth_file is not set, allow non-authorized PROPFIND
3920		if (method != NULL && !strcmp(method, "PROPFIND") && auth_file == NULL) {
3921		authorized = MG_TRUE;
3922		} else if (auth_file != NULL && (fp = fopen(auth_file, "r")) != NULL) {
3923		authorized = mg_authorize_digest(&conn->mg_conn, fp);
3924		fclose(fp);
3925		}
	3917	// If dav_auth_file is not set, allow non-authorized PROPFIND
	3918	if (method != NULL && !strcmp(method, "PROPFIND") && auth_file == NULL) {
	3919	authorized = MG_TRUE;
	3920	} else if (auth_file != NULL && (fp = fopen(auth_file, "r")) != NULL) {
	3921	authorized = mg_authorize_digest(&conn->mg_conn, fp);
	3922	fclose(fp);
	3923	}
3926	3924
3927		return authorized;
	3925	return authorized;
3928	3926	}
3929	3927
3930	3928	static int is_dav_request(const struct connection *conn) {
3931		const char *s = conn->mg_conn.request_method;
3932		return !strcmp(s, "PUT") \|\| !strcmp(s, "DELETE") \|\|
3933		!strcmp(s, "MKCOL") \|\| !strcmp(s, "PROPFIND");
	3929	const char *s = conn->mg_conn.request_method;
	3930	return !strcmp(s, "PUT") \|\| !strcmp(s, "DELETE") \|\|
	3931	!strcmp(s, "MKCOL") \|\| !strcmp(s, "PROPFIND");
3934	3932	}
3935	3933	#endif // MONGOOSE_NO_AUTH
3936	3934
3937	3935	static int parse_header(const char str, int str_len, const char var_name,
3938		char *buf, size_t buf_size) {
3939		int ch = ' ', len = 0, n = strlen(var_name);
3940		const char p, end = str + str_len, *s = NULL;
	3936	char *buf, size_t buf_size) {
	3937	int ch = ' ', len = 0, n = strlen(var_name);
	3938	const char p, end = str + str_len, *s = NULL;
3941	3939
3942		if (buf != NULL && buf_size > 0) buf[0] = '\0';
	3940	if (buf != NULL && buf_size > 0) buf[0] = '\0';
3943	3941
3944		// Find where variable starts
3945		for (s = str; s != NULL && s + n < end; s++) {
3946		if ((s == str \|\| s[-1] == ' ' \|\| s[-1] == ',') && s[n] == '=' &&
3947		!memcmp(s, var_name, n)) break;
3948		}
	3942	// Find where variable starts
	3943	for (s = str; s != NULL && s + n < end; s++) {
	3944	if ((s == str \|\| s[-1] == ' ' \|\| s[-1] == ',') && s[n] == '=' &&
	3945	!memcmp(s, var_name, n)) break;
	3946	}
3949	3947
3950		if (s != NULL && &s[n + 1] < end) {
3951		s += n + 1;
3952		if (s == '"' \|\| s == '\'') ch = *s++;
3953		p = s;
3954		while (p < end && p[0] != ch && p[0] != ',' && len < (int) buf_size) {
3955		if (p[0] == '\\' && p[1] == ch) p++;
3956		buf[len++] = *p++;
3957		}
3958		if (len >= (int) buf_size \|\| (ch != ' ' && *p != ch)) {
3959		len = 0;
3960		} else {
3961		if (len > 0 && s[len - 1] == ',') len--;
3962		if (len > 0 && s[len - 1] == ';') len--;
3963		buf[len] = '\0';
3964		}
3965		}
	3948	if (s != NULL && &s[n + 1] < end) {
	3949	s += n + 1;
	3950	if (s == '"' \|\| s == '\'') ch = *s++;
	3951	p = s;
	3952	while (p < end && p[0] != ch && p[0] != ',' && len < (int) buf_size) {
	3953	if (p[0] == '\\' && p[1] == ch) p++;
	3954	buf[len++] = *p++;
	3955	}
	3956	if (len >= (int) buf_size \|\| (ch != ' ' && *p != ch)) {
	3957	len = 0;
	3958	} else {
	3959	if (len > 0 && s[len - 1] == ',') len--;
	3960	if (len > 0 && s[len - 1] == ';') len--;
	3961	buf[len] = '\0';
	3962	}
	3963	}
3966	3964
3967		return len;
	3965	return len;
3968	3966	}
3969	3967
3970	3968	int mg_parse_header(const char s, const char var_name, char *buf,
3971		size_t buf_size) {
3972		return parse_header(s, s == NULL ? 0 : strlen(s), var_name, buf, buf_size);
	3969	size_t buf_size) {
	3970	return parse_header(s, s == NULL ? 0 : strlen(s), var_name, buf, buf_size);
3973	3971	}
3974	3972
3975	3973	#ifndef MONGOOSE_NO_SSI
3976	3974	static void send_ssi_file(struct mg_connection , const char , FILE *, int);
3977	3975
3978	3976	static void send_file_data(struct mg_connection conn, FILE fp) {
3979		char buf[IOBUF_SIZE];
3980		int n;
3981		while ((n = fread(buf, 1, sizeof(buf), fp)) > 0) {
3982		mg_write(conn, buf, n);
3983		}
	3977	char buf[IOBUF_SIZE];
	3978	int n;
	3979	while ((n = fread(buf, 1, sizeof(buf), fp)) > 0) {
	3980	mg_write(conn, buf, n);
	3981	}
3984	3982	}
3985	3983
3986	3984	static void do_ssi_include(struct mg_connection conn, const char ssi,
3987		char *tag, int include_level) {
3988		char file_name[IOBUF_SIZE], path[MAX_PATH_SIZE], *p;
3989		char **opts = (MG_CONN_2_CONN(conn))->server->config_options;
3990		FILE *fp;
	3985	char *tag, int include_level) {
	3986	char file_name[IOBUF_SIZE], path[MAX_PATH_SIZE], *p;
	3987	char **opts = (MG_CONN_2_CONN(conn))->server->config_options;
	3988	FILE *fp;
3991	3989
3992		// sscanf() is safe here, since send_ssi_file() also uses buffer
3993		// of size MG_BUF_LEN to get the tag. So strlen(tag) is always < MG_BUF_LEN.
3994		if (sscanf(tag, " virtual=\"%[^\"]\"", file_name) == 1) {
3995		// File name is relative to the webserver root
3996		mg_snprintf(path, sizeof(path), "%s%c%s",
3997		opts[DOCUMENT_ROOT], '/', file_name);
3998		} else if (sscanf(tag, " abspath=\"%[^\"]\"", file_name) == 1) {
3999		// File name is relative to the webserver working directory
4000		// or it is absolute system path
4001		mg_snprintf(path, sizeof(path), "%s", file_name);
4002		} else if (sscanf(tag, " file=\"%[^\"]\"", file_name) == 1 \|\|
4003		sscanf(tag, " \"%[^\"]\"", file_name) == 1) {
4004		// File name is relative to the currect document
4005		mg_snprintf(path, sizeof(path), "%s", ssi);
4006		if ((p = strrchr(path, '/')) != NULL) {
4007		p[1] = '\0';
4008		}
4009		mg_snprintf(path + strlen(path), sizeof(path) - strlen(path), "%s",
4010		file_name);
4011		} else {
4012		mg_printf(conn, "Bad SSI #include: [%s]", tag);
4013		return;
4014		}
	3990	// sscanf() is safe here, since send_ssi_file() also uses buffer
	3991	// of size MG_BUF_LEN to get the tag. So strlen(tag) is always < MG_BUF_LEN.
	3992	if (sscanf(tag, " virtual=\"%[^\"]\"", file_name) == 1) {
	3993	// File name is relative to the webserver root
	3994	mg_snprintf(path, sizeof(path), "%s%c%s",
	3995	opts[DOCUMENT_ROOT], '/', file_name);
	3996	} else if (sscanf(tag, " abspath=\"%[^\"]\"", file_name) == 1) {
	3997	// File name is relative to the webserver working directory
	3998	// or it is absolute system path
	3999	mg_snprintf(path, sizeof(path), "%s", file_name);
	4000	} else if (sscanf(tag, " file=\"%[^\"]\"", file_name) == 1 \|\|
	4001	sscanf(tag, " \"%[^\"]\"", file_name) == 1) {
	4002	// File name is relative to the currect document
	4003	mg_snprintf(path, sizeof(path), "%s", ssi);
	4004	if ((p = strrchr(path, '/')) != NULL) {
	4005	p[1] = '\0';
	4006	}
	4007	mg_snprintf(path + strlen(path), sizeof(path) - strlen(path), "%s",
	4008	file_name);
	4009	} else {
	4010	mg_printf(conn, "Bad SSI #include: [%s]", tag);
	4011	return;
	4012	}
4015	4013
4016		if ((fp = fopen(path, "rb")) == NULL) {
4017		mg_printf(conn, "Cannot open SSI #include: [%s]: fopen(%s): %s",
4018		tag, path, strerror(errno));
4019		} else {
4020		ns_set_close_on_exec(fileno(fp));
4021		if (mg_match_prefix(opts[SSI_PATTERN], strlen(opts[SSI_PATTERN]),
4022		path) > 0) {
4023		send_ssi_file(conn, path, fp, include_level + 1);
4024		} else {
4025		send_file_data(conn, fp);
4026		}
4027		fclose(fp);
4028		}
	4014	if ((fp = fopen(path, "rb")) == NULL) {
	4015	mg_printf(conn, "Cannot open SSI #include: [%s]: fopen(%s): %s",
	4016	tag, path, strerror(errno));
	4017	} else {
	4018	ns_set_close_on_exec(fileno(fp));
	4019	if (mg_match_prefix(opts[SSI_PATTERN], strlen(opts[SSI_PATTERN]),
	4020	path) > 0) {
	4021	send_ssi_file(conn, path, fp, include_level + 1);
	4022	} else {
	4023	send_file_data(conn, fp);
	4024	}
	4025	fclose(fp);
	4026	}
4029	4027	}
4030	4028
4031	4029	#ifndef MONGOOSE_NO_POPEN
4032	4030	static void do_ssi_exec(struct mg_connection conn, char tag) {
4033		char cmd[IOBUF_SIZE];
4034		FILE *fp;
	4031	char cmd[IOBUF_SIZE];
	4032	FILE *fp;
4035	4033
4036		if (sscanf(tag, " \"%[^\"]\"", cmd) != 1) {
4037		mg_printf(conn, "Bad SSI #exec: [%s]", tag);
4038		} else if ((fp = popen(cmd, "r")) == NULL) {
4039		mg_printf(conn, "Cannot SSI #exec: [%s]: %s", cmd, strerror(errno));
4040		} else {
4041		send_file_data(conn, fp);
4042		pclose(fp);
4043		}
	4034	if (sscanf(tag, " \"%[^\"]\"", cmd) != 1) {
	4035	mg_printf(conn, "Bad SSI #exec: [%s]", tag);
	4036	} else if ((fp = popen(cmd, "r")) == NULL) {
	4037	mg_printf(conn, "Cannot SSI #exec: [%s]: %s", cmd, strerror(errno));
	4038	} else {
	4039	send_file_data(conn, fp);
	4040	pclose(fp);
	4041	}
4044	4042	}
4045	4043	#endif // !MONGOOSE_NO_POPEN
4046	4044
4047	4045	static void send_ssi_file(struct mg_connection conn, const char path,
4048		FILE *fp, int include_level) {
4049		char buf[IOBUF_SIZE];
4050		int ch, offset, len, in_ssi_tag;
	4046	FILE *fp, int include_level) {
	4047	char buf[IOBUF_SIZE];
	4048	int ch, offset, len, in_ssi_tag;
4051	4049
4052		if (include_level > 10) {
4053		mg_printf(conn, "SSI #include level is too deep (%s)", path);
4054		return;
4055		}
	4050	if (include_level > 10) {
	4051	mg_printf(conn, "SSI #include level is too deep (%s)", path);
	4052	return;
	4053	}
4056	4054
4057		in_ssi_tag = len = offset = 0;
4058		while ((ch = fgetc(fp)) != EOF) {
4059		if (in_ssi_tag && ch == '>') {
4060		in_ssi_tag = 0;
4061		buf[len++] = (char) ch;
4062		buf[len] = '\0';
4063		assert(len <= (int) sizeof(buf));
4064		if (len < 6 \|\| memcmp(buf, "<!--#", 5) != 0) {
4065		// Not an SSI tag, pass it
4066		(void) mg_write(conn, buf, (size_t) len);
4067		} else {
4068		if (!memcmp(buf + 5, "include", 7)) {
4069		do_ssi_include(conn, path, buf + 12, include_level);
	4055	in_ssi_tag = len = offset = 0;
	4056	while ((ch = fgetc(fp)) != EOF) {
	4057	if (in_ssi_tag && ch == '>') {
	4058	in_ssi_tag = 0;
	4059	buf[len++] = (char) ch;
	4060	buf[len] = '\0';
	4061	assert(len <= (int) sizeof(buf));
	4062	if (len < 6 \|\| memcmp(buf, "<!--#", 5) != 0) {
	4063	// Not an SSI tag, pass it
	4064	(void) mg_write(conn, buf, (size_t) len);
	4065	} else {
	4066	if (!memcmp(buf + 5, "include", 7)) {
	4067	do_ssi_include(conn, path, buf + 12, include_level);
4070	4068	#if !defined(MONGOOSE_NO_POPEN)
4071		} else if (!memcmp(buf + 5, "exec", 4)) {
4072		do_ssi_exec(conn, buf + 9);
	4069	} else if (!memcmp(buf + 5, "exec", 4)) {
	4070	do_ssi_exec(conn, buf + 9);
4073	4071	#endif // !NO_POPEN
4074		} else {
4075		mg_printf(conn, "%s: unknown SSI " "command: \"%s\"", path, buf);
4076		}
4077		}
4078		len = 0;
4079		} else if (in_ssi_tag) {
4080		if (len == 5 && memcmp(buf, "<!--#", 5) != 0) {
4081		// Not an SSI tag
4082		in_ssi_tag = 0;
4083		} else if (len == (int) sizeof(buf) - 2) {
4084		mg_printf(conn, "%s: SSI tag is too large", path);
4085		len = 0;
4086		}
4087		buf[len++] = ch & 0xff;
4088		} else if (ch == '<') {
4089		in_ssi_tag = 1;
4090		if (len > 0) {
4091		mg_write(conn, buf, (size_t) len);
4092		}
4093		len = 0;
4094		buf[len++] = ch & 0xff;
4095		} else {
4096		buf[len++] = ch & 0xff;
4097		if (len == (int) sizeof(buf)) {
4098		mg_write(conn, buf, (size_t) len);
4099		len = 0;
4100		}
4101		}
4102		}
	4072	} else {
	4073	mg_printf(conn, "%s: unknown SSI " "command: \"%s\"", path, buf);
	4074	}
	4075	}
	4076	len = 0;
	4077	} else if (in_ssi_tag) {
	4078	if (len == 5 && memcmp(buf, "<!--#", 5) != 0) {
	4079	// Not an SSI tag
	4080	in_ssi_tag = 0;
	4081	} else if (len == (int) sizeof(buf) - 2) {
	4082	mg_printf(conn, "%s: SSI tag is too large", path);
	4083	len = 0;
	4084	}
	4085	buf[len++] = ch & 0xff;
	4086	} else if (ch == '<') {
	4087	in_ssi_tag = 1;
	4088	if (len > 0) {
	4089	mg_write(conn, buf, (size_t) len);
	4090	}
	4091	len = 0;
	4092	buf[len++] = ch & 0xff;
	4093	} else {
	4094	buf[len++] = ch & 0xff;
	4095	if (len == (int) sizeof(buf)) {
	4096	mg_write(conn, buf, (size_t) len);
	4097	len = 0;
	4098	}
	4099	}
	4100	}
4103	4101
4104		// Send the rest of buffered data
4105		if (len > 0) {
4106		mg_write(conn, buf, (size_t) len);
4107		}
	4102	// Send the rest of buffered data
	4103	if (len > 0) {
	4104	mg_write(conn, buf, (size_t) len);
	4105	}
4108	4106	}
4109	4107
4110	4108	static void handle_ssi_request(struct connection conn, const char path) {
4111		FILE *fp;
4112		struct vec mime_vec;
	4109	FILE *fp;
	4110	struct vec mime_vec;
4113	4111
4114		if ((fp = fopen(path, "rb")) == NULL) {
4115		send_http_error(conn, 500, "fopen(%s): %s", path, strerror(errno));
4116		} else {
4117		ns_set_close_on_exec(fileno(fp));
4118		get_mime_type(conn->server, path, &mime_vec);
4119		conn->mg_conn.status_code = 200;
4120		mg_printf(&conn->mg_conn,
4121		"HTTP/1.1 %d OK\r\n"
4122		"Content-Type: %.*s\r\n"
4123		"Connection: close\r\n\r\n",
4124		conn->mg_conn.status_code, (int) mime_vec.len, mime_vec.ptr);
4125		send_ssi_file(&conn->mg_conn, path, fp, 0);
4126		fclose(fp);
4127		close_local_endpoint(conn);
4128		}
	4112	if ((fp = fopen(path, "rb")) == NULL) {
	4113	send_http_error(conn, 500, "fopen(%s): %s", path, strerror(errno));
	4114	} else {
	4115	ns_set_close_on_exec(fileno(fp));
	4116	get_mime_type(conn->server, path, &mime_vec);
	4117	conn->mg_conn.status_code = 200;
	4118	mg_printf(&conn->mg_conn,
	4119	"HTTP/1.1 %d OK\r\n"
	4120	"Content-Type: %.*s\r\n"
	4121	"Connection: close\r\n\r\n",
	4122	conn->mg_conn.status_code, (int) mime_vec.len, mime_vec.ptr);
	4123	send_ssi_file(&conn->mg_conn, path, fp, 0);
	4124	fclose(fp);
	4125	close_local_endpoint(conn);
	4126	}
4129	4127	}
4130	4128	#endif
4131	4129
4132	4130	static void proxy_request(struct ns_connection pc, struct mg_connection c) {
4133		int i, sent_close_header = 0;
	4131	int i, sent_close_header = 0;
4134	4132
4135		ns_printf(pc, "%s %s HTTP/%s\r\n", c->request_method, c->uri,
4136		c->http_version);
4137		for (i = 0; i < c->num_headers; i++) {
4138		if (mg_strcasecmp(c->http_headers[i].name, "Connection") == 0) {
4139		// Force connection close, cause we don't parse proxy replies
4140		// therefore we don't know message boundaries
4141		ns_printf(pc, "%s: %s\r\n", "Connection", "close");
4142		sent_close_header = 1;
4143		} else {
4144		ns_printf(pc, "%s: %s\r\n", c->http_headers[i].name,
4145		c->http_headers[i].value);
4146		}
4147		}
4148		if (!sent_close_header) {
4149		ns_printf(pc, "%s: %s\r\n", "Connection", "close");
4150		}
4151		ns_printf(pc, "%s", "\r\n");
4152		ns_send(pc, c->content, c->content_len);
	4133	ns_printf(pc, "%s %s HTTP/%s\r\n", c->request_method, c->uri,
	4134	c->http_version);
	4135	for (i = 0; i < c->num_headers; i++) {
	4136	if (mg_strcasecmp(c->http_headers[i].name, "Connection") == 0) {
	4137	// Force connection close, cause we don't parse proxy replies
	4138	// therefore we don't know message boundaries
	4139	ns_printf(pc, "%s: %s\r\n", "Connection", "close");
	4140	sent_close_header = 1;
	4141	} else {
	4142	ns_printf(pc, "%s: %s\r\n", c->http_headers[i].name,
	4143	c->http_headers[i].value);
	4144	}
	4145	}
	4146	if (!sent_close_header) {
	4147	ns_printf(pc, "%s: %s\r\n", "Connection", "close");
	4148	}
	4149	ns_printf(pc, "%s", "\r\n");
	4150	ns_send(pc, c->content, c->content_len);
4153	4151
4154	4152	}
4155	4153
4156	4154	#ifdef NS_ENABLE_SSL
4157	4155	int mg_terminate_ssl(struct mg_connection c, const char cert) {
4158		static const char ok[] = "HTTP/1.0 200 OK\r\n\r\n";
4159		struct connection *conn = MG_CONN_2_CONN(c);
4160		SSL_CTX *ctx;
	4156	static const char ok[] = "HTTP/1.0 200 OK\r\n\r\n";
	4157	struct connection *conn = MG_CONN_2_CONN(c);
	4158	SSL_CTX *ctx;
4161	4159
4162		DBG(("%p MITM", conn));
4163		SSL_library_init();
4164		if ((ctx = SSL_CTX_new(SSLv23_server_method())) == NULL) return 0;
	4160	DBG(("%p MITM", conn));
	4161	SSL_library_init();
	4162	if ((ctx = SSL_CTX_new(SSLv23_server_method())) == NULL) return 0;
4165	4163
4166		SSL_CTX_use_certificate_file(ctx, cert, 1);
4167		SSL_CTX_use_PrivateKey_file(ctx, cert, 1);
4168		SSL_CTX_use_certificate_chain_file(ctx, cert);
	4164	SSL_CTX_use_certificate_file(ctx, cert, 1);
	4165	SSL_CTX_use_PrivateKey_file(ctx, cert, 1);
	4166	SSL_CTX_use_certificate_chain_file(ctx, cert);
4169	4167
4170		// When clear-text reply is pushed to client, switch to SSL mode.
4171		// TODO(lsm): check for send() failure
4172		send(conn->ns_conn->sock, ok, sizeof(ok) - 1, 0);
4173		DBG(("%p %lu %d SEND", c, (unsigned long)sizeof(ok) - 1, n));
4174		conn->ns_conn->send_iobuf.len = 0;
4175		conn->endpoint_type = EP_USER; // To keep-alive in close_local_endpoint()
4176		close_local_endpoint(conn); // Clean up current CONNECT request
4177		if ((conn->ns_conn->ssl = SSL_new(ctx)) != NULL) {
4178		SSL_set_fd(conn->ns_conn->ssl, conn->ns_conn->sock);
4179		}
4180		SSL_CTX_free(ctx);
4181		return 1;
	4168	// When clear-text reply is pushed to client, switch to SSL mode.
	4169	// TODO(lsm): check for send() failure
	4170	send(conn->ns_conn->sock, ok, sizeof(ok) - 1, 0);
	4171	DBG(("%p %lu %d SEND", c, (unsigned long)sizeof(ok) - 1, n));
	4172	conn->ns_conn->send_iobuf.len = 0;
	4173	conn->endpoint_type = EP_USER; // To keep-alive in close_local_endpoint()
	4174	close_local_endpoint(conn); // Clean up current CONNECT request
	4175	if ((conn->ns_conn->ssl = SSL_new(ctx)) != NULL) {
	4176	SSL_set_fd(conn->ns_conn->ssl, conn->ns_conn->sock);
	4177	}
	4178	SSL_CTX_free(ctx);
	4179	return 1;
4182	4180	}
4183	4181	#endif
4184	4182
4185	4183	int mg_forward(struct mg_connection c, const char host, int port, int ssl) {
4186		struct connection *conn = MG_CONN_2_CONN(c);
4187		struct ns_server *server = &conn->server->ns_server;
4188		struct ns_connection *pc;
	4184	struct connection *conn = MG_CONN_2_CONN(c);
	4185	struct ns_server *server = &conn->server->ns_server;
	4186	struct ns_connection *pc;
4189	4187
4190		if ((pc = ns_connect(server, host, port, ssl, conn)) == NULL) {
4191		conn->ns_conn->flags \|= NSF_CLOSE_IMMEDIATELY;
4192		return 0;
4193		}
	4188	if ((pc = ns_connect(server, host, port, ssl, conn)) == NULL) {
	4189	conn->ns_conn->flags \|= NSF_CLOSE_IMMEDIATELY;
	4190	return 0;
	4191	}
4194	4192
4195		// Interlink two connections
4196		pc->flags \|= MG_PROXY_CONN;
4197		conn->endpoint_type = EP_PROXY;
4198		conn->endpoint.nc = pc;
4199		DBG(("%p [%s] [%s:%d] -> %p %p",
4200		conn, c->uri, host, port, pc, conn->ns_conn->ssl));
	4193	// Interlink two connections
	4194	pc->flags \|= MG_PROXY_CONN;
	4195	conn->endpoint_type = EP_PROXY;
	4196	conn->endpoint.nc = pc;
	4197	DBG(("%p [%s] [%s:%d] -> %p %p",
	4198	conn, c->uri, host, port, pc, conn->ns_conn->ssl));
4201	4199
4202		if (strcmp(c->request_method, "CONNECT") == 0) {
4203		// For CONNECT request, reply with 200 OK. Tunnel is established.
4204		mg_printf(c, "%s", "HTTP/1.1 200 OK\r\n\r\n");
4205		} else {
4206		// Strip "http://host:port" part from the URI
4207		if (memcmp(c->uri, "http://", 7) == 0) c->uri += 7;
4208		while (c->uri != '\0' && c->uri != '/') c->uri++;
4209		proxy_request(pc, c);
4210		}
4211		return 1;
	4200	if (strcmp(c->request_method, "CONNECT") == 0) {
	4201	// For CONNECT request, reply with 200 OK. Tunnel is established.
	4202	mg_printf(c, "%s", "HTTP/1.1 200 OK\r\n\r\n");
	4203	} else {
	4204	// Strip "http://host:port" part from the URI
	4205	if (memcmp(c->uri, "http://", 7) == 0) c->uri += 7;
	4206	while (c->uri != '\0' && c->uri != '/') c->uri++;
	4207	proxy_request(pc, c);
	4208	}
	4209	return 1;
4212	4210	}
4213	4211
4214	4212	static void proxify_connection(struct connection *conn) {
4215		char proto[10], host[500], cert[500];
4216		unsigned short port = 80;
4217		struct mg_connection *c = &conn->mg_conn;
4218		int n = 0;
4219		const char *url = c->uri;
	4213	char proto[10], host[500], cert[500];
	4214	unsigned short port = 80;
	4215	struct mg_connection *c = &conn->mg_conn;
	4216	int n = 0;
	4217	const char *url = c->uri;
4220	4218
4221		proto[0] = host[0] = cert[0] = '\0';
4222		if (sscanf(url, "%499[^: ]:%hu%n", host, &port, &n) != 2 &&
4223		sscanf(url, "%9[a-z]://%499[^: ]:%hu%n", proto, host, &port, &n) != 3 &&
4224		sscanf(url, "%9[a-z]://%499[^/ ]%n", proto, host, &n) != 2) {
4225		n = 0;
4226		}
	4219	proto[0] = host[0] = cert[0] = '\0';
	4220	if (sscanf(url, "%499[^: ]:%hu%n", host, &port, &n) != 2 &&
	4221	sscanf(url, "%9[a-z]://%499[^: ]:%hu%n", proto, host, &port, &n) != 3 &&
	4222	sscanf(url, "%9[a-z]://%499[^/ ]%n", proto, host, &n) != 2) {
	4223	n = 0;
	4224	}
4227	4225
4228	4226	#ifdef NS_ENABLE_SSL
4229		// Find out whether we should be in the MITM mode
4230		{
4231		const char *certs = conn->server->config_options[SSL_MITM_CERTS];
4232		int host_len = strlen(host);
4233		struct vec a, b;
	4227	// Find out whether we should be in the MITM mode
	4228	{
	4229	const char *certs = conn->server->config_options[SSL_MITM_CERTS];
	4230	int host_len = strlen(host);
	4231	struct vec a, b;
4234	4232
4235		while (conn->ns_conn->ssl == NULL && port != 80 &&
4236		(certs = next_option(certs, &a, &b)) != NULL) {
4237		if (a.len != host_len \|\| mg_strncasecmp(a.ptr, host, a.len)) continue;
4238		snprintf(cert, sizeof(cert), "%.*s", b.len, b.ptr);
4239		mg_terminate_ssl(&conn->mg_conn, cert);
4240		return;
4241		}
4242		}
	4233	while (conn->ns_conn->ssl == NULL && port != 80 &&
	4234	(certs = next_option(certs, &a, &b)) != NULL) {
	4235	if (a.len != host_len \|\| mg_strncasecmp(a.ptr, host, a.len)) continue;
	4236	snprintf(cert, sizeof(cert), "%.*s", b.len, b.ptr);
	4237	mg_terminate_ssl(&conn->mg_conn, cert);
	4238	return;
	4239	}
	4240	}
4243	4241	#endif
4244	4242
4245		if (n > 0 && mg_forward(c, host, port, conn->ns_conn->ssl != NULL)) {
4246		} else {
4247		conn->ns_conn->flags \|= NSF_CLOSE_IMMEDIATELY;
4248		}
	4243	if (n > 0 && mg_forward(c, host, port, conn->ns_conn->ssl != NULL)) {
	4244	} else {
	4245	conn->ns_conn->flags \|= NSF_CLOSE_IMMEDIATELY;
	4246	}
4249	4247	}
4250	4248
4251	4249	#ifndef MONGOOSE_NO_FILESYSTEM
4252	4250	void mg_send_file_internal(struct mg_connection c, const char file_name,
4253		file_stat_t *st, int exists) {
4254		struct connection *conn = MG_CONN_2_CONN(c);
4255		char path[MAX_PATH_SIZE];
4256		const int is_directory = S_ISDIR(st->st_mode);
	4251	file_stat_t *st, int exists) {
	4252	struct connection *conn = MG_CONN_2_CONN(c);
	4253	char path[MAX_PATH_SIZE];
	4254	const int is_directory = S_ISDIR(st->st_mode);
4257	4255	#ifndef MONGOOSE_NO_CGI
4258		const char *cgi_pat = conn->server->config_options[CGI_PATTERN];
	4256	const char *cgi_pat = conn->server->config_options[CGI_PATTERN];
4259	4257	#else
4260		const char *cgi_pat = DEFAULT_CGI_PATTERN;
	4258	const char *cgi_pat = DEFAULT_CGI_PATTERN;
4261	4259	#endif
4262	4260	#ifndef MONGOOSE_NO_DIRECTORY_LISTING
4263		const char *dir_lst = conn->server->config_options[ENABLE_DIRECTORY_LISTING];
	4261	const char *dir_lst = conn->server->config_options[ENABLE_DIRECTORY_LISTING];
4264	4262	#else
4265		const char *dir_lst = "yes";
	4263	const char *dir_lst = "yes";
4266	4264	#endif
4267	4265
4268		mg_snprintf(path, sizeof(path), "%s", file_name);
	4266	mg_snprintf(path, sizeof(path), "%s", file_name);
4269	4267
4270		if (!exists \|\| must_hide_file(conn, path)) {
4271		send_http_error(conn, 404, NULL);
4272		} else if (is_directory &&
4273		conn->mg_conn.uri[strlen(conn->mg_conn.uri) - 1] != '/') {
4274		conn->mg_conn.status_code = 301;
4275		mg_printf(&conn->mg_conn, "HTTP/1.1 301 Moved Permanently\r\n"
4276		"Location: %s/\r\n\r\n", conn->mg_conn.uri);
4277		close_local_endpoint(conn);
4278		} else if (is_directory && !find_index_file(conn, path, sizeof(path), st)) {
4279		if (!mg_strcasecmp(dir_lst, "yes")) {
	4268	if (!exists \|\| must_hide_file(conn, path)) {
	4269	send_http_error(conn, 404, NULL);
	4270	} else if (is_directory &&
	4271	conn->mg_conn.uri[strlen(conn->mg_conn.uri) - 1] != '/') {
	4272	conn->mg_conn.status_code = 301;
	4273	mg_printf(&conn->mg_conn, "HTTP/1.1 301 Moved Permanently\r\n"
	4274	"Location: %s/\r\n\r\n", conn->mg_conn.uri);
	4275	close_local_endpoint(conn);
	4276	} else if (is_directory && !find_index_file(conn, path, sizeof(path), st)) {
	4277	if (!mg_strcasecmp(dir_lst, "yes")) {
4280	4278	#ifndef MONGOOSE_NO_DIRECTORY_LISTING
4281		send_directory_listing(conn, path);
	4279	send_directory_listing(conn, path);
4282	4280	#else
4283		send_http_error(conn, 501, NULL);
	4281	send_http_error(conn, 501, NULL);
4284	4282	#endif
4285		} else {
4286		send_http_error(conn, 403, NULL);
4287		}
4288		} else if (mg_match_prefix(cgi_pat, strlen(cgi_pat), path) > 0) {
	4283	} else {
	4284	send_http_error(conn, 403, NULL);
	4285	}
	4286	} else if (mg_match_prefix(cgi_pat, strlen(cgi_pat), path) > 0) {
4289	4287	#if !defined(MONGOOSE_NO_CGI)
4290		open_cgi_endpoint(conn, path);
	4288	open_cgi_endpoint(conn, path);
4291	4289	#else
4292		send_http_error(conn, 501, NULL);
	4290	send_http_error(conn, 501, NULL);
4293	4291	#endif // !MONGOOSE_NO_CGI
4294	4292	#ifndef MONGOOSE_NO_SSI
4295		} else if (mg_match_prefix(conn->server->config_options[SSI_PATTERN],
4296		strlen(conn->server->config_options[SSI_PATTERN]),
4297		path) > 0) {
4298		handle_ssi_request(conn, path);
	4293	} else if (mg_match_prefix(conn->server->config_options[SSI_PATTERN],
	4294	strlen(conn->server->config_options[SSI_PATTERN]),
	4295	path) > 0) {
	4296	handle_ssi_request(conn, path);
4299	4297	#endif
4300		} else if (is_not_modified(conn, st)) {
4301		send_http_error(conn, 304, NULL);
4302		} else if ((conn->endpoint.fd = open(path, O_RDONLY \| O_BINARY)) != -1) {
4303		// O_BINARY is required for Windows, otherwise in default text mode
4304		// two bytes \r\n will be read as one.
4305		open_file_endpoint(conn, path, st);
4306		} else {
4307		send_http_error(conn, 404, NULL);
4308		}
	4298	} else if (is_not_modified(conn, st)) {
	4299	send_http_error(conn, 304, NULL);
	4300	} else if ((conn->endpoint.fd = open(path, O_RDONLY \| O_BINARY)) != -1) {
	4301	// O_BINARY is required for Windows, otherwise in default text mode
	4302	// two bytes \r\n will be read as one.
	4303	open_file_endpoint(conn, path, st);
	4304	} else {
	4305	send_http_error(conn, 404, NULL);
	4306	}
4309	4307	}
4310	4308	void mg_send_file(struct mg_connection c, const char file_name) {
4311		file_stat_t st;
4312		const int exists = stat(file_name, &st) == 0;
4313		mg_send_file_internal(c, file_name, &st, exists);
	4309	file_stat_t st;
	4310	const int exists = stat(file_name, &st) == 0;
	4311	mg_send_file_internal(c, file_name, &st, exists);
4314	4312	}
4315	4313	#endif // !MONGOOSE_NO_FILESYSTEM
4316	4314
4317	4315	static void open_local_endpoint(struct connection *conn, int skip_user) {
4318	4316	#ifndef MONGOOSE_NO_FILESYSTEM
4319		char path[MAX_PATH_SIZE];
4320		file_stat_t st;
4321		int exists = 0;
	4317	char path[MAX_PATH_SIZE];
	4318	file_stat_t st;
	4319	int exists = 0;
4322	4320	#endif
4323	4321
4324		// If EP_USER was set in a prev call, reset it
4325		conn->endpoint_type = EP_NONE;
	4322	// If EP_USER was set in a prev call, reset it
	4323	conn->endpoint_type = EP_NONE;
4326	4324
4327	4325	#ifndef MONGOOSE_NO_AUTH
4328		if (conn->server->event_handler && call_user(conn, MG_AUTH) == MG_FALSE) {
4329		mg_send_digest_auth_request(&conn->mg_conn);
4330		return;
4331		}
	4326	if (conn->server->event_handler && call_user(conn, MG_AUTH) == MG_FALSE) {
	4327	mg_send_digest_auth_request(&conn->mg_conn);
	4328	return;
	4329	}
4332	4330	#endif
4333	4331
4334		// Call URI handler if one is registered for this URI
4335		if (skip_user == 0 && conn->server->event_handler != NULL) {
4336		conn->endpoint_type = EP_USER;
	4332	// Call URI handler if one is registered for this URI
	4333	if (skip_user == 0 && conn->server->event_handler != NULL) {
	4334	conn->endpoint_type = EP_USER;
4337	4335	#if MONGOOSE_POST_SIZE_LIMIT > 1
4338		{
4339		const char *cl = mg_get_header(&conn->mg_conn, "Content-Length");
4340		if ((strcmp(conn->mg_conn.request_method, "POST") == 0 \|\|
4341		strcmp(conn->mg_conn.request_method, "PUT") == 0) &&
4342		(cl == NULL \|\| to64(cl) > MONGOOSE_POST_SIZE_LIMIT)) {
4343		send_http_error(conn, 500, "POST size > %lu",
4344		(unsigned long) MONGOOSE_POST_SIZE_LIMIT);
4345		}
4346		}
	4336	{
	4337	const char *cl = mg_get_header(&conn->mg_conn, "Content-Length");
	4338	if ((strcmp(conn->mg_conn.request_method, "POST") == 0 \|\|
	4339	strcmp(conn->mg_conn.request_method, "PUT") == 0) &&
	4340	(cl == NULL \|\| to64(cl) > MONGOOSE_POST_SIZE_LIMIT)) {
	4341	send_http_error(conn, 500, "POST size > %lu",
	4342	(unsigned long) MONGOOSE_POST_SIZE_LIMIT);
	4343	}
	4344	}
4347	4345	#endif
4348		return;
4349		}
	4346	return;
	4347	}
4350	4348
4351		if (strcmp(conn->mg_conn.request_method, "CONNECT") == 0 \|\|
4352		mg_strncasecmp(conn->mg_conn.uri, "http", 4) == 0) {
4353		const char *enp = conn->server->config_options[ENABLE_PROXY];
4354		if (enp == NULL \|\| strcmp(enp, "yes") != 0) {
4355		send_http_error(conn, 405, NULL);
4356		} else {
4357		proxify_connection(conn);
4358		}
4359		return;
4360		}
	4349	if (strcmp(conn->mg_conn.request_method, "CONNECT") == 0 \|\|
	4350	mg_strncasecmp(conn->mg_conn.uri, "http", 4) == 0) {
	4351	const char *enp = conn->server->config_options[ENABLE_PROXY];
	4352	if (enp == NULL \|\| strcmp(enp, "yes") != 0) {
	4353	send_http_error(conn, 405, NULL);
	4354	} else {
	4355	proxify_connection(conn);
	4356	}
	4357	return;
	4358	}
4361	4359
4362		if (!strcmp(conn->mg_conn.request_method, "OPTIONS")) {
4363		send_options(conn);
4364		return;
4365		}
	4360	if (!strcmp(conn->mg_conn.request_method, "OPTIONS")) {
	4361	send_options(conn);
	4362	return;
	4363	}
4366	4364
4367	4365	#ifdef MONGOOSE_NO_FILESYSTEM
4368		send_http_error(conn, 404, NULL);
	4366	send_http_error(conn, 404, NULL);
4369	4367	#else
4370		exists = convert_uri_to_file_name(conn, path, sizeof(path), &st);
	4368	exists = convert_uri_to_file_name(conn, path, sizeof(path), &st);
4371	4369
4372		if (!strcmp(conn->mg_conn.request_method, "OPTIONS")) {
4373		send_options(conn);
4374		} else if (conn->server->config_options[DOCUMENT_ROOT] == NULL) {
4375		send_http_error(conn, 404, NULL);
	4370	if (!strcmp(conn->mg_conn.request_method, "OPTIONS")) {
	4371	send_options(conn);
	4372	} else if (conn->server->config_options[DOCUMENT_ROOT] == NULL) {
	4373	send_http_error(conn, 404, NULL);
4376	4374	#ifndef MONGOOSE_NO_AUTH
4377		} else if ((!is_dav_request(conn) && !is_authorized(conn, path,
4378		exists && S_ISDIR(st.st_mode))) \|\|
4379		(is_dav_request(conn) && !is_authorized_for_dav(conn))) {
4380		mg_send_digest_auth_request(&conn->mg_conn);
4381		close_local_endpoint(conn);
	4375	} else if ((!is_dav_request(conn) && !is_authorized(conn, path,
	4376	exists && S_ISDIR(st.st_mode))) \|\|
	4377	(is_dav_request(conn) && !is_authorized_for_dav(conn))) {
	4378	mg_send_digest_auth_request(&conn->mg_conn);
	4379	close_local_endpoint(conn);
4382	4380	#endif
4383	4381	#ifndef MONGOOSE_NO_DAV
4384		} else if (must_hide_file(conn, path)) {
4385		send_http_error(conn, 404, NULL);
4386		} else if (!strcmp(conn->mg_conn.request_method, "PROPFIND")) {
4387		handle_propfind(conn, path, &st, exists);
4388		} else if (!strcmp(conn->mg_conn.request_method, "MKCOL")) {
4389		handle_mkcol(conn, path);
4390		} else if (!strcmp(conn->mg_conn.request_method, "DELETE")) {
4391		handle_delete(conn, path);
4392		} else if (!strcmp(conn->mg_conn.request_method, "PUT")) {
4393		handle_put(conn, path);
	4382	} else if (must_hide_file(conn, path)) {
	4383	send_http_error(conn, 404, NULL);
	4384	} else if (!strcmp(conn->mg_conn.request_method, "PROPFIND")) {
	4385	handle_propfind(conn, path, &st, exists);
	4386	} else if (!strcmp(conn->mg_conn.request_method, "MKCOL")) {
	4387	handle_mkcol(conn, path);
	4388	} else if (!strcmp(conn->mg_conn.request_method, "DELETE")) {
	4389	handle_delete(conn, path);
	4390	} else if (!strcmp(conn->mg_conn.request_method, "PUT")) {
	4391	handle_put(conn, path);
4394	4392	#endif
4395		} else {
4396		mg_send_file_internal(&conn->mg_conn, path, &st, exists);
4397		}
	4393	} else {
	4394	mg_send_file_internal(&conn->mg_conn, path, &st, exists);
	4395	}
4398	4396	#endif // MONGOOSE_NO_FILESYSTEM
4399	4397	}
4400	4398
4401	4399	static void send_continue_if_expected(struct connection *conn) {
4402		static const char expect_response[] = "HTTP/1.1 100 Continue\r\n\r\n";
4403		const char *expect_hdr = mg_get_header(&conn->mg_conn, "Expect");
	4400	static const char expect_response[] = "HTTP/1.1 100 Continue\r\n\r\n";
	4401	const char *expect_hdr = mg_get_header(&conn->mg_conn, "Expect");
4404	4402
4405		if (expect_hdr != NULL && !mg_strcasecmp(expect_hdr, "100-continue")) {
4406		ns_send(conn->ns_conn, expect_response, sizeof(expect_response) - 1);
4407		}
	4403	if (expect_hdr != NULL && !mg_strcasecmp(expect_hdr, "100-continue")) {
	4404	ns_send(conn->ns_conn, expect_response, sizeof(expect_response) - 1);
	4405	}
4408	4406	}
4409	4407
4410	4408	// Conform to http://www.w3.org/Protocols/rfc2616/rfc2616-sec5.html#sec5.1.2
4411	4409	static int is_valid_uri(const char *uri) {
4412		unsigned short n;
4413		return uri[0] == '/' \|\|
4414		strcmp(uri, "*") == 0 \|\| // OPTIONS method can use asterisk URI
4415		mg_strncasecmp(uri, "http", 4) == 0 \|\| // Naive check for the absolute URI
4416		sscanf(uri, "%*[^ :]:%hu", &n) > 0; // CONNECT method can use host:port
	4410	unsigned short n;
	4411	return uri[0] == '/' \|\|
	4412	strcmp(uri, "*") == 0 \|\| // OPTIONS method can use asterisk URI
	4413	mg_strncasecmp(uri, "http", 4) == 0 \|\| // Naive check for the absolute URI
	4414	sscanf(uri, "%*[^ :]:%hu", &n) > 0; // CONNECT method can use host:port
4417	4415	}
4418	4416
4419	4417	static void try_parse(struct connection *conn) {
4420		struct iobuf *io = &conn->ns_conn->recv_iobuf;
	4418	struct iobuf *io = &conn->ns_conn->recv_iobuf;
4421	4419
4422		if (conn->request_len == 0 &&
4423		(conn->request_len = get_request_len(io->buf, io->len)) > 0) {
4424		// If request is buffered in, remove it from the iobuf. This is because
4425		// iobuf could be reallocated, and pointers in parsed request could
4426		// become invalid.
4427		conn->request = (char *) malloc(conn->request_len);
4428		memcpy(conn->request, io->buf, conn->request_len);
4429		//DBG(("%p [%.*s]", conn, conn->request_len, conn->request));
4430		iobuf_remove(io, conn->request_len);
4431		conn->request_len = parse_http_message(conn->request, conn->request_len,
4432		&conn->mg_conn);
4433		if (conn->request_len > 0) {
4434		const char *cl_hdr = mg_get_header(&conn->mg_conn, "Content-Length");
4435		conn->cl = cl_hdr == NULL ? 0 : to64(cl_hdr);
4436		conn->mg_conn.content_len = (size_t) conn->cl;
4437		}
4438		}
	4420	if (conn->request_len == 0 &&
	4421	(conn->request_len = get_request_len(io->buf, io->len)) > 0) {
	4422	// If request is buffered in, remove it from the iobuf. This is because
	4423	// iobuf could be reallocated, and pointers in parsed request could
	4424	// become invalid.
	4425	conn->request = (char *) malloc(conn->request_len);
	4426	memcpy(conn->request, io->buf, conn->request_len);
	4427	//DBG(("%p [%.*s]", conn, conn->request_len, conn->request));
	4428	iobuf_remove(io, conn->request_len);
	4429	conn->request_len = parse_http_message(conn->request, conn->request_len,
	4430	&conn->mg_conn);
	4431	if (conn->request_len > 0) {
	4432	const char *cl_hdr = mg_get_header(&conn->mg_conn, "Content-Length");
	4433	conn->cl = cl_hdr == NULL ? 0 : to64(cl_hdr);
	4434	conn->mg_conn.content_len = (size_t) conn->cl;
	4435	}
	4436	}
4439	4437	}
4440	4438
4441	4439	static void do_proxy(struct connection *conn) {
4442		if (0 && conn->request_len == 0) {
4443		try_parse(conn);
4444		DBG(("%p parsing -> %d", conn, conn->request_len));
4445		if (conn->request_len > 0 && call_user(conn, MG_REQUEST) == MG_FALSE) {
4446		proxy_request(conn->endpoint.nc, &conn->mg_conn);
4447		} else if (conn->request_len < 0) {
4448		ns_forward(conn->ns_conn, conn->endpoint.nc);
4449		}
4450		} else {
4451		DBG(("%p forwarding", conn));
4452		ns_forward(conn->ns_conn, conn->endpoint.nc);
4453		}
	4440	if (0 && conn->request_len == 0) {
	4441	try_parse(conn);
	4442	DBG(("%p parsing -> %d", conn, conn->request_len));
	4443	if (conn->request_len > 0 && call_user(conn, MG_REQUEST) == MG_FALSE) {
	4444	proxy_request(conn->endpoint.nc, &conn->mg_conn);
	4445	} else if (conn->request_len < 0) {
	4446	ns_forward(conn->ns_conn, conn->endpoint.nc);
	4447	}
	4448	} else {
	4449	DBG(("%p forwarding", conn));
	4450	ns_forward(conn->ns_conn, conn->endpoint.nc);
	4451	}
4454	4452	}
4455	4453
4456	4454	static void on_recv_data(struct connection *conn) {
4457		struct iobuf *io = &conn->ns_conn->recv_iobuf;
4458		int n;
	4455	struct iobuf *io = &conn->ns_conn->recv_iobuf;
	4456	int n;
4459	4457
4460		if (conn->endpoint_type == EP_PROXY) {
4461		if (conn->endpoint.nc != NULL) do_proxy(conn);
4462		return;
4463		}
	4458	if (conn->endpoint_type == EP_PROXY) {
	4459	if (conn->endpoint.nc != NULL) do_proxy(conn);
	4460	return;
	4461	}
4464	4462
4465		try_parse(conn);
4466		DBG(("%p %d %lu %d", conn, conn->request_len, (unsigned long)io->len,
4467		conn->ns_conn->flags));
4468		if (conn->request_len < 0 \|\|
4469		(conn->request_len > 0 && !is_valid_uri(conn->mg_conn.uri))) {
4470		send_http_error(conn, 400, NULL);
4471		} else if (conn->request_len == 0 && io->len > MAX_REQUEST_SIZE) {
4472		send_http_error(conn, 413, NULL);
4473		} else if (conn->request_len > 0 &&
4474		strcmp(conn->mg_conn.http_version, "1.0") != 0 &&
4475		strcmp(conn->mg_conn.http_version, "1.1") != 0) {
4476		send_http_error(conn, 505, NULL);
4477		} else if (conn->request_len > 0 && conn->endpoint_type == EP_NONE) {
	4463	try_parse(conn);
	4464	DBG(("%p %d %lu %d", conn, conn->request_len, (unsigned long)io->len,
	4465	conn->ns_conn->flags));
	4466	if (conn->request_len < 0 \|\|
	4467	(conn->request_len > 0 && !is_valid_uri(conn->mg_conn.uri))) {
	4468	send_http_error(conn, 400, NULL);
	4469	} else if (conn->request_len == 0 && io->len > MAX_REQUEST_SIZE) {
	4470	send_http_error(conn, 413, NULL);
	4471	} else if (conn->request_len > 0 &&
	4472	strcmp(conn->mg_conn.http_version, "1.0") != 0 &&
	4473	strcmp(conn->mg_conn.http_version, "1.1") != 0) {
	4474	send_http_error(conn, 505, NULL);
	4475	} else if (conn->request_len > 0 && conn->endpoint_type == EP_NONE) {
4478	4476	#ifndef MONGOOSE_NO_WEBSOCKET
4479		send_websocket_handshake_if_requested(&conn->mg_conn);
	4477	send_websocket_handshake_if_requested(&conn->mg_conn);
4480	4478	#endif
4481		send_continue_if_expected(conn);
4482		open_local_endpoint(conn, 0);
4483		}
	4479	send_continue_if_expected(conn);
	4480	open_local_endpoint(conn, 0);
	4481	}
4484	4482
4485	4483	#ifndef MONGOOSE_NO_CGI
4486		if (conn->endpoint_type == EP_CGI && conn->endpoint.nc != NULL) {
4487		ns_forward(conn->ns_conn, conn->endpoint.nc);
4488		}
	4484	if (conn->endpoint_type == EP_CGI && conn->endpoint.nc != NULL) {
	4485	ns_forward(conn->ns_conn, conn->endpoint.nc);
	4486	}
4489	4487	#endif
4490		if (conn->endpoint_type == EP_USER) {
4491		conn->mg_conn.content = io->buf;
4492		conn->mg_conn.content_len = io->len;
4493		n = call_user(conn, MG_RECV);
4494		if (n < 0) {
4495		conn->ns_conn->flags \|= NSF_FINISHED_SENDING_DATA;
4496		} else if ((size_t) n <= io->len) {
4497		iobuf_remove(io, n);
4498		}
4499		call_request_handler_if_data_is_buffered(conn);
4500		}
	4488	if (conn->endpoint_type == EP_USER) {
	4489	conn->mg_conn.content = io->buf;
	4490	conn->mg_conn.content_len = io->len;
	4491	n = call_user(conn, MG_RECV);
	4492	if (n < 0) {
	4493	conn->ns_conn->flags \|= NSF_FINISHED_SENDING_DATA;
	4494	} else if ((size_t) n <= io->len) {
	4495	iobuf_remove(io, n);
	4496	}
	4497	call_request_handler_if_data_is_buffered(conn);
	4498	}
4501	4499	#ifndef MONGOOSE_NO_DAV
4502		if (conn->endpoint_type == EP_PUT && io->len > 0) {
4503		forward_put_data(conn);
4504		}
	4500	if (conn->endpoint_type == EP_PUT && io->len > 0) {
	4501	forward_put_data(conn);
	4502	}
4505	4503	#endif
4506	4504	}
4507	4505
4508	4506	static void call_http_client_handler(struct connection *conn) {
4509		//conn->mg_conn.status_code = code;
4510		// For responses without Content-Lengh, use the whole buffer
4511		if (conn->cl == 0) {
4512		conn->mg_conn.content_len = conn->ns_conn->recv_iobuf.len;
4513		}
4514		conn->mg_conn.content = conn->ns_conn->recv_iobuf.buf;
4515		if (call_user(conn, MG_REPLY) == MG_FALSE) {
4516		conn->ns_conn->flags \|= NSF_CLOSE_IMMEDIATELY;
4517		}
4518		iobuf_remove(&conn->ns_conn->recv_iobuf, conn->mg_conn.content_len);
4519		conn->mg_conn.status_code = 0;
4520		conn->cl = conn->num_bytes_recv = conn->request_len = 0;
4521		free(conn->request);
4522		conn->request = NULL;
	4507	//conn->mg_conn.status_code = code;
	4508	// For responses without Content-Lengh, use the whole buffer
	4509	if (conn->cl == 0) {
	4510	conn->mg_conn.content_len = conn->ns_conn->recv_iobuf.len;
	4511	}
	4512	conn->mg_conn.content = conn->ns_conn->recv_iobuf.buf;
	4513	if (call_user(conn, MG_REPLY) == MG_FALSE) {
	4514	conn->ns_conn->flags \|= NSF_CLOSE_IMMEDIATELY;
	4515	}
	4516	iobuf_remove(&conn->ns_conn->recv_iobuf, conn->mg_conn.content_len);
	4517	conn->mg_conn.status_code = 0;
	4518	conn->cl = conn->num_bytes_recv = conn->request_len = 0;
	4519	free(conn->request);
	4520	conn->request = NULL;
4523	4521	}
4524	4522
4525	4523	static void process_response(struct connection *conn) {
4526		struct iobuf *io = &conn->ns_conn->recv_iobuf;
	4524	struct iobuf *io = &conn->ns_conn->recv_iobuf;
4527	4525
4528		try_parse(conn);
4529		DBG(("%p %d %lu", conn, conn->request_len, (unsigned long)io->len));
4530		if (conn->request_len < 0 \|\|
4531		(conn->request_len == 0 && io->len > MAX_REQUEST_SIZE)) {
4532		call_http_client_handler(conn);
4533		} else if ((int64_t) io->len >= conn->cl) {
4534		call_http_client_handler(conn);
4535		}
	4526	try_parse(conn);
	4527	DBG(("%p %d %lu", conn, conn->request_len, (unsigned long)io->len));
	4528	if (conn->request_len < 0 \|\|
	4529	(conn->request_len == 0 && io->len > MAX_REQUEST_SIZE)) {
	4530	call_http_client_handler(conn);
	4531	} else if ((int64_t) io->len >= conn->cl) {
	4532	call_http_client_handler(conn);
	4533	}
4536	4534	}
4537	4535
4538	4536	struct mg_connection mg_connect(struct mg_server server, const char *host,
4539		int port, int use_ssl) {
4540		struct ns_connection *nsconn;
4541		struct connection *conn;
	4537	int port, int use_ssl) {
	4538	struct ns_connection *nsconn;
	4539	struct connection *conn;
4542	4540
4543		nsconn = ns_connect(&server->ns_server, host, port, use_ssl, NULL);
4544		if (nsconn == NULL) return 0;
	4541	nsconn = ns_connect(&server->ns_server, host, port, use_ssl, NULL);
	4542	if (nsconn == NULL) return 0;
4545	4543
4546		if ((conn = (struct connection ) calloc(1, sizeof(conn))) == NULL) {
4547		nsconn->flags \|= NSF_CLOSE_IMMEDIATELY;
4548		return 0;
4549		}
	4544	if ((conn = (struct connection ) calloc(1, sizeof(conn))) == NULL) {
	4545	nsconn->flags \|= NSF_CLOSE_IMMEDIATELY;
	4546	return 0;
	4547	}
4550	4548
4551		// Interlink two structs
4552		conn->ns_conn = nsconn;
4553		nsconn->connection_data = conn;
	4549	// Interlink two structs
	4550	conn->ns_conn = nsconn;
	4551	nsconn->connection_data = conn;
4554	4552
4555		conn->server = server;
4556		conn->endpoint_type = EP_CLIENT;
4557		//conn->handler = handler;
4558		conn->mg_conn.server_param = server->ns_server.server_data;
4559		conn->ns_conn->flags = NSF_CONNECTING;
	4553	conn->server = server;
	4554	conn->endpoint_type = EP_CLIENT;
	4555	//conn->handler = handler;
	4556	conn->mg_conn.server_param = server->ns_server.server_data;
	4557	conn->ns_conn->flags = NSF_CONNECTING;
4560	4558
4561		return &conn->mg_conn;
	4559	return &conn->mg_conn;
4562	4560	}
4563	4561
4564	4562	#ifndef MONGOOSE_NO_LOGGING
4565	4563	static void log_header(const struct mg_connection conn, const char header,
4566		FILE *fp) {
4567		const char *header_value;
	4564	FILE *fp) {
	4565	const char *header_value;
4568	4566
4569		if ((header_value = mg_get_header(conn, header)) == NULL) {
4570		(void) fprintf(fp, "%s", " -");
4571		} else {
4572		(void) fprintf(fp, " \"%s\"", header_value);
4573		}
	4567	if ((header_value = mg_get_header(conn, header)) == NULL) {
	4568	(void) fprintf(fp, "%s", " -");
	4569	} else {
	4570	(void) fprintf(fp, " \"%s\"", header_value);
	4571	}
4574	4572	}
4575	4573
4576	4574	static void log_access(const struct connection conn, const char path) {
4577		const struct mg_connection *c = &conn->mg_conn;
4578		FILE *fp = (path == NULL) ? NULL : fopen(path, "a+");
4579		char date[64], user[100];
4580		time_t now;
	4575	const struct mg_connection *c = &conn->mg_conn;
	4576	FILE *fp = (path == NULL) ? NULL : fopen(path, "a+");
	4577	char date[64], user[100];
	4578	time_t now;
4581	4579
4582		if (fp == NULL) return;
4583		now = time(NULL);
4584		strftime(date, sizeof(date), "%d/%b/%Y:%H:%M:%S %z", localtime(&now));
	4580	if (fp == NULL) return;
	4581	now = time(NULL);
	4582	strftime(date, sizeof(date), "%d/%b/%Y:%H:%M:%S %z", localtime(&now));
4585	4583
4586		flockfile(fp);
4587		mg_parse_header(mg_get_header(&conn->mg_conn, "Authorization"), "username",
4588		user, sizeof(user));
4589		fprintf(fp, "%s - %s [%s] \"%s %s%s%s HTTP/%s\" %d 0",
4590		c->remote_ip, user[0] == '\0' ? "-" : user, date,
4591		c->request_method ? c->request_method : "-",
4592		c->uri ? c->uri : "-", c->query_string ? "?" : "",
4593		c->query_string ? c->query_string : "",
4594		c->http_version, c->status_code);
4595		log_header(c, "Referer", fp);
4596		log_header(c, "User-Agent", fp);
4597		fputc('\n', fp);
4598		fflush(fp);
	4584	flockfile(fp);
	4585	mg_parse_header(mg_get_header(&conn->mg_conn, "Authorization"), "username",
	4586	user, sizeof(user));
	4587	fprintf(fp, "%s - %s [%s] \"%s %s%s%s HTTP/%s\" %d 0",
	4588	c->remote_ip, user[0] == '\0' ? "-" : user, date,
	4589	c->request_method ? c->request_method : "-",
	4590	c->uri ? c->uri : "-", c->query_string ? "?" : "",
	4591	c->query_string ? c->query_string : "",
	4592	c->http_version, c->status_code);
	4593	log_header(c, "Referer", fp);
	4594	log_header(c, "User-Agent", fp);
	4595	fputc('\n', fp);
	4596	fflush(fp);
4599	4597
4600		funlockfile(fp);
4601		fclose(fp);
	4598	funlockfile(fp);
	4599	fclose(fp);
4602	4600	}
4603	4601	#endif
4604	4602
4605	4603	static void close_local_endpoint(struct connection *conn) {
4606		struct mg_connection *c = &conn->mg_conn;
4607		// Must be done before free()
4608		int keep_alive = should_keep_alive(&conn->mg_conn) &&
4609		(conn->endpoint_type == EP_FILE \|\| conn->endpoint_type == EP_USER);
4610		DBG(("%p %d %d %d", conn, conn->endpoint_type, keep_alive,
4611		conn->ns_conn->flags));
	4604	struct mg_connection *c = &conn->mg_conn;
	4605	// Must be done before free()
	4606	int keep_alive = should_keep_alive(&conn->mg_conn) &&
	4607	(conn->endpoint_type == EP_FILE \|\| conn->endpoint_type == EP_USER);
	4608	DBG(("%p %d %d %d", conn, conn->endpoint_type, keep_alive,
	4609	conn->ns_conn->flags));
4612	4610
4613		switch (conn->endpoint_type) {
4614		case EP_PUT:
4615		case EP_FILE:
4616		close(conn->endpoint.fd);
4617		break;
4618		case EP_CGI:
4619		case EP_PROXY:
4620		if (conn->endpoint.nc != NULL) {
4621		DBG(("%p %p %p :-)", conn, conn->ns_conn, conn->endpoint.nc));
4622		conn->endpoint.nc->flags \|= NSF_CLOSE_IMMEDIATELY;
4623		conn->endpoint.nc->connection_data = NULL;
4624		}
4625		break;
4626		default: break;
4627		}
	4611	switch (conn->endpoint_type) {
	4612	case EP_PUT:
	4613	case EP_FILE:
	4614	close(conn->endpoint.fd);
	4615	break;
	4616	case EP_CGI:
	4617	case EP_PROXY:
	4618	if (conn->endpoint.nc != NULL) {
	4619	DBG(("%p %p %p :-)", conn, conn->ns_conn, conn->endpoint.nc));
	4620	conn->endpoint.nc->flags \|= NSF_CLOSE_IMMEDIATELY;
	4621	conn->endpoint.nc->connection_data = NULL;
	4622	}
	4623	break;
	4624	default: break;
	4625	}
4628	4626
4629	4627	#ifndef MONGOOSE_NO_LOGGING
4630		if (c->status_code > 0 && conn->endpoint_type != EP_CLIENT &&
4631		c->status_code != 400) {
4632		log_access(conn, conn->server->config_options[ACCESS_LOG_FILE]);
4633		}
	4628	if (c->status_code > 0 && conn->endpoint_type != EP_CLIENT &&
	4629	c->status_code != 400) {
	4630	log_access(conn, conn->server->config_options[ACCESS_LOG_FILE]);
	4631	}
4634	4632	#endif
4635	4633
4636		// Gobble possible POST data sent to the URI handler
4637		iobuf_free(&conn->ns_conn->recv_iobuf);
4638		free(conn->request);
4639		free(conn->path_info);
4640		conn->endpoint.nc = NULL;
4641		conn->request = conn->path_info = NULL;
	4634	// Gobble possible POST data sent to the URI handler
	4635	iobuf_free(&conn->ns_conn->recv_iobuf);
	4636	free(conn->request);
	4637	free(conn->path_info);
	4638	conn->endpoint.nc = NULL;
	4639	conn->request = conn->path_info = NULL;
4642	4640
4643		conn->endpoint_type = EP_NONE;
4644		conn->cl = conn->num_bytes_recv = conn->request_len = 0;
4645		conn->ns_conn->flags &= ~(NSF_FINISHED_SENDING_DATA \|
4646		NSF_BUFFER_BUT_DONT_SEND \| NSF_CLOSE_IMMEDIATELY \|
4647		MG_HEADERS_SENT \| MG_LONG_RUNNING);
	4641	conn->endpoint_type = EP_NONE;
	4642	conn->cl = conn->num_bytes_recv = conn->request_len = 0;
	4643	conn->ns_conn->flags &= ~(NSF_FINISHED_SENDING_DATA \|
	4644	NSF_BUFFER_BUT_DONT_SEND \| NSF_CLOSE_IMMEDIATELY \|
	4645	MG_HEADERS_SENT \| MG_LONG_RUNNING);
4648	4646
4649		// Do not memset() the whole structure, as some of the fields
4650		// (IP addresses & ports, server_param) must survive. Nullify the rest.
4651		c->request_method = c->uri = c->http_version = c->query_string = NULL;
4652		c->num_headers = c->status_code = c->is_websocket = c->content_len = 0;
4653		c->connection_param = c->callback_param = NULL;
	4647	// Do not memset() the whole structure, as some of the fields
	4648	// (IP addresses & ports, server_param) must survive. Nullify the rest.
	4649	c->request_method = c->uri = c->http_version = c->query_string = NULL;
	4650	c->num_headers = c->status_code = c->is_websocket = c->content_len = 0;
	4651	c->connection_param = c->callback_param = NULL;
4654	4652
4655		if (keep_alive) {
4656		on_recv_data(conn); // Can call us recursively if pipelining is used
4657		} else {
4658		conn->ns_conn->flags \|= conn->ns_conn->send_iobuf.len == 0 ?
4659		NSF_CLOSE_IMMEDIATELY : NSF_FINISHED_SENDING_DATA;
4660		}
	4653	if (keep_alive) {
	4654	on_recv_data(conn); // Can call us recursively if pipelining is used
	4655	} else {
	4656	conn->ns_conn->flags \|= conn->ns_conn->send_iobuf.len == 0 ?
	4657	NSF_CLOSE_IMMEDIATELY : NSF_FINISHED_SENDING_DATA;
	4658	}
4661	4659	}
4662	4660
4663	4661	static void transfer_file_data(struct connection *conn) {
4664		char buf[IOBUF_SIZE];
4665		int n;
	4662	char buf[IOBUF_SIZE];
	4663	int n;
4666	4664
4667		// If output buffer is too big, don't send anything. Wait until
4668		// mongoose drains already buffered data to the client.
4669		if (conn->ns_conn->send_iobuf.len > sizeof(buf) * 2) return;
	4665	// If output buffer is too big, don't send anything. Wait until
	4666	// mongoose drains already buffered data to the client.
	4667	if (conn->ns_conn->send_iobuf.len > sizeof(buf) * 2) return;
4670	4668
4671		// Do not send anyt
4672		n = read(conn->endpoint.fd, buf, conn->cl < (int64_t) sizeof(buf) ?
4673		(int) conn->cl : (int) sizeof(buf));
	4669	// Do not send anyt
	4670	n = read(conn->endpoint.fd, buf, conn->cl < (int64_t) sizeof(buf) ?
	4671	(int) conn->cl : (int) sizeof(buf));
4674	4672
4675		if (n <= 0) {
4676		close_local_endpoint(conn);
4677		} else if (n > 0) {
4678		conn->cl -= n;
4679		ns_send(conn->ns_conn, buf, n);
4680		if (conn->cl <= 0) {
4681		close_local_endpoint(conn);
4682		}
4683		}
	4673	if (n <= 0) {
	4674	close_local_endpoint(conn);
	4675	} else if (n > 0) {
	4676	conn->cl -= n;
	4677	ns_send(conn->ns_conn, buf, n);
	4678	if (conn->cl <= 0) {
	4679	close_local_endpoint(conn);
	4680	}
	4681	}
4684	4682	}
4685	4683
4686	4684	int mg_poll_server(struct mg_server *server, int milliseconds) {
4687		return ns_server_poll(&server->ns_server, milliseconds);
	4685	return ns_server_poll(&server->ns_server, milliseconds);
4688	4686	}
4689	4687
4690	4688	void mg_destroy_server(struct mg_server **server) {
4691		if (server != NULL && *server != NULL) {
4692		struct mg_server s = server;
4693		int i;
	4689	if (server != NULL && *server != NULL) {
	4690	struct mg_server s = server;
	4691	int i;
4694	4692
4695		ns_server_free(&s->ns_server);
4696		for (i = 0; i < (int) ARRAY_SIZE(s->config_options); i++) {
4697		free(s->config_options[i]); // It is OK to free(NULL)
4698		}
4699		free(s);
4700		*server = NULL;
4701		}
	4693	ns_server_free(&s->ns_server);
	4694	for (i = 0; i < (int) ARRAY_SIZE(s->config_options); i++) {
	4695	free(s->config_options[i]); // It is OK to free(NULL)
	4696	}
	4697	free(s);
	4698	*server = NULL;
	4699	}
4702	4700	}
4703	4701
4704	4702	struct mg_iterator {
4705		mg_handler_t cb;
4706		void *param;
	4703	mg_handler_t cb;
	4704	void *param;
4707	4705	};
4708	4706
4709	4707	static void iter(struct ns_connection nsconn, enum ns_event ev, void param) {
4710		if (ev == NS_POLL) {
4711		struct mg_iterator it = (struct mg_iterator ) param;
4712		struct connection c = (struct connection ) nsconn->connection_data;
4713		if (c != NULL) c->mg_conn.callback_param = it->param;
4714		it->cb(&c->mg_conn, MG_POLL);
4715		}
	4708	if (ev == NS_POLL) {
	4709	struct mg_iterator it = (struct mg_iterator ) param;
	4710	struct connection c = (struct connection ) nsconn->connection_data;
	4711	if (c != NULL) c->mg_conn.callback_param = it->param;
	4712	it->cb(&c->mg_conn, MG_POLL);
	4713	}
4716	4714	}
4717	4715
4718	4716	struct mg_connection mg_next(struct mg_server s, struct mg_connection *c) {
4719		struct connection *conn = MG_CONN_2_CONN(c);
4720		struct ns_connection *nc = ns_next(&s->ns_server,
4721		c == NULL ? NULL : conn->ns_conn);
	4717	struct connection *conn = MG_CONN_2_CONN(c);
	4718	struct ns_connection *nc = ns_next(&s->ns_server,
	4719	c == NULL ? NULL : conn->ns_conn);
4722	4720
4723		return nc == NULL ? NULL :
4724		& ((struct connection *) nc->connection_data)->mg_conn;
	4721	return nc == NULL ? NULL :
	4722	& ((struct connection *) nc->connection_data)->mg_conn;
4725	4723	}
4726	4724
4727	4725	// Apply function to all active connections.
4728	4726	void mg_iterate_over_connections(struct mg_server *server, mg_handler_t cb,
4729		void *param) {
4730		struct mg_iterator it = { cb, param };
4731		ns_iterate(&server->ns_server, iter, &it);
	4727	void *param) {
	4728	struct mg_iterator it = { cb, param };
	4729	ns_iterate(&server->ns_server, iter, &it);
4732	4730	}
4733	4731
4734	4732	static int get_var(const char data, size_t data_len, const char name,
4735		char *dst, size_t dst_len) {
4736		const char p, e, *s;
4737		size_t name_len;
4738		int len;
	4733	char *dst, size_t dst_len) {
	4734	const char p, e, *s;
	4735	size_t name_len;
	4736	int len;
4739	4737
4740		if (dst == NULL \|\| dst_len == 0) {
4741		len = -2;
4742		} else if (data == NULL \|\| name == NULL \|\| data_len == 0) {
4743		len = -1;
4744		dst[0] = '\0';
4745		} else {
4746		name_len = strlen(name);
4747		e = data + data_len;
4748		len = -1;
4749		dst[0] = '\0';
	4738	if (dst == NULL \|\| dst_len == 0) {
	4739	len = -2;
	4740	} else if (data == NULL \|\| name == NULL \|\| data_len == 0) {
	4741	len = -1;
	4742	dst[0] = '\0';
	4743	} else {
	4744	name_len = strlen(name);
	4745	e = data + data_len;
	4746	len = -1;
	4747	dst[0] = '\0';
4750	4748
4751		// data is "var1=val1&var2=val2...". Find variable first
4752		for (p = data; p + name_len < e; p++) {
4753		if ((p == data \|\| p[-1] == '&') && p[name_len] == '=' &&
4754		!mg_strncasecmp(name, p, name_len)) {
	4749	// data is "var1=val1&var2=val2...". Find variable first
	4750	for (p = data; p + name_len < e; p++) {
	4751	if ((p == data \|\| p[-1] == '&') && p[name_len] == '=' &&
	4752	!mg_strncasecmp(name, p, name_len)) {
	4753	// Point p to variable value
	4754	p += name_len + 1;
4755	4755
4756		// Point p to variable value
4757		p += name_len + 1;
	4756	// Point s to the end of the value
	4757	s = (const char *) memchr(p, '&', (size_t)(e - p));
	4758	if (s == NULL) {
	4759	s = e;
	4760	}
	4761	assert(s >= p);
4758	4762
4759		// Point s to the end of the value
4760		s = (const char *) memchr(p, '&', (size_t)(e - p));
4761		if (s == NULL) {
4762		s = e;
4763		}
4764		assert(s >= p);
	4763	// Decode variable into destination buffer
	4764	len = mg_url_decode(p, (size_t)(s - p), dst, dst_len, 1);
4765	4765
4766		// Decode variable into destination buffer
4767		len = mg_url_decode(p, (size_t)(s - p), dst, dst_len, 1);
	4766	// Redirect error code from -1 to -2 (destination buffer too small).
	4767	if (len == -1) {
	4768	len = -2;
	4769	}
	4770	break;
	4771	}
	4772	}
	4773	}
4768	4774
4769		// Redirect error code from -1 to -2 (destination buffer too small).
4770		if (len == -1) {
4771		len = -2;
4772		}
4773		break;
4774		}
4775		}
4776		}
4777
4778		return len;
	4775	return len;
4779	4776	}
4780	4777
4781	4778	int mg_get_var(const struct mg_connection conn, const char name,
4782		char *dst, size_t dst_len) {
4783		int len = get_var(conn->query_string, conn->query_string == NULL ? 0 :
4784		strlen(conn->query_string), name, dst, dst_len);
4785		if (len < 0) {
4786		len = get_var(conn->content, conn->content_len, name, dst, dst_len);
4787		}
4788		return len;
	4779	char *dst, size_t dst_len) {
	4780	int len = get_var(conn->query_string, conn->query_string == NULL ? 0 :
	4781	strlen(conn->query_string), name, dst, dst_len);
	4782	if (len < 0) {
	4783	len = get_var(conn->content, conn->content_len, name, dst, dst_len);
	4784	}
	4785	return len;
4789	4786	}
4790	4787
4791	4788	static int get_line_len(const char *buf, int buf_len) {
4792		int len = 0;
4793		while (len < buf_len && buf[len] != '\n') len++;
4794		return buf[len] == '\n' ? len + 1: -1;
	4789	int len = 0;
	4790	while (len < buf_len && buf[len] != '\n') len++;
	4791	return buf[len] == '\n' ? len + 1: -1;
4795	4792	}
4796	4793
4797	4794	int mg_parse_multipart(const char *buf, int buf_len,
4798		char *var_name, int var_name_len,
4799		char *file_name, int file_name_len,
4800		const char *data, int data_len) {
4801		static const char cd[] = "Content-Disposition: ";
4802		//struct mg_connection c;
4803		int hl, bl, n, ll, pos, cdl = sizeof(cd) - 1;
4804		//char *p;
	4795	char *var_name, int var_name_len,
	4796	char *file_name, int file_name_len,
	4797	const char *data, int data_len) {
	4798	static const char cd[] = "Content-Disposition: ";
	4799	//struct mg_connection c;
	4800	int hl, bl, n, ll, pos, cdl = sizeof(cd) - 1;
	4801	//char *p;
4805	4802
4806		if (buf == NULL \|\| buf_len <= 0) return 0;
4807		if ((hl = get_request_len(buf, buf_len)) <= 0) return 0;
4808		if (buf[0] != '-' \|\| buf[1] != '-' \|\| buf[2] == '\n') return 0;
	4803	if (buf == NULL \|\| buf_len <= 0) return 0;
	4804	if ((hl = get_request_len(buf, buf_len)) <= 0) return 0;
	4805	if (buf[0] != '-' \|\| buf[1] != '-' \|\| buf[2] == '\n') return 0;
4809	4806
4810		// Get boundary length
4811		bl = get_line_len(buf, buf_len);
	4807	// Get boundary length
	4808	bl = get_line_len(buf, buf_len);
4812	4809
4813		// Loop through headers, fetch variable name and file name
4814		var_name[0] = file_name[0] = '\0';
4815		for (n = bl; (ll = get_line_len(buf + n, hl - n)) > 0; n += ll) {
4816		if (mg_strncasecmp(cd, buf + n, cdl) == 0) {
4817		parse_header(buf + n + cdl, ll - (cdl + 2), "name",
4818		var_name, var_name_len);
4819		parse_header(buf + n + cdl, ll - (cdl + 2), "filename",
4820		file_name, file_name_len);
4821		}
4822		}
	4810	// Loop through headers, fetch variable name and file name
	4811	var_name[0] = file_name[0] = '\0';
	4812	for (n = bl; (ll = get_line_len(buf + n, hl - n)) > 0; n += ll) {
	4813	if (mg_strncasecmp(cd, buf + n, cdl) == 0) {
	4814	parse_header(buf + n + cdl, ll - (cdl + 2), "name",
	4815	var_name, var_name_len);
	4816	parse_header(buf + n + cdl, ll - (cdl + 2), "filename",
	4817	file_name, file_name_len);
	4818	}
	4819	}
4823	4820
4824		// Scan body, search for terminating boundary
4825		for (pos = hl; pos + (bl - 2) < buf_len; pos++) {
4826		if (buf[pos] == '-' && !memcmp(buf, &buf[pos], bl - 2)) {
4827		if (data_len != NULL) *data_len = (pos - 2) - hl;
4828		if (data != NULL) *data = buf + hl;
4829		return pos;
4830		}
4831		}
	4821	// Scan body, search for terminating boundary
	4822	for (pos = hl; pos + (bl - 2) < buf_len; pos++) {
	4823	if (buf[pos] == '-' && !memcmp(buf, &buf[pos], bl - 2)) {
	4824	if (data_len != NULL) *data_len = (pos - 2) - hl;
	4825	if (data != NULL) *data = buf + hl;
	4826	return pos;
	4827	}
	4828	}
4832	4829
4833		return 0;
	4830	return 0;
4834	4831	}
4835	4832
4836	4833	const char **mg_get_valid_option_names(void) {
4837		return static_config_options;
	4834	return static_config_options;
4838	4835	}
4839	4836
4840	4837	static int get_option_index(const char *name) {
4841		int i;
	4838	int i;
4842	4839
4843		for (i = 0; static_config_options[i * 2] != NULL; i++) {
4844		if (strcmp(static_config_options[i * 2], name) == 0) {
4845		return i;
4846		}
4847		}
4848		return -1;
	4840	for (i = 0; static_config_options[i * 2] != NULL; i++) {
	4841	if (strcmp(static_config_options[i * 2], name) == 0) {
	4842	return i;
	4843	}
	4844	}
	4845	return -1;
4849	4846	}
4850	4847
4851	4848	static void set_default_option_values(char **opts) {
4852		const char value, *all_opts = mg_get_valid_option_names();
4853		int i;
	4849	const char value, *all_opts = mg_get_valid_option_names();
	4850	int i;
4854	4851
4855		for (i = 0; all_opts[i * 2] != NULL; i++) {
4856		value = all_opts[i * 2 + 1];
4857		if (opts[i] == NULL && value != NULL) {
4858		opts[i] = mg_strdup(value);
4859		}
4860		}
	4852	for (i = 0; all_opts[i * 2] != NULL; i++) {
	4853	value = all_opts[i * 2 + 1];
	4854	if (opts[i] == NULL && value != NULL) {
	4855	opts[i] = mg_strdup(value);
	4856	}
	4857	}
4861	4858	}
4862	4859
4863	4860	const char mg_set_option(struct mg_server server, const char *name,
4864		const char *value) {
4865		int ind = get_option_index(name);
4866		const char *error_msg = NULL;
4867		char **v = NULL;
	4861	const char *value) {
	4862	int ind = get_option_index(name);
	4863	const char *error_msg = NULL;
	4864	char **v = NULL;
4868	4865
4869		if (ind < 0) return "No such option";
4870		v = &server->config_options[ind];
	4866	if (ind < 0) return "No such option";
	4867	v = &server->config_options[ind];
4871	4868
4872		// Return success immediately if setting to the same value
4873		if ((*v == NULL && value == NULL) \|\|
4874		(value != NULL && v != NULL && !strcmp(value, v))) {
4875		return NULL;
4876		}
	4869	// Return success immediately if setting to the same value
	4870	if ((*v == NULL && value == NULL) \|\|
	4871	(value != NULL && v != NULL && !strcmp(value, v))) {
	4872	return NULL;
	4873	}
4877	4874
4878		if (*v != NULL) {
4879		free(*v);
4880		*v = NULL;
4881		}
	4875	if (*v != NULL) {
	4876	free(*v);
	4877	*v = NULL;
	4878	}
4882	4879
4883		if (value == NULL \|\| value[0] == '\0') return NULL;
	4880	if (value == NULL \|\| value[0] == '\0') return NULL;
4884	4881
4885		*v = mg_strdup(value);
4886		DBG(("%s [%s]", name, *v));
	4882	*v = mg_strdup(value);
	4883	DBG(("%s [%s]", name, *v));
4887	4884
4888		if (ind == LISTENING_PORT) {
4889		int port = ns_bind(&server->ns_server, value);
4890		if (port < 0) {
4891		error_msg = "Cannot bind to port";
4892		} else {
4893		char buf[100];
4894		ns_sock_to_str(server->ns_server.listening_sock, buf, sizeof(buf), 2);
4895		free(*v);
4896		*v = mg_strdup(buf);
4897		}
	4885	if (ind == LISTENING_PORT) {
	4886	int port = ns_bind(&server->ns_server, value);
	4887	if (port < 0) {
	4888	error_msg = "Cannot bind to port";
	4889	} else {
	4890	char buf[100];
	4891	ns_sock_to_str(server->ns_server.listening_sock, buf, sizeof(buf), 2);
	4892	free(*v);
	4893	*v = mg_strdup(buf);
	4894	}
4898	4895	#ifndef MONGOOSE_NO_FILESYSTEM
4899		} else if (ind == HEXDUMP_FILE) {
4900		server->ns_server.hexdump_file = *v;
	4896	} else if (ind == HEXDUMP_FILE) {
	4897	server->ns_server.hexdump_file = *v;
4901	4898	#endif
4902	4899	#ifndef _WIN32
4903		} else if (ind == RUN_AS_USER) {
4904		struct passwd *pw;
4905		if ((pw = getpwnam(value)) == NULL) {
4906		error_msg = "Unknown user";
4907		} else if (setgid(pw->pw_gid) != 0) {
4908		error_msg = "setgid() failed";
4909		} else if (setuid(pw->pw_uid) != 0) {
4910		error_msg = "setuid() failed";
4911		}
	4900	} else if (ind == RUN_AS_USER) {
	4901	struct passwd *pw;
	4902	if ((pw = getpwnam(value)) == NULL) {
	4903	error_msg = "Unknown user";
	4904	} else if (setgid(pw->pw_gid) != 0) {
	4905	error_msg = "setgid() failed";
	4906	} else if (setuid(pw->pw_uid) != 0) {
	4907	error_msg = "setuid() failed";
	4908	}
4912	4909	#endif
4913	4910	#ifdef NS_ENABLE_SSL
4914		} else if (ind == SSL_CERTIFICATE) {
4915		int res = ns_set_ssl_cert(&server->ns_server, value);
4916		if (res == -2) {
4917		error_msg = "Cannot load PEM";
4918		} else if (res == -3) {
4919		error_msg = "SSL not enabled";
4920		} else if (res == -1) {
4921		error_msg = "SSL_CTX_new() failed";
4922		}
4923		} else if (ind == SSL_CA_CERTIFICATE) {
4924		if (ns_set_ssl_ca_cert(&server->ns_server, value) != 0) {
4925		error_msg = "Error setting CA cert";
4926		}
	4911	} else if (ind == SSL_CERTIFICATE) {
	4912	int res = ns_set_ssl_cert(&server->ns_server, value);
	4913	if (res == -2) {
	4914	error_msg = "Cannot load PEM";
	4915	} else if (res == -3) {
	4916	error_msg = "SSL not enabled";
	4917	} else if (res == -1) {
	4918	error_msg = "SSL_CTX_new() failed";
	4919	}
	4920	} else if (ind == SSL_CA_CERTIFICATE) {
	4921	if (ns_set_ssl_ca_cert(&server->ns_server, value) != 0) {
	4922	error_msg = "Error setting CA cert";
	4923	}
4927	4924	#endif
4928		}
	4925	}
4929	4926
4930		return error_msg;
	4927	return error_msg;
4931	4928	}
4932	4929
4933	4930	static void set_ips(struct ns_connection *nc, int is_rem) {
4934		struct connection conn = (struct connection ) nc->connection_data;
4935		struct mg_connection *c = &conn->mg_conn;
4936		char buf[100];
	4931	struct connection conn = (struct connection ) nc->connection_data;
	4932	struct mg_connection *c = &conn->mg_conn;
	4933	char buf[100];
4937	4934
4938		ns_sock_to_str(nc->sock, buf, sizeof(buf), is_rem ? 7 : 3);
4939		sscanf(buf, "%47[^:]:%hu",
4940		is_rem ? c->remote_ip : c->local_ip,
4941		is_rem ? &c->remote_port : &c->local_port);
4942		//DBG(("%p %s %s", conn, is_rem ? "rem" : "loc", buf));
	4935	ns_sock_to_str(nc->sock, buf, sizeof(buf), is_rem ? 7 : 3);
	4936	sscanf(buf, "%47[^:]:%hu",
	4937	is_rem ? c->remote_ip : c->local_ip,
	4938	is_rem ? &c->remote_port : &c->local_port);
	4939	//DBG(("%p %s %s", conn, is_rem ? "rem" : "loc", buf));
4943	4940	}
4944	4941
4945	4942	static void on_accept(struct ns_connection nc, union socket_address sa) {
4946		struct mg_server server = (struct mg_server ) nc->server;
4947		struct connection *conn;
	4943	struct mg_server server = (struct mg_server ) nc->server;
	4944	struct connection *conn;
4948	4945
4949		if (!check_acl(server->config_options[ACCESS_CONTROL_LIST],
4950		ntohl(* (uint32_t *) &sa->sin.sin_addr)) \|\|
4951		(conn = (struct connection ) calloc(1, sizeof(conn))) == NULL) {
4952		nc->flags \|= NSF_CLOSE_IMMEDIATELY;
4953		} else {
4954		// Circularly link two connection structures
4955		nc->connection_data = conn;
4956		conn->ns_conn = nc;
	4946	if (!check_acl(server->config_options[ACCESS_CONTROL_LIST],
	4947	ntohl(* (uint32_t *) &sa->sin.sin_addr)) \|\|
	4948	(conn = (struct connection ) calloc(1, sizeof(conn))) == NULL) {
	4949	nc->flags \|= NSF_CLOSE_IMMEDIATELY;
	4950	} else {
	4951	// Circularly link two connection structures
	4952	nc->connection_data = conn;
	4953	conn->ns_conn = nc;
4957	4954
4958		// Initialize the rest of connection attributes
4959		conn->server = server;
4960		conn->mg_conn.server_param = nc->server->server_data;
4961		set_ips(nc, 1);
4962		set_ips(nc, 0);
4963		}
	4955	// Initialize the rest of connection attributes
	4956	conn->server = server;
	4957	conn->mg_conn.server_param = nc->server->server_data;
	4958	set_ips(nc, 1);
	4959	set_ips(nc, 0);
	4960	}
4964	4961	}
4965	4962
4966	4963	static void mg_ev_handler(struct ns_connection nc, enum ns_event ev, void p) {
4967		struct connection conn = (struct connection ) nc->connection_data;
	4964	struct connection conn = (struct connection ) nc->connection_data;
4968	4965
4969		// Send NS event to the handler. Note that call_user won't send an event
4970		// if conn == NULL. Therefore, repeat this for NS_ACCEPT event as well.
	4966	// Send NS event to the handler. Note that call_user won't send an event
	4967	// if conn == NULL. Therefore, repeat this for NS_ACCEPT event as well.
4971	4968	#ifdef MONGOOSE_SEND_NS_EVENTS
4972		{
4973		struct connection conn = (struct connection ) nc->connection_data;
4974		void *param[2] = { nc, p };
4975		if (conn != NULL) conn->mg_conn.callback_param = param;
4976		call_user(conn, (enum mg_event) ev);
4977		}
	4969	{
	4970	struct connection conn = (struct connection ) nc->connection_data;
	4971	void *param[2] = { nc, p };
	4972	if (conn != NULL) conn->mg_conn.callback_param = param;
	4973	call_user(conn, (enum mg_event) ev);
	4974	}
4978	4975	#endif
4979	4976
4980		switch (ev) {
4981		case NS_ACCEPT:
4982		on_accept(nc, (union socket_address *) p);
	4977	switch (ev) {
	4978	case NS_ACCEPT:
	4979	on_accept(nc, (union socket_address *) p);
4983	4980	#ifdef MONGOOSE_SEND_NS_EVENTS
4984		{
4985		struct connection conn = (struct connection ) nc->connection_data;
4986		void *param[2] = { nc, p };
4987		if (conn != NULL) conn->mg_conn.callback_param = param;
4988		call_user(conn, (enum mg_event) ev);
4989		}
	4981	{
	4982	struct connection conn = (struct connection ) nc->connection_data;
	4983	void *param[2] = { nc, p };
	4984	if (conn != NULL) conn->mg_conn.callback_param = param;
	4985	call_user(conn, (enum mg_event) ev);
	4986	}
4990	4987	#endif
4991		break;
	4988	break;
4992	4989
4993		case NS_CONNECT:
4994		if (nc->connection_data != NULL) {
4995		set_ips(nc, 1);
4996		set_ips(nc, 0);
4997		}
4998		conn->mg_conn.status_code = * (int *) p;
4999		if (conn->mg_conn.status_code != 0 \|\|
5000		(!(nc->flags & MG_PROXY_CONN) &&
5001		call_user(conn, MG_CONNECT) == MG_FALSE)) {
5002		nc->flags \|= NSF_CLOSE_IMMEDIATELY;
5003		}
5004		break;
	4990	case NS_CONNECT:
	4991	if (nc->connection_data != NULL) {
	4992	set_ips(nc, 1);
	4993	set_ips(nc, 0);
	4994	}
	4995	conn->mg_conn.status_code = * (int *) p;
	4996	if (conn->mg_conn.status_code != 0 \|\|
	4997	(!(nc->flags & MG_PROXY_CONN) &&
	4998	call_user(conn, MG_CONNECT) == MG_FALSE)) {
	4999	nc->flags \|= NSF_CLOSE_IMMEDIATELY;
	5000	}
	5001	break;
5005	5002
5006		case NS_RECV:
5007		if (conn != NULL) {
5008		conn->num_bytes_recv += * (int *) p;
5009		}
5010		if (nc->flags & NSF_ACCEPTED) {
5011		on_recv_data(conn);
	5003	case NS_RECV:
	5004	if (conn != NULL) {
	5005	conn->num_bytes_recv += * (int *) p;
	5006	}
	5007	if (nc->flags & NSF_ACCEPTED) {
	5008	on_recv_data(conn);
5012	5009	#ifndef MONGOOSE_NO_CGI
5013		} else if (nc->flags & MG_CGI_CONN) {
5014		on_cgi_data(nc);
	5010	} else if (nc->flags & MG_CGI_CONN) {
	5011	on_cgi_data(nc);
5015	5012	#endif
5016		} else if (nc->flags & MG_PROXY_CONN) {
5017		if (conn != NULL) {
5018		ns_forward(nc, conn->ns_conn);
5019		}
5020		} else {
5021		process_response(conn);
5022		}
5023		break;
	5013	} else if (nc->flags & MG_PROXY_CONN) {
	5014	if (conn != NULL) {
	5015	ns_forward(nc, conn->ns_conn);
	5016	}
	5017	} else {
	5018	process_response(conn);
	5019	}
	5020	break;
5024	5021
5025		case NS_SEND:
5026		break;
	5022	case NS_SEND:
	5023	break;
5027	5024
5028		case NS_CLOSE:
5029		nc->connection_data = NULL;
5030		if (nc->flags & (MG_CGI_CONN \| MG_PROXY_CONN)) {
5031		DBG(("%p %p closing cgi/proxy conn", conn, nc));
5032		if (conn && conn->ns_conn) {
5033		conn->ns_conn->flags &= ~NSF_BUFFER_BUT_DONT_SEND;
5034		conn->ns_conn->flags \|= conn->ns_conn->send_iobuf.len > 0 ?
5035		NSF_FINISHED_SENDING_DATA : NSF_CLOSE_IMMEDIATELY;
5036		conn->endpoint.nc = NULL;
5037		}
5038		} else if (conn != NULL) {
5039		DBG(("%p %p %d closing", conn, nc, conn->endpoint_type));
	5025	case NS_CLOSE:
	5026	nc->connection_data = NULL;
	5027	if (nc->flags & (MG_CGI_CONN \| MG_PROXY_CONN)) {
	5028	DBG(("%p %p closing cgi/proxy conn", conn, nc));
	5029	if (conn && conn->ns_conn) {
	5030	conn->ns_conn->flags &= ~NSF_BUFFER_BUT_DONT_SEND;
	5031	conn->ns_conn->flags \|= conn->ns_conn->send_iobuf.len > 0 ?
	5032	NSF_FINISHED_SENDING_DATA : NSF_CLOSE_IMMEDIATELY;
	5033	conn->endpoint.nc = NULL;
	5034	}
	5035	} else if (conn != NULL) {
	5036	DBG(("%p %p %d closing", conn, nc, conn->endpoint_type));
5040	5037
5041		if (conn->endpoint_type == EP_CLIENT && nc->recv_iobuf.len > 0) {
5042		call_http_client_handler(conn);
5043		}
	5038	if (conn->endpoint_type == EP_CLIENT && nc->recv_iobuf.len > 0) {
	5039	call_http_client_handler(conn);
	5040	}
5044	5041
5045		call_user(conn, MG_CLOSE);
5046		close_local_endpoint(conn);
5047		conn->ns_conn = NULL;
5048		free(conn);
5049		}
5050		break;
	5042	call_user(conn, MG_CLOSE);
	5043	close_local_endpoint(conn);
	5044	conn->ns_conn = NULL;
	5045	free(conn);
	5046	}
	5047	break;
5051	5048
5052		case NS_POLL:
5053		if (conn != NULL) {
5054		if (call_user(conn, MG_POLL) == MG_TRUE) {
5055		if (conn->ns_conn->flags & MG_HEADERS_SENT) {
5056		write_terminating_chunk(conn);
5057		}
5058		close_local_endpoint(conn);
5059		}
	5049	case NS_POLL:
	5050	if (conn != NULL) {
	5051	if (call_user(conn, MG_POLL) == MG_TRUE) {
	5052	if (conn->ns_conn->flags & MG_HEADERS_SENT) {
	5053	write_terminating_chunk(conn);
	5054	}
	5055	close_local_endpoint(conn);
	5056	}
5060	5057
5061		if (conn->endpoint_type == EP_FILE) {
5062		transfer_file_data(conn);
5063		}
5064		}
	5058	if (conn->endpoint_type == EP_FILE) {
	5059	transfer_file_data(conn);
	5060	}
	5061	}
5065	5062
5066		// Expire idle connections
5067		{
5068		time_t current_time = * (time_t *) p;
	5063	// Expire idle connections
	5064	{
	5065	time_t current_time = * (time_t *) p;
5069	5066
5070		if (conn != NULL && conn->mg_conn.is_websocket) {
5071		ping_idle_websocket_connection(conn, current_time);
5072		}
	5067	if (conn != NULL && conn->mg_conn.is_websocket) {
	5068	ping_idle_websocket_connection(conn, current_time);
	5069	}
5073	5070
5074		if (nc->last_io_time + MONGOOSE_IDLE_TIMEOUT_SECONDS < current_time) {
5075		mg_ev_handler(nc, NS_CLOSE, NULL);
5076		nc->flags \|= NSF_CLOSE_IMMEDIATELY;
5077		}
5078		}
5079		break;
	5071	if (nc->last_io_time + MONGOOSE_IDLE_TIMEOUT_SECONDS < current_time) {
	5072	mg_ev_handler(nc, NS_CLOSE, NULL);
	5073	nc->flags \|= NSF_CLOSE_IMMEDIATELY;
	5074	}
	5075	}
	5076	break;
5080	5077
5081		default:
5082		break;
5083		}
	5078	default:
	5079	break;
	5080	}
5084	5081	}
5085	5082
5086	5083	static void iter2(struct ns_connection nc, enum ns_event ev, void param) {
5087		mg_handler_t func = NULL;
5088		struct connection conn = (struct connection ) nc->connection_data;
5089		const char msg = (const char ) param;
5090		int n;
5091		(void) ev;
	5084	mg_handler_t func = NULL;
	5085	struct connection conn = (struct connection ) nc->connection_data;
	5086	const char msg = (const char ) param;
	5087	int n;
	5088	(void) ev;
5092	5089
5093		//DBG(("%p [%s]", conn, msg));
5094		if (sscanf(msg, "%p %n", &func, &n) && func != NULL) {
5095		conn->mg_conn.callback_param = (void *) (msg + n);
5096		func(&conn->mg_conn, MG_POLL);
5097		}
	5090	//DBG(("%p [%s]", conn, msg));
	5091	if (sscanf(msg, "%p %n", &func, &n) && func != NULL) {
	5092	conn->mg_conn.callback_param = (void *) (msg + n);
	5093	func(&conn->mg_conn, MG_POLL);
	5094	}
5098	5095	}
5099	5096
5100	5097	void mg_wakeup_server_ex(struct mg_server *server, mg_handler_t cb,
5101		const char *fmt, ...) {
5102		va_list ap;
5103		char buf[8 * 1024];
5104		int len;
	5098	const char *fmt, ...) {
	5099	va_list ap;
	5100	char buf[8 * 1024];
	5101	int len;
5105	5102
5106		// Encode callback (cb) into a buffer
5107		len = snprintf(buf, sizeof(buf), "%p ", cb);
5108		va_start(ap, fmt);
5109		len += vsnprintf(buf + len, sizeof(buf) - len, fmt, ap);
5110		va_end(ap);
	5103	// Encode callback (cb) into a buffer
	5104	len = snprintf(buf, sizeof(buf), "%p ", cb);
	5105	va_start(ap, fmt);
	5106	len += vsnprintf(buf + len, sizeof(buf) - len, fmt, ap);
	5107	va_end(ap);
5111	5108
5112		// "len + 1" is to include terminating \0 in the message
5113		ns_server_wakeup_ex(&server->ns_server, iter2, buf, len + 1);
	5109	// "len + 1" is to include terminating \0 in the message
	5110	ns_server_wakeup_ex(&server->ns_server, iter2, buf, len + 1);
5114	5111	}
5115	5112
5116	5113	void mg_wakeup_server(struct mg_server *server) {
5117		ns_server_wakeup_ex(&server->ns_server, NULL, (void *) "", 0);
	5114	ns_server_wakeup_ex(&server->ns_server, NULL, (void *) "", 0);
5118	5115	}
5119	5116
5120	5117	void mg_set_listening_socket(struct mg_server *server, int sock) {
5121		if (server->ns_server.listening_sock != INVALID_SOCKET) {
5122		closesocket(server->ns_server.listening_sock);
5123		}
5124		server->ns_server.listening_sock = (sock_t) sock;
	5118	if (server->ns_server.listening_sock != INVALID_SOCKET) {
	5119	closesocket(server->ns_server.listening_sock);
	5120	}
	5121	server->ns_server.listening_sock = (sock_t) sock;
5125	5122	}
5126	5123
5127	5124	int mg_get_listening_socket(struct mg_server *server) {
5128		return server->ns_server.listening_sock;
	5125	return server->ns_server.listening_sock;
5129	5126	}
5130	5127
5131	5128	const char mg_get_option(const struct mg_server server, const char *name) {
5132		const char opts = (const char ) server->config_options;
5133		int i = get_option_index(name);
5134		return i == -1 ? NULL : opts[i] == NULL ? "" : opts[i];
	5129	const char opts = (const char ) server->config_options;
	5130	int i = get_option_index(name);
	5131	return i == -1 ? NULL : opts[i] == NULL ? "" : opts[i];
5135	5132	}
5136	5133
5137	5134	struct mg_server mg_create_server(void server_data, mg_handler_t handler) {
5138		struct mg_server server = (struct mg_server ) calloc(1, sizeof(*server));
5139		ns_server_init(&server->ns_server, server_data, mg_ev_handler);
5140		set_default_option_values(server->config_options);
5141		server->event_handler = handler;
5142		return server;
	5135	struct mg_server server = (struct mg_server ) calloc(1, sizeof(*server));
	5136	ns_server_init(&server->ns_server, server_data, mg_ev_handler);
	5137	set_default_option_values(server->config_options);
	5138	server->event_handler = handler;
	5139	return server;
5143	5140	}
5144	5141
5145	5142	#ifdef _WIN32
5146	5143	static void mmap(void addr, int64_t len, int prot, int flags, int fd,
5147		int offset) {
5148		HANDLE fh = (HANDLE) _get_osfhandle(fd);
5149		HANDLE mh = CreateFileMapping(fh, 0, PAGE_READONLY, 0, 0, 0);
5150		void *p = MapViewOfFile(mh, FILE_MAP_READ, 0, 0, (size_t) len);
5151		CloseHandle(mh);
5152		return p;
	5144	int offset) {
	5145	HANDLE fh = (HANDLE) _get_osfhandle(fd);
	5146	HANDLE mh = CreateFileMapping(fh, 0, PAGE_READONLY, 0, 0, 0);
	5147	void *p = MapViewOfFile(mh, FILE_MAP_READ, 0, 0, (size_t) len);
	5148	CloseHandle(mh);
	5149	return p;
5153	5150	}
5154	5151	#define munmap(x, y) UnmapViewOfFile(x)
5155	5152	#define MAP_FAILED NULL
r32760	r32761
5160	5157	#endif
5161	5158
5162	5159	void mg_mmap(FILE fp, size_t size) {
5163		return mmap(NULL, size, PROT_READ, MAP_PRIVATE, fileno(fp), 0);
	5160	return mmap(NULL, size, PROT_READ, MAP_PRIVATE, fileno(fp), 0);
5164	5161	}
5165	5162
5166	5163	void mg_munmap(void *p, size_t size) {
5167		munmap(p, size);
	5164	munmap(p, size);
5168	5165	}

trunk/src/lib/web/mongoose.h
r32760	r32761
31	31
32	32	// This structure contains information about HTTP request.
33	33	struct mg_connection {
34		const char *request_method; // "GET", "POST", etc
35		const char *uri; // URL-decoded URI
36		const char *http_version; // E.g. "1.0", "1.1"
37		const char *query_string; // URL part after '?', not including '?', or NULL
	34	const char *request_method; // "GET", "POST", etc
	35	const char *uri; // URL-decoded URI
	36	const char *http_version; // E.g. "1.0", "1.1"
	37	const char *query_string; // URL part after '?', not including '?', or NULL
38	38
39		char remote_ip[48]; // Max IPv6 string length is 45 characters
40		char local_ip[48]; // Local IP address
41		unsigned short remote_port; // Client's port
42		unsigned short local_port; // Local port number
	39	char remote_ip[48]; // Max IPv6 string length is 45 characters
	40	char local_ip[48]; // Local IP address
	41	unsigned short remote_port; // Client's port
	42	unsigned short local_port; // Local port number
43	43
44		int num_headers; // Number of HTTP headers
45		struct mg_header {
46		const char *name; // HTTP header name
47		const char *value; // HTTP header value
48		} http_headers[30];
	44	int num_headers; // Number of HTTP headers
	45	struct mg_header {
	46	const char *name; // HTTP header name
	47	const char *value; // HTTP header value
	48	} http_headers[30];
49	49
50		char *content; // POST (or websocket message) data, or NULL
51		size_t content_len; // Data length
	50	char *content; // POST (or websocket message) data, or NULL
	51	size_t content_len; // Data length
52	52
53		int is_websocket; // Connection is a websocket connection
54		int status_code; // HTTP status code for HTTP error handler
55		int wsbits; // First byte of the websocket frame
56		void *server_param; // Parameter passed to mg_add_uri_handler()
57		void *connection_param; // Placeholder for connection-specific data
58		void *callback_param; // Needed by mg_iterate_over_connections()
	53	int is_websocket; // Connection is a websocket connection
	54	int status_code; // HTTP status code for HTTP error handler
	55	int wsbits; // First byte of the websocket frame
	56	void *server_param; // Parameter passed to mg_add_uri_handler()
	57	void *connection_param; // Placeholder for connection-specific data
	58	void *callback_param; // Needed by mg_iterate_over_connections()
59	59	};
60	60
61	61	struct mg_server; // Opaque structure describing server instance
62	62	enum mg_result { MG_FALSE, MG_TRUE, MG_MORE };
63	63	enum mg_event {
64		MG_POLL = 100, // Callback return value is ignored
65		MG_CONNECT, // If callback returns MG_FALSE, connect fails
66		MG_AUTH, // If callback returns MG_FALSE, authentication fails
67		MG_REQUEST, // If callback returns MG_FALSE, Mongoose continues with req
68		MG_REPLY, // If callback returns MG_FALSE, Mongoose closes connection
69		MG_RECV, // Mongoose has received POST data chunk.
70		// Callback should return a number of bytes to discard from
71		// the receive buffer, or -1 to close the connection.
72		MG_CLOSE, // Connection is closed, callback return value is ignored
73		MG_WS_HANDSHAKE, // New websocket connection, handshake request
74		MG_WS_CONNECT, // New websocket connection established
75		MG_HTTP_ERROR // If callback returns MG_FALSE, Mongoose continues with err
	64	MG_POLL = 100, // Callback return value is ignored
	65	MG_CONNECT, // If callback returns MG_FALSE, connect fails
	66	MG_AUTH, // If callback returns MG_FALSE, authentication fails
	67	MG_REQUEST, // If callback returns MG_FALSE, Mongoose continues with req
	68	MG_REPLY, // If callback returns MG_FALSE, Mongoose closes connection
	69	MG_RECV, // Mongoose has received POST data chunk.
	70	// Callback should return a number of bytes to discard from
	71	// the receive buffer, or -1 to close the connection.
	72	MG_CLOSE, // Connection is closed, callback return value is ignored
	73	MG_WS_HANDSHAKE, // New websocket connection, handshake request
	74	MG_WS_CONNECT, // New websocket connection established
	75	MG_HTTP_ERROR // If callback returns MG_FALSE, Mongoose continues with err
76	76	};
77	77	typedef int (mg_handler_t)(struct mg_connection , enum mg_event);
78	78
79	79	// Websocket opcodes, from http://tools.ietf.org/html/rfc6455
80	80	enum {
81		WEBSOCKET_OPCODE_CONTINUATION = 0x0,
82		WEBSOCKET_OPCODE_TEXT = 0x1,
83		WEBSOCKET_OPCODE_BINARY = 0x2,
84		WEBSOCKET_OPCODE_CONNECTION_CLOSE = 0x8,
85		WEBSOCKET_OPCODE_PING = 0x9,
86		WEBSOCKET_OPCODE_PONG = 0xa
	81	WEBSOCKET_OPCODE_CONTINUATION = 0x0,
	82	WEBSOCKET_OPCODE_TEXT = 0x1,
	83	WEBSOCKET_OPCODE_BINARY = 0x2,
	84	WEBSOCKET_OPCODE_CONNECTION_CLOSE = 0x8,
	85	WEBSOCKET_OPCODE_PING = 0x9,
	86	WEBSOCKET_OPCODE_PONG = 0xa
87	87	};
88	88
89	89	// Server management functions
r32760	r32761
110	110	size_t mg_printf(struct mg_connection conn, const char fmt, ...);
111	111
112	112	size_t mg_websocket_write(struct mg_connection *, int opcode,
113		const char *data, size_t data_len);
	113	const char *data, size_t data_len);
114	114	size_t mg_websocket_printf(struct mg_connection* conn, int opcode,
115		const char *fmt, ...);
	115	const char *fmt, ...);
116	116
117	117	void mg_send_file(struct mg_connection , const char path);
118	118	void mg_send_file_data(struct mg_connection *, int fd);
r32760	r32761
120	120	const char mg_get_header(const struct mg_connection , const char *name);
121	121	const char mg_get_mime_type(const char name, const char *default_mime_type);
122	122	int mg_get_var(const struct mg_connection conn, const char var_name,
123		char *buf, size_t buf_len);
	123	char *buf, size_t buf_len);
124	124	int mg_parse_header(const char hdr, const char var_name, char *buf, size_t);
125	125	int mg_parse_multipart(const char *buf, int buf_len,
126		char *var_name, int var_name_len,
127		char *file_name, int file_name_len,
128		const char *data, int data_len);
	126	char *var_name, int var_name_len,
	127	char *file_name, int file_name_len,
	128	const char *data, int data_len);
129	129
130	130	// Utility functions
131	131	void mg_start_thread(void (func)(void ), void *param);
r32760	r32761
141	141
142	142	// Templates support
143	143	struct mg_expansion {
144		const char *keyword;
145		void (handler)(struct mg_connection );
	144	const char *keyword;
	145	void (handler)(struct mg_connection );
146	146	};
147	147	void mg_template(struct mg_connection , const char text,
148		struct mg_expansion *expansions);
	148	struct mg_expansion *expansions);
149	149
150	150
151	151	#ifdef __cplusplus

trunk/src/version.c
r32760	r32761
9	9	***************************************************************************/
10	10
11	11	extern const char build_version[];
12		const char build_version[] = "0.154 (" __DATE__")";
	12	const char build_version[] = "0.155 (" __DATE__")";

trunk/src/mess/drivers/electron.c
r32760	r32761
194	194	/* 24000 9 keyboard mirror */
195	195	/* 28000 10 Basic rom */
196	196	ROM_LOAD( "basic.rom", 0x28000, 0x4000, CRC(79434781) SHA1(4a7393f3a45ea309f744441c16723e2ef447a281) )
197		/* 2c000 11 Basic rom mirror */
	197	/* 2c000 11 Basic rom mirror */
198	198	ROM_COPY( "user1", 0x28000, 0x2c000, 0x4000 )
199	199	/* 30000 12 available for cartridges with a language ROM */
200	200	/* 34000 13 available for cartridges with a language ROM */

trunk/src/mess/drivers/vboy.c
r32760	r32761
1112	1112	//AM_RANGE( 0x04000000, 0x04ffffff ) // Expansion area
1113	1113	AM_RANGE( 0x05000000, 0x0500ffff ) AM_MIRROR(0x0ff0000) AM_RAM AM_SHARE("wram")// Main RAM - 64K mask 0xffff
1114	1114	AM_RANGE( 0x06000000, 0x06003fff ) AM_DEVREADWRITE("cartslot", vboy_cart_slot_device, read_eeprom, write_eeprom) // Cart RAM - 8K NVRAM
1115		// AM_RANGE( 0x07000000, 0x071fffff ) AM_MIRROR(0x0e00000) AM_DEVREAD("cartslot", vboy_cart_slot_device, read_cart) /* ROM */
	1115	// AM_RANGE( 0x07000000, 0x071fffff ) AM_MIRROR(0x0e00000) AM_DEVREAD("cartslot", vboy_cart_slot_device, read_cart) /* ROM */
1116	1116	ADDRESS_MAP_END
1117	1117
1118	1118	static ADDRESS_MAP_START( vboy_io, AS_IO, 32, vboy_state )
r32760	r32761
1141	1141	// AM_RANGE( 0x04000000, 0x04ffffff ) // Expansion area
1142	1142	AM_RANGE( 0x05000000, 0x0500ffff ) AM_MIRROR(0x0ff0000) AM_RAM AM_SHARE("wram") // Main RAM - 64K mask 0xffff
1143	1143	AM_RANGE( 0x06000000, 0x06003fff ) AM_NOP // Cart RAM - 8K NVRAM ?
1144		// AM_RANGE( 0x07000000, 0x071fffff ) AM_MIRROR(0x0e00000) AM_DEVREAD("cartslot", vboy_cart_slot_device, read_cart) /* ROM */
	1144	// AM_RANGE( 0x07000000, 0x071fffff ) AM_MIRROR(0x0e00000) AM_DEVREAD("cartslot", vboy_cart_slot_device, read_cart) /* ROM */
1145	1145	ADDRESS_MAP_END
1146	1146
1147	1147	/* Input ports */

trunk/src/mess/drivers/ngp.c
r32760	r32761
136	136	m_k1ge(*this, "k1ge"),
137	137	m_io_controls(*this, "Controls"),
138	138	m_io_power(*this, "Power") ,
139		m_maincpu(*this, "maincpu")
	139	m_maincpu(*this, "maincpu")
140	140	{
141	141	m_flash_chip[0].present = 0;
142	142	m_flash_chip[0].state = F_READ;
r32760	r32761
651	651	m_maincpu->space(AS_PROGRAM).install_read_bank(0x800000, 0x9fffff, "flash1");
652	652	membank("flash0")->set_base(cart);
653	653	membank("flash1")->set_base(cart + 0x200000);
654
	654
655	655	m_flash_chip[0].data = cart;
656	656	m_flash_chip[0].org_data[0] = m_flash_chip[0].data[0];
657	657	m_flash_chip[0].org_data[1] = m_flash_chip[0].data[1];
r32760	r32761
669	669	m_flash_chip[0].org_data[13] = m_flash_chip[0].data[0x1fc001];
670	670	m_flash_chip[0].org_data[14] = m_flash_chip[0].data[0x1fc002];
671	671	m_flash_chip[0].org_data[15] = m_flash_chip[0].data[0x1fc003];
672
	672
673	673	m_flash_chip[1].data = cart + 0x200000;
674	674	m_flash_chip[1].org_data[0] = m_flash_chip[1].data[0];
675	675	m_flash_chip[1].org_data[1] = m_flash_chip[1].data[1];
r32760	r32761
739	739	DEVICE_IMAGE_LOAD_MEMBER( ngp_state, ngp_cart )
740	740	{
741	741	UINT32 size = m_cart->common_get_size("rom");
742
	742
743	743	if (size != 0x8000 && size != 0x80000 && size != 0x100000 && size != 0x200000 && size != 0x400000)
744	744	{
745	745	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
746	746	return IMAGE_INIT_FAIL;
747	747	}
748
	748
749	749	// alloc 0x400000 ROM to simplify mapping in the address map
750	750	m_cart->rom_alloc(0x400000, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
751		m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
752
	751	m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
	752
753	753	//printf("%2x%2x - %x - %x\n", (unsigned int) memregion("cart")->u8(0x20), (unsigned int) memregion("cart")->u8(0x21),
754	754	// (unsigned int) memregion("cart")->u8(0x22), (unsigned int) memregion("cart")->u8(0x23));
755	755	m_flash_chip[0].manufacturer_id = 0x98;

trunk/src/mess/drivers/nes.c
r32760	r32761
752	752	space.install_write_handler(0x6000, 0x7fff, write8_delegate(FUNC(nes_disksys_device::write_m), (nes_disksys_device *)slot));
753	753	space.install_read_handler(0x8000, 0xffff, read8_delegate(FUNC(nes_disksys_device::read_h), (nes_disksys_device *)slot));
754	754	space.install_write_handler(0x8000, 0xffff, write8_delegate(FUNC(nes_disksys_device::write_h), (nes_disksys_device *)slot));
755
	755
756	756	slot->vram_alloc(0x2000);
757	757	slot->prgram_alloc(0x8000);
758
	758
759	759	slot->pcb_start(machine(), m_ciram, FALSE);
760	760	slot->pcb_reg_postload(machine());
761	761	m_ppu->space(AS_PROGRAM).install_readwrite_handler(0, 0x1fff, read8_delegate(FUNC(device_nes_cart_interface::chr_r),(device_nes_cart_interface )slot), write8_delegate(FUNC(device_nes_cart_interface::chr_w),(device_nes_cart_interface )slot));
r32760	r32761
768	768
769	769
770	770	MACHINE_START_MEMBER( nes_state, fds )
771		{
	771	{
772	772	m_ciram = auto_alloc_array(machine(), UINT8, 0x800);
773	773	setup_ioports();
774	774	setup_disk(m_disk);
r32760	r32761
778	778	{
779	779	// Reset the mapper variables
780	780	m_disk->pcb_reset();
781
	781
782	782	// the rest is the same as for nes/famicom/dendy
783	783	m_maincpu->reset();
784
	784
785	785	memset(m_pad_latch, 0, sizeof(m_pad_latch));
786	786	memset(m_zapper_latch, 0, sizeof(m_zapper_latch));
787	787	m_paddle_latch = 0;
788		m_paddle_btn_latch = 0;
	788	m_paddle_btn_latch = 0;
789	789	}
790	790
791	791	static MACHINE_CONFIG_DERIVED( fds, famicom )
r32760	r32761
810	810	if (!m_cartslot->exists())
811	811	{
812	812	setup_disk(m_disk);
813
	813
814	814	// replace the famicom disk ROM with the famicom twin one (until we modernize the floppy drive)
815	815	m_maincpu->space(AS_PROGRAM).install_read_bank(0xe000, 0xffff, "ftbios");
816	816	membank("ftbios")->set_base(machine().root_device().memregion("maincpu")->base() + 0xe000);
r32760	r32761
824	824	// if there is no cart inserted, initialize the disk expansion instead
825	825	if (!m_cartslot->exists())
826	826	m_disk->pcb_reset();
827
	827
828	828	// the rest is the same as for nes/famicom/dendy
829	829	m_maincpu->reset();
830
	830
831	831	memset(m_pad_latch, 0, sizeof(m_pad_latch));
832	832	memset(m_zapper_latch, 0, sizeof(m_zapper_latch));
833	833	m_paddle_latch = 0;
834		m_paddle_btn_latch = 0;
	834	m_paddle_btn_latch = 0;
835	835	}
836	836
837	837	static MACHINE_CONFIG_DERIVED( famitwin, famicom )

trunk/src/mess/drivers/concept.c
r32760	r32761
196	196
197	197	SLOT_INTERFACE_START( concept_a2_cards )
198	198	SLOT_INTERFACE("fchdd", A2BUS_CORVUS) /* Corvus flat-cable HDD interface (see notes in a2corvus.c) */
199		SLOT_INTERFACE("fdc01", A2BUS_CORVFDC01) /* Corvus WD1793 floppy controller */
200		SLOT_INTERFACE("fdc02", A2BUS_CORVFDC02) /* Corvus NEC765 buffered floppy controller */
	199	SLOT_INTERFACE("fdc01", A2BUS_CORVFDC01) /* Corvus WD1793 floppy controller */
	200	SLOT_INTERFACE("fdc02", A2BUS_CORVFDC02) /* Corvus NEC765 buffered floppy controller */
201	201	SLOT_INTERFACE_END
202	202
203	203

trunk/src/mess/drivers/pencil2.c
r32760	r32761
107	107	AM_RANGE(0x0000, 0x1fff) AM_ROM
108	108	AM_RANGE(0x2000, 0x5fff) AM_WRITENOP // stop error log filling up
109	109	AM_RANGE(0x6000, 0x67ff) AM_MIRROR(0x1800) AM_RAM
110		//AM_RANGE(0x8000, 0xffff) // mapped by the cartslot
	110	//AM_RANGE(0x8000, 0xffff) // mapped by the cartslot
111	111	ADDRESS_MAP_END
112	112
113	113	static ADDRESS_MAP_START(pencil2_io, AS_IO, 8, pencil2_state)

trunk/src/mess/drivers/pockstat.c
r32760	r32761
961	961
962	962	if (size != 0x20f40)
963	963	return IMAGE_INIT_FAIL;
964
	964
965	965	image.fread(cart_id, 0xf40);
966	966
967	967	for (int i = 0; i < strlen(gme_id); i++)

trunk/src/mess/drivers/casloopy.c
r32760	r32761
478	478	UINT8 SRC, DST;
479	479	dynamic_buffer temp;
480	480	temp.resize(0x200000);
481
	481
482	482	m_cart->rom_alloc(size, GENERIC_ROM32_WIDTH, ENDIANNESS_LITTLE);
483	483
484	484	SRC = temp;
485	485	DST = m_cart->get_rom_base();
486		m_cart->common_load_rom(temp, size, "rom");
487
	486	m_cart->common_load_rom(temp, size, "rom");
	487
488	488	// fix endianness
489	489	for (int i = 0; i < 0x200000; i += 4)
490	490	{
r32760	r32761
495	495	DST[i + 2] = tempa;
496	496	DST[i + 3] = tempb;
497	497	}
498
	498
499	499	return IMAGE_INIT_PASS;
500	500	}
501	501

trunk/src/mess/drivers/myvision.c
r32760	r32761
66	66
67	67	static ADDRESS_MAP_START(myvision_mem, AS_PROGRAM, 8, myvision_state)
68	68	ADDRESS_MAP_UNMAP_HIGH
69		//AM_RANGE(0x0000, 0x5fff) // mapped by the cartslot
	69	//AM_RANGE(0x0000, 0x5fff) // mapped by the cartslot
70	70	AM_RANGE(0xa000, 0xa7ff) AM_RAM
71	71	AM_RANGE(0xe000, 0xe000) AM_DEVREADWRITE("tms9918", tms9918a_device, vram_read, vram_write)
72	72	AM_RANGE(0xe002, 0xe002) AM_DEVREADWRITE("tms9918", tms9918a_device, register_read, register_write)
r32760	r32761
144	144	DEVICE_IMAGE_LOAD_MEMBER( myvision_state, cart )
145	145	{
146	146	UINT32 size = m_cart->common_get_size("rom");
147
	147
148	148	if (size != 0x4000 && size != 0x6000)
149	149	{
150	150	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
151	151	return IMAGE_INIT_FAIL;
152	152	}
153
	153
154	154	m_cart->rom_alloc(size, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
155		m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
	155	m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
156	156
157	157	return IMAGE_INIT_PASS;
158	158	}

trunk/src/mess/drivers/a2600.c
r32760	r32761
244	244	{
245	245	m_cart->write_bank(space, offset, 0);
246	246	m_riot_ram[0x20 + offset] = data;
247
	247
248	248	}
249	249
250	250	WRITE8_MEMBER(a2600_state::cart_over_tia_w)
251	251	{
252	252	// Both Cart & TIA see these addresses
253	253	m_cart->write_bank(space, offset, data);
254		m_tia->write(space, offset, data);
	254	m_tia->write(space, offset, data);
255	255	}
256	256
257	257	MACHINE_START_MEMBER(a2600_state,a2600)
r32760	r32761
313	313	m_maincpu->space(AS_PROGRAM).install_read_handler(0x1000, 0x1fff, read8_delegate(FUNC(vcs_cart_slot_device::read_rom),(vcs_cart_slot_device*)m_cart));
314	314	break;
315	315	}
316
	316
317	317	/* Banks may have changed, reset the cpu so it uses the correct reset vector */
318	318	m_maincpu->reset();
319	319	}

trunk/src/mess/drivers/fc100.c
r32760	r32761
114	114	static ADDRESS_MAP_START( fc100_mem, AS_PROGRAM, 8, fc100_state )
115	115	ADDRESS_MAP_UNMAP_HIGH
116	116	AM_RANGE( 0x0000, 0x5fff ) AM_ROM AM_REGION("roms", 0)
117		//AM_RANGE(0x6000, 0x6fff) // mapped by the cartslot
	117	//AM_RANGE(0x6000, 0x6fff) // mapped by the cartslot
118	118	AM_RANGE( 0x7800, 0x7fff ) AM_READ_BANK("bankr") AM_WRITE_BANK("bankw") // Banked RAM/ROM
119	119	AM_RANGE( 0x8000, 0xbfff ) AM_RAM // expansion ram pack - if omitted you get a 'Pages?' prompt at boot
120	120	AM_RANGE( 0xc000, 0xffff ) AM_RAM AM_SHARE("videoram")

trunk/src/mess/drivers/apple2gs.c
r32760	r32761
576	576	ROM_LOAD ( "apple2gs.chr", 0x0000, 0x1000, CRC(91e53cd8) SHA1(34e2443e2ef960a36c047a09ed5a93f471797f89))
577	577
578	578	ROM_REGION(0x20000,"maincpu",0)
579		ROM_LOAD( "apple iigs alpha rom 2.0 19860310.bin", 0x000000, 0x020000, CRC(a47d275f) SHA1(c5836adcfc8be69c7351b84afa94c814e8d92b81) )
	579	ROM_LOAD( "apple iigs alpha rom 2.0 19860310.bin", 0x000000, 0x020000, CRC(a47d275f) SHA1(c5836adcfc8be69c7351b84afa94c814e8d92b81) )
580	580
581	581	ROM_REGION(0x20000, "es5503", ROMREGION_ERASE00)
582	582

trunk/src/mess/drivers/pc9801.c
r32760	r32761
38	38	- Dies on ARTIC check;
39	39	- Presumably one ROM is undumped?
40	40
41		TODO: (PC-9821AP)
42		- No way to exit the initial loop. Code looks broken/bad dump?
43
	41	TODO: (PC-9821AP)
	42	- No way to exit the initial loop. Code looks broken/bad dump?
	43
44	44	floppy issues TODO (certain fail)
45	45	- Unsupported disk types: .nfd, .fdd, *.nhd
46	46	- 46 Okunen Monogatari - The Shinkaron
r32760	r32761
553	553	UINT8 m_joy_sel;
554	554	UINT8 m_ext2_ff;
555	555	UINT8 m_sys_type;
556
	556
557	557	DECLARE_WRITE_LINE_MEMBER( keyboard_irq );
558	558	DECLARE_WRITE_LINE_MEMBER( write_uart_clock );
559	559	DECLARE_READ8_MEMBER(pc9801_xx_r);
r32760	r32761
702	702	DECLARE_MACHINE_START(pc9801bx2);
703	703	DECLARE_MACHINE_START(pc9821);
704	704	DECLARE_MACHINE_START(pc9821ap2);
705
	705
706	706	DECLARE_MACHINE_RESET(pc9801_common);
707	707	DECLARE_MACHINE_RESET(pc9801f);
708	708	DECLARE_MACHINE_RESET(pc9801rs);
r32760	r32761
1938	1938	WRITE8_MEMBER(pc9801_state::pc9801rs_bank_w)
1939	1939	{
1940	1940	if(offset == 1)
1941		{
	1941	{
1942	1942	if((data & 0xf0) == 0x00 \|\| (data & 0xf0) == 0x10)
1943	1943	{
1944	1944	if((data & 0xed) == 0x00)
r32760	r32761
3375	3375	MACHINE_START_MEMBER(pc9801_state,pc9821ap2)
3376	3376	{
3377	3377	MACHINE_START_CALL_MEMBER(pc9821);
3378
	3378
3379	3379	// ...
3380	3380	}
3381	3381
r32760	r32761
3891	3891	MCFG_CPU_IO_MAP(pc9821_io)
3892	3892	MCFG_CPU_VBLANK_INT_DRIVER("screen", pc9801_state, pc9801_vrtc_irq)
3893	3893	MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("pic8259_master", pic8259_device, inta_cb)
3894
	3894
3895	3895	MCFG_MACHINE_START_OVERRIDE(pc9801_state,pc9821ap2)
3896	3896	MACHINE_CONFIG_END
3897	3897

trunk/src/mess/drivers/a7800.c
r32760	r32761
9	9	2002/05/13 kubecj added more banks for bankswitching
10	10	added PAL machine description
11	11	changed clock to be precise
12		improved cart emulation (in machine/)
	12	improved cart emulation (in machine/)
13	13
14	14	2012/10/25 Robert Tuccitto NTSC Color Generator utilized for
15	15	color palette with hue shift/start
r32760	r32761
88	88
89	89	2014/05/06 Mike Saarna/Robert Tuccitto Brought initial Maria cycle counts
90	90	inline from measurements taken with logic analyzer and tests.
91
	91
92	92	2014/08/25 Fabio Priuli Converted carts to be slot devices and cleaned
93	93	up the driver (removed the pokey, cleaned up rom regions, etc.)
94
	94
95	95	***************************************************************************/
96	96
97	97	#include "emu.h"
r32760	r32761
121	121	m_io_console_buttons(*this, "console_buttons"),
122	122	m_cart(*this, "cartslot"),
123	123	m_screen(*this, "screen") { }
124
	124
125	125	int m_lines;
126	126	int m_ispal;
127
	127
128	128	int m_ctrl_lock;
129	129	int m_ctrl_reg;
130	130	int m_maria_flag;
131	131	int m_p1_one_button;
132	132	int m_p2_one_button;
133	133	int m_bios_enabled;
134
	134
135	135	UINT8 *m_bios;
136
	136
137	137	DECLARE_READ8_MEMBER(bios_or_cart_r);
138	138	DECLARE_WRITE8_MEMBER(ram0_w);
139	139	DECLARE_READ8_MEMBER(tia_r);
r32760	r32761
151	151	DECLARE_READ8_MEMBER(riot_joystick_r);
152	152	DECLARE_READ8_MEMBER(riot_console_button_r);
153	153	DECLARE_WRITE8_MEMBER(riot_button_pullup_w);
154
	154
155	155	protected:
156	156	required_device<cpu_device> m_maincpu;
157	157	required_device<tia_device> m_tia;
r32760	r32761
223	223	return 0x80;
224	224	default:
225	225	logerror("undefined TIA read %x\n",offset);
226
	226
227	227	}
228	228	return 0xff;
229	229	}
r32760	r32761
231	231	// TIA
232	232	WRITE8_MEMBER(a7800_state::tia_w)
233	233	{
234		if (offset < 0x20)
	234	if (offset < 0x20)
235	235	{ //INPTCTRL covers TIA registers 0x00-0x1F until locked
236	236	if (data & 0x01)
237	237	{
r32760	r32761
291	291	AM_RANGE(0x2040, 0x20ff) AM_RAMBANK("ram0") // mirror (6116 block 0)
292	292	AM_RANGE(0x2140, 0x21ff) AM_RAMBANK("ram1") // mirror (6116 block 1)
293	293
294		AM_RANGE(0x2800, 0x2fff) AM_RAMBANK("mirror") // these should mirror "main_ram" (according to docs)
	294	AM_RANGE(0x2800, 0x2fff) AM_RAMBANK("mirror") // these should mirror "main_ram" (according to docs)
295	295	AM_RANGE(0x3000, 0x37ff) AM_RAMBANK("mirror") // but system have issues in such case...
296	296	AM_RANGE(0x3800, 0x3fff) AM_RAMBANK("mirror")
297	297	AM_RANGE(0x4000, 0xffff) AM_DEVWRITE("cartslot", a78_cart_slot_device, write_40xx)
298	298	AM_RANGE(0x4000, 0xbfff) AM_DEVREAD("cartslot", a78_cart_slot_device, read_40xx)
299		AM_RANGE(0xc000, 0xffff) AM_READ(bios_or_cart_r) // here also the BIOS can be accessed
	299	AM_RANGE(0xc000, 0xffff) AM_READ(bios_or_cart_r) // here also the BIOS can be accessed
300	300	ADDRESS_MAP_END
301	301
302	302
r32760	r32761
1313	1313	save_item(NAME(m_ctrl_lock));
1314	1314	save_item(NAME(m_ctrl_reg));
1315	1315	save_item(NAME(m_maria_flag));
1316
	1316
1317	1317	// install additional handlers, if needed
1318	1318	if (m_cart->exists())
1319	1319	{

trunk/src/mess/drivers/sv8000.c
r32760	r32761
94	94
95	95	static ADDRESS_MAP_START(sv8000_mem, AS_PROGRAM, 8, sv8000_state)
96	96	ADDRESS_MAP_UNMAP_HIGH
97		//AM_RANGE(0x0000, 0x0fff) // mapped by the cartslot
	97	//AM_RANGE(0x0000, 0x0fff) // mapped by the cartslot
98	98	AM_RANGE( 0x8000, 0x83ff ) AM_RAM // Work RAM??
99	99	AM_RANGE( 0xc000, 0xcbff ) AM_RAM AM_SHARE("videoram")
100	100	ADDRESS_MAP_END
r32760	r32761
197	197	DEVICE_IMAGE_LOAD_MEMBER( sv8000_state, cart )
198	198	{
199	199	UINT32 size = m_cart->common_get_size("rom");
200
	200
201	201	if (size != 0x1000)
202	202	{
203	203	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Incorrect or not support cartridge size");
204	204	return IMAGE_INIT_FAIL;
205	205	}
206
	206
207	207	m_cart->rom_alloc(size, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
208		m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
209
	208	m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
	209
210	210	return IMAGE_INIT_PASS;
211	211	}
212	212

trunk/src/mess/drivers/tsispch.c
r32760	r32761
482	482	// 0 - to /CE of ROMs 12(U27) and 13(U50)
483	483	//
484	484	// Note U81 is optional; it can be replaced by a 74s138 instead of a prom,
485		// with A19, A18, A17 as inputs, for decoding the roms as:
	485	// with A19, A18, A17 as inputs, for decoding the roms as:
486	486	// 7 - to /CE of ROMs 0(U21) and 1(U44) (0xE0000-0xE3FFF)
487	487	// 6 - to /CE of ROMs 2(U22) and 3(U45) (0xE4000-0xE7FFF)
488	488	// 5 - to /CE of ROMs 4(U23) and 5(U46) (0xE8000-0xEBFFF)
r32760	r32761
490	490	// 3 - to /CE of ROMs 8(U25) and 9(U48) (0xF0000-0xF3FFF)
491	491	// 2 - to /CE of ROMs 10(U26) and 11(U49) (0xF4000-0xF7FFF)
492	492	// 1 - to /CE of ROMs 12(U27) and 13(U50) (0xF8000-0xFBFFF)
493		// 0 - to /CE of ROMs 14(U28) and 15(U51) (0xFC000-0xFFFFF)
494
	493	// 0 - to /CE of ROMs 14(U28) and 15(U51) (0xFC000-0xFFFFF)
	494
495	495	ROM_REGION(0x1000, "proms", 0)
496	496	ROM_LOAD( "am27s19.u77", 0x0000, 0x0020, CRC(A88757FC) SHA1(9066D6DBC009D7A126D75B8461CA464DDF134412))
497	497	ROM_LOAD( "am27s19.u79", 0x0020, 0x0020, CRC(A165B090) SHA1(BFC413C79915C68906033741318C070AD5DD0F6B))

trunk/src/mess/drivers/tutor.c
r32760	r32761
196	196	optional_device<cassette_image_device> m_cass;
197	197	optional_device<centronics_device> m_centronics;
198	198	optional_device<output_latch_device> m_cent_data_out;
199		required_memory_bank m_bank1;
	199	required_memory_bank m_bank1;
200	200	memory_region *m_cart_rom;
201	201
202	202	DECLARE_READ8_MEMBER(key_r);
r32760	r32761
223	223	{
224	224	astring region_tag;
225	225	m_cart_rom = memregion(region_tag.cpy(m_cart->tag()).cat(GENERIC_ROM_REGION_TAG));
226
	226
227	227	m_tape_interrupt_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(tutor_state::tape_interrupt_handler),this));
228
	228
229	229	m_bank1->configure_entry(0, memregion("maincpu")->base() + 0x8000);
230	230	m_bank1->set_entry(0);
231	231

trunk/src/mess/drivers/svision.c
r32760	r32761
452	452	DEVICE_IMAGE_LOAD_MEMBER( svision_state, svision_cart )
453	453	{
454	454	UINT32 size = m_cart->common_get_size("rom");
455
	455
456	456	if (size > 0x20000)
457	457	{
458	458	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
459	459	return IMAGE_INIT_FAIL;
460	460	}
461
	461
462	462	m_cart->rom_alloc(size, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
463		m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
464
	463	m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
	464
465	465	return IMAGE_INIT_PASS;
466	466	}
467	467

trunk/src/mess/drivers/specpls3.c
r32760	r32761
217	217	int ram_page = m_port_7ffd_data & 0x07;
218	218	unsigned char *ram_data = messram + (ram_page<<14);
219	219	membank("bank4")->set_base(ram_data);
220
	220
221	221	logerror("RAM at 0xc000: %02x\n", ram_page);
222
	222
223	223	/* Reset memory between 0x4000 - 0xbfff in case extended paging was being used */
224	224	/* Bank 5 in 0x4000 - 0x7fff */
225	225	membank("bank2")->set_base(messram + (5 << 14));
226
	226
227	227	/* Bank 2 in 0x8000 - 0xbfff */
228	228	membank("bank3")->set_base(messram + (2 << 14));
229	229
r32760	r32761
231	231	{
232	232	/* ROM switching */
233	233	int ROMSelection = BIT(m_port_7ffd_data, 4) \| ((m_port_1ffd_data >> 1) & 0x02);
234
	234
235	235	/* rom 0 is editor, rom 1 is syntax, rom 2 is DOS, rom 3 is 48 BASIC */
236	236	unsigned char *ChosenROM = memregion("maincpu")->base() + 0x010000 + (ROMSelection << 14);
237
	237
238	238	membank("bank1")->set_base(ChosenROM);
239	239	space.unmap_write(0x0000, 0x3fff);
240
	240
241	241	logerror("rom switch: %02x\n", ROMSelection);
242	242	}
243	243	}
r32760	r32761
247	247	int MemorySelection = (m_port_1ffd_data >> 1) & 0x03;
248	248	const int *memory_selection = &spectrum_plus3_memory_selections[(MemorySelection << 2)];
249	249	unsigned char *ram_data = messram + (memory_selection[0] << 14);
250
	250
251	251	membank("bank1")->set_base(ram_data);
252	252	/* allow writes to 0x0000-0x03fff */
253	253	space.install_write_bank(0x0000, 0x3fff, "bank1");
254
	254
255	255	ram_data = messram + (memory_selection[1] << 14);
256	256	membank("bank2")->set_base(ram_data);
257
	257
258	258	ram_data = messram + (memory_selection[2] << 14);
259	259	membank("bank3")->set_base(ram_data);
260
	260
261	261	ram_data = messram + (memory_selection[3] << 14);
262	262	membank("bank4")->set_base(ram_data);
263
	263
264	264	logerror("extended memory paging: %02x\n", MemorySelection);
265	265	}
266	266	}

trunk/src/mess/drivers/beta.c
r32760	r32761
60	60	m_q8(*this, "Q8"),
61	61	m_q9(*this, "Q9")
62	62	{ }
63
	63
64	64	required_device<cpu_device> m_maincpu;
65	65	required_device<speaker_sound_device> m_speaker;
66	66	required_device<generic_slot_device> m_eprom;
r32760	r32761
68	68	required_ioport m_q7;
69	69	required_ioport m_q8;
70	70	required_ioport m_q9;
71
	71
72	72	virtual void machine_start();
73
	73
74	74	DECLARE_READ8_MEMBER( riot_pa_r );
75	75	DECLARE_WRITE8_MEMBER( riot_pa_w );
76	76	DECLARE_READ8_MEMBER( riot_pb_r );
77	77	DECLARE_WRITE8_MEMBER( riot_pb_w );
78	78	DECLARE_INPUT_CHANGED_MEMBER( trigger_reset );
79
	79
80	80	DECLARE_DEVICE_IMAGE_LOAD_MEMBER( beta_eprom );
81	81	DECLARE_DEVICE_IMAGE_UNLOAD_MEMBER( beta_eprom );
82
	82
83	83	/* EPROM state */
84	84	int m_eprom_oe;
85	85	int m_eprom_ce;
r32760	r32761
87	87	UINT8 m_eprom_data;
88	88	UINT8 m_old_data;
89	89	dynamic_buffer m_eprom_rom;
90
	90
91	91	/* display state */
92	92	UINT8 m_ls145_p;
93	93	UINT8 m_segment;
94
	94
95	95	emu_timer *m_led_refresh_timer;
96	96	TIMER_CALLBACK_MEMBER(led_refresh);
97	97	};
r32760	r32761
285	285	DEVICE_IMAGE_LOAD_MEMBER( beta_state, beta_eprom )
286	286	{
287	287	UINT32 size = m_eprom->common_get_size("rom");
288
	288
289	289	if (size != 0x800)
290	290	{
291	291	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
292	292	return IMAGE_INIT_FAIL;
293	293	}
294
	294
295	295	m_eprom->rom_alloc(size, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
296		m_eprom->common_load_rom(m_eprom->get_rom_base(), size, "rom");
297
	296	m_eprom->common_load_rom(m_eprom->get_rom_base(), size, "rom");
	297
298	298	return IMAGE_INIT_PASS;
299	299	}
300	300

trunk/src/mess/drivers/atom.c
r32760	r32761
250	250	AM_RANGE(0x0a05, 0x7fff) AM_RAM
251	251	AM_RANGE(0x8000, 0x97ff) AM_RAM AM_SHARE("video_ram")
252	252	AM_RANGE(0x9800, 0x9fff) AM_RAM
253		// AM_RANGE(0xa000, 0xafff) // mapped by the cartslot
	253	// AM_RANGE(0xa000, 0xafff) // mapped by the cartslot
254	254	AM_RANGE(0xb000, 0xb003) AM_MIRROR(0x3fc) AM_DEVREADWRITE(INS8255_TAG, i8255_device, read, write)
255	255	// AM_RANGE(0xb400, 0xb403) AM_DEVREADWRITE(MC6854_TAG, mc6854_device, read, write)
256	256	// AM_RANGE(0xb404, 0xb404) AM_READ_PORT("ECONET")
r32760	r32761
680	680	}
681	681
682	682	slot->rom_alloc(size, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
683		slot->common_load_rom(slot->get_rom_base(), size, "rom");
	683	slot->common_load_rom(slot->get_rom_base(), size, "rom");
684	684
685	685	return IMAGE_INIT_PASS;
686	686	}
r32760	r32761
882	882	DRIVER_INIT_MEMBER(atomeb_state, atomeb)
883	883	{
884	884	// these have to be set here, so that we can pass m_ext[*] to device_image_load!
885		char str[8];
	885	char str[8];
886	886	for (int i = 0; i < 16; i++)
887	887	{
888	888	sprintf(str,"rom_a%x", i);
889	889	m_ext[i] = machine().device<generic_slot_device>(str);
890		}
	890	}
891	891	}
892	892
893	893

trunk/src/mess/drivers/uzebox.c
r32760	r32761
273	273	DEVICE_IMAGE_LOAD_MEMBER(uzebox_state, uzebox_cart)
274	274	{
275	275	UINT32 size = m_cart->common_get_size("rom");
276
	276
277	277	m_cart->rom_alloc(size, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
278	278
279	279	if (image.software_entry() == NULL)

trunk/src/mess/drivers/supracan.c
r32760	r32761
1125	1125	}
1126	1126
1127	1127	static ADDRESS_MAP_START( supracan_mem, AS_PROGRAM, 16, supracan_state )
1128		//AM_RANGE( 0x000000, 0x3fffff ) // mapped by the cartslot
	1128	//AM_RANGE( 0x000000, 0x3fffff ) // mapped by the cartslot
1129	1129	AM_RANGE( 0xe80200, 0xe80201 ) AM_READ_PORT("P1")
1130	1130	AM_RANGE( 0xe80202, 0xe80203 ) AM_READ_PORT("P2")
1131	1131	AM_RANGE( 0xe80208, 0xe80209 ) AM_READ_PORT("P3")
r32760	r32761
1754	1754	DEVICE_IMAGE_LOAD_MEMBER( supracan_state, supracan_cart )
1755	1755	{
1756	1756	UINT32 size = m_cart->common_get_size("rom");
1757
	1757
1758	1758	if (size > 0x400000)
1759	1759	{
1760	1760	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
r32760	r32761
1762	1762	}
1763	1763
1764	1764	m_cart->rom_alloc(size, GENERIC_ROM16_WIDTH, ENDIANNESS_BIG);
1765		m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
1766
	1765	m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
	1766
1767	1767	return IMAGE_INIT_PASS;
1768	1768	}
1769	1769

trunk/src/mess/drivers/channelf.c
r32760	r32761
178	178	m_maincpu->space(AS_PROGRAM).install_write_handler(0x3000, 0x3fff, write8_delegate(FUNC(channelf_cart_slot_device::write_bank),(channelf_cart_slot_device*)m_cart));
179	179	break;
180	180	}
181
	181
182	182	m_cart->save_ram();
183	183	}
184	184	}

trunk/src/mess/drivers/pc8401a.c
r32760	r32761
521	521
522	522	/* bank switch */
523	523	bankswitch(0);
524
	524
525	525	/* register for state saving */
526	526	save_item(NAME(m_mmr));
527	527	save_item(NAME(m_io_addr));

trunk/src/mess/drivers/spc1000.c
r32760	r32761
70	70	DECLARE_READ8_MEMBER(fdc_8255_c_r);
71	71	DECLARE_WRITE8_MEMBER(fdc_8255_c_w);
72	72	DECLARE_READ8_MEMBER( upd765_tc_r );
73		DECLARE_WRITE8_MEMBER( fdc_control_w );
	73	DECLARE_WRITE8_MEMBER( fdc_control_w );
74	74	MC6847_GET_CHARROM_MEMBER(get_char_rom)
75	75	{
76	76	return m_p_videoram[0x1000 + (ch & 0x7f) * 16 + line];
r32760	r32761
85	85	virtual void machine_reset();
86	86	required_device<mc6847_base_device> m_vdg;
87	87	required_device<cpu_device> m_maincpu;
88		required_device<cpu_device> m_fdccpu;
89		required_device<upd765a_device> m_fdc;
	88	required_device<cpu_device> m_fdccpu;
	89	required_device<upd765a_device> m_fdc;
90	90	required_device<i8255_device> m_pio;
91	91	required_device<ram_device> m_ram;
92	92	required_device<cassette_image_device> m_cass;
93	93
94	94	floppy_image_device *m_fd0;
95	95	floppy_image_device *m_fd1;
96
97		emu_timer *m_timer_tc;
98
	96
	97	emu_timer *m_timer_tc;
	98
99	99	UINT8 m_i8255_0_pc;
100	100	UINT8 m_i8255_1_pc;
101	101	UINT8 m_i8255_portb;
102
	102
103	103	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
104	104	};
105	105
106	106	void spc1000_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
107	107	{
108		m_fdc->tc_w(false);
	108	m_fdc->tc_w(false);
109	109	}
110	110
111	111	static ADDRESS_MAP_START(spc1000_mem, AS_PROGRAM, 8, spc1000_state )
r32760	r32761
255	255	AM_RANGE(0x8009, 0x8009) AM_READ_PORT("LINE9")
256	256	AM_RANGE(0xA000, 0xA000) AM_READWRITE(spc1000_iplk_r, spc1000_iplk_w)
257	257	AM_RANGE(0xC000, 0xC002) AM_READWRITE(spc1000_sd725_r, spc1000_sd725_w)
258		// AM_RANGE(0xC000, 0xC003) AM_DEVREADWRITE("d8255_master", i8255_device, read, write)
	258	// AM_RANGE(0xC000, 0xC003) AM_DEVREADWRITE("d8255_master", i8255_device, read, write)
259	259	ADDRESS_MAP_END
260	260
261	261	/* Input ports */
r32760	r32761
342	342	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("I") PORT_CODE(KEYCODE_I) PORT_CHAR('i') PORT_CHAR('I') PORT_CHAR(0x09)
343	343	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("8 (") PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(')
344	344	PORT_START("LINE9")
345		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_START) PORT_NAME("IPL") PORT_CODE(KEYCODE_END)
	345	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_START) PORT_NAME("IPL") PORT_CODE(KEYCODE_END)
346	346	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F5") PORT_CODE(KEYCODE_F5)
347	347	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("- =") PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-') PORT_CHAR('=')
348	348	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("0") PORT_CODE(KEYCODE_0) PORT_CHAR('0')
r32760	r32761
369	369	membank("bank2")->set_base(ram);
370	370	membank("bank3")->set_base(mem);
371	371	membank("bank4")->set_base(ram + 0x8000);
372
	372
373	373	m_work_ram = auto_alloc_array_clear(machine(), UINT8, 0x10000);
374	374	m_fdccpu->set_input_line_vector(0, 0);
375
	375
376	376	m_fd0 = machine().device<floppy_connector>("upd765:0")->get_device();
377	377	m_fd1 = machine().device<floppy_connector>("upd765:1")->get_device();
378	378
379		m_timer_tc = timer_alloc(1, NULL);
	379	m_timer_tc = timer_alloc(1, NULL);
380	380	m_timer_tc->adjust(attotime::never);
381	381
382	382	// enable rom
383		m_fdccpu->space(AS_PROGRAM).install_rom(0x0000, 0xfff, 0, 0x2000, memregion("rom")->base());
384
385		m_IPLK = 1;
	383	m_fdccpu->space(AS_PROGRAM).install_rom(0x0000, 0xfff, 0, 0x2000, memregion("rom")->base());
	384
	385	m_IPLK = 1;
386	386	}
387	387
388	388	READ8_MEMBER(spc1000_state::mc6847_videoram_r)
r32760	r32761
452	452	MCFG_CPU_ADD("fdccpu", Z80, XTAL_4MHz) /* 4 MHz */
453	453	MCFG_CPU_PROGRAM_MAP(sd725_mem)
454	454	MCFG_CPU_IO_MAP(sd725_io)
455
	455
456	456	MCFG_DEVICE_ADD("d8255_master", I8255, 0)
457	457	MCFG_I8255_IN_PORTA_CB(DEVREAD8("d8255_master", i8255_device, pb_r))
458	458	MCFG_I8255_IN_PORTB_CB(DEVREAD8("d8255_master", i8255_device, pa_r))
459		MCFG_I8255_OUT_PORTB_CB(WRITE8(spc1000_state, fdc_8255_b_w))
	459	MCFG_I8255_OUT_PORTB_CB(WRITE8(spc1000_state, fdc_8255_b_w))
460	460	MCFG_I8255_IN_PORTC_CB(READ8(spc1000_state, fdc_8255_c_r))
461		MCFG_I8255_OUT_PORTC_CB(WRITE8(spc1000_state, fdc_8255_c_w))
	461	MCFG_I8255_OUT_PORTC_CB(WRITE8(spc1000_state, fdc_8255_c_w))
462	462
463	463	// floppy disk controller
464	464	MCFG_UPD765A_ADD("upd765", true, true)
465		MCFG_UPD765_INTRQ_CALLBACK(INPUTLINE("fdccpu", INPUT_LINE_IRQ0))
	465	MCFG_UPD765_INTRQ_CALLBACK(INPUTLINE("fdccpu", INPUT_LINE_IRQ0))
466	466
467	467	// floppy drives
468	468	MCFG_FLOPPY_DRIVE_ADD("upd765:0", sd725_floppies, "sd320", floppy_image_device::default_floppy_formats)
469		MCFG_FLOPPY_DRIVE_ADD("upd765:1", sd725_floppies, "sd320", floppy_image_device::default_floppy_formats)
	469	MCFG_FLOPPY_DRIVE_ADD("upd765:1", sd725_floppies, "sd320", floppy_image_device::default_floppy_formats)
470	470	//CFG_SOFTWARE_LIST_ADD("disk_list","spc1000_flop")
471
	471
472	472	/* video hardware */
473	473	MCFG_SCREEN_MC6847_NTSC_ADD("screen", "mc6847")
474	474
r32760	r32761
501	501	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASEFF )
502	502	ROM_LOAD( "spcall.rom", 0x0000, 0x8000, CRC(19638fc9) SHA1(489f1baa7aebf3c8c660325fb1fd790d84203284))
503	503
504		ROM_REGION( 0x10000, "fdccpu", 0)
505		ROM_LOAD("sd725a.bin", 0x0000, 0x1000, CRC(96ac2eb8) SHA1(8e9d8f63a7fb87af417e95603e71cf537a6e83f1))
	504	ROM_REGION( 0x10000, "fdccpu", 0)
	505	ROM_LOAD("sd725a.bin", 0x0000, 0x1000, CRC(96ac2eb8) SHA1(8e9d8f63a7fb87af417e95603e71cf537a6e83f1))
506	506	ROM_END
507	507
508	508	#if 0

trunk/src/mess/drivers/atarist.c
r32760	r32761
1228	1228	AM_RANGE(0x000008, 0x1fffff) AM_RAM
1229	1229	AM_RANGE(0x200000, 0x3fffff) AM_RAM
1230	1230	AM_RANGE(0x400000, 0xf9ffff) AM_READWRITE(berr_r, berr_w)
1231		//AM_RANGE(0xfa0000, 0xfbffff) // mapped by the cartslot
	1231	//AM_RANGE(0xfa0000, 0xfbffff) // mapped by the cartslot
1232	1232	AM_RANGE(0xfc0000, 0xfeffff) AM_ROM AM_REGION(M68000_TAG, 0) AM_WRITE(berr_w)
1233	1233	AM_RANGE(0xff8000, 0xff8001) AM_READWRITE8(mmu_r, mmu_w, 0x00ff)
1234	1234	AM_RANGE(0xff8200, 0xff8203) AM_READWRITE8(shifter_base_r, shifter_base_w, 0x00ff)
r32760	r32761
1272	1272	AM_RANGE(0x000000, 0x000007) AM_ROM AM_REGION(M68000_TAG, 0)
1273	1273	AM_RANGE(0x000008, 0x1fffff) AM_RAM
1274	1274	AM_RANGE(0x200000, 0x3fffff) AM_RAM
1275		//AM_RANGE(0xfa0000, 0xfbffff) // mapped by the cartslot
	1275	//AM_RANGE(0xfa0000, 0xfbffff) // mapped by the cartslot
1276	1276	AM_RANGE(0xfc0000, 0xfeffff) AM_ROM AM_REGION(M68000_TAG, 0)
1277	1277	// AM_RANGE(0xff7f30, 0xff7f31) AM_READWRITE(blitter_dst_inc_y_r, blitter_dst_inc_y_w) // for TOS 1.02
1278	1278	AM_RANGE(0xff8000, 0xff8001) AM_READWRITE8(mmu_r, mmu_w, 0x00ff)

trunk/src/mess/drivers/ep64.c
r32760	r32761
320	320
321	321	static ADDRESS_MAP_START( dave_64k_mem, AS_PROGRAM, 8, ep64_state )
322	322	AM_RANGE(0x000000, 0x007fff) AM_ROM AM_REGION(Z80_TAG, 0)
323		//AM_RANGE(0x010000, 0x01ffff) // mapped by the cartslot
	323	//AM_RANGE(0x010000, 0x01ffff) // mapped by the cartslot
324	324	AM_RANGE(0x3f0000, 0x3fffff) AM_DEVICE(NICK_TAG, nick_device, vram_map)
325	325	ADDRESS_MAP_END
326	326

trunk/src/mess/drivers/pet.c
r32760	r32761
248	248	data = m_rom->base()[offset - 0x9000];
249	249	}
250	250	break;
251
	251
252	252	case SELB:
253	253	if (norom)
254	254	{
r32760	r32761
258	258	data = m_rom->base()[offset - 0x9000];
259	259	}
260	260	break;
261
	261
262	262	case SELC: case SELD: case SELF:
263	263	if (norom)
264	264	{

trunk/src/mess/drivers/m5.c
r32760	r32761
243	243	static ADDRESS_MAP_START( m5_mem, AS_PROGRAM, 8, m5_state )
244	244	ADDRESS_MAP_UNMAP_HIGH
245	245	AM_RANGE(0x0000, 0x1fff) AM_ROM
246		//AM_RANGE(0x2000, 0x6fff) // mapped by the cartslot
	246	//AM_RANGE(0x2000, 0x6fff) // mapped by the cartslot
247	247	AM_RANGE(0x7000, 0x7fff) AM_RAM
248	248	AM_RANGE(0x8000, 0xffff) AM_RAM
249	249	ADDRESS_MAP_END

trunk/src/mess/drivers/atari400.c
r32760	r32761
252	252	m_8000(*this, "8000"),
253	253	m_a000(*this, "a000"),
254	254	m_cart(*this, "cartleft"),
255		m_cart2(*this, "cartright") { }
	255	m_cart2(*this, "cartright") { }
256	256
257	257	DECLARE_MACHINE_START(a400);
258	258	DECLARE_MACHINE_START(a800);
r32760	r32761
267	267	DECLARE_WRITE8_MEMBER(a600xl_pia_pb_w);
268	268	DECLARE_WRITE8_MEMBER(a800xl_pia_pb_w);
269	269
270		DECLARE_READ8_MEMBER(read_d5xx); // at least one cart type can enable/disable roms when reading
	270	DECLARE_READ8_MEMBER(read_d5xx); // at least one cart type can enable/disable roms when reading
271	271	DECLARE_WRITE8_MEMBER(disable_cart);
272	272
273	273	// these are needed to handle carts which can disable ROM without
r32760	r32761
290	290	DECLARE_WRITE8_MEMBER(xegs_low_w);
291	291	DECLARE_READ8_MEMBER(xegs_high_r);
292	292	DECLARE_WRITE8_MEMBER(xegs_high_w);
293
	293
294	294	TIMER_DEVICE_CALLBACK_MEMBER(a400_interrupt);
295	295	TIMER_DEVICE_CALLBACK_MEMBER(a800xl_interrupt);
296	296	TIMER_DEVICE_CALLBACK_MEMBER(a5200_interrupt);
297
	297
298	298	protected:
299		//required_device<cpu_device> m_maincpu; // maincpu is already contained in atari_common_state
	299	//required_device<cpu_device> m_maincpu; // maincpu is already contained in atari_common_state
300	300	required_device<ram_device> m_ram;
301	301	required_device<pia6821_device> m_pia;
302	302	optional_device<dac_device> m_dac;
r32760	r32761
310	310	int m_cart_disabled, m_cart_helper;
311	311	int m_last_offs;
312	312	UINT8 m_mmu, m_ext_bank;
313
	313
314	314	void setup_ram(int bank,UINT32 size);
315	315	void setup_cart(a800_cart_slot_device *slot);
316	316	};
r32760	r32761
334	334
335	335	READ8_MEMBER(a400_state::a1200xl_low_r)
336	336	{
337		if (offset < 0x5000) // 0x0000-0x4fff
	337	if (offset < 0x5000) // 0x0000-0x4fff
338	338	return m_ram->pointer()[offset];
339		else if (offset < 0x5800) // 0x5000-0x57ff
	339	else if (offset < 0x5800) // 0x5000-0x57ff
340	340	{
341	341	if (m_mmu & 0x80)
342	342	return m_ram->pointer()[offset];
343	343	else
344	344	return m_region_maincpu->base()[0xd000 + (offset & 0x7ff)];
345	345	}
346		else if (offset < 0xc000) // 0x5800-0xbfff
	346	else if (offset < 0xc000) // 0x5800-0xbfff
347	347	return m_ram->pointer()[offset];
348		else // 0xc000-0xcfff
	348	else // 0xc000-0xcfff
349	349	{
350	350	if (!(m_mmu & 0x01))
351	351	return m_ram->pointer()[offset];
r32760	r32761
356	356
357	357	READ8_MEMBER(a400_state::a800xl_low_r)
358	358	{
359		if (offset < 0x5000) // 0x0000-0x4fff
	359	if (offset < 0x5000) // 0x0000-0x4fff
360	360	return m_ram->pointer()[offset];
361		else if (offset < 0x5800) // 0x5000-0x57ff
	361	else if (offset < 0x5800) // 0x5000-0x57ff
362	362	{
363	363	if (m_mmu & 0x80)
364	364	return m_ram->pointer()[offset];
365	365	else
366	366	return m_region_maincpu->base()[0xd000 + (offset & 0x7ff)];
367	367	}
368		else if (offset < 0xa000) // 0x5800-0x9fff
	368	else if (offset < 0xa000) // 0x5800-0x9fff
369	369	return m_ram->pointer()[offset];
370		else if (offset < 0xc000) // 0xa000-0xbfff
	370	else if (offset < 0xc000) // 0xa000-0xbfff
371	371	{
372	372	if (m_mmu & 0x02)
373	373	return m_ram->pointer()[offset];
374	374	else
375	375	return m_region_maincpu->base()[(offset & 0x1fff) + 0xa000];
376	376	}
377		else // 0xc000-0xcfff
	377	else // 0xc000-0xcfff
378	378	{
379	379	if (!(m_mmu & 0x01))
380	380	return m_ram->pointer()[offset];
r32760	r32761
385	385
386	386	WRITE8_MEMBER(a400_state::a800xl_low_w)
387	387	{
388		if (offset < 0x5000) // 0x0000-0x4fff
	388	if (offset < 0x5000) // 0x0000-0x4fff
389	389	m_ram->pointer()[offset] = data;
390		else if (offset < 0x5800) // 0x5000-0x57ff
	390	else if (offset < 0x5800) // 0x5000-0x57ff
391	391	{
392	392	if (m_mmu & 0x80)
393	393	m_ram->pointer()[offset] = data;
394	394	}
395		else if (offset < 0xa000) // 0x5800-0x7fff
	395	else if (offset < 0xa000) // 0x5800-0x7fff
396	396	m_ram->pointer()[offset] = data;
397		else if (offset < 0xc000) // 0xa000-0xbfff
	397	else if (offset < 0xc000) // 0xa000-0xbfff
398	398	{
399	399	if (m_mmu & 0x02)
400	400	m_ram->pointer()[offset] = data;
401	401	}
402		else // 0xc000-0xcfff
	402	else // 0xc000-0xcfff
403	403	{
404	404	if (!(m_mmu & 0x01))
405	405	m_ram->pointer()[offset] = data;
r32760	r32761
422	422
423	423	READ8_MEMBER(a400_state::a130xe_low_r)
424	424	{
425		if (offset < 0x4000) // 0x0000-0x3fff
	425	if (offset < 0x4000) // 0x0000-0x3fff
426	426	return m_ram->pointer()[offset];
427		else if (offset < 0x8000) // 0x4000-0x7fff
	427	else if (offset < 0x8000) // 0x4000-0x7fff
428	428	{
429	429	// NOTE: ANTIC accesses to extra RAM are not supported yet!
430	430	if (!(m_mmu & 0x80) && offset >= 0x5000 && offset < 0x5800)
r32760	r32761
434	434	else
435	435	return m_ram->pointer()[offset];
436	436	}
437		else if (offset < 0xa000) // 0x8000-0x9fff
	437	else if (offset < 0xa000) // 0x8000-0x9fff
438	438	return m_ram->pointer()[offset];
439		else if (offset < 0xc000) // 0xa000-0xbfff
	439	else if (offset < 0xc000) // 0xa000-0xbfff
440	440	{
441	441	if (m_mmu & 0x02)
442	442	return m_ram->pointer()[offset];
443	443	else
444	444	return m_region_maincpu->base()[(offset & 0x1fff) + 0xa000];
445	445	}
446		else // 0xc000-0xcfff
	446	else // 0xc000-0xcfff
447	447	{
448	448	if (!(m_mmu & 0x01))
449	449	return m_ram->pointer()[offset];
r32760	r32761
454	454
455	455	WRITE8_MEMBER(a400_state::a130xe_low_w)
456	456	{
457		if (offset < 0x4000) // 0x0000-0x3fff
	457	if (offset < 0x4000) // 0x0000-0x3fff
458	458	m_ram->pointer()[offset] = data;
459		else if (offset < 0x8000) // 0x4000-0x7fff
	459	else if (offset < 0x8000) // 0x4000-0x7fff
460	460	{
461	461	// NOTE: ANTIC accesses to extra RAM are not supported yet!
462	462	if (!(m_mmu & 0x80) && offset >= 0x5000 && offset < 0x5800)
r32760	r32761
466	466	else
467	467	m_ram->pointer()[offset] = data;
468	468	}
469		else if (offset < 0xa000) // 0x5800-0x7fff
	469	else if (offset < 0xa000) // 0x5800-0x7fff
470	470	m_ram->pointer()[offset] = data;
471		else if (offset < 0xc000) // 0xa000-0xbfff
	471	else if (offset < 0xc000) // 0xa000-0xbfff
472	472	{
473	473	if (m_mmu & 0x02)
474	474	m_ram->pointer()[offset] = data;
475	475	}
476		else // 0xc000-0xcfff
	476	else // 0xc000-0xcfff
477	477	{
478	478	if (!(m_mmu & 0x01))
479	479	m_ram->pointer()[offset] = data;
r32760	r32761
482	482
483	483	READ8_MEMBER(a400_state::xegs_low_r)
484	484	{
485		if (offset < 0x5000) // 0x0000-0x4fff
	485	if (offset < 0x5000) // 0x0000-0x4fff
486	486	return m_ram->pointer()[offset];
487		else if (offset < 0x5800) // 0x5000-0x57ff
	487	else if (offset < 0x5800) // 0x5000-0x57ff
488	488	{
489	489	if (m_mmu & 0x80)
490	490	return m_ram->pointer()[offset];
491	491	else
492	492	return m_region_maincpu->base()[0xd000 + (offset & 0x7ff)];
493	493	}
494		else if (offset < 0x8000) // 0x5800-0x7fff
	494	else if (offset < 0x8000) // 0x5800-0x7fff
495	495	return m_ram->pointer()[offset];
496		else if (offset < 0xa000) // 0x8000-0x9fff
	496	else if (offset < 0xa000) // 0x8000-0x9fff
497	497	return m_region_maincpu->base()[0x8000 + (offset & 0x1fff)];
498		else if (offset < 0xc000) // 0xa000-0xbfff
	498	else if (offset < 0xc000) // 0xa000-0xbfff
499	499	return m_region_maincpu->base()[0x8000 + (offset & 0x1fff)];
500		else // 0xc000-0xcfff
	500	else // 0xc000-0xcfff
501	501	{
502	502	if (!(m_mmu & 0x01))
503	503	return m_ram->pointer()[offset];
r32760	r32761
508	508
509	509	WRITE8_MEMBER(a400_state::xegs_low_w)
510	510	{
511		if (offset < 0x5000) // 0x0000-0x4fff
	511	if (offset < 0x5000) // 0x0000-0x4fff
512	512	m_ram->pointer()[offset] = data;
513		else if (offset < 0x5800) // 0x5000-0x57ff
	513	else if (offset < 0x5800) // 0x5000-0x57ff
514	514	{
515	515	if (m_mmu & 0x80)
516	516	m_ram->pointer()[offset] = data;
517	517	}
518		else if (offset < 0x8000) // 0x5800-0x7fff
	518	else if (offset < 0x8000) // 0x5800-0x7fff
519	519	m_ram->pointer()[offset] = data;
520		else if (offset < 0xc000) // 0xa000-0xbfff
	520	else if (offset < 0xc000) // 0xa000-0xbfff
521	521	return;
522		else // 0xc000-0xcfff
	522	else // 0xc000-0xcfff
523	523	{
524	524	if (!(m_mmu & 0x01))
525	525	m_ram->pointer()[offset] = data;
r32760	r32761
1705	1705
1706	1706	switch (bank)
1707	1707	{
1708		case 0: // 0x0000-0x7fff
	1708	case 0: // 0x0000-0x7fff
1709	1709	ram_top = MIN(size, 0x8000) - 1;
1710	1710	m_maincpu->space(AS_PROGRAM).install_readwrite_bank(0x0000, ram_top, "0000");
1711	1711	if (m_0000 == NULL)
1712	1712	m_0000.findit();
1713	1713	m_0000->set_base(m_ram->pointer());
1714	1714	break;
1715		case 1: // 0x8000-0x9fff
	1715	case 1: // 0x8000-0x9fff
1716	1716	ram_top = MIN(size, 0xa000) - 1;
1717	1717	if (ram_top > 0x8000)
1718	1718	{
r32760	r32761
1720	1720	if (m_8000 == NULL)
1721	1721	m_8000.findit();
1722	1722	m_8000->set_base(m_ram->pointer() + 0x8000);
1723		}
	1723	}
1724	1724	break;
1725		case 2: // 0xa000-0xbfff
	1725	case 2: // 0xa000-0xbfff
1726	1726	ram_top = MIN(size, 0xc000) - 1;
1727	1727	if (ram_top > 0xa000)
1728	1728	{
r32760	r32761
1730	1730	if (m_a000 == NULL)
1731	1731	m_a000.findit();
1732	1732	m_a000->set_base(m_ram->pointer() + 0xa000);
1733		}
	1733	}
1734	1734	break;
1735	1735	}
1736	1736	}
r32760	r32761
1745	1745	{
1746	1746	offset += 0x8000;
1747	1747	if (m_ram->size() < offset)
1748		return 0;
	1748	return 0;
1749	1749	else
1750	1750	return m_ram->pointer()[offset];
1751	1751	}
r32760	r32761
1769	1769	{
1770	1770	offset += 0xa000;
1771	1771	if (m_ram->size() < offset)
1772		return 0;
	1772	return 0;
1773	1773	else
1774	1774	return m_ram->pointer()[offset];
1775	1775	}
r32760	r32761
1808	1808	case A800_EXPRESS:
1809	1809	case A800_DIAMOND:
1810	1810	case A800_WILLIAMS:
1811		// use m_cart_disabled & m_last_offs to avoid continuous remapping of
	1811	// use m_cart_disabled & m_last_offs to avoid continuous remapping of
1812	1812	// the memory space in some games (e.g. dropzone)
1813	1813	if (offset & 0x8 && !m_cart_disabled)
1814	1814	m_cart_disabled = 1;
r32760	r32761
1816	1816	{
1817	1817	if (m_cart_disabled)
1818	1818	m_cart_disabled = 0;
1819
	1819
1820	1820	if ((offset & 0x7) != m_last_offs)
1821	1821	{
1822	1822	// we enter here only if we are writing to a different offset than last time
r32760	r32761
1833	1833	{
1834	1834	if (m_cart_disabled)
1835	1835	m_cart_disabled = 0;
1836
	1836
1837	1837	if ((offset & 0x0f) != m_last_offs)
1838	1838	{
1839	1839	// we enter here only if we are writing to a different offset than last time
r32760	r32761
1845	1845	case A800_SPARTADOS:
1846	1846	// writes with offset & 8 are also used to enable/disable the subcart, so they go through!
1847	1847	m_cart->write_d5xx(space, offset, data);
1848		break;
	1848	break;
1849	1849	case A800_OSSM091:
1850	1850	case A800_OSS8K:
1851	1851	if ((offset & 0x9) == 0x08)
r32760	r32761
1868	1868	break;
1869	1869	default:
1870	1870	break;
1871		}
	1871	}
1872	1872	}
1873	1873	}
1874	1874
r32760	r32761
1958	1958	m_maincpu->space(AS_PROGRAM).install_write_handler(0x4000, 0x5fff, write8_delegate(FUNC(a800_cart_slot_device::write_80xx),(a800_cart_slot_device*)slot));
1959	1959	m_maincpu->space(AS_PROGRAM).unmap_write(0x6000, 0xbfff);
1960	1960	break;
1961		}
	1961	}
1962	1962	}
1963	1963	}
1964	1964
r32760	r32761
2014	2014	MACHINE_START_MEMBER( a400_state, a800xl )
2015	2015	{
2016	2016	m_mmu = 0xfd;
2017		m_ext_bank = 0x03; // only used by a130xe
	2017	m_ext_bank = 0x03; // only used by a130xe
2018	2018	setup_cart(m_cart);
2019	2019
2020	2020	save_item(NAME(m_cart_disabled));
r32760	r32761
2056	2056	**************************************************************/
2057	2057
2058	2058	WRITE8_MEMBER(a400_state::a600xl_pia_pb_w)
2059		{
2060		m_mmu = data;
	2059	{
	2060	m_mmu = data;
2061	2061	}
2062	2062
2063	2063	WRITE8_MEMBER(a400_state::a800xl_pia_pb_w)

trunk/src/mess/drivers/pv1000.c
r32760	r32761
185	185
186	186
187	187	static ADDRESS_MAP_START( pv1000, AS_PROGRAM, 8, pv1000_state )
188		//AM_RANGE(0x0000, 0x7fff) // mapped by the cartslot
	188	//AM_RANGE(0x0000, 0x7fff) // mapped by the cartslot
189	189	AM_RANGE(0xb800, 0xbbff) AM_RAM AM_SHARE("p_videoram")
190	190	AM_RANGE(0xbc00, 0xbfff) AM_RAM_WRITE(gfxram_w) AM_REGION("gfxram", 0)
191	191	ADDRESS_MAP_END
r32760	r32761
312	312	DEVICE_IMAGE_LOAD_MEMBER( pv1000_state, pv1000_cart )
313	313	{
314	314	UINT32 size = m_cart->common_get_size("rom");
315
	315
316	316	if (size != 0x2000 && size != 0x4000)
317	317	{
318	318	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
319	319	return IMAGE_INIT_FAIL;
320	320	}
321
	321
322	322	m_cart->rom_alloc(size, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
323		m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
324
	323	m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
	324
325	325	return IMAGE_INIT_PASS;
326	326	}
327	327
r32760	r32761
407	407	// FIXME: this is needed for gfx decoding, but there is probably a cleaner solution!
408	408	astring region_tag;
409	409	memcpy(memregion("gfxrom")->base(), memregion(region_tag.cpy(m_cart->tag()).cat(GENERIC_ROM_REGION_TAG))->base(), m_cart->get_rom_size());
410		}
	410	}
411	411
412	412	save_item(NAME(m_io_regs));
413	413	save_item(NAME(m_fd_data));

trunk/src/mess/drivers/tvc.c
r32760	r32761
47	47	m_palette(*this, "palette"),
48	48	m_keyboard(*this, "LINE")
49	49	{ }
50
	50
51	51	required_device<cpu_device> m_maincpu;
52	52	required_device<ram_device> m_ram;
53	53	required_device<tvc_sound_device> m_sound;
r32760	r32761
65	65
66	66	void machine_start();
67	67	void machine_reset();
68
	68
69	69	void set_mem_page(UINT8 data);
70	70	DECLARE_WRITE8_MEMBER(bank_w);
71	71	DECLARE_WRITE8_MEMBER(vram_bank_w);
r32760	r32761
80	80	DECLARE_READ8_MEMBER(_5b_r);
81	81	DECLARE_WRITE_LINE_MEMBER(int_ff_set);
82	82	DECLARE_WRITE_LINE_MEMBER(centronics_ack);
83
	83
84	84	// expansions
85	85	DECLARE_WRITE8_MEMBER(expansion_w);
86	86	DECLARE_READ8_MEMBER(expansion_r);
87	87	DECLARE_READ8_MEMBER(exp_id_r);
88	88	DECLARE_WRITE8_MEMBER(expint_ack_w);
89
	89
90	90	DECLARE_QUICKLOAD_LOAD_MEMBER( tvc64);
91
	91
92	92	MC6845_UPDATE_ROW(crtc_update_row);
93
	93
94	94	UINT8 m_video_mode;
95	95	UINT8 m_keyline;
96	96	UINT8 m_active_slot;

trunk/src/mess/drivers/nc.c
r32760	r32761
801	801	m_card_size = m_card_ram->bytes();
802	802	else
803	803	m_card_size = 0;
804
	804
805	805	/* keyboard timer */
806	806	m_keyboard_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(nc_state::nc_keyboard_timer_callback),this));
807	807	m_keyboard_timer->adjust(attotime::from_msec(10));
r32760	r32761
1138	1138	MACHINE_START_MEMBER(nc_state, nc200)
1139	1139	{
1140	1140	m_type = NC_TYPE_200;
1141
	1141
1142	1142	astring region_tag;
1143	1143	m_card_ram = memregion(region_tag.cpy(m_card->tag()).cat(GENERIC_ROM_REGION_TAG));
1144	1144	if (m_card_ram)
1145	1145	m_card_size = m_card_ram->bytes();
1146	1146	else
1147	1147	m_card_size = 0;
1148
	1148
1149	1149	/* keyboard timer */
1150	1150	m_keyboard_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(nc_state::nc_keyboard_timer_callback),this));
1151	1151	m_keyboard_timer->adjust(attotime::from_msec(10));

trunk/src/mess/drivers/gmaster.c
r32760	r32761
182	182	static ADDRESS_MAP_START( gmaster_mem, AS_PROGRAM, 8, gmaster_state )
183	183	AM_RANGE(0x0000, 0x3fff) AM_ROM
184	184	AM_RANGE(0x4000, 0x7fff) AM_READWRITE(gmaster_io_r, gmaster_io_w)
185		//AM_RANGE(0x8000, 0xfeff) // mapped by the cartslot
	185	//AM_RANGE(0x8000, 0xfeff) // mapped by the cartslot
186	186	AM_RANGE(0xff00, 0xffff) AM_RAM
187	187	ADDRESS_MAP_END
188	188

trunk/src/mess/drivers/kyocera.c
r32760	r32761
1167	1167	void kc85_state::machine_start()
1168	1168	{
1169	1169	address_space &program = m_maincpu->space(AS_PROGRAM);
1170
	1170
1171	1171	astring region_tag;
1172	1172	m_opt_region = memregion(region_tag.cpy(m_opt_cart->tag()).cat(GENERIC_ROM_REGION_TAG));
1173
	1173
1174	1174	/* initialize RTC */
1175	1175	m_rtc->cs_w(1);
1176	1176	m_rtc->oe_w(1);
r32760	r32761
1210	1210	void pc8201_state::machine_start()
1211	1211	{
1212	1212	UINT8 *ram = m_ram->pointer();
1213
	1213
1214	1214	astring region_tag;
1215	1215	m_opt_region = memregion(region_tag.cpy(m_opt_cart->tag()).cat(GENERIC_ROM_REGION_TAG));
1216
	1216
1217	1217	/* initialize RTC */
1218	1218	m_rtc->cs_w(1);
1219	1219	m_rtc->oe_w(1);
r32760	r32761
1244	1244	void trsm100_state::machine_start()
1245	1245	{
1246	1246	address_space &program = m_maincpu->space(AS_PROGRAM);
1247
	1247
1248	1248	astring region_tag;
1249	1249	m_opt_region = memregion(region_tag.cpy(m_opt_cart->tag()).cat(GENERIC_ROM_REGION_TAG));
1250
	1250
1251	1251	/* initialize RTC */
1252	1252	m_rtc->cs_w(1);
1253	1253	m_rtc->oe_w(1);

trunk/src/mess/drivers/cgenie.c
r32760	r32761
492	492	DEVICE_IMAGE_LOAD_MEMBER( cgenie_state, cgenie_cart )
493	493	{
494	494	UINT32 size = m_cart->common_get_size("rom");
495
	495
496	496	if (size > 0x1000)
497	497	{
498	498	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
499	499	return IMAGE_INIT_FAIL;
500	500	}
501
	501
502	502	m_cart->rom_alloc(0x1000, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
503		m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
504
	503	m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
	504
505	505	return IMAGE_INIT_PASS;
506	506	}
507	507

trunk/src/mess/drivers/spectrum.c
r32760	r32761
654	654	DEVICE_IMAGE_LOAD_MEMBER(spectrum_state, spectrum_cart)
655	655	{
656	656	UINT32 size = m_cart->common_get_size("rom");
657
	657
658	658	if (size != 0x4000)
659	659	{
660	660	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
661	661	return IMAGE_INIT_FAIL;
662	662	}
663
	663
664	664	m_cart->rom_alloc(size, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
665		m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
666
	665	m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
	666
667	667	return IMAGE_INIT_PASS;
668	668	}
669	669

trunk/src/mess/drivers/itt3030.c
r32760	r32761
324	324	{
325	325	if (offset)
326	326	{
327		// printf("Read 8078 status\n");
	327	// printf("Read 8078 status\n");
328	328	if (!m_keyskip)
329	329	{
330		return 0x10;
	330	return 0x10;
331	331	}
332	332	}
333	333	else
334	334	{
335		// printf("Read 8078 data\n");
	335	// printf("Read 8078 data\n");
336	336	if (!m_keyskip)
337	337	{
338		m_keyskip = true; // don't keep reporting the 'b' key, just the once to trick the boot ROM
	338	m_keyskip = true; // don't keep reporting the 'b' key, just the once to trick the boot ROM
339	339	return 0x0c;
340	340	}
341	341	}
r32760	r32761
433	433	}
434	434
435	435	/*
436		7 Data Request (DRQ - inverted 1791-Signal)
437		6 Interrupt Request (INTRQ - 1791-Signal)
438		5 Head Load (HLD - inverted 1791-Signal)
439		4 Ready 3 (Drive 3 ready)
440		3 Ready 2 (Drive 2 ready)
441		2 Ready l (Drive 1 ready)
442		1 Write protect (the disk in the selected drive is write protected)
443		0 HLT (Halt signal during head load and track change)
	436	7 Data Request (DRQ - inverted 1791-Signal)
	437	6 Interrupt Request (INTRQ - 1791-Signal)
	438	5 Head Load (HLD - inverted 1791-Signal)
	439	4 Ready 3 (Drive 3 ready)
	440	3 Ready 2 (Drive 2 ready)
	441	2 Ready l (Drive 1 ready)
	442	1 Write protect (the disk in the selected drive is write protected)
	443	0 HLT (Halt signal during head load and track change)
444	444	*/
445	445	READ8_MEMBER(itt3030_state::fdc_stat_r)
446	446	{
447	447	UINT8 res = 0;
448		floppy_image_device *floppy1 = m_con1 ? m_con1->get_device() : 0;
449		floppy_image_device *floppy2 = m_con2 ? m_con2->get_device() : 0;
450		floppy_image_device *floppy3 = m_con3 ? m_con3->get_device() : 0;
	448	floppy_image_device *floppy1 = m_con1 ? m_con1->get_device() : 0;
	449	floppy_image_device *floppy2 = m_con2 ? m_con2->get_device() : 0;
	450	floppy_image_device *floppy3 = m_con3 ? m_con3->get_device() : 0;
451	451
452	452	res = m_fdc_drq ? 0x80 : 0x00;
453	453	res \|= m_fdc_irq ? 0x40 : 0x00;
r32760	r32761
472	472	}
473	473
474	474	/*
475		7 SEL1 - Select drive 1
476		6 SEL2 - Select drive 2
477		5 SEL3 - Select drive 3
478		4 MOTOR - Motor on
479		3 DOOR - Drive door lock drives 1 + 2 (not possible with all drives)
480		2 SIDESEL - Select disk side
481		1 KOMP - write comp on/off
482		0 RG J - Change separator stage to read
	475	7 SEL1 - Select drive 1
	476	6 SEL2 - Select drive 2
	477	5 SEL3 - Select drive 3
	478	4 MOTOR - Motor on
	479	3 DOOR - Drive door lock drives 1 + 2 (not possible with all drives)
	480	2 SIDESEL - Select disk side
	481	1 KOMP - write comp on/off
	482	0 RG J - Change separator stage to read
483	483	*/
484	484	WRITE8_MEMBER(itt3030_state::fdc_cmd_w)
485	485	{

trunk/src/mess/drivers/x07.c
r32760	r32761
1038	1038	DEVICE_IMAGE_LOAD_MEMBER( x07_state, x07_card )
1039	1039	{
1040	1040	UINT32 size = m_card->common_get_size("rom");
1041
	1041
1042	1042	// check card type
1043	1043	if (image.software_entry() != NULL)
1044	1044	{
1045	1045	const char *card_type = image.get_feature("card_type");
1046
	1046
1047	1047	if (strcmp(card_type, "xp140"))
1048	1048	{
1049	1049	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported card type");
r32760	r32761
1052	1052	}
1053	1053
1054	1054	m_card->rom_alloc(size, GENERIC_ROM8_WIDTH, ENDIANNESS_BIG);
1055		m_card->common_load_rom(m_card->get_rom_base(), size, "rom");
	1055	m_card->common_load_rom(m_card->get_rom_base(), size, "rom");
1056	1056
1057	1057	m_card->ram_alloc(0x1000);
1058	1058

trunk/src/mess/drivers/bbcbc.c
r32760	r32761
42	42
43	43	static ADDRESS_MAP_START( bbcbc_prg, AS_PROGRAM, 8, bbcbc_state )
44	44	AM_RANGE(0x0000, 0x3fff) AM_ROM
45		//AM_RANGE(0x4000, 0xbfff) // mapped by the cartslot
	45	//AM_RANGE(0x4000, 0xbfff) // mapped by the cartslot
46	46	AM_RANGE(0xe000, 0xe02f) AM_RAM
47	47	AM_RANGE(0xe030, 0xe030) AM_READ_PORT("LINE01")
48	48	AM_RANGE(0xe031, 0xe031) AM_READ_PORT("LINE02")

trunk/src/mess/drivers/sorcerer.c
r32760	r32761
163	163	ADDRESS_MAP_UNMAP_HIGH
164	164	AM_RANGE(0x0000, 0x07ff) AM_RAMBANK("boot")
165	165	AM_RANGE(0x0800, 0xbfff) AM_RAM
166		//AM_RANGE(0xc000, 0xdfff) // mapped by the cartslot
	166	//AM_RANGE(0xc000, 0xdfff) // mapped by the cartslot
167	167	AM_RANGE(0xe000, 0xefff) AM_ROM /* rom pac and bios */
168	168	AM_RANGE(0xf000, 0xf7ff) AM_RAM AM_REGION("maincpu", 0xf000) /* screen ram */
169	169	AM_RANGE(0xf800, 0xfbff) AM_ROM /* char rom */
r32760	r32761
176	176	AM_RANGE(0x0800, 0xbbff) AM_RAM
177	177	AM_RANGE(0xbc00, 0xbcff) AM_ROM
178	178	AM_RANGE(0xbe00, 0xbe03) AM_DEVREADWRITE("fdc", micropolis_device, read, write)
179		//AM_RANGE(0xc000, 0xdfff) // mapped by the cartslot
	179	//AM_RANGE(0xc000, 0xdfff) // mapped by the cartslot
180	180	AM_RANGE(0xe000, 0xefff) AM_ROM /* rom pac and bios */
181	181	AM_RANGE(0xf000, 0xf7ff) AM_RAM AM_REGION("maincpu", 0xf000) /* screen ram */
182	182	AM_RANGE(0xf800, 0xfbff) AM_ROM /* char rom */

trunk/src/mess/drivers/crvision.c
r32760	r32761
712	712	// state saving
713	713	save_item(NAME(m_keylatch));
714	714	save_item(NAME(m_joylatch));
715
	715
716	716	if (m_cart->exists())
717	717	{
718	718	m_maincpu->space(AS_PROGRAM).install_read_handler(0x4000, 0x7fff, read8_delegate(FUNC(crvision_cart_slot_device::read_rom40),(crvision_cart_slot_device*)m_cart));
r32760	r32761
729	729	// state saving
730	730	save_item(NAME(m_keylatch));
731	731	save_item(NAME(m_joylatch));
732
	732
733	733	if (m_cart->exists())
734	734	{
735	735	m_maincpu->space(AS_PROGRAM).install_read_handler(0x4000, 0x7fff, read8_delegate(FUNC(crvision_cart_slot_device::read_rom40),(crvision_cart_slot_device*)m_cart));

trunk/src/mess/drivers/pv2000.c
r32760	r32761
179	179
180	180	AM_RANGE(0x7000, 0x7fff) AM_RAM
181	181	//AM_RANGE(0x8000, 0xbfff) ext ram?
182		//AM_RANGE(0xc000, 0xffff) // mapped by the cartslot
	182	//AM_RANGE(0xc000, 0xffff) // mapped by the cartslot
183	183	ADDRESS_MAP_END
184	184
185	185
r32760	r32761
361	361	DEVICE_IMAGE_LOAD_MEMBER( pv2000_state, pv2000_cart )
362	362	{
363	363	UINT32 size = m_cart->common_get_size("rom");
364
	364
365	365	if (size != 0x2000 && size != 0x4000)
366	366	{
367	367	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
368	368	return IMAGE_INIT_FAIL;
369	369	}
370
	370
371	371	m_cart->rom_alloc(size, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
372		m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
373
	372	m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
	373
374	374	return IMAGE_INIT_PASS;
375	375	}
376	376

trunk/src/mess/drivers/msx.c
r32760	r32761
1926	1926	// 1? Cartridge slot
1927	1927	// No keyboard?
1928	1928	// No cassette port?
1929		// No printer port?
1930
	1929	// No printer port?
	1930
1931	1931	MCFG_MSX_LAYOUT_ROM("bios", 0, 0, 0, 2, "maincpu", 0x0000)
1932	1932	MCFG_MSX_LAYOUT_CARTRIDGE("cartslot1", 1, 0)
1933	1933	MCFG_MSX_LAYOUT_RAM("ram", 2, 0, 3, 1) /* 16KB RAM */
r32760	r32761
2142	2142	MCFG_MSX_LAYOUT_CARTRIDGE("cartslot1", 1, 0)
2143	2143	MCFG_MSX_LAYOUT_RAM("ram", 2, 0, 0, 4) // 64KB RAM
2144	2144	MCFG_MSX_LAYOUT_CARTRIDGE("cartslot2", 3, 0)
2145
	2145
2146	2146	MCFG_FRAGMENT_ADD( msx1_cartlist )
2147	2147	MACHINE_CONFIG_END
2148	2148
r32760	r32761
4009	4009	// AY8910/YM2149?
4010	4010	// FDC: None, 0 drives,
4011	4011	// 2 Cartridge slots?
4012
	4012
4013	4013	MCFG_MSX_LAYOUT_ROM("bios", 0, 0, 0, 2, "maincpu", 0x0000)
4014	4014	MCFG_MSX_LAYOUT_CARTRIDGE("cartslot1", 1, 0)
4015	4015	MCFG_MSX_LAYOUT_RAM("ram", 2, 0, 2, 2) // 32KB RAM
r32760	r32761
4029	4029	// AY8910/YM2149?
4030	4030	// FDC: None, 0 drives,
4031	4031	// 2 Cartridge slots?
4032
	4032
4033	4033	MCFG_MSX_LAYOUT_ROM("bios", 0, 0, 0, 2, "maincpu", 0x0000)
4034	4034	MCFG_MSX_LAYOUT_CARTRIDGE("cartslot1", 1, 0)
4035	4035	MCFG_MSX_LAYOUT_RAM("ram", 2, 0, 0, 4) // 64KB RAM
r32760	r32761
4062	4062
4063	4063	/* MSX - Yamaha CX5F (with SFG05) */
4064	4064
4065		ROM_START (cx5f)
	4065	ROM_START (cx5f)
4066	4066	ROM_REGION (0x8000, "maincpu", 0)
4067	4067	ROM_LOAD ("cx5fbios.rom", 0x0000, 0x8000, CRC(dc662057) SHA1(36d77d357a5fd15af2ab266ee66e5091ba4770a3))
4068	4068	ROM_END
r32760	r32761
6036	6036	/* MSX2 - Sanyo MPC-2500FD */
6037	6037
6038	6038	ROM_START (mpc2500f)
6039		ROM_REGION (0x10000, "maincpu", 0)
6040		ROM_LOAD ("mpc2500fdbios.rom", 0x0000, 0x8000, CRC(e7d08e29) SHA1(0f851ee7a1cf79819f61cc89e9948ee72a413802))
6041		ROM_LOAD ("mpc2500fdext.rom", 0x8000, 0x4000, CRC(3d7dc718) SHA1(e1f834b28c3ee7c9f79fe6fbf2b23c8a0617892b))
	6039	ROM_REGION (0x10000, "maincpu", 0)
	6040	ROM_LOAD ("mpc2500fdbios.rom", 0x0000, 0x8000, CRC(e7d08e29) SHA1(0f851ee7a1cf79819f61cc89e9948ee72a413802))
	6041	ROM_LOAD ("mpc2500fdext.rom", 0x8000, 0x4000, CRC(3d7dc718) SHA1(e1f834b28c3ee7c9f79fe6fbf2b23c8a0617892b))
6042	6042	ROM_LOAD ("mpc2500fddisk.rom", 0xc000, 0x4000, CRC(38454059) SHA1(58ac78bba29a06645ca8d6a94ef2ac68b743ad32))
6043	6043	ROM_END
6044	6044
6045	6045	static MACHINE_CONFIG_DERIVED( mpc2500f, msx2 )
6046		// YM2149
6047		// FDC: wd2793?, 1? 3.5" DSDD drive?
6048		// 2 Cartridge slots?
	6046	// YM2149
	6047	// FDC: wd2793?, 1? 3.5" DSDD drive?
	6048	// 2 Cartridge slots?
6049	6049	// S-3527 MSX Eninge
6050	6050
6051		MCFG_MSX_LAYOUT_ROM("bios", 0, 0, 0, 2, "maincpu", 0x0000)
6052		MCFG_MSX_LAYOUT_CARTRIDGE("cartslot1", 1, 0)
6053		MCFG_MSX_LAYOUT_CARTRIDGE("cartslot2", 2, 0)
	6051	MCFG_MSX_LAYOUT_ROM("bios", 0, 0, 0, 2, "maincpu", 0x0000)
	6052	MCFG_MSX_LAYOUT_CARTRIDGE("cartslot1", 1, 0)
	6053	MCFG_MSX_LAYOUT_CARTRIDGE("cartslot2", 2, 0)
6054	6054	MCFG_MSX_LAYOUT_ROM("ext", 2, 3, 0, 1, "maincpu", 0x8000)
6055	6055	MCFG_MSX_LAYOUT_DISK1("disk", 3, 1, 1, 1, "maincpu", 0xC000)
6056		MCFG_MSX_LAYOUT_RAM_MM("ram_mm", 3, 2, 0x10000) /* 64KB?? Mapper RAM */
	6056	MCFG_MSX_LAYOUT_RAM_MM("ram_mm", 3, 2, 0x10000) /* 64KB?? Mapper RAM */
6057	6057
6058	6058	MCFG_FRAGMENT_ADD( msx_wd2793_force_ready )
6059	6059	MCFG_FRAGMENT_ADD( msx_1_35_dd_drive )
6060	6060	MCFG_FRAGMENT_ADD( msx2_floplist )
6061	6061
6062		MCFG_FRAGMENT_ADD( msx2_cartlist )
	6062	MCFG_FRAGMENT_ADD( msx2_cartlist )
6063	6063	MACHINE_CONFIG_END
6064	6064
6065	6065	/* MSX2 - Sanyo Wavy MPC-25FD */
r32760	r32761
7202	7202	ROM_LOAD ("hc95aext.rom", 0x8000, 0x4000, CRC(4a48779c) SHA1(b8e30d604d319d511cbfbc61e5d8c38fbb9c5a33))
7203	7203	ROM_LOAD ("hc95adisk.rom", 0xc000, 0x4000, CRC(11bca2ed) SHA1(a7a34671bddb48fa6c74182e2977f9129558ec32))
7204	7204	ROM_LOAD ("hc95afirm.rom", 0x10000, 0x4000, CRC(53791d91) SHA1(caeffdd654394726c8c0824b21af7ff51c0b1031))
7205
	7205
7206	7206	ROM_REGION (0x20000, "kanji", 0)
7207	7207	ROM_LOAD ("hc95akfn.rom", 0x0000, 0x20000, CRC(d23d4d2d) SHA1(db03211b7db46899df41db2b1dfbec972109a967))
7208	7208	ROM_END
r32760	r32761
7215	7215	// 1 Cartridge slot (slot 1 or 2?)
7216	7216	// S-1985 MSX Engine
7217	7217	// V9958 VDP
7218
	7218
7219	7219	MCFG_MSX_LAYOUT_ROM("bios", 0, 0, 0, 2, "maincpu", 0x0000)
7220	7220	MCFG_MSX_LAYOUT_ROM("ext", 0, 1, 0, 1, "maincpu", 0x8000)
7221	7221	MCFG_MSX_LAYOUT_ROM("firm", 0, 1, 1, 1, "maincpu", 0x10000)
r32760	r32761
7387	7387
7388	7388	static MACHINE_CONFIG_DERIVED( yis604, msx2 )
7389	7389	// YM2149 (in S-3527)
7390		// FDC: None, 0 drives
	7390	// FDC: None, 0 drives
7391	7391	// 2 Cartridge slots
7392	7392	// S-3527 MSX Engine
7393	7393
r32760	r32761
7398	7398	MCFG_MSX_LAYOUT_ROM("yrm502", 3, 1, 1, 1, "maincpu", 0xc000)
7399	7399	MCFG_MSX_LAYOUT_RAM_MM("ram_mm", 3, 2, 0x10000) // 64KB Mapper RAM
7400	7400	MCFG_MSX_LAYOUT_YAMAHA_EXPANSION("expansion", 3, 3, "sfg05")
7401
	7401
7402	7402	MCFG_FRAGMENT_ADD( msx2_cartlist )
7403	7403	MACHINE_CONFIG_END
7404	7404
r32760	r32761
8433	8433	/* Temporary placeholders, Turbo-R hardware is not supported yet */
8434	8434	COMP(19??, fsa1gt, 0, 0, fsa1gt, msx2jp, driver_device, 0, "Panasonic", "FS-A1GT (MSX Turbo-R)", GAME_NOT_WORKING)
8435	8435	COMP(19??, fsa1st, 0, 0, fsa1st, msx2jp, driver_device, 0, "Panasonic", "FS-A1ST (MSX Turbo-R)", GAME_NOT_WORKING)
8436

trunk/src/mess/drivers/aim65.c
r32760	r32761
158	158	{
159	159	astring errmsg;
160	160	errmsg.printf("Attempted to load file with wrong extension\nSocket '%s' only accepts files with '.%s' extension",
161		slot_tag, slot_tag);
	161	slot_tag, slot_tag);
162	162	image.seterror(IMAGE_ERROR_UNSPECIFIED, errmsg.cstr());
163	163	return IMAGE_INIT_FAIL;
164	164	}

trunk/src/mess/drivers/apple2.c
r32760	r32761
177	177	The external drive port supports not only 5.25 drives but also UniDisk and
178	178	Apple 3.5 drives, allowing via daisy-chaining any combination of UniDisk,
179	179	Apple 3.5 and Apple 5.25 drives - up to three devices
180
181		----------------------------------
182
183		TK3000 keyboard matrix
184
185		Data bus D0-D7 is X0-X7
186		Address bus A0-A11 is Y0-Y11
187
	180
	181	----------------------------------
	182
	183	TK3000 keyboard matrix
	184
	185	Data bus D0-D7 is X0-X7
	186	Address bus A0-A11 is Y0-Y11
	187
188	188	***************************************************************************/
189	189
190	190
r32760	r32761
267	267	ADDRESS_MAP_END
268	268
269	269	/*
270
	270
271	271	LS259 at H12
272
	272
273	273	A8 = D
274	274	A9 = A
275	275	A10 = B
276	276	A11 = C
277
278		374/259 outputs to 65C02 c000/c010 selected by Z80 WR OR Z80 IORQ? (schematic is not super legible)
279
	277
	278	374/259 outputs to 65C02 c000/c010 selected by Z80 WR OR Z80 IORQ? (schematic is not super legible)
	279
280	280	*/
281	281
282	282	// RAM and ROM alternate in 8K blocks: ROM at 0/4/8/c, RAM at 2/6/a/e (RAM is only 1k and further mirrors inside those locations)
r32760	r32761
1028	1028	SLOT_INTERFACE("mcms1", A2BUS_MCMS1) /* Mountain Computer Music System, card 1 of 2 */
1029	1029	SLOT_INTERFACE("mcms2", A2BUS_MCMS2) /* Mountain Computer Music System, card 2 of 2. must be in card 1's slot + 1! */
1030	1030	SLOT_INTERFACE("dx1", A2BUS_DX1) /* Decillonix DX-1 sampler card */
1031		SLOT_INTERFACE("tm2ho", A2BUS_TIMEMASTERHO) /* Applied Engineering TimeMaster II H.O. */
1032		SLOT_INTERFACE("mouse", A2BUS_MOUSE) /* Apple II Mouse Card */
1033		// SLOT_INTERFACE("magicmusician", A2BUS_MAGICMUSICIAN) /* Magic Musician Card */
	1031	SLOT_INTERFACE("tm2ho", A2BUS_TIMEMASTERHO) /* Applied Engineering TimeMaster II H.O. */
	1032	SLOT_INTERFACE("mouse", A2BUS_MOUSE) /* Apple II Mouse Card */
	1033	// SLOT_INTERFACE("magicmusician", A2BUS_MAGICMUSICIAN) /* Magic Musician Card */
1034	1034	SLOT_INTERFACE_END
1035	1035
1036	1036	static SLOT_INTERFACE_START(apple2eaux_cards)
r32760	r32761
1197	1197	static MACHINE_CONFIG_DERIVED( tk3000, apple2e )
1198	1198	MCFG_CPU_REPLACE("maincpu", M65C02, 1021800) /* close to actual CPU frequency of 1.020484 MHz */
1199	1199
1200		MCFG_CPU_ADD("subcpu", Z80, 1021800) // schematics are illegible on where the clock comes from, but it seems to be the same as the 65C02 clock
	1200	MCFG_CPU_ADD("subcpu", Z80, 1021800) // schematics are illegible on where the clock comes from, but it seems to be the same as the 65C02 clock
1201	1201	MCFG_CPU_PROGRAM_MAP(tk3000_kbd_map)
1202	1202	MACHINE_CONFIG_END
1203	1203
r32760	r32761
1330	1330	MCFG_A2BUS_ONBOARD_ADD("a2bus", "sl4", A2BUS_LASER128, NULL)
1331	1331	MCFG_A2BUS_ONBOARD_ADD("a2bus", "sl5", A2BUS_LASER128, NULL)
1332	1332	MCFG_A2BUS_ONBOARD_ADD("a2bus", "sl6", A2BUS_LASER128, NULL)
1333		MCFG_A2BUS_ONBOARD_ADD("a2bus", "sl7", A2BUS_LASER128, NULL)
	1333	MCFG_A2BUS_ONBOARD_ADD("a2bus", "sl7", A2BUS_LASER128, NULL)
1334	1334	MACHINE_CONFIG_END
1335	1335
1336	1336	static MACHINE_CONFIG_DERIVED( space84, apple2p )
r32760	r32761
1672	1672	ROM_LOAD ( "341-0265-a.chr", 0x1000, 0x1000, BAD_DUMP CRC(2651014d) SHA1(b2b5d87f52693817fc747df087a4aa1ddcdb1f10)) // need to dump real laser rom
1673	1673
1674	1674	ROM_REGION(0x8000,"maincpu",0)
1675		ROM_LOAD( "laser 128ex2 rom version 6.1.bin", 0x000000, 0x008000, CRC(7f911c90) SHA1(125754c1bd777d4c510f5239b96178c6f2e3236b) )
	1675	ROM_LOAD( "laser 128ex2 rom version 6.1.bin", 0x000000, 0x008000, CRC(7f911c90) SHA1(125754c1bd777d4c510f5239b96178c6f2e3236b) )
1676	1676
1677	1677	ROM_REGION( 0x800, "keyboard", ROMREGION_ERASE00 )
1678	1678	ROM_LOAD( "342-0132-c.e12", 0x000, 0x800, BAD_DUMP CRC(e47045f4) SHA1(12a2e718f5f4acd69b6c33a45a4a940b1440a481) ) // need to dump real laser rom

trunk/src/mess/drivers/vc4000.c
r32760	r32761
378	378	m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x1800, 0x1bff, read8_delegate(FUNC(vc4000_cart_slot_device::read_ram),(vc4000_cart_slot_device)m_cart), write8_delegate(FUNC(vc4000_cart_slot_device::write_ram),(vc4000_cart_slot_device)m_cart));
379	379	break;
380	380	// undumped Radofin Hobby Module
381		// case VC4000_HOBBY:
382		// m_maincpu->space(AS_PROGRAM).install_read_handler(0x0000, 0x07ff, read8_delegate(FUNC(vc4000_cart_slot_device::read_rom),(vc4000_cart_slot_device*)m_cart));
383		// m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x0800, 0x0fff, read8_delegate(FUNC(vc4000_cart_slot_device::read_ram),(vc4000_cart_slot_device)m_cart), write8_delegate(FUNC(vc4000_cart_slot_device::write_ram),(vc4000_cart_slot_device)m_cart));
384		// break;
	381	// case VC4000_HOBBY:
	382	// m_maincpu->space(AS_PROGRAM).install_read_handler(0x0000, 0x07ff, read8_delegate(FUNC(vc4000_cart_slot_device::read_rom),(vc4000_cart_slot_device*)m_cart));
	383	// m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x0800, 0x0fff, read8_delegate(FUNC(vc4000_cart_slot_device::read_ram),(vc4000_cart_slot_device)m_cart), write8_delegate(FUNC(vc4000_cart_slot_device::write_ram),(vc4000_cart_slot_device)m_cart));
	384	// break;
385	385	}
386
	386
387	387	m_cart->save_ram();
388	388	}
389	389	}
r32760	r32761
398	398	dynamic_buffer quick_data;
399	399	int read_;
400	400	int result = IMAGE_INIT_FAIL;
401
	401
402	402	quick_length = image.length();
403	403	quick_data.resize(quick_length);
404	404	read_ = image.fread( quick_data, quick_length);
r32760	r32761
420	420	{
421	421	int quick_addr = quick_data[1] * 256 + quick_data[2];
422	422	exec_addr = quick_data[3] * 256 + quick_data[4];
423
	423
424	424	if (quick_length < 0x5)
425	425	{
426	426	image.seterror(IMAGE_ERROR_INVALIDIMAGE, "File too short");
r32760	r32761
436	436	{
437	437	space.write_byte(0x08be, quick_data[3]);
438	438	space.write_byte(0x08bf, quick_data[4]);
439
	439
440	440	for (i = 5; i < quick_length; i++)
441	441	space.write_byte(i - 5 + quick_addr, quick_data[i]);
442
	442
443	443	/* display a message about the loaded quickload */
444	444	image.message(" Quickload: size=%04X : start=%04X : end=%04X : exec=%04X",quick_length-5,quick_addr,quick_addr+quick_length-5,exec_addr);
445
	445
446	446	// Start the quickload
447	447	m_maincpu->set_state_int(S2650_PC, exec_addr);
448	448	result = IMAGE_INIT_PASS;
r32760	r32761
460	460	else
461	461	{
462	462	exec_addr = quick_data[1] * 256 + quick_data[2];
463
	463
464	464	if (exec_addr >= quick_length)
465	465	{
466	466	image.seterror(IMAGE_ERROR_INVALIDIMAGE, "Exec address beyond end of file");
r32760	r32761
482	482	{
483	483	space.write_byte(0x08be, quick_data[1]);
484	484	space.write_byte(0x08bf, quick_data[2]);
485
	485
486	486	// load to 08C0-15FF (standard ram + extra)
487	487	int read_ = 0x1600;
488	488	if (quick_length < 0x1600)
489	489	read_ = quick_length;
490	490	for (i = 0x8c0; i < read_; i++)
491	491	space.write_byte(i, quick_data[i]);
492
	492
493	493	// load to 1F50-1FAF (PVI regs)
494	494	read_ = 0x1FB0;
495	495	if (quick_length < 0x1FB0)
r32760	r32761
497	497	if (quick_length > 0x1FC0)
498	498	for (i = 0x1F50; i < read_; i++)
499	499	vc4000_video_w(space, i-0x1f00, quick_data[i]);
500
	500
501	501	/* display a message about the loaded quickload */
502	502	image.message(" Quickload: size=%04X : exec=%04X",quick_length,exec_addr);
503
	503
504	504	// Start the quickload
505	505	m_maincpu->set_state_int(S2650_PC, exec_addr);
506	506	result = IMAGE_INIT_PASS;

trunk/src/mess/drivers/ibmpcjr.c
r32760	r32761
464	464	size -= header_size;
465	465	image.fseek(header_size, SEEK_SET);
466	466	}
467
	467
468	468	slot->rom_alloc(size, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
469	469	slot->common_load_rom(slot->get_rom_base(), size, "rom");
470	470

trunk/src/mess/drivers/gamepock.c
r32760	r32761
12	12	ADDRESS_MAP_UNMAP_HIGH
13	13	AM_RANGE(0x0000,0x0fff) AM_ROM
14	14	AM_RANGE(0x1000,0x3fff) AM_NOP
15		//AM_RANGE(0x4000,0xbfff) AM_ROM // mapped by the cartslot
	15	//AM_RANGE(0x4000,0xbfff) AM_ROM // mapped by the cartslot
16	16	AM_RANGE(0xc000,0xc7ff) AM_MIRROR(0x0800) AM_RAM
17	17	AM_RANGE(0xff80,0xffff) AM_RAM /* 128 bytes microcontroller RAM */
18	18	ADDRESS_MAP_END

trunk/src/mess/drivers/apf.c
r32760	r32761
246	246	m_has_cart_ram = true;
247	247	break;
248	248	}
249
	249
250	250	m_cart->save_ram();
251	251	}
252	252	}
r32760	r32761
310	310	AM_RANGE(0x0000, 0x03ff) AM_MIRROR(0x1c00) AM_RAM AM_SHARE("videoram")
311	311	AM_RANGE(0x2000, 0x3fff) AM_MIRROR(0x1ffc) AM_DEVREADWRITE("pia0", pia6821_device, read, write)
312	312	AM_RANGE(0x4000, 0x4fff) AM_MIRROR(0x1000) AM_ROM AM_REGION("roms", 0)
313		AM_RANGE(0x6800, 0x7fff) AM_NOP // BASIC accesses ROM here too, but this is installed at machine_start
	313	AM_RANGE(0x6800, 0x7fff) AM_NOP // BASIC accesses ROM here too, but this is installed at machine_start
314	314	AM_RANGE(0x8000, 0x9fff) AM_DEVREAD("cartslot", apf_cart_slot_device, read_rom)
315	315	AM_RANGE(0xe000, 0xefff) AM_MIRROR(0x1000) AM_ROM AM_REGION("roms", 0)
316	316	ADDRESS_MAP_END

trunk/src/mess/drivers/apple3.c
r32760	r32761
33	33	SLOT_INTERFACE("cffa2", A2BUS_CFFA2_6502) /* CFFA2000 Compact Flash for Apple II (www.dreher.net), 6502 firmware */
34	34	SLOT_INTERFACE("applicard", A2BUS_APPLICARD) /* PCPI Applicard */
35	35	SLOT_INTERFACE("thclock", A2BUS_THUNDERCLOCK) /* ThunderWare ThunderClock Plus - driver assumes slot 2 by default */
36		SLOT_INTERFACE("mouse", A2BUS_MOUSE) /* Apple II Mouse Card */
	36	SLOT_INTERFACE("mouse", A2BUS_MOUSE) /* Apple II Mouse Card */
37	37	SLOT_INTERFACE_END
38	38
39	39	static SLOT_INTERFACE_START( a3_floppies )

trunk/src/mess/drivers/pt68k4.c
r32760	r32761
9	9	2014-01-03 Connect real DUARTs, FDC, and TimeKeeper. Settings now save properly, floppies can be read.
10	10	2014-01-19 ISA bus and compatible cards, PC keyboard support, speaker support
11	11	2014-09-20 Add PT68K2, add save states, we have a working SK*DOS disk!
12
	12
13	13	This has the appearance of a PC, including pc power supply, slots, etc
14	14	on a conventional pc-like motherboard and case.
15	15
16	16	Some pics: http://www.wormfood.net/old_computers/
17
18		Source code and manuals for the HUMBUG BIOS and SK*DOS are at:
19		http://www.users.cloud9.net/~stark/sources.html
20
21		Usage:
	17
	18	Source code and manuals for the HUMBUG BIOS and SK*DOS are at:
	19	http://www.users.cloud9.net/~stark/sources.html
	20
	21	Usage:
22	22	Start up and press Enter as prompted. Type he to see a command list, or fd to boot from the
23	23	first floppy drive.
24
	24
25	25	The stock NVRAM configures PT68k2 for 2 DSDD 5.25" drives, and PT68k4 for 2 DSHD 5.25" drives.
26
	26
27	27	Chips:
28	28	68230 Parallel Interface/Timer @ FE0081
29	29	68681 DUART/Timer (x2) @ FE0001 and FE0041
r32760	r32761
48	48	5: DUART1
49	49	6: PC FDC IRQ
50	50
51		TODO: 68230 device
52		This system and SK*DOS don't like our ISA WDXT-GEN emulation so HDD installs are not currently possible.
53
	51	TODO: 68230 device
	52	This system and SK*DOS don't like our ISA WDXT-GEN emulation so HDD installs are not currently possible.
	53
54	54	****************************************************************************/
55	55
56	56	#include "emu.h"
r32760	r32761
73	73	#define ISABUS_TAG "isa"
74	74	#define KBDC_TAG "pc_kbdc"
75	75	#define SPEAKER_TAG "speaker"
76		#define WDFDC_TAG "wdfdc"
	76	#define WDFDC_TAG "wdfdc"
77	77
78	78	class pt68k4_state : public driver_device
79	79	{
r32760	r32761
219	219	switch (drive)
220	220	{
221	221	case 0:
222		floppy->ss_w((data & 0x40) ? 1 : 0);
	222	floppy->ss_w((data & 0x40) ? 1 : 0);
223	223	break;
224	224
225	225	case 1:
226		floppy2->ss_w((data & 0x40) ? 1 : 0);
	226	floppy2->ss_w((data & 0x40) ? 1 : 0);
227	227	break;
228	228
229	229	default:
r32760	r32761
381	381
382	382	static MACHINE_CONFIG_START( pt68k2, pt68k4_state )
383	383	/* basic machine hardware */
384		MCFG_CPU_ADD(M68K_TAG, M68000, XTAL_16MHz/2) // 68k2 came in 8, 10, and 12 MHz versions
	384	MCFG_CPU_ADD(M68K_TAG, M68000, XTAL_16MHz/2) // 68k2 came in 8, 10, and 12 MHz versions
385	385	MCFG_CPU_PROGRAM_MAP(pt68k2_mem)
386	386
387	387	MCFG_MC68681_ADD("duart1", XTAL_3_6864MHz)
r32760	r32761
459	459	/* ROM definition */
460	460	ROM_START( pt68k2 )
461	461	ROM_REGION16_BE( 0x10000, "roms", 0 )
462		ROM_LOAD16_BYTE( "hum_u20.bin", 0x000000, 0x008000, CRC(69db483a) SHA1(9dfea73e4d7deef7c66a27cca92eb7c9ff767215) )
463		ROM_LOAD16_BYTE( "hum_u27.bin", 0x000001, 0x008000, CRC(54441b06) SHA1(0e2d63b1cd01f88f37fc4859c11c252c4fea220b) )
	462	ROM_LOAD16_BYTE( "hum_u20.bin", 0x000000, 0x008000, CRC(69db483a) SHA1(9dfea73e4d7deef7c66a27cca92eb7c9ff767215) )
	463	ROM_LOAD16_BYTE( "hum_u27.bin", 0x000001, 0x008000, CRC(54441b06) SHA1(0e2d63b1cd01f88f37fc4859c11c252c4fea220b) )
464	464
465	465	ROM_REGION(0x800, TIMEKEEPER_TAG, 0)
466	466	ROM_LOAD( "u21_ds1220.bin", 0x000000, 0x000800, CRC(7a6b75ce) SHA1(07663860aa6cc21aed04a568ff9c05bc75d62e4f) )

trunk/src/mess/drivers/pegasus.c
r32760	r32761
95	95	DECLARE_DRIVER_INIT(pegasus);
96	96	TIMER_DEVICE_CALLBACK_MEMBER(pegasus_firq);
97	97	void pegasus_decrypt_rom(UINT8 *ROM, bool force_decrypt);
98
	98
99	99	int load_cart(device_image_interface &image, generic_slot_device slot, const char reg_tag);
100	100	DECLARE_DEVICE_IMAGE_LOAD_MEMBER(exp00_load) { return load_cart(image, m_exp_00, "0000"); }
101	101	DECLARE_DEVICE_IMAGE_LOAD_MEMBER(exp01_load) { return load_cart(image, m_exp_01, "1000"); }
r32760	r32761
183	183
184	184	static ADDRESS_MAP_START(pegasus_mem, AS_PROGRAM, 8, pegasus_state)
185	185	ADDRESS_MAP_UNMAP_HIGH
186		//AM_RANGE(0x0000, 0x2fff) // mapped by the cartslots 1-3
	186	//AM_RANGE(0x0000, 0x2fff) // mapped by the cartslots 1-3
187	187	AM_RANGE(0xb000, 0xbdff) AM_RAM
188	188	AM_RANGE(0xbe00, 0xbfff) AM_RAM AM_SHARE("p_videoram")
189		//AM_RANGE(0xc000, 0xdfff) // mapped by the cartslots 4-5
	189	//AM_RANGE(0xc000, 0xdfff) // mapped by the cartslots 4-5
190	190	AM_RANGE(0xe000, 0xe1ff) AM_READ(pegasus_protection_r)
191	191	AM_RANGE(0xe200, 0xe3ff) AM_READWRITE(pegasus_pcg_r,pegasus_pcg_w)
192	192	AM_RANGE(0xe400, 0xe403) AM_MIRROR(0x1fc) AM_DEVREADWRITE("pia_u", pia6821_device, read, write)
r32760	r32761
413	413	{
414	414	UINT32 size = slot->common_get_size(reg_tag);
415	415	bool any_socket = false;
416
	416
417	417	if (size > 0x1000)
418	418	{
419	419	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
420	420	return IMAGE_INIT_FAIL;
421	421	}
422
	422
423	423	if (image.software_entry() != NULL && size == 0)
424	424	{
425	425	// we might be loading a cart compatible with all sockets!
r32760	r32761
436	436	}
437	437	}
438	438
439		slot->rom_alloc(0x1000, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE); // we alloc 0x1000 also for smaller roms!
	439	slot->rom_alloc(0x1000, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE); // we alloc 0x1000 also for smaller roms!
440	440	slot->common_load_rom(slot->get_rom_base(), size, any_socket ? "rom" : reg_tag);
441
	441
442	442	// raw images have to be decrypted (in particular the ones from softlist)
443	443	pegasus_decrypt_rom(slot->get_rom_base(), image.software_entry() != NULL);
444
	444
445	445	return IMAGE_INIT_PASS;
446	446	}
447	447

trunk/src/mess/drivers/pc6001.c
r32760	r32761
922	922	static ADDRESS_MAP_START(pc6001_map, AS_PROGRAM, 8, pc6001_state )
923	923	ADDRESS_MAP_UNMAP_HIGH
924	924	AM_RANGE(0x0000, 0x3fff) AM_ROM AM_WRITENOP
925		//AM_RANGE(0x4000, 0x5fff) // mapped by the cartslot
	925	//AM_RANGE(0x4000, 0x5fff) // mapped by the cartslot
926	926	AM_RANGE(0x6000, 0x7fff) AM_ROMBANK("bank1")
927	927	AM_RANGE(0x8000, 0xffff) AM_RAM AM_SHARE("ram")
928	928	ADDRESS_MAP_END
r32760	r32761
1639	1639	if(0)
1640	1640	{
1641	1641	//printf("%02x\n",data);
1642
	1642
1643	1643	if ((data & 0x0f) == 0x05 && m_cart_rom)
1644	1644	m_bank1->set_base(m_cart_rom->base() + 0x2000);
1645	1645	if ((data & 0x0f) == 0x04)
r32760	r32761
2074	2074	void pc6001_state::machine_reset()
2075	2075	{
2076	2076	m_video_ram = m_region_maincpu->base() + 0xc000;
2077
	2077
2078	2078	if (m_cart->exists())
2079	2079	m_maincpu->space(AS_PROGRAM).install_read_handler(0x4000, 0x5fff, read8_delegate(FUNC(generic_slot_device::read_rom),(generic_slot_device*)m_cart));
2080	2080
2081	2081	astring region_tag;
2082	2082	m_cart_rom = memregion(region_tag.cpy(m_cart->tag()).cat(GENERIC_ROM_REGION_TAG));
2083
	2083
2084	2084	m_port_c_8255=0;
2085	2085
2086	2086	m_cas_switch = 0;
r32760	r32761
2095	2095	MACHINE_RESET_MEMBER(pc6001_state,pc6001m2)
2096	2096	{
2097	2097	m_video_ram = m_region_maincpu->base() + 0xc000 + 0x28000;
2098
	2098
2099	2099	astring region_tag;
2100	2100	m_cart_rom = memregion(region_tag.cpy(m_cart->tag()).cat(GENERIC_ROM_REGION_TAG));
2101	2101	// hackish way to simplify bankswitch handling
2102	2102	if (m_cart_rom)
2103	2103	memcpy(m_region_maincpu->base() + 0x48000, m_cart_rom->base(), 0x4000);
2104
	2104
2105	2105	m_port_c_8255=0;
2106	2106
2107	2107	m_cas_switch = 0;
r32760	r32761
2134	2134	MACHINE_RESET_MEMBER(pc6001_state,pc6001sr)
2135	2135	{
2136	2136	m_video_ram = m_region_maincpu->base() + 0x70000;
2137
	2137
2138	2138	astring region_tag;
2139	2139	m_cart_rom = memregion(region_tag.cpy(m_cart->tag()).cat(GENERIC_ROM_REGION_TAG));
2140	2140	// should this be mirrored into the EXROM regions? hard to tell without an actual cart dump...
2141
	2141
2142	2142	m_port_c_8255=0;
2143	2143
2144	2144	m_cas_switch = 0;

trunk/src/mess/drivers/scv.c
r32760	r32761
64	64
65	65
66	66	static ADDRESS_MAP_START( scv_mem, AS_PROGRAM, 8, scv_state )
67		AM_RANGE( 0x0000, 0x0fff ) AM_ROM // BIOS
	67	AM_RANGE( 0x0000, 0x0fff ) AM_ROM // BIOS
68	68
69	69	AM_RANGE( 0x2000, 0x3403 ) AM_RAM AM_SHARE("videoram") // VRAM + 4 registers
70	70	AM_RANGE( 0x3600, 0x3600 ) AM_DEVWRITE("upd1771c", upd1771c_device, write)
71	71
72		AM_RANGE( 0x8000, 0xff7f ) AM_DEVREADWRITE("cartslot", scv_cart_slot_device, read_cart, write_cart) // cartridge
73		AM_RANGE( 0xff80, 0xffff ) AM_RAM // upd7801 internal RAM
	72	AM_RANGE( 0x8000, 0xff7f ) AM_DEVREADWRITE("cartslot", scv_cart_slot_device, read_cart, write_cart) // cartridge
	73	AM_RANGE( 0xff80, 0xffff ) AM_RAM // upd7801 internal RAM
74	74	ADDRESS_MAP_END
75	75
76	76

trunk/src/mess/drivers/socrates.c
r32760	r32761
319	319	{
320	320	astring region_tag;
321	321	m_cart_reg = memregion(region_tag.cpy(m_cart->tag()).cat(GENERIC_ROM_REGION_TAG));
322
	322
323	323	m_rom_bank = 0xF3; // actually set semi-randomly on real console but we need to initialize it somewhere...
324	324	socrates_set_rom_bank();
325	325	m_ram_bank = 0; // the actual console sets it semi randomly on power up, and the bios cleans it up.
r32760	r32761
898	898	{
899	899	astring region_tag;
900	900	m_cart_reg = memregion(region_tag.cpy(m_cart->tag()).cat(GENERIC_ROM_REGION_TAG));
901
	901
902	902	UINT8 *bios = m_bios_reg->base();
903	903	UINT8 *cart = m_cart_reg ? m_cart_reg->base() : m_bios_reg->base();
904	904	UINT8 *ram = m_vram_reg->base();

trunk/src/mess/drivers/gba.c
r32760	r32761
1896	1896
1897	1897	if (m_bios_protected != 0)
1898	1898	offset = (m_bios_last_address + 8) / 4;
1899
	1899
1900	1900	return rom[offset & 0x3fff];
1901	1901	}
1902	1902

trunk/src/mess/drivers/rx78.c
r32760	r32761
259	259	static ADDRESS_MAP_START(rx78_mem, AS_PROGRAM, 8, rx78_state)
260	260	ADDRESS_MAP_UNMAP_HIGH
261	261	AM_RANGE(0x0000, 0x1fff) AM_ROM
262		//AM_RANGE(0x2000, 0x5fff) // mapped by the cartslot
	262	//AM_RANGE(0x2000, 0x5fff) // mapped by the cartslot
263	263	AM_RANGE(0x6000, 0xafff) AM_RAM //ext RAM
264	264	AM_RANGE(0xb000, 0xebff) AM_RAM
265	265	AM_RANGE(0xec00, 0xffff) AM_READWRITE(rx78_vram_r, rx78_vram_w)
r32760	r32761
409	409
410	410	void rx78_state::machine_reset()
411	411	{
412		address_space &prg = m_maincpu->space(AS_PROGRAM);
	412	address_space &prg = m_maincpu->space(AS_PROGRAM);
413	413	if (m_cart->exists())
414	414	prg.install_read_handler(0x2000, 0x5fff, read8_delegate(FUNC(generic_slot_device::read_rom),(generic_slot_device*)m_cart));
415	415	}
r32760	r32761
417	417	DEVICE_IMAGE_LOAD_MEMBER( rx78_state, rx78_cart )
418	418	{
419	419	UINT32 size = m_cart->common_get_size("rom");
420
	420
421	421	if (size != 0x2000 && size != 0x4000)
422	422	{
423	423	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
424	424	return IMAGE_INIT_FAIL;
425	425	}
426
	426
427	427	m_cart->rom_alloc(size, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
428		m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
429
	428	m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
	429
430	430	return IMAGE_INIT_PASS;
431	431	}
432	432

trunk/src/mess/drivers/laser3k.c
r32760	r32761
1	1	/***************************************************************************
2
	2
3	3	laser3k.c
4	4	Driver for VTech Laser 3000 / Dick Smith Electronics "The Cat"
5
	5
6	6	This machine is somewhat similar to a 48K Apple II if you blur your eyes
7	7	a lot, but it generally fits in poorly with 100% compatible machines
8	8	(no chance of a compatible language card or auxmem) so it gets its own driver.
9
	9
10	10	An "emulation cartridge" is required to run Apple II software; it's unclear
11	11	what that consists of.
12
	12
13	13	Banking theory:
14	14	- 6502 has 4 banking windows, 0000-3FFF, 4000-7FFF, 8000-BFFF, C000-FFFF
15	15	- Physical address space is 0x00000-0x3FFFF. ROM and I/O at the top, RAM
16	16	up to 0x2FFFF (192k max).
17	17	- Each window has a bank number register at physical 3C07C/D/E/F
18
	18
19	19	Technical manual at:
20	20	http://mirrors.apple2.org.za/Apple%20II%20Documentation%20Project/Computers/LASER/LASER%203000/Manuals/The%20Cat%20Technical%20Reference%20Manual.pdf
21
	21
22	22	TODO:
23	23	- Finish keyboard
24	24	- RGB graphics mode
25	25	- FDC C800 page appears to be inside the FDC cartridge, need a dump :( (can hack to use IWM in the meantime)
26	26	- Centronics printer port (data at 3c090, read ack at 3c1c0, read busy at 3c1c2)
27	27	- cassette
28
	28
29	29	***************************************************************************/
30	30
31	31	#include "emu.h"
r32760	r32761
248	248	{
249	249	switch (offset)
250	250	{
251		case 0x08: // set border color to black
	251	case 0x08: // set border color to black
252	252	m_border_color = 0;
253	253	break;
254		case 0x09: // set border color to red
	254	case 0x09: // set border color to red
255	255	m_border_color = 1;
256	256	break;
257		case 0x0a: // set border color to green
	257	case 0x0a: // set border color to green
258	258	m_border_color = 12;
259	259	break;
260		case 0x0b: // set border color to yellow
	260	case 0x0b: // set border color to yellow
261	261	m_border_color = 13;
262	262	break;
263		case 0x0c: // set border color to blue
	263	case 0x0c: // set border color to blue
264	264	m_border_color = 6;
265	265	break;
266		case 0x0d: // set border color to magenta
	266	case 0x0d: // set border color to magenta
267	267	m_border_color = 3;
268	268	break;
269		case 0x0e: // set border color to cyan
	269	case 0x0e: // set border color to cyan
270	270	m_border_color = 14;
271	271	break;
272		case 0x0f: // set border color to white
	272	case 0x0f: // set border color to white
273	273	m_border_color = 15;
274	274	break;
275	275
276		case 0x18: // set bg color to black
	276	case 0x18: // set bg color to black
277	277	m_bg_color = 0;
278	278	break;
279		case 0x19: // set bg color to red
	279	case 0x19: // set bg color to red
280	280	m_bg_color = 1;
281	281	break;
282		case 0x1a: // set bg color to green
	282	case 0x1a: // set bg color to green
283	283	m_bg_color = 12;
284	284	break;
285		case 0x1b: // set bg color to yellow
	285	case 0x1b: // set bg color to yellow
286	286	m_bg_color = 13;
287	287	break;
288		case 0x1c: // set bg color to blue
	288	case 0x1c: // set bg color to blue
289	289	m_bg_color = 6;
290	290	break;
291		case 0x1d: // set bg color to magenta
	291	case 0x1d: // set bg color to magenta
292	292	m_bg_color = 3;
293	293	break;
294		case 0x1e: // set bg color to cyan
	294	case 0x1e: // set bg color to cyan
295	295	m_bg_color = 14;
296	296	break;
297		case 0x1f: // set bg color to white
	297	case 0x1f: // set bg color to white
298	298	m_bg_color = 15;
299	299	break;
300	300
301		case 0x28: // set fg color to normal
	301	case 0x28: // set fg color to normal
302	302	m_fg_color = 15;
303	303	break;
304		case 0x29: // set fg color to red
	304	case 0x29: // set fg color to red
305	305	m_fg_color = 1;
306	306	break;
307		case 0x2a: // set fg color to green
	307	case 0x2a: // set fg color to green
308	308	m_fg_color = 12;
309	309	break;
310		case 0x2b: // set fg color to yellow
	310	case 0x2b: // set fg color to yellow
311	311	m_fg_color = 13;
312	312	break;
313		case 0x2c: // set fg color to blue
	313	case 0x2c: // set fg color to blue
314	314	m_fg_color = 6;
315	315	break;
316		case 0x2d: // set fg color to magenta
	316	case 0x2d: // set fg color to magenta
317	317	m_fg_color = 3;
318	318	break;
319		case 0x2e: // set fg color to cyan
	319	case 0x2e: // set fg color to cyan
320	320	m_fg_color = 14;
321	321	break;
322		case 0x2f: // set fg color to white
	322	case 0x2f: // set fg color to white
323	323	m_fg_color = 15;
324	324	break;
325	325
r32760	r32761
328	328	m_speaker->level_w(m_speaker_state);
329	329	break;
330	330
331		case 0x4c: // low resolution (40 column)
	331	case 0x4c: // low resolution (40 column)
332	332	m_80col = false;
333	333	m_maincpu->set_unscaled_clock(1021800);
334	334	break;
335	335
336		case 0x4d: // RGB mode
	336	case 0x4d: // RGB mode
337	337	m_gfxmode = RGB;
338	338	break;
339	339
340		case 0x4e: // double hi-res
	340	case 0x4e: // double hi-res
341	341	m_80col = true;
342	342	m_gfxmode = DHIRES;
343	343	m_maincpu->set_unscaled_clock(1021800*2);
344	344	break;
345
346		case 0x4f: // high resolution (80 column). Yes, the CPU clock also doubles when the pixel clock does (!)
	345
	346	case 0x4f: // high resolution (80 column). Yes, the CPU clock also doubles when the pixel clock does (!)
347	347	m_80col = true;
348	348	m_maincpu->set_unscaled_clock(1021800*2);
349	349	break;
350	350
351		case 0x50: // graphics mode
	351	case 0x50: // graphics mode
352	352	m_gfxmode = HIRES;
353	353	break;
354	354
355		case 0x51: // text mode
	355	case 0x51: // text mode
356	356	m_gfxmode = TEXT;
357	357	break;
358	358
359		case 0x52: // no mix
	359	case 0x52: // no mix
360	360	m_mix = false;
361	361	break;
362	362
363		case 0x53: // mixed mode
	363	case 0x53: // mixed mode
364	364	m_mix = true;
365	365	break;
366	366
367		case 0x54: // set page 1
	367	case 0x54: // set page 1
368	368	m_disp_page = 0;
369	369	break;
370	370
371		case 0x55: // set page 2
	371	case 0x55: // set page 2
372	372	m_disp_page = 1;
373	373	break;
374	374
375		case 0x56: // disable emulation (?)
	375	case 0x56: // disable emulation (?)
376	376	break;
377	377
378	378	default:
r32760	r32761
385	385	{
386	386	switch (offset)
387	387	{
388		case 0x00: // keyboard latch
	388	case 0x00: // keyboard latch
389	389	return m_transchar \| m_strobe;
390	390
391		case 0x10: // keyboard strobe
	391	case 0x10: // keyboard strobe
392	392	{
393	393	UINT8 rv = m_transchar \| m_strobe;
394	394	m_strobe = 0;
r32760	r32761
397	397
398	398	case 0x7c:
399	399	return m_bank0val;
400
	400
401	401	case 0x7d:
402	402	return m_bank1val;
403
	403
404	404	case 0x7e:
405	405	return m_bank2val;
406
	406
407	407	case 0x7f:
408	408	return m_bank3val;
409
	409
410	410	default:
411	411	do_io(offset);
412	412	break;
r32760	r32761
419	419	{
420	420	switch (offset)
421	421	{
422		case 0x10: // clear keyboard latch
	422	case 0x10: // clear keyboard latch
423	423	m_strobe = 0;
424	424	break;
425	425
426		case 0x68: // SN76489 sound
	426	case 0x68: // SN76489 sound
427	427	m_sn->write(space, 0, data);
428	428	break;
429	429
430		case 0x78: // called "SYSTEM" in the boot ROM listing, but unsure what it does
	430	case 0x78: // called "SYSTEM" in the boot ROM listing, but unsure what it does
431	431	break;
432	432
433		case 0x7c: // bank 0
	433	case 0x7c: // bank 0
434	434	m_bank0val = data & 0xf;
435	435	m_bank0->set_bank(m_bank0val);
436	436	break;
r32760	r32761
440	440	m_bank1->set_bank(m_bank1val);
441	441	break;
442	442
443		case 0x7e: // bank 2
	443	case 0x7e: // bank 2
444	444	m_bank2val = data & 0xf;
445	445	m_bank2->set_bank(m_bank2val);
446	446	break;
447	447
448		case 0x7f: // bank 3
	448	case 0x7f: // bank 3
449	449	m_bank3val = data & 0xf;
450	450	m_bank3->set_bank(m_bank3val);
451	451	break;
r32760	r32761
460	460	{
461	461	switch (offset)
462	462	{
463		case 0xc2: // h-blank status
	463	case 0xc2: // h-blank status
464	464	return space.machine().first_screen()->hblank() ? 0x80 : 0x00;
465	465
466		case 0xc3: // v-blank status
	466	case 0xc3: // v-blank status
467	467	return space.machine().first_screen()->vblank() ? 0x80 : 0x00;
468	468
469		case 0xc5: // CPU 1/2 MHz status?
	469	case 0xc5: // CPU 1/2 MHz status?
470	470	return 0x00;
471
	471
472	472	default:
473	473	printf("io2_r @ unknown %x\n", offset);
474	474	break;
r32760	r32761
505	505
506	506	for (i = 0; i < xscale; i++)
507	507	{
508		bitmap.pix16(ypos + y, xpos + (x * xscale) + i) = color;
	508	bitmap.pix16(ypos + y, xpos + (x * xscale) + i) = color;
509	509	}
510	510	}
511	511	}
r32760	r32761
520	520
521	521	if (m_80col)
522	522	{
523		start_address = (m_disp_page == 0) ? 0x1000 : 0x1800;
	523	start_address = (m_disp_page == 0) ? 0x1000 : 0x1800;
524	524	}
525	525	else
526	526	{
527		start_address = (m_disp_page == 0) ? 0x400 : 0x800;
	527	start_address = (m_disp_page == 0) ? 0x400 : 0x800;
528	528	}
529	529
530	530	m_flash = ((machine().time() * 4).seconds & 1) ? 1 : 0;
r32760	r32761
541	541	/* calculate address */
542	542	address = start_address + ((((row/8) & 0x07) << 7) \| (((row/8) & 0x18) * 5 + col));
543	543
544		plot_text_character(bitmap, col * 7, row, 1, m_a2_videoram[address],
	544	plot_text_character(bitmap, col * 7, row, 1, m_a2_videoram[address],
545	545	memregion("gfx1")->base(), memregion("gfx1")->bytes());
546		plot_text_character(bitmap, (col + 40) * 7, row, 1, m_a2_videoram[address+0x400],
	546	plot_text_character(bitmap, (col + 40) * 7, row, 1, m_a2_videoram[address+0x400],
547	547	memregion("gfx1")->base(), memregion("gfx1")->bytes());
548	548	}
549	549	}
r32760	r32761
553	553	{
554	554	/* calculate address */
555	555	address = start_address + ((((row/8) & 0x07) << 7) \| (((row/8) & 0x18) * 5 + col));
556		plot_text_character(bitmap, col * 14, row, 2, m_a2_videoram[address],
	556	plot_text_character(bitmap, col * 14, row, 2, m_a2_videoram[address],
557	557	memregion("gfx1")->base(), memregion("gfx1")->bytes());
558	558	}
559	559	}
r32760	r32761
565	565	const UINT8 *vram;
566	566	int row, col, b;
567	567	int offset;
568		UINT8 vram_row[42] ;
	568	UINT8 vram_row[42] ;
569	569	UINT16 v;
570	570	UINT16 *p;
571	571	UINT32 w;
r32760	r32761
601	601	\| (((UINT32) vram_row[col+2] & 0x7f) << 14);
602	602
603	603	artifact_map_ptr = &m_hires_artifact_map[((vram_row[col+1] & 0x80) >> 7) * 16];
604		for (b = 0; b < 7; b++)
	604	for (b = 0; b < 7; b++)
605	605	{
606	606	v = artifact_map_ptr[((w >> (b + 7-1)) & 0x07) \| (((b ^ col) & 0x01) << 3)];
607	607	*(p++) = v;
r32760	r32761
629	629	if (endrow < beginrow)
630	630	return;
631	631
632		vram = m_ram->pointer() + (m_disp_page ? 0x8000 : 0x4000);
	632	vram = m_ram->pointer() + (m_disp_page ? 0x8000 : 0x4000);
633	633
634	634	vram_row[0] = 0;
635	635	vram_row[81] = 0;
r32760	r32761
641	641	offset = ((((row/8) & 0x07) << 7) \| (((row/8) & 0x18) * 5 + col)) \| ((row & 7) << 10);
642	642	if (col < 40)
643	643	{
644		vram_row[1+(col*2)+0] = vram[offset];
	644	vram_row[1+(col*2)+0] = vram[offset];
645	645	vram_row[1+(col*2)+1] = vram[offset+1];
646	646	}
647	647	else
648	648	{
649		vram_row[1+(col*2)+0] = vram[offset+0x2000];
	649	vram_row[1+(col*2)+0] = vram[offset+0x2000];
650	650	vram_row[1+(col*2)+1] = vram[offset+0x2001];
651	651	}
652	652	}
r32760	r32761
659	659	\| (((UINT32) vram_row[col+1] & 0x7f) << 7)
660	660	\| (((UINT32) vram_row[col+2] & 0x7f) << 14);
661	661
662		for (b = 0; b < 7; b++)
	662	for (b = 0; b < 7; b++)
663	663	{
664	664	v = m_dhires_artifact_map[((((w >> (b + 7-1)) & 0x0F) * 0x11) >> (((2-(col*7+b))) & 0x03)) & 0x0F];
665	665	*(p++) = v;
r32760	r32761
673	673	switch (m_gfxmode)
674	674	{
675	675	case TEXT:
676		text_update(screen, bitmap, cliprect, 0, 191);
	676	text_update(screen, bitmap, cliprect, 0, 191);
677	677	break;
678	678
679	679	case HIRES:
680	680	if (m_mix)
681	681	{
682		hgr_update(screen, bitmap, cliprect, 0, 159);
683		text_update(screen, bitmap, cliprect, 160, 191);
	682	hgr_update(screen, bitmap, cliprect, 0, 159);
	683	text_update(screen, bitmap, cliprect, 160, 191);
684	684	}
685	685	else
686	686	{
687		hgr_update(screen, bitmap, cliprect, 0, 191);
	687	hgr_update(screen, bitmap, cliprect, 0, 191);
688	688	}
689	689	break;
690	690
r32760	r32761
694	694	case DHIRES:
695	695	if (m_mix)
696	696	{
697		dhgr_update(screen, bitmap, cliprect, 0, 159);
698		text_update(screen, bitmap, cliprect, 160, 191);
	697	dhgr_update(screen, bitmap, cliprect, 0, 159);
	698	text_update(screen, bitmap, cliprect, 160, 191);
699	699	}
700	700	else
701	701	{
702		dhgr_update(screen, bitmap, cliprect, 0, 191);
	702	dhgr_update(screen, bitmap, cliprect, 0, 191);
703	703	}
704	704	break;
705	705	}
r32760	r32761
793	793	mod = (m_kbspecial->read() & 0x06) ? 0x01 : 0x00;
794	794	mod \|= (m_kbspecial->read() & 0x08) ? 0x02 : 0x00;
795	795
796		// printf("lastchar = %02x\n", m_lastchar & 0x3f);
	796	// printf("lastchar = %02x\n", m_lastchar & 0x3f);
797	797
798	798	m_transchar = key_remap[m_lastchar&0x3f][mod];
799	799
800	800	if (m_transchar != 0)
801	801	{
802	802	m_strobe = 0x80;
803		// printf("new char = %04x (%02x)\n", m_lastchar&0x3f, m_transchar);
	803	// printf("new char = %04x (%02x)\n", m_lastchar&0x3f, m_transchar);
804	804	}
805	805	}
806	806	}
r32760	r32761
865	865	PORT_BIT(0x008, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Esc") PORT_CODE(KEYCODE_ESC) PORT_CHAR(27)
866	866	PORT_BIT(0x010, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_A) PORT_CHAR('A') PORT_CHAR('a')
867	867	PORT_BIT(0x020, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
868		PORT_BIT(0x040, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR('\'') PORT_CHAR('\"')
	868	PORT_BIT(0x040, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR('\'') PORT_CHAR('\"')
869	869	PORT_BIT(0x080, IP_ACTIVE_HIGH, IPT_UNUSED)
870	870	PORT_BIT(0x100, IP_ACTIVE_HIGH, IPT_UNUSED)
871	871	PORT_BIT(0x200, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Return") PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13)

trunk/src/mess/drivers/intv.c
r32760	r32761
380	380	AM_RANGE(0x01f0, 0x01ff) AM_DEVREADWRITE8("ay8914", ay8914_device, read, write, 0x00ff)
381	381	AM_RANGE(0x0200, 0x035f) AM_READWRITE(intv_ram16_r, intv_ram16_w)
382	382	AM_RANGE(0x0400, 0x04ff) AM_DEVREAD("cartslot", intv_cart_slot_device, read_rom04)
383		AM_RANGE(0x1000, 0x1fff) AM_ROM AM_REGION("maincpu", 0x1000 << 1) // Exec ROM, 10-bits wide
	383	AM_RANGE(0x1000, 0x1fff) AM_ROM AM_REGION("maincpu", 0x1000 << 1) // Exec ROM, 10-bits wide
384	384	AM_RANGE(0x2000, 0x2fff) AM_DEVREAD("cartslot", intv_cart_slot_device, read_rom20)
385	385	AM_RANGE(0x3000, 0x37ff) AM_DEVREAD("stic", stic_device, grom_read) // GROM, 8-bits wide
386		AM_RANGE(0x3800, 0x39ff) AM_READWRITE(intv_gram_r, intv_gram_w) // GRAM, 8-bits wide
387		AM_RANGE(0x3a00, 0x3bff) AM_READWRITE(intv_gram_r, intv_gram_w) // GRAM Alias, 8-bits wide
	386	AM_RANGE(0x3800, 0x39ff) AM_READWRITE(intv_gram_r, intv_gram_w) // GRAM, 8-bits wide
	387	AM_RANGE(0x3a00, 0x3bff) AM_READWRITE(intv_gram_r, intv_gram_w) // GRAM Alias, 8-bits wide
388	388	AM_RANGE(0x4000, 0x47ff) AM_DEVREAD("cartslot", intv_cart_slot_device, read_rom40)
389	389	AM_RANGE(0x4800, 0x4fff) AM_DEVREAD("cartslot", intv_cart_slot_device, read_rom48)
390	390	AM_RANGE(0x5000, 0x5fff) AM_DEVREAD("cartslot", intv_cart_slot_device, read_rom50)
r32760	r32761
407	407	AM_RANGE(0x01f0, 0x01ff) AM_DEVREADWRITE8("ay8914", ay8914_device, read, write, 0x00ff)
408	408	AM_RANGE(0x0200, 0x035f) AM_READWRITE(intv_ram16_r, intv_ram16_w)
409	409	AM_RANGE(0x0400, 0x04ff) AM_DEVREAD("voice", intv_voice_device, read_rom04)
410		AM_RANGE(0x1000, 0x1fff) AM_ROM AM_REGION("maincpu", 0x1000 << 1) // Exec ROM, 10-bits wide
	410	AM_RANGE(0x1000, 0x1fff) AM_ROM AM_REGION("maincpu", 0x1000 << 1) // Exec ROM, 10-bits wide
411	411	AM_RANGE(0x2000, 0x2fff) AM_DEVREAD("voice", intv_voice_device, read_rom20)
412	412	AM_RANGE(0x3000, 0x37ff) AM_DEVREAD("stic", stic_device, grom_read) // GROM, 8-bits wide
413		AM_RANGE(0x3800, 0x39ff) AM_READWRITE(intv_gram_r, intv_gram_w) // GRAM, 8-bits wide
414		AM_RANGE(0x3a00, 0x3bff) AM_READWRITE(intv_gram_r, intv_gram_w) // GRAM Alias, 8-bits wide
	413	AM_RANGE(0x3800, 0x39ff) AM_READWRITE(intv_gram_r, intv_gram_w) // GRAM, 8-bits wide
	414	AM_RANGE(0x3a00, 0x3bff) AM_READWRITE(intv_gram_r, intv_gram_w) // GRAM Alias, 8-bits wide
415	415	AM_RANGE(0x4000, 0x47ff) AM_DEVREAD("voice", intv_voice_device, read_rom40)
416	416	AM_RANGE(0x4800, 0x4fff) AM_DEVREAD("voice", intv_voice_device, read_rom48)
417	417	AM_RANGE(0x5000, 0x5fff) AM_DEVREAD("voice", intv_voice_device, read_rom50)
r32760	r32761
432	432	AM_RANGE(0x0100, 0x01ef) AM_READWRITE(intv_ram8_r, intv_ram8_w)
433	433	AM_RANGE(0x01f0, 0x01ff) AM_DEVREADWRITE8("ay8914", ay8914_device, read, write, 0x00ff)
434	434	AM_RANGE(0x0200, 0x035f) AM_READWRITE(intv_ram16_r, intv_ram16_w)
435		AM_RANGE(0x0400, 0x04ff) AM_ROM AM_REGION("maincpu", 0x400 << 1) // Exec ROM, 10-bits wide
436		AM_RANGE(0x1000, 0x1fff) AM_ROM AM_REGION("maincpu", 0x1000 << 1) // Exec ROM, 10-bits wide
	435	AM_RANGE(0x0400, 0x04ff) AM_ROM AM_REGION("maincpu", 0x400 << 1) // Exec ROM, 10-bits wide
	436	AM_RANGE(0x1000, 0x1fff) AM_ROM AM_REGION("maincpu", 0x1000 << 1) // Exec ROM, 10-bits wide
437	437	AM_RANGE(0x2000, 0x2fff) AM_DEVREAD("cartslot", intv_cart_slot_device, read_rom20)
438		AM_RANGE(0x3000, 0x37ff) AM_DEVREAD("stic", stic_device, grom_read) // GROM, 8-bits wide
439		AM_RANGE(0x3800, 0x39ff) AM_READWRITE(intv_gram_r, intv_gram_w) // GRAM, 8-bits wide
440		AM_RANGE(0x3a00, 0x3bff) AM_READWRITE(intv_gram_r, intv_gram_w) // GRAM Alias, 8-bits wide
	438	AM_RANGE(0x3000, 0x37ff) AM_DEVREAD("stic", stic_device, grom_read) // GROM, 8-bits wide
	439	AM_RANGE(0x3800, 0x39ff) AM_READWRITE(intv_gram_r, intv_gram_w) // GRAM, 8-bits wide
	440	AM_RANGE(0x3a00, 0x3bff) AM_READWRITE(intv_gram_r, intv_gram_w) // GRAM Alias, 8-bits wide
441	441	AM_RANGE(0x4000, 0x47ff) AM_DEVREAD("cartslot", intv_cart_slot_device, read_rom40)
442	442	AM_RANGE(0x4800, 0x4fff) AM_DEVREAD("cartslot", intv_cart_slot_device, read_rom48)
443	443	AM_RANGE(0x5000, 0x5fff) AM_DEVREAD("cartslot", intv_cart_slot_device, read_rom50)

trunk/src/mess/drivers/vii.c
r32760	r32761
961	961	void vii_state::test_centered(UINT8 *ROM)
962	962	{
963	963	if (ROM[0x3cd808] == 0x99 &&
964		ROM[0x3cd809] == 0x99 &&
965		ROM[0x3cd80a] == 0x83 &&
966		ROM[0x3cd80b] == 0x5e &&
967		ROM[0x3cd80c] == 0x52 &&
968		ROM[0x3cd80d] == 0x6b &&
969		ROM[0x3cd80e] == 0x78 &&
970		ROM[0x3cd80f] == 0x7f)
	964	ROM[0x3cd809] == 0x99 &&
	965	ROM[0x3cd80a] == 0x83 &&
	966	ROM[0x3cd80b] == 0x5e &&
	967	ROM[0x3cd80c] == 0x52 &&
	968	ROM[0x3cd80d] == 0x6b &&
	969	ROM[0x3cd80e] == 0x78 &&
	970	ROM[0x3cd80f] == 0x7f)
971	971	{
972	972	m_centered_coordinates = 0;
973	973	}
r32760	r32761
982	982	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
983	983	return IMAGE_INIT_FAIL;
984	984	}
985
	985
986	986	m_cart->rom_alloc(size, GENERIC_ROM16_WIDTH, ENDIANNESS_LITTLE);
987		m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
988
	987	m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
	988
989	989	test_centered(m_cart->get_rom_base());
990	990
991	991	return IMAGE_INIT_PASS;
r32760	r32761
994	994	DEVICE_IMAGE_LOAD_MEMBER( vii_state, vsmile_cart )
995	995	{
996	996	UINT32 size = m_cart->common_get_size("rom");
997
	997
998	998	m_cart->rom_alloc(size, GENERIC_ROM16_WIDTH, ENDIANNESS_LITTLE);
999		m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
1000
	999	m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
	1000
1001	1001	return IMAGE_INIT_PASS;
1002	1002	}
1003	1003
r32760	r32761
1031	1031	m_cart_rom = memregion(region_tag.cpy(m_cart->tag()).cat(GENERIC_ROM_REGION_TAG));
1032	1032	memcpy(m_p_cart, m_cart_rom->base(), 0x400000 * 2);
1033	1033	}
1034		else if (m_spg243_mode == SPG243_VII) // Vii bios is banked
	1034	else if (m_spg243_mode == SPG243_VII) // Vii bios is banked
1035	1035	memcpy(m_p_cart, m_bios_rom->base(), 0x400000 * 2);
1036	1036	else
1037	1037	memcpy(m_p_cart, memregion("maincpu")->base(), 0x400000 * 2);
1038
	1038
1039	1039	m_video_regs[0x36] = 0xffff;
1040	1040	m_video_regs[0x37] = 0xffff;
1041	1041

trunk/src/mess/drivers/geniusiq.c
r32760	r32761
759	759	DEVICE_IMAGE_LOAD_MEMBER(geniusiq_state,iq128_cart)
760	760	{
761	761	UINT32 size = m_cart->common_get_size("rom");
762
	762
763	763	// we always a 0x100000 region, for easier mapping in the memory map
764	764	m_cart->rom_alloc(0x100000, GENERIC_ROM16_WIDTH, ENDIANNESS_LITTLE);
765		m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
	765	m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
766	766
767	767	m_cart_state = IQ128_ROM_CART;
768	768

trunk/src/mess/drivers/thomson.c
r32760	r32761
1093	1093
1094	1094	MCFG_DEVICE_REMOVE( "mc6846" )
1095	1095
1096		MCFG_PALETTE_MODIFY( "palette" )
	1096	MCFG_PALETTE_MODIFY( "palette" )
1097	1097	MCFG_PALETTE_INIT_OWNER(thomson_state, mo5)
1098	1098
1099	1099	MCFG_DEVICE_MODIFY(THOM_PIA_SYS)

trunk/src/mess/drivers/gameking.c
r32760	r32761
103	103	DEVICE_IMAGE_LOAD_MEMBER( gameking_state, gameking_cart )
104	104	{
105	105	UINT32 size = m_cart->common_get_size("rom");
106
	106
107	107	if (size > 0x20000)
108	108	{
109	109	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
110	110	return IMAGE_INIT_FAIL;
111	111	}
112
	112
113	113	m_cart->rom_alloc(size, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
114		m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
115
	114	m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
	115
116	116	return IMAGE_INIT_PASS;
117	117	}
118	118

trunk/src/mess/drivers/timex.c
r32760	r32761
598	598	int chunks_in_file = 0;
599	599	dynamic_buffer header;
600	600	header.resize(9);
601
	601
602	602	if (size % 0x2000 != 9)
603	603	{
604	604	image.seterror(IMAGE_ERROR_UNSPECIFIED, "File corrupted");
r32760	r32761
609	609	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Loading from softlist is not supported yet");
610	610	return IMAGE_INIT_FAIL;
611	611	}
612
	612
613	613	m_dock->rom_alloc(0x10000, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
614	614	DOCK = m_dock->get_rom_base();
615
	615
616	616	// check header
617	617	image.fread(header, 9);
618
	618
619	619	for (int i = 0; i < 8; i++)
620	620	if (header[i + 1] & 0x02) chunks_in_file++;
621
	621
622	622	if (chunks_in_file * 0x2000 + 0x09 != size)
623	623	{
624	624	image.seterror(IMAGE_ERROR_UNSPECIFIED, "File corrupted");
625	625	return IMAGE_INIT_FAIL;
626	626	}
627
	627
628	628	switch (header[0])
629	629	{
630	630	case 0x00: logerror ("DOCK cart\n");
r32760	r32761
643	643	}
644	644	}
645	645	break;
646
	646
647	647	default:
648	648	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Cart type not supported");
649	649	return IMAGE_INIT_FAIL;

trunk/src/mess/drivers/studio2.c
r32760	r32761
201	201	class studio2_state : public driver_device
202	202	{
203	203	public:
204
	204
205	205	studio2_state(const machine_config &mconfig, device_type type, const char *tag)
206	206	: driver_device(mconfig, type, tag),
207	207	m_maincpu(*this, CDP1802_TAG),
r32760	r32761
213	213	m_b(*this, "B"),
214	214	m_screen(*this, "screen")
215	215	{ }
216
	216
217	217	required_device<cosmac_device> m_maincpu;
218	218	required_device<beep_device> m_beeper;
219	219	optional_device<cdp1861_device> m_vdc;
r32760	r32761
222	222	required_ioport m_a;
223	223	required_ioport m_b;
224	224	required_device<screen_device> m_screen;
225
	225
226	226	virtual void machine_start();
227	227	virtual void machine_reset();
228
	228
229	229	DECLARE_READ8_MEMBER( cart_400 );
230	230	DECLARE_READ8_MEMBER( cart_a00 );
231	231	DECLARE_READ8_MEMBER( cart_e00 );
r32760	r32761
238	238	DECLARE_WRITE_LINE_MEMBER( q_w );
239	239	DECLARE_INPUT_CHANGED_MEMBER( reset_w );
240	240	DECLARE_DEVICE_IMAGE_LOAD_MEMBER( studio2_cart_load );
241
	241
242	242	/* keyboard state */
243	243	UINT8 m_keylatch;
244	244	DECLARE_DRIVER_INIT(studio2);
r32760	r32761
252	252	m_color0_ram(*this, "color0_ram"),
253	253	m_color1_ram(*this, "color1_ram")
254	254	{ }
255
	255
256	256	virtual UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
257
	257
258	258	required_shared_ptr<UINT8> m_color0_ram;
259	259	required_shared_ptr<UINT8> m_color1_ram;
260
	260
261	261	DECLARE_WRITE8_MEMBER( dma_w );
262	262	};
263	263
r32760	r32761
269	269	m_cti(*this, CDP1864_TAG),
270	270	m_color_ram(*this, "color_ram")
271	271	{ }
272
	272
273	273	required_device<cdp1864_device> m_cti;
274
	274
275	275	virtual void machine_start();
276	276	virtual void machine_reset();
277
	277
278	278	DECLARE_READ8_MEMBER( cart_c00 );
279	279	DECLARE_WRITE8_MEMBER( dma_w );
280	280	DECLARE_READ_LINE_MEMBER( rdata_r );
281	281	DECLARE_READ_LINE_MEMBER( bdata_r );
282	282	DECLARE_READ_LINE_MEMBER( gdata_r );
283
	283
284	284	/* video state */
285	285	required_shared_ptr<UINT8> m_color_ram;
286	286	UINT8 m_color;
r32760	r32761
511	511	m_maincpu->space(AS_PROGRAM).install_read_handler(0x0400, 0x07ff, read8_delegate(FUNC(studio2_state::cart_400), this));
512	512	m_maincpu->space(AS_PROGRAM).install_read_handler(0x0c00, 0x0fff, read8_delegate(FUNC(mpt02_state::cart_c00), this));
513	513	}
514
	514
515	515	// register for state saving
516	516	save_item(NAME(m_keylatch));
517	517	}
r32760	r32761
529	529	DEVICE_IMAGE_LOAD_MEMBER( studio2_state, studio2_cart_load )
530	530	{
531	531	UINT32 size;
532
	532
533	533	// always alloc 3K, even if range $400-$600 is not read by the system (RAM is present there)
534	534	m_cart->rom_alloc(0xc00, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
535
	535
536	536	if (image.software_entry() == NULL)
537	537	{
538	538	if (!strcmp(image.filetype(), "st2"))
r32760	r32761
540	540	UINT8 header[0x100];
541	541	UINT8 catalogue[10], title[32], pages[64];
542	542	UINT8 blocks;
543
544		if (image.length() <= 0x100)
	543
	544	if (image.length() <= 0x100)
545	545	{
546	546	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Invalid ROM file");
547	547	return IMAGE_INIT_FAIL;
r32760	r32761
560	560	memcpy(&catalogue, &header[16], 10);
561	561	memcpy(&title, &header[32], 32);
562	562	memcpy(&pages, &header[64], 64);
563
	563
564	564	/* read ST2 cartridge into memory */
565	565	for (int block = 0; block < (blocks - 1); block++)
566	566	{

trunk/src/mess/drivers/pokemini.c
r32760	r32761
56	56	m_speaker(*this, "speaker"),
57	57	m_i2cmem(*this, "i2cmem"),
58	58	m_cart(*this, "cartslot"),
59		m_inputs(*this, "INPUTS")
	59	m_inputs(*this, "INPUTS")
60	60	{ }
61	61
62	62	UINT8 m_pm_reg[0x100];
r32760	r32761
1506	1506	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Invalid ROM image: ROM image is too small");
1507	1507	return IMAGE_INIT_FAIL;
1508	1508	}
1509
	1509
1510	1510	/* Verify that the image is not too big */
1511	1511	if (size > 0x1fffff)
1512	1512	{
r32760	r32761
1515	1515	}
1516	1516
1517	1517	m_cart->rom_alloc(size, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
1518		m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
	1518	m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
1519	1519
1520	1520	return IMAGE_INIT_PASS;
1521	1521	}

trunk/src/mess/drivers/exelv.c
r32760	r32761
361	361
362	362
363	363	/*
364		CARTRIDGE ACCESS
	364	CARTRIDGE ACCESS
365	365	*/
366	366	READ8_MEMBER(exelv_state::rom_r)
367	367	{
r32760	r32761
466	466	/* Machine Initialization */
467	467
468	468	MACHINE_START_MEMBER( exelv_state, exl100)
469		{
	469	{
470	470	/* register for state saving */
471	471	save_item(NAME(m_tms7020_portb));
472	472	save_item(NAME(m_tms7041_portb));
r32760	r32761
481	481	UINT8 *rom = memregion("user1")->base() + 0x0200;
482	482	membank("bank1")->configure_entry(0, rom);
483	483	membank("bank1")->set_entry(0);
484
	484
485	485	/* register for state saving */
486	486	save_item(NAME(m_tms7020_portb));
487	487	save_item(NAME(m_tms7041_portb));

trunk/src/mess/drivers/ti74.c
r32760	r32761
5	5	Texas Instruments TI-74 BASICALC
6	6	Texas Instruments TI-95 PROCALC
7	7	hardware family: CC-40 -> TI-74 BASICALC -> TI-95 PROCALC
8
	8
9	9	TI-74 PCB layout:
10	10	note: TI-95 PCB is nearly the same, just with a different size LCD screen,
11	11	its CPU is labeled C70011, and the system ROM is labeled HN61256PC95.
12
	12
13	13	DOCK-BUS
14	14	--\|\|\|\|\|\|\|\|---
15	15	C == \|
r32760	r32761
49	49
50	50	* - indicates that it's on the other side of the PCB
51	51
52
	52
53	53	Overall, the hardware is very similar to TI CC-40. A lot has been shuffled around
54	54	to cut down on complexity (and probably for protection too). To reduce power usage
55	55	even more, the OS often idles while waiting for any keypress that triggers an interrupt
56	56	and wakes the processor up.
57
	57
58	58	The machine is powered by 4 AAA batteries. These will also save internal RAM,
59	59	provided that the machine is turned off properly.
60
61
	60
	61
62	62	TODO:
63	63	- it runs too fast due to missing clock divider emulation in TMS70C46
64	64	- external ram cartridge
r32760	r32761
131	131	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Invalid file size");
132	132	return IMAGE_INIT_FAIL;
133	133	}
134
	134
135	135	m_cart->rom_alloc(size, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
136		m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
137
	136	m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
	137
138	138	return IMAGE_INIT_PASS;
139	139	}
140	140
r32760	r32761
165	165	// TI-95 ref._________________...
166	166	// output# \| 40 43 41 44 42 12 11 10/13/14 0 1 2
167	167	// above \| _LOW _ERROR 2nd INV ALPHA LC INS DEGRAD HEX OCT I/O
168		// screen- \| _P{70} <{71} RUN{3}
	168	// screen- \| _P{70} <{71} RUN{3}
169	169	// area . SYS{4}
170	170	output_set_lamp_value(y * 10 + x, state);
171	171	}
r32760	r32761
175	175	// char size is 5x7 + cursor
176	176	if (x > 4 \|\| y > 7)
177	177	return;
178
	178
179	179	if (line == 1 && pos == 15)
180	180	{
181	181	// the last char is used to control the 14 lcd indicators
r32760	r32761
236	236	if (m_key_select >> i & 1)
237	237	ret \|= m_key_matrix[i]->read();
238	238	}
239
	239
240	240	return ret;
241	241	}
242	242
r32760	r32761
250	250	{
251	251	// d0-d1: system rom bankswitch
252	252	membank("sysbank")->set_entry(data & 3);
253
	253
254	254	// d2: power-on latch
255	255	if (~data & 4 && m_power)
256	256	{
257	257	m_power = 0;
258	258	m_maincpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE); // stop running
259	259	}
260
	260
261	261	// d3: N/C
262	262	}
263	263
r32760	r32761
265	265	ADDRESS_MAP_UNMAP_HIGH
266	266	AM_RANGE(0x1000, 0x1001) AM_DEVREADWRITE("hd44780", hd44780_device, read, write)
267	267	AM_RANGE(0x2000, 0x3fff) AM_RAM AM_SHARE("sysram.ic3")
268		//AM_RANGE(0x4000, 0xbfff) // mapped by the cartslot
	268	//AM_RANGE(0x4000, 0xbfff) // mapped by the cartslot
269	269	AM_RANGE(0xc000, 0xdfff) AM_ROMBANK("sysbank")
270	270	ADDRESS_MAP_END
271	271
r32760	r32761
486	486	void ti74_state::machine_reset()
487	487	{
488	488	m_power = 1;
489
	489
490	490	update_battery_status(m_battery_inp->read());
491	491	}
492	492

trunk/src/mess/drivers/cc40.c
r32760	r32761
51	51	provided that the machine is turned off properly. If a program is running,
52	52	you may have to press [BREAK] before turning the CC-40 off. If RAM contents
53	53	ends up dodgy somehow, just delete the nvram files.
54
	54
55	55	Officially, minimum total RAM size is 6KB. The system will still boot with less,
56	56	but don't expect all software to work properly.
57	57
r32760	r32761
114	114	UINT8 m_clock_control;
115	115	UINT8 m_clock_divider;
116	116	UINT8 m_key_select;
117
	117
118	118	UINT8 *m_sysram[2];
119	119	UINT16 m_sysram_size[2];
120	120	UINT16 m_sysram_end[2];
r32760	r32761
165	165	return IMAGE_INIT_FAIL;
166	166	}
167	167
168		m_cart->rom_alloc(0x20000, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE); // allocate a larger ROM region to have 4x32K banks
169		m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
	168	m_cart->rom_alloc(0x20000, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE); // allocate a larger ROM region to have 4x32K banks
	169	m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
170	170
171	171	return IMAGE_INIT_PASS;
172	172	}
r32760	r32761
265	265	m_sysram_mask[0] = d3 - 1;
266	266	m_sysram_end[1] = d3 + d2;
267	267	m_sysram_mask[1] = d2 - 1;
268
	268
269	269	// d4,d5: cartridge memory addressing
270	270	// 00: 2K @ $5000-$57ff & $5800-$5fff
271	271	// 01: 8K @ $5000-$6fff & $7000-$8fff
r32760	r32761
524	524	// init to largest possible
525	525	m_sysram[chip] = auto_alloc_array(machine(), UINT8, 0x2000);
526	526	save_pointer(NAME(m_sysram[chip]), 0x2000, chip);
527
	527
528	528	save_item(NAME(m_sysram_size[chip]), chip);
529	529	save_item(NAME(m_sysram_end[chip]), chip);
530	530	save_item(NAME(m_sysram_mask[chip]), chip);
531	531	}
532
	532
533	533	m_nvram[chip]->set_base(m_sysram[chip], size);
534	534	m_sysram_size[chip] = size;
535	535	}

trunk/src/mess/drivers/pc2000.c
r32760	r32761
759	759	UINT8 *cart = memregion(region_tag.cpy(m_cart->tag()).cat(GENERIC_ROM_REGION_TAG))->base();
760	760	if (!cart)
761	761	cart = memregion("bios")->base();
762
	762
763	763	m_bank0->configure_entries(0, 0x20, bios, 0x4000);
764	764	m_bank1->configure_entries(0, 0x20, bios, 0x4000);
765	765	m_bank2->configure_entries(0, 0x20, bios, 0x4000);
r32760	r32761
814	814	// we always allocate a 0x40000 region, even if most carts span only 0x20000,
815	815	// because the bankswitch code accesses up to 16 x 16K banks...
816	816	m_cart->rom_alloc(0x40000, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
817		m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
818
	817	m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
	818
819	819	return IMAGE_INIT_PASS;
820	820	}
821	821

trunk/src/mess/drivers/fm7.c
r32760	r32761
1001	1001	, m_avbank8, m_avbank9, m_avbank10, m_avbank11, m_avbank12, m_avbank13, m_avbank14, m_avbank15, m_avbank16 };
1002	1002
1003	1003	avbank[bank]->set_bank(physical);
1004		/* UINT8* RAM = memregion("maincpu")->base();
1005		UINT16 size = 0xfff;
1006		char bank_name[10];
	1004	/* UINT8* RAM = memregion("maincpu")->base();
	1005	UINT16 size = 0xfff;
	1006	char bank_name[10];
1007	1007
1008		if(bank == 15)
1009		size = 0xbff;
	1008	if(bank == 15)
	1009	size = 0xbff;
1010	1010
1011		sprintf(bank_name,"bank%d",bank+1);
	1011	sprintf(bank_name,"bank%d",bank+1);
1012	1012
1013		if(physical >= 0x10 && physical <= 0x1b)
1014		{
1015		switch(physical)
1016		{
1017		case 0x10:
1018		space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram0_r),this),write8_delegate(FUNC(fm7_state::fm7_vram0_w),this));
1019		break;
1020		case 0x11:
1021		space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram1_r),this),write8_delegate(FUNC(fm7_state::fm7_vram1_w),this));
1022		break;
1023		case 0x12:
1024		space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram2_r),this),write8_delegate(FUNC(fm7_state::fm7_vram2_w),this));
1025		break;
1026		case 0x13:
1027		space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram3_r),this),write8_delegate(FUNC(fm7_state::fm7_vram3_w),this));
1028		break;
1029		case 0x14:
1030		space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram4_r),this),write8_delegate(FUNC(fm7_state::fm7_vram4_w),this));
1031		break;
1032		case 0x15:
1033		space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram5_r),this),write8_delegate(FUNC(fm7_state::fm7_vram5_w),this));
1034		break;
1035		case 0x16:
1036		space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram6_r),this),write8_delegate(FUNC(fm7_state::fm7_vram6_w),this));
1037		break;
1038		case 0x17:
1039		space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram7_r),this),write8_delegate(FUNC(fm7_state::fm7_vram7_w),this));
1040		break;
1041		case 0x18:
1042		space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram8_r),this),write8_delegate(FUNC(fm7_state::fm7_vram8_w),this));
1043		break;
1044		case 0x19:
1045		space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram9_r),this),write8_delegate(FUNC(fm7_state::fm7_vram9_w),this));
1046		break;
1047		case 0x1a:
1048		space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vramA_r),this),write8_delegate(FUNC(fm7_state::fm7_vramA_w),this));
1049		break;
1050		case 0x1b:
1051		space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vramB_r),this),write8_delegate(FUNC(fm7_state::fm7_vramB_w),this));
1052		break;
1053		}
	1013	if(physical >= 0x10 && physical <= 0x1b)
	1014	{
	1015	switch(physical)
	1016	{
	1017	case 0x10:
	1018	space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram0_r),this),write8_delegate(FUNC(fm7_state::fm7_vram0_w),this));
	1019	break;
	1020	case 0x11:
	1021	space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram1_r),this),write8_delegate(FUNC(fm7_state::fm7_vram1_w),this));
	1022	break;
	1023	case 0x12:
	1024	space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram2_r),this),write8_delegate(FUNC(fm7_state::fm7_vram2_w),this));
	1025	break;
	1026	case 0x13:
	1027	space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram3_r),this),write8_delegate(FUNC(fm7_state::fm7_vram3_w),this));
	1028	break;
	1029	case 0x14:
	1030	space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram4_r),this),write8_delegate(FUNC(fm7_state::fm7_vram4_w),this));
	1031	break;
	1032	case 0x15:
	1033	space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram5_r),this),write8_delegate(FUNC(fm7_state::fm7_vram5_w),this));
	1034	break;
	1035	case 0x16:
	1036	space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram6_r),this),write8_delegate(FUNC(fm7_state::fm7_vram6_w),this));
	1037	break;
	1038	case 0x17:
	1039	space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram7_r),this),write8_delegate(FUNC(fm7_state::fm7_vram7_w),this));
	1040	break;
	1041	case 0x18:
	1042	space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram8_r),this),write8_delegate(FUNC(fm7_state::fm7_vram8_w),this));
	1043	break;
	1044	case 0x19:
	1045	space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vram9_r),this),write8_delegate(FUNC(fm7_state::fm7_vram9_w),this));
	1046	break;
	1047	case 0x1a:
	1048	space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vramA_r),this),write8_delegate(FUNC(fm7_state::fm7_vramA_w),this));
	1049	break;
	1050	case 0x1b:
	1051	space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_vramB_r),this),write8_delegate(FUNC(fm7_state::fm7_vramB_w),this));
	1052	break;
	1053	}
1054	1054	// membank(bank+1)->set_base(RAM+(physical<<12)-0x10000);
1055		return;
1056		}
1057		if(physical == 0x1c)
1058		{
1059		space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_console_ram_banked_r),this),write8_delegate(FUNC(fm7_state::fm7_console_ram_banked_w),this));
1060		return;
1061		}
1062		if(physical == 0x1d)
1063		{
1064		space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_sub_ram_ports_banked_r),this),write8_delegate(FUNC(fm7_state::fm7_sub_ram_ports_banked_w),this));
1065		return;
1066		}
1067		if(physical == 0x35)
1068		{
1069		if(m_init_rom_en && (m_type == SYS_FM11 \|\| m_type == SYS_FM16))
1070		{
1071		RAM = memregion("init")->base();
1072		space.install_read_bank(bank0x1000,(bank0x1000)+size,bank_name);
1073		space.nop_write(bank0x1000,(bank0x1000)+size);
1074		membank(bank_name)->set_base(RAM+(physical<<12)-0x35000);
1075		return;
1076		}
1077		}
1078		if(physical == 0x36 \|\| physical == 0x37)
1079		{
1080		if(m_init_rom_en && (m_type != SYS_FM11 && m_type != SYS_FM16))
1081		{
1082		RAM = memregion("init")->base();
1083		space.install_read_bank(bank0x1000,(bank0x1000)+size,bank_name);
1084		space.nop_write(bank0x1000,(bank0x1000)+size);
1085		membank(bank_name)->set_base(RAM+(physical<<12)-0x36000);
1086		return;
1087		}
1088		}
1089		if(physical > 0x37 && physical <= 0x3f)
1090		{
1091		if(m_basic_rom_en && (m_type != SYS_FM11 && m_type != SYS_FM16))
1092		{
1093		RAM = memregion("fbasic")->base();
1094		space.install_read_bank(bank0x1000,(bank0x1000)+size,bank_name);
1095		space.nop_write(bank0x1000,(bank0x1000)+size);
1096		membank(bank_name)->set_base(RAM+(physical<<12)-0x38000);
1097		return;
1098		}
1099		}
1100		space.install_readwrite_bank(bank0x1000,(bank0x1000)+size,bank_name);
1101		membank(bank_name)->set_base(RAM+(physical<<12));
1102		*/
	1055	return;
	1056	}
	1057	if(physical == 0x1c)
	1058	{
	1059	space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_console_ram_banked_r),this),write8_delegate(FUNC(fm7_state::fm7_console_ram_banked_w),this));
	1060	return;
	1061	}
	1062	if(physical == 0x1d)
	1063	{
	1064	space.install_readwrite_handler(bank0x1000,(bank0x1000)+size,read8_delegate(FUNC(fm7_state::fm7_sub_ram_ports_banked_r),this),write8_delegate(FUNC(fm7_state::fm7_sub_ram_ports_banked_w),this));
	1065	return;
	1066	}
	1067	if(physical == 0x35)
	1068	{
	1069	if(m_init_rom_en && (m_type == SYS_FM11 \|\| m_type == SYS_FM16))
	1070	{
	1071	RAM = memregion("init")->base();
	1072	space.install_read_bank(bank0x1000,(bank0x1000)+size,bank_name);
	1073	space.nop_write(bank0x1000,(bank0x1000)+size);
	1074	membank(bank_name)->set_base(RAM+(physical<<12)-0x35000);
	1075	return;
	1076	}
	1077	}
	1078	if(physical == 0x36 \|\| physical == 0x37)
	1079	{
	1080	if(m_init_rom_en && (m_type != SYS_FM11 && m_type != SYS_FM16))
	1081	{
	1082	RAM = memregion("init")->base();
	1083	space.install_read_bank(bank0x1000,(bank0x1000)+size,bank_name);
	1084	space.nop_write(bank0x1000,(bank0x1000)+size);
	1085	membank(bank_name)->set_base(RAM+(physical<<12)-0x36000);
	1086	return;
	1087	}
	1088	}
	1089	if(physical > 0x37 && physical <= 0x3f)
	1090	{
	1091	if(m_basic_rom_en && (m_type != SYS_FM11 && m_type != SYS_FM16))
	1092	{
	1093	RAM = memregion("fbasic")->base();
	1094	space.install_read_bank(bank0x1000,(bank0x1000)+size,bank_name);
	1095	space.nop_write(bank0x1000,(bank0x1000)+size);
	1096	membank(bank_name)->set_base(RAM+(physical<<12)-0x38000);
	1097	return;
	1098	}
	1099	}
	1100	space.install_readwrite_bank(bank0x1000,(bank0x1000)+size,bank_name);
	1101	membank(bank_name)->set_base(RAM+(physical<<12));
	1102	*/
1103	1103	}
1104	1104
1105	1105	void fm7_state::fm7_mmr_refresh(address_space& space)

trunk/src/mess/mess.mak
r32760	r32761
963	963	$(MESS_DRIVERS)/superslave.o\
964	964
965	965	$(MESSOBJ)/alesis.a: \
966		$(MESS_DRIVERS)/alesis.o $(MESS_AUDIO)/alesis.o $(MESS_VIDEO)/alesis.o \
	966	$(MESS_DRIVERS)/alesis.o $(MESS_AUDIO)/alesis.o $(MESS_VIDEO)/alesis.o \
967	967
968	968	$(MESSOBJ)/altos.a: \
969	969	$(MESS_DRIVERS)/altos5.o \
r32760	r32761
989	989	$(MESSOBJ)/apple.a: \
990	990	$(MESS_DRIVERS)/apple1.o $(MESS_MACHINE)/apple1.o $(MESS_VIDEO)/apple1.o \
991	991	$(MESS_DRIVERS)/apple2.o $(MESS_MACHINE)/apple2.o $(MESS_VIDEO)/apple2.o \
992		$(MESS_DRIVERS)/apple2gs.o $(MESS_MACHINE)/apple2gs.o $(MESS_VIDEO)/apple2gs.o \
	992	$(MESS_DRIVERS)/apple2gs.o $(MESS_MACHINE)/apple2gs.o $(MESS_VIDEO)/apple2gs.o \
993	993	$(MESS_DRIVERS)/apple3.o $(MESS_MACHINE)/apple3.o $(MESS_VIDEO)/apple3.o \
994	994	$(MESS_DRIVERS)/lisa.o $(MESS_MACHINE)/lisa.o \
995	995	$(MESS_DRIVERS)/mac.o $(MESS_AUDIO)/mac.o $(MESS_MACHINE)/egret.o $(MESS_MACHINE)/mac.o $(MESS_MACHINE)/macadb.o $(MESS_MACHINE)/macrtc.o $(MESS_MACHINE)/mackbd.o $(MESS_MACHINE)/swim.o $(MESS_VIDEO)/mac.o \
r32760	r32761
1029	1029	$(MESS_DRIVERS)/wswan.o $(MESS_AUDIO)/wswan_snd.o $(MESS_MACHINE)/wswan.o $(MESS_VIDEO)/wswan.o \
1030	1030
1031	1031	$(MESSOBJ)/be.a: \
1032		$(MESS_DRIVERS)/bebox.o $(MESS_MACHINE)/bebox.o \
	1032	$(MESS_DRIVERS)/bebox.o $(MESS_MACHINE)/bebox.o \
1033	1033
1034	1034	$(MESSOBJ)/bnpo.a: \
1035	1035	$(MESS_DRIVERS)/b2m.o $(MESS_MACHINE)/b2m.o $(MESS_VIDEO)/b2m.o \
r32760	r32761
1359	1359	$(MESS_DRIVERS)/irisha.o \
1360	1360
1361	1361	$(MESSOBJ)/microkey.a: \
1362		$(MESS_DRIVERS)/primo.o $(MESS_MACHINE)/primo.o $(MESS_VIDEO)/primo.o \
	1362	$(MESS_DRIVERS)/primo.o $(MESS_MACHINE)/primo.o $(MESS_VIDEO)/primo.o \
1363	1363
1364	1364	$(MESSOBJ)/mit.a: \
1365	1365	$(MESS_DRIVERS)/tx0.o $(MESS_VIDEO)/crt.o $(MESS_VIDEO)/tx0.o \
r32760	r32761
1469	1469	$(MESSOBJ)/pc.a: \
1470	1470	$(MESS_DRIVERS)/asst128.o \
1471	1471	$(MESS_DRIVERS)/europc.o \
1472		$(MESS_DRIVERS)/genpc.o $(MESS_MACHINE)/genpc.o \
	1472	$(MESS_DRIVERS)/genpc.o $(MESS_MACHINE)/genpc.o \
1473	1473	$(MESS_DRIVERS)/ibmpc.o \
1474	1474	$(MESS_DRIVERS)/ibmpcjr.o \
1475	1475	$(MESS_DRIVERS)/pc.o \
r32760	r32761
1480	1480
1481	1481	$(MESSOBJ)/pel.a: \
1482	1482	$(MESS_DRIVERS)/galeb.o $(MESS_VIDEO)/galeb.o \
1483		$(MESS_DRIVERS)/orao.o $(MESS_MACHINE)/orao.o $(MESS_VIDEO)/orao.o \
	1483	$(MESS_DRIVERS)/orao.o $(MESS_MACHINE)/orao.o $(MESS_VIDEO)/orao.o \
1484	1484
1485	1485	$(MESSOBJ)/philips.a: \
1486	1486	$(MESS_DRIVERS)/p2000t.o $(MESS_MACHINE)/p2000t.o $(MESS_VIDEO)/p2000m.o \
r32760	r32761
1686	1686	$(MESS_DRIVERS)/tec1.o \
1687	1687
1688	1688	$(MESSOBJ)/tesla.a: \
1689		$(MESS_DRIVERS)/ondra.o $(MESS_MACHINE)/ondra.o $(MESS_VIDEO)/ondra.o \
	1689	$(MESS_DRIVERS)/ondra.o $(MESS_MACHINE)/ondra.o $(MESS_VIDEO)/ondra.o \
1690	1690	$(MESS_DRIVERS)/pmd85.o $(MESS_MACHINE)/pmd85.o $(MESS_VIDEO)/pmd85.o \
1691	1691	$(MESS_DRIVERS)/pmi80.o \
1692	1692	$(MESS_DRIVERS)/sapi1.o \
r32760	r32761
1699	1699	$(MESS_DRIVERS)/thomson.o $(MESS_MACHINE)/thomson.o $(MESS_MACHINE)/thomflop.o $(MESS_VIDEO)/thomson.o \
1700	1700
1701	1701	$(MESSOBJ)/ti.a: \
1702		$(MESS_DRIVERS)/avigo.o $(MESS_VIDEO)/avigo.o \
	1702	$(MESS_DRIVERS)/avigo.o $(MESS_VIDEO)/avigo.o \
1703	1703	$(MESS_DRIVERS)/cc40.o \
1704	1704	$(MESS_DRIVERS)/evmbug.o \
1705	1705	$(MESS_DRIVERS)/exelv.o \

trunk/src/mess/tools/imgtool/modules/amiga.c
r32760	r32761
1776	1776	t_v = amiga_crack_time(&root.v);
1777	1777	t_r = amiga_crack_time(&root.r);
1778	1778
1779		strftime(c, sizeof(c), "%d-%b-%y %H:%M:%S", localtime(&t_c));
1780		strftime(v, sizeof(v), "%d-%b-%y %H:%M:%S", localtime(&t_v));
1781		strftime(r, sizeof(r), "%d-%b-%y %H:%M:%S", localtime(&t_r));
	1779	strftime(c, sizeof(c), "%d-%b-%y %H:%M:%S", localtime(&t_c));
	1780	strftime(v, sizeof(v), "%d-%b-%y %H:%M:%S", localtime(&t_v));
	1781	strftime(r, sizeof(r), "%d-%b-%y %H:%M:%S", localtime(&t_r));
1782	1782
1783	1783	strcpy(info, "Volume name: ");
1784	1784	strncat(info, (char *)root.diskname, root.name_len);

trunk/src/mess/audio/wswan_snd.h
r32760	r32761
25	25	vol_right(0),
26	26	on(0),
27	27	signal(0) { }
28
	28
29	29	UINT16 freq; /* frequency */
30	30	UINT32 period; /* period */
31	31	UINT32 pos; /* position */
r32760	r32761
44	44	public:
45	45	wswan_sound_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
46	46	~wswan_sound_device() { }
47
	47
48	48	protected:
49	49	// device-level overrides
50	50	virtual void device_start();
51	51	virtual void device_reset();
52
	52
53	53	// sound stream update overrides
54	54	virtual void sound_stream_update(sound_stream &stream, stream_sample_t inputs, stream_sample_t outputs, int samples);
55
	55
56	56	public:
57	57	DECLARE_WRITE8_MEMBER( port_w );
58
	58
59	59	private:
60	60	void wswan_ch_set_freq( CHAN *ch, UINT16 freq );
61
	61
62	62	private:
63	63	sound_stream *m_channel;
64	64	CHAN m_audio1; /* Audio channel 1 */

trunk/src/mess/audio/vc4000snd.h
r32760	r32761
21	21	public:
22	22	vc4000_sound_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
23	23	~vc4000_sound_device() { }
24
	24
25	25	protected:
26	26	// device-level overrides
27	27	virtual void device_start();
28
	28
29	29	// sound stream update overrides
30	30	virtual void sound_stream_update(sound_stream &stream, stream_sample_t inputs, stream_sample_t outputs, int samples);
31
	31
32	32	public:
33	33	void soundport_w(int mode, int data);
34
	34
35	35	private:
36	36	sound_stream *m_channel;
37	37	UINT8 m_reg[1];

trunk/src/mess/machine/lynx.c
r32760	r32761
1019	1019	case RCART:
1020	1020	if (m_cart->exists())
1021	1021	value = m_cart->read_rom(space, (m_suzy.high * m_granularity) + m_suzy.low);
1022		else
	1022	else
1023	1023	value = 0;
1024	1024	m_suzy.low = (m_suzy.low + 1) & (m_granularity - 1);
1025	1025	break;
r32760	r32761
2078	2078	// 22 chars manufacturer
2079	2079	UINT8 header[0x40];
2080	2080	image.fread(header, 0x40);
2081
	2081
2082	2082	// Check the image
2083	2083	if (lynx_verify_cart((char*)header, LYNX_CART) == IMAGE_VERIFY_FAIL)
2084	2084	return IMAGE_INIT_FAIL;
2085
	2085
2086	2086	/* 2008-10 FP: According to Handy source these should be page_size_bank0. Are we using
2087	2087	it correctly in MESS? Moreover, the next two values should be page_size_bank1. We should
2088	2088	implement this as well */
2089	2089	gran = header[4] \| (header[5] << 8);
2090
	2090
2091	2091	logerror ("%s %dkb cartridge with %dbyte granularity from %s\n", header + 10, size / 1024, gran, header + 42);
2092	2092	size -= 0x40;
2093	2093	}
2094		}
	2094	}
2095	2095
2096	2096	m_cart->rom_alloc(size, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
2097		m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
	2097	m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
2098	2098
2099	2099	// set-up granularity
2100	2100	if (image.software_entry() == NULL)
2101	2101	{
2102	2102	const char *filetype = image.filetype();
2103		if (!core_stricmp(filetype, "lnx")) // from header
	2103	if (!core_stricmp(filetype, "lnx")) // from header
2104	2104	m_granularity = gran;
2105	2105	else if (!core_stricmp(filetype, "lyx"))
2106	2106	{
r32760	r32761
2122	2122	else
2123	2123	m_granularity = 0x400; // Homebrew roms not using all 256 banks (T-Tris) (none currently in softlist)
2124	2124	}
2125
	2125
2126	2126	// set-up rotation from softlist
2127	2127	if (image.software_entry() != NULL)
2128	2128	{
r32760	r32761
2140	2140
2141	2141	return IMAGE_INIT_PASS;
2142	2142	}
2143

trunk/src/mess/machine/gamepock.c
r32760	r32761
139	139
140	140	if (m_cart->exists())
141	141	m_maincpu->space(AS_PROGRAM).install_read_handler(0x4000,0xbfff, read8_delegate(FUNC(generic_slot_device::read_rom),(generic_slot_device*)m_cart));
142
	142
143	143	}
144	144
145	145	UINT32 gamepock_state::screen_update_gamepock(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)

trunk/src/mess/machine/concept.c
r32760	r32761
154	154
155	155	WRITE_LINE_MEMBER(concept_state::via_out_cb2)
156	156	{
157		// LOG(("via_out_cb2: Sound control written: data=0x%2.2x\n", state));
	157	// LOG(("via_out_cb2: Sound control written: data=0x%2.2x\n", state));
158	158	m_speaker->level_w(state);
159	159	}
160	160
r32760	r32761
210	210
211	211	if (card)
212	212	{
213		return card->read_cnxx(space, offset & 0xff);
	213	return card->read_cnxx(space, offset & 0xff);
214	214	}
215	215	}
216	216	break;
r32760	r32761
245	245
246	246	case 3:
247	247	/* NVIA versatile system interface */
248		// LOG(("concept_io_r: VIA read at address 0x03%4.4x\n", offset << 1));
	248	// LOG(("concept_io_r: VIA read at address 0x03%4.4x\n", offset << 1));
249	249	{
250	250	via6522_device *via_0 = machine().device<via6522_device>("via6522_0");
251	251	return via_0->read(space, offset & 0xf);
r32760	r32761
301	301
302	302	if (card)
303	303	{
304		return card->write_c0nx(space, offset & 0x0f, data);
	304	return card->write_c0nx(space, offset & 0x0f, data);
305	305	}
306	306	}
307	307	break;

trunk/src/mess/machine/intv.c
r32760	r32761
351	351	save_item(NAME(m_ram16));
352	352	save_item(NAME(m_sr1_int_pending));
353	353	save_item(NAME(m_ram8));
354
	354
355	355	// intvkbd
356	356	if (m_is_keybd)
357	357	{
r32760	r32761
388	388	case INTV_VOICE:
389	389	m_cart->late_subslot_setup();
390	390	m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x0080, 0x0081, read16_delegate(FUNC(intv_cart_slot_device::read_speech),(intv_cart_slot_device)m_cart), write16_delegate(FUNC(intv_cart_slot_device::write_speech),(intv_cart_slot_device)m_cart));
391
	391
392	392	// passthru for RAM-equipped carts
393	393	m_maincpu->space(AS_PROGRAM).install_write_handler(0x8800, 0x8fff, write16_delegate(FUNC(intv_cart_slot_device::write_88),(intv_cart_slot_device*)m_cart));
394	394	m_maincpu->space(AS_PROGRAM).install_write_handler(0xd000, 0xd7ff, write16_delegate(FUNC(intv_cart_slot_device::write_d0),(intv_cart_slot_device*)m_cart));
r32760	r32761
402	402	m_maincpu->space(AS_PROGRAM).install_write_handler(0x7000, 0x7fff, write16_delegate(FUNC(intv_cart_slot_device::write_rom70),(intv_cart_slot_device*)m_cart));
403	403	m_maincpu->space(AS_PROGRAM).install_write_handler(0xe000, 0xefff, write16_delegate(FUNC(intv_cart_slot_device::write_rome0),(intv_cart_slot_device*)m_cart));
404	404	m_maincpu->space(AS_PROGRAM).install_write_handler(0xf000, 0xffff, write16_delegate(FUNC(intv_cart_slot_device::write_romf0),(intv_cart_slot_device*)m_cart));
405
	405
406	406	// passthru for Intellivoice expansion
407	407	m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x0080, 0x0081, read16_delegate(FUNC(intv_cart_slot_device::read_speech),(intv_cart_slot_device)m_cart), write16_delegate(FUNC(intv_cart_slot_device::write_speech),(intv_cart_slot_device)m_cart));
408
	408
409	409	// passthru for RAM-equipped carts
410	410	m_maincpu->space(AS_PROGRAM).install_write_handler(0x8800, 0x8fff, write16_delegate(FUNC(intv_cart_slot_device::write_88),(intv_cart_slot_device*)m_cart));
411	411	m_maincpu->space(AS_PROGRAM).install_write_handler(0xd000, 0xd7ff, write16_delegate(FUNC(intv_cart_slot_device::write_d0),(intv_cart_slot_device*)m_cart));

trunk/src/mess/machine/bbc.c
r32760	r32761
1941	1941	int bbc_state::bbc_load_cart(device_image_interface &image, generic_slot_device *slot)
1942	1942	{
1943	1943	UINT32 size = slot->common_get_size("rom");
1944
	1944
1945	1945	if (size != 0x2000 && size != 0x4000)
1946	1946	{
1947	1947	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
1948	1948	return IMAGE_INIT_FAIL;
1949	1949	}
1950
	1950
1951	1951	slot->rom_alloc(size, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
1952	1952	slot->common_load_rom(slot->get_rom_base(), size, "rom");
1953
	1953
1954	1954	return IMAGE_INIT_PASS;
1955	1955	}
1956	1956
r32760	r32761
1969	1969	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
1970	1970	return IMAGE_INIT_FAIL;
1971	1971	}
1972
	1972
1973	1973	slot->rom_alloc(filesize, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
1974	1974	image.fread(slot->get_rom_base(), filesize);
1975	1975	return IMAGE_INIT_PASS;
r32760	r32761
1978	1978	{
1979	1979	UINT32 size_lo = image.get_software_region_length("lorom");
1980	1980	UINT32 size_hi = image.get_software_region_length("uprom");
1981
	1981
1982	1982	if (size_lo + size_hi != 0x8000)
1983	1983	{
1984	1984	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
1985	1985	return IMAGE_INIT_FAIL;
1986	1986	}
1987
	1987
1988	1988	slot->rom_alloc(size_lo + size_hi, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
1989	1989	memcpy(slot->get_rom_base() + 0, image.get_software_region("uprom"), size_hi);
1990	1990	memcpy(slot->get_rom_base() + size_hi, image.get_software_region("lorom"), size_lo);
1991	1991	}
1992
	1992
1993	1993	return IMAGE_INIT_PASS;
1994	1994	}
1995	1995
r32760	r32761
2052	2052	eprom[3] = tmp_reg->base() + shift;
2053	2053	else
2054	2054	eprom[3] = m_region_opt->base() + 0xc000 + shift;
2055
	2055
2056	2056	membank->configure_entries(0, 1, eprom[0], size);
2057	2057	membank->configure_entries(1, 1, eprom[1], size);
2058	2058	membank->configure_entries(2, 1, eprom[2], size);
r32760	r32761
2078	2078	eprom[1] = tmp_reg->base() + shift;
2079	2079	else
2080	2080	eprom[1] = m_region_opt->base() + 0x8000 + shift;
2081
	2081
2082	2082	membank->configure_entries(0, 1, eprom[0], size);
2083	2083	membank->configure_entries(1, 1, eprom[0] + 0x4000, size);
2084	2084	membank->configure_entries(2, 1, eprom[1], size);
2085	2085	membank->configure_entries(3, 1, eprom[1] + 0x4000, size);
2086
	2086
2087	2087	if (banks > 4)
2088	2088	{
2089	2089	for (int i = 0; i < banks - 4; i++)
r32760	r32761
2127	2127	m_previous_wd177x_int_state=1;
2128	2128	bbc_setup_banks(m_bank4, 16, 0, 0x4000);
2129	2129	if (m_region_dfs)
2130		m_bank4->configure_entries(16, 8, m_region_dfs->base(), 0x4000); // additional bank for paged ram
	2130	m_bank4->configure_entries(16, 8, m_region_dfs->base(), 0x4000); // additional bank for paged ram
2131	2131	}
2132	2132
2133	2133	MACHINE_RESET_MEMBER(bbc_state, bbcb)
r32760	r32761
2155	2155	m_maincpu->space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(bbc_state::bbcbp_direct_handler), this));
2156	2156
2157	2157	bbc_setup_banks(m_bank4, 16, 0, 0x3000);
2158		m_bank4->configure_entries(16, 1, m_region_maincpu->base() + 0x8000, 0x3000); // additional bank for paged ram
	2158	m_bank4->configure_entries(16, 1, m_region_maincpu->base() + 0x8000, 0x3000); // additional bank for paged ram
2159	2159	bbc_setup_banks(m_bank6, 16, 0x3000, 0x1000);
2160	2160	}
2161	2161
r32760	r32761
2180	2180	m_maincpu->space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(bbc_state::bbcm_direct_handler), this));
2181	2181
2182	2182	bbcm_setup_banks(m_bank4, 16, 0, 0x1000);
2183		m_bank4->configure_entries(16, 1, m_region_maincpu->base() + 0x8000, 0x1000); // additional bank for paged ram
	2183	m_bank4->configure_entries(16, 1, m_region_maincpu->base() + 0x8000, 0x1000); // additional bank for paged ram
2184	2184	bbcm_setup_banks(m_bank5, 16, 0x1000, 0x3000);
2185	2185
2186	2186	/* Set ROM/IO bank to point to rom */

trunk/src/mess/machine/apple2.c
r32760	r32761
366	366	}
367	367	}
368	368	}
369
	369
370	370	if ((m_machinetype == APPLE_IICPLUS) && (slot == 6))
371	371	{
372	372	offset &= 0xf;
r32760	r32761
377	377	{
378	378	offset &= 0xf;
379	379	UINT8 retval = m_exp_regs[offset];
380
	380
381	381	if (offset == 3)
382	382	{
383	383	retval = m_exp_ram[m_exp_liveptr&m_exp_addrmask];
r32760	r32761
2287	2287
2288	2288	MACHINE_START_MEMBER(apple2_state,tk3000)
2289	2289	{
2290		m_machinetype = TK3000; // enhanced IIe clone with Z80 keyboard scanner subcpu
	2290	m_machinetype = TK3000; // enhanced IIe clone with Z80 keyboard scanner subcpu
2291	2291
2292	2292	apple2eplus_init_common((void *)NULL);
2293	2293	}
r32760	r32761
2335	2335	apple2_init_common();
2336	2336
2337	2337	// 1 MB of expansion RAM in slot 5
2338		m_exp_ram = auto_alloc_array(machine(), UINT8, 1024*1024);
	2338	m_exp_ram = auto_alloc_array(machine(), UINT8, 1024*1024);
2339	2339	memset(m_exp_ram, 0xff, 1024*1024);
2340	2340
2341	2341	m_exp_bankhior = 0xf0;

trunk/src/mess/machine/apple3.c
r32760	r32761
1275	1275	m_maincpu->set_input_line(INPUT_LINE_NMI, state);
1276	1276	}
1277	1277	}
1278

trunk/src/mess/machine/aim65.c
r32760	r32761
149	149	space.install_read_handler(0xc000, 0xcfff, read8_delegate(FUNC(generic_slot_device::read_rom),(generic_slot_device*)m_z25));
150	150	if (m_z26->exists())
151	151	space.install_read_handler(0xb000, 0xbfff, read8_delegate(FUNC(generic_slot_device::read_rom),(generic_slot_device*)m_z26));
152
	152
153	153	// Init RAM
154	154	space.install_ram(0x0000, ram->size() - 1, ram->pointer());
155	155

trunk/src/mess/machine/gamecom.c
r32760	r32761
640	640	UINT32 load_offset = 0;
641	641
642	642	if (size != 0x008000 && size != 0x040000 && size != 0x080000
643		&& size != 0x100000 && size != 0x1c0000 && size != 0x200000)
	643	&& size != 0x100000 && size != 0x1c0000 && size != 0x200000)
644	644	{
645	645	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
646	646	return IMAGE_INIT_FAIL;
647	647	}
648
	648
649	649	if (size == 0x1c0000)
650	650	load_offset = 0x40000;
651
	651
652	652	// in order to simplify banked access from the driver, we always allocate 0x200000,
653	653	slot->rom_alloc(0x200000, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
654	654	// we load what we have
r32760	r32761
661	661	if (size < 0x080000) { memcpy(crt + 0x040000, crt, 0x040000); } /* ->512KB */
662	662	if (size < 0x100000) { memcpy(crt + 0x080000, crt, 0x080000); } /* ->1MB */
663	663	if (size < 0x1c0000) { memcpy(crt + 0x100000, crt, 0x100000); } /* -> >=1.8MB */
664
	664
665	665	return IMAGE_INIT_PASS;
666	666	}
667	667

trunk/src/mess/machine/thomson.c
r32760	r32761
1841	1841	thom_set_video_mode( THOM_VMODE_TO9 );
1842	1842	break;
1843	1843
1844		// undocumented, but tested on a real TO8D
1845		case 0x20: thom_set_video_mode( THOM_VMODE_MO5_ALT ); break;
	1844	// undocumented, but tested on a real TO8D
	1845	case 0x20: thom_set_video_mode( THOM_VMODE_MO5_ALT ); break;
1846	1846
1847	1847	case 0x21: thom_set_video_mode( THOM_VMODE_BITMAP4 ); break;
1848	1848
1849	1849	case 0x41: thom_set_video_mode( THOM_VMODE_BITMAP4_ALT ); break;
1850	1850
1851		// also undocumented but tested
	1851	// also undocumented but tested
1852	1852	case 0x59: thom_set_video_mode( THOM_VMODE_BITMAP4_ALT_HALF ); break;
1853	1853
1854	1854	case 0x2a:
r32760	r32761
1866	1866
1867	1867	case 0x26: thom_set_video_mode( THOM_VMODE_OVERLAY ); break;
1868	1868
1869		// undocumented 160x200 variant of overlay
	1869	// undocumented 160x200 variant of overlay
1870	1870	case 0x3e: thom_set_video_mode( THOM_VMODE_OVERLAY_HALF ); break;
1871	1871
1872	1872	case 0x3f: thom_set_video_mode( THOM_VMODE_OVERLAY3 ); break;

trunk/src/mess/machine/nc.c
r32760	r32761
49	49	UINT32 size = m_card->common_get_size("rom");
50	50
51	51	m_card->rom_alloc(size, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
52		m_card->common_load_rom(m_card->get_rom_base(), size, "rom");
	52	m_card->common_load_rom(m_card->get_rom_base(), size, "rom");
53	53
54	54	set_card_present_state(1);
55	55	m_membank_card_ram_mask = card_calculate_mask(size);
r32760	r32761
64	64	// if there is no data to write, quit
65	65	if (!m_card_size)
66	66	return;
67
	67
68	68	logerror("attempting card save\n");
69
	69
70	70	// write data
71	71	image.fwrite(m_card_ram, m_card_size);
72
	72
73	73	logerror("write succeeded!\r\n");
74
	74
75	75	// set card not present state
76	76	set_card_present_state(0);
77	77	m_card_size = 0;
r32760	r32761
83	83	set_card_present_state(0);
84	84	m_card_size = 0;
85	85	}
86

trunk/src/mess/machine/primo.c
r32760	r32761
244	244	{
245	245	astring region_tag;
246	246	m_cart1_rom = memregion(region_tag.cpy(m_cart1->tag()).cat(GENERIC_ROM_REGION_TAG));
247		m_cart2_rom = memregion(region_tag.cpy(m_cart2->tag()).cat(GENERIC_ROM_REGION_TAG));
	247	m_cart2_rom = memregion(region_tag.cpy(m_cart2->tag()).cat(GENERIC_ROM_REGION_TAG));
248	248	}
249	249
250	250	void primo_state::machine_reset()

trunk/src/mess/machine/electron.c
r32760	r32761
344	344	}
345	345
346	346	void electron_state::machine_start()
347		{
	347	{
348	348	UINT8 lo_rom, up_rom;
349	349	astring region_tag;
350	350	memory_region *cart_rom = memregion(region_tag.cpy(m_cart->tag()).cat(GENERIC_ROM_REGION_TAG));
r32760	r32761
357	357	lo_rom = cart_rom->base() + 0x4000;
358	358	else
359	359	lo_rom = memregion("user1")->base();
360
	360
361	361	membank("bank2")->configure_entries(0, 1, lo_rom, 0x4000);
362	362	membank("bank2")->configure_entries(1, 11, memregion("user1")->base() + 0x04000, 0x4000);
363	363	membank("bank2")->configure_entries(12, 1, up_rom, 0x4000);
r32760	r32761
389	389	{
390	390	int upsize = image.get_software_region_length("uprom");
391	391	int losize = image.get_software_region_length("lorom");
392
	392
393	393	if (upsize != 16384 && upsize != 0)
394	394	{
395	395	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Invalid size for uprom");
396	396	return IMAGE_INIT_FAIL;
397	397	}
398
	398
399	399	if (losize != 16384 && losize != 0)
400	400	{
401	401	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Invalid size for lorom");
r32760	r32761
406	406
407	407	if (upsize)
408	408	memcpy(m_cart->get_rom_base(), image.get_software_region("uprom"), upsize);
409
	409
410	410	if (losize)
411	411	memcpy(m_cart->get_rom_base() + upsize, image.get_software_region("lorom"), losize);
412	412

trunk/src/mess/machine/nes.c
r32760	r32761
97	97	sprintf(str, "FT_COL%i", i);
98	98	m_io_ftrainer[i] = ioport(str);
99	99	}
100
	100
101	101	m_io_ctrlsel = ioport("CTRLSEL");
102	102	m_io_exp = ioport("EXP");
103	103	m_io_paddle = ioport("PADDLE");

trunk/src/mess/machine/amstrad.c
r32760	r32761
3031	3031	m_asic.ram = m_region_user1->base(); // 16kB RAM for ASIC, memory-mapped registers.
3032	3032	m_system_type = SYSTEM_PLUS;
3033	3033	m_centronics->write_data7(0);
3034
	3034
3035	3035	astring region_tag;
3036	3036	m_region_cart = memregion(region_tag.cpy(m_cart->tag()).cat(GENERIC_ROM_REGION_TAG));
3037	3037	}
r32760	r32761
3073	3073	{
3074	3074	m_asic.ram = m_region_user1->base(); // 16kB RAM for ASIC, memory-mapped registers.
3075	3075	m_system_type = SYSTEM_GX4000;
3076
	3076
3077	3077	astring region_tag;
3078	3078	m_region_cart = memregion(region_tag.cpy(m_cart->tag()).cat(GENERIC_ROM_REGION_TAG));
3079	3079	}
r32760	r32761
3187	3187	// check for .CPR header
3188	3188	if (image.software_entry() == NULL)
3189	3189	{
3190		image.fread(header, 12);
	3190	image.fread(header, 12);
3191	3191	if (strncmp((char *)header, "RIFF", 4) != 0)
3192	3192	{
3193	3193	// not a CPR file, so rewind the image at start
r32760	r32761
3219	3219	return IMAGE_INIT_FAIL;
3220	3220	}
3221	3221	else
3222		image.fread(m_cart->get_rom_base(), size);
	3222	image.fread(m_cart->get_rom_base(), size);
3223	3223	}
3224	3224	else
3225	3225	{
r32760	r32761
3229	3229	// Chunks labeled 'cb00' represent Cartridge block 0, and is loaded to &0000-&3fff
3230	3230	// 'cb01' represent Cartridge block 1, and is loaded to &4000-&7fff
3231	3231	// ... and so on.
3232
	3232
3233	3233	UINT32 offset = 0;
3234	3234	UINT8 *crt = m_cart->get_rom_base();
3235	3235	dynamic_buffer temp_copy;
r32760	r32761
3241	3241	char chunklen[4]; // chunk length (always little-endian)
3242	3242	int chunksize; // chunk length, calcaulated from the above
3243	3243	int ramblock; // 16k RAM block chunk is to be loaded into
3244		unsigned int bytes_to_read; // total bytes to read, as mame_feof doesn't react to EOF without trying to go past it.
	3244	unsigned int bytes_to_read; // total bytes to read, as mame_feof doesn't react to EOF without trying to go past it.
3245	3245
3246	3246	// Is RIFF format (*.cpr)
3247	3247	if (strncmp((char*)(header + 8), "AMS!", 4) != 0)

trunk/src/mess/machine/svi318.c
r32760	r32761
60	60	}
61	61
62	62	m_cart->rom_alloc(size, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
63		m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
	63	m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
64	64
65	65	if (image.software_entry() == NULL && !cart_verify(m_cart->get_rom_base()))
66	66	return IMAGE_INIT_FAIL;
r32760	r32761
407	407	/* memory */
408	408	m_empty_bank = auto_alloc_array(machine(), UINT8, 0x8000);
409	409	memset(m_empty_bank, 0xff, 0x8000);
410
	410
411	411	m_bank_low_ptr = m_empty_bank;
412	412	m_bank_high1_ptr = m_empty_bank;
413		m_bank_high2_ptr = m_empty_bank;
	413	m_bank_high2_ptr = m_empty_bank;
414	414	}
415	415
416	416	DRIVER_INIT_MEMBER(svi318_state, svi328_806)
r32760	r32761
434	434	save_item(NAME(m_svi806_ram));
435	435	memset(m_svi806_ram, 0x00, 0x800);
436	436	memset(m_svi806_ram + 0x800, 0xff, 0x800);
437
	437
438	438	m_svi806_gfx = memregion("gfx1")->base();
439
	439
440	440	// Set SVI-806 80 column card palette
441	441	m_palette->set_pen_color(TMS9928A_PALETTE_SIZE, 0, 0, 0); /* Monochrome black */
442	442	m_palette->set_pen_color(TMS9928A_PALETTE_SIZE+1, 0, 224, 0); /* Monochrome green */
r32760	r32761
459	459
460	460	save_item(NAME(m_svi806_present));
461	461	save_item(NAME(m_svi806_ram_enabled));
462
	462
463	463	machine().save().register_postload(save_prepost_delegate(FUNC(svi318_state::postload), this));
464	464	}
465	465
r32760	r32761
485	485	}
486	486
487	487	void svi318_state::machine_reset()
488		{
	488	{
489	489	m_keyboard_row = 0;
490	490	m_centronics_busy = 0;
491	491	m_svi806_present = 0;
r32760	r32761
587	587	}
588	588
589	589	m_bank_high1_ptr = m_empty_bank;
590		m_bank_high1_read_only = 1;
	590	m_bank_high1_read_only = 1;
591	591	m_bank_high2_ptr = m_empty_bank;
592	592	m_bank_high2_read_only = 1;
593	593

trunk/src/mess/machine/amigakbd.c
r32760	r32761
8	8	We currently emulate the Amiga 500 keyboard controller, which was
9	9	also used in later Amiga 2000 keyboards.
10	10
11		TODO: - Natural keyboard mode doesn't work with shifted characters,
12		they get sent in the wrong order (core bug?)
13		- Move 6500/1 to its own CPU core so that it can be shared with
14		other systems
15		- Add support for more keyboard controllers (pending on them
16		getting dumped)
	11	TODO: - Natural keyboard mode doesn't work with shifted characters,
	12	they get sent in the wrong order (core bug?)
	13	- Move 6500/1 to its own CPU core so that it can be shared with
	14	other systems
	15	- Add support for more keyboard controllers (pending on them
	16	getting dumped)
17	17
18		Amiga 1000 keyboard part numbers (manufactured by Mitsumi):
	18	Amiga 1000 keyboard part numbers (manufactured by Mitsumi):
19	19
20		- 327063-01 R56-2144 English
21		- 327063-02 British
22		- 327063-03 R56-2153 German
23		- 327063-04 R56-2152 French
24		- 327063-05 R56-2154 Italian
	20	- 327063-01 R56-2144 English
	21	- 327063-02 British
	22	- 327063-03 R56-2153 German
	23	- 327063-04 R56-2152 French
	24	- 327063-05 R56-2154 Italian
25	25
26	26	***************************************************************************/
27	27
r32760	r32761
335	335	m_kclk = 1;
336	336	m_port_c = 0xff;
337	337	m_port_d = 0xff;
338		m_latch = 0xffff; // not initialized by hardware
339		m_counter = 0xffff; // not initialized by hardware
	338	m_latch = 0xffff; // not initialized by hardware
	339	m_counter = 0xffff; // not initialized by hardware
340	340	m_control = 0x00;
341	341
342	342	m_timer->adjust(attotime::zero, 0, attotime::from_hz(XTAL_3MHz / 2));

trunk/src/mess/machine/wswan.c
r32760	r32761
201	201	{
202	202	m_ws_bios_bank = auto_alloc_array(machine(), UINT8, 0x10000);
203	203	memcpy(m_ws_bios_bank + 0xffc0, ws_fake_bios_code, 0x40);
204
	204
205	205	m_vdp.timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(wswan_state::wswan_scanline_interrupt),this), &m_vdp);
206	206	m_vdp.timer->adjust(attotime::from_ticks(256, 3072000), 0, attotime::from_ticks(256, 3072000));
207
	207
208	208	wswan_register_save();
209
	209
210	210	machine().device<nvram_device>("nvram")->set_base(m_internal_eeprom, INTERNAL_EEPROM_SIZE);
211
	211
212	212	if (m_cart->exists())
213		{
	213	{
214	214	// ROM
215	215	m_maincpu->space(AS_PROGRAM).install_read_handler(0x20000, 0x2ffff, read8_delegate(FUNC(ws_cart_slot_device::read_rom20),(ws_cart_slot_device*)m_cart));
216	216	m_maincpu->space(AS_PROGRAM).install_read_handler(0x30000, 0x3ffff, read8_delegate(FUNC(ws_cart_slot_device::read_rom30),(ws_cart_slot_device*)m_cart));
217	217	m_maincpu->space(AS_PROGRAM).install_read_handler(0x40000, 0xeffff, read8_delegate(FUNC(ws_cart_slot_device::read_rom40),(ws_cart_slot_device*)m_cart));
218
	218
219	219	// SRAM
220	220	if (m_cart->get_type() == WS_SRAM)
221	221	{
r32760	r32761
249	249	if (m_cart->exists())
250	250	m_rotate = m_cart->get_is_rotated();
251	251	else
252		m_rotate = 0;
	252	m_rotate = 0;
253	253
254	254	/* Intialize ports */
255	255	memcpy(m_ws_portram, ws_portram_init, 256);
r32760	r32761
332	332	case 0xc1:
333	333	case 0xc2:
334	334	case 0xc3:
335		case 0xc4: // EEPROM data
336		case 0xc5: // EEPROM data
	335	case 0xc4: // EEPROM data
	336	case 0xc5: // EEPROM data
337	337	case 0xc6:
338	338	case 0xc7:
339	339	case 0xc8:
340	340	case 0xc9:
341	341	case 0xca:
342		case 0xcb: // RTC data
	342	case 0xcb: // RTC data
343	343	case 0xcc:
344	344	case 0xcd:
345	345	case 0xce:
r32760	r32761
1034	1034	logerror( "Unsupported internal EEPROM command: %X\n", data );
1035	1035	}
1036	1036	break;
1037		case 0xc0: // ROM bank $40000-$fffff
1038		case 0xc1: // SRAM bank
1039		case 0xc2: // ROM bank $20000-$2ffff
1040		case 0xc3: // ROM bank $30000-$3ffff
	1037	case 0xc0: // ROM bank $40000-$fffff
	1038	case 0xc1: // SRAM bank
	1039	case 0xc2: // ROM bank $20000-$2ffff
	1040	case 0xc3: // ROM bank $30000-$3ffff
1041	1041	case 0xc4:
1042	1042	case 0xc5:
1043		case 0xc6: // EEPROM address / command
1044		case 0xc7: // EEPROM address / command
1045		case 0xc8: // EEPROM command
	1043	case 0xc6: // EEPROM address / command
	1044	case 0xc7: // EEPROM address / command
	1045	case 0xc8: // EEPROM command
1046	1046	case 0xc9:
1047		case 0xca: // RTC command
1048		case 0xcb: // RTC data
	1047	case 0xca: // RTC command
	1048	case 0xcb: // RTC data
1049	1049	case 0xcc:
1050	1050	case 0xcd:
1051	1051	case 0xce:

trunk/src/mess/machine/vtech2.c
r32760	r32761
71	71
72	72	m_laser_latch = -1;
73	73	m_mem = memregion("maincpu")->base();
74
	74
75	75	// check ROM expansion
76	76	astring region_tag;
77	77	m_cart_rom = memregion(region_tag.cpy(m_cart->tag()).cat(GENERIC_ROM_REGION_TAG));
78
	78
79	79	for (i = 0; i < ARRAY_LENGTH(m_laser_bank); i++)
80	80	m_laser_bank[i] = -1;
81	81	}
r32760	r32761
88	88	m_laser_video_bank = video_mask;
89	89	m_videoram = m_mem + m_laser_video_bank * 0x04000;
90	90	logerror("laser_machine_init(): bank mask $%04X, video %d [$%05X]\n", m_laser_bank_mask, m_laser_video_bank, m_laser_video_bank * 0x04000);
91
	91
92	92	for (int i = 0; i < ARRAY_LENGTH(m_laser_bank); i++)
93	93	laser_bank_select_w(m_maincpu->space(AS_PROGRAM), i, 0);
94	94	}
r32760	r32761
153	153	else
154	154	{
155	155	sprintf(bank, "bank%d", offset + 1);
156		if (data >= 12 && m_cart_rom && (m_cart_rom->bytes() > (data % 12) * 0x4000)) // Expansion ROM banks
	156	if (data >= 12 && m_cart_rom && (m_cart_rom->bytes() > (data % 12) * 0x4000)) // Expansion ROM banks
157	157	{
158	158	membank(bank)->set_base(m_cart_rom->base()+ (data % 12) * 0x4000);
159	159	m_maincpu->space(AS_PROGRAM).install_read_bank(offset * 0x4000, offset * 0x4000 + 0x3fff, mra_bank_hard[offset]);
160	160	m_maincpu->space(AS_PROGRAM).install_write_bank(offset * 0x4000, offset * 0x4000 + 0x3fff, mwa_bank_hard[offset]);
161	161	}
162		else if (data < 12 && (m_laser_bank_mask & (1 << data))) // ROM/RAM banks
	162	else if (data < 12 && (m_laser_bank_mask & (1 << data))) // ROM/RAM banks
163	163	{
164	164	// video RAM bank selected?
165	165	if (data == m_laser_video_bank)
r32760	r32761
175	175	m_maincpu->space(AS_PROGRAM).nop_readwrite(offset * 0x4000, offset * 0x4000 + 0x3fff);
176	176	}
177	177	}
178
	178
179	179	}
180	180	}
181	181

trunk/src/mess/tiny.lst
r32760	r32761
39	39	******************************************************************************/
40	40
41	41	coleco // NTSC ColecoVision
42		colecop // PAL Colecovision
	42	colecop // PAL Colecovision

trunk/src/mess/includes/svi318.h
r32760	r32761
52	52	m_bank3(*this, "bank3"),
53	53	m_bank4(*this, "bank4")
54	54	{ }
55
	55
56	56	// FDC
57	57	UINT8 m_driveselect;
58	58	int m_drq;
r32760	r32761
91	91	MC6845_UPDATE_ROW(crtc_update_row);
92	92	memory_region *m_cart_rom;
93	93	memory_region *m_bios_rom;
94
	94
95	95	protected:
96	96	required_device<z80_device> m_maincpu;
97	97	required_device<cassette_image_device> m_cassette;
r32760	r32761
111	111	optional_device<palette_device> m_palette;
112	112
113	113	private:
114
	114
115	115	void set_banks();
116	116	void postload();
117
	117
118	118	// memory banking
119	119	UINT8 m_bank_switch;
120	120	UINT8 m_bank_low;
121	121	UINT8 m_bank_high;
122
	122
123	123	UINT8 m_bank_low_read_only;
124	124	UINT8 m_bank_high1_read_only;
125	125	UINT8 m_bank_high2_read_only;
126
	126
127	127	UINT8 *m_empty_bank;
128	128	UINT8 *m_bank_low_ptr;
129	129	UINT8 *m_bank_high1_ptr;
130	130	UINT8 *m_bank_high2_ptr;
131
	131
132	132	// keyboard
133	133	UINT8 m_keyboard_row;
134
	134
135	135	// centronics
136	136	int m_centronics_busy;
137
	137
138	138	// SVI-806 80 column card
139	139	UINT8 m_svi806_present;
140	140	UINT8 m_svi806_ram_enabled;

trunk/src/mess/includes/atom.h
r32760	r32761
108	108	/* devices */
109	109	int m_previous_i8271_int_state;
110	110	TIMER_DEVICE_CALLBACK_MEMBER(cassette_output_tick);
111
	111
112	112	int load_cart(device_image_interface &image, generic_slot_device *slot);
113		DECLARE_DEVICE_IMAGE_LOAD_MEMBER(cart_load) { return load_cart(image, m_cart); }
	113	DECLARE_DEVICE_IMAGE_LOAD_MEMBER(cart_load) { return load_cart(image, m_cart); }
114	114	DECLARE_QUICKLOAD_LOAD_MEMBER(atom_atm);
115	115	};
116	116
r32760	r32761
121	121	: atom_state(mconfig, type, tag),
122	122	m_e0(*this, "rom_e0"),
123	123	m_e1(*this, "rom_e1")
124		{
	124	{
125	125	}
126	126
127	127	virtual void machine_start();
r32760	r32761
132	132	DECLARE_READ8_MEMBER(dos_r);
133	133
134	134	DECLARE_DRIVER_INIT(atomeb);
135
	135
136	136	/* eprom state */
137	137	int m_eprom;
138
	138
139	139	generic_slot_device *m_ext[16];
140	140	required_device<generic_slot_device> m_e0;
141	141	required_device<generic_slot_device> m_e1;

trunk/src/mess/includes/electron.h
r32760	r32761
70	70	: driver_device(mconfig, type, tag),
71	71	m_maincpu(*this, "maincpu"),
72	72	m_cassette(*this, "cassette"),
73		m_beeper(*this, "beeper"),
	73	m_beeper(*this, "beeper"),
74	74	m_cart(*this, "cartslot"),
75		m_keybd(*this, "LINE")
	75	m_keybd(*this, "LINE")
76	76	{ }
77	77
78	78	ULA m_ula;

trunk/src/mess/includes/intv.h
r32760	r32761
44	44	m_io_options(*this, "OPTIONS"),
45	45	m_io_test(*this, "TEST"),
46	46	m_gfxdecode(*this, "gfxdecode"),
47		m_palette(*this, "palette")
	47	m_palette(*this, "palette")
48	48	{ }
49	49
50	50	required_device<cpu_device> m_maincpu;
r32760	r32761
66	66
67	67	DECLARE_READ8_MEMBER(intv_right_control_r);
68	68	DECLARE_READ8_MEMBER(intv_left_control_r);
69
	69
70	70	UINT8 m_bus_copy_mode;
71	71	UINT8 m_backtab_row;
72	72	UINT16 m_ram16[0x160];

trunk/src/mess/includes/concept.h
r32760	r32761
21	21	#define ACIA_0_TAG "acia0"
22	22	#define ACIA_1_TAG "acia1"
23	23	#define KBD_ACIA_TAG "kbacia"
24		#define SPEAKER_TAG "spkr"
	24	#define SPEAKER_TAG "spkr"
25	25	#define A2BUS_TAG "a2bus"
26	26
27	27	class concept_state : public driver_device

trunk/src/mess/includes/radio86.h
r32760	r32761
88	88
89	89	protected:
90	90	required_device<cassette_image_device> m_cassette;
91		optional_device<generic_slot_device> m_cart; // for ROMDisk - only Radio86K & Orion?
	91	optional_device<generic_slot_device> m_cart; // for ROMDisk - only Radio86K & Orion?
92	92	optional_device<i8257_device> m_dma8257;
93	93	required_device<i8255_device> m_ppi8255_1;
94	94	optional_device<i8255_device> m_ppi8255_2;

trunk/src/mess/includes/apple2.h
r32760	r32761
26	26
27	27	#define IIC_ACIA1_TAG "acia1"
28	28	#define IIC_ACIA2_TAG "acia2"
29		#define IICP_IWM_TAG "iwm"
	29	#define IICP_IWM_TAG "iwm"
30	30
31	31	#define LASER128_UDC_TAG "l128udc"
32	32
r32760	r32761
83	83	APPLE_IIC, // Apple IIc
84	84	APPLE_IICPLUS, // Apple IIc+
85	85	TK2000, // Microdigital TK2000
86		TK3000, // Microdigital TK3000
	86	TK3000, // Microdigital TK3000
87	87	LASER128, // Laser 128/128EX/128EX2
88	88	SPACE84, // "Space 84" with flipped text mode
89	89	LABA2P // lab equipment (?) II Plus with flipped text mode

trunk/src/mess/video/maria.c
r32760	r32761
2	2
3	3	Atari MARIA video emulation
4	4
5
	5
6	6	- some history:
7		2014-10-05 Mike Saarna, Robert Tuccitto Last Line DMA value corrected
8		to 6. GCC and Atari docs both show a difference between
9		Other Line and Last Line as +6 at the lowest part of the
	7	2014-10-05 Mike Saarna, Robert Tuccitto Last Line DMA value corrected
	8	to 6. GCC and Atari docs both show a difference between
	9	Other Line and Last Line as +6 at the lowest part of the
10	10	range.
11		Blank scanlines are drawn when DMA is off, like real
	11	Blank scanlines are drawn when DMA is off, like real
12	12	hardware.
13		If MARIA hits the DMA limit, the CPU doesn't run until
	13	If MARIA hits the DMA limit, the CPU doesn't run until
14	14	the next scanline.
15	15
16		2014-09-03 Mike Saarna, Robert Tuccitto reorganized DMA penalties to
	16	2014-09-03 Mike Saarna, Robert Tuccitto reorganized DMA penalties to
17	17	support new rendering timeout code.
18	18
19	19	2014-08-29 Mike Saarna Timeout rendering added.
20
	20
21	21	2014-08-26 Fabio Priuli Converted to device
22	22
23	23	2014-05-06 Mike Saarna Added interrupts to DMA cycle eating. Updates to
r32760	r32761
61	61
62	62
63	63	void atari_maria_device::device_start()
64		{
	64	{
65	65	m_cpu = machine().device<cpu_device>(m_cpu_tag);
66	66	m_screen = machine().first_screen();
67	67	m_screen->register_screen_bitmap(m_bitmap);
r32760	r32761
181	181	// All lines in a zone have the same initial DMA startup time. We'll adjust
182	182	// cycles for the special last zone line later, as those penalties happen after
183	183	// MARIA is done rendering, or after its hit the maximum rendering time.
184		maria_cycles = 16;
	184	maria_cycles = 16;
185	185
186	186
187	187	/* Process this DLL entry */
r32760	r32761
232	232	data_addr = (m_charbase \| c) + (m_offset << 8);
233	233	if (is_holey(data_addr))
234	234	continue;
235
	235
236	236	maria_cycles += 3;
237	237	if (m_cwidth) // two data bytes per map byte
238	238	{
r32760	r32761
260	260	}
261	261	}
262	262	}
263
	263
264	264	// Last Line post-render DMA cycle penalties...
265		if (m_offset == 0)
	265	if (m_offset == 0)
266	266	{
267	267	maria_cycles += 6; // extra shutdown time
268	268	if (READ_MEM(m_dll + 3) & 0x80)
r32760	r32761
443	443	m_color_kill = data & 0x80;
444	444	switch ((data >> 5) & 3)
445	445	{
446		case 0x00:
	446	case 0x00:
447	447	case 01:
448	448	logerror("dma test mode, do not use.\n");
449	449	break;

trunk/src/mess/video/maria.h
r32760	r32761
12	12	atari_maria_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
13	13
14	14	static void set_cpu_tag(device_t &device, const char *tag) { downcast<atari_maria_device &>(device).m_cpu_tag = tag; }
15
	15
16	16	void interrupt(int lines);
17	17	void startdma(int lines);
18
	18
19	19	DECLARE_READ8_MEMBER(read);
20	20	DECLARE_WRITE8_MEMBER(write);
21	21
22	22	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
23
	23
24	24	protected:
25	25	// device-level overrides
26	26	virtual void device_start();
27	27	virtual void device_reset();
28	28
29	29	private:
30
	30
31	31	int m_maria_palette[32];
32	32	int m_line_ram[2][160];
33	33	int m_active_buffer;
r32760	r32761
54	54	int write_line_ram(int addr, UINT8 offset, int pal);
55	55
56	56	const char *m_cpu_tag;
57		cpu_device *m_cpu; // CPU whose space(AS_PROGRAM) serves as DMA source
	57	cpu_device *m_cpu; // CPU whose space(AS_PROGRAM) serves as DMA source
58	58	screen_device *m_screen;
59	59	};
60	60

trunk/src/mess/video/advision.c
r32760	r32761
65	65
66	66	for (int i = 0; i < 8; i++)
67	67	{
68		if (!BIT(data, 7 - i))
	68	if (!BIT(data, 7 - i))
69	69	dst[i * 256] = 8;
70	70	}
71	71

trunk/src/mess/video/apple3.c
r32760	r32761
412	412
413	413	UINT32 apple3_state::screen_update_apple3(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
414	414	{
415		// printf("gfx mode %x\n", m_flags & (VAR_VM3\|VAR_VM1\|VAR_VM0));
	415	// printf("gfx mode %x\n", m_flags & (VAR_VM3\|VAR_VM1\|VAR_VM0));
416	416
417	417	switch(m_flags & (VAR_VM3\|VAR_VM1\|VAR_VM0))
418	418	{

trunk/src/mess/video/nes.c
r32760	r32761
37	37	m_ppu->render(bitmap, 0, 0, 0, 0);
38	38
39	39	// if this is a disk system game, check for the flip-disk key
40		if ((m_cartslot && m_cartslot->exists() && (m_cartslot->get_pcb_id() == STD_DISKSYS)) // first scenario = disksys in m_cartslot (= famicom)
41		\|\| m_disk) // second scenario = disk via fixed internal disk option (fds & famitwin)
	40	if ((m_cartslot && m_cartslot->exists() && (m_cartslot->get_pcb_id() == STD_DISKSYS)) // first scenario = disksys in m_cartslot (= famicom)
	41	\|\| m_disk) // second scenario = disk via fixed internal disk option (fds & famitwin)
42	42	{
43	43	// latch this input so it doesn't go at warp speed
44	44	if ((m_io_disksel->read_safe(0) & 0x01) && (!m_last_frame_flip))

trunk/src/mess/video/thomson.c
r32760	r32761
412	412	int i;
413	413	pen_t c[2];
414	414	c[0] = pal[ (ramb & 15) ^ 8 ];
415		c[1] = pal[ (ramb >> 4) ^ 8 ];
	415	c[1] = pal[ (ramb >> 4) ^ 8 ];
416	416	for ( i = 0; i < 16; i += 2, rama >>= 1 )
417	417	dst[ 15 - i ] = dst[ 14 - i ] = c[ rama & 1 ];
418	418	}
r32760	r32761
715	715	c[0][0] = pal[ 0 ];
716	716	c[0][1] = c[1][1] = pal[ 1 ];
717	717	c[1][0] = pal[ 2 ];
718		rama >>= 4;
719		ramb >>= 4;
	718	rama >>= 4;
	719	ramb >>= 4;
720	720	for ( i = 0; i < 16; i += 4, rama >>= 1, ramb >>= 1 )
721		dst[ 15 - i ] = dst[ 14 - i ] = dst[ 13 - i ] = dst[ 12 - i ] =
722		c[ ramb & 1 ] [ rama & 1 ];
	721	dst[ 15 - i ] = dst[ 14 - i ] = dst[ 13 - i ] = dst[ 12 - i ] =
	722	c[ ramb & 1 ] [ rama & 1 ];
723	723	}
724	724	END_UPDATE
725	725
r32760	r32761
730	730	c[0][0] = pal[ 0 ];
731	731	c[0][1] = c[1][1] = pal[ 1 ];
732	732	c[1][0] = pal[ 2 ];
733		rama >>= 4;
734		ramb >>= 4;
	733	rama >>= 4;
	734	ramb >>= 4;
735	735	for ( i = 0; i < 8; i += 2, rama >>= 1, ramb >>= 1 )
736	736	dst[ 7 - i ] = dst[ 6 - i ] = c[ ramb & 1 ] [ rama & 1 ];
737	737	}
r32760	r32761
782	782	FUN(to770), FUN(mo5), FUN(bitmap4), FUN(bitmap4alt), FUN(mode80),
783	783	FUN(bitmap16), FUN(page1), FUN(page2), FUN(overlay), FUN(overlay3),
784	784	FUN(to9), FUN(mode80_to9),
785		FUN(bitmap4althalf), FUN(mo5alt), FUN(overlayhalf),
	785	FUN(bitmap4althalf), FUN(mo5alt), FUN(overlayhalf),
786	786	};
787	787
788	788
r32760	r32761
1199	1199	{
1200	1200	LOG (( "thom: palette init called\n" ));
1201	1201
1202		/* TO8 and later use an EF9369 color palette chip
1203		The spec shows a built-in gamma correction for gamma=2.8
1204		i.e., output is out = in ^ (1/2.8)
	1202	/* TO8 and later use an EF9369 color palette chip
	1203	The spec shows a built-in gamma correction for gamma=2.8
	1204	i.e., output is out = in ^ (1/2.8)
1205	1205
1206		For the TO7, the gamma correction is irrelevant.
1207
1208		For the TO7/70, we use the same palette and gamma has the TO8,
1209		which gives good results (but is not verified).
1210		*/
1211		thom_configure_palette(1.0 / 2.8, thom_pal_init, palette);
	1206	For the TO7, the gamma correction is irrelevant.
	1207
	1208	For the TO7/70, we use the same palette and gamma has the TO8,
	1209	which gives good results (but is not verified).
	1210	*/
	1211	thom_configure_palette(1.0 / 2.8, thom_pal_init, palette);
1212	1212	}
1213	1213
1214	1214	PALETTE_INIT_MEMBER(thomson_state, mo5)
1215	1215	{
1216	1216	LOG (( "thom: MO5 palette init called\n" ));
1217	1217
1218		/* The MO5 has a different fixed palette than the TO7/70.
1219		We use a smaller gamma correction which gives intutively better
1220		results (but is not verified).
1221		*/
1222		thom_configure_palette(1.0, mo5_pal_init, palette);
	1218	/* The MO5 has a different fixed palette than the TO7/70.
	1219	We use a smaller gamma correction which gives intutively better
	1220	results (but is not verified).
	1221	*/
	1222	thom_configure_palette(1.0, mo5_pal_init, palette);
1223	1223	}
1224	1224
1225	1225

trunk/src/mess/video/apple2.c
r32760	r32761
102	102	switch (m_sysconfig->read() & 0x03)
103	103	{
104	104	case 0:
105		break; // leave alone
	105	break; // leave alone
106	106
107	107	case 1:
108	108	if ((m_machinetype == APPLE_II) \|\| (m_machinetype == LABA2P) \|\| (m_machinetype == SPACE84))
r32760	r32761
182	182
183	183	for (i = 0; i < xscale; i++)
184	184	{
185		bitmap.pix16(ypos + y, xpos + (x * xscale) + i) = color;
	185	bitmap.pix16(ypos + y, xpos + (x * xscale) + i) = color;
186	186	}
187	187	}
188	188	}
r32760	r32761
352	352	{
353	353	case 0:
354	354	artifact_map_ptr = &m_hires_artifact_map[((vram_row[col+1] & 0x80) >> 7) * 16];
355		for (b = 0; b < 7; b++)
	355	for (b = 0; b < 7; b++)
356	356	{
357	357	v = artifact_map_ptr[((w >> (b + 7-1)) & 0x07) \| (((b ^ col) & 0x01) << 3)];
358	358	*(p++) = v;
r32760	r32761
362	362
363	363	case 1:
364	364	w >>= 7;
365		for (b = 0; b < 7; b++)
	365	for (b = 0; b < 7; b++)
366	366	{
367	367	v = (w & 1);
368	368	w >>= 1;
r32760	r32761
373	373
374	374	case 2:
375	375	w >>= 7;
376		for (b = 0; b < 7; b++)
	376	for (b = 0; b < 7; b++)
377	377	{
378	378	v = (w & 1);
379	379	w >>= 1;
r32760	r32761
384	384
385	385	case 3:
386	386	w >>= 7;
387		for (b = 0; b < 7; b++)
	387	for (b = 0; b < 7; b++)
388	388	{
389	389	v = (w & 1);
390	390	w >>= 1;
r32760	r32761
411	411	switch (mon_type)
412	412	{
413	413	case 0:
414		for (b = 0; b < 7; b++)
	414	for (b = 0; b < 7; b++)
415	415	{
416	416	v = m_dhires_artifact_map[((((w >> (b + 7-1)) & 0x0F) * 0x11) >> (((2-(col*7+b))) & 0x03)) & 0x0F];
417	417	*(p++) = v;

trunk/src/mame/includes/cinemat.h
r32760	r32761
30	30	optional_shared_ptr<UINT16> m_rambase;
31	31
32	32	typedef void (cinemat_state::*sound_func)(UINT8 sound_val, UINT8 bits_changed);
33
	33
34	34	sound_func m_sound_handler;
35		UINT8 m_sound_control;
	35	UINT8 m_sound_control;
36	36	UINT32 m_current_shift;
37	37	UINT32 m_last_shift;
38	38	UINT32 m_last_shift2;

trunk/src/mame/includes/stv.h
r32760	r32761
766	766	DECLARE_DEVICE_IMAGE_LOAD_MEMBER( stv_cart2 ) { return load_cart(image, m_cart2); }
767	767	DECLARE_DEVICE_IMAGE_LOAD_MEMBER( stv_cart3 ) { return load_cart(image, m_cart3); }
768	768	DECLARE_DEVICE_IMAGE_LOAD_MEMBER( stv_cart4 ) { return load_cart(image, m_cart4); }
769
	769
770	770	void install_stvbios_speedups( void );
771	771
772	772	DECLARE_MACHINE_START(stv);

trunk/src/mame/includes/fuukifg2.h
r32760	r32761
23	23	m_gfxdecode(*this, "gfxdecode"),
24	24	m_screen(*this, "screen"),
25	25	m_palette(*this, "palette"),
26		m_fuukivid(*this, "fuukivid")
	26	m_fuukivid(*this, "fuukivid")
27	27	{ }
28	28
29	29	/* memory pointers */

trunk/src/mame/includes/thepit.h
r32760	r32761
14	14	required_device<cpu_device> m_maincpu;
15	15	required_device<gfxdecode_device> m_gfxdecode;
16	16	required_device<palette_device> m_palette;
17
	17
18	18	required_shared_ptr<UINT8> m_videoram;
19	19	required_shared_ptr<UINT8> m_colorram;
20	20	required_shared_ptr<UINT8> m_attributesram;
21	21	required_shared_ptr<UINT8> m_spriteram;
22
	22
23	23	int m_question_address;
24	24	int m_question_rom;
25	25	int m_remap_address[16];

trunk/src/mame/includes/taito_f3.h
r32760	r32761
67	67	required_device<gfxdecode_device> m_gfxdecode;
68	68	required_device<screen_device> m_screen;
69	69	required_device<palette_device> m_palette;
70
	70
71	71	optional_shared_ptr<UINT32> m_f3_ram;
72	72	optional_shared_ptr<UINT32> m_paletteram32;
73
	73
74	74	UINT16 *m_videoram;
75	75	UINT16 *m_spriteram;
76	76	UINT16 *m_f3_vram;
r32760	r32761
364	364	inline void dpix_bg(UINT32 bgcolor);
365	365	void init_alpha_blend_func();
366	366	inline void draw_scanlines(bitmap_rgb32 &bitmap, int xsize, INT16 draw_line_num, const struct f3_playfield_line_inf line_t, const int sprite, UINT32 orient, int skip_layer_num);
367		void visible_tile_check(struct f3_playfield_line_inf line_t, int line, UINT32 x_index_fx,UINT32 y_index, UINT16 f3_pf_data_n);
	367	void visible_tile_check(struct f3_playfield_line_inf line_t, int line, UINT32 x_index_fx,UINT32 y_index, UINT16 f3_pf_data_n);
368	368	void calculate_clip(int y, UINT16 pri, UINT32* clip0, UINT32* clip1, int* line_enable);
369	369	void get_spritealphaclip_info();
370	370	void get_line_ram_info(tilemap_t tmap, int sx, int sy, int pos, UINT16 f3_pf_data_n);

trunk/src/mame/includes/fuukifg3.h
r32760	r32761
30	30	m_gfxdecode(*this, "gfxdecode"),
31	31	m_screen(*this, "screen"),
32	32	m_palette(*this, "palette"),
33		m_fuukivid(*this, "fuukivid")
	33	m_fuukivid(*this, "fuukivid")
34	34	{ }
35	35
36	36	/* memory pointers */

trunk/src/mame/includes/exterm.h
r32760	r32761
24	24	required_device<cpu_device> m_audioslave;
25	25	required_device<tms34010_device> m_slave;
26	26	required_device<dac_device> m_dac;
27
	27
28	28	required_shared_ptr<UINT16> m_master_videoram;
29	29	required_shared_ptr<UINT16> m_slave_videoram;
30
	30
31	31	UINT8 m_aimpos[2];
32	32	UINT8 m_trackball_old[2];
33	33	UINT8 m_master_sound_latch;

trunk/src/mame/includes/simple_st0016.h
r32760	r32761
12	12	{ }
13	13
14	14	int mux_port;
15		// UINT32 m_st0016_rom_bank;
	15	// UINT32 m_st0016_rom_bank;
16	16
17	17	optional_device<st0016_cpu_device> m_maincpu;
18	18	DECLARE_READ8_MEMBER(mux_r);

trunk/src/mame/includes/midyunit.h
r32760	r32761
57	57	optional_device<williams_narc_sound_device> m_narc_sound;
58	58	optional_device<williams_cvsd_sound_device> m_cvsd_sound;
59	59	optional_device<williams_adpcm_sound_device> m_adpcm_sound;
60
	60
61	61	required_shared_ptr<UINT16> m_generic_paletteram_16;
62	62	optional_shared_ptr<UINT8> m_gfx_rom;
63	63
r32760	r32761
130	130	DECLARE_VIDEO_START(common);
131	131	TIMER_CALLBACK_MEMBER(dma_callback);
132	132	TIMER_CALLBACK_MEMBER(autoerase_line);
133
	133
134	134	protected:
135	135	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
136	136	void dma_draw(UINT16 command);

trunk/src/mame/includes/artmagic.h
r32760	r32761
30	30	required_device<okim6295_device> m_oki;
31	31	required_device<tms34010_device> m_tms;
32	32	required_device<tlc34076_device> m_tlc34076;
33
	33
34	34	required_shared_ptr<UINT16> m_control;
35	35	required_shared_ptr<UINT16> m_vram0;
36	36	required_shared_ptr<UINT16> m_vram1;
37
	37
38	38	UINT8 m_tms_irq;
39	39	UINT8 m_hack_irq;
40	40	UINT8 m_prot_input[16];
r32760	r32761
49	49	void ultennis_protection();
50	50	void cheesech_protection();
51	51	void stonebal_protection();
52
	52
53	53	int m_xor[16];
54	54	int m_is_stoneball;
55	55	UINT16 *m_blitter_base;
r32760	r32761
80	80	void execute_blit();
81	81	void update_irq_state();
82	82	inline UINT16 address_to_vram(offs_t address);
83
	83
84	84	protected:
85	85	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
86	86	};

trunk/src/mame/includes/coolpool.h
r32760	r32761
19	19	required_device<cpu_device> m_dsp;
20	20	required_device<dac_device> m_dac;
21	21	optional_device<tlc34076_device> m_tlc34076;
22
	22
23	23	required_shared_ptr<UINT16> m_vram_base;
24	24	required_shared_ptr<UINT16> m_nvram;
25	25
r32760	r32761
37	37
38	38	UINT16 m_result;
39	39	UINT16 m_lastresult;
40
	40
41	41	UINT16 m_nvram_write_seq[NVRAM_UNLOCK_SEQ_LEN];
42	42	UINT8 m_nvram_write_enable;
43	43	UINT8 m_old_cmd;

trunk/src/mame/includes/midtunit.h
r32760	r32761
104	104	const UINT8 *jdredd_prot_table;
105	105	UINT8 jdredd_prot_index;
106	106	UINT8 jdredd_prot_max;
107
	107
108	108	UINT8 m_gfx_rom_large;
109	109
110	110	protected:

trunk/src/mame/includes/suprnova.h
r32760	r32761
43	43	required_device<sknsspr_device> m_spritegen;
44	44	required_device<gfxdecode_device> m_gfxdecode;
45	45	required_device<palette_device> m_palette;
46
	46
47	47	required_shared_ptr<UINT32> m_spriteram;
48	48	required_shared_ptr<UINT32> m_spc_regs;
49	49	required_shared_ptr<UINT32> m_v3_regs;
r32760	r32761
55	55	required_shared_ptr<UINT32> m_v3t_ram;
56	56	required_shared_ptr<UINT32> m_main_ram;
57	57	required_shared_ptr<UINT32> m_cache_ram;
58
	58
59	59	hit_t m_hit;
60	60	UINT32 m_timer_0_temp[4];
61	61	bitmap_ind16 m_sprite_bitmap;

trunk/src/mame/includes/namcos2.h
r32760	r32761
120	120	// game type helpers
121	121	bool is_system21();
122	122	int m_gametype;
123
	123
124	124	emu_timer *m_posirq_timer;
125	125	int m_mcu_analog_ctrl;
126	126	int m_mcu_analog_data;

trunk/src/mame/includes/tatsumi.h
r32760	r32761
39	39	required_device<okim6295_device> m_oki;
40	40	required_device<gfxdecode_device> m_gfxdecode;
41	41	required_device<palette_device> m_palette;
42
	42
43	43	optional_shared_ptr<UINT16> m_videoram;
44	44	optional_shared_ptr<UINT16> m_cyclwarr_cpua_ram;
45	45	optional_shared_ptr<UINT16> m_cyclwarr_cpub_ram;
r32760	r32761
58	58	optional_shared_ptr<UINT16> m_roundup_p_ram;
59	59	optional_shared_ptr<UINT16> m_roundup_l_ram;
60	60	required_shared_ptr<UINT16> m_spriteram;
61
	61
62	62	UINT16 m_bigfight_a20000[8];
63	63	UINT16 m_bigfight_a60000[2];
64	64	UINT16 m_bigfight_a40000[2];

trunk/src/mame/includes/meadows.h
r32760	r32761
24	24	m_videoram(*this, "videoram")
25	25	{
26	26	}
27
	27
28	28	required_device<s2650_device> m_maincpu;
29	29	optional_device<s2650_device> m_audiocpu;
30	30	optional_device<dac_device> m_dac;
r32760	r32761
35	35
36	36	optional_shared_ptr<UINT8> m_spriteram;
37	37	required_shared_ptr<UINT8> m_videoram;
38
	38
39	39	UINT8 m_dac_data;
40	40	int m_dac_enable;
41	41	int m_channel;

trunk/src/mame/includes/model1.h
r32760	r32761
36	36	required_shared_ptr<UINT16> m_display_list0;
37	37	required_shared_ptr<UINT16> m_display_list1;
38	38	required_shared_ptr<UINT16> m_color_xlat;
39
	39
40	40	struct view *m_view;
41	41	struct point *m_pointdb;
42	42	struct point *m_pointpt;
r32760	r32761
274	274	void sort_quads();
275	275	void unsort_quads();
276	276	void draw_quads(bitmap_rgb32 &bitmap, const rectangle &cliprect);
277		void fclip_push_quad_next(int level, struct quad_m1 q, struct point p1, struct point p2, struct point p3, struct point *p4);
	277	void fclip_push_quad_next(int level, struct quad_m1 q, struct point p1, struct point p2, struct point p3, struct point *p4);
278	278	void fclip_push_quad(int level, struct quad_m1 *q);
279	279	void push_object(UINT32 tex_adr, UINT32 poly_adr, UINT32 size);
280	280	UINT16 push_direct(UINT16 list);

trunk/src/mame/includes/micro3d.h
r32760	r32761
52	52	m_shared_ram(*this, "shared_ram"),
53	53	m_mac_sram(*this, "mac_sram"),
54	54	m_sprite_vram(*this, "sprite_vram") { }
55
	55
56	56	required_device<cpu_device> m_maincpu;
57	57	required_device<i8051_device> m_audiocpu;
58	58	required_device<upd7759_device> m_upd7759;
r32760	r32761
172	172	void rasterise_spans(UINT32 min_y, UINT32 max_y, UINT32 attr);
173	173	int clip_triangle(micro3d_vtx v, micro3d_vtx vout, int num_vertices, enum planes plane);
174	174	void draw_triangles(UINT32 attr);
175
176	175
	176
177	177	protected:
178	178	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
179	179	};

trunk/src/mame/includes/cosmic.h
r32760	r32761
31	31
32	32	/* video-related */
33	33	typedef pen_t (cosmic_state::*color_func)(UINT8 x, UINT8 y);
34		color_func m_map_color;
	34	color_func m_map_color;
35	35	int m_color_registers[3];
36	36	int m_background_enable;
37	37	int m_magspot_pen_mask;
r32760	r32761
54	54	optional_device<gfxdecode_device> m_gfxdecode;
55	55	required_device<screen_device> m_screen;
56	56	required_device<palette_device> m_palette;
57
	57
58	58	DECLARE_WRITE8_MEMBER(panic_sound_output_w);
59	59	DECLARE_WRITE8_MEMBER(panic_sound_output2_w);
60	60	DECLARE_WRITE8_MEMBER(cosmicg_output_w);

trunk/src/mame/includes/vectrex.h
r32760	r32761
57	57	m_io_lpenx(*this, "LPENX"),
58	58	m_io_lpeny(*this, "LPENY"),
59	59	m_io_coin(*this, "COIN"),
60		m_screen(*this, "screen")
	60	m_screen(*this, "screen")
61	61	{ }
62	62
63	63	required_shared_ptr<UINT8> m_gce_vectorram;

trunk/src/mame/includes/model3.h
r32760	r32761
94	94	required_shared_ptr<UINT64> m_work_ram;
95	95	required_shared_ptr<UINT64> m_paletteram64;
96	96	optional_device<dsbz80_device> m_dsbz80; // Z80-based MPEG Digital Sound Board
97		required_shared_ptr<UINT16> m_soundram;
	97	required_shared_ptr<UINT16> m_soundram;
98	98
99	99	required_device<gfxdecode_device> m_gfxdecode;
100	100	required_device<palette_device> m_palette;
r32760	r32761
261	261	DECLARE_DRIVER_INIT(spikeout);
262	262	DECLARE_DRIVER_INIT(magtruck);
263	263	DECLARE_DRIVER_INIT(lamachin);
264		DECLARE_DRIVER_INIT(model3_15);
	264	DECLARE_DRIVER_INIT(model3_15);
265	265	DECLARE_MACHINE_START(model3_10);
266	266	DECLARE_MACHINE_RESET(model3_10);
267	267	DECLARE_MACHINE_START(model3_15);

trunk/src/mame/includes/jpmimpct.h
r32760	r32761
106	106	DECLARE_READ8_MEMBER(hopper_c_r);
107	107	DECLARE_WRITE8_MEMBER(payen_a_w);
108	108	DECLARE_WRITE8_MEMBER(display_c_w);
109
	109
110	110	DECLARE_WRITE_LINE_MEMBER(tms_irq);
111	111	TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg);
112	112	TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg);
113	113	TMS340X0_SCANLINE_RGB32_CB_MEMBER(scanline_update);
114
	114
115	115	DECLARE_MACHINE_START(jpmimpct);
116	116	DECLARE_MACHINE_RESET(jpmimpct);
117	117	DECLARE_VIDEO_START(jpmimpct);

trunk/src/mame/includes/tnzs.h
r32760	r32761
85	85	DECLARE_WRITE8_MEMBER(kageki_csport_w);
86	86	DECLARE_WRITE8_MEMBER(kabukiz_sound_bank_w);
87	87	DECLARE_WRITE8_MEMBER(kabukiz_sample_w);
88
	88
89	89	DECLARE_READ8_MEMBER(tnzs_ramrom_bank_r);
90	90	DECLARE_WRITE8_MEMBER(tnzs_ramrom_bank_w);
91
	91
92	92	SAMPLES_START_CB_MEMBER(kageki_init_samples);
93	93
94	94	DECLARE_DRIVER_INIT(arknoid2);

trunk/src/mame/includes/sslam.h
r32760	r32761
16	16	m_regs(*this, "regs"),
17	17	m_spriteram(*this, "spriteram") { }
18	18
19
	19
20	20	required_device<cpu_device> m_maincpu;
21	21	required_device<cpu_device> m_audiocpu;
22	22	required_device<okim6295_device> m_oki;
r32760	r32761
28	28	optional_shared_ptr<UINT16> m_tx_tileram;
29	29	required_shared_ptr<UINT16> m_regs;
30	30	required_shared_ptr<UINT16> m_spriteram;
31
	31
32	32	emu_timer *m_music_timer;
33	33
34	34	int m_sound;

trunk/src/mame/includes/bfm_sc45.h
r32760	r32761
585	585	void bfm_sc4_68307_portb_w(address_space &space, bool dedicated, UINT16 data, UINT16 line_mask);
586	586	UINT8 bfm_sc4_68307_porta_r(address_space &space, bool dedicated, UINT8 line_mask);
587	587	UINT16 bfm_sc4_68307_portb_r(address_space &space, bool dedicated, UINT16 line_mask);
588
	588
589	589	void find_mbus(UINT16* rom);
590	590
591	591

trunk/src/mame/includes/8080bw.h
r32760	r32761
52	52	UINT8 m_schaser_background_disable;
53	53	UINT8 m_schaser_background_select;
54	54	UINT16 m_claybust_gun_pos;
55
	55
56	56	int m_invmulti_bank;
57	57
58	58

trunk/src/mame/includes/splash.h
r32760	r32761
18	18	m_msm2(*this, "msm2"),
19	19	m_gfxdecode(*this, "gfxdecode"),
20	20	m_palette(*this, "palette"),
21
	21
22	22	funystrp_val(0),
23	23	funystrp_ff3cc7_val(0),
24	24	funystrp_ff3cc8_val(0)

trunk/src/mame/includes/snk.h
r32760	r32761
26	26	required_device<gfxdecode_device> m_gfxdecode;
27	27	required_device<screen_device> m_screen;
28	28	required_device<palette_device> m_palette;
29
	29
30	30	required_shared_ptr<UINT8> m_spriteram;
31	31	optional_shared_ptr<UINT8> m_fg_videoram;
32	32	required_shared_ptr<UINT8> m_bg_videoram;
r32760	r32761
39	39	int m_marvins_sound_busy_flag;
40	40	// FIXME this should be initialised on machine reset
41	41	int m_sound_status;
42
	42
43	43	tilemap_t *m_tx_tilemap;
44	44	tilemap_t *m_fg_tilemap;
45	45	tilemap_t *m_bg_tilemap;
r32760	r32761
181	181	UINT32 screen_update_tnk3(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
182	182	UINT32 screen_update_ikari(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
183	183	UINT32 screen_update_gwar(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
184		UINT32 screen_update_tdfever(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	184	UINT32 screen_update_tdfever(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
185	185	TIMER_CALLBACK_MEMBER(sgladiat_sndirq_update_callback);
186	186	TIMER_CALLBACK_MEMBER(sndirq_update_callback);
187	187	DECLARE_WRITE_LINE_MEMBER(ymirq_callback_2);
188	188	void marvins_draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect, const int scrollx, const int scrolly, const int from, const int to);
189	189	void tnk3_draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect, const int xscroll, const int yscroll);
190	190	void ikari_draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect, const int start, const int xscroll, const int yscroll, const UINT8 *source, const int gfxnum );
191		void tdfever_draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect, const int xscroll, const int yscroll, const UINT8 *source, const int gfxnum, const int hw_xflip, const int from, const int to);
	191	void tdfever_draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect, const int xscroll, const int yscroll, const UINT8 *source, const int gfxnum, const int hw_xflip, const int from, const int to);
192	192	int hardflags_check(int num);
193	193	int hardflags_check8(int num);
194	194	int turbofront_check(int small, int num);

trunk/src/mame/includes/suna8.h
r32760	r32761
148	148	DECLARE_WRITE8_MEMBER(suna8_samples_number_w);
149	149	void play_sample(int index);
150	150	SAMPLES_START_CB_MEMBER(sh_start);
151
	151
152	152	void draw_normal_sprites(bitmap_ind16 &bitmap,const rectangle &cliprect, int which);
153	153	void draw_text_sprites(bitmap_ind16 &bitmap,const rectangle &cliprect);
154	154	UINT8 *brickzn_decrypt();

trunk/src/mame/includes/polyplay.h
r32760	r32761
16	16
17	17	required_shared_ptr<UINT8> m_videoram;
18	18	required_shared_ptr<UINT8> m_characterram;
19
	19
20	20	required_device<cpu_device> m_maincpu;
21	21	required_device<samples_device> m_samples;
22	22	required_device<gfxdecode_device> m_gfxdecode;
23	23	required_device<palette_device> m_palette;
24
	24
25	25	int m_freq1;
26	26	int m_freq2;
27	27	int m_channel_playing1;
r32760	r32761
35	35	int m_channel2_const;
36	36	timer_device* m_timer;
37	37	int m_last;
38
	38
39	39	DECLARE_WRITE8_MEMBER(polyplay_sound_channel);
40	40	DECLARE_WRITE8_MEMBER(polyplay_start_timer2);
41	41	DECLARE_READ8_MEMBER(polyplay_random_read);

trunk/src/mame/includes/harddriv.h
r32760	r32761
331	331	DECLARE_WRITE16_MEMBER( hdgsp_io_w );
332	332
333	333	DECLARE_WRITE16_MEMBER( hdgsp_protection_w );
334
	334
335	335	DECLARE_WRITE_LINE_MEMBER( hdgsp_irq_gen );
336	336	DECLARE_WRITE_LINE_MEMBER( hdmsp_irq_gen );
337	337
r32760	r32761
385	385
386	386	void hdds3sdsp_reset_timer();
387	387	void hdds3xdsp_reset_timer();
388
	388
389	389	TIMER_CALLBACK_MEMBER( xsdp_sport1_irq_off_callback );
390	390
391	391	/* DSK board */
r32760	r32761
441	441	/----------- defined in video/harddriv.c -----------/
442	442	TMS340X0_TO_SHIFTREG_CB_MEMBER(hdgsp_write_to_shiftreg);
443	443	TMS340X0_FROM_SHIFTREG_CB_MEMBER(hdgsp_read_from_shiftreg);
444
	444
445	445	void update_palette_bank(int newbank);
446
	446
447	447	DECLARE_READ16_MEMBER( hdgsp_control_lo_r );
448	448	DECLARE_WRITE16_MEMBER( hdgsp_control_lo_w );
449	449	DECLARE_READ16_MEMBER( hdgsp_control_hi_r );
r32760	r32761
454	454	DECLARE_WRITE16_MEMBER( hdgsp_vram_2bpp_w );
455	455
456	456	inline void gsp_palette_change(int offset);
457
	457
458	458	DECLARE_READ16_MEMBER( hdgsp_paletteram_lo_r );
459	459	DECLARE_WRITE16_MEMBER( hdgsp_paletteram_lo_w );
460	460	DECLARE_READ16_MEMBER( hdgsp_paletteram_hi_r );
r32760	r32761
466	466	/* DS III/IV board */
467	467	TIMER_DEVICE_CALLBACK_MEMBER( ds3sdsp_internal_timer_callback );
468	468	TIMER_DEVICE_CALLBACK_MEMBER( ds3xdsp_internal_timer_callback );
469
	469
470	470	TMS340X0_SCANLINE_IND16_CB_MEMBER(scanline_driver);
471	471	TMS340X0_SCANLINE_IND16_CB_MEMBER(scanline_multisync);
472	472	};

trunk/src/mame/includes/legionna.h
r32760	r32761
21	21	m_palette(*this, "palette"),
22	22	m_wordswapram(*this, "wordswapram"),
23	23	m_raiden2cop(*this, "raiden2cop")
24		{
	24	{
25	25	memset(scrollvals, 0, sizeof(UINT16)*6);
26	26	}
27	27
r32760	r32761
91	91	optional_device<raiden2cop_device> m_raiden2cop;
92	92
93	93	};
94
95

trunk/src/mame/includes/raiden2.h
r32760	r32761
13	13	mid_data(*this, "mid_data"),
14	14	text_data(*this, "text_data"),
15	15	*/
16		sprites(*this, "sprites") ,
17		m_maincpu(*this, "maincpu"),
18		m_seibu_sound(*this, "seibu_sound"),
19		m_gfxdecode(*this, "gfxdecode"),
20		m_palette(*this, "palette"),
21
22		bg_bank(0),
23		fg_bank(0),
24		mid_bank(0),
25		tx_bank(0),
26		raiden2_tilemap_enable(0),
27		prg_bank(0),
28		cop_bank(0),
	16	sprites(*this, "sprites") ,
	17	m_maincpu(*this, "maincpu"),
	18	m_seibu_sound(*this, "seibu_sound"),
	19	m_gfxdecode(*this, "gfxdecode"),
	20	m_palette(*this, "palette"),
29	21
30		sprite_prot_x(0),
31		sprite_prot_y(0),
32		dst1(0),
33		cop_spr_maxx(0),
34		cop_spr_off(0),
35
36		tile_buffer(320, 256),
37		sprite_buffer(320, 256),
38		m_raiden2cop(*this, "raiden2cop")
	22	bg_bank(0),
	23	fg_bank(0),
	24	mid_bank(0),
	25	tx_bank(0),
	26	raiden2_tilemap_enable(0),
	27	prg_bank(0),
	28	cop_bank(0),
	29
	30	sprite_prot_x(0),
	31	sprite_prot_y(0),
	32	dst1(0),
	33	cop_spr_maxx(0),
	34	cop_spr_off(0),
	35
	36	tile_buffer(320, 256),
	37	sprite_buffer(320, 256),
	38	m_raiden2cop(*this, "raiden2cop")
39	39	{
40	40	memset(scrollvals, 0, sizeof(UINT16)*6);
41	41	memset(sprite_prot_src_addr, 0, sizeof(UINT16)*2);
r32760	r32761
87	87	bool blend_active[0x800]; // cfg
88	88
89	89	tilemap_t background_layer,midground_layer,foreground_layer,text_layer;
90
91
	90
	91
92	92	int bg_bank, fg_bank, mid_bank, tx_bank;
93	93	UINT16 raiden2_tilemap_enable;
94	94	UINT8 prg_bank;

trunk/src/mame/includes/konamigx.h
r32760	r32761
155	155
156	156	void konamigx_esc_alert(UINT32 *srcbase, int srcoffs, int count, int mode);
157	157	void konamigx_precache_registers(void);
158
	158
159	159	void wipezbuf(int noshadow);
160	160
161	161	void dmastart_callback(int data);

trunk/src/mame/mame.mak
r32760	r32761
1210	1210	$(DRIVERS)/igs_m036.o \
1211	1211	$(DRIVERS)/iqblock.o $(VIDEO)/iqblock.o \
1212	1212	$(DRIVERS)/lordgun.o $(VIDEO)/lordgun.o \
1213		$(DRIVERS)/pgm.o $(VIDEO)/pgm.o $(MACHINE)/pgmprot_igs027a_type1.o $(MACHINE)/pgmprot_igs027a_type2.o $(MACHINE)/pgmprot_igs027a_type3.o $(MACHINE)/pgmprot_igs025_igs012.o $(MACHINE)/pgmprot_igs025_igs022.o $(MACHINE)/pgmprot_igs025_igs028.o $(MACHINE)/pgmprot_orlegend.o \
	1213	$(DRIVERS)/pgm.o $(VIDEO)/pgm.o $(MACHINE)/pgmprot_igs027a_type1.o $(MACHINE)/pgmprot_igs027a_type2.o $(MACHINE)/pgmprot_igs027a_type3.o $(MACHINE)/pgmprot_igs025_igs012.o $(MACHINE)/pgmprot_igs025_igs022.o $(MACHINE)/pgmprot_igs025_igs028.o $(MACHINE)/pgmprot_orlegend.o \
1214	1214	$(DRIVERS)/pgm2.o \
1215	1215	$(DRIVERS)/spoker.o \
1216	1216	$(MACHINE)/igs036crypt.o \

trunk/src/mame/video/dooyong.c
r32760	r32761
224	224	flags = ((attr & 0x02) ? TILE_FLIPX : 0) \| ((attr & 0x04) ? TILE_FLIPY : 0);
225	225	}
226	226	else
227		{
228
	227	{
229	228	/* primella */
230	229	/* Tiles take two bytes in ROM:
231	230	MSB LSB
r32760	r32761
237	236	Y = y flip */
238	237	int codemask = 0x03;
239	238	int palmask = 0x3c;
240
	239
241	240	if (m_gfxdecode->gfx(1)->depth() == 256) // pop bingo has an 8bpp layer and uses what would be the low palette bit to address more tiles (girls 4,5,6 in bonus game)
242	241	{
243	242	codemask = 0x07;

trunk/src/mame/video/snk.c
r32760	r32761
835	835	-xx-x--- (bank number)
836	836	x------- (x offset bit8)
837	837	*/
838		void snk_state::tdfever_draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect, const int xscroll, const int yscroll, const UINT8 *source, const int gfxnum,
	838	void snk_state::tdfever_draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect, const int xscroll, const int yscroll, const UINT8 *source, const int gfxnum,
839	839	const int hw_xflip, const int from, const int to)
840	840	{
841	841	gfx_element *gfx = m_gfxdecode->gfx(gfxnum);

trunk/src/mame/video/sknsspr.h
r32760	r32761
4	4	{
5	5	public:
6	6	sknsspr_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
7
	7
8	8	void skns_draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect, UINT32* spriteram_source, size_t spriteram_size, UINT8* gfx_source, size_t gfx_length, UINT32* sprite_regs);
9	9	void skns_sprite_kludge(int x, int y);
10	10

trunk/src/mame/video/battlera.c
r32760	r32761
1	1	// delete me
2

trunk/src/mame/video/fuukifg.c
r32760	r32761
1		/*
	1	/*
2	2	*/
3	3
4	4	#include "emu.h"
r32760	r32761
65	65
66	66	6.w Tile Code
67	67
68		for FG3 hardware
	68	for FG3 hardware
69	69
70	70	6.w fe-- ---- ---- ---- Tile Bank
71	71	--dc ba98 7654 3210 Tile Code
r32760	r32761
180	180	{
181	181	memcpy(m_sprram_old2, m_sprram_old, 0x2000);
182	182	memcpy(m_sprram_old, m_sprram, 0x2000);
183		}
		No newline at end of file
	183	}

trunk/src/mame/video/fuukifg.h
r32760	r32761
9	9
10	10	// static configuration
11	11	static void static_set_gfxdecode_tag(device_t &device, const char *tag);
12
	12
13	13	void draw_sprites(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect, int flip_screen, UINT32* tilebank);
14	14	UINT16* m_sprram;
15		UINT16* m_sprram_old;
	15	UINT16* m_sprram_old;
16	16	UINT16* m_sprram_old2;
17	17
18	18
r32760	r32761
25	25	{
26	26	return m_sprram[offset];
27	27	}
28
	28
29	29	void buffer_sprites(void);
30	30
31	31	protected:
r32760	r32761
40	40
41	41	#define MCFG_FUUKI_VIDEO_GFXDECODE(_gfxtag) \
42	42	fuukivid_device::static_set_gfxdecode_tag(*device, "^" _gfxtag);
43

trunk/src/mame/video/legionna.c
r32760	r32761
63	63
64	64	WRITE16_MEMBER(legionna_state::videowrite_cb_w)
65	65	{
66		// AM_RANGE(0x101000, 0x1017ff) AM_RAM // _WRITE(legionna_background_w) AM_SHARE("back_data")
67		// AM_RANGE(0x101800, 0x101fff) AM_RAM // _WRITE(legionna_foreground_w) AM_SHARE("fore_data")
68		// AM_RANGE(0x102000, 0x1027ff) AM_RAM // _WRITE(legionna_midground_w) AM_SHARE("mid_data")
69		// AM_RANGE(0x102800, 0x1037ff) AM_RAM // _WRITE(legionna_text_w) AM_SHARE("textram")
	66	// AM_RANGE(0x101000, 0x1017ff) AM_RAM // _WRITE(legionna_background_w) AM_SHARE("back_data")
	67	// AM_RANGE(0x101800, 0x101fff) AM_RAM // _WRITE(legionna_foreground_w) AM_SHARE("fore_data")
	68	// AM_RANGE(0x102000, 0x1027ff) AM_RAM // _WRITE(legionna_midground_w) AM_SHARE("mid_data")
	69	// AM_RANGE(0x102800, 0x1037ff) AM_RAM // _WRITE(legionna_text_w) AM_SHARE("textram")
70	70
71	71	if (offset < 0x800 / 2)
72	72	{
r32760	r32761
194	194
195	195	VIDEO_START_MEMBER(legionna_state,legionna)
196	196	{
197
198	197	m_back_data = auto_alloc_array_clear(machine(), UINT16, 0x800/2);
199	198	m_fore_data = auto_alloc_array_clear(machine(), UINT16, 0x800/2);
200	199	m_mid_data = auto_alloc_array_clear(machine(), UINT16, 0x800/2);
r32760	r32761
220	219
221	220	VIDEO_START_MEMBER(legionna_state,denjinmk)
222	221	{
223
224	222	m_back_data = auto_alloc_array_clear(machine(), UINT16, 0x800/2);
225	223	m_fore_data = auto_alloc_array_clear(machine(), UINT16, 0x800/2);
226	224	m_mid_data = auto_alloc_array_clear(machine(), UINT16, 0x800/2);
r32760	r32761
499	497
500	498	UINT32 legionna_state::screen_update_godzilla(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
501	499	{
502
503
504
505	500	bitmap.fill(0x0200, cliprect);
506	501	screen.priority().fill(0, cliprect);
507	502
r32760	r32761
521	516
522	517	UINT32 legionna_state::screen_update_grainbow(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
523	518	{
524
525
526	519	bitmap.fill(m_palette->black_pen(), cliprect);
527	520	screen.priority().fill(0, cliprect);
528	521

trunk/src/mame/video/decmxc06.h
r32760	r32761
16	16	void draw_sprites( bitmap_ind16 &bitmap, const rectangle &cliprect, UINT16* spriteram16, int pri_mask, int pri_val, int col_mask );
17	17	void draw_sprites_bootleg( bitmap_ind16 &bitmap, const rectangle &cliprect, UINT16* spriteram, int pri_mask, int pri_val, int col_mask );
18	18	void set_pri_type( int type ) { m_priority_type = type; }
19
	19
20	20	protected:
21	21	virtual void device_start();
22	22	virtual void device_reset();

trunk/src/mame/video/skyfox.c
r32760	r32761
173	173	for (dx = xstart; dx != xend; dx += xinc, code++)
174	174	{
175	175	gfx->transpen(bitmap, cliprect, code, 0, flipx, flipy, dx8 + x, dy8 + y, 0xff);
176
	176
177	177	// wraparound y - BTANB: large sprites exiting the screen sometimes reappear on the other edge
178	178	gfx->transpen(bitmap, cliprect, code, 0, flipx, flipy, dx8 + x, dy8 + y - 256, 0xff);
179	179	}

trunk/src/mame/video/taito_f3.c
r32760	r32761
1398	1398
1399	1399	/============================================================================/
1400	1400
1401		inline void taito_f3_state::draw_scanlines(
	1401	inline void taito_f3_state::draw_scanlines(
1402	1402	bitmap_rgb32 &bitmap,int xsize,INT16 *draw_line_num,
1403	1403	const struct f3_playfield_line_inf **line_t,
1404	1404	const int *sprite,

trunk/src/mame/video/fuukifg3.c
r32760	r32761
90	90
91	91	void fuuki32_state::video_start()
92	92	{
93		// m_buf_spriteram = auto_alloc_array(machine(), UINT32, m_spriteram.bytes() / 4);
94		// m_buf_spriteram2 = auto_alloc_array(machine(), UINT32, m_spriteram.bytes() / 4);
	93	// m_buf_spriteram = auto_alloc_array(machine(), UINT32, m_spriteram.bytes() / 4);
	94	// m_buf_spriteram2 = auto_alloc_array(machine(), UINT32, m_spriteram.bytes() / 4);
95	95
96	96
97	97

trunk/src/mame/video/tc0480scp.c
r32760	r32761
156	156	m_palette(*this)
157	157	{
158	158	memset(m_ctrl, 0, sizeof(m_ctrl));
159
	159
160	160	for (int i = 0; i < 4; i++)
161	161	{
162	162	m_bg_ram[i] = NULL;

trunk/src/mame/video/k054156_k054157_k056832.c
r32760	r32761
1269	1269	*/
1270	1270	{
1271	1271	bitmap_ind16 *pixmap;
1272
	1272
1273	1273	UINT8 code_transparent, code_opaque;
1274	1274	const pen_t *pal_ptr;
1275	1275	const UINT8 *src_ptr;

trunk/src/mame/video/mario.c
r32760	r32761
193	193
194	194	y = y ^ (m_flip ? 0xFF : 0x00); /* physical screen location */
195	195	x = x ^ (m_flip ? 0xFF : 0x00); /* physical screen location */
196
	196
197	197	code = m_spriteram[offs + 2];
198	198	color = (m_spriteram[offs + 1] & 0x0f) + 16 * m_palette_bank + 32 * m_monitor;
199	199	flipx = (m_spriteram[offs + 1] & 0x80);
r32760	r32761
216	216	x = m_spriteram[offs + 0];
217	217	y = 240 - y; /* logical screen position */
218	218
219		// y = y ^ (m_flip ? 0xFF : 0x00); /* physical screen location */
220		// x = x ^ (m_flip ? 0xFF : 0x00); /* physical screen location */
	219	// y = y ^ (m_flip ? 0xFF : 0x00); /* physical screen location */
	220	// x = x ^ (m_flip ? 0xFF : 0x00); /* physical screen location */
221	221
222	222	code = (m_spriteram[offs + 2] & 0x7f) \| ((m_spriteram[offs + 1] & 0x40) << 1); // upper tile bit is where the flipy bit goes on mario
223	223	color = (m_spriteram[offs + 1] & 0x0f) + 16 * m_palette_bank + 32 * m_monitor;
r32760	r32761
237	237	}
238	238	else
239	239	{
240
241	240	m_gfxdecode->gfx(1)->transpen(bitmap, cliprect,
242	241	code,
243	242	color,

trunk/src/mame/video/seibuspi.c
r32760	r32761
26	26	m_midl_layer_offset = 0x2000 / 4 / 2;
27	27	m_text_layer_offset = 0x3000 / 4 / 2;
28	28	}
29
	29
30	30	m_fore_layer_d13 = m_layer_bank >> 14 & 0x2000;
31	31	m_back_layer_d14 = m_rf2_layer_bank << 14 & 0x4000;
32	32	m_midl_layer_d14 = m_rf2_layer_bank << 13 & 0x4000;
r32760	r32761
657	657	m_rf2_layer_bank = 0;
658	658	m_rowscroll_enable = 0;
659	659	set_layer_offsets();
660
	660
661	661	m_tilemap_ram_size = 0;
662	662	m_palette_ram_size = 0x4000;
663	663	m_sprite_ram_size = 0x2000;

trunk/src/mame/video/model3.c
r32760	r32761
3	3	#include "video/rgbutil.h"
4	4	#include "includes/model3.h"
5	5
6		#define ENABLE_BILINEAR 1
	6	#define ENABLE_BILINEAR 1
7	7
8	8	#define TRI_PARAM_TEXTURE_PAGE 0x1
9	9	#define TRI_PARAM_TEXTURE_MIRROR_U 0x2
r32760	r32761
27	27	: poly_manager<float, model3_polydata, 6, 50000>(state.machine())//, m_state(state)
28	28	{
29	29	m_fb = auto_bitmap_rgb32_alloc(state.machine(), width, height);
30		m_zb = auto_bitmap_ind32_alloc(state.machine(), width, height);
	30	m_zb = auto_bitmap_ind32_alloc(state.machine(), width, height);
31	31	}
32	32
33	33	void draw(bitmap_rgb32 &bitmap, const rectangle &cliprect);
r32760	r32761
67	67	FILE* file;
68	68	int i;
69	69	file = fopen("m3_texture_ram.bin","wb");
70		for (i=0; i < 0x200000; i++)
71		{
72		fputc((UINT8)(m_texture_ram[0][i] >> 8), file);
73		fputc((UINT8)(m_texture_ram[0][i] >> 0), file);
74		}
75	70	for (i=0; i < 0x200000; i++)
76		{
77		fputc((UINT8)(m_texture_ram[1][i] >> 8), file);
78		fputc((UINT8)(m_texture_ram[1][i] >> 0), file);
79		}
80		fclose(file);
	71	{
	72	fputc((UINT8)(m_texture_ram[0][i] >> 8), file);
	73	fputc((UINT8)(m_texture_ram[0][i] >> 0), file);
	74	}
	75	for (i=0; i < 0x200000; i++)
	76	{
	77	fputc((UINT8)(m_texture_ram[1][i] >> 8), file);
	78	fputc((UINT8)(m_texture_ram[1][i] >> 0), file);
	79	}
	80	fclose(file);
81	81
82		file = fopen("m3_displist.bin","wb");
83		for (i=0; i < 0x40000; i++)
84		{
85		fputc((UINT8)(m_display_list_ram[i] >> 24), file);
86		fputc((UINT8)(m_display_list_ram[i] >> 16), file);
87		fputc((UINT8)(m_display_list_ram[i] >> 8), file);
88		fputc((UINT8)(m_display_list_ram[i] >> 0), file);
89		}
90		fclose(file);
	82	file = fopen("m3_displist.bin","wb");
	83	for (i=0; i < 0x40000; i++)
	84	{
	85	fputc((UINT8)(m_display_list_ram[i] >> 24), file);
	86	fputc((UINT8)(m_display_list_ram[i] >> 16), file);
	87	fputc((UINT8)(m_display_list_ram[i] >> 8), file);
	88	fputc((UINT8)(m_display_list_ram[i] >> 0), file);
	89	}
	90	fclose(file);
91	91
92	92	file = fopen("m3_culling_ram.bin","wb");
93		for (i=0; i < 0x100000; i++)
94		{
95		fputc((UINT8)(m_culling_ram[i] >> 24), file);
96		fputc((UINT8)(m_culling_ram[i] >> 16), file);
97		fputc((UINT8)(m_culling_ram[i] >> 8), file);
98		fputc((UINT8)(m_culling_ram[i] >> 0), file);
99		}
100		fclose(file);
	93	for (i=0; i < 0x100000; i++)
	94	{
	95	fputc((UINT8)(m_culling_ram[i] >> 24), file);
	96	fputc((UINT8)(m_culling_ram[i] >> 16), file);
	97	fputc((UINT8)(m_culling_ram[i] >> 8), file);
	98	fputc((UINT8)(m_culling_ram[i] >> 0), file);
	99	}
	100	fclose(file);
101	101
102	102	file = fopen("m3_polygon_ram.bin","wb");
103		for (i=0; i < 0x100000; i++)
104		{
105		fputc((UINT8)(m_polygon_ram[i] >> 24), file);
106		fputc((UINT8)(m_polygon_ram[i] >> 16), file);
107		fputc((UINT8)(m_polygon_ram[i] >> 8), file);
108		fputc((UINT8)(m_polygon_ram[i] >> 0), file);
109		}
110		fclose(file);
	103	for (i=0; i < 0x100000; i++)
	104	{
	105	fputc((UINT8)(m_polygon_ram[i] >> 24), file);
	106	fputc((UINT8)(m_polygon_ram[i] >> 16), file);
	107	fputc((UINT8)(m_polygon_ram[i] >> 8), file);
	108	fputc((UINT8)(m_polygon_ram[i] >> 0), file);
	109	}
	110	fclose(file);
111	111
112	112	file = fopen("m3_vrom.bin","wb");
113		for (i=0; i < 0x1000000; i++)
114		{
115		fputc((UINT8)(m_vrom[i] >> 24), file);
116		fputc((UINT8)(m_vrom[i] >> 16), file);
117		fputc((UINT8)(m_vrom[i] >> 8), file);
118		fputc((UINT8)(m_vrom[i] >> 0), file);
119		}
120		fclose(file);
	113	for (i=0; i < 0x1000000; i++)
	114	{
	115	fputc((UINT8)(m_vrom[i] >> 24), file);
	116	fputc((UINT8)(m_vrom[i] >> 16), file);
	117	fputc((UINT8)(m_vrom[i] >> 8), file);
	118	fputc((UINT8)(m_vrom[i] >> 0), file);
	119	}
	120	fclose(file);
121	121	#endif
122	122
123		// invalidate_texture(0, 0, 0, 6, 5);
124		// invalidate_texture(1, 0, 0, 6, 5);
	123	// invalidate_texture(0, 0, 0, 6, 5);
	124	// invalidate_texture(1, 0, 0, 6, 5);
125	125	}
126	126
127	127	void model3_state::video_start()
r32760	r32761
197	197	init_matrix_stack();
198	198	}
199	199
200		#define MODEL3_TILE_INFO4(address) \
	200	#define MODEL3_TILE_INFO4(address) \
201	201	do { \
202		UINT16 tiles = (UINT16)&m_m3_tile_ram[address + (tile_index / 4)]; \
	202	UINT16 tiles = (UINT16)&m_m3_tile_ram[address + (tile_index / 4)]; \
203	203	UINT16 t = BYTE_REVERSE16(tiles[(tile_index & 3) ^ NATIVE_ENDIAN_VALUE_LE_BE(2,0)]); \
204	204	int tile = ((t << 1) & 0x7ffe) \| ((t >> 15) & 0x1); \
205	205	int color = (t & 0x7ff0) >> 4; \
206	206	SET_TILE_INFO_MEMBER(0, tile, color, 0); \
207	207	} while (0)
208	208
209		#define MODEL3_TILE_INFO8(address) \
	209	#define MODEL3_TILE_INFO8(address) \
210	210	do { \
211		UINT16 tiles = (UINT16)&m_m3_tile_ram[address + (tile_index / 4)]; \
	211	UINT16 tiles = (UINT16)&m_m3_tile_ram[address + (tile_index / 4)]; \
212	212	UINT16 t = BYTE_REVERSE16(tiles[(tile_index & 3) ^ NATIVE_ENDIAN_VALUE_LE_BE(2,0)]); \
213	213	int tile = ((t << 1) & 0x7ffe) \| ((t >> 15) & 0x1); \
214	214	int color = (t & 0x7f00) >> 8; \
r32760	r32761
400	400	}
401	401
402	402	/*
403		Video registers:
	403	Video registers:
404	404
405		0xF1180000: ?
406		0xF1180004: ?
407		0xF1180008: ?
	405	0xF1180000: ?
	406	0xF1180004: ?
	407	0xF1180008: ?
408	408
409		0xF1180010: VBL IRQ acknowledge
	409	0xF1180010: VBL IRQ acknowledge
410	410
411		0xF1180020: -------- x------- -------- -------- Layer 3 bitdepth (0 = 8-bit, 1 = 4-bit)
412		-------- -x------ -------- -------- Layer 2 bitdepth (0 = 8-bit, 1 = 4-bit)
413		-------- --x----- -------- -------- Layer 1 bitdepth (0 = 8-bit, 1 = 4-bit)
414		-------- ---x---- -------- -------- Layer 0 bitdepth (0 = 8-bit, 1 = 4-bit)
415		-------- ----x--- -------- -------- Layer 3 priority (0 = below 3D, 1 = above 3D)
416		-------- -----x-- -------- -------- Layer 2 priority (0 = below 3D, 1 = above 3D)
417		-------- ------x- -------- -------- Layer 1 priority (0 = below 3D, 1 = above 3D)
418		-------- -------x -------- -------- Layer 0 priority (0 = below 3D, 1 = above 3D)
	411	0xF1180020: -------- x------- -------- -------- Layer 3 bitdepth (0 = 8-bit, 1 = 4-bit)
	412	-------- -x------ -------- -------- Layer 2 bitdepth (0 = 8-bit, 1 = 4-bit)
	413	-------- --x----- -------- -------- Layer 1 bitdepth (0 = 8-bit, 1 = 4-bit)
	414	-------- ---x---- -------- -------- Layer 0 bitdepth (0 = 8-bit, 1 = 4-bit)
	415	-------- ----x--- -------- -------- Layer 3 priority (0 = below 3D, 1 = above 3D)
	416	-------- -----x-- -------- -------- Layer 2 priority (0 = below 3D, 1 = above 3D)
	417	-------- ------x- -------- -------- Layer 1 priority (0 = below 3D, 1 = above 3D)
	418	-------- -------x -------- -------- Layer 0 priority (0 = below 3D, 1 = above 3D)
419	419
420		0xF1180040: Foreground layer color modulation?
421		-------- xxxxxxxx -------- -------- Red component
422		-------- -------- xxxxxxxx -------- Green component
423		-------- -------- -------- xxxxxxxx Blue component
	420	0xF1180040: Foreground layer color modulation?
	421	-------- xxxxxxxx -------- -------- Red component
	422	-------- -------- xxxxxxxx -------- Green component
	423	-------- -------- -------- xxxxxxxx Blue component
424	424
425		0xF1180044: Background layer color modulation?
426		-------- xxxxxxxx -------- -------- Red component
427		-------- -------- xxxxxxxx -------- Green component
428		-------- -------- -------- xxxxxxxx Blue component
	425	0xF1180044: Background layer color modulation?
	426	-------- xxxxxxxx -------- -------- Red component
	427	-------- -------- xxxxxxxx -------- Green component
	428	-------- -------- -------- xxxxxxxx Blue component
429	429
430		0xF1180060: x------- -------- -------- -------- Layer 0 enable
431		-------x xxxxxxxx -------- -------- Layer 0 Y scroll position
432		-------- -------- -------x xxxxxxxx Layer 0 X scroll position
	430	0xF1180060: x------- -------- -------- -------- Layer 0 enable
	431	-------x xxxxxxxx -------- -------- Layer 0 Y scroll position
	432	-------- -------- -------x xxxxxxxx Layer 0 X scroll position
433	433
434		0xF1180064: x------- -------- -------- -------- Layer 1 enable
435		-------x xxxxxxxx -------- -------- Layer 1 Y scroll position
436		-------- -------- -------x xxxxxxxx Layer 1 X scroll position
	434	0xF1180064: x------- -------- -------- -------- Layer 1 enable
	435	-------x xxxxxxxx -------- -------- Layer 1 Y scroll position
	436	-------- -------- -------x xxxxxxxx Layer 1 X scroll position
437	437
438		0xF1180068: x------- -------- -------- -------- Layer 2 enable
439		-------x xxxxxxxx -------- -------- Layer 2 Y scroll position
440		-------- -------- -------x xxxxxxxx Layer 2 X scroll position
	438	0xF1180068: x------- -------- -------- -------- Layer 2 enable
	439	-------x xxxxxxxx -------- -------- Layer 2 Y scroll position
	440	-------- -------- -------x xxxxxxxx Layer 2 X scroll position
441	441
442		0xF118006C: x------- -------- -------- -------- Layer 3 enable
443		-------x xxxxxxxx -------- -------- Layer 3 Y scroll position
444		-------- -------- -------x xxxxxxxx Layer 3 X scroll position
	442	0xF118006C: x------- -------- -------- -------- Layer 3 enable
	443	-------x xxxxxxxx -------- -------- Layer 3 Y scroll position
	444	-------- -------- -------x xxxxxxxx Layer 3 X scroll position
445	445	*/
446	446
447	447
r32760	r32761
634	634	/* Real3D Graphics stuff */
635	635
636	636	/*
637		Real3D Pro-1000 capabilities:
	637	Real3D Pro-1000 capabilities:
638	638
639		Coordinate sets
640		- 4096 matrices (matrix base pointer in viewport node)
	639	Coordinate sets
	640	- 4096 matrices (matrix base pointer in viewport node)
641	641
642		Polygons
643		- 32MB max polygon memory. VROM in Model 3, the low 4MB of VROM is overlaid by Polygon RAM for runtime generated content.
	642	Polygons
	643	- 32MB max polygon memory. VROM in Model 3, the low 4MB of VROM is overlaid by Polygon RAM for runtime generated content.
644	644
645		Texture
646		- 2 texture sheets of 2048x1024
647		- Mipmaps located in the bottom right corner
648		- Texture size 32x32 to 1024x1024
649		- Microtextures (is this featured in Model 3?)
	645	Texture
	646	- 2 texture sheets of 2048x1024
	647	- Mipmaps located in the bottom right corner
	648	- Texture size 32x32 to 1024x1024
	649	- Microtextures (is this featured in Model 3?)
650	650
651		LODs
652		- 127 blend types per viewport with 4 sets of min/max angle or range (where is this in the viewport node?)
	651	LODs
	652	- 127 blend types per viewport with 4 sets of min/max angle or range (where is this in the viewport node?)
653	653
654		Lighting
655		- Self-luminous lighting (enable and luminosity parameter in polygon structure)
656		- Fixed polygon shading, fixed shading weight per vertex (not found in Model 3, yet)
657		- Flat sun shading (lighting parameters in viewport node) needs a separate enable?
658		- Smooth polygon shading (lighting parameters in viewport, use vertex normals)
	654	Lighting
	655	- Self-luminous lighting (enable and luminosity parameter in polygon structure)
	656	- Fixed polygon shading, fixed shading weight per vertex (not found in Model 3, yet)
	657	- Flat sun shading (lighting parameters in viewport node) needs a separate enable?
	658	- Smooth polygon shading (lighting parameters in viewport, use vertex normals)
659	659
660		Gamma table
661		- 256 entry 8-bit table, possibly in Polygon RAM
	660	Gamma table
	661	- 256 entry 8-bit table, possibly in Polygon RAM
662	662	*/
663	663
664	664	/*
665		Real3D Memory Structures:
666
667		Culling Nodes:
668		- Located in Culling RAM (0x8E000000)
669		- Limit of 15 child nodes (nesting), not including polygon nodes
670		- Color table (is this featured in Model 3?)
	665	Real3D Memory Structures:
671	666
672		0x00: -------- -------- ------xx -------- Viewport number 0-3
673		-------- -------- -------- ---xx--- Viewport priority
	667	Culling Nodes:
	668	- Located in Culling RAM (0x8E000000)
	669	- Limit of 15 child nodes (nesting), not including polygon nodes
	670	- Color table (is this featured in Model 3?)
674	671
675		0x01: Child node pointer (inherits parameters from this node)
676		0x02: Sibling node pointer
677		0x03: Unknown (float)
678		0x04: Sun light vector Z-component (float)
679		0x05: Sun light vector X-component (float)
680		0x06: Sun light vector Y-component (float)
681		0x07: Sun light intensity (float)
682		0x08: Far Clip plane Z
683		0x09: Far Clip plane Distance
684		0x0a: Near Clip plane Z
685		0x0b: Near Clip plane Distance
686		0x0c: Left Clip plane Z
687		0x0d: Left Clip plane X
688		0x0e: Top Clip plane Z
689		0x0f: Top Clip plane Y
690		0x10: Right Clip plane Z
691		0x11: Right Clip plane X
692		0x12: Bottom Clip plane Z
693		0x13: Bottom Clip plane Y
	672	0x00: -------- -------- ------xx -------- Viewport number 0-3
	673	-------- -------- -------- ---xx--- Viewport priority
694	674
695		0x14: xxxxxxxx xxxxxxxx -------- -------- Viewport height (14.2 fixed-point)
696		-------- -------- xxxxxxxx xxxxxxxx Viewport width (14.2 fixed-point)
	675	0x01: Child node pointer (inherits parameters from this node)
	676	0x02: Sibling node pointer
	677	0x03: Unknown (float)
	678	0x04: Sun light vector Z-component (float)
	679	0x05: Sun light vector X-component (float)
	680	0x06: Sun light vector Y-component (float)
	681	0x07: Sun light intensity (float)
	682	0x08: Far Clip plane Z
	683	0x09: Far Clip plane Distance
	684	0x0a: Near Clip plane Z
	685	0x0b: Near Clip plane Distance
	686	0x0c: Left Clip plane Z
	687	0x0d: Left Clip plane X
	688	0x0e: Top Clip plane Z
	689	0x0f: Top Clip plane Y
	690	0x10: Right Clip plane Z
	691	0x11: Right Clip plane X
	692	0x12: Bottom Clip plane Z
	693	0x13: Bottom Clip plane Y
697	694
698		0x15: ?
699		0x16: Matrix base pointer
700		0x17: LOD blend type table pointer? (seems to be 8x float per entry)
701		0x18: ?
702		0x19: ?
	695	0x14: xxxxxxxx xxxxxxxx -------- -------- Viewport height (14.2 fixed-point)
	696	-------- -------- xxxxxxxx xxxxxxxx Viewport width (14.2 fixed-point)
703	697
704		0x1a: xxxxxxxx xxxxxxxx -------- -------- Viewport Y coordinate (12.4 fixed-point)
705		-------- -------- xxxxxxxx xxxxxxxx Viewport X coordinate (12.4 fixed-point)
	698	0x15: ?
	699	0x16: Matrix base pointer
	700	0x17: LOD blend type table pointer? (seems to be 8x float per entry)
	701	0x18: ?
	702	0x19: ?
706	703
707		0x1b: Copy of word 0x00
708		0x1c: ?
	704	0x1a: xxxxxxxx xxxxxxxx -------- -------- Viewport Y coordinate (12.4 fixed-point)
	705	-------- -------- xxxxxxxx xxxxxxxx Viewport X coordinate (12.4 fixed-point)
709	706
710		0x1d: xxxxxxxx xxxxxxxx -------- -------- Spotlight Y size
711		-------- -------- xxxxxxxx xxxxxxxx Spotlight Y position (13.3 fixed-point?)
	707	0x1b: Copy of word 0x00
	708	0x1c: ?
712	709
713		0x1e: xxxxxxxx xxxxxxxx -------- -------- Spotlight X size
714		-------- -------- xxxxxxxx xxxxxxxx Spotlight X position (13.3 fixed-point?)
	710	0x1d: xxxxxxxx xxxxxxxx -------- -------- Spotlight Y size
	711	-------- -------- xxxxxxxx xxxxxxxx Spotlight Y position (13.3 fixed-point?)
715	712
716		0x1f: Light extent (float)
	713	0x1e: xxxxxxxx xxxxxxxx -------- -------- Spotlight X size
	714	-------- -------- xxxxxxxx xxxxxxxx Spotlight X position (13.3 fixed-point?)
717	715
718		0x20: xxxxxxxx -------- -------- -------- ?
719		-------- xxxxxxxx -------- -------- ?
720		-------- -------- --xxx--- -------- Light RGB (RGB111?)
721		-------- -------- -----xxx -------- Light RGB Fog (RGB111?)
722		-------- -------- -------- xxxxxxxx Scroll Fog (0.8 fixed-point?) What is this???
	716	0x1f: Light extent (float)
723	717
724		0x21: ?
725		0x22: Fog Color (RGB888)
726		0x23: Fog Density (float)
	718	0x20: xxxxxxxx -------- -------- -------- ?
	719	-------- xxxxxxxx -------- -------- ?
	720	-------- -------- --xxx--- -------- Light RGB (RGB111?)
	721	-------- -------- -----xxx -------- Light RGB Fog (RGB111?)
	722	-------- -------- -------- xxxxxxxx Scroll Fog (0.8 fixed-point?) What is this???
727	723
728		0x24: xxxxxxxx xxxxxxxx -------- -------- ?
729		-------- -------- xxxxxxxx -------- Sun light ambient (0.8 fixed-point)
730		-------- -------- -------- xxxxxxxx Scroll attenuation (0.8 fixed-point) What is this???
	724	0x21: ?
	725	0x22: Fog Color (RGB888)
	726	0x23: Fog Density (float)
731	727
732		0x25: Fog offset
733		0x26: ?
734		0x27: ?
735		0x28: ?
736		0x29: ?
737		0x2a: ?
738		0x2b: ?
739		0x2c: ?
740		0x2d: ?
741		0x2e: ?
742		0x2f: ?
	728	0x24: xxxxxxxx xxxxxxxx -------- -------- ?
	729	-------- -------- xxxxxxxx -------- Sun light ambient (0.8 fixed-point)
	730	-------- -------- -------- xxxxxxxx Scroll attenuation (0.8 fixed-point) What is this???
743	731
	732	0x25: Fog offset
	733	0x26: ?
	734	0x27: ?
	735	0x28: ?
	736	0x29: ?
	737	0x2a: ?
	738	0x2b: ?
	739	0x2c: ?
	740	0x2d: ?
	741	0x2e: ?
	742	0x2f: ?
744	743
745		Sub types:
746		LOD Culling Node. Up to 4 LODs.
747	744
748		Articulated Part Culling Node (is this used by Model 3?)
749		- An Articulated Part culling node, or six degreeoffreedom node, is used to define
	745	Sub types:
	746	LOD Culling Node. Up to 4 LODs.
	747
	748	Articulated Part Culling Node (is this used by Model 3?)
	749	- An Articulated Part culling node, or six degree?of?freedom node, is used to define
750	750	geometry that can move relative to the parent coordinate set to which it is attached.
751	751	Fifteen levels of coordinate set nesting (levels of articulation) are supported.
752
753		Animation Culling Node
754		- Animation culling nodes are used to build a culling hierarchy for an object with different
	752
	753	Animation Culling Node
	754	- Animation culling nodes are used to build a culling hierarchy for an object with different
755	755	representations, or animation frames. which can be turned on and off by the
756	756	application. Each child (culling node or polygon) added to an Animation culling node
757	757	specifies the frame for which the child is valid.
758
759		Instance Culling Node
760		- Instance culling nodes define the top of a shared display list segment that can be
761		referenced from other parts of the scene display list.
762	758
763		Instance Reference Culling Node
764		- An Instance Reference node is considered a leaf node; its
765		"child" is the shared geometry segment. An Instance Reference may be attached to
766		a parent node and may not have any other children, but may have siblings.
	759	Instance Culling Node
	760	- Instance culling nodes define the top of a shared display list segment that can be
	761	referenced from other parts of the scene display list.
767	762
768		Point Light
769		- A Point Light is used to create an instance of a point luminous feature. The size,
	763	Instance Reference Culling Node
	764	- An Instance Reference node is considered a leaf node; its
	765	"child" is the shared geometry segment. An Instance Reference may be attached to
	766	a parent node and may not have any other children, but may have siblings.
	767
	768	Point Light
	769	- A Point Light is used to create an instance of a point luminous feature. The size,
770	770	feature type, and number of sides of the point light model may be customized.
771	771
772		Instance Set
773		- An Instance Set is a culling node which defines a set of point features. Each feature
	772	Instance Set
	773	- An Instance Set is a culling node which defines a set of point features. Each feature
774	774	is positioned individually. This type of culling node can be used to simulate particles.
775	775
776	776
777	777
778		Instance Node?
	778	Instance Node?
779	779
780		0x00: xxxxxxxx xxxxxxxx xxxxxx-- -------- Node number/ID?, num of bits unknown
781		-------- -------- -------- ---x---- This node applies translation, else matrix
782		-------- -------- -------- ----x--- LOD enable?
783		-------- -------- -------- -----x-- ?
784		-------- -------- -------- ------x- ?
785		-------- -------- -------- -------x ?
	780	0x00: xxxxxxxx xxxxxxxx xxxxxx-- -------- Node number/ID?, num of bits unknown
	781	-------- -------- -------- ---x---- This node applies translation, else matrix
	782	-------- -------- -------- ----x--- LOD enable?
	783	-------- -------- -------- -----x-- ?
	784	-------- -------- -------- ------x- ?
	785	-------- -------- -------- -------x ?
786	786
787
788		0x01: ? (not present on Step 1.0)
789		0x02: ? (not present on Step 1.0) Scud Race has 0x00000101
790	787
791		0x03: --x----- -------- -------- -------- ?
792		-------- -xxxxxxx xxxx---- -------- LOD?
793		-------- -------- ----xxxx xxxxxxxx Node matrix
794
795		0x04: Translation X coordinate
796		0x05: Translation Y coordinate
797		0x06: Translation Z coordinate
798		0x07: Child node pointer
799		0x08: Sibling node pointer
	788	0x01: ? (not present on Step 1.0)
	789	0x02: ? (not present on Step 1.0) Scud Race has 0x00000101
800	790
801		0x09: xxxxxxxx xxxxxxxx -------- -------- Culling or sorting related?
802		-------- -------- xxxxxxxx xxxxxxxx Culling or sorting related?
	791	0x03: --x----- -------- -------- -------- ?
	792	-------- -xxxxxxx xxxx---- -------- LOD?
	793	-------- -------- ----xxxx xxxxxxxx Node matrix
803	794
	795	0x04: Translation X coordinate
	796	0x05: Translation Y coordinate
	797	0x06: Translation Z coordinate
	798	0x07: Child node pointer
	799	0x08: Sibling node pointer
804	800
805		Polygon Data
	801	0x09: xxxxxxxx xxxxxxxx -------- -------- Culling or sorting related?
	802	-------- -------- xxxxxxxx xxxxxxxx Culling or sorting related?
806	803
807		0x00: -------- xxxxxxxx xxxxxx-- -------- Polygon ID
808		-------- -------- -------- -x------ 0 = Triangle, 1 = Quad
809		-------- -------- -------- ----x--- Vertex 3 shared from previous polygon
810		-------- -------- -------- -----x-- Vertex 2 shared from previous polygon
811		-------- -------- -------- ------x- Vertex 1 shared from previous polygon
812		-------- -------- -------- -------x Vertex 0 shared from previous polygon
813		xxxxxxxx -------- -------- x-xx---- ?
814		-------- -------- ------xx -------- Broken polygons in srally2 set these (a way to mark them for HW to not render?)
815	804
816		0x01: xxxxxxxx xxxxxxxx xxxxxxxx -------- Polygon normal X coordinate (2.22 fixed point)
817		-------- -------- -------- -x------ UV format (0 = 13.3, 1 = 16.0)
818		-------- -------- -------- -----x-- If set, this is the last polygon
819		-------- -------- -------- x-xxx-xx ?
	805	Polygon Data
820	806
821		0x02: xxxxxxxx xxxxxxxx xxxxxxxx -------- Polygon normal Y coordinate (2.22 fixed point)
822		-------- -------- -------- ------x- Texture U mirror enable
823		-------- -------- -------- -------x Texture V mirror enable
824		-------- -------- -------- xxxxxx-- ?
	807	0x00: -------- xxxxxxxx xxxxxx-- -------- Polygon ID
	808	-------- -------- -------- -x------ 0 = Triangle, 1 = Quad
	809	-------- -------- -------- ----x--- Vertex 3 shared from previous polygon
	810	-------- -------- -------- -----x-- Vertex 2 shared from previous polygon
	811	-------- -------- -------- ------x- Vertex 1 shared from previous polygon
	812	-------- -------- -------- -------x Vertex 0 shared from previous polygon
	813	xxxxxxxx -------- -------- x-xx---- ?
	814	-------- -------- ------xx -------- Broken polygons in srally2 set these (a way to mark them for HW to not render?)
825	815
826		0x03: xxxxxxxx xxxxxxxx xxxxxxxx -------- Polygon normal Z coordinate (2.22 fixed point)
827		-------- -------- -------- --xxx--- Texture width (in 8-pixel tiles)
828		-------- -------- -------- -----xxx Texture height (in 8-pixel tiles)
	816	0x01: xxxxxxxx xxxxxxxx xxxxxxxx -------- Polygon normal X coordinate (2.22 fixed point)
	817	-------- -------- -------- -x------ UV format (0 = 13.3, 1 = 16.0)
	818	-------- -------- -------- -----x-- If set, this is the last polygon
	819	-------- -------- -------- x-xxx-xx ?
829	820
830		0x04: xxxxxxxx xxxxxxxx xxxxxxxx -------- Color (RGB888)
831		-------- -------- -------- -x------ Texture page
832		-------- -------- -------- ---xxxxx Upper 5 bits of texture U coordinate
833		-------- -------- -------- x-x----- ?
	821	0x02: xxxxxxxx xxxxxxxx xxxxxxxx -------- Polygon normal Y coordinate (2.22 fixed point)
	822	-------- -------- -------- ------x- Texture U mirror enable
	823	-------- -------- -------- -------x Texture V mirror enable
	824	-------- -------- -------- xxxxxx-- ?
834	825
835		0x05: xxxxxxxx xxxxxxxx xxxxxxxx -------- Specular color?
836		-------- -------- -------- x------- Low bit of texture U coordinate
837		-------- -------- -------- ---xxxxx Low 5 bits of texture V coordinate
838		-------- -------- -------- -xx----- ?
	826	0x03: xxxxxxxx xxxxxxxx xxxxxxxx -------- Polygon normal Z coordinate (2.22 fixed point)
	827	-------- -------- -------- --xxx--- Texture width (in 8-pixel tiles)
	828	-------- -------- -------- -----xxx Texture height (in 8-pixel tiles)
839	829
840		0x06: x------- -------- -------- -------- Texture contour enable
841		-----x-- -------- -------- -------- Texture enable
842		-------- x------- -------- -------- 1 = disable transparency?
843		-------- -xxxxx-- -------- -------- Polygon transparency (0 = fully transparent)
844		-------- -------x -------- -------- 1 = disable lighting
845		-------- -------- xxxxx--- -------- Polygon luminosity
846		-------- -------- ------xx x------- Texture format
847		-------- -------- -------- -------x Alpha enable?
848		-xxxx-xx ------x- -----x-- -xxxxxx- ?
	830	0x04: xxxxxxxx xxxxxxxx xxxxxxxx -------- Color (RGB888)
	831	-------- -------- -------- -x------ Texture page
	832	-------- -------- -------- ---xxxxx Upper 5 bits of texture U coordinate
	833	-------- -------- -------- x-x----- ?
849	834
	835	0x05: xxxxxxxx xxxxxxxx xxxxxxxx -------- Specular color?
	836	-------- -------- -------- x------- Low bit of texture U coordinate
	837	-------- -------- -------- ---xxxxx Low 5 bits of texture V coordinate
	838	-------- -------- -------- -xx----- ?
850	839
851		Vertex entry
	840	0x06: x------- -------- -------- -------- Texture contour enable
	841	-----x-- -------- -------- -------- Texture enable
	842	-------- x------- -------- -------- 1 = disable transparency?
	843	-------- -xxxxx-- -------- -------- Polygon transparency (0 = fully transparent)
	844	-------- -------x -------- -------- 1 = disable lighting
	845	-------- -------- xxxxx--- -------- Polygon luminosity
	846	-------- -------- ------xx x------- Texture format
	847	-------- -------- -------- -------x Alpha enable?
	848	-xxxx-xx ------x- -----x-- -xxxxxx- ?
852	849
853		0x00: xxxxxxxx xxxxxxxx xxxxxxxx -------- Vertex X coordinate (17.7 fixed-point in Step 1.0, 13.11 otherwise)
854		-------- -------- -------- xxxxxxxx Vertex normal X (offset from polygon normal)
855	850
856		0x01: xxxxxxxx xxxxxxxx xxxxxxxx -------- Vertex Y coordinate
857		-------- -------- -------- xxxxxxxx Vertex normal Y
	851	Vertex entry
858	852
859		0x02: xxxxxxxx xxxxxxxx xxxxxxxx -------- Vertex Z coordinate
860		-------- -------- -------- xxxxxxxx Vertex normal Z
	853	0x00: xxxxxxxx xxxxxxxx xxxxxxxx -------- Vertex X coordinate (17.7 fixed-point in Step 1.0, 13.11 otherwise)
	854	-------- -------- -------- xxxxxxxx Vertex normal X (offset from polygon normal)
861	855
862		0x03: xxxxxxxx xxxxxxxx -------- -------- Vertex U coordinate
863		-------- -------- xxxxxxxx xxxxxxxx Vertex V coordinate
	856	0x01: xxxxxxxx xxxxxxxx xxxxxxxx -------- Vertex Y coordinate
	857	-------- -------- -------- xxxxxxxx Vertex normal Y
864	858
	859	0x02: xxxxxxxx xxxxxxxx xxxxxxxx -------- Vertex Z coordinate
	860	-------- -------- -------- xxxxxxxx Vertex normal Z
	861
	862	0x03: xxxxxxxx xxxxxxxx -------- -------- Vertex U coordinate
	863	-------- -------- xxxxxxxx xxxxxxxx Vertex V coordinate
	864
865	865	*/
866	866
867	867
r32760	r32761
891	891
892	892	static const UINT8 texture_decode[64] =
893	893	{
894		0, 1, 4, 5, 8, 9, 12, 13,
895		2, 3, 6, 7, 10, 11, 14, 15,
	894	0, 1, 4, 5, 8, 9, 12, 13,
	895	2, 3, 6, 7, 10, 11, 14, 15,
896	896	16, 17, 20, 21, 24, 25, 28, 29,
897	897	18, 19, 22, 23, 26, 27, 30, 31,
898	898	32, 33, 36, 37, 40, 41, 44, 45,
r32760	r32761
1003	1003	m_texture_fifo_pos = 0;
1004	1004
1005	1005	m_renderer->clear_buffers();
1006
1007		real3d_traverse_display_list();
	1006
	1007	real3d_traverse_display_list();
1008	1008	}
1009	1009
1010	1010	void model3_state::real3d_display_list1_dma(UINT32 src, UINT32 dst, int length, int byteswap)
r32760	r32761
1041	1041
1042	1042	void model3_state::real3d_vrom_texture_dma(UINT32 src, UINT32 dst, int length, int byteswap)
1043	1043	{
1044		address_space &space = m_maincpu->space(AS_PROGRAM);
	1044	address_space &space = m_maincpu->space(AS_PROGRAM);
1045	1045	if ((dst & 0xff) == 0)
1046	1046	{
1047	1047	for (int i=0; i < length; i+=12)
r32760	r32761
1286	1286	MATRIX transform_matrix;
1287	1287	float center_x, center_y;
1288	1288
1289		if (m_step < 0x15) // position coordinates are 17.7 fixed-point in Step 1.0
	1289	if (m_step < 0x15) // position coordinates are 17.7 fixed-point in Step 1.0
1290	1290	fixed_point_fraction = 1.0f / 128.0f;
1291		else // 13.11 fixed-point in other Steps
	1291	else // 13.11 fixed-point in other Steps
1292	1292	fixed_point_fraction = 1.0f / 2048.0f;
1293
	1293
1294	1294	get_top_matrix(&transform_matrix);
1295	1295
1296	1296	/* current viewport center coordinates on screen */
r32760	r32761
1323	1323	if (header[1] & 0x4)
1324	1324	last_polygon = TRUE;
1325	1325
1326		if ((header[0] & 0x300) == 0x300) // TODO: broken polygons in srally2 have these bits set
	1326	if ((header[0] & 0x300) == 0x300) // TODO: broken polygons in srally2 have these bits set
1327	1327	return;
1328	1328
1329	1329	num_vertices = (header[0] & 0x40) ? 4 : 3;
r32760	r32761
1354	1354	vertex[vi].z = (float)((INT32)(zw) >> 8) * fixed_point_fraction;
1355	1355	vertex[vi].u = (UINT16)(model[index] >> 16);
1356	1356	vertex[vi].v = (UINT16)(model[index++]);
1357		// vertex[vi].nx = normal[0] + ((float)((INT8)(xw)) / 127.0f);
1358		// vertex[vi].ny = normal[1] + ((float)((INT8)(yw)) / 127.0f);
1359		// vertex[vi].nz = normal[2] + ((float)((INT8)(zw)) / 127.0f);
	1357	// vertex[vi].nx = normal[0] + ((float)((INT8)(xw)) / 127.0f);
	1358	// vertex[vi].ny = normal[1] + ((float)((INT8)(yw)) / 127.0f);
	1359	// vertex[vi].nz = normal[2] + ((float)((INT8)(zw)) / 127.0f);
1360	1360
1361	1361	vertex[vi].nx = ((float)((INT8)(xw)) / 127.0f);
1362	1362	vertex[vi].ny = ((float)((INT8)(yw)) / 127.0f);
r32760	r32761
1408	1408	// transform vertex normal
1409	1409	VECTOR3 n;
1410	1410	n[0] = (vertex[i].nx * transform_matrix[0][0]) +
1411		(vertex[i].ny * transform_matrix[1][0]) +
1412		(vertex[i].nz * transform_matrix[2][0]);
	1411	(vertex[i].ny * transform_matrix[1][0]) +
	1412	(vertex[i].nz * transform_matrix[2][0]);
1413	1413	n[0] *= m_coordinate_system[0][1];
1414	1414	n[1] = (vertex[i].nx * transform_matrix[0][1]) +
1415		(vertex[i].ny * transform_matrix[1][1]) +
1416		(vertex[i].nz * transform_matrix[2][1]);
	1415	(vertex[i].ny * transform_matrix[1][1]) +
	1416	(vertex[i].nz * transform_matrix[2][1]);
1417	1417	n[1] *= m_coordinate_system[1][2];
1418	1418	n[2] = (vertex[i].nx * transform_matrix[0][2]) +
1419		(vertex[i].ny * transform_matrix[1][2]) +
1420		(vertex[i].nz * transform_matrix[2][2]);
	1419	(vertex[i].ny * transform_matrix[1][2]) +
	1420	(vertex[i].nz * transform_matrix[2][2]);
1421	1421	n[2] *= m_coordinate_system[2][0];
1422	1422
1423	1423	// lighting
r32760	r32761
1484	1484	int tex_height = (header[3] & 0x7);
1485	1485	int tex_format = (header[6] >> 7) & 0x7;
1486	1486
1487		if (tex_width >= 6 \|\| tex_height >= 6) // srally2 poly ram has degenerate polys with 2k tex size (cpu bug or intended?)
	1487	if (tex_width >= 6 \|\| tex_height >= 6) // srally2 poly ram has degenerate polys with 2k tex size (cpu bug or intended?)
1488	1488	return;
1489	1489
1490	1490	texture = get_texture((header[4] & 0x40) ? 1 : 0, tex_x, tex_y, tex_width, tex_height, tex_format);
r32760	r32761
1761	1761	cliprect.max_y = 383;
1762	1762
1763	1763	m_fb->fill(0x00000000, cliprect);
1764
	1764
1765	1765	float zvalue = 10000000000.0f;
1766	1766	m_zb->fill((int)&zvalue, cliprect);
1767	1767	}
r32760	r32761
1779	1779	if (tri->param & TRI_PARAM_TEXTURE_ENABLE)
1780	1780	{
1781	1781	for (int i=0; i < 3; i++)
1782		{
	1782	{
1783	1783	v[i].x = tri->v[i].x;
1784	1784	v[i].y = tri->v[i].y;
1785	1785	v[i].p[0] = tri->v[i].z;
1786	1786	v[i].p[1] = 1.0f / tri->v[i].z;
1787		v[i].p[2] = tri->v[i].u * 256.0f; // 8 bits of subtexel precision for bilinear filtering
	1787	v[i].p[2] = tri->v[i].u * 256.0f; // 8 bits of subtexel precision for bilinear filtering
1788	1788	v[i].p[3] = tri->v[i].v * 256.0f;
1789		v[i].p[4] = tri->v[i].i;
	1789	v[i].p[4] = tri->v[i].i;
1790	1790	}
1791	1791
1792	1792	model3_polydata &extra = object_data_alloc();
r32760	r32761
1821	1821	v[i].x = tri->v[i].x;
1822	1822	v[i].y = tri->v[i].y;
1823	1823	v[i].p[0] = tri->v[i].z;
1824		v[i].p[1] = tri->v[i].i;
	1824	v[i].p[1] = tri->v[i].i;
1825	1825	}
1826	1826
1827	1827	model3_polydata &extra = object_data_alloc();
r32760	r32761
1881	1881	}
1882	1882	}
1883	1883
1884		#define TEX_FETCH_NOFILTER() \
1885		do { \
1886		float intz = 1.0f / ooz; \
1887		UINT32 u = uoz * intz; \
1888		UINT32 v = voz * intz; \
1889		UINT32 u1 = (u >> 8) & umask; \
1890		UINT32 v1 = (v >> 8) & vmask; \
1891		texel = texture->data[(v1 << width) + u1]; \
	1884	#define TEX_FETCH_NOFILTER() \
	1885	do { \
	1886	float intz = 1.0f / ooz; \
	1887	UINT32 u = uoz * intz; \
	1888	UINT32 v = voz * intz; \
	1889	UINT32 u1 = (u >> 8) & umask; \
	1890	UINT32 v1 = (v >> 8) & vmask; \
	1891	texel = texture->data[(v1 << width) + u1]; \
1892	1892	} while(0);
1893	1893
1894		#define TEX_FETCH_BILINEAR() \
1895		do { \
1896		float intz = 1.0f / ooz; \
1897		UINT32 u = uoz * intz; \
1898		UINT32 v = voz * intz; \
1899		UINT32 u1 = (u >> 8) & umask; \
1900		UINT32 v1 = (v >> 8) & vmask; \
1901		UINT32 u2 = (u1 + 1) & umask; \
1902		UINT32 v2 = (v1 + 1) & vmask; \
1903		UINT32 pix00 = texture->data[(v1 << width) + u1]; \
1904		UINT32 pix01 = texture->data[(v1 << width) + u2]; \
1905		UINT32 pix10 = texture->data[(v2 << width) + u1]; \
1906		UINT32 pix11 = texture->data[(v2 << width) + u2]; \
1907		texel = rgba_bilinear_filter(pix00, pix01, pix10, pix11, u, v); \
	1894	#define TEX_FETCH_BILINEAR() \
	1895	do { \
	1896	float intz = 1.0f / ooz; \
	1897	UINT32 u = uoz * intz; \
	1898	UINT32 v = voz * intz; \
	1899	UINT32 u1 = (u >> 8) & umask; \
	1900	UINT32 v1 = (v >> 8) & vmask; \
	1901	UINT32 u2 = (u1 + 1) & umask; \
	1902	UINT32 v2 = (v1 + 1) & vmask; \
	1903	UINT32 pix00 = texture->data[(v1 << width) + u1]; \
	1904	UINT32 pix01 = texture->data[(v1 << width) + u2]; \
	1905	UINT32 pix10 = texture->data[(v2 << width) + u1]; \
	1906	UINT32 pix11 = texture->data[(v2 << width) + u2]; \
	1907	texel = rgba_bilinear_filter(pix00, pix01, pix10, pix11, u, v); \
1908	1908	} while(0);
1909	1909
1910	1910	#if ENABLE_BILINEAR
r32760	r32761
1989	1989
1990	1990	UINT32 fa = texel >> 24;
1991	1991	if (fa >= 0xf8)
1992		{
	1992	{
1993	1993	UINT32 r = ((texel & 0x00ff0000) * fa) >> 8;
1994	1994	UINT32 g = ((texel & 0x0000ff00) * fa) >> 8;
1995	1995	UINT32 b = ((texel & 0x000000ff) * fa) >> 8;
1996
	1996
1997	1997	UINT32 orig = fb[x];
1998
	1998
1999	1999	int minalpha = 255 - fa;
2000
	2000
2001	2001	r += ((orig & 0x00ff0000) * minalpha) >> 8;
2002	2002	g += ((orig & 0x0000ff00) * minalpha) >> 8;
2003	2003	b += ((orig & 0x000000ff) * minalpha) >> 8;
2004
	2004
2005	2005	fb[x] = 0xff000000 \| (r & 0xff0000) \| (g & 0xff00) \| (b & 0xff);
2006	2006	zb[x] = z;
2007	2007	}
r32760	r32761
2055	2055	r = (r * srctrans) >> 5;
2056	2056	g = (g * srctrans) >> 5;
2057	2057	b = (b * srctrans) >> 5;
2058
	2058
2059	2059	UINT32 orig = fb[x];
2060
	2060
2061	2061	r += ((orig & 0x00ff0000) * desttrans) >> 5;
2062	2062	g += ((orig & 0x0000ff00) * desttrans) >> 5;
2063	2063	b += ((orig & 0x000000ff) * desttrans) >> 5;
r32760	r32761
2091	2091	float in = extent.param[4].start;
2092	2092	float inz = extent.param[4].dpdx;
2093	2093
2094		// int srctrans = polydata.transparency;
2095		// int desttrans = 32 - polydata.transparency;
	2094	// int srctrans = polydata.transparency;
	2095	// int desttrans = 32 - polydata.transparency;
2096	2096
2097	2097	UINT32 umask = (((polydata.texture_param & TRI_PARAM_TEXTURE_MIRROR_U) ? 64 : 32) << texture->width) - 1;
2098	2098	UINT32 vmask = (((polydata.texture_param & TRI_PARAM_TEXTURE_MIRROR_V) ? 64 : 32) << texture->height) - 1;
r32760	r32761
2136	2136	in += inz;
2137	2137	z += dz;
2138	2138	}
2139		}
		No newline at end of file
	2139	}

trunk/src/mame/video/gtia.c
r32760	r32761
131	131	{
132	132	m_read_cb.resolve();
133	133	m_write_cb.resolve();
134
	134
135	135	save_item(NAME(m_r.m0pf));
136	136	save_item(NAME(m_r.m1pf));
137	137	save_item(NAME(m_r.m2pf));
r32760	r32761
218	218	save_item(NAME(m_h.vdelay_p1));
219	219	save_item(NAME(m_h.vdelay_p2));
220	220	save_item(NAME(m_h.vdelay_p3));
221
	221
222	222	save_item(NAME(m_lumpf1));
223	223	save_item(NAME(m_huepm0));
224	224	save_item(NAME(m_huepm1));
r32760	r32761
226	226	save_item(NAME(m_huepm3));
227	227	save_item(NAME(m_huepm4));
228	228	save_item(NAME(m_huepf2));
229		save_item(NAME(m_huebk));
	229	save_item(NAME(m_huebk));
230	230
231		save_item(NAME(m_color_lookup));
	231	save_item(NAME(m_color_lookup));
232	232
233	233	machine().save().register_postload(save_prepost_delegate(FUNC(gtia_device::gtia_postload), this));
234	234	}
r32760	r32761
291	291	m_r.but[i] = 1;
292	292	m_r.but[i] &= BIT(button_port, i);
293	293	}
294
	294
295	295	/* button registers for xl/xe */
296	296	if (button_count == 2)
297	297	{
298	298	m_r.but[2] = 1; /* not used on xl/xe */
299	299	m_r.but[3] = 0; /* 1 if external cartridge is inserted */
300	300	}
301
	301
302	302	}
303	303
304	304
r32760	r32761
967	967	player_render(m_h.grafp2, m_w.sizep2 + 1, GTIA_P2, &pmbits[m_w.hposp2]);
968	968	if (m_h.grafp3)
969	969	player_render(m_h.grafp3, m_w.sizep3 + 1, GTIA_P3, &pmbits[m_w.hposp3]);
970
	970
971	971	if (m_h.grafm0)
972	972	missile_render(m_h.grafm0, m_w.sizem + 1, GTIA_M0, &pmbits[m_w.hposm0]);
973	973	if (m_h.grafm1)

trunk/src/mame/video/gtia.h
r32760	r32761
127	127	public:
128	128	// construction/destruction
129	129	gtia_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
130
	130
131	131	template<class _Object> static devcb_base &set_read_callback(device_t &device, _Object object) { return downcast<gtia_device &>(device).m_read_cb.set_callback(object); }
132	132	template<class _Object> static devcb_base &set_write_callback(device_t &device, _Object object) { return downcast<gtia_device &>(device).m_write_cb.set_callback(object); }
133
	133
134	134	DECLARE_READ8_MEMBER( read );
135	135	DECLARE_WRITE8_MEMBER( write );
136	136
r32760	r32761
143	143	UINT8 get_w_prior() { return m_w.prior; }
144	144	void count_hitclr_frames() { m_h.hitclr_frames++; }
145	145	void button_interrupt(int button_count, UINT8 button_port);
146
	146
147	147	void render(UINT8 src, UINT8 dst, UINT8 pmbits, UINT8 prio);
148
	148
149	149	protected:
150	150	// device-level overrides
151	151	virtual void device_start();
152	152	virtual void device_reset();
153
	153
154	154	void gtia_postload();
155
	155
156	156	int is_ntsc();
157	157	void recalc_p0();
158	158	void recalc_p1();
r32760	r32761
162	162	void recalc_m1();
163	163	void recalc_m2();
164	164	void recalc_m3();
165
	165
166	166	inline void player_render(UINT8 gfx, int size, UINT8 color, UINT8 *dst);
167	167	inline void missile_render(UINT8 gfx, int size, UINT8 color, UINT8 *dst);
168
	168
169	169	private:
170	170	gtia_readregs m_r; /* read registers */
171	171	gtia_writeregs m_w; /* write registers */
172	172	gtia_helpervars m_h; /* helper variables */
173
	173
174	174	UINT8 m_lumpf1;
175	175	UINT8 m_huepm0, m_huepm1, m_huepm2, m_huepm3, m_huepm4;
176	176	UINT8 m_huepf2, m_huebk;
177
178		UINT16 m_color_lookup[256]; /* color lookup table */ // probably better fit to ANTIC, but it remains here for the moment...
179
	177
	178	UINT16 m_color_lookup[256]; /* color lookup table */ // probably better fit to ANTIC, but it remains here for the moment...
	179
180	180	devcb_read8 m_read_cb;
181	181	devcb_write8 m_write_cb;
182	182	};

trunk/src/mame/video/antic.c
r32760	r32761
58	58	{
59	59	m_gtia = machine().device<gtia_device>(m_gtia_tag);
60	60	assert(m_gtia);
61
	61
62	62	m_bitmap = auto_bitmap_ind16_alloc(machine(), machine().first_screen()->width(), machine().first_screen()->height());
63
	63
64	64	m_cclk_expand = auto_alloc_array_clear(machine(), UINT32, 21 * 256);
65
	65
66	66	m_pf_21 = &m_cclk_expand[ 0 * 256];
67	67	m_pf_x10b = &m_cclk_expand[ 1 * 256];
68	68	m_pf_3210b2 = &m_cclk_expand[ 3 * 256];
r32760	r32761
72	72	m_pf_gtia1 = &m_cclk_expand[18 * 256];
73	73	m_pf_gtia2 = &m_cclk_expand[19 * 256];
74	74	m_pf_gtia3 = &m_cclk_expand[20 * 256];
75
	75
76	76	m_used_colors = auto_alloc_array(machine(), UINT8, 21 * 256);
77
	77
78	78	memset(m_used_colors, 0, 21 * 256 * sizeof(UINT8));
79
	79
80	80	m_uc_21 = &m_used_colors[ 0 * 256];
81	81	m_uc_x10b = &m_used_colors[ 1 * 256];
82	82	m_uc_3210b2 = &m_used_colors[ 3 * 256];
r32760	r32761
86	86	m_uc_g1 = &m_used_colors[18 * 256];
87	87	m_uc_g2 = &m_used_colors[19 * 256];
88	88	m_uc_g3 = &m_used_colors[20 * 256];
89
	89
90	90	LOG(("atari cclk_init\n"));
91	91	cclk_init();
92
	92
93	93	for (int i = 0; i < 64; i++)
94	94	m_prio_table[i] = auto_alloc_array_clear(machine(), UINT8, 8*256);
95
	95
96	96	LOG(("atari prio_init\n"));
97	97	prio_init();
98
	98
99	99	for (int i = 0; i < machine().first_screen()->height(); i++)
100	100	m_video[i] = auto_alloc_clear(machine(), VIDEO);
101
	101
102	102	/* save states */
103	103	save_pointer(NAME((UINT8 *) &m_r), sizeof(m_r));
104	104	save_pointer(NAME((UINT8 *) &m_w), sizeof(m_w));
105	105	// TODO: save VIDEO items
106
	106
107	107	save_item(NAME(m_tv_artifacts));
108	108	save_item(NAME(m_render1));
109	109	save_item(NAME(m_render2));
r32760	r32761
556	556	{
557	557	int i, j, pm, p, c;
558	558	const UINT8 * prio;
559
	559
560	560	/* 32 priority bit combinations */
561	561	for( i = 0; i < 32; i++ )
562	562	{
r32760	r32761
575	575	}
576	576	m_prio_table[i][(j << 8) + pm] = c;
577	577	if( (c==PL0 \|\| c==P000 \|\| c==P001 \|\| c==P010 \|\| c==P011) &&
578		(pm & (P0+P1))==(P0+P1))
	578	(pm & (P0+P1))==(P0+P1))
579	579	c = EOR;
580	580	if( (c==PL2 \|\| c==P200 \|\| c==P201 \|\| c==P210 \|\| c==P211) &&
581		(pm & (P2+P3))==(P2+P3))
	581	(pm & (P2+P3))==(P2+P3))
582	582	c = EOR;
583	583	m_prio_table[32 + i][(j << 8) + pm] = c;
584	584	}
r32760	r32761
598	598	static const UINT8 _pf_310b[4] = {PBK,PF0,PF1,PF3};
599	599	int i;
600	600	UINT8 * dst;
601
	601
602	602	/* setup color translation for the ANTIC modes */
603	603	for( i = 0; i < 256; i++ )
604	604	{
r32760	r32761
608	608	*dst++ = _pf_21[(i>>4)&3];
609	609	*dst++ = _pf_21[(i>>2)&3];
610	610	*dst++ = _pf_21[(i>>0)&3];
611
	611
612	612	/**** 4 color text (4,5) with pf2, D, E ********/
613	613	dst = (UINT8 *)&m_pf_x10b[0x000+i];
614	614	*dst++ = _pf_210b[(i>>6)&3];
r32760	r32761
620	620	*dst++ = _pf_310b[(i>>4)&3];
621	621	*dst++ = _pf_310b[(i>>2)&3];
622	622	*dst++ = _pf_310b[(i>>0)&3];
623
	623
624	624	/**** pf0 color text (6,7), 9, B, C ********/
625	625	dst = (UINT8 )&m_pf_3210b2[0x000+i2];
626	626	*dst++ = (i&0x80)?PF0:PBK;
r32760	r32761
631	631	*dst++ = (i&0x04)?PF0:PBK;
632	632	*dst++ = (i&0x02)?PF0:PBK;
633	633	*dst++ = (i&0x01)?PF0:PBK;
634
	634
635	635	/**** pf1 color text (6,7), 9, B, C ********/
636	636	dst = (UINT8 )&m_pf_3210b2[0x200+i2];
637	637	*dst++ = (i&0x80)?PF1:PBK;
r32760	r32761
642	642	*dst++ = (i&0x04)?PF1:PBK;
643	643	*dst++ = (i&0x02)?PF1:PBK;
644	644	*dst++ = (i&0x01)?PF1:PBK;
645
	645
646	646	/**** pf2 color text (6,7), 9, B, C ********/
647	647	dst = (UINT8 )&m_pf_3210b2[0x400+i2];
648	648	*dst++ = (i&0x80)?PF2:PBK;
r32760	r32761
653	653	*dst++ = (i&0x04)?PF2:PBK;
654	654	*dst++ = (i&0x02)?PF2:PBK;
655	655	*dst++ = (i&0x01)?PF2:PBK;
656
	656
657	657	/**** pf3 color text (6,7), 9, B, C ********/
658	658	dst = (UINT8 )&m_pf_3210b2[0x600+i2];
659	659	*dst++ = (i&0x80)?PF3:PBK;
r32760	r32761
664	664	*dst++ = (i&0x04)?PF3:PBK;
665	665	*dst++ = (i&0x02)?PF3:PBK;
666	666	*dst++ = (i&0x01)?PF3:PBK;
667
	667
668	668	/**** 4 color graphics 4 cclks (8) ********/
669	669	dst = (UINT8 )&m_pf_210b4[i4];
670	670	*dst++ = _pf_210b[(i>>6)&3];
r32760	r32761
683	683	*dst++ = _pf_210b[(i>>0)&3];
684	684	*dst++ = _pf_210b[(i>>0)&3];
685	685	*dst++ = _pf_210b[(i>>0)&3];
686
	686
687	687	/**** 4 color graphics 2 cclks (A) ********/
688	688	dst = (UINT8 )&m_pf_210b2[i2];
689	689	*dst++ = _pf_210b[(i>>6)&3];
r32760	r32761
694	694	*dst++ = _pf_210b[(i>>2)&3];
695	695	*dst++ = _pf_210b[(i>>0)&3];
696	696	*dst++ = _pf_210b[(i>>0)&3];
697
	697
698	698	/**** high resolution graphics (F) ********/
699	699	dst = (UINT8 *)&m_pf_1b[i];
700	700	*dst++ = _pf_1b[(i>>6)&3];
701	701	*dst++ = _pf_1b[(i>>4)&3];
702	702	*dst++ = _pf_1b[(i>>2)&3];
703	703	*dst++ = _pf_1b[(i>>0)&3];
704
	704
705	705	/**** gtia mode 1 ********/
706	706	dst = (UINT8 *)&m_pf_gtia1[i];
707	707	*dst++ = GT1+((i>>4)&15);
708	708	*dst++ = GT1+((i>>4)&15);
709	709	*dst++ = GT1+(i&15);
710	710	*dst++ = GT1+(i&15);
711
	711
712	712	/**** gtia mode 2 ********/
713	713	dst = (UINT8 *)&m_pf_gtia2[i];
714	714	*dst++ = GT2+((i>>4)&15);
715	715	*dst++ = GT2+((i>>4)&15);
716	716	*dst++ = GT2+(i&15);
717	717	*dst++ = GT2+(i&15);
718
	718
719	719	/**** gtia mode 3 ********/
720	720	dst = (UINT8 *)&m_pf_gtia3[i];
721	721	*dst++ = GT3+((i>>4)&15);
722	722	*dst++ = GT3+((i>>4)&15);
723	723	*dst++ = GT3+(i&15);
724	724	*dst++ = GT3+(i&15);
725
	725
726	726	}
727
	727
728	728	/* setup used color tables */
729	729	for( i = 0; i < 256; i++ )
730	730	{
731	731	/* used colors in text modes 2,3 */
732	732	m_uc_21[i] = (i) ? PF2 \| PF1 : PF2;
733
	733
734	734	/* used colors in text modes 4,5 and graphics modes D,E */
735	735	switch( i & 0x03 )
736	736	{
r32760	r32761
756	756	case 0x80: m_uc_x10b[0x000+i] \|= PF1; m_uc_x10b[0x100+i] \|= PF1; break;
757	757	case 0xc0: m_uc_x10b[0x000+i] \|= PF2; m_uc_x10b[0x100+i] \|= PF3; break;
758	758	}
759
	759
760	760	/* used colors in text modes 6,7 and graphics modes 9,B,C */
761	761	if( i )
762	762	{
r32760	r32761
765	765	m_uc_3210b2[0x400+i*2] \|= PF2;
766	766	m_uc_3210b2[0x600+i*2] \|= PF3;
767	767	}
768
	768
769	769	/* used colors in graphics mode 8 */
770	770	switch( i & 0x03 )
771	771	{
r32760	r32761
791	791	case 0x80: m_uc_210b4[i*4] \|= PF1; break;
792	792	case 0xc0: m_uc_210b4[i*4] \|= PF2; break;
793	793	}
794
	794
795	795	/* used colors in graphics mode A */
796	796	switch( i & 0x03 )
797	797	{
r32760	r32761
817	817	case 0x80: m_uc_210b2[i*2] \|= PF1; break;
818	818	case 0xc0: m_uc_210b2[i*2] \|= PF2; break;
819	819	}
820
	820
821	821	/* used colors in graphics mode F */
822	822	if( i )
823	823	m_uc_1b[i] \|= PF1;
824
	824
825	825	/* used colors in GTIA graphics modes */
826	826	/* GTIA 1 is 16 different luminances with hue of colbk */
827	827	m_uc_g1[i] = 0x00;
r32760	r32761
838	838	case 0x07: m_uc_g2[i] = 0x08; break;
839	839	default: m_uc_g2[i] = 0x00;
840	840	}
841
	841
842	842	/* GTIA 3 is 16 different hues with luminance of colbk */
843	843	m_uc_g3[i] = 0x00;
844	844	}
r32760	r32761
1293	1293	{
1294	1294	VIDEO *video = m_video[m_scanline];
1295	1295	int add_bytes = 0, erase = 0;
1296
	1296
1297	1297	if (param3 == 0 \|\| param2 <= 1)
1298	1298	{
1299	1299	mode_0(space, video);
1300	1300	return;
1301	1301	}
1302
	1302
1303	1303	if ((param3 == 1 \|\| param3 == 2) && param1)
1304	1304	param3++;
1305
	1305
1306	1306	switch (param3)
1307	1307	{
1308	1308	case 1:
r32760	r32761
1318	1318	erase = 0;
1319	1319	break;
1320	1320	}
1321
	1321
1322	1322	switch (param2)
1323	1323	{
1324	1324	case 0x02:
r32760	r32761
1387	1387	{
1388	1388	UINT32 new_tv_artifacts = screen.ioport("artifacts")->read_safe(0);
1389	1389	copybitmap(bitmap, *m_bitmap, 0, 0, 0, 0, cliprect);
1390
	1390
1391	1391	if (m_tv_artifacts != new_tv_artifacts)
1392	1392	m_tv_artifacts = new_tv_artifacts;
1393
	1393
1394	1394	return 0;
1395	1395	}
1396	1396
r32760	r32761
1404	1404	UINT8 atari_C = b + c;
1405	1405	UINT8 atari_D = m_gtia->get_w_colbk();
1406	1406	UINT16 *color_lookup = m_gtia->get_color_lookup();
1407
	1407
1408	1408	for (int x = 0; x < width * 4; x++)
1409	1409	{
1410	1410	n = *src++;
r32760	r32761
1478	1478	UINT8 atari_C = b+c;
1479	1479	UINT8 atari_D = m_gtia->get_w_colpf2();
1480	1480	UINT16 *color_lookup = m_gtia->get_color_lookup();
1481
	1481
1482	1482	for (int x = 0; x < width * 4; x++)
1483	1483	{
1484	1484	n = *src++;
r32760	r32761
1550	1550	UINT32 *dst;
1551	1551	UINT32 scanline[4 + (HCHARS * 2) + 4];
1552	1552	UINT16 *color_lookup = m_gtia->get_color_lookup();
1553
	1553
1554	1554	/* increment the scanline */
1555	1555	if( ++m_scanline == machine().first_screen()->height() )
1556	1556	{
r32760	r32761
1560	1560	/* count frames gone since last write to hitclr */
1561	1561	m_gtia->count_hitclr_frames();
1562	1562	}
1563
	1563
1564	1564	if( m_scanline < MIN_Y \|\| m_scanline > MAX_Y )
1565	1565	return;
1566
	1566
1567	1567	y = m_scanline - MIN_Y;
1568	1568	src = &m_cclock[PMOFFSET - m_hscrol_old + 12];
1569	1569	dst = scanline;
1570
	1570
1571	1571	if( m_tv_artifacts )
1572	1572	{
1573	1573	if( (m_cmd & 0x0f) == 2 \|\| (m_cmd & 0x0f) == 3 )
r32760	r32761
1648	1648	dst[1] = color_lookup[PBK] \| color_lookup[PBK] << 16;
1649	1649	dst[2] = color_lookup[PBK] \| color_lookup[PBK] << 16;
1650	1650	dst[3] = color_lookup[PBK] \| color_lookup[PBK] << 16;
1651
	1651
1652	1652	draw_scanline8(m_bitmap, 12, y, MIN(m_bitmap->width() - 12, sizeof(scanline)), (const UINT8 ) scanline, NULL);
1653	1653	}
1654	1654
1655	1655
1656		#define ANTIC_TIME_FROM_CYCLES(cycles) \
	1656	#define ANTIC_TIME_FROM_CYCLES(cycles) \
1657	1657	(attotime)(machine().first_screen()->scan_period() * (cycles) / CYCLES_PER_LINE)
1658	1658
1659	1659	void antic_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
r32760	r32761
1714	1714	LOG((" @cycle #%3d release CPU\n", cycle()));
1715	1715	/* release the CPU (held for emulating cycles stolen by ANTIC DMA) */
1716	1716	machine().scheduler().trigger(TRIGGER_STEAL);
1717
	1717
1718	1718	/* refresh the display (translate color clocks to pixels) */
1719	1719	linerefresh();
1720	1720	}
r32760	r32761
1748	1748	TIMER_CALLBACK_MEMBER( antic_device::scanline_render )
1749	1749	{
1750	1750	address_space &space = machine().device("maincpu")->memory().space(AS_PROGRAM);
1751
	1751
1752	1752	LOG((" @cycle #%3d render mode $%X lines to go #%d\n", cycle(), (m_cmd & 0x0f), m_modelines));
1753
	1753
1754	1754	render(space, m_render1, m_render2, m_render3);
1755
	1755
1756	1756	/* if player/missile graphics is enabled */
1757	1757	if( m_scanline < 256 && (m_w.dmactl & (DMA_PLAYER\|DMA_MISSILE)) )
1758	1758	{
r32760	r32761
1796	1796	}
1797	1797	}
1798	1798	}
1799
	1799
1800	1800	if (m_scanline >= VBL_END && m_scanline < 256)
1801	1801	m_gtia->render((UINT8 )m_pmbits + PMOFFSET, (UINT8 )m_cclock + PMOFFSET - m_hscrol_old, (UINT8 )m_prio_table[m_gtia->get_w_prior() & 0x3f], (UINT8 )&m_pmbits);
1802
	1802
1803	1803	m_steal_cycles += CYCLES_REFRESH;
1804	1804	LOG((" run CPU for %d cycles\n", CYCLES_HSYNC - CYCLES_HSTART - m_steal_cycles));
1805	1805	timer_set(ANTIC_TIME_FROM_CYCLES(CYCLES_HSYNC - CYCLES_HSTART - m_steal_cycles), TIMER_CYCLE_STEAL);
r32760	r32761
1856	1856	m_render3 = m_w.dmactl & 3;
1857	1857	UINT8 vscrol_subtract = 0;
1858	1858	UINT8 new_cmd;
1859
	1859
1860	1860	new_cmd = RDANTIC(space);
1861	1861	m_doffs = (m_doffs + 1) & DOFFS;
1862	1862	/* steal at one clock cycle from the CPU for fetching the command */
r32760	r32761
1894	1894	}
1895	1895	/* Set the ANTIC mode renderer function */
1896	1896	m_render2 = new_cmd & ANTIC_MODE;
1897
	1897
1898	1898	switch( new_cmd & ANTIC_MODE )
1899	1899	{
1900	1900	case 0x00:
r32760	r32761
2048	2048	m_render2 = 0;
2049	2049	m_render3 = 0;
2050	2050	}
2051
	2051
2052	2052	m_r.nmist &= ~DLI_NMI;
2053	2053	if (m_modelines == 1 && (m_cmd & m_w.nmien & DLI_NMI))
2054	2054	timer_set(ANTIC_TIME_FROM_CYCLES(CYCLES_DLI_NMI), TIMER_ISSUE_DLI);
2055
	2055
2056	2056	timer_set(ANTIC_TIME_FROM_CYCLES(CYCLES_HSTART), TIMER_LINE_REND);
2057	2057	}
2058	2058
r32760	r32761
2068	2068	void antic_device::generic_interrupt(int button_count)
2069	2069	{
2070	2070	LOG(("ANTIC #%3d @cycle #%d scanline interrupt\n", m_scanline, cycle()));
2071
	2071
2072	2072	if( m_scanline < VBL_START )
2073	2073	{
2074	2074	scanline_dma(0);
2075	2075	return;
2076	2076	}
2077
	2077
2078	2078	if( m_scanline == VBL_START )
2079	2079	{
2080	2080	/* specify buttons relevant to this Atari variant */
2081	2081	m_gtia->button_interrupt(button_count, machine().root_device().ioport("djoy_b")->read_safe(0));
2082
	2082
2083	2083	/* do nothing new for the rest of the frame */
2084	2084	m_modelines = machine().first_screen()->height() - VBL_START;
2085	2085	m_render1 = 0;
2086	2086	m_render2 = 0;
2087	2087	m_render3 = 0;
2088
	2088
2089	2089	/* if the CPU want's to be interrupted at vertical blank... */
2090	2090	if( m_w.nmien & VBL_NMI )
2091	2091	{
r32760	r32761
2095	2095	machine().device("maincpu")->execute().set_input_line(INPUT_LINE_NMI, PULSE_LINE);
2096	2096	}
2097	2097	}
2098
	2098
2099	2099	/* refresh the display (translate color clocks to pixels) */
2100	2100	linerefresh();
2101	2101	}
2102

trunk/src/mame/video/antic.h
r32760	r32761
3	3	Atari 400/800
4	4
5	5	ANTIC video controller
6
	6
7	7	Juergen Buchmueller, June 1998
8	8
9	9	***************************************************************************/
r32760	r32761
293	293	m_w.chbasl++
294	294
295	295	/* erase a number of color clocks to background color PBK */
296		#define ERASE(size) \
297		for (int i = 0; i < size; i++) \
298		{ \
	296	#define ERASE(size) \
	297	for (int i = 0; i < size; i++) \
	298	{ \
299	299	*dst++ = (PBK << 24) \| (PBK << 16) \| (PBK << 8) \| PBK; \
300		} \
301
	300	}
302	301	#define ZAP48() \
303	302	dst = (UINT32 *)&antic.cclock[PMOFFSET]; \
304	303	dst[ 0] = (PBK << 24) \| (PBK << 16) \| (PBK << 8) \| PBK; \
r32760	r32761
309	308	dst[47] = (PBK << 24) \| (PBK << 16) \| (PBK << 8) \| PBK
310	309
311	310	#define REP(FUNC, size) \
312		for (int i = 0; i < size; i++) \
313		{ \
314		FUNC(i); \
315		} \
	311	for (int i = 0; i < size; i++) \
	312	{ \
	313	FUNC(i); \
	314	}
316	315
317	316
318
319	317	struct ANTIC_R {
320	318	UINT8 antic00; /* 00 nothing */
321	319	UINT8 antic01; /* 01 nothing */
r32760	r32761
379	377
380	378	UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
381	379	void generic_interrupt(int button_count);
382
	380
383	381	private:
384	382	static const device_timer_id TIMER_CYCLE_STEAL = 0;
385	383	static const device_timer_id TIMER_ISSUE_DLI = 1;
r32760	r32761
454	452	UINT8 m_uc_g2; / used colors for gfx GTIA 2 */
455	453	UINT8 m_uc_g3; / used colors for gfx GTIA 3 */
456	454	bitmap_ind16 *m_bitmap;
457
	455
458	456	void prio_init();
459	457	void cclk_init();
460	458

trunk/src/mame/layout/s11a.lay
r32760	r32761
1	1	<!-- s11a.lay -->
2	2
3	3	<!-- 2012-11-04: Initial version. [Robbbert]
4		2012-12-19: Rearranged layout, replaced diagnostic 7-digit LED with 3 single LEDs [Barry Rodewald]-->
	4	2012-12-19: Rearranged layout, replaced diagnostic 7-digit LED with 3 single LEDs [Barry Rodewald]-->
5	5
6	6	<mamelayout version="2">
7	7

trunk/src/mame/layout/mgavegas.lay
r32760	r32761
35	35
36	36	<element name="P12"><text string="500"><color red="1.0" green="1.0" blue="1.0" /></text></element>
37	37	<element name="P13"><text string="300"><color red="1.0" green="1.0" blue="1.0" /></text></element>
38		<element name="P14"><text string="200"><color red="1.0" green="1.0" blue="1.0" /></text></element>
	38	<element name="P14"><text string="200"><color red="1.0" green="1.0" blue="1.0" /></text></element>
39	39	<element name="P15"><text string="100"><color red="1.0" green="1.0" blue="1.0" /></text></element>
40
	40
41	41	<element name="P16"><text string="INSERT COIN"><color red="1.0" green="1.0" blue="1.0" /></text></element>
42		<element name="P17"><text string="NO CAMBIO"><color red="1.0" green="1.0" blue="1.0" /></text></element>
	42	<element name="P17"><text string="NO CAMBIO"><color red="1.0" green="1.0" blue="1.0" /></text></element>
43	43	<element name="P18"><text string="FUSE"><color red="1.0" green="1.0" blue="1.0" /></text></element>
44	44	<element name="P19"><text string="FALTA"><color red="1.0" green="1.0" blue="1.0" /></text></element>
45
46		<element name="P20"><text string="MGA"><color red="1.0" green="1.0" blue="1.0" /></text></element>
	45
	46	<element name="P20"><text string="MGA"><color red="1.0" green="1.0" blue="1.0" /></text></element>
47	47	<element name="P21"><text string="50"><color red="1.0" green="1.0" blue="1.0" /></text></element>
48	48	<element name="P22"><text string="MGA"><color red="1.0" green="1.0" blue="1.0" /></text></element>
49	49	<element name="P23"><text string="25"><color red="1.0" green="1.0" blue="1.0" /></text></element>
50		<element name="P24"><text string="250"><color red="1.0" green="1.0" blue="1.0" /></text></element>
	50	<element name="P24"><text string="250"><color red="1.0" green="1.0" blue="1.0" /></text></element>
51	51	<element name="P25"><text string="MGA"><color red="1.0" green="1.0" blue="1.0" /></text></element>
52	52	<element name="P26"><text string="100"><color red="1.0" green="1.0" blue="1.0" /></text></element>
53	53	<element name="P27"><text string="MGA"><color red="1.0" green="1.0" blue="1.0" /></text></element>
54	54	<element name="P28"><text string="25"><color red="1.0" green="1.0" blue="1.0" /></text></element>
55
	55
56	56	<element name="P29"><text string="Premio Sorpresa"><color red="1.0" green="1.0" blue="1.0" /></text></element>
57	57
58
	58
59	59	<view name="Default Layout">
60	60
61	61	<!-- Background -->
r32760	r32761
74	74	<bezel name="MR" element="red_led">
75	75	<bounds x="360" y="50" width="5" height="5" />
76	76	</bezel>
77
	77
78	78	<bezel name="CL" element="red_led">
79	79	<bounds x="280" y="100" width="5" height="5" />
80	80	</bezel>
r32760	r32761
103	103	</bezel>
104	104	<bezel name="PR" element="red_led">
105	105	<bounds x="360" y="200" width="5" height="5" />
106		</bezel>
107
	106	</bezel>
	107
108	108	<bezel name="500" element="red_led">
109	109	<bounds x="410" y="50" width="5" height="5" />
110	110	</bezel>
r32760	r32761
113	113	</bezel>
114	114	<bezel name="200" element="red_led">
115	115	<bounds x="410" y="150" width="5" height="5" />
116		</bezel>
	116	</bezel>
117	117	<bezel name="100" element="red_led">
118	118	<bounds x="410" y="200" width="5" height="5" />
119		</bezel>
120
	119	</bezel>
	120
121	121	<bezel name="INSERTCOIN" element="red_led">
122	122	<bounds x="270" y="250" width="5" height="5" />
123	123	</bezel>
r32760	r32761
126	126	</bezel>
127	127	<bezel name="FUSE" element="red_led">
128	128	<bounds x="350" y="250" width="5" height="5" />
129		</bezel>
	129	</bezel>
130	130	<bezel name="FALTA" element="red_led">
131	131	<bounds x="400" y="250" width="5" height="5" />
132	132	</bezel>
r32760	r32761
139	139	</bezel>
140	140	<bezel name="MGA3" element="red_led">
141	141	<bounds x="125" y="350" width="30" height="30" />
142		</bezel>
	142	</bezel>
143	143	<bezel name="252" element="red_led">
144	144	<bounds x="170" y="350" width="30" height="30" />
145	145	</bezel>
r32760	r32761
151	151	</bezel>
152	152	<bezel name="1002" element="red_led">
153	153	<bounds x="305" y="350" width="30" height="30" />
154		</bezel>
	154	</bezel>
155	155	<bezel name="MGA" element="red_led">
156	156	<bounds x="350" y="350" width="30" height="30" />
157	157	</bezel>
r32760	r32761
159	159	<bounds x="395" y="350" width="30" height="30" />
160	160	</bezel>
161	161
162
	162
163	163	<bezel name="MGA4" element="red_led">
164	164	<bounds x="40" y="50" width="5" height="5" />
165	165	</bezel>
r32760	r32761
168	168	</bezel>
169	169	<bezel name="MGA3" element="red_led">
170	170	<bounds x="80" y="150" width="5" height="5" />
171		</bezel>
	171	</bezel>
172	172	<bezel name="252" element="red_led">
173	173	<bounds x="100" y="200" width="5" height="5" />
174	174	</bezel>
r32760	r32761
180	180	</bezel>
181	181	<bezel name="1002" element="red_led">
182	182	<bounds x="160" y="150" width="5" height="5" />
183		</bezel>
	183	</bezel>
184	184	<bezel name="MGA" element="red_led">
185	185	<bounds x="180" y="100" width="5" height="5" />
186	186	</bezel>
r32760	r32761
191	191	<bezel name="PREMIOS" element="red_led">
192	192	<bounds x="220" y="150" width="10" height="10" />
193	193	</bezel>
194
195
196
	194
	195
	196
197	197	<bezel element="P0"><bounds left="350" right="370" top="20" bottom="40" /></bezel>
198	198	<bezel element="P1"><bounds left="310" right="330" top="20" bottom="40" /></bezel>
199	199	<bezel element="P2"><bounds left="270" right="290" top="20" bottom="40" /></bezel>
r32760	r32761
219	219	<bezel element="P17"><bounds left="310" right="330" top="220" bottom="240" /></bezel>
220	220	<bezel element="P18"><bounds left="350" right="370" top="220" bottom="240" /></bezel>
221	221	<bezel element="P19"><bounds left="400" right="420" top="220" bottom="240" /></bezel>
222
	222
223	223	<bezel element="P20"><bounds left="35" right="55" top="320" bottom="340" /></bezel>
224	224	<bezel element="P21"><bounds left="80" right="100" top="320" bottom="340" /></bezel>
225	225	<bezel element="P22"><bounds left="125" right="145" top="320" bottom="340" /></bezel>
226		<bezel element="P23"><bounds left="170" right="190" top="320" bottom="340" /></bezel>
	226	<bezel element="P23"><bounds left="170" right="190" top="320" bottom="340" /></bezel>
227	227	<bezel element="P24"><bounds left="215" right="235" top="320" bottom="340" /></bezel>
228	228	<bezel element="P25"><bounds left="260" right="280" top="320" bottom="340" /></bezel>
229	229	<bezel element="P26"><bounds left="305" right="325" top="320" bottom="340" /></bezel>
230		<bezel element="P27"><bounds left="350" right="370" top="320" bottom="340" /></bezel>
231		<bezel element="P28"><bounds left="395" right="415" top="320" bottom="340" /></bezel>
	230	<bezel element="P27"><bounds left="350" right="370" top="320" bottom="340" /></bezel>
	231	<bezel element="P28"><bounds left="395" right="415" top="320" bottom="340" /></bezel>
232	232
233	233
234	234	<bezel element="P20"><bounds left="40" right="60" top="35" bottom="45" /></bezel>
235	235	<bezel element="P21"><bounds left="60" right="80" top="85" bottom="95" /></bezel>
236	236	<bezel element="P22"><bounds left="80" right="100" top="135" bottom="145" /></bezel>
237		<bezel element="P23"><bounds left="100" right="120" top="185" bottom="195" /></bezel>
	237	<bezel element="P23"><bounds left="100" right="120" top="185" bottom="195" /></bezel>
238	238	<bezel element="P24"><bounds left="120" right="140" top="235" bottom="245" /></bezel>
239	239	<bezel element="P25"><bounds left="140" right="160" top="185" bottom="195" /></bezel>
240	240	<bezel element="P26"><bounds left="160" right="180" top="135" bottom="145" /></bezel>
241		<bezel element="P27"><bounds left="180" right="200" top="85" bottom="95" /></bezel>
242		<bezel element="P28"><bounds left="200" right="220" top="35" bottom="45" /></bezel>
	241	<bezel element="P27"><bounds left="180" right="200" top="85" bottom="95" /></bezel>
	242	<bezel element="P28"><bounds left="200" right="220" top="35" bottom="45" /></bezel>
243	243
244		<bezel element="P29"><bounds left="190" right="260" top="130" bottom="150" /></bezel>
245
	244	<bezel element="P29"><bounds left="190" right="260" top="130" bottom="150" /></bezel>
	245
246	246	</view>
247	247	</mamelayout>

trunk/src/mame/drivers/itech32.c
r32760	r32761
4405	4405
4406	4406	/* The protection code is:
4407	4407
4408		addq #1, 1132.w
4409		clr.l d0
4410		clr.l d1
4411		move.b 680002,d0 ; Read protection result
4412		move.b 112f.w,d1
4413		andi.b #$01,d0
	4408	addq #1, 1132.w
	4409	clr.l d0
	4410	clr.l d1
	4411	move.b 680002,d0 ; Read protection result
	4412	move.b 112f.w,d1
	4413	andi.b #$01,d0
4414	4414	Label1 bne.s Label1 ; Infinite loop if result isn't 0x01
4415		nop ; Otherwise just return to the game :-)
	4415	nop ; Otherwise just return to the game :-)
4416	4416
4417	4417	*/
4418	4418	}
r32760	r32761
4426	4426
4427	4427	/* The protection code is:
4428	4428
4429		addq #1, 1132.w
4430		clr.l d0
4431		clr.l d1
4432		move.b 680002,d0 ; Read protection result
4433		andi.b #$C0,d0
4434		cmpi.b #$80,d0
	4429	addq #1, 1132.w
	4430	clr.l d0
	4431	clr.l d1
	4432	move.b 680002,d0 ; Read protection result
	4433	andi.b #$C0,d0
	4434	cmpi.b #$80,d0
4435	4435	Label1 bne.s Label1 ; Infinite loop if result isn't 0x80
4436		rts ; Otherwise just return to the game :-)
	4436	rts ; Otherwise just return to the game :-)
4437	4437
4438	4438	*/
4439	4439	}

trunk/src/mame/drivers/travrusa.c
r32760	r32761
617	617	GAME( 1985, shtrider, 0, shtrider, shtrider, driver_device, 0, ROT270\|ORIENTATION_FLIP_X, "Seibu Kaihatsu", "Shot Rider", GAME_SUPPORTS_SAVE ) // possible bootleg
618	618	GAME( 1984, shtridera,shtrider, shtrider, shtrider, travrusa_state, shtridra, ROT270\|ORIENTATION_FLIP_X, "Seibu Kaihatsu (Sigma license)", "Shot Rider (Sigma license)", GAME_SUPPORTS_SAVE )
619	619	GAME( 1985, shtriderb,shtrider, shtriderb,shtrider, travrusa_state, shtridrb, ROT270\|ORIENTATION_FLIP_X, "bootleg", "Shot Rider (bootleg)", GAME_SUPPORTS_SAVE ) // resets when you attempt to start a game?
620

trunk/src/mame/drivers/20pacgal.c
r32760	r32761
363	363	save_item(NAME(m_sprite_ram));
364	364	save_item(NAME(m_sprite_color_lookup));
365	365	}
366
	366
367	367	void _20pacgal_state::machine_start()
368	368	{
369	369	common_save_state();

trunk/src/mame/drivers/system16.c
r32760	r32761
1115	1115	AM_RANGE(0x440000, 0x440fff) AM_RAM AM_SHARE("sprites")
1116	1116	AM_RANGE(0x840000, 0x840fff) AM_RAM_WRITE(paletteram_w) AM_SHARE("paletteram")
1117	1117
1118		// moved from C4xxxx to E4xxxx
	1118	// moved from C4xxxx to E4xxxx
1119	1119	AM_RANGE(0xe40000, 0xe40001) AM_READ_PORT("COINAGE")
1120	1120	AM_RANGE(0xe40002, 0xe40003) AM_READ_PORT("DSW1")
1121	1121	AM_RANGE(0xe40006, 0xe40007) AM_WRITE(sound_command_irq_w)
r32760	r32761
2521	2521	ROM_LOAD16_BYTE( "epr12097.b8", 0x60000, 0x010000, CRC(e645902c) SHA1(497cfcf6c25cc2e042e16dbcb1963d2223def15a) ) // 16- ic103
2522	2522
2523	2523	ROM_REGION( 0x10000, "soundcpu", 0 ) /* sound CPU */
2524		ROM_LOAD( "a-1 ic68", 0x0000, 0x8000, CRC(8321eb0b) SHA1(61cf95833c0aa38e35fc18db39d4ec74e4aaf01e) )
	2524	ROM_LOAD( "a-1 ic68", 0x0000, 0x8000, CRC(8321eb0b) SHA1(61cf95833c0aa38e35fc18db39d4ec74e4aaf01e) )
2525	2525
2526	2526	ROM_REGION( 0x1000, "mcu", 0 ) /* MCU code */
2527	2527	ROM_LOAD( "d8749h.mcu", 0x0000, 0x1000, NO_DUMP )

trunk/src/mame/drivers/mpu5hw.c
r32760	r32761
17	17
18	18	-- Much of the communication is done via a 68681 DUART.
19	19
20		-- The ASIC acts as the main I/O control, including an interface to a Z89321 DSP and a 16bit DAC.
21
	20	-- The ASIC acts as the main I/O control, including an interface to a Z89321 DSP and a 16bit DAC.
	21
22	22	-- Help wanted, the MFME sources (which are based on MAME anyway) should be of some help here, if somebody
23	23	in the FM emu community wants to adopt this driver they're welcome to it.
24	24
r32760	r32761
68	68	UINT8 m_pic_stored_input;
69	69	UINT8 m_pic_output_bit;
70	70	UINT8 m_input_strobe;
71
	71
72	72	DECLARE_READ32_MEMBER(mpu5_mem_r);
73	73	DECLARE_WRITE32_MEMBER(mpu5_mem_w);
74	74
r32760	r32761
101	101	//send init and ready for now - need to work on full DSP
102	102	return 0x85;
103	103	}
104
	104
105	105	case 0x0b:
106	106	{
107	107	return 0;
r32760	r32761
148	148	logerror("%08x DUART read\n", pc);
149	149	break;
150	150	}
151
	151
152	152	case 0xf0:
153	153	{
154	154	return asic_r32(space, offset&3,mem_mask);
155	155	}
156
	156
157	157	default:
158	158	logerror("%08x maincpu read access offset %08x mem_mask %08x cs %d\n", pc, offset*4, mem_mask, cs);
159	159	break;
160	160	}
161	161	}
162	162	break;
163
	163
164	164	case 3:
165	165	case 4:
166	166	offset &=0x3fff;
r32760	r32761
188	188	if (m_led_strobe_temp != data)
189	189	{
190	190	m_led_strobe_temp = data;
191
	191
192	192	switch (m_led_strobe_temp)
193	193	{
194	194	case 0x00:
r32760	r32761
222	222	}
223	223	break;
224	224	}
225
	225
226	226	case 0x09:
227	227	{
228	228	//Assume SEC fitted for now
r32760	r32761
233	233	case 0x0b:
234	234	{
235	235	output_set_value("statuslamp1", ((data&0x10) != 0));
236
	236
237	237	output_set_value("statuslamp2", ((data&0x20) != 0));
238
	238
239	239	if (data & 0x40)
240	240	{
241		// m_dsp_pin =1;
	241	// m_dsp_pin =1;
242	242	}
243	243	}
244	244	break;
r32760	r32761
280	280	m_pic_bit1 = (data & 0x01);
281	281	break;
282	282	}
283
	283
284	284	case 0x06:
285	285	case 0x07:
286	286	{
r32760	r32761
291	291	m_pic_data \|= m_pic_bit1;
292	292	m_pic_stored_input <<= 1;
293	293	m_pic_clocked_bits ++;
294
	294
295	295	if (m_pic_clocked_bits >=8)
296	296	{
297	297	m_pic_data =0;
298	298	m_pic_clocked_bits =0;
299
	299
300	300	if (m_input_strobe <4)
301	301	{
302	302	m_input_strobe +=1;
303	303	}
304
	304
305	305	}
306	306	}
307	307	else
r32760	r32761
319	319	break;
320	320	}
321	321	}
322
	322
323	323	}
324	324
325	325	WRITE32_MEMBER(mpu5_state::mpu5_mem_w)
r32760	r32761
344	344	logerror("%08x DUART write\n", pc);
345	345	break;
346	346	}
347
	347
348	348	case 0xf0:
349	349	{
350	350	asic_w32(space, offset&3,data,mem_mask);
351	351	break;
352	352	}
353
	353
354	354	default:
355	355	logerror("%08x maincpu write access offset %08x data %08x mem_mask %08x cs %d\n", pc, offset*4, data, mem_mask, cs);
356	356	break;

trunk/src/mame/drivers/bartop52.c
r32760	r32761
33	33	TIMER_DEVICE_CALLBACK_MEMBER( bartop_interrupt );
34	34
35	35	virtual void machine_reset();
36		//required_device<cpu_device> m_maincpu; // maincpu is already contained in atari_common_state
	36	//required_device<cpu_device> m_maincpu; // maincpu is already contained in atari_common_state
37	37	};
38	38
39	39

trunk/src/mame/drivers/galaxian.c
r32760	r32761
1697	1697	AM_RANGE(0xb801, 0xb801) AM_WRITE(irq_enable_w)
1698	1698	AM_RANGE(0xb806, 0xb806) AM_WRITE(galaxian_flip_screen_x_w)
1699	1699	AM_RANGE(0xb807, 0xb807) AM_WRITE(galaxian_flip_screen_y_w)
1700		// AM_RANGE(0xb818, 0xb818) AM_WRITE(coin_count_0_w) /* IOPC7 */
1701		// AM_RANGE(0xb81c, 0xb81c) AM_WRITE(coin_count_1_w) /* POUT1 */
	1700	// AM_RANGE(0xb818, 0xb818) AM_WRITE(coin_count_0_w) /* IOPC7 */
	1701	// AM_RANGE(0xb81c, 0xb81c) AM_WRITE(coin_count_1_w) /* POUT1 */
1702	1702	// todo, map inputs properly for this version
1703	1703	ADDRESS_MAP_END
1704	1704
r32760	r32761
6578	6578	// space.nop_write(0x6803, 0x6803);
6579	6579
6580	6580	m_audiocpu->space(AS_PROGRAM).install_read_handler(0x3000, 0x3000, read8_delegate(FUNC(galaxian_state::scorpion_digitalker_intr_r),this));
6581
	6581
6582	6582	save_item(NAME(m_protection_state));
6583	6583	/*
6584	6584	{
r32760	r32761
6697	6697	/* ROMCMP reports "BADADDR xxxxxx-xxxxx". Observed data sequence repeated every 32 bytes */
6698	6698	ROM_LOAD( "swarpt7m.bin", 0x2000, 0x1000, BAD_DUMP CRC(a2dff6c8) SHA1(d1c72848450dc5ff386dc94a26e4bf704ccc7121) )
6699	6699	/* Stripped "repaired" rom. Was original rom supposed to be 0x1000 or 0x800? */
6700		// ROM_LOAD( "swarpt7m-repair.bin", 0x2000, 0x0800, CRC(109f95cf) SHA1(d99171ffd6639fec28966edaf7cce3a4df5e948d) )
	6700	// ROM_LOAD( "swarpt7m-repair.bin", 0x2000, 0x0800, CRC(109f95cf) SHA1(d99171ffd6639fec28966edaf7cce3a4df5e948d) )
6701	6701
6702	6702	ROM_REGION( 0x1000, "gfx1", 0 )
6703	6703	ROM_LOAD( "swarpb1h.bin", 0x0000, 0x0800, CRC(6ee3b5f7) SHA1(8150f2ecd59d3a165c0541b550664c56d049edd5) )

trunk/src/mame/drivers/gaiden.c
r32760	r32761
1160	1160	ROM_START( ryukendna )
1161	1161	ROM_REGION( 0x40000, "maincpu", 0 ) /* 2128k for 68000 code /
1162	1162	ROM_LOAD16_BYTE( "1.3s", 0x00000, 0x20000, CRC(5532e302) SHA1(8ce48963ba737890d1a46c42a113d9419a3c174c) ) // found on 2 pcbs
1163		// ROM_LOAD16_BYTE( "1.3s", 0x00000, 0x20000, CRC(0ed5464c) SHA1(2eab6650ad1c38cd560ec3d084f47156756c97a4) ) 2 bytes different ( 022a : 50 instead of 51, 12f9 : 6b instead of 6a) - possible bad rom
	1163	// ROM_LOAD16_BYTE( "1.3s", 0x00000, 0x20000, CRC(0ed5464c) SHA1(2eab6650ad1c38cd560ec3d084f47156756c97a4) ) 2 bytes different ( 022a : 50 instead of 51, 12f9 : 6b instead of 6a) - possible bad rom
1164	1164	ROM_LOAD16_BYTE( "2.4s", 0x00001, 0x20000, CRC(a93a8256) SHA1(6bf6c189f82cb9341d3427a822de83cbaed27bc0) )
1165	1165
1166	1166	ROM_REGION( 0x10000, "audiocpu", 0 )

trunk/src/mame/drivers/aces1.c
r32760	r32761
136	136	{
137	137	//There needs to be some way of connecting these values to stepper coils, or doing the MCU properly
138	138	// We should be able to see an enable clock, a sense and a full/half step selector, we don't have the half step visible it seems.
139
	139
140	140	//3 1 16 14
141	141	int phases[] = {0x05,0x01,0x09,0x08,0x0a,0x02,0x06,0x04,};
142	142	for (int reel=0; reel <4; reel++)
r32760	r32761
165	165	logerror("Reel %x Enable %x \n",reel, clock );
166	166	}
167	167	}
168		// logerror("Reel %x Enable %x Sense %i \n",reel, (data & (1<<reel)), (data & (4 + (1<<reel))) ? 1:-1 );
	168	// logerror("Reel %x Enable %x Sense %i \n",reel, (data & (1<<reel)), (data & (4 + (1<<reel))) ? 1:-1 );
169	169	}
170
171
172		// printf("reels, extender strobe %02x\n", data);
	170
	171
	172	// printf("reels, extender strobe %02x\n", data);
173	173	}
174	174
175	175	DECLARE_READ8_MEMBER( ic37_read_a )
r32760	r32761
194	194	if (stepper_optic_state(reel)) pattern \|= 1<<reel;
195	195	if (m_reel_count[reel]) action \|= 1<<reel;
196	196	}
197
	197
198	198	return ((pattern << 4) \| action);
199	199	}
200	200
r32760	r32761
313	313	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
314	314	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
315	315	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
316
	316
317	317	PORT_START("IO4")
318	318	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
319	319	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
r32760	r32761
353	353	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
354	354	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
355	355	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
356
	356
357	357	PORT_START("IO8")
358	358	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
359	359	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
r32760	r32761
363	363	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
364	364	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
365	365	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
366
	366
367	367	PORT_START("DSWA")
368	368	PORT_DIPNAME( 0x01, 0x01, "DSWA" )
369	369	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )

trunk/src/mame/drivers/model1.c
r32760	r32761
783	783	COMBINE_DATA(m_display_list1+offset);
784	784	// never executed
785	785	//if(0 && offset)
786		// return;
	786	// return;
787	787	if(1 && m_dump)
788	788	logerror("TGP: md1_w %x, %04x @ %04x (%x)\n", offset, data, mem_mask, space.device().safe_pc());
789	789	}
r32760	r32761
793	793	COMBINE_DATA(m_display_list0+offset);
794	794	// never executed
795	795	//if(0 && offset)
796		// return;
	796	// return;
797	797	if(1 && m_dump)
798	798	logerror("TGP: md0_w %x, %04x @ %04x (%x)\n", offset, data, mem_mask, space.device().safe_pc());
799	799	}

trunk/src/mame/drivers/dkong.c
r32760	r32761
1000	1000
1001	1001	static INPUT_PORTS_START( dkongx )
1002	1002	/* Supposedly the physical DIPS are read as defaults for the NVRAM when it's initially created.
1003		The settings here match those from the default DSW0 settings. Beyond the initial NVRAM
1004		creation, DIPS (other than CABINET) can only be adjusted from the Service Mode */
	1003	The settings here match those from the default DSW0 settings. Beyond the initial NVRAM
	1004	creation, DIPS (other than CABINET) can only be adjusted from the Service Mode */
1005	1005	PORT_INCLUDE( dkong )
1006	1006
1007	1007	PORT_MODIFY("DSW0")

trunk/src/mame/drivers/raiden2.c
r32760	r32761
134	134
135	135	High Priority
136	136
137		Protection
	137	Protection
138	138	- zeroteam has bogus collision detection;
139	139	- raiden2 has a weird movement after that the ship completes animation from the aircraft. Probably 42c2 should be floating point rounded ...
140	140	- (and probably more)
141
	141
142	142	Unemulated 0-0x3ffff ROM banking for raidendx, but it's unknown if/where it's used (hopefully NOT on getting perfect on Alpha course).
143	143
144	144	zeroteam - sort-DMA doesn't seem to work too well, sprite-sprite priorities are broken as per now
145
	145
146	146	xsedae - do an "8-liner"-style scroll during attract, doesn't work too well.
147
	147
148	148	sprite chip is the same as seibuspi.c and feversoc.c, needs device-ification and merging.
149
150		sprite chip also uses first entry for "something" that isn't sprite, some of them looks clipping
	149
	150	sprite chip also uses first entry for "something" that isn't sprite, some of them looks clipping
151	151	regions (150 - ff in zeroteam, 150 - 0 and 150 - 80 in raiden2). Latter probably do double buffering
152	152	on odd/even frames, by updating only top or bottom part of screen.
153	153
r32760	r32761
180	180	save_item(NAME(cop_spr_maxx));
181	181	save_item(NAME(cop_spr_off));
182	182
183
	183
184	184	save_item(NAME(scrollvals));
185	185
186	186	save_item(NAME(sprite_prot_src_addr));
r32760	r32761
190	190	/*
191	191	UINT16 raiden2_state::rps()
192	192	{
193		return m_maincpu->state_int(NEC_CS);
	193	return m_maincpu->state_int(NEC_CS);
194	194	}
195	195
196	196	UINT16 raiden2_state::rpc()
197	197	{
198		return m_maincpu->state_int(NEC_IP);
	198	return m_maincpu->state_int(NEC_IP);
199	199	}
200	200	*/
201	201
r32760	r32761
843	843	dst1 += 8;
844	844	}
845	845	//printf("[%08x] %08x %08x %04x %04x\n",src,dx,dy,dst1,dst2);
846		// debugger_break(machine());
	846	// debugger_break(machine());
847	847	}
848	848
849	849	READ16_MEMBER(raiden2_state::sprite_prot_dst1_r)

trunk/src/mame/drivers/iqblock.c
r32760	r32761
214	214	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
215	215	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
216	216	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 )
217		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 )
	217	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 )
218	218
219	219	PORT_START("P2")
220	220	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN2 )
r32760	r32761
227	227	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_COCKTAIL
228	228
229	229	PORT_START("EXTRA")
230		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 )
231		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON4 )
	230	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 )
	231	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON4 )
232	232	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_COCKTAIL
233	233	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_COCKTAIL
234	234	PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )

trunk/src/mame/drivers/jeutel.c
r32760	r32761
11	11
12	12	ToDo:
13	13	- Everything!
14		- Each machine has 4 players, 7-digit, 12-segment florescent display
	14	- Each machine has 4 players, 7-digit, 12-segment florescent display
15	15
16	16	********************************************************************************/
17	17

trunk/src/mame/drivers/rastersp.c
r32760	r32761
855	855
856	856	MCFG_CPU_ADD("dsp", TMS32031, 33330000)
857	857	MCFG_CPU_PROGRAM_MAP(dsp_map)
858		MCFG_TMS3203X_MCBL(true) // Boot-loader mode
	858	MCFG_TMS3203X_MCBL(true) // Boot-loader mode
859	859
860	860	/* Devices */
861	861	MCFG_TIMER_DRIVER_ADD("tms_timer1", rastersp_state, tms_timer1)

trunk/src/mame/drivers/model3.c
r32760	r32761
32	32	von2/von254g - works
33	33	fvipers2 - waiting for decrementer (same code as eca)
34	34	vs298 - works, hangs with an onscreen error code
35		vs299/vs2v991 - works
36		oceanhun - same as daytona2
37		lamachin - works
	35	vs299/vs2v991 - works
	36	oceanhun - same as daytona2
	37	lamachin - works
38	38
39	39	dayto2pe - bug in DRC MMU page-fault handling, causes infinite loop at PC:0x2270 (or debug assert)
40	40	daytona2 - As above.
41	41	spikeout/spikeofe - As above.
42	42	dirtdvls/dirtdvla - works
43		swtrilgy -
44		swtrilga -
	43	swtrilgy -
	44	swtrilga -
45	45	magtruck - works, broken FPU values in matrices during 2nd part of attract mode (cpu core bug?)
46	46	eca/ecax - cabinet network error
47	47
r32760	r32761
1615	1615	{
1616	1616	UINT8 res = 0;
1617	1617	res \|= 1;
1618		res \|= 0x2; // magtruck country check
	1618	res \|= 0x2; // magtruck country check
1619	1619	return res;
1620	1620	}
1621	1621	}
r32760	r32761
5401	5401	0x02: Video (VBLANK start?)
5402	5402	0x01: Video (unused?)
5403	5403
5404		IRQ 0x08 and 0x04 directly affect the game speed in magtruck, once per scanline seems fast enough
5405		Un-syncing the interrupts breaks the progress bar in magtruck
	5404	IRQ 0x08 and 0x04 directly affect the game speed in magtruck, once per scanline seems fast enough
	5405	Un-syncing the interrupts breaks the progress bar in magtruck
5406	5406	*/
5407	5407	TIMER_DEVICE_CALLBACK_MEMBER(model3_state::model3_interrupt)
5408	5408	{
r32760	r32761
5694	5694	DRIVER_INIT_CALL(model3_15);
5695	5695
5696	5696	m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xc1000000, 0xc10000ff, read64_delegate(FUNC(model3_state::scsi_r),this), write64_delegate(FUNC(model3_state::scsi_w),this));
5697
5698		// rom[(0x73fe38^4)/4] = 0x38840004; /* This seems to be an actual bug in the original code */
	5697
	5698	// rom[(0x73fe38^4)/4] = 0x38840004; /* This seems to be an actual bug in the original code */
5699	5699	}
5700	5700
5701	5701	DRIVER_INIT_MEMBER(model3_state,vf3)
r32760	r32761
5826	5826
5827	5827
5828	5828	DRIVER_INIT_MEMBER(model3_state,srally2)
5829		{
	5829	{
5830	5830	DRIVER_INIT_CALL(model3_20);
5831	5831
5832	5832
5833		UINT32 rom = (UINT32)memregion("user1")->base();
	5833	UINT32 rom = (UINT32)memregion("user1")->base();
5834	5834	rom[(0x7c0c4^4)/4] = 0x60000000;
5835	5835	rom[(0x7c0c8^4)/4] = 0x60000000;
5836	5836	rom[(0x7c0cc^4)/4] = 0x60000000;
r32760	r32761
5850	5850	rom[(0xf7770^4)/4] = 0x60000000;
5851	5851	rom[(0xf7774^4)/4] = 0x60000000;
5852	5852
5853		rom[(0x043dc^4)/4] = 0x48000090; // skip force feedback setup
	5853	rom[(0x043dc^4)/4] = 0x48000090; // skip force feedback setup
5854	5854	rom[(0xf6e44^4)/4] = 0x60000000;
5855	5855	}
5856	5856
r32760	r32761
5865	5865	DRIVER_INIT_MEMBER(model3_state,von2)
5866	5866	{
5867	5867	m_step20_with_old_real3d = true;
5868
	5868
5869	5869	DRIVER_INIT_CALL(model3_20);
5870	5870	}
5871	5871

trunk/src/mame/drivers/cps1.c
r32760	r32761
6834	6834	ROM_CONTINUE( 0x000006, 0x80000)
6835	6835	ROMX_LOAD( "b-se194.bin", 0x200000, 0x80000, CRC(5726cab8) SHA1(0b2243a9a7184d53d42ddab7a8c51b63001c2f56) , ROM_GROUPWORD \| ROM_SKIP(6) )
6836	6836	ROM_CONTINUE( 0x200004, 0x80000)
6837		ROMX_LOAD( "d-se064.bin", 0x200002, 0x80000, CRC(4dd24197) SHA1(548beaa0a6f1c3c88f4fc83169d1a3c86e0755d4) , ROM_GROUPWORD \| ROM_SKIP(6) ) //sf2-8m.6c 99.999809%
	6837	ROMX_LOAD( "d-se064.bin", 0x200002, 0x80000, CRC(4dd24197) SHA1(548beaa0a6f1c3c88f4fc83169d1a3c86e0755d4) , ROM_GROUPWORD \| ROM_SKIP(6) ) //sf2-8m.6c 99.999809%
6838	6838	ROM_CONTINUE( 0x200006, 0x80000)
6839	6839	ROMX_LOAD( "e-sf004.bin", 0x400000, 0x80000, CRC(187667cc) SHA1(fae65bf23f49a32903fda8080659ccf8d42b911f) , ROM_GROUPWORD \| ROM_SKIP(6) )
6840	6840	ROM_CONTINUE( 0x400004, 0x80000)
6841	6841	ROMX_LOAD( "f-sf001.bin", 0x400002, 0x80000, CRC(5b585071) SHA1(ad3371b1ba0441c67d9fcbb23b09464710e4e28a) , ROM_GROUPWORD \| ROM_SKIP(6) )
6842	6842	ROM_CONTINUE( 0x400006, 0x80000)
6843
	6843
6844	6844	// These map over the MASK roms on this bootleg why? isn't it a waste of eprom?
6845	6845	ROMX_LOAD( "27c1024.10", 0x400000, 0x20000, CRC(84427d1b) SHA1(f988a2b53c8cc46eeb8032084f24966a539b3734) , ROM_GROUPWORD \| ROM_SKIP(6) )//e-sf004.bin [1/8] IDENTICAL
6846	6846	ROMX_LOAD( "27c1024.12", 0x400002, 0x20000, CRC(55bc790c) SHA1(a1114b89f6fa4487210477676984c77ad94b5ef8) , ROM_GROUPWORD \| ROM_SKIP(6) )//f-sf001.bin [1/8] IDENTICAL
r32760	r32761
6867	6867
6868	6868	ROM_REGION( 0x600000, "gfx", 0 )
6869	6869	/* There are 8 mask and 8 otp eprom on this board, data match sf2 set in the end */
6870		ROMX_LOAD( "1-b-yf197.07", 0x000000, 0x80000, CRC(22c9cc8e) SHA1(b9194fb337b30502c1c9501cd6c64ae4035544d4) , ROM_GROUPWORD \| ROM_SKIP(6) )
6871		ROMX_LOAD( "1-d-yf207.12", 0x000002, 0x80000, CRC(57213be8) SHA1(3759b851ac0904ec79cbb67a2264d384b6f2f9f9) , ROM_GROUPWORD \| ROM_SKIP(6) )
6872		ROMX_LOAD( "27020.1", 0x000004, 0x40000, CRC(84afb959) SHA1(ff8f3fb39203d229552649b09046a509aa399b7d) , ROM_SKIP(7) )
6873		ROMX_LOAD( "27020.3", 0x000005, 0x40000, CRC(ab21635d) SHA1(c6294b06c482a43cc1736674b0c1bc790da8cc8c) , ROM_SKIP(7) )
6874		ROMX_LOAD( "27020.5", 0x000006, 0x40000, CRC(2ce56f9f) SHA1(5bd23823df52aeff8e84a6eb3199a5e75f38cd42) , ROM_SKIP(7) )
6875		ROMX_LOAD( "27020.7", 0x000007, 0x40000, CRC(0ad7fb2b) SHA1(51265b331cbbe9d133274bafdbf043151240a20d) , ROM_SKIP(7) )
6876
6877		ROMX_LOAD( "27020.2", 0x200000, 0x40000, CRC(031525cc) SHA1(65e280607c058cf9c005a6fc809ed375d379c0bf) , ROM_SKIP(7) )
6878		ROMX_LOAD( "27020.4", 0x200001, 0x40000, CRC(c97046a5) SHA1(88c7becaa2713c85e22ddd3e2305770525a9132b) , ROM_SKIP(7) )
6879		ROMX_LOAD( "1-h-yg010.10", 0x200002, 0x80000, CRC(b5548f17) SHA1(baa92b91cf616bc9e2a8a66adc777ffbf962a51b) , ROM_GROUPWORD \| ROM_SKIP(6) )
6880		ROMX_LOAD( "1-e-yg003.02", 0x200004, 0x80000, CRC(14b84312) SHA1(2eea16673e60ba7a10bd4d8f6c217bb2441a5b0e) , ROM_GROUPWORD \| ROM_SKIP(6) )
6881		ROMX_LOAD( "27020.6", 0x200006, 0x40000, CRC(dbbfd400) SHA1(fc25928b6ed025fa2397d924bae93fd28a4e728f) , ROM_SKIP(7) )
6882		ROMX_LOAD( "27020.8", 0x200007, 0x40000, CRC(37635e97) SHA1(b4e5dd6e93174af76aaeeb47471ded0d0bc253e2) , ROM_SKIP(7) )
6883
6884		ROMX_LOAD( "1-j-yf213.09", 0x400000, 0x80000, CRC(994bfa58) SHA1(5669b845f624b10e7be56bfc89b76592258ce48b) , ROM_GROUPWORD \| ROM_SKIP(6) )
	6870	ROMX_LOAD( "1-b-yf197.07", 0x000000, 0x80000, CRC(22c9cc8e) SHA1(b9194fb337b30502c1c9501cd6c64ae4035544d4) , ROM_GROUPWORD \| ROM_SKIP(6) )
	6871	ROMX_LOAD( "1-d-yf207.12", 0x000002, 0x80000, CRC(57213be8) SHA1(3759b851ac0904ec79cbb67a2264d384b6f2f9f9) , ROM_GROUPWORD \| ROM_SKIP(6) )
	6872	ROMX_LOAD( "27020.1", 0x000004, 0x40000, CRC(84afb959) SHA1(ff8f3fb39203d229552649b09046a509aa399b7d) , ROM_SKIP(7) )
	6873	ROMX_LOAD( "27020.3", 0x000005, 0x40000, CRC(ab21635d) SHA1(c6294b06c482a43cc1736674b0c1bc790da8cc8c) , ROM_SKIP(7) )
	6874	ROMX_LOAD( "27020.5", 0x000006, 0x40000, CRC(2ce56f9f) SHA1(5bd23823df52aeff8e84a6eb3199a5e75f38cd42) , ROM_SKIP(7) )
	6875	ROMX_LOAD( "27020.7", 0x000007, 0x40000, CRC(0ad7fb2b) SHA1(51265b331cbbe9d133274bafdbf043151240a20d) , ROM_SKIP(7) )
	6876
	6877	ROMX_LOAD( "27020.2", 0x200000, 0x40000, CRC(031525cc) SHA1(65e280607c058cf9c005a6fc809ed375d379c0bf) , ROM_SKIP(7) )
	6878	ROMX_LOAD( "27020.4", 0x200001, 0x40000, CRC(c97046a5) SHA1(88c7becaa2713c85e22ddd3e2305770525a9132b) , ROM_SKIP(7) )
	6879	ROMX_LOAD( "1-h-yg010.10", 0x200002, 0x80000, CRC(b5548f17) SHA1(baa92b91cf616bc9e2a8a66adc777ffbf962a51b) , ROM_GROUPWORD \| ROM_SKIP(6) )
	6880	ROMX_LOAD( "1-e-yg003.02", 0x200004, 0x80000, CRC(14b84312) SHA1(2eea16673e60ba7a10bd4d8f6c217bb2441a5b0e) , ROM_GROUPWORD \| ROM_SKIP(6) )
	6881	ROMX_LOAD( "27020.6", 0x200006, 0x40000, CRC(dbbfd400) SHA1(fc25928b6ed025fa2397d924bae93fd28a4e728f) , ROM_SKIP(7) )
	6882	ROMX_LOAD( "27020.8", 0x200007, 0x40000, CRC(37635e97) SHA1(b4e5dd6e93174af76aaeeb47471ded0d0bc253e2) , ROM_SKIP(7) )
	6883
	6884	ROMX_LOAD( "1-j-yf213.09", 0x400000, 0x80000, CRC(994bfa58) SHA1(5669b845f624b10e7be56bfc89b76592258ce48b) , ROM_GROUPWORD \| ROM_SKIP(6) )
6885	6885	ROMX_LOAD( "wm91m-11-yd025.11", 0x400002, 0x80000, CRC(3e66ad9d) SHA1(9af9df0826988872662753e9717c48d46f2974b0) , ROM_GROUPWORD \| ROM_SKIP(6) )
6886		ROMX_LOAD( "1-i-yf224.03", 0x400004, 0x80000, CRC(c1befaa8) SHA1(a6a7f4725e52678cbd8d557285c01cdccb2c2602) , ROM_GROUPWORD \| ROM_SKIP(6) )
6887		ROMX_LOAD( "1-k-yf036.06", 0x400006, 0x80000, CRC(0627c831) SHA1(f9a92d614e8877d648449de2612fc8b43c85e4c2) , ROM_GROUPWORD \| ROM_SKIP(6) )
6888
	6886	ROMX_LOAD( "1-i-yf224.03", 0x400004, 0x80000, CRC(c1befaa8) SHA1(a6a7f4725e52678cbd8d557285c01cdccb2c2602) , ROM_GROUPWORD \| ROM_SKIP(6) )
	6887	ROMX_LOAD( "1-k-yf036.06", 0x400006, 0x80000, CRC(0627c831) SHA1(f9a92d614e8877d648449de2612fc8b43c85e4c2) , ROM_GROUPWORD \| ROM_SKIP(6) )
	6888
6889	6889	/* These map over the MASK roms on this bootleg to get rid of the CAPCOM logo (wasteful, but correct) */
6890	6890	ROMX_LOAD( "27010.09hi", 0x400000, 0x10000, CRC(a505621e) SHA1(8ffa8cedad54948870bbd8f629d927332dc9fcf6) , ROM_SKIP(7) )
6891	6891	ROM_CONTINUE( 0x400004, 0x10000 )
r32760	r32761
11613	11613	GAME( 1991, sf2jl, sf2, cps1_10MHz, sf2j, cps_state, cps1, ROT0, "Capcom", "Street Fighter II: The World Warrior (Japan 920312)", GAME_SUPPORTS_SAVE )
11614	11614	GAME( 1992, sf2ebbl, sf2, cps1_10MHz, sf2hack, cps_state, sf2hack, ROT0, "bootleg", "Street Fighter II: The World Warrior (TAB Austria, bootleg, set 1)", GAME_SUPPORTS_SAVE ) // 910214 - based on World version
11615	11615	GAME( 1992, sf2ebbl2, sf2, cps1_10MHz, sf2hack, cps_state, sf2hack, ROT0, "bootleg", "Street Fighter II: The World Warrior (TAB Austria, bootleg, set 3)", GAME_SUPPORTS_SAVE ) // 910214 - based on World version
11616		GAME( 1992, sf2ebbl3, sf2, cps1_10MHz, sf2hack, cps_state, sf2hack, ROT0, "bootleg", "Street Fighter II: The World Warrior (TAB Austria, bootleg, set 4)", GAME_SUPPORTS_SAVE ) // 910214 - based on World version
	11616	GAME( 1992, sf2ebbl3, sf2, cps1_10MHz, sf2hack, cps_state, sf2hack, ROT0, "bootleg", "Street Fighter II: The World Warrior (TAB Austria, bootleg, set 4)", GAME_SUPPORTS_SAVE ) // 910214 - based on World version
11617	11617	GAME( 1992, sf2stt, sf2, cps1_10MHz, sf2hack, cps_state, sf2hack, ROT0, "bootleg", "Street Fighter II: The World Warrior (TAB Austria, bootleg, set 2)", GAME_NOT_WORKING \| GAME_SUPPORTS_SAVE ) // 910214 - based on World version
11618	11618	GAME( 1992, sf2rk, sf2, cps1_10MHz, sf2hack, cps_state, sf2hack, ROT0, "bootleg", "Street Fighter II: The World Warrior (RK, bootleg)", GAME_NOT_WORKING \| GAME_SUPPORTS_SAVE ) // 920211 (pcb)
11619	11619	GAME( 1991, sf2qp1, sf2, cps1_10MHz, sf2, cps_state, cps1, ROT0, "bootleg", "Street Fighter II: The World Warrior (Quicken Pt-I, bootleg)", GAME_SUPPORTS_SAVE ) // 910214 - based on World version

trunk/src/mame/drivers/jchan.c
r32760	r32761
201	201	required_device<sknsspr_device> m_spritegen1;
202	202	required_device<sknsspr_device> m_spritegen2;
203	203	required_device<kaneko_view2_tilemap_device> m_view2_0;
204
	204
205	205	required_shared_ptr<UINT16> m_spriteram_1;
206	206	required_shared_ptr<UINT16> m_sprregs_1;
207	207	required_shared_ptr<UINT16> m_spriteram_2;

trunk/src/mame/drivers/hikaru.c
r32760	r32761
622	622
623	623	/* ROM board using 64M SOP44 MASKROM */
624	624	ROM_REGION( 0x10000000, "user2", 0)
625		ROM_LOAD("mpr-23086.ic37" , 0x0000000, 0x0800000, CRC(ef6f20f1) SHA1(11fb66bf71223b4c6650d3adaea21e8709b8d67b))
626		ROM_LOAD("mpr-23087.ic38" , 0x0800000, 0x0800000, CRC(54389822) SHA1(6357f0aa77ef0a5a08a751e085fa026d26ba47d1))
627		ROM_LOAD("mpr-23088.ic39" , 0x1000000, 0x0800000, CRC(9f1a382e) SHA1(b846c3a091d04e49cc1e731237c9326ccac39a64))
628		ROM_LOAD("mpr-23089.ic40" , 0x1800000, 0x0800000, CRC(6aae64fc) SHA1(392b6fba25d20bb41fd72be3a3a9ce95b2374065))
629		ROM_LOAD("mpr-23090.ic41" , 0x2000000, 0x0800000, CRC(ba857872) SHA1(c07ff7955d3d07f2a60d9761b4bd692c0a9c9353))
630		ROM_LOAD("mpr-23091.ic42" , 0x2800000, 0x0800000, CRC(66a73e27) SHA1(c4e7d190a80499225a78b7f788c2abc7ec4ebdca))
631		ROM_LOAD("mpr-23092.ic43" , 0x3000000, 0x0800000, CRC(4f20a0f5) SHA1(0580feba6a6dd01a21d09ec2503ccf77030f8d2a))
632		ROM_LOAD("mpr-23093.ic44" , 0x3800000, 0x0800000, CRC(e74d7d64) SHA1(c28e44319bf08aedd9aed625a12834ec76f1e5e0))
633		ROM_LOAD("mpr-23094.ic45" , 0x4000000, 0x0800000, CRC(90f04c14) SHA1(b55846ea1edd920fd527e3257b13fea8df1f713f))
634		ROM_LOAD("mpr-23095.ic46" , 0x4800000, 0x0800000, CRC(cc67cb5b) SHA1(85e99ec22d1c65139685a94f1ba0c52a0eb33a2e))
635		ROM_LOAD("mpr-23096.ic47" , 0x5000000, 0x0800000, CRC(799ab79e) SHA1(c0ac85ad7f4cf46ff162f1ec2e85a3f22817de5e))
636		ROM_LOAD("mpr-23097.ic48" , 0x5800000, 0x0800000, CRC(f68439de) SHA1(475d0f22e78e3c86431b742e37cbfd764ca8acee))
637		ROM_LOAD("mpr-23098.ic49" , 0x6000000, 0x0800000, CRC(a1e2009c) SHA1(c6a600d47fd2a96d28c637631862150e6f303c3d))
638		ROM_LOAD("mpr-23099.ic50" , 0x6800000, 0x0800000, CRC(ce36f642) SHA1(6cb2e69095efc7969255ebc637e2597c56442751))
639		ROM_LOAD("mpr-23100.ic51" , 0x7000000, 0x0800000, CRC(0f966653) SHA1(1544af662188ea734e0a2e559e05e5f782fb292d))
640		ROM_LOAD("mpr-23101.ic52" , 0x7800000, 0x0800000, CRC(2640fbaa) SHA1(59e9bd143734c71968beb9953122680d3350e69c))
641		ROM_LOAD("mpr-23102.ic53" , 0x8000000, 0x0800000, CRC(080c5bcb) SHA1(0cf54348420ae9866edd64422cb82464990f1f2f))
642		ROM_LOAD("mpr-23103.ic54" , 0x8800000, 0x0800000, CRC(19c7758f) SHA1(fed7f45dd91e1cb6bba7d8e80ed17dca27d92e43))
643		ROM_LOAD("mpr-23104.ic55" , 0x9000000, 0x0800000, CRC(4ca74216) SHA1(0e65971359ba0e2b4fc032a26d1c10d8efadc205))
644		ROM_LOAD("mpr-23105.ic56" , 0x9800000, 0x0800000, CRC(e2dd35ba) SHA1(2213e3195a49532a177086de8134ce8b753fc7ce))
645		ROM_LOAD("mpr-23106.ic57" , 0xa000000, 0x0800000, CRC(dd325515) SHA1(8144e1a87f7d72a18791d1d452123a91cfb354dd))
646		ROM_LOAD("mpr-23107.ic58" , 0xa800000, 0x0800000, CRC(a527a22a) SHA1(54c105b21797c9b0a2a6b2c7091de726c49a55e8))
647		ROM_LOAD("mpr-23108.ic59" , 0xb000000, 0x0800000, CRC(47817d9a) SHA1(d2c6f1b2e800448eaf694d550733bba2280b6746))
648		ROM_LOAD("mpr-23109.ic60" , 0xb800000, 0x0800000, CRC(8c61dec4) SHA1(25a1a5b236b3aed013fc94bd9695906ae5d7f305))
649		ROM_LOAD("mpr-23110.ic61" , 0xc000000, 0x0800000, CRC(4ddae9f1) SHA1(d1c5e3f18932af806f166779cf14909ab17d052c))
650		ROM_LOAD("mpr-23111.ic62" , 0xc800000, 0x0800000, CRC(c404cb1c) SHA1(e14855ec8a5a5ba243a2339c571928fdcc187157))
651		ROM_LOAD("mpr-23112.ic63" , 0xd000000, 0x0800000, CRC(d001fe59) SHA1(ab395d2933b5d691259221168dfaa063cf9a4d1c))
652		ROM_LOAD("mpr-23113.ic64" , 0xd800000, 0x0800000, CRC(f241cfd5) SHA1(5b85e8b50559becff7a76565c95487825bbd9351))
653		ROM_LOAD("mpr-23114.ic65" , 0xe000000, 0x0800000, CRC(80049d7c) SHA1(56aab53e9317b1b5d10bd2af78fd83e7422d8939))
654		ROM_LOAD("mpr-23115.ic66" , 0xe800000, 0x0800000, CRC(4fc540fe) SHA1(df580421d856566e067c2b319c8ac4671629682f))
655		ROM_LOAD("mpr-23116.ic67" , 0xf000000, 0x0800000, CRC(9f567fce) SHA1(c35bcf968f139557e50ceafa9c6bad4deb87154f))
656		ROM_LOAD("mpr-23117.ic68" , 0xf800000, 0x0800000, CRC(9d4d3529) SHA1(66008445629681ebf2f26b3f181d8524a8576d2f))
	625	ROM_LOAD("mpr-23086.ic37" , 0x0000000, 0x0800000, CRC(ef6f20f1) SHA1(11fb66bf71223b4c6650d3adaea21e8709b8d67b))
	626	ROM_LOAD("mpr-23087.ic38" , 0x0800000, 0x0800000, CRC(54389822) SHA1(6357f0aa77ef0a5a08a751e085fa026d26ba47d1))
	627	ROM_LOAD("mpr-23088.ic39" , 0x1000000, 0x0800000, CRC(9f1a382e) SHA1(b846c3a091d04e49cc1e731237c9326ccac39a64))
	628	ROM_LOAD("mpr-23089.ic40" , 0x1800000, 0x0800000, CRC(6aae64fc) SHA1(392b6fba25d20bb41fd72be3a3a9ce95b2374065))
	629	ROM_LOAD("mpr-23090.ic41" , 0x2000000, 0x0800000, CRC(ba857872) SHA1(c07ff7955d3d07f2a60d9761b4bd692c0a9c9353))
	630	ROM_LOAD("mpr-23091.ic42" , 0x2800000, 0x0800000, CRC(66a73e27) SHA1(c4e7d190a80499225a78b7f788c2abc7ec4ebdca))
	631	ROM_LOAD("mpr-23092.ic43" , 0x3000000, 0x0800000, CRC(4f20a0f5) SHA1(0580feba6a6dd01a21d09ec2503ccf77030f8d2a))
	632	ROM_LOAD("mpr-23093.ic44" , 0x3800000, 0x0800000, CRC(e74d7d64) SHA1(c28e44319bf08aedd9aed625a12834ec76f1e5e0))
	633	ROM_LOAD("mpr-23094.ic45" , 0x4000000, 0x0800000, CRC(90f04c14) SHA1(b55846ea1edd920fd527e3257b13fea8df1f713f))
	634	ROM_LOAD("mpr-23095.ic46" , 0x4800000, 0x0800000, CRC(cc67cb5b) SHA1(85e99ec22d1c65139685a94f1ba0c52a0eb33a2e))
	635	ROM_LOAD("mpr-23096.ic47" , 0x5000000, 0x0800000, CRC(799ab79e) SHA1(c0ac85ad7f4cf46ff162f1ec2e85a3f22817de5e))
	636	ROM_LOAD("mpr-23097.ic48" , 0x5800000, 0x0800000, CRC(f68439de) SHA1(475d0f22e78e3c86431b742e37cbfd764ca8acee))
	637	ROM_LOAD("mpr-23098.ic49" , 0x6000000, 0x0800000, CRC(a1e2009c) SHA1(c6a600d47fd2a96d28c637631862150e6f303c3d))
	638	ROM_LOAD("mpr-23099.ic50" , 0x6800000, 0x0800000, CRC(ce36f642) SHA1(6cb2e69095efc7969255ebc637e2597c56442751))
	639	ROM_LOAD("mpr-23100.ic51" , 0x7000000, 0x0800000, CRC(0f966653) SHA1(1544af662188ea734e0a2e559e05e5f782fb292d))
	640	ROM_LOAD("mpr-23101.ic52" , 0x7800000, 0x0800000, CRC(2640fbaa) SHA1(59e9bd143734c71968beb9953122680d3350e69c))
	641	ROM_LOAD("mpr-23102.ic53" , 0x8000000, 0x0800000, CRC(080c5bcb) SHA1(0cf54348420ae9866edd64422cb82464990f1f2f))
	642	ROM_LOAD("mpr-23103.ic54" , 0x8800000, 0x0800000, CRC(19c7758f) SHA1(fed7f45dd91e1cb6bba7d8e80ed17dca27d92e43))
	643	ROM_LOAD("mpr-23104.ic55" , 0x9000000, 0x0800000, CRC(4ca74216) SHA1(0e65971359ba0e2b4fc032a26d1c10d8efadc205))
	644	ROM_LOAD("mpr-23105.ic56" , 0x9800000, 0x0800000, CRC(e2dd35ba) SHA1(2213e3195a49532a177086de8134ce8b753fc7ce))
	645	ROM_LOAD("mpr-23106.ic57" , 0xa000000, 0x0800000, CRC(dd325515) SHA1(8144e1a87f7d72a18791d1d452123a91cfb354dd))
	646	ROM_LOAD("mpr-23107.ic58" , 0xa800000, 0x0800000, CRC(a527a22a) SHA1(54c105b21797c9b0a2a6b2c7091de726c49a55e8))
	647	ROM_LOAD("mpr-23108.ic59" , 0xb000000, 0x0800000, CRC(47817d9a) SHA1(d2c6f1b2e800448eaf694d550733bba2280b6746))
	648	ROM_LOAD("mpr-23109.ic60" , 0xb800000, 0x0800000, CRC(8c61dec4) SHA1(25a1a5b236b3aed013fc94bd9695906ae5d7f305))
	649	ROM_LOAD("mpr-23110.ic61" , 0xc000000, 0x0800000, CRC(4ddae9f1) SHA1(d1c5e3f18932af806f166779cf14909ab17d052c))
	650	ROM_LOAD("mpr-23111.ic62" , 0xc800000, 0x0800000, CRC(c404cb1c) SHA1(e14855ec8a5a5ba243a2339c571928fdcc187157))
	651	ROM_LOAD("mpr-23112.ic63" , 0xd000000, 0x0800000, CRC(d001fe59) SHA1(ab395d2933b5d691259221168dfaa063cf9a4d1c))
	652	ROM_LOAD("mpr-23113.ic64" , 0xd800000, 0x0800000, CRC(f241cfd5) SHA1(5b85e8b50559becff7a76565c95487825bbd9351))
	653	ROM_LOAD("mpr-23114.ic65" , 0xe000000, 0x0800000, CRC(80049d7c) SHA1(56aab53e9317b1b5d10bd2af78fd83e7422d8939))
	654	ROM_LOAD("mpr-23115.ic66" , 0xe800000, 0x0800000, CRC(4fc540fe) SHA1(df580421d856566e067c2b319c8ac4671629682f))
	655	ROM_LOAD("mpr-23116.ic67" , 0xf000000, 0x0800000, CRC(9f567fce) SHA1(c35bcf968f139557e50ceafa9c6bad4deb87154f))
	656	ROM_LOAD("mpr-23117.ic68" , 0xf800000, 0x0800000, CRC(9d4d3529) SHA1(66008445629681ebf2f26b3f181d8524a8576d2f))
657	657	ROM_END
658	658
659	659	ROM_START( braveff )

trunk/src/mame/drivers/cv1k.c
r32760	r32761
514	514	ROM_RELOAD(0x200000,0x200000)
515	515
516	516	ROM_REGION( 0x8400000, "game", ROMREGION_ERASEFF)
517		// ROM_LOAD("mushisama_u2", 0x000000, 0x8400000, CRC(f1e0cf65) SHA1(d00d950422309fdf08efe1e2d5f040beb45ee6fb) ) // bad rom, one corrupt asset vs. below
	517	// ROM_LOAD("mushisama_u2", 0x000000, 0x8400000, CRC(f1e0cf65) SHA1(d00d950422309fdf08efe1e2d5f040beb45ee6fb) ) // bad rom, one corrupt asset vs. below
518	518	ROM_LOAD("mushisam_u2", 0x000000, 0x8400000, CRC(4f0a842a) SHA1(33f3550ec676a7088b6348cd72c16cc6594afb84) ) /* (2004/10/12.MASTER VER.) */
519	519
520	520	ROM_REGION( 0x800000, "ymz770", ROMREGION_ERASEFF)
r32760	r32761
528	528	ROM_RELOAD(0x200000,0x200000)
529	529
530	530	ROM_REGION( 0x8400000, "game", ROMREGION_ERASEFF)
531		// ROM_LOAD("mushisamb_u2", 0x000000, 0x8400000, CRC(6cc9d1a9) SHA1(17907798dce1defadd10354cec6c8d364e045570) ) // bad rom, one corrupt asset vs. below
	531	// ROM_LOAD("mushisamb_u2", 0x000000, 0x8400000, CRC(6cc9d1a9) SHA1(17907798dce1defadd10354cec6c8d364e045570) ) // bad rom, one corrupt asset vs. below
532	532	ROM_LOAD("mushisam_u2", 0x000000, 0x8400000, CRC(4f0a842a) SHA1(33f3550ec676a7088b6348cd72c16cc6594afb84) ) /* (2004/10/12.MASTER VER.) */
533	533
534	534	ROM_REGION( 0x800000, "ymz770", ROMREGION_ERASEFF)
r32760	r32761
568	568	ROM_RELOAD(0x200000,0x200000)
569	569
570	570	ROM_REGION( 0x8400000, "game", ROMREGION_ERASEFF)
571		// ROM_LOAD("mushitama_u2", 0x000000, 0x8400000, CRC(3f93ff82) SHA1(6f6c250aa7134016ffb288d056bc937ea311f538) ) // recycled ROM - only unused areas differ
	571	// ROM_LOAD("mushitama_u2", 0x000000, 0x8400000, CRC(3f93ff82) SHA1(6f6c250aa7134016ffb288d056bc937ea311f538) ) // recycled ROM - only unused areas differ
572	572	ROM_LOAD("mushitam_u2", 0x000000, 0x8400000, CRC(8ba498ab) SHA1(459c0b4ab831bbe019bdd5b0ac56955948b9e3a6) ) /* (2005/09/09.MASTER VER) */
573	573
574	574	ROM_REGION( 0x800000, "ymz770", ROMREGION_ERASEFF)
r32760	r32761
595	595	ROM_RELOAD(0x200000,0x200000)
596	596
597	597	ROM_REGION( 0x8400000, "game", ROMREGION_ERASEFF)
598		// ROM_LOAD("futari15a_u2", 0x000000, 0x8400000, CRC(b9d815f9) SHA1(6b6f668b0bbb087ffac65e4f0d8bd9d5b28eeb28) ) // recycled ROM - only unused areas differ
	598	// ROM_LOAD("futari15a_u2", 0x000000, 0x8400000, CRC(b9d815f9) SHA1(6b6f668b0bbb087ffac65e4f0d8bd9d5b28eeb28) ) // recycled ROM - only unused areas differ
599	599	ROM_LOAD("futari15_u2", 0x000000, 0x8400000, CRC(b9eae1fc) SHA1(410f8e7cfcbfd271b41fb4f8d049a13a3191a1f9) ) /* (2006/12/8.MAST VER. 1.54.) */
600	600
601	601	ROM_REGION( 0x800000, "ymz770", ROMREGION_ERASEFF)

trunk/src/mame/drivers/capr1.c
r32760	r32761
3	3	/***************************************************************************
4	4
5	5	Taito Capriccio Z80 crane hardware (let's call it 1st generation)
6
	6
7	7	These are presumed to be on similar hardware:
8	8	- Capriccio 1991
9	9	- New Capriccio 1992
r32760	r32761
11	11	- New Capriccio 2 1993
12	12	- Capriccio Spin 1994
13	13	- Capriccio Spin 2 1996
14
	14
15	15	The next released game of this series is Capriccio Cyclone, see caprcyc.c
16	16	More games were released after this.
17
	17
18	18	TODO:
19	19	- get cspin2 working a bit:
20	20	* unknown reads and writes
r32760	r32761
56	56	static ADDRESS_MAP_START( cspin2_map, AS_PROGRAM, 8, capr1_state )
57	57	AM_RANGE(0x0000, 0x7fff) AM_ROM
58	58	AM_RANGE(0x8000, 0x9fff) AM_RAM
59		// AM_RANGE(0xa000, 0xa01f) AM_RAM // wrong
	59	// AM_RANGE(0xa000, 0xa01f) AM_RAM // wrong
60	60	AM_RANGE(0xc000, 0xc001) AM_DEVREADWRITE("ym", ym2203_device, read, write)
61		// AM_RANGE(0xc004, 0xc005) AM_WRITENOP
62		// AM_RANGE(0xc008, 0xc009) AM_WRITENOP
63		// AM_RANGE(0xc00c, 0xc00d) AM_WRITENOP
64		// AM_RANGE(0xc00d, 0xc00d) AM_DEVREADWRITE("oki", okim6295_device, read, write)
	61	// AM_RANGE(0xc004, 0xc005) AM_WRITENOP
	62	// AM_RANGE(0xc008, 0xc009) AM_WRITENOP
	63	// AM_RANGE(0xc00c, 0xc00d) AM_WRITENOP
	64	// AM_RANGE(0xc00d, 0xc00d) AM_DEVREADWRITE("oki", okim6295_device, read, write)
65	65	ADDRESS_MAP_END
66	66
67	67
r32760	r32761
83	83	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 )
84	84	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 )
85	85	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 )
86
	86
87	87	PORT_START("IN1")
88	88	PORT_DIPUNKNOWN_DIPLOC( 0x01, 0x01, "SW1:1" )
89	89	PORT_DIPUNKNOWN_DIPLOC( 0x02, 0x02, "SW1:2" )

trunk/src/mame/drivers/8080bw.c
r32760	r32761
3193	3193	WRITE8_MEMBER(_8080bw_state::invmulti_bank_w)
3194	3194	{
3195	3195	m_invmulti_bank = data; //needed to restore the bankswitch post load
3196
	3196
3197	3197	// d0, d4, d6: bank
3198	3198	int bank = (data & 1) \| (data >> 3 & 2) \| (data >> 4 & 4);
3199	3199	membank("bank1")->set_base(memregion("maincpu")->base() + bank * 0x4000 + 0x0000);
r32760	r32761
3208	3208	MACHINE_RESET_MEMBER(_8080bw_state,invmulti)
3209	3209	{
3210	3210	m_invmulti_bank = 0;
3211
	3211
3212	3212	invmulti_bank_w(m_maincpu->space(AS_PROGRAM), 0, 0);
3213	3213
3214	3214	MACHINE_RESET_CALL_MEMBER(mw8080bw);
r32760	r32761
3234	3234	// decrypt rom
3235	3235	for (int i = 0; i < len; i++)
3236	3236	dest[i] = BITSWAP8(src[(i & 0x100ff) \| (BITSWAP8(i >> 8 & 0xff, 7,3,4,5,0,6,1,2) << 8)],0,6,5,7,4,3,1,2);
3237
	3237
3238	3238	save_item(NAME(m_invmulti_bank));
3239	3239	machine().save().register_postload(save_prepost_delegate(FUNC(_8080bw_state::invmulti_bankswitch_restore), this));
3240	3240	}

trunk/src/mame/drivers/taito_z.c
r32760	r32761
3043	3043	MCFG_TC0100SCN_PALETTE("palette")
3044	3044
3045	3045	MCFG_DEVICE_ADD("tc0150rod", TC0150ROD, 0)
3046
	3046
3047	3047	MCFG_TC0110PCR_ADD("tc0110pcr")
3048	3048	MCFG_TC0110PCR_PALETTE("palette")
3049	3049
r32760	r32761
3121	3121	MCFG_TC0100SCN_PALETTE("palette")
3122	3122
3123	3123	MCFG_DEVICE_ADD("tc0150rod", TC0150ROD, 0)
3124
	3124
3125	3125	MCFG_TC0110PCR_ADD("tc0110pcr")
3126	3126	MCFG_TC0110PCR_PALETTE("palette")
3127	3127
r32760	r32761
3201	3201	MCFG_TC0100SCN_PALETTE("palette")
3202	3202
3203	3203	MCFG_DEVICE_ADD("tc0150rod", TC0150ROD, 0)
3204
	3204
3205	3205	MCFG_TC0110PCR_ADD("tc0110pcr")
3206	3206	MCFG_TC0110PCR_PALETTE("palette")
3207	3207
r32760	r32761
3277	3277	MCFG_TC0100SCN_PALETTE("palette")
3278	3278
3279	3279	MCFG_DEVICE_ADD("tc0150rod", TC0150ROD, 0)
3280
	3280
3281	3281	/* sound hardware */
3282	3282	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
3283	3283
r32760	r32761
3358	3358	MCFG_TC0100SCN_PALETTE("palette")
3359	3359
3360	3360	MCFG_DEVICE_ADD("tc0150rod", TC0150ROD, 0)
3361
	3361
3362	3362	/* sound hardware */
3363	3363	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
3364	3364
r32760	r32761
3434	3434	MCFG_TC0100SCN_PALETTE("palette")
3435	3435
3436	3436	MCFG_DEVICE_ADD("tc0150rod", TC0150ROD, 0)
3437
	3437
3438	3438	MCFG_TC0110PCR_ADD("tc0110pcr")
3439	3439	MCFG_TC0110PCR_PALETTE("palette")
3440	3440
r32760	r32761
3514	3514	MCFG_TC0100SCN_PALETTE("palette")
3515	3515
3516	3516	MCFG_DEVICE_ADD("tc0150rod", TC0150ROD, 0)
3517
	3517
3518	3518	MCFG_TC0110PCR_ADD("tc0110pcr")
3519	3519	MCFG_TC0110PCR_PALETTE("palette")
3520	3520
r32760	r32761
3664	3664	MCFG_TC0480SCP_PALETTE("palette")
3665	3665
3666	3666	MCFG_DEVICE_ADD("tc0150rod", TC0150ROD, 0)
3667
	3667
3668	3668	/* sound hardware */
3669	3669	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
3670	3670
r32760	r32761
3740	3740	MCFG_TC0480SCP_PALETTE("palette")
3741	3741
3742	3742	MCFG_DEVICE_ADD("tc0150rod", TC0150ROD, 0)
3743
	3743
3744	3744	/* sound hardware */
3745	3745	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
3746	3746

trunk/src/mame/drivers/midxunit.c
r32760	r32761
245	245	MCFG_CPU_PROGRAM_MAP(main_map)
246	246	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
247	247	MCFG_TMS340X0_PIXEL_CLOCK(PIXEL_CLOCK) /* pixel clock */
248		MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
	248	MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
249	249	MCFG_TMS340X0_SCANLINE_IND16_CB(midxunit_state, scanline_update) /* scanline updater (indexed16) */
250	250	MCFG_TMS340X0_TO_SHIFTREG_CB(midtunit_state, to_shiftreg) /* write to shiftreg function */
251	251	MCFG_TMS340X0_FROM_SHIFTREG_CB(midtunit_state, from_shiftreg) /* read from shiftreg function */

trunk/src/mame/drivers/macs.c
r32760	r32761
82	82	DECLARE_DRIVER_INIT(kisekaem);
83	83	DECLARE_DRIVER_INIT(macs2);
84	84	DECLARE_MACHINE_RESET(macs);
85
	85
86	86	UINT32 screen_update_macs(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
87	87
88	88	optional_device<st0016_cpu_device> m_maincpu;
r32760	r32761
149	149	{
150	150	membank("bank1")->set_base(memregion("maincpu")->base() + (data* 0x4000) + macs_cart_slot*0x400000 );
151	151
152		// m_st0016_rom_bank=data;
	152	// m_st0016_rom_bank=data;
153	153	}
154	154
155	155	WRITE8_MEMBER(macs_state::macs_output_w)

trunk/src/mame/drivers/alg.c
r32760	r32761
769	769	*************************************/
770	770
771	771	/* BIOS */
772		GAME( 199?, alg_bios, 0, alg_r1, alg, alg_state, ntsc, ROT0, "American Laser Games", "American Laser Games BIOS", GAME_IS_BIOS_ROOT )
	772	GAME( 199?, alg_bios, 0, alg_r1, alg, alg_state, ntsc, ROT0, "American Laser Games", "American Laser Games BIOS", GAME_IS_BIOS_ROOT )
773	773
774	774	/* Rev. A board */
775	775	/* PAL R1 */
776		GAME( 1990, maddoga, maddog, alg_r1, alg, alg_state, palr1, ROT0, "American Laser Games", "Mad Dog McCree v1C board rev.A", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
	776	GAME( 1990, maddoga, maddog, alg_r1, alg, alg_state, palr1, ROT0, "American Laser Games", "Mad Dog McCree v1C board rev.A", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
777	777
778	778	/* PAL R3 */
779		GAME( 1991, wsjr, alg_bios, alg_r1, alg, alg_state, palr3, ROT0, "American Laser Games", "Who Shot Johnny Rock? v1.6", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
780		GAME( 1991, wsjr_15, wsjr, alg_r1, alg, alg_state, palr3, ROT0, "American Laser Games", "Who Shot Johnny Rock? v1.5", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
	779	GAME( 1991, wsjr, alg_bios, alg_r1, alg, alg_state, palr3, ROT0, "American Laser Games", "Who Shot Johnny Rock? v1.6", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
	780	GAME( 1991, wsjr_15, wsjr, alg_r1, alg, alg_state, palr3, ROT0, "American Laser Games", "Who Shot Johnny Rock? v1.5", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
781	781
782	782	/* Rev. B board */
783	783	/* PAL R6 */
784	784
785		GAME( 1990, maddog, alg_bios, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "Mad Dog McCree v2.03 board rev.B", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
	785	GAME( 1990, maddog, alg_bios, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "Mad Dog McCree v2.03 board rev.B", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
786	786	GAME( 1990, maddog_202, maddog, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "Mad Dog McCree v2.02 board rev.B", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
787	787
788	788	/* works ok but uses right player (2) controls only for trigger and holster */
789		GAME( 1992, maddog2, alg_bios, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "Mad Dog II: The Lost Gold v2.04", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
	789	GAME( 1992, maddog2, alg_bios, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "Mad Dog II: The Lost Gold v2.04", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
790	790	GAME( 1992, maddog2_202, maddog2, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "Mad Dog II: The Lost Gold v2.02", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
791	791	GAME( 1992, maddog2_110, maddog2, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "Mad Dog II: The Lost Gold v1.10", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
792	792	GAME( 1992, maddog2_100, maddog2, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "Mad Dog II: The Lost Gold v1.00", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
793	793	/* works ok but uses right player (2) controls only for trigger and holster */
794		GAME( 1992, spacepir, alg_bios, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "Space Pirates v2.2", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
	794	GAME( 1992, spacepir, alg_bios, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "Space Pirates v2.2", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
795	795	GAME( 1992, spacepir_14, spacepir, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "Space Pirates v1.4", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
796	796
797		GAME( 1992, gallgall, alg_bios, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "Gallagher's Gallery v2.2", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
	797	GAME( 1992, gallgall, alg_bios, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "Gallagher's Gallery v2.2", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
798	798	GAME( 1992, gallgall_21, gallgall, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "Gallagher's Gallery v2.1", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
799	799	/* all good, but no holster */
800		GAME( 1993, crimepat, alg_bios, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "Crime Patrol v1.51", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
	800	GAME( 1993, crimepat, alg_bios, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "Crime Patrol v1.51", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
801	801	GAME( 1993, crimepat_14, crimepat, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "Crime Patrol v1.4", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
802	802	GAME( 1993, crimepat_12, crimepat, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "Crime Patrol v1.2", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
803	803
804		GAME( 1993, crimep2, alg_bios, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "Crime Patrol 2: Drug Wars v1.3", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
	804	GAME( 1993, crimep2, alg_bios, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "Crime Patrol 2: Drug Wars v1.3", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
805	805	GAME( 1993, crimep2_11, crimep2, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "Crime Patrol 2: Drug Wars v1.1", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
806		GAME( 1994, lastbh, alg_bios, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "The Last Bounty Hunter v1.01", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
	806	GAME( 1994, lastbh, alg_bios, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "The Last Bounty Hunter v1.01", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
807	807	GAME( 1994, lastbh_006, lastbh, alg_r2, alg_2p, alg_state, palr6, ROT0, "American Laser Games", "The Last Bounty Hunter v0.06", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
808		GAME( 1995, fastdraw, alg_bios, alg_r2, alg_2p, alg_state, palr6, ROT90, "American Laser Games", "Fast Draw Showdown v1.31", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
	808	GAME( 1995, fastdraw, alg_bios, alg_r2, alg_2p, alg_state, palr6, ROT90, "American Laser Games", "Fast Draw Showdown v1.31", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
809	809	GAME( 1995, fastdraw_130,fastdraw, alg_r2, alg_2p, alg_state, palr6, ROT90, "American Laser Games", "Fast Draw Showdown v1.30", GAME_NOT_WORKING \| GAME_NO_SOUND \| GAME_IMPERFECT_GRAPHICS )
810	810	/* works ok but uses right player (2) controls only for trigger and holster */
811	811

trunk/src/mame/drivers/potgoldu.c
r32760	r32761
27	27	potgold_state(const machine_config &mconfig, device_type type, const char *tag)
28	28	: driver_device(mconfig, type, tag),
29	29	m_maincpu(*this, "maincpu") { }
30
	30
31	31	required_device<cpu_device> m_maincpu;
32
	32
33	33	virtual void machine_reset();
34	34	virtual void video_start();
35
	35
36	36	TMS340X0_SCANLINE_RGB32_CB_MEMBER(scanline_update);
37	37	};
38	38

trunk/src/mame/drivers/mario.c
r32760	r32761
186	186	//AM_RANGE(0xa000, 0xa000) AM_READ_PORT("IN1")
187	187	AM_RANGE(0xa000, 0xa000) AM_READNOP /* watchdog? */
188	188	AM_RANGE(0xa100, 0xa100) AM_READ_PORT("DSW") /* DSW */
189		AM_RANGE(0xa206, 0xa206) AM_WRITE(mario_gfxbank_w)
	189	AM_RANGE(0xa206, 0xa206) AM_WRITE(mario_gfxbank_w)
190	190
191	191	AM_RANGE(0x8000, 0x9fff) AM_ROM
192	192	AM_RANGE(0xb000, 0xbfff) AM_ROM
r32760	r32761
457	457	16,16, /* 1616 sprites /
458	458	RGN_FRAC(1,3), /* 256 sprites */
459	459	3, /* 3 bits per pixel */
460		{ RGN_FRAC(2,3),RGN_FRAC(1,3),RGN_FRAC(0,3) },
461		{ 0, 1, 2, 3, 4, 5, 6, 7,
	460	{ RGN_FRAC(2,3),RGN_FRAC(1,3),RGN_FRAC(0,3) },
	461	{ 0, 1, 2, 3, 4, 5, 6, 7,
462	462	64,65,66,67,68,69,70,71 },
463	463	{ 08, 18, 28, 38, 48, 58, 68, 78,
464	464	168, 178, 188, 198, 208, 218, 228, 238 },
465		16*16
	465	16*16
466	466	};
467	467
468	468	static GFXDECODE_START( mariobl )
r32760	r32761
475	475	16,16, /* 1616 sprites /
476	476	RGN_FRAC(1,2), /* 256 sprites */
477	477	2, /* 3 bits per pixel */
478		{ RGN_FRAC(1,2),RGN_FRAC(0,2) },
479		{ 0, 1, 2, 3, 4, 5, 6, 7,
	478	{ RGN_FRAC(1,2),RGN_FRAC(0,2) },
	479	{ 0, 1, 2, 3, 4, 5, 6, 7,
480	480	64,65,66,67,68,69,70,71 },
481	481	{ 08, 18, 28, 38, 48, 58, 68, 78,
482	482	168, 178, 188, 198, 208, 218, 228, 238 },
483		16*16
	483	16*16
484	484	};
485	485
486	486	static GFXDECODE_START( dkong3abl )
r32760	r32761
548	548	MACHINE_CONFIG_END
549	549
550	550	/*
551		Mario Bros japan bootleg on Ambush hardware
	551	Mario Bros japan bootleg on Ambush hardware
552	552
553	553	This romset (japanese version) comes from a faulty bootleg pcb.Game differences are none.
554	554	Note:it runs on a modified (extended) Tecfri's Ambush hardware.
r32760	r32761
582	582
583	583	/* sound hardware */
584	584	MCFG_SPEAKER_STANDARD_MONO("mono")
585
	585
586	586	MCFG_SOUND_ADD("ay1", AY8910, XTAL_18_432MHz/6/2) /* XTAL confirmed, divisor guessed */
587	587	MCFG_AY8910_PORT_A_READ_CB(IOPORT("SYSTEM"))
588		// MCFG_AY8910_PORT_B_WRITE_CB(WRITE8(mario_state, ay1_outputb_w))
	588	// MCFG_AY8910_PORT_B_WRITE_CB(WRITE8(mario_state, ay1_outputb_w))
589	589
590	590	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.33)
591	591
592	592	MCFG_SOUND_ADD("ay2", AY8910, XTAL_18_432MHz/6/2) /* XTAL confirmed, divisor guessed */
593	593	MCFG_AY8910_PORT_A_READ_CB(IOPORT("INPUTS"))
594		// MCFG_AY8910_PORT_B_WRITE_CB(WRITE8(mario_state, ay2_outputb_w))
	594	// MCFG_AY8910_PORT_B_WRITE_CB(WRITE8(mario_state, ay2_outputb_w))
595	595
596	596	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.33)
597	597

trunk/src/mame/drivers/arkanoid.c
r32760	r32761
16	16	The 68705 code for this one was not available; I made it up from
17	17	the current A75-06.IC16 changing the level data pointer table.
18	18	arkanoidj Japanese version. Final revision, MCU code not dumped.
19		arkanoidja Japanese version. A later revision with level selector.
	19	arkanoidja Japanese version. A later revision with level selector.
20	20	The 68705 code for this one was not available; I made it up from
21	21	the current A75-06.IC16 changing the level data pointer table.
22	22	arkanoidjbl Bootleg of the early Japanese version. The only difference is
r32760	r32761
809	809
810	810	READ8_MEMBER(arkanoid_state::hexaa_f000_r)
811	811	{
812		// return hexaa_from_sub;
	812	// return hexaa_from_sub;
813	813	return rand();
814	814	}
815	815
r32760	r32761
844	844	READ8_MEMBER(arkanoid_state::hexaa_sub_90_r)
845	845	{
846	846	return hexaa_from_main;
847		// return rand();
	847	// return rand();
848	848	}
849	849
850	850	static ADDRESS_MAP_START( hexaa_sub_iomap, AS_IO, 8, arkanoid_state )
r32760	r32761
853	853	AM_RANGE(0x80, 0x80) AM_WRITE(hexaa_sub_80_w)
854	854	AM_RANGE(0x90, 0x90) AM_READ(hexaa_sub_90_r)
855	855	ADDRESS_MAP_END
856
857	856
858	857
	858
859	859	static ADDRESS_MAP_START( brixian_map, AS_PROGRAM, 8, arkanoid_state )
860	860	AM_RANGE(0x0000, 0xbfff) AM_ROM
861	861	AM_RANGE(0xc000, 0xc7ff) AM_RAM AM_SHARE("protram")
r32760	r32761
1832	1832	ROM_LOAD( "sub1.bin", 0x00000, 0x8000, CRC(82c091fa) SHA1(e509ab4d9372f93d81df70772a4632100081ffd7) )
1833	1833	ROM_LOAD( "main4.bin", 0x10000, 0x8000, CRC(3d5d006c) SHA1(ad4eadab82024b122182eacb5a322cfd6e476a70) )
1834	1834
1835		ROM_REGION( 0x18000, "subcpu", 0 )
	1835	ROM_REGION( 0x18000, "subcpu", 0 )
1836	1836	ROM_LOAD( "sub2.bin", 0x00000, 0x2000, CRC(c3bb9661) SHA1(e4bccb822d6eba77bb9cba75125cddb740775a2c)) // 1ST AND 2ND HALF IDENTICAL (contains just 0x55 bytes of code)
1837	1837
1838	1838

trunk/src/mame/drivers/st_mp100.c
r32760	r32761
500	500	if (!state)
501	501	m_counter = 0;
502	502	}
503
	503
504	504	WRITE_LINE_MEMBER( st_mp100_state::u10_cb2_w )
505	505	{
506	506	}

trunk/src/mame/drivers/peplus.c
r32760	r32761
1226	1226	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME("Card Cage") PORT_CODE(KEYCODE_M) PORT_TOGGLE
1227	1227
1228	1228	PORT_MODIFY("SW1")
1229		PORT_DIPNAME( 0x02, 0x02, "Credit" ) PORT_DIPLOCATION("SW1:2")
	1229	PORT_DIPNAME( 0x02, 0x02, "Credit" ) PORT_DIPLOCATION("SW1:2")
1230	1230	PORT_DIPSETTING( 0x02, "Coin Play" )
1231	1231	PORT_DIPSETTING( 0x00, "Credit Play" )
1232		PORT_DIPNAME( 0x04, 0x00, "Coin Acceptor" ) PORT_DIPLOCATION("SW1:3")
	1232	PORT_DIPNAME( 0x04, 0x00, "Coin Acceptor" ) PORT_DIPLOCATION("SW1:3")
1233	1233	PORT_DIPSETTING( 0x04, "Mechanical" )
1234	1234	PORT_DIPSETTING( 0x00, "Optical" )
1235		PORT_DIPNAME( 0x08, 0x08, "Double Up" ) PORT_DIPLOCATION("SW1:4")
	1235	PORT_DIPNAME( 0x08, 0x08, "Double Up" ) PORT_DIPLOCATION("SW1:4")
1236	1236	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1237	1237	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1238		PORT_DIPNAME( 0x10, 0x10, "Progressive" ) PORT_DIPLOCATION("SW1:5")
	1238	PORT_DIPNAME( 0x10, 0x10, "Progressive" ) PORT_DIPLOCATION("SW1:5")
1239	1239	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
1240	1240	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1241		PORT_DIPNAME( 0x60, 0x40, "Max Hopper Pay" ) PORT_DIPLOCATION("SW1:6,7")
	1241	PORT_DIPNAME( 0x60, 0x40, "Max Hopper Pay" ) PORT_DIPLOCATION("SW1:6,7")
1242	1242	PORT_DIPSETTING( 0x60, "300 Coins" )
1243	1243	PORT_DIPSETTING( 0x40, "400 Coins" )
1244	1244	PORT_DIPSETTING( 0x20, "600 Coins" )
1245	1245	PORT_DIPSETTING( 0x00, "1000 Coins" )
1246		PORT_DIPNAME( 0x80, 0x00, "Show Pay Table" ) PORT_DIPLOCATION("SW1:8")
	1246	PORT_DIPNAME( 0x80, 0x00, "Show Pay Table" ) PORT_DIPLOCATION("SW1:8")
1247	1247	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1248	1248	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1249	1249	INPUT_PORTS_END

trunk/src/mame/drivers/segac2.c
r32760	r32761
432	432	D0 : To CN1 pin 8. (Coin meter 1)
433	433	*/
434	434	//coin_lockout_w(space.machine(), 1, data & 0x08);
435		//coin_lockout_w(space.machine(), 0, data & 0x04);
	435	//coin_lockout_w(space.machine(), 0, data & 0x04);
436	436	coin_counter_w(space.machine(), 1, data & 0x02);
437	437	coin_counter_w(space.machine(), 0, data & 0x01);
438	438	}

trunk/src/mame/drivers/dlair.c
r32760	r32761
769	769	DISK_IMAGE_READONLY( "dlair", 0, NO_DUMP )
770	770	ROM_END
771	771
772		ROM_START( dlair_2 )
	772	ROM_START( dlair_2 )
773	773	ROM_REGION( 0xa000, "maincpu", 0 )
774	774	ROM_LOAD( "dlu1.bin", 0x0000, 0x2000, CRC(ea6d5498) SHA1(1d854c04e0074e693e791e22a4c9cc21d5175d95) )
775	775	ROM_LOAD( "dlu2.bin", 0x2000, 0x2000, CRC(ffe84a95) SHA1(675ce2e68e43beb1f389bc6ab1a55bee862a1440) )

trunk/src/mame/drivers/bublbobl.c
r32760	r32761
573	573
574	574	static INPUT_PORTS_START( sboblbobl )
575	575	PORT_INCLUDE( sboblboblb )
576
	576
577	577	PORT_MODIFY( "IN0" )
578	578	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(1)
579	579	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(1)

trunk/src/mame/drivers/simple_st0016.c
r32760	r32761
77	77	WRITE8_MEMBER(st0016_state::st0016_rom_bank_w)
78	78	{
79	79	membank("bank1")->set_base(memregion("maincpu")->base() + (data* 0x4000));
80		// st0016_rom_bank=data;
	80	// st0016_rom_bank=data;
81	81	}
82	82
83	83	static ADDRESS_MAP_START( st0016_io, AS_IO, 8, st0016_state )
r32760	r32761
472	472	MCFG_SCREEN_PALETTE("maincpu:palette")
473	473
474	474
475		// MCFG_VIDEO_START_OVERRIDE(st0016_state,st0016)
	475	// MCFG_VIDEO_START_OVERRIDE(st0016_state,st0016)
476	476
477	477	MACHINE_CONFIG_END
478	478

trunk/src/mame/drivers/snowbros.c
r32760	r32761
2368	2368	ROM_LOAD( "87c52.mcu", 0x00000, 0x10000 , NO_DUMP ) /* can't be dumped */
2369	2369
2370	2370	ROM_REGION16_BE( 0x200, "user1", ROMREGION_ERASE00 ) /* Data from Shared RAM */
2371		// ROM_LOAD16_WORD( "protdata.bin", 0x00000, 0x200 , CRC(1) SHA1(1) )
	2371	// ROM_LOAD16_WORD( "protdata.bin", 0x00000, 0x200 , CRC(1) SHA1(1) )
2372	2372
2373	2373	ROM_REGION( 0x040000, "oki", 0 ) /* Samples */
2374	2374	ROM_LOAD( "su_ho_sung.uj15", 0x00000, 0x40000, CRC(266fcae8) SHA1(0f15f880bde0c12b5c663ed387f9353c13b731b6) )

trunk/src/mame/drivers/caprcyc.c
r32760	r32761
3	3	/***************************************************************************
4	4
5	5	Taito Capriccio Cyclone crane hardware
6
	6
7	7	Main PCB: NEC uPD30200GD-100-MBB VR4300, Galileo GT-64111 (system controller?), ...
8	8	Sound PCB: Panasonic MN1020819 (has internal ROM), Zoom ZSG-2. No effects DSP!
9
	9
10	10	Like most other Taito Capriccio cabinets, it has two cranes. There are
11	11	no 7seg leds on the cranes this time, some colour lamps instead.
12
	12
13	13	TODO:
14	14	- everything
15	15

trunk/src/mame/drivers/pacman.c
r32760	r32761
1325	1325	AM_RANGE(0x8400, 0x87ff) AM_RAM_WRITE(pacman_colorram_w) AM_SHARE("colorram")
1326	1326
1327	1327	AM_RANGE(0x8800, 0x8bff) AM_RAM
1328		// AM_RANGE(0x8800, 0x8bff) AM_READ(pacman_read_nop) AM_WRITENOP
	1328	// AM_RANGE(0x8800, 0x8bff) AM_READ(pacman_read_nop) AM_WRITENOP
1329	1329	AM_RANGE(0x8c00, 0x8fef) AM_RAM
1330	1330	AM_RANGE(0x8ff0, 0x8fff) AM_RAM AM_SHARE("spriteram")
1331	1331	AM_RANGE(0x9000, 0x9000) AM_WRITE(irq_mask_w)
r32760	r32761
2935	2935	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN1 )
2936	2936	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START1 )
2937	2937
2938		PORT_MODIFY("DSW1")
	2938	PORT_MODIFY("DSW1")
2939	2939	PORT_DIPNAME( 0x03, 0x00, DEF_STR( Coinage ) )
2940	2940	PORT_DIPSETTING( 0x03, DEF_STR( 4C_1C ) )
2941	2941	PORT_DIPSETTING( 0x02, DEF_STR( 3C_1C ) )
r32760	r32761
3952	3952	ROM_CONTINUE(0x1800,0x800)
3953	3953
3954	3954	ROM_REGION( 0x0120, "proms", 0 )
3955		ROM_LOAD( "82s123.h7", 0x0000, 0x0020, CRC(3545e7e9) SHA1(b866b02579438afb11296e5c53a32c6425bd044d) )
	3955	ROM_LOAD( "82s123.h7", 0x0000, 0x0020, CRC(3545e7e9) SHA1(b866b02579438afb11296e5c53a32c6425bd044d) )
3956	3956	ROM_LOAD( "82s129-3.d1", 0x0020, 0x0100, CRC(3eb3a8e4) SHA1(19097b5f60d1030f8b82d9f1d3a241f93e5c75d6) )
3957	3957
3958	3958	ROM_REGION( 0x0200, "namco", 0 ) /* sound PROMs */
r32760	r32761
4234	4234	ROM_LOAD( "pengopac.4", 0x4000, 0x1000, CRC(1519d59b) SHA1(13b99780fcccac61b16201500e309c9b442406c8) )
4235	4235	ROM_LOAD( "pengopac.5", 0x5000, 0x1000, CRC(1b90c32c) SHA1(1761add93d71d29840b1462b9747a3d463b7148d) )
4236	4236	ROM_LOAD( "pengopac.6", 0x6000, 0x2000, CRC(8d2994ee) SHA1(1f16b32c4574107a4a15d40113b966581b374a81) )
4237
	4237
4238	4238	ROM_REGION( 0x2000, "gfx1", 0 )
4239	4239	ROM_LOAD( "pengopac.5e", 0x0000, 0x0800, CRC(ad88978a) SHA1(a568baf751753660223958b722980f031310eba1) )
4240	4240	ROM_LOAD( "pengopac.5f", 0x0800, 0x0800, CRC(cb208b9f) SHA1(63b64b52c9c3e18b2d2823e79095160fb1a71f00) )
r32760	r32761
6544	6544
6545	6545	ROM[0x7ffe] = 0xa7;
6546	6546	ROM[0x7fee] = 0x6d;
6547
	6547
6548	6548	save_item(NAME(m_rocktrv2_question_bank));
6549	6549	}
6550	6550

trunk/src/mame/drivers/igs011.c
r32760	r32761
96	96	optional_device<okim6295_device> m_oki;
97	97	required_device<screen_device> m_screen;
98	98	required_device<palette_device> m_palette;
99
	99
100	100	/* memory pointers */
101	101	required_shared_ptr<UINT16> m_priority_ram;
102	102	optional_shared_ptr<UINT16> m_vbowl_trackball;
103	103	required_shared_ptr<UINT16> m_generic_paletteram_16;
104
	104
105	105	UINT8 *m_layer[8];
106	106	UINT16 m_priority;
107	107	UINT8 m_lhb2_pen_hi;
r32760	r32761
277	277	}
278	278
279	279	m_lhb2_pen_hi = 0;
280
	280
281	281	save_item(NAME(m_priority));
282	282	save_item(NAME(m_lhb2_pen_hi));
283	283	save_item(NAME(m_blitter.x));

trunk/src/mame/drivers/mgavegas.c
r32760	r32761
2	2
3	3	mgavegas.c
4	4
5		Coin pusher
	5	Coin pusher
6	6
7	7	TODO
8	8	-better analog audio out/mixer
9		-some output (mostly not used)
	9	-some output (mostly not used)
10	10
11	11	Ver. 1.33 have no speech and no change funcion implemented in software
12	12	Ver. 2.1 and 2.3 have change function working and speech
13	13	Ver. 2.2 should exist
14
	14
15	15	************************************************************************************/
16	16
17	17	#include "emu.h"
r32760	r32761
28	28	* LOG defines *
29	29	****************************/
30	30
31		#define LOG_AY8910 0
	31	#define LOG_AY8910 0
32	32	#define LOG_MSM5205 0
33		#define LOG_CSO1 0
34		#define LOG_CSO2 0
	33	#define LOG_CSO1 0
	34	#define LOG_CSO2 0
35	35
36	36
37	37	/****************************
38	38	* Clock defines *
39	39	****************************/
40		#define MAIN_XTAL XTAL_8MHz
	40	#define MAIN_XTAL XTAL_8MHz
41	41	#define CPU_CLK MAIN_XTAL/2
42	42	#define AY_CLK CPU_CLK/2
43	43	#define MSM_CLK 384000
r32760	r32761
54	54	m_ticket(*this, "hopper"),
55	55	m_filter1(*this, "filter1"),
56	56	m_filter2(*this, "filter2")
57
58
	57
	58
59	59	{ }
60	60	UINT8 m_int;
61
	61
62	62	//OUT1
63	63	UINT8 m_ckmod;
64	64	UINT8 m_dmod;
r32760	r32761
68	68	UINT8 m_seg;
69	69	UINT8 m_printer;
70	70	UINT8 m_auxp;
71
	71
72	72	//helper...
73	73	UINT8 m_old_ckmod;
74	74	UINT8 m_old_emod;
r32760	r32761
82	82	UINT8 m_cont_ent;
83	83	UINT8 m_cont_sal;
84	84	UINT8 m_cont_caj;
85
	85
86	86	//lamps out
87	87	UINT64 m_custom_data;
88	88	UINT8 m_auxs;
r32760	r32761
117	117	UINT8 m_ml;
118	118	UINT8 m_mc;
119	119	UINT8 m_mr;
120
	120
121	121	DECLARE_READ8_MEMBER(start_read);
122	122
123	123	DECLARE_WRITE8_MEMBER(w_a0);
r32760	r32761
125	125	DECLARE_WRITE8_MEMBER(cso1_w);
126	126	DECLARE_WRITE8_MEMBER(cso2_w);
127	127	DECLARE_WRITE8_MEMBER(csoki_w);
128		DECLARE_READ8_MEMBER(csoki_r);
129
	128	DECLARE_READ8_MEMBER(csoki_r);
	129
130	130	DECLARE_READ8_MEMBER(ay8910_a_r);
131	131	DECLARE_READ8_MEMBER(ay8910_b_r);
132
	132
133	133	DECLARE_DRIVER_INIT(mgavegas);
134	134	DECLARE_DRIVER_INIT(mgavegas21);
135	135	DECLARE_DRIVER_INIT(mgavegas133);
136
	136
137	137	TIMER_DEVICE_CALLBACK_MEMBER(int_0);
138
139
	138
	139
140	140	protected:
141	141
142	142	// devices
r32760	r32761
158	158
159	159
160	160	void mgavegas_state::update_lamp(){
161
162		//output_set_value("AUXS", m_auxs); //unused
	161	//output_set_value("AUXS", m_auxs); //unused
163	162	output_set_value("MGA4", m_anal&0x01);
164	163	output_set_value("MGA3", m_anacl&0x01);
165	164	output_set_value("MGA2", m_anacr&0x01);
r32760	r32761
171	170	output_set_value("1002", m_luz_100_rul&0x01);
172	171	output_set_value("50", m_luz_50_rlul&0x01);
173	172	output_set_value("252", m_luz_25_lrul&0x01);
174		output_set_value("25", m_luz_25_rrul&0x01);
	173	output_set_value("25", m_luz_25_rrul&0x01);
175	174	output_set_value("FL", m_fl&0x01);
176	175	output_set_value("FC", m_fc&0x01);
177	176	output_set_value("FR", m_fr&0x01);
r32760	r32761
179	178	output_set_value("NOCAMBIO", m_no_cambio&0x01);
180	179	output_set_value("FUSE", m_fuse&0x01);
181	180	output_set_value("FALTA", m_falta&0x01);
182		//output_set_value("ANAG", m_anag&0x01); //unused
	181	//output_set_value("ANAG", m_anag&0x01); //unused
183	182	output_set_value("CL", m_cl&0x01);
184	183	output_set_value("CC", m_cc&0x01);
185	184	output_set_value("CR", m_cr&0x01);
r32760	r32761
192	191	output_set_value("MC", m_mc&0x01);
193	192	output_set_value("MR", m_mr&0x01);
194	193	/*
195		m_inh=BIT(data, 3);
196		m_printer=BIT(data, 6); //not_used
197		m_auxp=BIT(data, 7); //not_used
198
199		m_bobina_ctrl=BIT(data, 0);
200		m_timbre=BIT(data, 1);
201		m_coil_1=BIT(data, 2);
202		m_coil_2=BIT(data, 3);
203		m_coil_3=BIT(data, 4);
204		m_cont_ent=BIT(data, 5);
205		m_cont_sal=BIT(data, 6);
206		m_cont_caj=BIT(data, 7);
	194	m_inh=BIT(data, 3);
	195	m_printer=BIT(data, 6); //not_used
	196	m_auxp=BIT(data, 7); //not_used
	197
	198	m_bobina_ctrl=BIT(data, 0);
	199	m_timbre=BIT(data, 1);
	200	m_coil_1=BIT(data, 2);
	201	m_coil_2=BIT(data, 3);
	202	m_coil_3=BIT(data, 4);
	203	m_cont_ent=BIT(data, 5);
	204	m_cont_sal=BIT(data, 6);
	205	m_cont_caj=BIT(data, 7);
207	206	*/
208	207	}
209	208
r32760	r32761
217	216	}
218	217
219	218	if( (m_emod==0) & (m_old_emod==1) ){
220		//valid emod, check for valid data and updatae custom status this is how the hw works
	219	//valid emod, check for valid data and updatae custom status this is how the hw works
221	220	if( (BIT(m_custom_data, 32)==0) && (BIT(m_custom_data, 33)==0) && (BIT(m_custom_data, 34)==0) && (BIT(m_custom_data, 35)==0) ){
222	221	tmp=~m_custom_data;
223		m_auxs= tmp&0x00000001;
224		// m_anal= (tmp&0x00000002)>>1; //schematics error!!!
225		// m_anacl= (tmp&0x00000004)>>2; //schematics error!!!
226		m_luz_50_rlul= (tmp&0x00000002)>>1;
227		m_luz_25_lrul= (tmp&0x00000004)>>2;
228		m_anacr= (tmp&0x00000008)>>3;
229		m_anar= (tmp&0x00000010)>>4;
230		m_pl= (tmp&0x00000020)>>5;
231		m_pc= (tmp&0x00000040)>>6;
232		m_pr= (tmp&0x00000080)>>7;
233		m_luz_250_rul= (tmp&0x00000100)>>8;
234		m_luz_100_rul= (tmp&0x00000200)>>9;
235		// m_luz_50_rlul= (tmp&0x00000400)>>10; //schematics error!!!
236		// m_luz_25_lrul= (tmp&0x00000800)>>11; //schematics error!!!
237		m_anacl= (tmp&0x00000400)>>10;
238		m_anal= (tmp&0x00000800)>>11;
239		m_luz_25_rrul= (tmp&0x00001000)>>12;
240		m_fl= (tmp&0x00002000)>>13;
241		m_fc= (tmp&0x00004000)>>14;
242		m_fr= (tmp&0x00008000)>>15;
243		m_insert_coin= (tmp&0x00010000)>>16;
244		m_no_cambio= (tmp&0x00020000)>>17;
245		m_fuse= (tmp&0x00040000)>>18;
246		m_falta= (tmp&0x00080000)>>19;
247		m_anag= (tmp&0x00100000)>>20;
248		m_cl= (tmp&0x00200000)>>21;
249		m_cc= (tmp&0x00400000)>>22;
250		m_cr= (tmp&0x00800000)>>23;
251		m_premio_s= (tmp&0x01000000)>>24;
252		m_100= (tmp&0x02000000)>>25;
253		m_200= (tmp&0x04000000)>>26;
254		m_300= (tmp&0x08000000)>>27;
255		m_500= (tmp&0x10000000)>>28;
256		m_ml= (tmp&0x20000000)>>29;
257		m_mc= (tmp&0x40000000)>>30;
258		m_mr= (tmp&0x80000000)>>31;
	222	m_auxs= tmp&0x00000001;
	223	// m_anal= (tmp&0x00000002)>>1; //schematics error!!!
	224	// m_anacl= (tmp&0x00000004)>>2; //schematics error!!!
	225	m_luz_50_rlul= (tmp&0x00000002)>>1;
	226	m_luz_25_lrul= (tmp&0x00000004)>>2;
	227	m_anacr= (tmp&0x00000008)>>3;
	228	m_anar= (tmp&0x00000010)>>4;
	229	m_pl= (tmp&0x00000020)>>5;
	230	m_pc= (tmp&0x00000040)>>6;
	231	m_pr= (tmp&0x00000080)>>7;
	232	m_luz_250_rul= (tmp&0x00000100)>>8;
	233	m_luz_100_rul= (tmp&0x00000200)>>9;
	234	// m_luz_50_rlul= (tmp&0x00000400)>>10; //schematics error!!!
	235	// m_luz_25_lrul= (tmp&0x00000800)>>11; //schematics error!!!
	236	m_anacl= (tmp&0x00000400)>>10;
	237	m_anal= (tmp&0x00000800)>>11;
	238	m_luz_25_rrul= (tmp&0x00001000)>>12;
	239	m_fl= (tmp&0x00002000)>>13;
	240	m_fc= (tmp&0x00004000)>>14;
	241	m_fr= (tmp&0x00008000)>>15;
	242	m_insert_coin= (tmp&0x00010000)>>16;
	243	m_no_cambio= (tmp&0x00020000)>>17;
	244	m_fuse= (tmp&0x00040000)>>18;
	245	m_falta= (tmp&0x00080000)>>19;
	246	m_anag= (tmp&0x00100000)>>20;
	247	m_cl= (tmp&0x00200000)>>21;
	248	m_cc= (tmp&0x00400000)>>22;
	249	m_cr= (tmp&0x00800000)>>23;
	250	m_premio_s= (tmp&0x01000000)>>24;
	251	m_100= (tmp&0x02000000)>>25;
	252	m_200= (tmp&0x04000000)>>26;
	253	m_300= (tmp&0x08000000)>>27;
	254	m_500= (tmp&0x10000000)>>28;
	255	m_ml= (tmp&0x20000000)>>29;
	256	m_mc= (tmp&0x40000000)>>30;
	257	m_mr= (tmp&0x80000000)>>31;
259	258
260	259	update_lamp();
261	260	}
262	261	}
263
	262
264	263	m_old_ckmod=m_ckmod;
265	264	m_old_emod=m_emod;
266	265	}
r32760	r32761
268	267
269	268	READ8_MEMBER( mgavegas_state::start_read )
270	269	{
271		// in HW it look for /IOREQ going down to clear the IRQ line
	270	// in HW it look for /IOREQ going down to clear the IRQ line
272	271	if (m_int){
273	272	m_maincpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
274	273	m_int=0;
r32760	r32761
285	284	{
286	285	UINT8 ret=0;
287	286
288
	287
289	288	switch (offset&0x03)
290	289	{
291		case 1: //bdir=0 BC1=1
	290	case 1: //bdir=0 BC1=1
292	291	ret=m_ay->data_r(space,0);
293	292	break;
294		default:
	293	default:
295	294	if (LOG_AY8910)
296	295	logerror("AY 3-8910 area unknow read!!!\n");
297	296	break;
298	297	}
299
	298
300	299	if (LOG_AY8910)
301		logerror("read from %04X return %02X\n",offset+0xa000,ret);
	300	logerror("read from %04X return %02X\n",offset+0xa000,ret);
302	301	return ret;
303	302	}
304	303
305	304	WRITE8_MEMBER(mgavegas_state::w_a0)
306	305	{
307
308	306	if (LOG_AY8910)
309	307	logerror("write to %04X data = %02X \n",offset+0xa000,data);
310	308
311	309	switch (offset&0x03)
312	310	{
313		case 0: //bdir=1 bc1=1
	311	case 0: //bdir=1 bc1=1
314	312	m_ay->address_w(space,0,data );
315	313	break;
316		case 2: //bdir=1 bc1=0
	314	case 2: //bdir=1 bc1=0
317	315	m_ay->data_w(space,0,data );
318	316	break;
319	317	/*
320		case 1: //bdir=0 bc1=1
321		break;
322		case 3: //bdir=0 bc1=0
323		break;
	318	case 1: //bdir=0 bc1=1
	319	break;
	320	case 3: //bdir=0 bc1=0
	321	break;
324	322	*/
325		default:
	323	default:
326	324	if (LOG_AY8910)
327	325	logerror("AY 3-8910 area unknow write!!!\n");
328	326	break;
r32760	r32761
338	336	UINT8 ret=0;
339	337
340	338	if (LOG_MSM5205)
341		logerror("read from %04X return %02X\n",offset+0xc800,ret);
	339	logerror("read from %04X return %02X\n",offset+0xc800,ret);
342	340	return ret;
343	341	}
344	342
345	343	WRITE8_MEMBER(mgavegas_state::csoki_w)
346	344	{
347
348	345	if (LOG_MSM5205)
349	346	logerror("MSM5205 write to %04X data = %02X \n",offset+0xc800,data);
350	347	m_msm->reset_w(data&0x10>>4);
r32760	r32761
357	354	int hopper_data = 0x00;
358	355	if (LOG_CSO1)
359	356	logerror("write to CSO1 data = %02X\n",data);
360
	357
361	358	m_ckmod=BIT(data, 0);
362	359	m_dmod=BIT(data, 1);
363	360	m_emod=BIT(data, 2);
364	361	m_inh=BIT(data, 3);
365	362	m_hop=BIT(data, 4);
366	363	m_seg=BIT(data, 5);
367		m_printer=BIT(data, 6); //not_used
368		m_auxp=BIT(data, 7); //not_used
	364	m_printer=BIT(data, 6); //not_used
	365	m_auxp=BIT(data, 7); //not_used
369	366
370	367	update_custom();
371	368
r32760	r32761
377	374	{
378	375	if (LOG_CSO2)
379	376	logerror("write to CSO2 data = %02X\n",data);
380
	377
381	378	m_bobina_ctrl=BIT(data, 0);
382	379	m_timbre=BIT(data, 1);
383	380	m_coil_1=BIT(data, 2);
r32760	r32761
411	408
412	409	if (LOG_AY8910)
413	410	logerror("read from port B return %02X\n",ret);
414
	411
415	412	return ret;
416	413	}
417	414
r32760	r32761
422	419	static ADDRESS_MAP_START( mgavegas_map, AS_PROGRAM, 8, mgavegas_state )
423	420	AM_RANGE(0x0000, 0x7fff) AM_ROM
424	421	AM_RANGE(0x8000, 0x9fff) AM_RAM AM_SHARE("nvram")
425		AM_RANGE(0xa000, 0xa003) AM_READWRITE(r_a0,w_a0) // AY-3-8910
426		AM_RANGE(0xc000, 0xc001) AM_WRITE(cso1_w) // /CSout1
427		AM_RANGE(0xc400, 0xc401) AM_WRITE(cso2_w) // /CSout2
428		AM_RANGE(0xc800, 0xc801) AM_READWRITE(csoki_r,csoki_w) // /CSoki
429		//AM_RANGE(0xcc00, 0xcc01) AM_READWRITE(cso3_r,cso3_w) // /CSout3 unused
430		//AM_RANGE(0xe000, 0xe003) AM_READWRITE(r_e0,w_e0) // /CSaux unused
	422	AM_RANGE(0xa000, 0xa003) AM_READWRITE(r_a0,w_a0) // AY-3-8910
	423	AM_RANGE(0xc000, 0xc001) AM_WRITE(cso1_w) // /CSout1
	424	AM_RANGE(0xc400, 0xc401) AM_WRITE(cso2_w) // /CSout2
	425	AM_RANGE(0xc800, 0xc801) AM_READWRITE(csoki_r,csoki_w) // /CSoki
	426	//AM_RANGE(0xcc00, 0xcc01) AM_READWRITE(cso3_r,cso3_w) // /CSout3 unused
	427	//AM_RANGE(0xe000, 0xe003) AM_READWRITE(r_e0,w_e0) // /CSaux unused
431	428	ADDRESS_MAP_END
432	429
433	430
r32760	r32761
443	440	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) //200ptas in for change with 8 25 ptas coins
444	441	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) //25 ptas in to play
445	442	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN3 ) //100ptas in for change with 4 25 ptas coins
446		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER )
	443	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER )
447	444	PORT_BIT( 0x10, IP_ACTIVE_LOW,IPT_SPECIAL ) PORT_READ_LINE_DEVICE_MEMBER("hopper", ticket_dispenser_device, line_r)
448		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_Y) PORT_NAME("25 ptas level") //"hack" hopper always full
449		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_U) PORT_NAME("Door")
	445	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_Y) PORT_NAME("25 ptas level") //"hack" hopper always full
	446	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_U) PORT_NAME("Door")
450	447	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_I) PORT_NAME("Channel")
451	448
452	449	PORT_START("DSW1")
453	450	PORT_DIPNAME( 0x07, 0x02, "Percentage" )
454		PORT_DIPSETTING( 0x00, "70%" )
	451	PORT_DIPSETTING( 0x00, "70%" )
455	452	PORT_DIPSETTING( 0x01, "70%" )
456	453	PORT_DIPSETTING( 0x02, "72%" )
457	454	PORT_DIPSETTING( 0x03, "74%" )
r32760	r32761
459	456	PORT_DIPSETTING( 0x05, "78%" )
460	457	PORT_DIPSETTING( 0x06, "80%" )
461	458	PORT_DIPSETTING( 0x07, "82%" )
462
	459
463	460	PORT_DIPNAME( 0x08, 0x08, "Sound" )
464	461	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
465	462	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
466
	463
467	464	PORT_DIPNAME( 0x10, 0x10, "Speech" )
468	465	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
469	466	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
470
	467
471	468	PORT_DIPNAME( 0x60, 0x00, "Jackpot" )
472	469	PORT_DIPSETTING( 0x40, "Jackpot 1%" )
473	470	PORT_DIPSETTING( 0x60, "Jackpot 2,5%" )
474	471	PORT_DIPSETTING( 0x00, "Jackpot 5%" )
475		//PORT_DIPSETTING( 0x20, DEF_STR( On ) ) //unlisted
476
	472	//PORT_DIPSETTING( 0x20, DEF_STR( On ) ) //unlisted
	473
477	474	PORT_DIPNAME( 0x80, 0x80, "Reset" )
478	475	PORT_DIPSETTING( 0x80, "Normal Gameplay" )
479	476	PORT_DIPSETTING( 0x00, "Reset" )
480
	477
481	478	INPUT_PORTS_END
482	479
483	480	/******************************
r32760	r32761
486	483
487	484	void mgavegas_state::machine_reset()
488	485	{
489
490	486	m_int=1;
491	487	m_custom_data=U64(0xffffffffffffffff);
492
	488
493	489	m_old_ckmod=1;
494	490	m_old_emod=0;
495	491
r32760	r32761
501	497	m_seg=0;
502	498	m_printer=0;
503	499	m_auxp=0;
504
505
	500
	501
506	502	m_bobina_ctrl=0;
507	503	m_timbre=0;
508	504	m_coil_1=0;
r32760	r32761
511	507	m_cont_ent=0;
512	508	m_cont_sal=0;
513	509	m_cont_caj=0;
514
	510
515	511	m_auxs=0;
516	512	m_anal=0;
517	513	m_anacl=0;
r32760	r32761
543	539	m_500=0;
544	540	m_ml=0;
545	541	m_mc=0;
546		m_mr=0;
	542	m_mr=0;
547	543
548		m_filter1->filter_rc_set_RC(FLT_RC_LOWPASS, 1000, 0, 0, CAP_N(1) ); /* RC out of MSM5205 R=1K C=1nF */
549		m_filter2->filter_rc_set_RC(FLT_RC_HIGHPASS, 3846, 0, 0, CAP_N(100 )); /ALP3B active-hybrid filter fc=2.6Khz 2poles???/
	544	m_filter1->filter_rc_set_RC(FLT_RC_LOWPASS, 1000, 0, 0, CAP_N(1) ); /* RC out of MSM5205 R=1K C=1nF */
	545	m_filter2->filter_rc_set_RC(FLT_RC_HIGHPASS, 3846, 0, 0, CAP_N(100 )); /ALP3B active-hybrid filter fc=2.6Khz 2poles???/
550	546	}
551	547
552	548
r32760	r32761
578	574	DRIVER_INIT_MEMBER(mgavegas_state,mgavegas133)
579	575	{
580	576	//hack to clear the irq on reti instruction
581		m_maincpu->space(AS_PROGRAM).install_read_handler(0x00dd, 0x00dd, read8_delegate(FUNC(mgavegas_state::start_read), this));
	577	m_maincpu->space(AS_PROGRAM).install_read_handler(0x00dd, 0x00dd, read8_delegate(FUNC(mgavegas_state::start_read), this));
582	578	}
583	579
584	580	/*************************
r32760	r32761
588	584
589	585	static MACHINE_CONFIG_START( mgavegas, mgavegas_state )
590	586	/* basic machine hardware */
591		MCFG_CPU_ADD("maincpu", Z80, CPU_CLK)
	587	MCFG_CPU_ADD("maincpu", Z80, CPU_CLK)
592	588	MCFG_CPU_PROGRAM_MAP(mgavegas_map)
593
	589
594	590	MCFG_TIMER_DRIVER_ADD_PERIODIC("int_0", mgavegas_state, int_0, attotime::from_hz(6000)) //6KHz from MSM5205 /VCK
595
	591
596	592	MCFG_NVRAM_ADD_1FILL("nvram")
597
	593
598	594	MCFG_TICKET_DISPENSER_ADD("hopper",attotime::from_msec(200),TICKET_MOTOR_ACTIVE_HIGH,TICKET_STATUS_ACTIVE_LOW);
599	595
600	596	/* sound hardware */
601
	597
602	598	MCFG_SPEAKER_STANDARD_MONO("mono")
603	599	MCFG_SOUND_ADD("aysnd", AY8910, AY_CLK)
604	600	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.3)
605	601	MCFG_AY8910_PORT_A_READ_CB(READ8(mgavegas_state, ay8910_a_r))
606	602	MCFG_AY8910_PORT_B_READ_CB(READ8(mgavegas_state, ay8910_b_r))
607
608		MCFG_SOUND_ADD("5205", MSM5205, MSM_CLK)
609		MCFG_MSM5205_PRESCALER_SELECTOR(MSM5205_S64_4B)
	603
	604	MCFG_SOUND_ADD("5205", MSM5205, MSM_CLK)
	605	MCFG_MSM5205_PRESCALER_SELECTOR(MSM5205_S64_4B)
610	606	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "filter1", 2.0)
611
612	607
	608
613	609	MCFG_FILTER_RC_ADD("filter1", 0)
614	610	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "filter2",2.0)
615	611	MCFG_FILTER_RC_ADD("filter2", 0)
616	612	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 2.0)
617	613
618
	614
619	615	/* Video */
620	616	MCFG_DEFAULT_LAYOUT(layout_mgavegas)
621
	617
622	618	MACHINE_CONFIG_END
623	619
624	620
r32760	r32761
630	626	ROM_START(mgavegas)
631	627	ROM_REGION(0x8000, "maincpu", 0)
632	628	ROM_LOAD("vegas1-k2.3.bin", 0x0000, 0x8000, CRC(418b1d04) SHA1(27669a85ed52d5dab25d6ebea6ef3d9b01a4795d) )
633
634		ROM_REGION( 0x2000, "nvram", 0 )
	629
	630	ROM_REGION( 0x2000, "nvram", 0 )
635	631	ROM_LOAD( "mgavegas23.nv", 0x0000, 0x2000, CRC(d0a175b0) SHA1(7698135dbc020f459fdaa660bf488595b67b77d0) ) //default setting
636	632	ROM_END
637	633
638	634	ROM_START(mgavegas21)
639	635	ROM_REGION(0x8000, "maincpu", 0)
640	636	ROM_LOAD("vegas1-2.1.bin", 0x0000, 0x8000, CRC(a7e988a4) SHA1(32fa1684c79f4a132553fa41006f243d4b51cef6) )
641
642		ROM_REGION( 0x2000, "nvram", 0 )
	637
	638	ROM_REGION( 0x2000, "nvram", 0 )
643	639	ROM_LOAD( "mgavegas21.nv", 0x0000, 0x2000, CRC(a4471550) SHA1(b8527e9158b5563460febd1009b44c8d74dbae4e) ) //default setting
644	640	ROM_END
645	641
646	642	ROM_START(mgavegas133)
647	643	ROM_REGION(0x8000, "maincpu", 0)
648	644	ROM_LOAD("vegas1-1.33.bin", 0x0000, 0x8000, CRC(1eea7f0f) SHA1(6fb54b8e2ab19e5378a95192e5007175ad76bc7a) )
649
650		ROM_REGION( 0x2000, "nvram", 0 )
	645
	646	ROM_REGION( 0x2000, "nvram", 0 )
651	647	ROM_LOAD( "mgavegas133.nv", 0x0000, 0x2000, CRC(20fe4db7) SHA1(887b69468ac7e6490827a06cd1f0ff15228a9c73) ) //default setting
652	648	ROM_END
653	649
r32760	r32761
655	651	/*************************
656	652	* Game Drivers *
657	653	*************************/
658		/* YEAR NAME PARENT MACHINE INPUT STATE INIT ROT COMPANY FULLNAME FLAGS*/
659		GAME( 1985, mgavegas, 0, mgavegas, mgavegas, mgavegas_state, mgavegas, ROT0, "MGA", "Vegas 1 (Ver 2.3 dual coin pulse, shorter)", GAME_MECHANICAL )
660		GAME( 1985, mgavegas21, mgavegas, mgavegas, mgavegas, mgavegas_state, mgavegas21, ROT0, "MGA", "Vegas 1 (Ver 2.1 dual coin pulse, longer)", GAME_MECHANICAL )
661		GAME( 1985, mgavegas133, mgavegas, mgavegas, mgavegas, mgavegas_state, mgavegas133,ROT0, "MGA", "Vegas 1 (Ver 1.33 single coin pulse)", GAME_MECHANICAL )
	654	/* YEAR NAME PARENT MACHINE INPUT STATE INIT ROT COMPANY FULLNAME FLAGS*/
	655	GAME( 1985, mgavegas, 0, mgavegas, mgavegas, mgavegas_state, mgavegas, ROT0, "MGA", "Vegas 1 (Ver 2.3 dual coin pulse, shorter)", GAME_MECHANICAL )
	656	GAME( 1985, mgavegas21, mgavegas, mgavegas, mgavegas, mgavegas_state, mgavegas21, ROT0, "MGA", "Vegas 1 (Ver 2.1 dual coin pulse, longer)", GAME_MECHANICAL )
	657	GAME( 1985, mgavegas133, mgavegas, mgavegas, mgavegas, mgavegas_state, mgavegas133,ROT0, "MGA", "Vegas 1 (Ver 1.33 single coin pulse)", GAME_MECHANICAL )

trunk/src/mame/drivers/coinmvga.c
r32760	r32761
187	187
188	188	- Added Colorama (P521 V13, Spanish).
189	189	- Changed the Colorama parent set description to Colorama (P521, English).
190		- Added technical notes.
	190	- Added technical notes.
191	191
192	192
193	193	[2009-08-18]

trunk/src/mame/drivers/bfm_sc1.c
r32760	r32761
1054	1054	MCFG_CPU_PERIODIC_INT_DRIVER(bfm_sc1_state, timer_irq, 1000) // generate 1000 IRQ's per second
1055	1055	MCFG_WATCHDOG_TIME_INIT(PERIOD_OF_555_MONOSTABLE(120000,100e-9))
1056	1056
1057
	1057
1058	1058	MCFG_BFMBD1_ADD("vfd0",0)
1059	1059	MCFG_SPEAKER_STANDARD_MONO("mono")
1060	1060	MCFG_SOUND_ADD("aysnd",AY8912, MASTER_CLOCK/4)

trunk/src/mame/drivers/galpani3.c
r32760	r32761
85	85	m_priority_buffer(*this, "priority_buffer"),
86	86	m_sprregs(*this, "sprregs"),
87	87	m_sprite_bitmap_1(1024, 1024)
88
	88
89	89	{ }
90	90
91	91	required_device<cpu_device> m_maincpu;
r32760	r32761
94	94	required_device<kaneko_grap2_device> m_grap2_2;
95	95	required_device<palette_device> m_palette;
96	96	required_device<sknsspr_device> m_spritegen;
97
	97
98	98	required_shared_ptr<UINT16> m_paletteram;
99	99	optional_shared_ptr<UINT16> m_spriteram;
100	100	required_shared_ptr<UINT16> m_priority_buffer;
101	101	required_shared_ptr<UINT16> m_sprregs;
102	102
103	103	bitmap_ind16 m_sprite_bitmap_1;
104
	104
105	105	UINT16 m_priority_buffer_scrollx;
106	106	UINT16 m_priority_buffer_scrolly;
107	107

trunk/src/mame/drivers/skimaxx.c
r32760	r32761
55	55	required_device<cpu_device> m_maincpu;
56	56	required_device<cpu_device> m_subcpu;
57	57	required_device<tms34010_device> m_tms;
58
	58
59	59	required_shared_ptr<UINT32> m_blitter_regs;
60	60	required_shared_ptr<UINT32> m_fpga_ctrl;
61	61	required_shared_ptr<UINT16> m_fg_buffer;
62
	62
63	63	UINT32 *m_bg_buffer;
64	64	UINT32 *m_bg_buffer_front;
65	65	UINT32 *m_bg_buffer_back;
r32760	r32761
69	69	UINT32 m_blitter_src_dx;
70	70	UINT32 m_blitter_src_y;
71	71	UINT32 m_blitter_src_dy;
72
	72
73	73	DECLARE_WRITE32_MEMBER(skimaxx_blitter_w);
74	74	DECLARE_READ32_MEMBER(skimaxx_blitter_r);
75	75	DECLARE_WRITE32_MEMBER(skimaxx_fpga_ctrl_w);
r32760	r32761
79	79	DECLARE_WRITE32_MEMBER(skimaxx_sub_ctrl_w);
80	80	DECLARE_READ32_MEMBER(skimaxx_analog_r);
81	81	DECLARE_WRITE_LINE_MEMBER(tms_irq);
82
	82
83	83	TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg);
84	84	TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg);
85	85	TMS340X0_SCANLINE_IND16_CB_MEMBER(scanline_update);
86
	86
87	87	virtual void machine_reset();
88	88	virtual void video_start();
89	89	};

trunk/src/mame/drivers/xtheball.c
r32760	r32761
327	327	MCFG_CPU_PROGRAM_MAP(main_map)
328	328	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
329	329	MCFG_TMS340X0_PIXEL_CLOCK(10000000) /* pixel clock */
330		MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
	330	MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
331	331	MCFG_TMS340X0_SCANLINE_RGB32_CB(xtheball_state, scanline_update) /* scanline updater (rgb32) */
332	332	MCFG_TMS340X0_TO_SHIFTREG_CB(xtheball_state, to_shiftreg) /* write to shiftreg function */
333	333	MCFG_TMS340X0_FROM_SHIFTREG_CB(xtheball_state, from_shiftreg) /* read from shiftreg function */

trunk/src/mame/drivers/punchout.c
r32760	r32761
234	234	{
235	235	// d0-d3: D0-D3 to RP5C01
236	236	m_rtc->write(space, offset >> 4 & 0xf, data & 0xf);
237
	237
238	238	// d0: 74LS74 1D + 74LS74 2D
239	239	// 74LS74 1Q -> RP5H01 DATA CLOCK + TEST
240	240	// 74LS74 2Q -> RP5H01 RESET
r32760	r32761
516	516	1110 1xxx 20 20 0*
517	517
518	518	1111 xxxx "Freeplay"
519
	519
520	520	0*: Not a "Freeplay": you MUST insert a coin!
521	521
522	522	*/
r32760	r32761
682	682	MCFG_DEVICE_ADD("rtc", RP5C01, 0) // OSCIN -> Vcc
683	683	MCFG_RP5C01_REMOVE_BATTERY()
684	684	MCFG_RP5H01_ADD("rp5h01")
685
	685
686	686	MCFG_MACHINE_RESET_OVERRIDE(punchout_state, spnchout)
687	687	MACHINE_CONFIG_END
688	688
r32760	r32761
743	743	ROM_CONTINUE( 0x03800, 0x0800 )
744	744
745	745	ROM_REGION( 0x30000, "gfx3", ROMREGION_ERASEFF )
746		ROM_LOAD( "chp1-v.2r", 0x00000, 0x4000, CRC(bd1d4b2e) SHA1(492ae301a9890c2603d564c9048b1b67895052dd) ) /* chars #3 / / Labeled Rev B, but same as Rev A */
	746	ROM_LOAD( "chp1-v.2r", 0x00000, 0x4000, CRC(bd1d4b2e) SHA1(492ae301a9890c2603d564c9048b1b67895052dd) ) /* chars #3 / / Labeled Rev B, but same as Rev A */
747	747	ROM_LOAD( "chp1-v.2t", 0x04000, 0x4000, CRC(dd9a688a) SHA1(fbb98eebfbaab445928da939846a2d07a8046afb) )
748	748	ROM_LOAD( "chp1-v.2u", 0x08000, 0x2000, CRC(da6a3c4b) SHA1(e03469fb6f552f41a9b7f4b3e51c15a52b61cf84) )
749	749	/* 0a000-0bfff empty (space for 16k ROM) */
r32760	r32761
762	762	/* 2c000-2ffff empty (4v doesn't exist, it is seen as a 0xff fill) */
763	763
764	764	ROM_REGION( 0x10000, "gfx4", ROMREGION_ERASEFF )
765		ROM_LOAD( "chp1-v.6p", 0x00000, 0x0800, CRC(75be7aae) SHA1(396bc1d301b99e064de4dad699882618b1b9c958) ) /* chars #4 / / Revision B */
	765	ROM_LOAD( "chp1-v.6p", 0x00000, 0x0800, CRC(75be7aae) SHA1(396bc1d301b99e064de4dad699882618b1b9c958) ) /* chars #4 / / Revision B */
766	766	ROM_CONTINUE( 0x01000, 0x0800 )
767	767	ROM_CONTINUE( 0x00800, 0x0800 )
768	768	ROM_CONTINUE( 0x01800, 0x0800 )
769		ROM_LOAD( "chp1-v.6n", 0x02000, 0x0800, CRC(daf74de0) SHA1(9373d4527b675b3128a5a830f42e1dc5dcb85307) ) /* Revision B */
	769	ROM_LOAD( "chp1-v.6n", 0x02000, 0x0800, CRC(daf74de0) SHA1(9373d4527b675b3128a5a830f42e1dc5dcb85307) ) /* Revision B */
770	770	ROM_CONTINUE( 0x03000, 0x0800 )
771	771	ROM_CONTINUE( 0x02800, 0x0800 )
772	772	ROM_CONTINUE( 0x03800, 0x0800 )
773	773	/* 04000-07fff empty (space for 6l and 6k) */
774		ROM_LOAD( "chp1-v.8p", 0x08000, 0x0800, CRC(4cb7ea82) SHA1(213b7c1431f4c92e5519a8771035bda28b3bab8a) ) /* Revision B */
	774	ROM_LOAD( "chp1-v.8p", 0x08000, 0x0800, CRC(4cb7ea82) SHA1(213b7c1431f4c92e5519a8771035bda28b3bab8a) ) /* Revision B */
775	775	ROM_CONTINUE( 0x09000, 0x0800 )
776	776	ROM_CONTINUE( 0x08800, 0x0800 )
777	777	ROM_CONTINUE( 0x09800, 0x0800 )
778		ROM_LOAD( "chp1-v.8n", 0x0a000, 0x0800, CRC(1c0d09aa) SHA1(3276bae7400453f3612f53d7b47fb199cbe53e6d) ) /* Revision B */
	778	ROM_LOAD( "chp1-v.8n", 0x0a000, 0x0800, CRC(1c0d09aa) SHA1(3276bae7400453f3612f53d7b47fb199cbe53e6d) ) /* Revision B */
779	779	ROM_CONTINUE( 0x0b000, 0x0800 )
780	780	ROM_CONTINUE( 0x0a800, 0x0800 )
781	781	ROM_CONTINUE( 0x0b800, 0x0800 )
r32760	r32761
798	798	ROM_LOAD( "chp1-b-8f_white.8f", 0x1a00, 0x0200, CRC(1ffd894a) SHA1(9e8c1c28b4c12acf42f814bc109d353729a25652) ) /* B */
799	799	ROM_LOAD( "chp1-v-2d.2d", 0x2000, 0x0100, CRC(71dc0d48) SHA1(dd6609f547d74887f520d7e71a1a00317ff181d0) ) /* timing - not used */
800	800
801		ROM_REGION( 0x4000, "vlm", 0 ) /* 16k for the VLM5030 data */
	801	ROM_REGION( 0x4000, "vlm", 0 ) /* 16k for the VLM5030 data */
802	802	ROM_LOAD( "chp1-c.6p", 0x0000, 0x4000, CRC(ea0bbb31) SHA1(b1da024cb688341d39791a78d1144fe09acb00cf) )
803	803	ROM_END
804	804
r32760	r32761
1184	1184	ROM_LOAD( "chs1-b-8f_white.8f", 0x1a00, 0x0200, CRC(1663eed7) SHA1(90ff876a6b885f8a80c17531cde8b91864f1a6a5) ) /* B */
1185	1185	ROM_LOAD( "chs1-v.2d", 0x2000, 0x0100, CRC(71dc0d48) SHA1(dd6609f547d74887f520d7e71a1a00317ff181d0) ) /* timing - not used */
1186	1186
1187		ROM_REGION( 0x4000, "vlm", 0 ) /* 16k for the VLM5030 data */
	1187	ROM_REGION( 0x4000, "vlm", 0 ) /* 16k for the VLM5030 data */
1188	1188	ROM_LOAD( "chs1-c.6p", 0x0000, 0x4000, CRC(ad8b64b8) SHA1(0f1232a10faf71b782f9f6653cca8570243c17e0) )
1189	1189	ROM_END
1190	1190

trunk/src/mame/drivers/maxaflex.c
r32760	r32761
73	73	TIMER_DEVICE_CALLBACK_MEMBER(mcu_timer_proc);
74	74	int atari_input_disabled();
75	75	virtual void machine_reset();
76		//required_device<cpu_device> m_maincpu; // maincpu is already contained in atari_common_state
	76	//required_device<cpu_device> m_maincpu; // maincpu is already contained in atari_common_state
77	77	required_device<cpu_device> m_mcu;
78	78	required_device<speaker_sound_device> m_speaker;
79	79	required_memory_region m_region_maincpu;
r32760	r32761
408	408	m_portC_in = m_portC_out = m_ddrC = 0;
409	409	m_tdr = m_tcr = 0;
410	410	m_mcu_timer = machine().device<timer_device>("mcu_timer");
411
	411
412	412	output_set_lamp_value(0, 0);
413	413	output_set_lamp_value(1, 0);
414	414	output_set_lamp_value(2, 0);

trunk/src/mame/drivers/nmk16.c
r32760	r32761
72	72	- Vandyke: Many enemies make very strange sounds because they seem to have no
73	73	rate limit for making their sound effect. This is normal, it's like this on all
74	74	PCB recordings.
75
76	75
	76
77	77	----
78	78
79	79	tdragon and hachamf test mode:
r32760	r32761
354	354	AM_RANGE(0x080002, 0x080003) AM_READ_PORT("IN1")
355	355	AM_RANGE(0x080008, 0x080009) AM_READ_PORT("DSW1")
356	356	AM_RANGE(0x08000a, 0x08000b) AM_READ_PORT("DSW2")
357		// AM_RANGE(0x08000e, 0x08000f) AM_DEVREAD8("nmk004", nmk004_device, read, 0x00ff)
	357	// AM_RANGE(0x08000e, 0x08000f) AM_DEVREAD8("nmk004", nmk004_device, read, 0x00ff)
358	358	AM_RANGE(0x080016, 0x080017) AM_WRITENOP /* IRQ enable? */
359	359	AM_RANGE(0x080018, 0x080019) AM_WRITE(nmk_tilebank_w)
360	360	AM_RANGE(0x080010, 0x08001d) AM_WRITE(vandykeb_scroll_w) /* 10, 12, 1a, 1c */
361		// AM_RANGE(0x08001e, 0x08001f) AM_DEVWRITE8("nmk004", nmk004_device, write, 0x00ff)
	361	// AM_RANGE(0x08001e, 0x08001f) AM_DEVWRITE8("nmk004", nmk004_device, write, 0x00ff)
362	362	AM_RANGE(0x088000, 0x0887ff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
363	363	AM_RANGE(0x08c000, 0x08c007) AM_WRITENOP /* just in case... */
364	364	AM_RANGE(0x090000, 0x093fff) AM_RAM_WRITE(nmk_bgvideoram0_w) AM_SHARE("nmk_bgvideoram0")
r32760	r32761
625	625	case 0xe51e/2: PROT_INPUT(0xe51e/2,0x0f82,0xe008/2,0x00080008); break;
626	626	case 0xe6b4/2: PROT_INPUT(0xe6b4/2,0x79be,0xe00c/2,0x0008000a); break;
627	627	case 0xe10e/2: PROT_JSR(0xe10e,0x8007,0x870a);//870a not 9d66
628		PROT_JSR(0xe10e,0x8000,0xd9c6); break;
	628	PROT_JSR(0xe10e,0x8000,0xd9c6); break;
629	629	case 0xe11e/2: PROT_JSR(0xe11e,0x8038,DUMMYA);//972a - (unused)
630		PROT_JSR(0xe11e,0x8031,0x7a54); break;
	630	PROT_JSR(0xe11e,0x8031,0x7a54); break;
631	631	case 0xe12e/2: PROT_JSR(0xe12e,0x8019,0x9642);//OK-9642
632		PROT_JSR(0xe12e,0x8022,0xda06); break;
	632	PROT_JSR(0xe12e,0x8022,0xda06); break;
633	633	case 0xe13e/2: PROT_JSR(0xe13e,0x802a,0x9d66);//9d66 not 9400 - OK
634		PROT_JSR(0xe13e,0x8013,0x81aa); break;
	634	PROT_JSR(0xe13e,0x8013,0x81aa); break;
635	635	case 0xe14e/2: PROT_JSR(0xe14e,0x800b,0xb3f2);//b3f2 - OK
636		PROT_JSR(0xe14e,0x8004,0x8994); break;
	636	PROT_JSR(0xe14e,0x8004,0x8994); break;
637	637	case 0xe15e/2: PROT_JSR(0xe15e,0x803c,0xb59e);//b59e - OK
638		PROT_JSR(0xe15e,0x8035,0x8c36); break;
	638	PROT_JSR(0xe15e,0x8035,0x8c36); break;
639	639	case 0xe16e/2: PROT_JSR(0xe16e,0x801d,0x9ac2);//9ac2 - OK
640		PROT_JSR(0xe16e,0x8026,0x8d0c); break;
	640	PROT_JSR(0xe16e,0x8026,0x8d0c); break;
641	641	case 0xe17e/2: PROT_JSR(0xe17e,0x802e,0xc366);//c366 - OK
642		PROT_JSR(0xe17e,0x8017,0x870a); break;
	642	PROT_JSR(0xe17e,0x8017,0x870a); break;
643	643	case 0xe18e/2: PROT_JSR(0xe18e,0x8004,DUMMYA); //unused
644		PROT_JSR(0xe18e,0x8008,DUMMYA); break; //unused
	644	PROT_JSR(0xe18e,0x8008,DUMMYA); break; //unused
645	645	case 0xe19e/2: PROT_JSR(0xe19e,0x8030,0xd9c6);//OK-d9c6
646		PROT_JSR(0xe19e,0x8039,0x9642); break;
	646	PROT_JSR(0xe19e,0x8039,0x9642); break;
647	647	case 0xe1ae/2: PROT_JSR(0xe1ae,0x8011,0x7a54);//d1f8 not c67e
648		PROT_JSR(0xe1ae,0x802a,0x9d66); break;
	648	PROT_JSR(0xe1ae,0x802a,0x9d66); break;
649	649	case 0xe1be/2: PROT_JSR(0xe1be,0x8022,0xda06);//da06
650		PROT_JSR(0xe1be,0x801b,0xb3f2); break;
	650	PROT_JSR(0xe1be,0x801b,0xb3f2); break;
651	651	case 0xe1ce/2: PROT_JSR(0xe1ce,0x8003,0x81aa);//81aa
652		PROT_JSR(0xe1ce,0x800c,0xb59e); break;
	652	PROT_JSR(0xe1ce,0x800c,0xb59e); break;
653	653	case 0xe1de/2: PROT_JSR(0xe1de,0x8034,0x8994);//8994 - OK
654		PROT_JSR(0xe1de,0x803d,0x9ac2); break;
	654	PROT_JSR(0xe1de,0x803d,0x9ac2); break;
655	655	case 0xe1ee/2: PROT_JSR(0xe1ee,0x8015,0x8c36);//8d0c not 82f6
656		PROT_JSR(0xe1ee,0x802e,0xc366); break;
	656	PROT_JSR(0xe1ee,0x802e,0xc366); break;
657	657	case 0xe1fe/2: PROT_JSR(0xe1fe,0x8026,0x8d0c);//8c36
658		PROT_JSR(0xe1fe,0x8016,DUMMYA); break; //unused
	658	PROT_JSR(0xe1fe,0x8016,DUMMYA); break; //unused
659	659	case 0xef00/2:
660	660	if(m_mainram[0xef00/2] == 0x60fe)
661	661	{
r32760	r32761
667	667	}
668	668	break;
669	669	}
670		#undef DUMMYA
	670	#undef DUMMYA
671	671	}
672	672
673	673
r32760	r32761
3809	3809	\| \| DMA \| \|
3810	3810
3811	3811	CPU is stopped during DMA
3812
	3812
3813	3813	*/
3814	3814
3815	3815	// todo:total scanlines is 263, adjust according to that!
r32760	r32761
3820	3820	const int IRQ1_SCANLINE = 25; // guess
3821	3821	const int VBIN_SCANLINE = 0;
3822	3822	const int VBOUT_sCANLINE = 240;
3823		const int SPRDMA_SCANLINE = 241; // 256 USEC after VBOUT
	3823	const int SPRDMA_SCANLINE = 241; // 256 USEC after VBOUT
3824	3824
3825	3825	int scanline = param;
3826	3826
3827		if(scanline == VBOUT_sCANLINE) // vblank-out irq
3828		m_maincpu->set_input_line(4, HOLD_LINE);
	3827	if(scanline == VBOUT_sCANLINE) // vblank-out irq
	3828	m_maincpu->set_input_line(4, HOLD_LINE);
3829	3829
3830		if (scanline == SPRDMA_SCANLINE)
3831		{
3832		// 2 buffers confirmed on PCB
3833		memcpy(m_spriteram_old2,m_spriteram_old, 0x1000);
3834		memcpy(m_spriteram_old, m_mainram + m_sprdma_base / 2, 0x1000);
3835		}
	3830	if (scanline == SPRDMA_SCANLINE)
	3831	{
	3832	// 2 buffers confirmed on PCB
	3833	memcpy(m_spriteram_old2,m_spriteram_old, 0x1000);
	3834	memcpy(m_spriteram_old, m_mainram + m_sprdma_base / 2, 0x1000);
	3835	}
3836	3836
3837		/* Vblank-in irq, Vandyke definitely relies that irq fires at scanline ~0 instead of 112 (as per previous
3838		cpu_getiloops function implementation), mostly noticeable with sword collisions and related attract mode behaviour. */
3839		if(scanline == VBIN_SCANLINE)
3840		m_maincpu->set_input_line(2, HOLD_LINE);
	3837	/* Vblank-in irq, Vandyke definitely relies that irq fires at scanline ~0 instead of 112 (as per previous
	3838	cpu_getiloops function implementation), mostly noticeable with sword collisions and related attract mode behaviour. */
	3839	if(scanline == VBIN_SCANLINE)
	3840	m_maincpu->set_input_line(2, HOLD_LINE);
3841	3841
3842		/* time from IRQ2 to first IRQ1 fire. is not stated, 25 is a guess */
3843		if(scanline == IRQ1_SCANLINE)
3844		m_maincpu->set_input_line(1, HOLD_LINE);
	3842	/* time from IRQ2 to first IRQ1 fire. is not stated, 25 is a guess */
	3843	if(scanline == IRQ1_SCANLINE)
	3844	m_maincpu->set_input_line(1, HOLD_LINE);
3845	3845
3846		/* 8.9ms from first IRQ1 to second IRQ1 fire. approx 128 lines (half frame time) */
3847		if(scanline == IRQ1_SCANLINE+(NUM_SCANLINES/2)) // if this happens too late bioship sprites will glitch on the left edge
3848		m_maincpu->set_input_line(1, HOLD_LINE);
	3846	/* 8.9ms from first IRQ1 to second IRQ1 fire. approx 128 lines (half frame time) */
	3847	if(scanline == IRQ1_SCANLINE+(NUM_SCANLINES/2)) // if this happens too late bioship sprites will glitch on the left edge
	3848	m_maincpu->set_input_line(1, HOLD_LINE);
3849	3849	}
3850	3850
3851	3851	#define NMK_HACKY_INTERRUPT_TIMING \
3852		MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", nmk16_state, nmk16_scanline, "screen", 0, 1) \
3853
	3852	MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", nmk16_state, nmk16_scanline, "screen", 0, 1)
3854	3853	#define NMK_HACKY_SCREEN_LOWRES \
3855	3854	MCFG_SCREEN_ADD("screen", RASTER) \
3856	3855	MCFG_SCREEN_REFRESH_RATE(56.18) \
r32760	r32761
3884	3883	/* video hardware */
3885	3884	NMK_HACKY_SCREEN_LOWRES
3886	3885	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_tharrier)
3887
3888	3886
	3887
3889	3888	MCFG_GFXDECODE_ADD("gfxdecode", "palette", tharrier)
3890	3889	MCFG_PALETTE_ADD("palette", 512)
3891	3890	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBRGBx)
r32760	r32761
3918	3917	/* video hardware */
3919	3918	NMK_HACKY_SCREEN_LOWRES
3920	3919	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_macross)
3921
3922	3920
	3921
3923	3922	MCFG_GFXDECODE_ADD("gfxdecode", "palette", macross)
3924	3923	MCFG_PALETTE_ADD("palette", 1024)
3925	3924	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBRGBx)
r32760	r32761
3957	3956	/* video hardware */
3958	3957	NMK_HACKY_SCREEN_LOWRES
3959	3958	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_macross)
3960
3961	3959
	3960
3962	3961	MCFG_GFXDECODE_ADD("gfxdecode", "palette", macross)
3963	3962	MCFG_PALETTE_ADD("palette", 1024)
3964	3963	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBRGBx)
r32760	r32761
3983	3982	/* video hardware */
3984	3983	NMK_HACKY_SCREEN_LOWRES
3985	3984	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_bioship)
3986
3987	3985
	3986
3988	3987	MCFG_GFXDECODE_ADD("gfxdecode", "palette", bioship)
3989	3988	MCFG_PALETTE_ADD("palette", 1024)
3990	3989	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBRGBx)
r32760	r32761
4020	4019	/* video hardware */
4021	4020	NMK_HACKY_SCREEN_LOWRES
4022	4021	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_macross)
4023
4024	4022
	4023
4025	4024	MCFG_GFXDECODE_ADD("gfxdecode", "palette", macross)
4026	4025	MCFG_PALETTE_ADD("palette", 1024)
4027	4026	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBRGBx)
r32760	r32761
4060	4059	/* video hardware */
4061	4060	NMK_HACKY_SCREEN_LOWRES
4062	4061	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_macross)
4063
4064	4062
	4063
4065	4064	MCFG_GFXDECODE_ADD("gfxdecode", "palette", macross)
4066	4065	MCFG_PALETTE_ADD("palette", 1024)
4067	4066	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBRGBx)
r32760	r32761
4085	4084	/* video hardware */
4086	4085	NMK_HACKY_SCREEN_LOWRES
4087	4086	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_macross)
4088
4089	4087
	4088
4090	4089	MCFG_GFXDECODE_ADD("gfxdecode", "palette", macross)
4091	4090	MCFG_PALETTE_ADD("palette", 1024)
4092	4091	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBxxxx)
r32760	r32761
4125	4124	/* video hardware */
4126	4125	NMK_HACKY_SCREEN_LOWRES
4127	4126	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_macross)
4128
4129	4127
	4128
4130	4129	MCFG_GFXDECODE_ADD("gfxdecode", "palette", macross)
4131	4130	MCFG_PALETTE_ADD("palette", 1024)
4132	4131	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBRGBx)
r32760	r32761
4147	4146	/* video hardware */
4148	4147	NMK_HACKY_SCREEN_LOWRES
4149	4148	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_macross)
4150
4151	4149
	4150
4152	4151	MCFG_GFXDECODE_ADD("gfxdecode", "palette", macross)
4153	4152	MCFG_PALETTE_ADD("palette", 1024)
4154	4153	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBRGBx)
r32760	r32761
4190	4189	/* video hardware */
4191	4190	NMK_HACKY_SCREEN_LOWRES
4192	4191	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_macross)
4193
4194	4192
	4193
4195	4194	MCFG_GFXDECODE_ADD("gfxdecode", "palette", macross)
4196	4195	MCFG_PALETTE_ADD("palette", 1024)
4197	4196	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBRGBx)
r32760	r32761
4216	4215	/* video hardware */
4217	4216	NMK_HACKY_SCREEN_LOWRES
4218	4217	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_strahl)
4219
	4218
4220	4219	MCFG_GFXDECODE_ADD("gfxdecode", "palette", strahl)
4221	4220	MCFG_PALETTE_ADD("palette", 1024)
4222	4221	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBxxxx)
r32760	r32761
4252	4251	/* video hardware */
4253	4252	NMK_HACKY_SCREEN_LOWRES
4254	4253	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_macross)
4255
4256	4254
	4255
4257	4256	MCFG_GFXDECODE_ADD("gfxdecode", "palette", macross)
4258	4257	MCFG_PALETTE_ADD("palette", 1024)
4259	4258	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBRGBx)
r32760	r32761
4293	4292	/* video hardware */
4294	4293	NMK_HACKY_SCREEN_LOWRES
4295	4294	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_macross)
4296
4297	4295
	4296
4298	4297	MCFG_GFXDECODE_ADD("gfxdecode", "palette", macross)
4299	4298	MCFG_PALETTE_ADD("palette", 1024)
4300	4299	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBRGBx)
r32760	r32761
4330	4329	/* video hardware */
4331	4330	NMK_HACKY_SCREEN_LOWRES
4332	4331	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_macross)
4333
4334	4332
	4333
4335	4334	MCFG_GFXDECODE_ADD("gfxdecode", "palette", macross)
4336	4335	MCFG_PALETTE_ADD("palette", 1024)
4337	4336	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBRGBx)
r32760	r32761
4367	4366	/* video hardware */
4368	4367	NMK_HACKY_SCREEN_HIRES
4369	4368	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_gunnail)
4370
4371	4369
4372	4370
4373	4371
	4372
4374	4373	MCFG_GFXDECODE_ADD("gfxdecode", "palette", macross)
4375	4374	MCFG_PALETTE_ADD("palette", 1024)
4376	4375	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBRGBx)
r32760	r32761
4410	4409	/* video hardware */
4411	4410	NMK_HACKY_SCREEN_HIRES
4412	4411	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_gunnail)
4413
4414	4412
	4413
4415	4414	MCFG_GFXDECODE_ADD("gfxdecode", "palette", macross2)
4416	4415	MCFG_PALETTE_ADD("palette", 1024)
4417	4416	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBRGBx)
r32760	r32761
4453	4452	/* video hardware */
4454	4453	NMK_HACKY_SCREEN_HIRES
4455	4454	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_tdragon2)
4456
4457	4455
	4456
4458	4457	MCFG_GFXDECODE_ADD("gfxdecode", "palette", macross2)
4459	4458	MCFG_PALETTE_ADD("palette", 1024)
4460	4459	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBRGBx)
r32760	r32761
4495	4494	/* video hardware */
4496	4495	NMK_HACKY_SCREEN_HIRES
4497	4496	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_tdragon2)
4498
4499	4497
	4498
4500	4499	MCFG_GFXDECODE_ADD("gfxdecode", "palette", macross2)
4501	4500	MCFG_PALETTE_ADD("palette", 1024)
4502	4501	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBRGBx)
r32760	r32761
4534	4533	/* video hardware */
4535	4534	NMK_HACKY_SCREEN_HIRES
4536	4535	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_bjtwin)
4537
4538	4536
	4537
4539	4538	MCFG_GFXDECODE_ADD("gfxdecode", "palette", bjtwin)
4540	4539	MCFG_PALETTE_ADD("palette", 1024)
4541	4540	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBRGBx)
r32760	r32761
4568	4567	/* video hardware */
4569	4568	NMK_HACKY_SCREEN_HIRES
4570	4569	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_bjtwin)
4571
4572	4570
	4571
4573	4572	MCFG_GFXDECODE_ADD("gfxdecode", "palette", atombjt)
4574	4573	MCFG_PALETTE_ADD("palette", 1024)
4575	4574	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBRGBx)
r32760	r32761
4624	4623	MCFG_SCREEN_SIZE(256, 256)
4625	4624	MCFG_SCREEN_VISIBLE_AREA(08, 328-1, 18, 318-1)
4626	4625	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_manybloc)
4627
	4626
4628	4627	MCFG_SCREEN_PALETTE("palette")
4629	4628
4630	4629	MCFG_GFXDECODE_ADD("gfxdecode", "palette", tharrier)
r32760	r32761
5095	5094	/* video hardware */
5096	5095	NMK_HACKY_SCREEN_LOWRES
5097	5096	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_afega)
5098
5099	5097
	5098
5100	5099	MCFG_GFXDECODE_ADD("gfxdecode", "palette", stagger1)
5101	5100	MCFG_PALETTE_ADD("palette", 768)
5102	5101	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBRGBx)
r32760	r32761
5177	5176	/* video hardware */
5178	5177	NMK_HACKY_SCREEN_LOWRES
5179	5178	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_firehawk)
5180
5181	5179
	5180
5182	5181	MCFG_GFXDECODE_ADD("gfxdecode", "palette", grdnstrm)
5183	5182	MCFG_PALETTE_ADD("palette", 768)
5184	5183	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBRGBx)
r32760	r32761
5208	5207	/* video hardware */
5209	5208	NMK_HACKY_SCREEN_LOWRES
5210	5209	MCFG_SCREEN_UPDATE_DRIVER(nmk16_state, screen_update_macross)
5211
5212	5210
	5211
5213	5212	MCFG_GFXDECODE_ADD("gfxdecode", "palette", macross)
5214	5213	MCFG_PALETTE_ADD("palette", 1024)
5215	5214	MCFG_PALETTE_FORMAT(RRRRGGGGBBBBRGBx)
r32760	r32761
6001	6000
6002	6001	ROM_REGION( 0xa0000, "oki1", 0 ) /* Oki sample data */
6003	6002	ROM_LOAD( "str8pmw1.540", 0x00000, 0x20000, CRC(01d6bb6a) SHA1(b157f6f921483ed8067a7e13e370f73fdb60d136) )
6004		/* this is a mess */
	6003	/* this is a mess */
6005	6004	ROM_CONTINUE( 0x80000, 0x20000 ) /* banked */
6006	6005	ROM_CONTINUE( 0x60000, 0x20000 ) /* banked */
6007	6006	ROM_CONTINUE( 0x40000, 0x20000 ) /* banked */
6008	6007
6009	6008	ROM_REGION( 0xa0000, "oki2", 0 ) /* Oki sample data */
6010	6009	ROM_LOAD( "str9pew1.639", 0x00000, 0x20000, CRC(6bb3eb9f) SHA1(9c1394df4f8a08f9098c85eb3d38fb862d6eabbb) )
6011		/* this is a mess */
	6010	/* this is a mess */
6012	6011	ROM_CONTINUE( 0x80000, 0x20000 ) /* banked */
6013	6012	ROM_CONTINUE( 0x60000, 0x20000 ) /* banked */
6014	6013	ROM_CONTINUE( 0x40000, 0x20000 ) /* banked */
r32760	r32761
6038	6037
6039	6038	ROM_REGION( 0xa0000, "oki1", 0 ) /* Oki sample data */
6040	6039	ROM_LOAD( "str8pmw1.540", 0x00000, 0x20000, CRC(01d6bb6a) SHA1(b157f6f921483ed8067a7e13e370f73fdb60d136) )
6041		/* this is a mess */
	6040	/* this is a mess */
6042	6041	ROM_CONTINUE( 0x80000, 0x20000 ) /* banked */
6043	6042	ROM_CONTINUE( 0x60000, 0x20000 ) /* banked */
6044	6043	ROM_CONTINUE( 0x40000, 0x20000 ) /* banked */
6045	6044
6046	6045	ROM_REGION( 0xa0000, "oki2", 0 ) /* Oki sample data */
6047	6046	ROM_LOAD( "str9pew1.639", 0x00000, 0x20000, CRC(6bb3eb9f) SHA1(9c1394df4f8a08f9098c85eb3d38fb862d6eabbb) )
6048		/* this is a mess */
	6047	/* this is a mess */
6049	6048	ROM_CONTINUE( 0x80000, 0x20000 ) /* banked */
6050	6049	ROM_CONTINUE( 0x60000, 0x20000 ) /* banked */
6051	6050	ROM_CONTINUE( 0x40000, 0x20000 ) /* banked */

trunk/src/mame/drivers/namcops2.c
r32760	r32761
208	208	SYSTEM256_BIOS
209	209
210	210	ROM_REGION(0x840000, "key", ROMREGION_ERASE00)
211		ROM_LOAD( "kn2vera.ic002", 0x000000, 0x800000, CRC(fb2f71f7) SHA1(29a331cc171d395ad10b352b9b30a61a455a50fe) )
212		ROM_LOAD( "kn2vera_spr.ic002", 0x800000, 0x040000, CRC(9c18fa50) SHA1(1f75052cf264c3f2e5b332a755d30544d6e5f45c) )
	211	ROM_LOAD( "kn2vera.ic002", 0x000000, 0x800000, CRC(fb2f71f7) SHA1(29a331cc171d395ad10b352b9b30a61a455a50fe) )
	212	ROM_LOAD( "kn2vera_spr.ic002", 0x800000, 0x040000, CRC(9c18fa50) SHA1(1f75052cf264c3f2e5b332a755d30544d6e5f45c) )
213	213
214	214	DISK_REGION("dvd")
215	215	DISK_IMAGE_READONLY( "kn2", 0, SHA1(3e1b773cc584911b673d46f9296a5b1a2cef9a45) )
r32760	r32761
526	526	ROM_LOAD( "fud1vera.ic002", 0x000000, 0x800000, CRC(892ffdd1) SHA1(4a444ed49e5c89dd0af4f026626a164b9eec61d1) )
527	527	ROM_LOAD( "fud1vera_spr.ic002", 0x800000, 0x040000, CRC(0fca4e99) SHA1(0bd74de26f10089ee848f03093229abfa8c84663) )
528	528
529		DISK_REGION("dvd") // actually HDD for this game
	529	DISK_REGION("dvd") // actually HDD for this game
530	530	DISK_IMAGE_READONLY( "fud-hdd0-a", 0, SHA1(1189863ae0e339e11708b9660521f86b3b97bc9e) )
531	531	ROM_END
532	532
r32760	r32761
558	558	SYSTEM256_BIOS
559	559
560	560	ROM_REGION(0x840000, "key", ROMREGION_ERASE00)
561		ROM_LOAD( "gnx1001-na-a.ic002", 0x000000, 0x800000, CRC(1d6d2f54) SHA1(17f6e7278e61b5b81605175d3f2df7b747ca7246) )
562		ROM_LOAD( "gnx1001-na-a_spr.ic002", 0x800000, 0x040000, CRC(a999ba5c) SHA1(009a56f7be50b57bf435fb8c8b41cf14086b1d1a) )
	561	ROM_LOAD( "gnx1001-na-a.ic002", 0x000000, 0x800000, CRC(1d6d2f54) SHA1(17f6e7278e61b5b81605175d3f2df7b747ca7246) )
	562	ROM_LOAD( "gnx1001-na-a_spr.ic002", 0x800000, 0x040000, CRC(a999ba5c) SHA1(009a56f7be50b57bf435fb8c8b41cf14086b1d1a) )
563	563
564		DISK_REGION("dvd") // actually HDD for this game
	564	DISK_REGION("dvd") // actually HDD for this game
565	565	DISK_IMAGE_READONLY( "gnx100-1na-a", 0, SHA1(a2344f533895793a2e13198c7de0c759f0dbf817) )
566	566	ROM_END
567	567
r32760	r32761
581	581	SYSTEM246_BIOS
582	582
583	583	ROM_REGION(0x840000, "key", ROMREGION_ERASE00)
584		ROM_LOAD( "bax1vera.ic002", 0x000000, 0x800000, CRC(18a6f424) SHA1(027a8d371fb6782c906434b86db9779057eaa954) )
585		ROM_LOAD( "bax1vera_spr.ic002", 0x800000, 0x040000, CRC(abfb749b) SHA1(b45f8c79dd0cc0359f27c33f55626d6cad82127c) )
	584	ROM_LOAD( "bax1vera.ic002", 0x000000, 0x800000, CRC(18a6f424) SHA1(027a8d371fb6782c906434b86db9779057eaa954) )
	585	ROM_LOAD( "bax1vera_spr.ic002", 0x800000, 0x040000, CRC(abfb749b) SHA1(b45f8c79dd0cc0359f27c33f55626d6cad82127c) )
586	586
587	587	DISK_REGION("dvd")
588	588	DISK_IMAGE_READONLY( "bax1_dvd0", 0, SHA1(56d58e66eeaa57ff07668000491360853b064936) )

trunk/src/mame/drivers/segaybd.c
r32760	r32761
809	809	ADDRESS_MAP_UNMAP_HIGH
810	810	ADDRESS_MAP_GLOBAL_MASK(0xff)
811	811
812		// AM_RANGE(0x40, 0x40) AM_READ_PORT("LinkDSW")
	812	// AM_RANGE(0x40, 0x40) AM_READ_PORT("LinkDSW")
813	813	AM_RANGE(0xc0, 0xc0) AM_READ(link_portc0_r)
814	814	ADDRESS_MAP_END
815	815
r32760	r32761
1809	1809	ROM_LOAD16_BYTE( "epr-11791.14", 0x000001, 0x20000, CRC(36b2910a) SHA1(9948b91837f944a7a606542fa685525e74bbe398) )
1810	1810	ROM_LOAD16_BYTE( "epr-11790.17", 0x040000, 0x20000, CRC(2a564e66) SHA1(5f30fc15bfd017d75cfffe1e9e62ed0bcf32a98e) )
1811	1811	ROM_LOAD16_BYTE( "epr-11792.15", 0x040001, 0x20000, CRC(c85caf6e) SHA1(2411ea99ec7f6e2b0b4f219e86ff2172539ad2c4) )
1812
	1812
1813	1813	ROM_REGION64_BE( 0x400000, "ysprites", 0)
1814	1814	ROMX_LOAD( "epr-11757.67", 0x000000, 0x20000, CRC(e46dc478) SHA1(baf79e230aef3d63fb50373b2b1626f7c56ee94f), ROM_SKIP(7) )
1815	1815	ROMX_LOAD( "epr-11758.75", 0x000001, 0x20000, CRC(5b435c87) SHA1(6b42b08e73957c36cd8faa896ca14461d00afd29), ROM_SKIP(7) )

trunk/src/mame/drivers/karnov.c
r32760	r32761
832	832
833	833	static ADDRESS_MAP_START( chelnovjbl_mcu_io_map, AS_IO, 8, karnov_state )
834	834	//internal port
835		// AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READWRITE(p1_r, p1_w)
836		// AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE(p3_r, p3_w)
	835	// AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READWRITE(p1_r, p1_w)
	836	// AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE(p3_r, p3_w)
837	837	ADDRESS_MAP_END
838	838
839	839
r32760	r32761
1181	1181	ROM_LOAD( "a-c5.bin", 0x00000, 0x08000, CRC(1abf2c6d) SHA1(86d625ae94cd9ea69e4e613895410640efb175b3) ) /* Characters */
1182	1182
1183	1183	ROM_REGION( 0x40000, "gfx2", 0 ) /* Backgrounds */ // same content split into more roms
1184		ROM_LOAD( "8.bin", 0x00000, 0x08000, CRC(a78b174a) SHA1(e0d82b600a154b81d7e1a787f0e20eb1a341894f) )
	1184	ROM_LOAD( "8.bin", 0x00000, 0x08000, CRC(a78b174a) SHA1(e0d82b600a154b81d7e1a787f0e20eb1a341894f) )
1185	1185	ROM_LOAD( "9.bin", 0x08000, 0x08000, CRC(97d2c146) SHA1(075bb9afc4f0623cd413883ec2bca574d7ff88d4) )
1186	1186	ROM_LOAD( "2.bin", 0x10000, 0x08000, CRC(8c45e7de) SHA1(d843b7dcc64ed3a5b8717af172a1f22c4c599480) )
1187	1187	ROM_LOAD( "3.bin", 0x18000, 0x08000, CRC(504cc95c) SHA1(97e5e9f8cd8ebf5e0c18f27f2988a45c4d3809b3) )
r32760	r32761
1233	1233	ROM_LOAD( "a-c5.bin", 0x00000, 0x08000, CRC(1abf2c6d) SHA1(86d625ae94cd9ea69e4e613895410640efb175b3) ) /* Characters */
1234	1234
1235	1235	ROM_REGION( 0x40000, "gfx2", 0 ) /* Backgrounds */ // same content split into more roms
1236		ROM_LOAD( "8.bin", 0x00000, 0x08000, CRC(a78b174a) SHA1(e0d82b600a154b81d7e1a787f0e20eb1a341894f) )
	1236	ROM_LOAD( "8.bin", 0x00000, 0x08000, CRC(a78b174a) SHA1(e0d82b600a154b81d7e1a787f0e20eb1a341894f) )
1237	1237	ROM_LOAD( "9.bin", 0x08000, 0x08000, CRC(97d2c146) SHA1(075bb9afc4f0623cd413883ec2bca574d7ff88d4) )
1238	1238	ROM_LOAD( "2.bin", 0x10000, 0x08000, CRC(8c45e7de) SHA1(d843b7dcc64ed3a5b8717af172a1f22c4c599480) )
1239	1239	ROM_LOAD( "3.bin", 0x18000, 0x08000, CRC(504cc95c) SHA1(97e5e9f8cd8ebf5e0c18f27f2988a45c4d3809b3) )

trunk/src/mame/drivers/cops.c
r32760	r32761
4	4	(hardware developed by Nova Productions Limited)
5	5	Preliminary driver by Mariusz Wojcieszek, James Wallace
6	6
7		Cops uses a Sony CD-ROM in addition to the regular setup, purely to play
8		Bad Boys by Inner Circle, so there is muscial accompaniment to areas
9		where the laserdisc audio is muted.
	7	Cops uses a Sony CD-ROM in addition to the regular setup, purely to play
	8	Bad Boys by Inner Circle, so there is muscial accompaniment to areas
	9	where the laserdisc audio is muted.
10	10
11		NOTES: To boot up Revelations, turn the refill key (R) and press button A.
	11	NOTES: To boot up Revelations, turn the refill key (R) and press button A.
12	12	TODO: There are probably more ROMs for Revelations, the disc contains
13		full data for a picture based memory game called 'Vision Quest'.
14
15		LaserMax memory map needs sorting out, Cops uses a subset of what's
16		actually available
	13	full data for a picture based memory game called 'Vision Quest'.
17	14
	15	LaserMax memory map needs sorting out, Cops uses a subset of what's
	16	actually available
	17
18	18	The UK version COPS appears to want to communicate with the LDP in a
19		different way.
	19	different way.
20	20	***************************************************************************/
21	21
22	22
r32760	r32761
355	355	*
356	356	*************************************/
357	357
358		void cops_state::update_dacia_irq()
	358	void cops_state::update_dacia_irq()
359	359	{
360	360	UINT8 isr = generate_isr();
361	361	//remove bits
r32760	r32761
390	390	UINT8 cops_state::generate_isr()
391	391	{
392	392	UINT8 isr =0;
393
	393
394	394	isr \|= m_dacia_receiver_full;
395	395	isr \|= (m_dacia_cmp1 << 1);
396		isr \|= (m_dacia_trans <<4);
397
	396	isr \|= (m_dacia_trans <<4);
	397
398	398	if (isr)
399	399	{
400	400	isr \|= 0x40;
r32760	r32761
413	413	m_maincpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
414	414	return isr;
415	415	}
416
	416
417	417	case 1: /* CSR1: Control Status Register */
418	418	{
419	419	UINT8 csr =0;
420	420	csr \|= m_dacia_rts1;
421	421	csr \|= (m_dacia_dtr1 << 1);
422		csr \|= (m_dacia_cts <<4);
423		csr \|= (m_dacia_fe1 <<7);
	422	csr \|= (m_dacia_cts <<4);
	423	csr \|= (m_dacia_fe1 <<7);
424	424	if (LOG_DACIA) logerror("CSR1 %02x\n",csr);
425	425	return csr;
426		}
	426	}
427	427
428	428	case 3: /* RDR1: Receive data register */
429	429	m_dacia_receiver_full = 0;
r32760	r32761
463	463	{
464	464	m_dacia_rts1 = (data & 0x01);
465	465	m_dacia_dtr1 = (data & 0x02 ? 1:0);
466		m_parity_1 = (data & 0x04);
467		m_parity_mode_1 = ((data & 0x18) >> 3);
	466	m_parity_1 = (data & 0x04);
	467	m_parity_mode_1 = ((data & 0x18) >> 3);
468	468	m_bpc_1 = ((data & 0x60) >> 5) +5;
469	469	if (LOG_DACIA) logerror("DACIA Format Register: %02x\n", data);
470	470	}
r32760	r32761
479	479	}
480	480	else
481	481	{
482		m_dacia_reg1 = CMP_REGISTER;
	482	m_dacia_reg1 = CMP_REGISTER;
483	483	}
484	484	if (LOG_DACIA) logerror("DACIA TIME %02d\n", XTAL_3_6864MHz / m_dacia_ic_div_1);
485
	485
486	486	m_ld_timer->adjust(attotime::from_hz(XTAL_3_6864MHz / m_dacia_ic_div_1), 0, attotime::from_hz(XTAL_3_6864MHz / m_dacia_ic_div_1));
487	487
488	488	if (LOG_DACIA) logerror("DACIA Ctrl Register: %02x\n", data);
489
	489
490	490	}
491	491	break;
492		}
	492	}
493	493	case 2: /* Compare / Aux Ctrl Register 1 */
494	494	{
495		if (m_dacia_reg1 == CMP_REGISTER)
	495	if (m_dacia_reg1 == CMP_REGISTER)
496	496	{
497	497	m_dacia_cmp1 =1;
498	498	m_dacia_cmpval1=data;
499		if (LOG_DACIA) logerror("DACIA Compare mode: %02x \n", data);
500		// update_dacia_irq();
	499	if (LOG_DACIA) logerror("DACIA Compare mode: %02x \n", data);
	500	// update_dacia_irq();
501	501	}
502	502	else
503	503	{
504		if (LOG_DACIA) logerror("DACIA Aux ctrl: %02x \n", data);
	504	if (LOG_DACIA) logerror("DACIA Aux ctrl: %02x \n", data);
505	505	}
506	506	}
507	507	case 3: /* Transmit Data Register 1 */
r32760	r32761
869	869
870	870	/* sound hardware */
871	871	MCFG_SPEAKER_STANDARD_MONO("mono")
872
	872
873	873	/* TODO: Verify clock */
874	874	MCFG_SOUND_ADD("snsnd", SN76489, MAIN_CLOCK/2)
875	875	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
r32760	r32761
908	908	ROM_END
909	909
910	910
911		GAMEL( 1994, cops, 0, cops, cops, cops_state, cops, ROT0, "Atari Games", "Cops (USA)", GAME_NOT_WORKING \| GAME_NO_SOUND, layout_cops )
912		GAMEL( 1994, copsuk, cops,cops, cops, cops_state, cops, ROT0, "Nova Productions / Deith Leisure","Cops (UK)", GAME_NOT_WORKING \| GAME_NO_SOUND, layout_cops )
913		GAMEL( 1994, revlatns, 0, cops, revlatns, cops_state, cops, ROT0, "Nova Productions", "Revelations", GAME_NOT_WORKING \| GAME_NO_SOUND, layout_cops )
	911	GAMEL( 1994, cops, 0, cops, cops, cops_state, cops, ROT0, "Atari Games", "Cops (USA)", GAME_NOT_WORKING \| GAME_NO_SOUND, layout_cops )
	912	GAMEL( 1994, copsuk, cops,cops, cops, cops_state, cops, ROT0, "Nova Productions / Deith Leisure","Cops (UK)", GAME_NOT_WORKING \| GAME_NO_SOUND, layout_cops )
	913	GAMEL( 1994, revlatns, 0, cops, revlatns, cops_state, cops, ROT0, "Nova Productions", "Revelations", GAME_NOT_WORKING \| GAME_NO_SOUND, layout_cops )

trunk/src/mame/drivers/namcos21.c
r32760	r32761
490	490	void namcos21_kickstart(running_machine &machine, int internal)
491	491	{
492	492	namcos21_state *state = machine.driver_data<namcos21_state>();
493
	493
494	494	/* patch dsp watchdog */
495	495	switch( state->m_gametype )
496	496	{

trunk/src/mame/drivers/foodf.c
r32760	r32761
411	411
412	412	ROM_REGION( 0x100, "proms", 0 )
413	413	ROM_LOAD( "136020-112.2p", 0x000000, 0x000100, CRC(0aa962d6) SHA1(efb51e4c95efb1b85206c416c1d6d35c6f4ff35c) )
414
	414
415	415	ROM_REGION( 0x100, "nvram", 0 ) // default initialized nvram
416	416	ROM_LOAD( "foodf.nv", 0x000000, 0x000100, CRC(a4186b13) SHA1(7633ceb6f61403a46e36cc2172839e6c3f31bac2) )
417	417	ROM_END
r32760	r32761
437	437
438	438	ROM_REGION( 0x100, "proms", 0 )
439	439	ROM_LOAD( "136020-112.2p", 0x000000, 0x000100, CRC(0aa962d6) SHA1(efb51e4c95efb1b85206c416c1d6d35c6f4ff35c) )
440
	440
441	441	ROM_REGION( 0x100, "nvram", 0 ) // default initialized nvram
442	442	ROM_LOAD( "foodf.nv", 0x000000, 0x000100, CRC(a4186b13) SHA1(7633ceb6f61403a46e36cc2172839e6c3f31bac2) )
443	443	ROM_END
r32760	r32761
463	463
464	464	ROM_REGION( 0x100, "proms", 0 )
465	465	ROM_LOAD( "136020-112.2p", 0x000000, 0x000100, CRC(0aa962d6) SHA1(efb51e4c95efb1b85206c416c1d6d35c6f4ff35c) )
466
	466
467	467	ROM_REGION( 0x100, "nvram", 0 ) // default initialized nvram
468	468	ROM_LOAD( "foodf.nv", 0x000000, 0x000100, CRC(a4186b13) SHA1(7633ceb6f61403a46e36cc2172839e6c3f31bac2) )
469	469	ROM_END
r32760	r32761
489	489
490	490	ROM_REGION( 0x100, "proms", 0 )
491	491	ROM_LOAD( "136020-112.2p", 0x000000, 0x000100, CRC(0aa962d6) SHA1(efb51e4c95efb1b85206c416c1d6d35c6f4ff35c) )
492
	492
493	493	ROM_REGION( 0x100, "nvram", 0 ) // default initialized nvram, differs from the other sets
494	494	ROM_LOAD( "foodfc.nv", 0x000000, 0x000100, CRC(c1385dab) SHA1(52f4dc772e5da0f7c9bcef6c6ef3a655dcd3d59d) )
495	495	ROM_END

trunk/src/mame/drivers/4enraya.c
r32760	r32761
65	65	***************************************************************************
66	66
67	67	Unknown Pac-Man gambling game.
68
	68
69	69	It's a basic Pac-Man front game, that has a gambling game hidden inside.
70	70	The purpose of this "stealth" game, is just to be a "camouflage" for the
71	71	real gambling game, for locations where the gambling games are forbidden.
r32760	r32761
89	89	discard and press START to eliminate the number and place the representative
90	90	ghost again in the original place outside the center.
91	91
92		Once done, just press UP (deal) again, and pacman will re-eat the new placed
	92	Once done, just press UP (deal) again, and pacman will re-eat the new placed
93	93	ghosts, revealing the new numbers (as a new deal).
94	94
95	95	If you have a winning hand, you can press DOWN (double-up) to get a Double-Up,
r32760	r32761
241	241	AM_RANGE(0x00, 0x00) AM_READ_PORT("DSW1")
242	242	AM_RANGE(0x01, 0x01) AM_READ_PORT("IN1")
243	243	AM_RANGE(0x02, 0x02) AM_READ_PORT("IN2")
244		// AM_RANGE(0x03, 0x03) AM_WRITE("out_w") // to investigate...
	244	// AM_RANGE(0x03, 0x03) AM_WRITE("out_w") // to investigate...
245	245	AM_RANGE(0x17, 0x17) AM_DEVWRITE("aysnd", ay8910_device, data_w)
246	246	AM_RANGE(0x27, 0x27) AM_DEVREAD("aysnd", ay8910_device, data_r)
247	247	AM_RANGE(0x37, 0x37) AM_DEVWRITE("aysnd", ay8910_device, address_w)
r32760	r32761
300	300
301	301	static INPUT_PORTS_START( unkpacg )
302	302	PORT_START("IN1")
303		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_NAME("Front Game Coin A") // 1 credits / initiate minigame
304		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN3 ) PORT_NAME("Gambling Game Coin In") // 5 credits / initiate gambling
305		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_NAME("Front Game Coin B") // 10 credits
	303	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_NAME("Front Game Coin A") // 1 credits / initiate minigame
	304	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN3 ) PORT_NAME("Gambling Game Coin In") // 5 credits / initiate gambling
	305	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_NAME("Front Game Coin B") // 10 credits
306	306	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
307	307	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
308	308	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
r32760	r32761
459	459	MCFG_NVRAM_ADD_0FILL("nvram")
460	460
461	461	/* sound hardware */
462		// MCFG_SPEAKER_STANDARD_MONO("mono")
	462	// MCFG_SPEAKER_STANDARD_MONO("mono")
463	463	MCFG_SOUND_REPLACE("aysnd", AY8910, MAIN_CLOCK/4) /* guess */
464	464	MCFG_AY8910_PORT_A_READ_CB(IOPORT("DSW2"))
465	465	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)

trunk/src/mame/drivers/fcrash.c
r32760	r32761
2532	2532	mem16[0x64E/2] = 0x6046; // fix priorities
2533	2533
2534	2534	DRIVER_INIT_CALL(dinopic);
2535
	2535
2536	2536	}
2537	2537
2538	2538
r32760	r32761
2664	2664	ROM_LOAD16_BYTE( "27040.5", 0x000001, 0x80000, CRC(137d5f2e) SHA1(835e9b767e6499f161c5c4fd9a31a9f54b3ee68f) )
2665	2665	ROM_LOAD16_BYTE( "27010.4", 0x100000, 0x20000, CRC(8226c11c) SHA1(9588bd64e338901394805aca8a234f880674dc60) )
2666	2666	ROM_LOAD16_BYTE( "27010.3", 0x100001, 0x20000, CRC(924c6ce2) SHA1(676a912652bd75da5087f0c7eae047b7681a993c) )
2667
2668	2667
	2668
2669	2669	ROM_REGION( 0x600000, "gfx", 0 )
2670	2670	ROMX_LOAD( "tat-01.bin", 0x000000, 0x40000, CRC(a887f7d4) SHA1(d7e0c46b3ab1c6352f45033cb9e610d9c34d51fb), ROM_SKIP(7) )
2671	2671	ROM_CONTINUE( 0x000004, 0x40000)
r32760	r32761
2675	2675	ROM_CONTINUE( 0x000006, 0x40000)
2676	2676	ROMX_LOAD( "tat-06.bin", 0x000003, 0x40000, CRC(90f2053e) SHA1(a78710421e702b410650c45c3dec21bf16799fb4), ROM_SKIP(7) )
2677	2677	ROM_CONTINUE( 0x000007, 0x40000)
2678
	2678
2679	2679	ROMX_LOAD( "tat-03.bin", 0x200000, 0x40000, CRC(79fa8bf0) SHA1(9f8f7b8dc54a75226beb017b9ca9fd62a9e42f6b), ROM_SKIP(7) )
2680	2680	ROM_CONTINUE( 0x200004, 0x40000)
2681	2681	ROMX_LOAD( "tat-07.bin", 0x200001, 0x40000, CRC(6a5f153c) SHA1(f3d82ad01e2e4bdb2039815747fa14399c69753a), ROM_SKIP(7) )
r32760	r32761
2693	2693	ROM_CONTINUE( 0x400006, 0x40000)
2694	2694	ROMX_LOAD( "tat-12.bin", 0x400003, 0x40000, CRC(6ee19b94) SHA1(c45119d04879b6ca23a3f7749175c56b381b43f2), ROM_SKIP(7) )
2695	2695	ROM_CONTINUE( 0x400007, 0x40000)
2696
	2696
2697	2697	ROM_REGION( 0x18000, "audiocpu", 0 ) /* 64k for the audio CPU (+banks) */
2698	2698	ROM_LOAD( "27512.1", 0x00000, 0x08000, CRC(08f6b60e) SHA1(8258fcaca4ac419312531eec67079b97f471179c) )
2699	2699	ROM_CONTINUE( 0x10000, 0x08000 )
2700	2700
2701	2701	ROM_REGION( 0x40000, "oki", 0 ) /* Samples */
2702	2702	ROM_LOAD( "27020.2", 0x00000, 0x40000, CRC(6cfffb11) SHA1(995526183ffd35f92e9096500a3fe6237faaa2dd) )
2703
	2703
2704	2704	ROM_REGION( 0x00c8d, "pld", 0 ) /* pal/gal */
2705	2705	ROM_LOAD( "gal20v8.68kadd", 0x00000, 0x00c8d, CRC(27cdd376) SHA1(9fb5844b33002bec80fb92d3e5d1bbc779087300) )//68k address decoder
2706
	2706
2707	2707	ROM_END
2708	2708
2709	2709	DRIVER_INIT_MEMBER(cps_state, sf2mdt)

trunk/src/mame/drivers/redclash.c
r32760	r32761
470	470	ROM_LOAD( "zhi.c7", 0x0800, 0x0800, CRC(dcfefb4c) SHA1(9d8f57f5f09368225bae06a64971b82a848b1a7e) )
471	471	ROM_LOAD( "zhi.c6", 0x1000, 0x0800, CRC(ddc66d36) SHA1(1cbf6e27e7b2ccd39199c1a26783d53d6d90d195) )
472	472	ROM_LOAD( "zhi.c5", 0x1800, 0x0800, CRC(25c5872d) SHA1(df008db607b72a92c4284d6a8127eafec2432ca4) ) // == ze4_4.c5
473		// ROM_LOAD( "zhi.c4", 0x2000, 0x0800, CRC(9b70464b) SHA1(ccd173e12630ba044fe659915dfce21f2b5e0e39) ) // corrupt
	473	// ROM_LOAD( "zhi.c4", 0x2000, 0x0800, CRC(9b70464b) SHA1(ccd173e12630ba044fe659915dfce21f2b5e0e39) ) // corrupt
474	474	ROM_LOAD( "zhi.c4", 0x2000, 0x0800, CRC(d7ce3add) SHA1(d8dd7ad98e7a0a4f35de181549b2e88a9e0a73d6) ) // use rom from above sets instead
475	475	ROM_LOAD( "zhi.c3", 0x2800, 0x0800, CRC(29dee5e4) SHA1(13c1778d427a11f5c24ce8116fe55d60e98e3d83) )
476	476

trunk/src/mame/drivers/speglsht.c
r32760	r32761
344	344	VIDEO_START_MEMBER(speglsht_state,speglsht)
345	345	{
346	346	m_bitmap = auto_bitmap_ind16_alloc(machine(), 512, 5122 );
347		// VIDEO_START_CALL_MEMBER(st0016);
	347	// VIDEO_START_CALL_MEMBER(st0016);
348	348	}
349	349
350	350	#define PLOT_PIXEL_RGB(x,y,r,g,b) if(y>=0 && x>=0 && x<512 && y<512) \

trunk/src/mame/drivers/centiped.c
r32760	r32761
1876	1876	*************************************/
1877	1877
1878	1878	/*
1879		Alt. part numbers for mask ROMs:
	1879	Alt. part numbers for mask ROMs:
1880	1880
1881		136001-03 = 136001-07
1882		136001-04 = 136001-08
1883		136001-05 = 136001-09
1884		136001-06 = 136001-10
1885		136001-01 = 136001-11
1886		136001-02 = 136001-12
	1881	136001-03 = 136001-07
	1882	136001-04 = 136001-08
	1883	136001-05 = 136001-09
	1884	136001-06 = 136001-10
	1885	136001-01 = 136001-11
	1886	136001-02 = 136001-12
1887	1887	*/
1888	1888
1889	1889	ROM_START( centiped )

trunk/src/mame/drivers/igs017.c
r32760	r32761
720	720
721	721	void igs017_state::mgcs_patch_rom()
722	722	{
723		// UINT16 rom = (UINT16 )memregion("maincpu")->base();
	723	// UINT16 rom = (UINT16 )memregion("maincpu")->base();
724	724
725		// rom[0x20666/2] = 0x601e; // 020666: 671E beq $20686 (rom check)
	725	// rom[0x20666/2] = 0x601e; // 020666: 671E beq $20686 (rom check)
726	726
727	727	// IGS029 send command
728		// rom[0x4dfce/2] = 0x6010; // 04DFCE: 6610 bne $4dfe0
729		// rom[0x4e00e/2] = 0x4e75;
730		// rom[0x4e036/2] = 0x6006; // 04E036: 6306 bls $4e03e
	728	// rom[0x4dfce/2] = 0x6010; // 04DFCE: 6610 bne $4dfe0
	729	// rom[0x4e00e/2] = 0x4e75;
	730	// rom[0x4e036/2] = 0x6006; // 04E036: 6306 bls $4e03e
731	731	}
732	732
733	733	DRIVER_INIT_MEMBER(igs017_state,mgcs)
r32760	r32761
1457	1457	coin_counter_w(machine(), 0, (~data) & 0x20); // coin in
1458	1458	coin_counter_w(machine(), 1, (~data) & 0x40); // coin out
1459	1459
1460		// popmessage("PORT1 %02X", data);
	1460	// popmessage("PORT1 %02X", data);
1461	1461
1462	1462	if ( data & ~0x70 )
1463	1463	logerror("%s: warning, unknown bits written in port %02x = %02x\n", machine().describe_context(), port, data);
r32760	r32761
1467	1467	case 0x03:
1468	1468	m_dsw_select = data;
1469	1469
1470		// popmessage("PORT3 %02X", data);
	1470	// popmessage("PORT3 %02X", data);
1471	1471
1472	1472	if ( data & ~0x03 )
1473	1473	logerror("%s: warning, unknown bits written in port %02x = %02x\n", machine().describe_context(), port, data);
r32760	r32761
1501	1501	logerror("READ DSW\n");
1502	1502
1503	1503	UINT8 ret;
1504		if (~m_dsw_select & 0x01) ret = ioport("DSW1")->read();
1505		else if (~m_dsw_select & 0x02) ret = ioport("DSW2")->read();
	1504	if (~m_dsw_select & 0x01) ret = ioport("DSW1")->read();
	1505	else if (~m_dsw_select & 0x02) ret = ioport("DSW2")->read();
1506	1506	else
1507	1507	{
1508	1508	logerror("%s: warning, reading dsw with dsw_select = %02x\n", machine().describe_context(), m_dsw_select);
r32760	r32761
1515	1515	}
1516	1516	else if (m_igs029_send_buf[0] == 0x07 && m_igs029_send_buf[1] == 0x2c)
1517	1517	{
1518		logerror("?? (2C)\n"); // ??
	1518	logerror("?? (2C)\n"); // ??
1519	1519
1520	1520	// 4 inputs. Returns 1 long
1521	1521
r32760	r32761
1525	1525	m_igs029_recv_buf[m_igs029_recv_len++] = 0x00;
1526	1526	m_igs029_recv_buf[m_igs029_recv_len++] = 0x00;
1527	1527	m_igs029_recv_buf[m_igs029_recv_len++] = 0x00;
1528		m_igs029_recv_buf[m_igs029_recv_len++] = 0x01; // ??
	1528	m_igs029_recv_buf[m_igs029_recv_len++] = 0x01; // ??
1529	1529	m_igs029_recv_buf[m_igs029_recv_len++] = 0x05;
1530	1530	}
1531	1531	else if (m_igs029_send_buf[0] == 0x07 && m_igs029_send_buf[1] == 0x15)
r32760	r32761
1571	1571	case 0x00:
1572	1572	if (ACCESSING_BITS_0_7)
1573	1573	{
1574		bool igs029_irq = !(m_input_select & 0x04) && (data & 0x04); // 0->1
	1574	bool igs029_irq = !(m_input_select & 0x04) && (data & 0x04); // 0->1
1575	1575
1576	1576	// 7654 3--- Keys
1577	1577	// ---- -2-- IRQ on IGS029
r32760	r32761
1623	1623	if (ACCESSING_BITS_0_7)
1624	1624	{
1625	1625	m_scramble_data = data & 0xff;
1626		// logerror("%s: writing %02x to igs_magic = %02x\n", machine().describe_context(), data & 0xff, m_igs_magic[0]);
	1626	// logerror("%s: writing %02x to igs_magic = %02x\n", machine().describe_context(), data & 0xff, m_igs_magic[0]);
1627	1627	}
1628	1628	break;
1629	1629
r32760	r32761
1633	1633	if (ACCESSING_BITS_0_7)
1634	1634	{
1635	1635	m_igs029_send_data = data & 0xff;
1636		// logerror("%s: writing %02x to igs_magic = %02x\n", machine().describe_context(), data & 0xff, m_igs_magic[0]);
	1636	// logerror("%s: writing %02x to igs_magic = %02x\n", machine().describe_context(), data & 0xff, m_igs_magic[0]);
1637	1637	}
1638	1638	break;
1639	1639
r32760	r32761
1666	1666	return ret;
1667	1667	}
1668	1668
1669		// case 0x05: ???
	1669	// case 0x05: ???
1670	1670
1671	1671	default:
1672	1672	logerror("%s: warning, reading with igs_magic = %02x\n", machine().describe_context(), m_igs_magic[0]);
r32760	r32761
2947	2947
2948	2948	// DSWs are read through a protection device (IGS029). See code at 1CF16
2949	2949
2950		PORT_START("DSW1") // $3009e2
	2950	PORT_START("DSW1") // $3009e2
2951	2951	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coinage ) )
2952	2952	PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
2953	2953	PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
r32760	r32761
2971	2971	PORT_DIPSETTING( 0x80, "1000" )
2972	2972	PORT_DIPSETTING( 0x00, "2000" )
2973	2973
2974		PORT_START("DSW2") // $3009e3
	2974	PORT_START("DSW2") // $3009e3
2975	2975	PORT_DIPNAME( 0x03, 0x03, "Min Bet" )
2976	2976	PORT_DIPSETTING( 0x03, "1" )
2977	2977	PORT_DIPSETTING( 0x02, "2" )

trunk/src/mame/drivers/dlair2.c
r32760	r32761
268	268
269	269	ROM_REGION( 0x2000, "bios", 0 ) /* BIOS for proto board */
270	270	ROM_LOAD( "dl2_amoa_proto_bios_mod_56ee.bin",0x00000, 0x2000, CRC(1fc21576) SHA1(dc5443f6a8d80ec8148314244f05ac0290e380ea) )
271
	271
272	272	ROM_END
273	273
274	274	ROM_START( spacea91 )

trunk/src/mame/drivers/speedbal.c
r32760	r32761
351	351	DRIVER_INIT_MEMBER(speedbal_state,musicbal)
352	352	{
353	353	UINT8* rom = memregion("maincpu")->base();
354
355		const UINT8 xorTable[8] = {0x05, 0x06, 0x84, 0x84, 0x00, 0x87, 0x84, 0x84}; // XORs affecting bits #0, #1, #2 & #7
356		const int swapTable[4][4] = { // 4 possible swaps affecting bits #0, #1, #2 & #7
357		{1,0,7,2},
358		{2,7,0,1},
359		{7,2,1,0},
360		{0,2,1,7}
361		};
362
	354
	355	const UINT8 xorTable[8] = {0x05, 0x06, 0x84, 0x84, 0x00, 0x87, 0x84, 0x84}; // XORs affecting bits #0, #1, #2 & #7
	356	const int swapTable[4][4] = { // 4 possible swaps affecting bits #0, #1, #2 & #7
	357	{1,0,7,2},
	358	{2,7,0,1},
	359	{7,2,1,0},
	360	{0,2,1,7}
	361	};
	362
363	363	for (int i=0;i<0x8000;i++)
364	364	{
365		int addIdx = BIT(i,3)^(BIT(i,5)<<1)^(BIT(i,9)<<2); // 3 bits of address...
366		int xorMask = xorTable[addIdx]; // ... control the xor...
367		int bswIdx = xorMask & 3; // ... and the bitswap
	365	int addIdx = BIT(i,3)^(BIT(i,5)<<1)^(BIT(i,9)<<2); // 3 bits of address...
	366	int xorMask = xorTable[addIdx]; // ... control the xor...
	367	int bswIdx = xorMask & 3; // ... and the bitswap
368	368
369		// only bits #0, #1, #2 & #7 are affected
370		rom[i] = BITSWAP8(rom[i], swapTable[bswIdx][3], 6,5,4,3, swapTable[bswIdx][2], swapTable[bswIdx][1], swapTable[bswIdx][0]) ^ xorTable[addIdx];
371		}
	369	// only bits #0, #1, #2 & #7 are affected
	370	rom[i] = BITSWAP8(rom[i], swapTable[bswIdx][3], 6,5,4,3, swapTable[bswIdx][2], swapTable[bswIdx][1], swapTable[bswIdx][0]) ^ xorTable[addIdx];
	371	}
372	372
373	373	DRIVER_INIT_CALL(speedbal);
374	374	}

trunk/src/mame/drivers/btoads.c
r32760	r32761
304	304	MCFG_CPU_PROGRAM_MAP(main_map)
305	305	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
306	306	MCFG_TMS340X0_PIXEL_CLOCK(VIDEO_CLOCK/2) /* pixel clock */
307		MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
	307	MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
308	308	MCFG_TMS340X0_SCANLINE_RGB32_CB(btoads_state, scanline_update) /* scanline updater (RGB32) */
309	309	MCFG_TMS340X0_TO_SHIFTREG_CB(btoads_state, to_shiftreg) /* write to shiftreg function */
310	310	MCFG_TMS340X0_FROM_SHIFTREG_CB(btoads_state, from_shiftreg) /* read from shiftreg function */

trunk/src/mame/drivers/megatech.c
r32760	r32761
131	131	DECLARE_DEVICE_IMAGE_LOAD_MEMBER( mt_cart6 ) { return load_cart(image, m_cart6, 5); }
132	132	DECLARE_DEVICE_IMAGE_LOAD_MEMBER( mt_cart7 ) { return load_cart(image, m_cart7, 6); }
133	133	DECLARE_DEVICE_IMAGE_LOAD_MEMBER( mt_cart8 ) { return load_cart(image, m_cart8, 7); }
134
	134
135	135	UINT32 screen_update_main(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
136	136	UINT32 screen_update_menu(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
137	137	void screen_eof_main(screen_device &screen, bool state);
r32760	r32761
424	424	if (m_cart_reg[gameno])
425	425	{
426	426	memcpy(memregion("maincpu")->base(), m_cart_reg[gameno]->base(), 0x400000);
427
	427
428	428	if (!m_cart_is_genesis[gameno])
429	429	{
430	430	logerror("enabling SMS Z80\n");
r32760	r32761
442	442	//m_maincpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
443	443	}
444	444	}
445		else /* else, no cart.. */
	445	else /* else, no cart.. */
446	446	{
447	447	memset(memregion("mtbios")->base() + 0x8000, 0x00, 0x8000);
448	448	memset(memregion("maincpu")->base(), 0x00, 0x400000);
r32760	r32761
594	594	m_banked_ram = auto_alloc_array(machine(), UINT8, 0x1000*8);
595	595
596	596	DRIVER_INIT_CALL(megadriv);
597
	597
598	598	// this gets set in DEVICE_IMAGE_LOAD
599	599	memset(m_cart_is_genesis, 0, sizeof(m_cart_is_genesis));
600	600	}
r32760	r32761
641	641	{
642	642	m_mt_bank_addr = 0;
643	643	MACHINE_RESET_CALL_MEMBER(megadriv);
644
	644
645	645	astring region_tag;
646	646	if (m_cart1)
647	647	m_cart_reg[0] = memregion(region_tag.cpy(m_cart1->tag()).cat(GENERIC_ROM_REGION_TAG));
r32760	r32761
730	730	UINT8 *ROM;
731	731	const char *pcb_name;
732	732	UINT32 size = slot->common_get_size("rom");
733
	733
734	734	if (image.software_entry() == NULL)
735	735	return IMAGE_INIT_FAIL;
736
	736
737	737	slot->rom_alloc(size, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
738	738	ROM = slot->get_rom_base();
739	739	memcpy(ROM, image.get_software_region("rom"), size);
r32760	r32761
753	753	m_cart_is_genesis[gameno] = 0;
754	754	}
755	755	else
756		osd_printf_debug("cart%d is invalid\n", gameno + 1);
	756	osd_printf_debug("cart%d is invalid\n", gameno + 1);
757	757	}
758
	758
759	759	return IMAGE_INIT_PASS;
760	760	}
761	761

trunk/src/mame/drivers/vamphalf.c
r32760	r32761
383	383	}
384	384	READ32_MEMBER(vamphalf_state::yorizori_1c_r)
385	385	{
386		// printf("yorizori_1c_r %08x\n", space.device().safe_pc());
	386	// printf("yorizori_1c_r %08x\n", space.device().safe_pc());
387	387	return 0x00;// 0xaa;
388	388	}
389	389	WRITE32_MEMBER(vamphalf_state::yorizori_1c_w)
390	390	{
391		// printf("yorizori_1c_w %08x %08x\n", space.device().safe_pc(), data);
	391	// printf("yorizori_1c_w %08x %08x\n", space.device().safe_pc(), data);
392	392	}
393	393
394	394	WRITE32_MEMBER( vamphalf_state::wyvernwg_snd_w )
r32760	r32761
2078	2078	ROM_START( yorizori )
2079	2079	ROM_REGION32_BE( 0x200000, "user1", ROMREGION_ERASE00 ) /* Hyperstone CPU Code */
2080	2080	ROM_LOAD( "prg1", 0x000000, 0x200000, CRC(0e04eb40) SHA1(0cec9dc91aaf9cf7c459c7baac200cf0fcfddc18) )
2081
	2081
2082	2082	ROM_REGION( 0x080000, "qs1000:cpu", 0 ) /* QDSP (8052) Code */
2083	2083	ROM_LOAD( "snd5", 0x00000, 0x20000, CRC(79067367) SHA1(a8f0c02dd616ff8c5fb49dea1a116fea2aced19c) )
2084	2084	ROM_RELOAD( 0x20000, 0x20000 )

trunk/src/mame/drivers/snesb.c
r32760	r32761
638	638	static INPUT_PORTS_START( endless )
639	639	PORT_INCLUDE(snes_common)
640	640
641		PORT_START("DSW1")
642		PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coinage ) )
643		PORT_DIPSETTING( 0x01, DEF_STR( 4C_1C ) )
644		PORT_DIPSETTING( 0x02, DEF_STR( 3C_1C ) )
645		PORT_DIPSETTING( 0x03, DEF_STR( 2C_1C ) )
646		PORT_DIPSETTING( 0x07, DEF_STR( 1C_1C ) )
	641	PORT_START("DSW1")
	642	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coinage ) )
	643	PORT_DIPSETTING( 0x01, DEF_STR( 4C_1C ) )
	644	PORT_DIPSETTING( 0x02, DEF_STR( 3C_1C ) )
	645	PORT_DIPSETTING( 0x03, DEF_STR( 2C_1C ) )
	646	PORT_DIPSETTING( 0x07, DEF_STR( 1C_1C ) )
647	647	// PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) ) /* duplicate setting */
648		PORT_DIPSETTING( 0x06, DEF_STR( 1C_2C ) )
649		PORT_DIPSETTING( 0x05, DEF_STR( 1C_3C ) )
650		PORT_DIPSETTING( 0x04, DEF_STR( 1C_4C ) )
651		PORT_DIPNAME( 0x38, 0x38, DEF_STR( Difficulty ) ) /* "LEVEL" */
652		PORT_DIPSETTING( 0x38, "0 (Easiest)" ) /* "EASY" */
653		PORT_DIPSETTING( 0x30, "1" ) /* "NORMAL" */
654		PORT_DIPSETTING( 0x28, "2" ) /* "HARD" */
655		PORT_DIPSETTING( 0x20, "3" ) /* undefined */
656		PORT_DIPSETTING( 0x18, "4" ) /* undefined */
657		PORT_DIPSETTING( 0x10, "5" ) /* undefined */
658		PORT_DIPSETTING( 0x08, "6" ) /* undefined */
659		PORT_DIPSETTING( 0x00, "7 (Hardest)" ) /* undefined */
660		PORT_DIPNAME( 0xc0, 0xc0, "Time" ) /* "TIME" */
661		PORT_DIPSETTING( 0xc0, "99" ) /* "LIMIT" */
662		PORT_DIPSETTING( 0x80, "60" ) /* undefined */
663		PORT_DIPSETTING( 0x40, "30" ) /* undefined */
664		PORT_DIPSETTING( 0x00, "Infinite" ) /* "NO LIMIT" */
	648	PORT_DIPSETTING( 0x06, DEF_STR( 1C_2C ) )
	649	PORT_DIPSETTING( 0x05, DEF_STR( 1C_3C ) )
	650	PORT_DIPSETTING( 0x04, DEF_STR( 1C_4C ) )
	651	PORT_DIPNAME( 0x38, 0x38, DEF_STR( Difficulty ) ) /* "LEVEL" */
	652	PORT_DIPSETTING( 0x38, "0 (Easiest)" ) /* "EASY" */
	653	PORT_DIPSETTING( 0x30, "1" ) /* "NORMAL" */
	654	PORT_DIPSETTING( 0x28, "2" ) /* "HARD" */
	655	PORT_DIPSETTING( 0x20, "3" ) /* undefined */
	656	PORT_DIPSETTING( 0x18, "4" ) /* undefined */
	657	PORT_DIPSETTING( 0x10, "5" ) /* undefined */
	658	PORT_DIPSETTING( 0x08, "6" ) /* undefined */
	659	PORT_DIPSETTING( 0x00, "7 (Hardest)" ) /* undefined */
	660	PORT_DIPNAME( 0xc0, 0xc0, "Time" ) /* "TIME" */
	661	PORT_DIPSETTING( 0xc0, "99" ) /* "LIMIT" */
	662	PORT_DIPSETTING( 0x80, "60" ) /* undefined */
	663	PORT_DIPSETTING( 0x40, "30" ) /* undefined */
	664	PORT_DIPSETTING( 0x00, "Infinite" ) /* "NO LIMIT" */
665	665
666		PORT_START("DSW2")
667		PORT_DIPUNUSED( 0x01, IP_ACTIVE_LOW )
668		PORT_DIPUNUSED( 0x02, IP_ACTIVE_LOW )
669		PORT_DIPUNUSED( 0x04, IP_ACTIVE_LOW )
670		PORT_DIPUNUSED( 0x08, IP_ACTIVE_LOW )
671		PORT_DIPUNUSED( 0x10, IP_ACTIVE_LOW )
672		PORT_DIPUNUSED( 0x20, IP_ACTIVE_LOW )
673		PORT_DIPUNUSED( 0x40, IP_ACTIVE_LOW )
674		PORT_DIPUNUSED( 0x80, IP_ACTIVE_LOW )
	666	PORT_START("DSW2")
	667	PORT_DIPUNUSED( 0x01, IP_ACTIVE_LOW )
	668	PORT_DIPUNUSED( 0x02, IP_ACTIVE_LOW )
	669	PORT_DIPUNUSED( 0x04, IP_ACTIVE_LOW )
	670	PORT_DIPUNUSED( 0x08, IP_ACTIVE_LOW )
	671	PORT_DIPUNUSED( 0x10, IP_ACTIVE_LOW )
	672	PORT_DIPUNUSED( 0x20, IP_ACTIVE_LOW )
	673	PORT_DIPUNUSED( 0x40, IP_ACTIVE_LOW )
	674	PORT_DIPUNUSED( 0x80, IP_ACTIVE_LOW )
675	675
676	676	PORT_START("COIN")
677	677	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )

trunk/src/mame/drivers/battlera.c
r32760	r32761
72	72	AM_RANGE( 0x1FE400, 0x1FE7FF) AM_DEVREADWRITE( "huc6260", huc6260_device, read, write )
73	73	AM_RANGE( 0x1FEC00, 0x1FEFFF) AM_DEVREADWRITE( "maincpu", h6280_device, timer_r, timer_w )
74	74	AM_RANGE( 0x1FF400, 0x1FF7FF) AM_DEVREADWRITE( "maincpu", h6280_device, irq_status_r, irq_status_w )
75
	75
76	76	ADDRESS_MAP_END
77	77
78	78	static ADDRESS_MAP_START( battlera_portmap, AS_IO, 8, battlera_state )

trunk/src/mame/drivers/atarisy4.c
r32760	r32761
33	33	public:
34	34	atarisy4_renderer(atarisy4_state &state, screen_device &screen);
35	35	~atarisy4_renderer() {}
36
	36
37	37	void draw_scanline(INT32 scanline, const extent_t &extent, const atarisy4_polydata &extradata, int threadid);
38	38	void draw_polygon(UINT16 color);
39
	39
40	40	atarisy4_state &m_state;
41	41	};
42	42
r32760	r32761
54	54	m_screen_ram(*this, "screen_ram"),
55	55	m_dsp0_bank1(*this, "dsp0_bank1"),
56	56	m_dsp1_bank1(*this, "dsp1_bank1") { }
57
	57
58	58	required_device<cpu_device> m_maincpu;
59	59	required_device<cpu_device> m_dsp0;
60	60	optional_device<cpu_device> m_dsp1;
61	61	required_device<palette_device> m_palette;
62	62	required_device<screen_device> m_screen;
63
	63
64	64	required_shared_ptr<UINT16> m_m68k_ram;
65	65	required_shared_ptr<UINT16> m_screen_ram;
66
	66
67	67	required_memory_bank m_dsp0_bank1;
68	68	optional_memory_bank m_dsp1_bank1;
69	69
70	70	atarisy4_renderer *m_renderer;
71
	71
72	72	UINT8 m_r_color_table[256];
73	73	UINT8 m_g_color_table[256];
74	74	UINT8 m_b_color_table[256];
75	75	UINT16 m_dsp_bank[2];
76	76	UINT8 m_csr[2];
77	77	UINT16 *m_shared_ram[2];
78
	78
79	79	DECLARE_WRITE16_MEMBER(gpu_w);
80	80	DECLARE_READ16_MEMBER(gpu_r);
81	81	DECLARE_READ16_MEMBER(m68k_shared_0_r);
r32760	r32761
177	177	{
178	178	}
179	179
180		void atarisy4_state::video_start()
	180	void atarisy4_state::video_start()
181	181	{
182	182	m_renderer = auto_alloc(machine(), atarisy4_renderer(this, m_screen));
183	183	}

trunk/src/mame/drivers/metro.c
r32760	r32761
3465	3465
3466	3466	PORT_START("DSW0")
3467	3467	// DSW1, stored at 0xff0085.b (cpl'ed)
3468		PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:1,2,3")
	3468	PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:1,2,3")
3469	3469	PORT_DIPSETTING( 0x0005, DEF_STR( 3C_1C ) )
3470	3470	PORT_DIPSETTING( 0x0006, DEF_STR( 2C_1C ) )
3471	3471	PORT_DIPSETTING( 0x0007, DEF_STR( 1C_1C ) )
r32760	r32761
3475	3475	PORT_DIPSETTING( 0x0001, DEF_STR( 1C_5C ) )
3476	3476	PORT_DIPSETTING( 0x0000, DEF_STR( 1C_6C ) )
3477	3477	PORT_DIPUNUSED_DIPLOC( 0x0008, IP_ACTIVE_LOW, "SW1:4" ) /* 0x01 (OFF) or 0x02 (ON) written to 0xff0112.b but NEVER read back - old credits for 2 players game ? */
3478		PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:5") /* 0x07c1 written to 0x1788ac.w (screen control ?) at first (code at 0x0001b8) */
	3478	PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:5") /* 0x07c1 written to 0x1788ac.w (screen control ?) at first (code at 0x0001b8) */
3479	3479	PORT_DIPSETTING( 0x0010, DEF_STR( Off ) ) /* 0x07c1 written to 0xff0114.w (then 0x1788ac.w) during initialisation (code at 0x000436) */
3480	3480	PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) /* 0x07c0 written to 0xff0114.w (then 0x1788ac.w) during initialisation (code at 0x000436) */
3481		PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:6")
	3481	PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:6")
3482	3482	PORT_DIPSETTING( 0x0000, DEF_STR( Off ) )
3483	3483	PORT_DIPSETTING( 0x0020, DEF_STR( On ) )
3484	3484	PORT_DIPUNUSED_DIPLOC( 0x0040, IP_ACTIVE_LOW, "SW1:7" )
r32760	r32761
3486	3486
3487	3487	PORT_START("IN2")
3488	3488	// DSW2, stored at 0xff0084.b (cpl'ed)
3489		PORT_DIPNAME( 0x0003, 0x0003, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:1,2")
	3489	PORT_DIPNAME( 0x0003, 0x0003, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:1,2")
3490	3490	PORT_DIPSETTING( 0x0002, DEF_STR( Easy ) )
3491	3491	PORT_DIPSETTING( 0x0003, DEF_STR( Normal ) )
3492	3492	PORT_DIPSETTING( 0x0001, DEF_STR( Hard ) )
3493	3493	PORT_DIPSETTING( 0x0000, DEF_STR( Hardest ) )
3494		PORT_DIPNAME( 0x000c, 0x000c, DEF_STR( Lives ) ) PORT_DIPLOCATION("SW2:3,4")
	3494	PORT_DIPNAME( 0x000c, 0x000c, DEF_STR( Lives ) ) PORT_DIPLOCATION("SW2:3,4")
3495	3495	PORT_DIPSETTING( 0x0008, "1" )
3496	3496	PORT_DIPSETTING( 0x0004, "2" )
3497	3497	PORT_DIPSETTING( 0x000c, "3" )
3498	3498	PORT_DIPSETTING( 0x0000, "4" )
3499		PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("SW2:5") /* code at 0x0004a4 */
	3499	PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("SW2:5") /* code at 0x0004a4 */
3500	3500	PORT_DIPSETTING( 0x0010, "Every 30000" )
3501	3501	PORT_DIPSETTING( 0x0000, "Every 60000" )
3502	3502	PORT_DIPUNUSED_DIPLOC( 0x0020, IP_ACTIVE_LOW, "SW2:6" )

trunk/src/mame/drivers/midwunit.c
r32760	r32761
621	621	MCFG_CPU_PROGRAM_MAP(main_map)
622	622	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
623	623	MCFG_TMS340X0_PIXEL_CLOCK(PIXEL_CLOCK) /* pixel clock */
624		MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
	624	MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
625	625	MCFG_TMS340X0_SCANLINE_IND16_CB(midtunit_state, scanline_update) /* scanline updater (indexed16) */
626	626	MCFG_TMS340X0_TO_SHIFTREG_CB(midtunit_state, to_shiftreg) /* write to shiftreg function */
627	627	MCFG_TMS340X0_FROM_SHIFTREG_CB(midtunit_state, from_shiftreg) /* read from shiftreg function */

trunk/src/mame/drivers/legionna.c
r32760	r32761
106	106	AM_RANGE(0x100428, 0x100429) AM_DEVWRITE("raiden2cop", raiden2cop_device, cop_dma_v1_w)
107	107	AM_RANGE(0x10042a, 0x10042b) AM_DEVWRITE("raiden2cop", raiden2cop_device, cop_dma_v2_w)
108	108	AM_RANGE(0x10042c, 0x10042d) AM_DEVREADWRITE("raiden2cop", raiden2cop_device, cop_prng_maxvalue_r, cop_prng_maxvalue_w)
109
	109
110	110	AM_RANGE(0x100432, 0x100433) AM_DEVWRITE("raiden2cop", raiden2cop_device, cop_pgm_data_w)
111	111	AM_RANGE(0x100434, 0x100435) AM_DEVWRITE("raiden2cop", raiden2cop_device, cop_pgm_addr_w)
112	112	AM_RANGE(0x100436, 0x100437) AM_DEVWRITE("raiden2cop", raiden2cop_device, cop_hitbox_baseadr_w)
113	113	AM_RANGE(0x100438, 0x100439) AM_DEVWRITE("raiden2cop", raiden2cop_device, cop_pgm_value_w)
114	114	AM_RANGE(0x10043a, 0x10043b) AM_DEVWRITE("raiden2cop", raiden2cop_device, cop_pgm_mask_w)
115	115	AM_RANGE(0x10043c, 0x10043d) AM_DEVWRITE("raiden2cop", raiden2cop_device, cop_pgm_trigger_w)
116		//AM_RANGE(0x10043e, 0x10043f) AM_DEVWRITE("raiden2cop", raiden2cop_device,) /* 0 in all 68k based games, 0xffff in raiden2 / raidendx, 0x2000 in zeroteam / xsedae , it's always set up just before the 0x474 register */
	116	//AM_RANGE(0x10043e, 0x10043f) AM_DEVWRITE("raiden2cop", raiden2cop_device,) /* 0 in all 68k based games, 0xffff in raiden2 / raidendx, 0x2000 in zeroteam / xsedae , it's always set up just before the 0x474 register */
117	117
118	118	AM_RANGE(0x100444, 0x100445) AM_DEVWRITE("raiden2cop", raiden2cop_device, cop_scale_w)
119	119	AM_RANGE(0x100446, 0x100447) AM_DEVWRITE("raiden2cop", raiden2cop_device, cop_rom_addr_unk_w) // 68k
120	120	AM_RANGE(0x100448, 0x100449) AM_DEVWRITE("raiden2cop", raiden2cop_device, cop_rom_addr_lo_w) // 68k
121	121	AM_RANGE(0x10044a, 0x10044b) AM_DEVWRITE("raiden2cop", raiden2cop_device, cop_rom_addr_hi_w) // 68k
122
	122
123	123	AM_RANGE(0x100450, 0x100451) AM_DEVWRITE("raiden2cop", raiden2cop_device, cop_sort_ram_addr_hi_w)
124	124	AM_RANGE(0x100452, 0x100453) AM_DEVWRITE("raiden2cop", raiden2cop_device, cop_sort_ram_addr_lo_w)
125	125	AM_RANGE(0x100454, 0x100455) AM_DEVWRITE("raiden2cop", raiden2cop_device, cop_sort_lookup_hi_w)
r32760	r32761
128	128	AM_RANGE(0x10045a, 0x10045b) AM_DEVWRITE("raiden2cop", raiden2cop_device, cop_pal_brightness_val_w) //palette DMA brightness val, used by X Se Dae / Zero Team
129	129	AM_RANGE(0x10045c, 0x10045d) AM_DEVWRITE("raiden2cop", raiden2cop_device, cop_pal_brightness_mode_w) //palette DMA brightness mode, used by X Se Dae / Zero Team (sets to 5)
130	130
131		// AM_RANGE(0x100470, 0x100471) AM_READWRITE(cop_tile_bank_2_r,cop_tile_bank_2_w)
132		// AM_RANGE(0x100474, 0x100475) AM_DEVWRITE("raiden2cop", raiden2cop_device,) // this gets set to a pointer to spriteram (relative to start of ram) on all games excecpt raiden 2, where it isn't set
	131	// AM_RANGE(0x100470, 0x100471) AM_READWRITE(cop_tile_bank_2_r,cop_tile_bank_2_w)
	132	// AM_RANGE(0x100474, 0x100475) AM_DEVWRITE("raiden2cop", raiden2cop_device,) // this gets set to a pointer to spriteram (relative to start of ram) on all games excecpt raiden 2, where it isn't set
133	133	AM_RANGE(0x100476, 0x100477) AM_DEVWRITE("raiden2cop", raiden2cop_device, cop_dma_adr_rel_w)
134	134	AM_RANGE(0x100478, 0x100479) AM_DEVWRITE("raiden2cop", raiden2cop_device,cop_dma_src_w)
135	135	AM_RANGE(0x10047a, 0x10047b) AM_DEVWRITE("raiden2cop", raiden2cop_device,cop_dma_size_w)
r32760	r32761
142	142	AM_RANGE(0x1004a0, 0x1004ad) AM_DEVREADWRITE("raiden2cop", raiden2cop_device, cop_reg_high_r, cop_reg_high_w)
143	143	AM_RANGE(0x1004c0, 0x1004cd) AM_DEVREADWRITE("raiden2cop", raiden2cop_device, cop_reg_low_r, cop_reg_low_w)
144	144
145		// AM_RANGE(0x100500, 0x100505) AM_WRITE(cop_cmd_w) // ADD ME
	145	// AM_RANGE(0x100500, 0x100505) AM_WRITE(cop_cmd_w) // ADD ME
146	146	AM_RANGE(0x100500, 0x100505) AM_DEVWRITE("raiden2cop", raiden2cop_device,LEGACY_cop_cmd_w) // REMOVE ME
147	147
148	148	AM_RANGE(0x100580, 0x100581) AM_DEVREAD("raiden2cop", raiden2cop_device, cop_collision_status_r)
r32760	r32761
222	222	AM_RANGE(0x101800, 0x101fff) AM_RAM // _WRITE(legionna_foreground_w) AM_SHARE("fore_data")
223	223	AM_RANGE(0x102000, 0x1027ff) AM_RAM // _WRITE(legionna_midground_w) AM_SHARE("mid_data")
224	224	AM_RANGE(0x102800, 0x1037ff) AM_RAM // _WRITE(legionna_text_w) AM_SHARE("textram")
225		AM_RANGE(0x103800, 0x103fff) AM_RAM // check?
	225	AM_RANGE(0x103800, 0x103fff) AM_RAM // check?
226	226	AM_RANGE(0x104000, 0x104fff) AM_RAM // _DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
227	227	AM_RANGE(0x105000, 0x105fff) AM_RAM AM_SHARE("spriteram")
228	228	AM_RANGE(0x106000, 0x1067ff) AM_RAM

trunk/src/mame/drivers/aristmk4.c
r32760	r32761
1703	1703
1704	1704	MCFG_SOUND_ADD("samples", SAMPLES, 0)
1705	1705	MCFG_SAMPLES_CHANNELS(5) /* one for each meter - can pulse simultaneously */
1706		MCFG_SAMPLES_NAMES(meter_sample_names)
	1706	MCFG_SAMPLES_NAMES(meter_sample_names)
1707	1707	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.05)
1708	1708
1709	1709	MACHINE_CONFIG_END

trunk/src/mame/drivers/naomi.c
r32760	r32761
1783	1783	} else
1784	1784	if (reg == 0x284/4)
1785	1785	return U64(0xffffffffffffff00) \| aw_ctrl_type;
1786
1787	1786
	1787
1788	1788	osd_printf_verbose("MODEM: Unmapped read %08x\n", 0x600000+reg*4);
1789	1789	return 0;
1790	1790	}
r32760	r32761
1800	1800	if (reg == 0x284/4)
1801	1801	{
1802	1802	/*
1803		0x00600284 rw ddccbbaa
	1803	0x00600284 rw ddccbbaa
1804	1804	aa/bb/cc/dd - set type of Maple devices at ports 0/1/2/3
1805		0 - regular DC controller, but with 4 analogue channels (default)
1806		1 - DC lightgun
1807		2 - DC mouse/trackball
1808		TODO: hook this then MAME have such devices emulated
	1805	0 - regular DC controller, but with 4 analogue channels (default)
	1806	1 - DC lightgun
	1807	2 - DC mouse/trackball
	1808	TODO: hook this then MAME have such devices emulated
1809	1809	*/
1810	1810	aw_ctrl_type = dat & 0xFF;
1811	1811	}
r32760	r32761
4109	4109	NAOMI_DEFAULT_EEPROM
4110	4110
4111	4111	ROM_REGION( 0x7800000, "rom_board", ROMREGION_ERASEFF)
4112		ROM_LOAD( "epr-24286.ic22", 0x0000000, 0x0400000, CRC(9d26e2fc) SHA1(74bcd7daf994a5c97c836b6f060c73d31a9c06d8) )
4113		ROM_LOAD( "mpr-24276.ic1", 0x0800000, 0x1000000, CRC(35ac9283) SHA1(74af0e3f294fc76d44c8c6b54042186dec8b9f8a) )
4114		ROM_LOAD( "mpr-24277.ic2", 0x1800000, 0x1000000, CRC(16111394) SHA1(7ca20de07cfa3fa248b472819bc893f00689e3a1) )
4115		ROM_LOAD( "mpr-24278.ic3", 0x2800000, 0x1000000, CRC(bf0ec0bc) SHA1(7de72decf97999e74b510e9655a57ad6d1def1c8) )
4116		ROM_LOAD( "mpr-24279.ic4", 0x3800000, 0x1000000, CRC(f7d0ab5b) SHA1(10188a22a1918b18008973135ef2e00dd26dd6cb) )
4117		ROM_LOAD( "mpr-24280.ic5", 0x4800000, 0x1000000, CRC(61d5c470) SHA1(c2b3dc71706a5c8a237efc2fe5c35061abb99173) )
4118		ROM_LOAD( "mpr-24281.ic6", 0x5800000, 0x1000000, CRC(39133c32) SHA1(09ea8c1a98ba0fac36e18ae14ed5302feaeb89ca) )
4119		ROM_LOAD( "mpr-24282.ic7", 0x6800000, 0x1000000, CRC(9aa4ad5a) SHA1(2d81f99a579477c5db725f71c51f18afc15abce7) )
	4112	ROM_LOAD( "epr-24286.ic22", 0x0000000, 0x0400000, CRC(9d26e2fc) SHA1(74bcd7daf994a5c97c836b6f060c73d31a9c06d8) )
	4113	ROM_LOAD( "mpr-24276.ic1", 0x0800000, 0x1000000, CRC(35ac9283) SHA1(74af0e3f294fc76d44c8c6b54042186dec8b9f8a) )
	4114	ROM_LOAD( "mpr-24277.ic2", 0x1800000, 0x1000000, CRC(16111394) SHA1(7ca20de07cfa3fa248b472819bc893f00689e3a1) )
	4115	ROM_LOAD( "mpr-24278.ic3", 0x2800000, 0x1000000, CRC(bf0ec0bc) SHA1(7de72decf97999e74b510e9655a57ad6d1def1c8) )
	4116	ROM_LOAD( "mpr-24279.ic4", 0x3800000, 0x1000000, CRC(f7d0ab5b) SHA1(10188a22a1918b18008973135ef2e00dd26dd6cb) )
	4117	ROM_LOAD( "mpr-24280.ic5", 0x4800000, 0x1000000, CRC(61d5c470) SHA1(c2b3dc71706a5c8a237efc2fe5c35061abb99173) )
	4118	ROM_LOAD( "mpr-24281.ic6", 0x5800000, 0x1000000, CRC(39133c32) SHA1(09ea8c1a98ba0fac36e18ae14ed5302feaeb89ca) )
	4119	ROM_LOAD( "mpr-24282.ic7", 0x6800000, 0x1000000, CRC(9aa4ad5a) SHA1(2d81f99a579477c5db725f71c51f18afc15abce7) )
4120	4120
4121	4121	ROM_REGION( 4, "rom_key", ROMREGION_ERASE00 )
4122	4122	ROM_END
r32760	r32761
9014	9014	/* 0018 */ GAME( 2001, lupinsho, naomigd, naomigd, hotd2, naomi_state, naomigd, ROT0, "Sega / Eighting", "Lupin The Third - The Shooting (GDS-0018)", GAME_FLAGS )
9015	9015	// 0018A Lupin The Third - The Shooting (Rev A)
9016	9016	/* 0019 */ GAME( 2002, vathlete, naomigd, naomigd, naomi, naomi_state, naomigd, ROT0, "Sega", "Virtua Athletics / Virtua Athlete (GDS-0019)", GAME_FLAGS )
9017		/* 0020 */ GAME( 2002, initdo, initd, naomi2gd, naomi, naomi_state, naomi2, ROT0, "Sega", "Initial D Arcade Stage (Japan) (GDS-0020)", GAME_FLAGS )
	9017	/* 0020 */ GAME( 2002, initdo, initd, naomi2gd, naomi, naomi_state, naomi2, ROT0, "Sega", "Initial D Arcade Stage (Japan) (GDS-0020)", GAME_FLAGS )
9018	9018	// 0020A Initial D Arcade Stage (Rev A)
9019	9019	/* 0020B */ GAME( 2002, initd, naomi2, naomi2gd, naomi, naomi_state, naomi2, ROT0, "Sega", "Initial D Arcade Stage (Rev B) (Japan) (GDS-0020B)", GAME_FLAGS )
9020	9020	// 0021 Lupin The Third - The Typing

trunk/src/mame/drivers/snk6502.c
r32760	r32761
827	827	MCFG_SOUND_ADD("snk6502", SNK6502, 0)
828	828	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
829	829
830
	830
831	831	MCFG_SOUND_ADD("samples", SAMPLES, 0)
832	832	MCFG_SAMPLES_CHANNELS(4)
833	833	MCFG_SAMPLES_NAMES(sasuke_sample_names)

trunk/src/mame/drivers/tatsumi.c
r32760	r32761
1397	1397	int len1 = memregion("gfx2")->bytes();
1398	1398	UINT8 *src2 = memregion("gfx3")->base();
1399	1399	int len2 = memregion("gfx3")->bytes();
1400
	1400
1401	1401	for (int i=0; i<len1; i+=32)
1402	1402	{
1403	1403	memcpy(dst,src1,32);

trunk/src/mame/drivers/r2dx_v33.c
r32760	r32761
5	5	Raiden 2 / DX checks if there's the string "RAIDEN" at start-up inside the eeprom, otherwise it dies.
6	6	Then it puts settings at 0x9e08 and 0x9e0a (bp 91acb)
7	7
8		the 333 ROM is a 0x10000 byte table (bytes values?)
9		followed by a 0x400 bytes (word values)?
10		the remaining space is 0xff
	8	the 333 ROM is a 0x10000 byte table (bytes values?)
	9	followed by a 0x400 bytes (word values)?
	10	the remaining space is 0xff
11	11
12		Notes:
	12	Notes:
13	13
14		Zero Team 2000
15		- EEPROM contains high scores, but they don't get restored? (original bug?)
	14	Zero Team 2000
	15	- EEPROM contains high scores, but they don't get restored? (original bug?)
16	16
17		New Zero Team
18		- 2 Player only? Service mode only shows 2 Players and I don't see a switch
19		- Stages 3 and 1 are swapped, this is correct.
	17	New Zero Team
	18	- 2 Player only? Service mode only shows 2 Players and I don't see a switch
	19	- Stages 3 and 1 are swapped, this is correct.
20	20
21		Raiden 2 New / Raiden DX
22		- This is a 2-in-1 board. The current game to boot is stored in the EEPROM.
23		If you wish to change game then on powerup you must hold down all 4 (P1) joystick
24		directions simultaneously along with either button 1 or button 2.
25		Obviously this is impossible with a real joystck!
	21	Raiden 2 New / Raiden DX
	22	- This is a 2-in-1 board. The current game to boot is stored in the EEPROM.
	23	If you wish to change game then on powerup you must hold down all 4 (P1) joystick
	24	directions simultaneously along with either button 1 or button 2.
	25	Obviously this is impossible with a real joystck!
26	26
27		It is also impossible in MAME unless you enable -joystick_contradictory
28		to disable MAME from preventing opposing joystick directions being pressed
29		and you'll most likely have to remap some keys too because 5 buttons at the
30		same time is beyond the limits of most keyboards.
	27	It is also impossible in MAME unless you enable -joystick_contradictory
	28	to disable MAME from preventing opposing joystick directions being pressed
	29	and you'll most likely have to remap some keys too because 5 buttons at the
	30	same time is beyond the limits of most keyboards.
31	31
32		We currently use a default EEPROM for each game as this is most likely how
33		it shipped, the game changing is an undocumented secret.
	32	We currently use a default EEPROM for each game as this is most likely how
	33	it shipped, the game changing is an undocumented secret.
34	34
35		- The sound is awful, this is just how it is.
36
37		- In Raiden 2 New stages 5 and 1 are swapped, and the intro is missing, this is
38		correct.
	35	- The sound is awful, this is just how it is.
39	36
	37	- In Raiden 2 New stages 5 and 1 are swapped, and the intro is missing, this is
	38	correct.
	39
40	40	*/
41	41
42		/* Rom structure notes
	42	/* Rom structure notes
43	43
44	44	Raiden 2 New/DX (hardware can bank upper/lower half of rom to switch fixed areas)
45	45
r32760	r32761
192	192	// 0x04 is active in Raiden DX mode, it could be part of the rom bank (which half of the rom to use) or the FG tile bank (or both?)
193	193	// the bit gets set if it reads RAIDENDX from the EEPROM
194	194	m_r2dxgameselect = (data & 0x04) >> 2;
195
	195
196	196	tx_bank = m_r2dxgameselect;
197	197	text_layer->mark_all_dirty();
198	198
r32760	r32761
277	277
278	278	WRITE16_MEMBER(r2dx_v33_state::mcu_table2_w)
279	279	{
280		// printf("mcu_table2_w %04x %04x\n", data, mem_mask);
	280	// printf("mcu_table2_w %04x %04x\n", data, mem_mask);
281	281
282	282	mcu_data[offset+4] = data;
283	283
r32760	r32761
356	356	{
357	357	int src = 0x1f000;
358	358
359		for (int i = 0; i < 0x1000 / 2; i++)
	359	for (int i = 0; i < 0x1000 / 2; i++)
360	360	{
361	361	UINT16 palval = space.read_word(src);
362	362	src += 2;
r32760	r32761
392	392	AM_RANGE(0x00436, 0x00437) AM_READ(r2dx_cos_r)
393	393
394	394	AM_RANGE(0x00600, 0x0064f) AM_DEVREADWRITE("crtc", seibu_crtc_device, read, write)
395		// AM_RANGE(0x00650, 0x0068f) AM_RAM //???
	395	// AM_RANGE(0x00650, 0x0068f) AM_RAM //???
396	396
397	397	AM_RANGE(0x0068e, 0x0068f) AM_WRITENOP // maybe a watchdog?
398	398	AM_RANGE(0x006b0, 0x006b1) AM_WRITE(mcu_prog_w) // could be encryption key uploads just like raiden2.c ?
r32760	r32761
400	400	// AM_RANGE(0x006b4, 0x006b5) AM_WRITENOP
401	401	// AM_RANGE(0x006b6, 0x006b7) AM_WRITENOP
402	402	AM_RANGE(0x006bc, 0x006bd) AM_WRITE(mcu_prog_offs_w)
403		// AM_RANGE(0x006be, 0x006bf) AM_WRITENOP
	403	// AM_RANGE(0x006be, 0x006bf) AM_WRITENOP
404	404
405	405	// sprite protection not 100% verified as the same
406	406	AM_RANGE(0x006c0, 0x006c1) AM_READWRITE(sprite_prot_off_r, sprite_prot_off_w)
r32760	r32761
411	411	AM_RANGE(0x006da, 0x006db) AM_WRITE(sprite_prot_y_w)
412	412	AM_RANGE(0x006dc, 0x006dd) AM_READWRITE(sprite_prot_maxx_r, sprite_prot_maxx_w)
413	413	AM_RANGE(0x006de, 0x006df) AM_WRITE(sprite_prot_src_w)
414
415	414
	415
416	416	AM_RANGE(0x00700, 0x00701) AM_WRITE(rdx_v33_eeprom_w)
417	417	AM_RANGE(0x00740, 0x00741) AM_READ(r2dx_debug_r)
418	418	AM_RANGE(0x00744, 0x00745) AM_READ_PORT("INPUT")
r32760	r32761
502	502
503	503	WRITE16_MEMBER(r2dx_v33_state::zerotm2k_eeprom_w)
504	504	{
505		// printf("zerotm2k_eeprom_w %04x %04x\n", data, mem_mask);
	505	// printf("zerotm2k_eeprom_w %04x %04x\n", data, mem_mask);
506	506
507	507	m_eeprom->clk_write((data & 0x02) ? ASSERT_LINE : CLEAR_LINE);
508	508	m_eeprom->di_write((data & 0x04) >> 2);
r32760	r32761
962	962	ROM_LOAD("prg.223", 0x000000, 0x400000, CRC(b3dbcf98) SHA1(30d6ec2090531c8c579dff74c4898889902d7d87) )
963	963
964	964	ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF ) /* v33 main cpu */
965
	965
966	966	ROM_REGION( 0x040000, "gfx1", 0 ) /* chars */
967	967	ROM_LOAD( "fix.613", 0x000000, 0x040000, CRC(3da27e39) SHA1(3d446990bf36dd0a3f8fadb68b15bed54904c8b5) )
968	968
r32760	r32761
1011	1011	ROM_END
1012	1012
1013	1013	// uses dipswitches
1014		ROM_START( nzeroteam ) /* V33 SYSTEM TYPE_B hardware, uses SEI333 (AKA COPX-D3) for protection */
	1014	ROM_START( nzeroteam ) /* V33 SYSTEM TYPE_B hardware, uses SEI333 (AKA COPX-D3) for protection */
1015	1015	ROM_REGION( 0x100000, "mainprg", 0 ) /* v30 main cpu */
1016	1016	ROM_LOAD16_BYTE("prg1", 0x000000, 0x80000, CRC(3c7d9410) SHA1(25f2121b6c2be73f11263934266901ed5d64d2ee) )
1017	1017	ROM_LOAD16_BYTE("prg2", 0x000001, 0x80000, CRC(6cba032d) SHA1(bf5d488cd578fff09e62e3650efdee7658033e3f) )

trunk/src/mame/drivers/warpsped.c
r32760	r32761
98	98
99	99	required_device<cpu_device> m_maincpu;
100	100	required_device<gfxdecode_device> m_gfxdecode;
101
	101
102	102	required_shared_ptr<UINT8> m_videoram;
103	103	required_shared_ptr<UINT8> m_workram;
104
	104
105	105	tilemap_t *m_text_tilemap;
106	106	tilemap_t *m_starfield_tilemap;
107	107	UINT8 m_regs[0x28];

trunk/src/mame/drivers/splash.c
r32760	r32761
1023	1023
1024	1024	int ofst = offset+(0x100000/2);
1025	1025
1026		// logerror ("PROTR: %5.5x, pc: %5.5x\n", ofst*2, pc);
	1026	// logerror ("PROTR: %5.5x, pc: %5.5x\n", ofst*2, pc);
1027	1027
1028	1028	// don't interfere with ram check.
1029	1029	if (pc == 0x04770) return 0x00;
r32760	r32761
1071	1071
1072	1072	//-----------------------------------------------------------------
1073	1073	// sub $7F70, $8038, $116E2, no subtractions, straight compare!, original value from 68k
1074		// increase ff3cc8 value in sub $116e2
1075
	1074	// increase ff3cc8 value in sub $116e2
	1075
1076	1076	case ((0x100001 / 2) + 0x0010): // $7F72
1077	1077	funystrp_val = funystrp_ff3cc8_val;
1078	1078	return 0;
r32760	r32761
1102	1102	return (funystrp_val + 0x12) & 0xff;
1103	1103
1104	1104	// first case... weird?
1105		// case ((0x104801 / 2) + 0x013A): // $857E
1106		// return (funystrp_val + 0x00) & 0xff;
	1105	// case ((0x104801 / 2) + 0x013A): // $857E
	1106	// return (funystrp_val + 0x00) & 0xff;
1107	1107
1108	1108	case ((0x104801 / 2) + 0x0277): // $85A4
1109	1109	return (funystrp_val + 0x04) & 0xff;
r32760	r32761
1136	1136
1137	1137	//-----------------------------------------------------------------
1138	1138	// sub $9DD2, subtractions, original value from protection device
1139
	1139
1140	1140	case ((0x170001 / 2) + 0x006B): // $9DD4
1141	1141	funystrp_val = 0;
1142	1142	return 0;
r32760	r32761
1176	1176	//-----------------------------------------------------------------
1177	1177	// sub $C5E4, subtractions, original value from 68k
1178	1178
1179		// these cases are already in sub $7ACC, last one is new!!
1180		// case ((0x107001 / 2) + 0x0030): // $7ACE
1181		// funystrp_val = funystrp_ff3cc7_val & 0x7f;
1182		// return 0;
	1179	// these cases are already in sub $7ACC, last one is new!!
	1180	// case ((0x107001 / 2) + 0x0030): // $7ACE
	1181	// funystrp_val = funystrp_ff3cc7_val & 0x7f;
	1182	// return 0;
1183	1183
1184		// case ((0x107001 / 2) + 0x013e): // $7AFC
1185		// return (funystrp_val + 0x13) & 0xff;
	1184	// case ((0x107001 / 2) + 0x013e): // $7AFC
	1185	// return (funystrp_val + 0x13) & 0xff;
1186	1186
1187		// case ((0x107001 / 2) + 0x0279): // $7B38
1188		// return (funystrp_val + 0x22) & 0xff;
	1187	// case ((0x107001 / 2) + 0x0279): // $7B38
	1188	// return (funystrp_val + 0x22) & 0xff;
1189	1189
1190		// case ((0x107001 / 2) + 0x0357): // $7B6E
1191		// return (funystrp_val + 0x44) & 0xff;
	1190	// case ((0x107001 / 2) + 0x0357): // $7B6E
	1191	// return (funystrp_val + 0x44) & 0xff;
1192	1192
1193	1193	case ((0x107001 / 2) + 0x0381): // $7BA4
1194	1194	return (funystrp_val + 0x6a) & 0xff;
r32760	r32761
1215	1215	//-----------------------------------------------------------------
1216	1216	// sub $F72C, subtractions, original value from protection device,
1217	1217	// routine verified working!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1218
	1218
1219	1219	case ((0x100001 / 2) + 0x0017): // $F72E
1220	1220	funystrp_val = 0;
1221	1221	return 0;
r32760	r32761
1233	1233	return (funystrp_val + 0x70) & 0xff;
1234	1234
1235	1235	//-----------------------------------------------------------------
1236		// sub $F82E, subtractions, original value from protection device,
1237
	1236	// sub $F82E, subtractions, original value from protection device,
	1237
1238	1238	case ((0x100001 / 2) + 0x0013): // $F830
1239	1239	funystrp_val = 0;
1240	1240	return 0;
r32760	r32761
1242	1242	case ((0x100001 / 2) + 0x0125): // $F84E
1243	1243	return (funystrp_val + 0x17) & 0xff;
1244	1244
1245		// used in sub $7E76
1246		// case ((0x110001 / 2) + 0x0261): // $F88A
1247		// return (funystrp_val + 0x0f) & 0xff;
	1245	// used in sub $7E76
	1246	// case ((0x110001 / 2) + 0x0261): // $F88A
	1247	// return (funystrp_val + 0x0f) & 0xff;
1248	1248
1249		// case ((0x110001 / 2) + 0x0322): // $F8C0
1250		// return (funystrp_val + 0x12) & 0xff;
	1249	// case ((0x110001 / 2) + 0x0322): // $F8C0
	1250	// return (funystrp_val + 0x12) & 0xff;
1251	1251
1252		// case ((0x110001 / 2) + 0x039B): // $F8F6
1253		// return (funystrp_val + 0x70) & 0xff;
	1252	// case ((0x110001 / 2) + 0x039B): // $F8F6
	1253	// return (funystrp_val + 0x70) & 0xff;
1254	1254
1255	1255	//-----------------------------------------------------------------
1256	1256	// sub $10FE2, subtractions, original value from protection device
1257	1257	// routine is different from rest, unoptimized or just poorly coded?
1258	1258	// examine later to verify this is right
1259
	1259
1260	1260	case ((0x105001 / 2) + 0x0021): // $10FF6
1261	1261	funystrp_val = 0;
1262	1262	return 0;
r32760	r32761
1274	1274	return (funystrp_val + 0x03) & 0xff;
1275	1275
1276	1276	//-----------------------------------------------------------------
1277		// sub $11F2C, subtractions, original value from protection device,
	1277	// sub $11F2C, subtractions, original value from protection device,
1278	1278	// routine is different from rest, unoptimized or just poorly coded?
1279	1279	// examine later to verify this is right
1280
	1280
1281	1281	case ((0x183001 / 2) + 0x0088): // $11F3C
1282	1282	funystrp_val = 0;
1283	1283	return 0;
r32760	r32761
1302	1302	{
1303	1303	int ofst = (0x100000/2)+offset;
1304	1304
1305		// logerror ("PROTW: %5.5x, %4.4x, PC: %5.5x m: %4.4x\n", ofst*2, data, space.device().safe_pc(), mem_mask);
	1305	// logerror ("PROTW: %5.5x, %4.4x, PC: %5.5x m: %4.4x\n", ofst*2, data, space.device().safe_pc(), mem_mask);
1306	1306
1307		// if (ACCESSING_BITS_0_7) // ??
	1307	// if (ACCESSING_BITS_0_7) // ??
1308	1308	{
1309	1309	switch (ofst)
1310	1310	{
r32760	r32761
1320	1320	case (0x1007e5/2):
1321	1321	funystrp_ff3cc8_val = data;
1322	1322	return;
1323
	1323
1324	1324	case (0x1007e7/2):
1325	1325	funystrp_ff3cc7_val = data;
1326	1326	return;

trunk/src/mame/drivers/bmcpokr.c
r32760	r32761
232	232
233	233	switch (layer)
234	234	{
235		case 1: tmap = m_tilemap_1; scroll = m_scrollram_1; ctrl = (m_layerctrl[0] >> 8) & 0xff; break;
236		case 2: tmap = m_tilemap_2; scroll = m_scrollram_2; ctrl = (m_layerctrl[0] >> 0) & 0xff; break;
237		default: tmap = 0; scroll = m_scrollram_3; ctrl = (m_layerctrl[1] >> 8) & 0xff; break;
	235	case 1: tmap = m_tilemap_1; scroll = m_scrollram_1; ctrl = (m_layerctrl[0] >> 8) & 0xff; break;
	236	case 2: tmap = m_tilemap_2; scroll = m_scrollram_2; ctrl = (m_layerctrl[0] >> 0) & 0xff; break;
	237	default: tmap = 0; scroll = m_scrollram_3; ctrl = (m_layerctrl[1] >> 8) & 0xff; break;
238	238	}
239	239
240	240	if (ctrl == 0x00)
r32760	r32761
292	292
293	293	bitmap.fill(m_palette->black_pen(), cliprect);
294	294
295		if (layers_ctrl & 2) draw_layer(screen, bitmap, cliprect, 2);
	295	if (layers_ctrl & 2) draw_layer(screen, bitmap, cliprect, 2);
296	296	/*
297		title: 17, 13/17
298		dogs: 1b, 13, 17
299		service: 17
300		game: 17
	297	title: 17, 13/17
	298	dogs: 1b, 13, 17
	299	service: 17
	300	game: 17
301	301	*/
302	302	if (*m_priority & 0x0008)
303	303	{
304		if (layers_ctrl & 4) draw_layer(screen, bitmap, cliprect, 3);
305		if (layers_ctrl & 1) draw_layer(screen, bitmap, cliprect, 1);
	304	if (layers_ctrl & 4) draw_layer(screen, bitmap, cliprect, 3);
	305	if (layers_ctrl & 1) draw_layer(screen, bitmap, cliprect, 1);
306	306	}
307	307	else
308	308	{
309		if (layers_ctrl & 1) draw_layer(screen, bitmap, cliprect, 1);
310		if (layers_ctrl & 4) draw_layer(screen, bitmap, cliprect, 3);
	309	if (layers_ctrl & 1) draw_layer(screen, bitmap, cliprect, 1);
	310	if (layers_ctrl & 4) draw_layer(screen, bitmap, cliprect, 3);
311	311	}
312	312	return 0;
313	313	}
r32760	r32761
326	326	{
327	327	switch (m_prot_val >> 8)
328	328	{
329		case 0x00: return 0x1d << 8;
330		case 0x94: return 0x81 << 8;
	329	case 0x00: return 0x1d << 8;
	330	case 0x94: return 0x81 << 8;
331	331	}
332	332	return 0x00 << 8;
333	333	}
334	334	WRITE16_MEMBER(bmcpokr_state::prot_w)
335	335	{
336	336	COMBINE_DATA(&m_prot_val);
337		// logerror("%s: prot val = %04x\n", machine().describe_context(), m_prot_val);
	337	// logerror("%s: prot val = %04x\n", machine().describe_context(), m_prot_val);
338	338	}
339	339
340	340	/***************************************************************************
r32760	r32761
346	346	COMBINE_DATA(&m_mux);
347	347	if (ACCESSING_BITS_0_7)
348	348	{
349		m_hopper->write(space, 0, (data & 0x0001) ? 0x80 : 0x00); // hopper motor
350		coin_counter_w(machine(), 1, data & 0x0002); // coin-in / key-in
351		coin_counter_w(machine(), 2, data & 0x0004); // pay-out
352		// data & 0x0060 // DSW mux
353		// data & 0x0080 // ? always on
	349	m_hopper->write(space, 0, (data & 0x0001) ? 0x80 : 0x00); // hopper motor
	350	coin_counter_w(machine(), 1, data & 0x0002); // coin-in / key-in
	351	coin_counter_w(machine(), 2, data & 0x0004); // pay-out
	352	// data & 0x0060 // DSW mux
	353	// data & 0x0080 // ? always on
354	354	}
355	355
356		// popmessage("mux %04x", m_mux);
	356	// popmessage("mux %04x", m_mux);
357	357	}
358	358	READ16_MEMBER(bmcpokr_state::dsw_r)
359	359	{
r32760	r32761
402	402
403	403	AM_RANGE(0x2a0000, 0x2dffff) AM_RAM_WRITE(pixram_w) AM_SHARE("pixram")
404	404
405		AM_RANGE(0x2ff800, 0x2ff9ff) AM_RAM AM_SHARE("scrollram_1")
406		AM_RANGE(0x2ffa00, 0x2ffbff) AM_RAM AM_SHARE("scrollram_2")
407		AM_RANGE(0x2ffc00, 0x2ffdff) AM_RAM AM_SHARE("scrollram_3")
	405	AM_RANGE(0x2ff800, 0x2ff9ff) AM_RAM AM_SHARE("scrollram_1")
	406	AM_RANGE(0x2ffa00, 0x2ffbff) AM_RAM AM_SHARE("scrollram_2")
	407	AM_RANGE(0x2ffc00, 0x2ffdff) AM_RAM AM_SHARE("scrollram_3")
408	408	AM_RANGE(0x2ffe00, 0x2fffff) AM_RAM
409	409
410	410	AM_RANGE(0x320000, 0x320003) AM_RAM AM_SHARE("layerctrl")
411	411
412	412	AM_RANGE(0x330000, 0x330001) AM_READWRITE(prot_r, prot_w)
413	413
414		AM_RANGE(0x340000, 0x340001) AM_RAM // 340001.b, rw
415		AM_RANGE(0x340002, 0x340003) AM_RAM // 340003.b, w(9d)
	414	AM_RANGE(0x340000, 0x340001) AM_RAM // 340001.b, rw
	415	AM_RANGE(0x340002, 0x340003) AM_RAM // 340003.b, w(9d)
416	416	AM_RANGE(0x340006, 0x340007) AM_WRITE(irq_ack_w)
417	417	AM_RANGE(0x340008, 0x340009) AM_WRITE(irq_enable_w)
418		AM_RANGE(0x34000e, 0x34000f) AM_RAM AM_SHARE("priority") // 34000f.b, w (priority?)
	418	AM_RANGE(0x34000e, 0x34000f) AM_RAM AM_SHARE("priority") // 34000f.b, w (priority?)
419	419	AM_RANGE(0x340016, 0x340017) AM_WRITE(pixpal_w)
420		AM_RANGE(0x340018, 0x340019) AM_RAM // 340019.b, w
421		AM_RANGE(0x34001a, 0x34001b) AM_READ(unk_r) AM_WRITENOP
422		AM_RANGE(0x34001c, 0x34001d) AM_RAM // 34001d.b, w(0)
	420	AM_RANGE(0x340018, 0x340019) AM_RAM // 340019.b, w
	421	AM_RANGE(0x34001a, 0x34001b) AM_READ(unk_r) AM_WRITENOP
	422	AM_RANGE(0x34001c, 0x34001d) AM_RAM // 34001d.b, w(0)
423	423
424	424	AM_RANGE(0x350000, 0x350001) AM_DEVWRITE8("ramdac",ramdac_device, index_w, 0x00ff )
425	425	AM_RANGE(0x350002, 0x350003) AM_DEVWRITE8("ramdac",ramdac_device, pal_w, 0x00ff )
r32760	r32761
453	453	PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_GAMBLE_DEAL ) PORT_CONDITION("DSW4",0x80,EQUALS,0x80) // n.a. [START, ESC in service mode]
454	454	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_GAMBLE_TAKE ) PORT_CONDITION("DSW4",0x80,EQUALS,0x80) // SCORE
455	455	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_POKER_BET ) PORT_CONDITION("DSW4",0x80,EQUALS,0x80) // BET [BET, credit -1]
456		PORT_BIT( 0x0200, IP_ACTIVE_HIGH,IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, bmcpokr_state,hopper_r, NULL) // HP [HOPPER, credit -100]
	456	PORT_BIT( 0x0200, IP_ACTIVE_HIGH,IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, bmcpokr_state,hopper_r, NULL) // HP [HOPPER, credit -100]
457	457	PORT_SERVICE_NO_TOGGLE( 0x0400, IP_ACTIVE_LOW ) PORT_CONDITION("DSW4",0x80,EQUALS,0x80) // ACCOUNT [SERVICE MODE]
458	458	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_GAMBLE_KEYOUT ) PORT_CONDITION("DSW4",0x80,EQUALS,0x80) // KEY-OUT [KEY-OUT, no hopper]
459	459	PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_GAMBLE_D_UP ) PORT_CONDITION("DSW4",0x80,EQUALS,0x80) // DOUBLE-UP
r32760	r32761
471	471	PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_GAMBLE_DEAL ) PORT_CONDITION("DSW4",0x80,EQUALS,0x00) // n.a. [START, ESC in service mode]
472	472	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2) PORT_CONDITION("DSW4",0x80,EQUALS,0x00) // <Left>2 (3rd)
473	473	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_POKER_BET ) PORT_CONDITION("DSW4",0x80,EQUALS,0x00) // <Down>1 (2nd) [BET, credit -1]
474		// PORT_BIT( 0x0200, IP_ACTIVE_HIGH,IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, bmcpokr_state,hopper_r, NULL) // HP [HOPPER, credit -100]
	474	// PORT_BIT( 0x0200, IP_ACTIVE_HIGH,IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, bmcpokr_state,hopper_r, NULL) // HP [HOPPER, credit -100]
475	475	PORT_SERVICE_NO_TOGGLE( 0x0400, IP_ACTIVE_LOW ) PORT_CONDITION("DSW4",0x80,EQUALS,0x00) // A2 [SERVICE MODE]
476	476	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_GAMBLE_KEYOUT ) PORT_CONDITION("DSW4",0x80,EQUALS,0x00) // C2 [KEY-OUT, no hopper]
477	477	PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_GAMBLE_D_UP ) PORT_CONDITION("DSW4",0x80,EQUALS,0x00) // S1 [START, ESC in service mode]
r32760	r32761
480	480	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_CONDITION("DSW4",0x80,EQUALS,0x00) PORT_IMPULSE(5) // <coin-in> (1st) [COIN-IN, credit +100, coin-jam]
481	481
482	482	PORT_START("INPUTS2")
483		PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_GAMBLE_PAYOUT ) // <coin-out> (2nd) [COIN-OUT, hopper (otherwise pay-error)]
	483	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_GAMBLE_PAYOUT ) // <coin-out> (2nd) [COIN-OUT, hopper (otherwise pay-error)]
484	484
485	485	PORT_START("DSW1")
486	486	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("DIP1:1")
r32760	r32761
602	602	ADDRESS_MAP_END
603	603
604	604	static MACHINE_CONFIG_START( bmcpokr, bmcpokr_state )
605		MCFG_CPU_ADD("maincpu", M68000, XTAL_42MHz / 4) // 68000 @10.50MHz (42/4)
	605	MCFG_CPU_ADD("maincpu", M68000, XTAL_42MHz / 4) // 68000 @10.50MHz (42/4)
606	606	MCFG_CPU_PROGRAM_MAP(bmcpokr_mem)
607	607	MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", bmcpokr_state, interrupt, "screen", 0, 1)
608	608
609	609	MCFG_SCREEN_ADD("screen", RASTER)
610		MCFG_SCREEN_REFRESH_RATE(58.935) // HSync - 15.440kHz, VSync - 58.935Hz
	610	MCFG_SCREEN_REFRESH_RATE(58.935) // HSync - 15.440kHz, VSync - 58.935Hz
611	611
612	612	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
613	613	MCFG_SCREEN_UPDATE_DRIVER(bmcpokr_state, screen_update_bmcpokr)
r32760	r32761
621	621
622	622	MCFG_NVRAM_ADD_0FILL("nvram")
623	623
624		MCFG_TICKET_DISPENSER_ADD("hopper", attotime::from_msec(10), TICKET_MOTOR_ACTIVE_HIGH, TICKET_STATUS_ACTIVE_LOW) // hopper stuck low if too slow
	624	MCFG_TICKET_DISPENSER_ADD("hopper", attotime::from_msec(10), TICKET_MOTOR_ACTIVE_HIGH, TICKET_STATUS_ACTIVE_LOW) // hopper stuck low if too slow
625	625
626	626	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
627	627
628		MCFG_SOUND_ADD("ymsnd", YM2413, XTAL_42MHz / 12) // UM3567 @3.50MHz (42/12)
	628	MCFG_SOUND_ADD("ymsnd", YM2413, XTAL_42MHz / 12) // UM3567 @3.50MHz (42/12)
629	629	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.50)
630	630	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.50)
631	631
632		MCFG_OKIM6295_ADD("oki", XTAL_42MHz / 40, OKIM6295_PIN7_HIGH) // M6295 @1.05MHz (42/40), pin 7 not verified
	632	MCFG_OKIM6295_ADD("oki", XTAL_42MHz / 40, OKIM6295_PIN7_HIGH) // M6295 @1.05MHz (42/40), pin 7 not verified
633	633	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.50)
634	634	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.50)
635	635	MACHINE_CONFIG_END

trunk/src/mame/drivers/jclub2.c
r32760	r32761
114	114	m_gamecpu(*this, "gamecpu"),
115	115	m_eeprom(*this, "eeprom"),
116	116	m_palette(*this, "palette"),
117		m_gfxdecode(*this, "gfxdecode")
	117	m_gfxdecode(*this, "gfxdecode")
118	118	{ }
119	119
120	120	tilemap_t *m_tmap;

trunk/src/mame/drivers/ltd.c
r32760	r32761
387	387	TIMER_DEVICE_CALLBACK_MEMBER( ltd_state::timer_r )
388	388	{
389	389	m_timer_r ^= 1;
390		m_maincpu->set_input_line(M6800_IRQ_LINE, (m_timer_r) ? CLEAR_LINE : ASSERT_LINE);
	390	m_maincpu->set_input_line(M6800_IRQ_LINE, (m_timer_r) ? CLEAR_LINE : ASSERT_LINE);
391	391	static const UINT8 patterns[16] = { 0x3f, 0x06, 0x5b, 0x4f, 0x66, 0x6d, 0x7c, 0x07, 0x7f, 0x67, 0x58, 0x4c, 0x62, 0x69, 0x78, 0 }; // 7447
392	392	m_out_offs++;
393	393	if (m_out_offs > 0x7f) m_out_offs = 0x60;

trunk/src/mame/drivers/segas32.c
r32760	r32761
2503	2503	requires 2 linked system32 pcbs
2504	2504	requires additional math DSP to be emulated
2505	2505
2506		The link PCB attaches 2 System 32 mainboards together, then ROM boards for each mainboard attaches to the link PCB.
2507		This provides a direct connection between the PCBs (NOT a network link) so they effectively operate as a single boardset
2508		sharing RAM (we should emulate it as such)
	2506	The link PCB attaches 2 System 32 mainboards together, then ROM boards for each mainboard attaches to the link PCB.
	2507	This provides a direct connection between the PCBs (NOT a network link) so they effectively operate as a single boardset
	2508	sharing RAM (we should emulate it as such)
2509	2509
2510		Link PCB is a single sparsely populated romless PCB but contains
2511
2512		Left side
2513		1x MB8431-12LP (IC2)
2514		2x HD74LS74AP (IC6, IC7)
2515		2x GAL16V8A-25LP (stamped 315-5545) (IC3)
	2510	Link PCB is a single sparsely populated romless PCB but contains
2516	2511
2517		Right side
2518		1x MB8421-12LP (IC1)
2519		1x GAL16V8A-25LP (stamped xxx-xxxx) (IC5)
2520		1x HD74LS74AP (IC8)
2521		1x GAL16V8A-25LP (stamped 315-5545) (IC4)
	2512	Left side
	2513	1x MB8431-12LP (IC2)
	2514	2x HD74LS74AP (IC6, IC7)
	2515	2x GAL16V8A-25LP (stamped 315-5545) (IC3)
2522	2516
2523		(todo, full layout)
	2517	Right side
	2518	1x MB8421-12LP (IC1)
	2519	1x GAL16V8A-25LP (stamped xxx-xxxx) (IC5)
	2520	1x HD74LS74AP (IC8)
	2521	1x GAL16V8A-25LP (stamped 315-5545) (IC4)
2524	2522
2525		~~The~~ ~~left~~ ~~Rom~~ ~~PCB~~ (~~mas~~t~~er?) c~~o~~ntains a sub-boar~~d o~~n the ROM board with the math DSP~~, ~~the~~ ~~right R~~o~~m PCB does no~~t ~~have this.~~
	2523	(todo, full layout)
2526	2524
	2525	The left Rom PCB (master?) contains a sub-board on the ROM board with the math DSP, the right Rom PCB does not have this.
	2526
2527	2527	*/
2528	2528	ROM_START( arescue )
2529	2529	ROM_REGION( 0x200000, "maincpu", 0 ) /* v60 code + data */

trunk/src/mame/drivers/stv.c
r32760	r32761
1251	1251	{
1252	1252	UINT8 *ROM;
1253	1253	UINT32 size = slot->common_get_size("rom");
1254
	1254
1255	1255	if (image.software_entry() == NULL)
1256	1256	return IMAGE_INIT_FAIL;
1257
	1257
1258	1258	slot->rom_alloc(size, GENERIC_ROM32_WIDTH, ENDIANNESS_BIG);
1259	1259	ROM = slot->get_rom_base();
1260	1260	memcpy(ROM, image.get_software_region("rom"), size);
1261
	1261
1262	1262	/* fix endianess */
1263	1263	{
1264	1264	UINT8 j[4];
1265
	1265
1266	1266	for (int i = 0; i < size; i += 4)
1267	1267	{
1268	1268	j[0] = ROM[i + 0];
r32760	r32761
1275	1275	ROM[i + 3] = j[0];
1276	1276	}
1277	1277	}
1278
	1278
1279	1279	return IMAGE_INIT_PASS;
1280	1280	}
1281	1281

trunk/src/mame/drivers/vectrex.c
r32760	r32761
19	19
20	20
21	21	static ADDRESS_MAP_START(vectrex_map, AS_PROGRAM, 8, vectrex_state )
22		AM_RANGE(0x0000, 0x7fff) AM_NOP // cart area, handled at machine_start
	22	AM_RANGE(0x0000, 0x7fff) AM_NOP // cart area, handled at machine_start
23	23	AM_RANGE(0xc800, 0xcbff) AM_RAM AM_MIRROR(0x0400) AM_SHARE("gce_vectorram")
24	24	AM_RANGE(0xd000, 0xd7ff) AM_READWRITE(vectrex_via_r, vectrex_via_w)
25	25	AM_RANGE(0xe000, 0xffff) AM_ROM AM_REGION("maincpu", 0)

trunk/src/mame/drivers/fuukifg2.c
r32760	r32761
238	238	INPUT_PORTS_END
239	239
240	240
241		static INPUT_PORTS_START( gogomileo ) /* The ealier version has different coinage settings. */
	241	static INPUT_PORTS_START( gogomileo ) /* The ealier version has different coinage settings. */
242	242	PORT_INCLUDE( gogomile )
243	243
244	244	PORT_MODIFY("DSW") // $880000.w

trunk/src/mame/drivers/tickee.c
r32760	r32761
53	53	optional_device<okim6295_device> m_oki;
54	54	required_device<screen_device> m_screen;
55	55	required_device<tlc34076_device> m_tlc34076;
56
	56
57	57	required_shared_ptr<UINT16> m_vram;
58	58	optional_shared_ptr<UINT16> m_control;
59
	59
60	60	emu_timer *m_setup_gun_timer;
61	61	int m_beamxadd;
62	62	int m_beamyadd;
63	63	int m_palette_bank;
64	64	UINT8 m_gunx[2];
65	65	void get_crosshair_xy(int player, int &x, int &y);
66
	66
67	67	DECLARE_WRITE16_MEMBER(rapidfir_transparent_w);
68	68	DECLARE_READ16_MEMBER(rapidfir_transparent_r);
69	69	DECLARE_WRITE16_MEMBER(tickee_control_w);
r32760	r32761
80	80	TIMER_CALLBACK_MEMBER(trigger_gun_interrupt);
81	81	TIMER_CALLBACK_MEMBER(clear_gun_interrupt);
82	82	TIMER_CALLBACK_MEMBER(setup_gun_interrupts);
83
	83
84	84	TMS340X0_TO_SHIFTREG_CB_MEMBER(rapidfir_to_shiftreg);
85	85	TMS340X0_FROM_SHIFTREG_CB_MEMBER(rapidfir_from_shiftreg);
86	86	TMS340X0_SCANLINE_RGB32_CB_MEMBER(scanline_update);
r32760	r32761
746	746	MCFG_CPU_PROGRAM_MAP(tickee_map)
747	747	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
748	748	MCFG_TMS340X0_PIXEL_CLOCK(VIDEO_CLOCK/2) /* pixel clock */
749		MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
	749	MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
750	750	MCFG_TMS340X0_SCANLINE_RGB32_CB(tickee_state, scanline_update) /* scanline callback (rgb32) */
751	751
752	752	MCFG_MACHINE_RESET_OVERRIDE(tickee_state,tickee)
r32760	r32761
791	791
792	792	/* basic machine hardware */
793	793	MCFG_CPU_ADD("maincpu", TMS34010, XTAL_50MHz)
794		MCFG_CPU_PROGRAM_MAP(rapidfir_map)
	794	MCFG_CPU_PROGRAM_MAP(rapidfir_map)
795	795	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
796	796	MCFG_TMS340X0_PIXEL_CLOCK(VIDEO_CLOCK/2) /* pixel clock */
797		MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
	797	MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
798	798	MCFG_TMS340X0_SCANLINE_RGB32_CB(tickee_state, rapidfir_scanline_update) /* scanline callback (rgb32) */
799	799	MCFG_TMS340X0_TO_SHIFTREG_CB(tickee_state, rapidfir_to_shiftreg) /* write to shiftreg function */
800	800	MCFG_TMS340X0_FROM_SHIFTREG_CB(tickee_state, rapidfir_from_shiftreg) /* read from shiftreg function */
r32760	r32761
826	826	MCFG_CPU_PROGRAM_MAP(mouseatk_map)
827	827	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
828	828	MCFG_TMS340X0_PIXEL_CLOCK(VIDEO_CLOCK/2) /* pixel clock */
829		MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
	829	MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
830	830	MCFG_TMS340X0_SCANLINE_RGB32_CB(tickee_state, scanline_update) /* scanline callback (rgb32) */
831	831
832	832	MCFG_MACHINE_RESET_OVERRIDE(tickee_state,tickee)

trunk/src/mame/drivers/chqflag.c
r32760	r32761
178	178	AM_RANGE(0x8000, 0x87ff) AM_RAM /* RAM */
179	179	AM_RANGE(0x9000, 0x9000) AM_WRITE(k007232_bankswitch_w) /* 007232 bankswitch */
180	180	AM_RANGE(0xa000, 0xa00d) AM_DEVREADWRITE("k007232_1", k007232_device, read, write) /* 007232 (chip 1) */
181		AM_RANGE(0xa01c, 0xa01c) AM_WRITE(k007232_extvolume_w) /* extra volume, goes to the 007232 w/ A4 */
	181	AM_RANGE(0xa01c, 0xa01c) AM_WRITE(k007232_extvolume_w) /* extra volume, goes to the 007232 w/ A4 */
182	182	/* selecting a different latch for the external port */
183	183	AM_RANGE(0xb000, 0xb00d) AM_DEVREADWRITE("k007232_2", k007232_device, read, write) /* 007232 (chip 2) */
184	184	AM_RANGE(0xc000, 0xc001) AM_DEVREADWRITE("ymsnd", ym2151_device, read, write) /* YM2151 */

trunk/src/mame/drivers/midyunit.c
r32760	r32761
1073	1073	MCFG_CPU_PROGRAM_MAP(main_map)
1074	1074	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
1075	1075	MCFG_TMS340X0_PIXEL_CLOCK(MEDRES_PIXEL_CLOCK) /* pixel clock */
1076		MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
	1076	MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
1077	1077	MCFG_TMS340X0_SCANLINE_IND16_CB(midyunit_state, scanline_update) /* scanline updater (indexed16) */
1078	1078	MCFG_TMS340X0_TO_SHIFTREG_CB(midyunit_state, to_shiftreg) /* write to shiftreg function */
1079	1079	MCFG_TMS340X0_FROM_SHIFTREG_CB(midyunit_state, from_shiftreg) /* read from shiftreg function */
r32760	r32761
1115	1115	MCFG_CPU_PROGRAM_MAP(main_map)
1116	1116	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
1117	1117	MCFG_TMS340X0_PIXEL_CLOCK(STDRES_PIXEL_CLOCK) /* pixel clock */
1118		MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
	1118	MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
1119	1119	MCFG_TMS340X0_SCANLINE_IND16_CB(midyunit_state, scanline_update) /* scanline updater (indexed16) */
1120	1120	MCFG_TMS340X0_TO_SHIFTREG_CB(midyunit_state, to_shiftreg) /* write to shiftreg function */
1121	1121	MCFG_TMS340X0_FROM_SHIFTREG_CB(midyunit_state, from_shiftreg) /* read from shiftreg function */

trunk/src/mame/drivers/segas18.c
r32760	r32761
908	908
909	909	static INPUT_PORTS_START( ddcrew3p )
910	910	PORT_INCLUDE( ddcrew2p )
911
	911
912	912	PORT_MODIFY("PORTC")
913	913	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
914	914	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)

trunk/src/mame/drivers/rainbow.c
r32760	r32761
841	841
842	842	ROM_REGION( 0x200, "pals", 0 )
843	843	ROM_LOAD( "jumping-pal16r6.bin", 0x000, 0x104, CRC(12e9a7b8) SHA1(a0ce8b6083c9adfcb4bdbca87f63a01f292525f3) )
844		ROM_LOAD( "jumping-pal20l8.bin", 0x000, 0x144, CRC(76944f81) SHA1(ab78e4e157ffdc13aea5dc360268b2640e60d19c) )
	844	ROM_LOAD( "jumping-pal20l8.bin", 0x000, 0x144, CRC(76944f81) SHA1(ab78e4e157ffdc13aea5dc360268b2640e60d19c) )
845	845	ROM_END
846	846
847	847	ROM_START( jumpinga )
r32760	r32761
887	887
888	888	ROM_REGION( 0x200, "pals", 0 )
889	889	ROM_LOAD( "jumping-pal16r6.bin", 0x000, 0x104, CRC(12e9a7b8) SHA1(a0ce8b6083c9adfcb4bdbca87f63a01f292525f3) )
890		ROM_LOAD( "jumping-pal20l8.bin", 0x000, 0x144, CRC(76944f81) SHA1(ab78e4e157ffdc13aea5dc360268b2640e60d19c) )
	890	ROM_LOAD( "jumping-pal20l8.bin", 0x000, 0x144, CRC(76944f81) SHA1(ab78e4e157ffdc13aea5dc360268b2640e60d19c) )
891	891	ROM_END
892	892
893	893

trunk/src/mame/drivers/srmp5.c
r32760	r32761
66	66	public:
67	67	srmp5_state(const machine_config &mconfig, device_type type, const char *tag)
68	68	: driver_device(mconfig, type, tag),
69		m_gfxdecode(*this, "gfxdecode"),
70		m_palette(*this, "palette"),
	69	m_gfxdecode(*this, "gfxdecode"),
	70	m_palette(*this, "palette"),
71	71	m_maincpu(*this,"maincpu"),
72		m_subcpu(*this, "sub")
73
	72	m_subcpu(*this, "sub")
	73
74	74	{ }
75	75
76	76	UINT32 m_databank;

trunk/src/mame/drivers/dragrace.c
r32760	r32761
84	84	m_discrete->write(space, DRAGRACE_ATTRACT_EN, (m_misc_flags & 0x00001000) ? 1: 0); // Attract enable
85	85	m_discrete->write(space, DRAGRACE_LOTONE_EN, (m_misc_flags & 0x00002000) ? 1: 0); // LoTone enable
86	86	m_discrete->write(space, DRAGRACE_HITONE_EN, (m_misc_flags & 0x20000000) ? 1: 0); // HiTone enable
87
	87
88	88	// the tachometers are driven from the same frequency generator that creates the engine sound
89	89	output_set_value("tachometer", ~m_misc_flags & 0x0000001f);
90	90	output_set_value("tachometer2", (~m_misc_flags & 0x001f0000) >> 0x10);

trunk/src/mame/drivers/coolpool.c
r32760	r32761
833	833	MCFG_TMS340X0_SCANLINE_RGB32_CB(coolpool_state, coolpool_scanline) /* scanline callback (rgb32) */
834	834	MCFG_TMS340X0_TO_SHIFTREG_CB(coolpool_state, to_shiftreg) /* write to shiftreg function */
835	835	MCFG_TMS340X0_FROM_SHIFTREG_CB(coolpool_state, from_shiftreg) /* read from shiftreg function */
836
	836
837	837	MCFG_CPU_ADD("dsp", TMS32026,XTAL_40MHz)
838	838	MCFG_CPU_PROGRAM_MAP(coolpool_dsp_pgm_map)
839	839	MCFG_CPU_IO_MAP(coolpool_dsp_io_map)

trunk/src/mame/drivers/midtunit.c
r32760	r32761
587	587	MCFG_CPU_PROGRAM_MAP(main_map)
588	588	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
589	589	MCFG_TMS340X0_PIXEL_CLOCK(PIXEL_CLOCK) /* pixel clock */
590		MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
	590	MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
591	591	MCFG_TMS340X0_SCANLINE_IND16_CB(midtunit_state, scanline_update) /* scanline updater (indexed16) */
592	592	MCFG_TMS340X0_TO_SHIFTREG_CB(midtunit_state, to_shiftreg) /* write to shiftreg function */
593	593	MCFG_TMS340X0_FROM_SHIFTREG_CB(midtunit_state, from_shiftreg) /* read from shiftreg function */

trunk/src/mame/drivers/twinkle.c
r32760	r32761
6	6
7	7	TODO:
8	8
9		dvd check for bmiidx, bmiidxa, bmiidxc & bmiidxca
	9	dvd check for bmiidx, bmiidxa, bmiidxc & bmiidxca
10	10	finish sound board emulation and remove response hle
11	11	emulate dvd player and video mixing
12	12	16seg led font
r32760	r32761
1038	1038
1039	1039	MCFG_DEVICE_ADD("rs232", RS232_PORT, 0)
1040	1040	MCFG_SLOT_OPTION_ADD("xvd701", JVC_XVD701)
1041		// MCFG_SLOT_OPTION_ADD("xvs1100", JVC_XVS1100) // 8th mix only
	1041	// MCFG_SLOT_OPTION_ADD("xvs1100", JVC_XVS1100) // 8th mix only
1042	1042	MCFG_SLOT_DEFAULT_OPTION("xvd701")
1043	1043	MCFG_RS232_RXD_HANDLER(DEVWRITELINE("fdc37c665gt:uart2", ins8250_uart_device, rx_w))
1044	1044	MCFG_RS232_DCD_HANDLER(DEVWRITELINE("fdc37c665gt:uart2", ins8250_uart_device, dcd_w))

trunk/src/mame/drivers/calchase.c
r32760	r32761
4	4
5	5	California Chase (c) 1999 The Game Room
6	6	Host Invaders (c) 1998 The Game Room
7
	7
8	8	driver by Angelo Salese & Grull Osgo
9	9
10	10	TODO:
r32760	r32761
50	50	connectors for COM1, COM2, LPT1, IDE0, IDE1, floppy etc
51	51	uses standard AT PSU
52	52
53		Video card is Trident TGUI9680 with 512k on-board VRAM
	53	Video card is Trident TGUI9680 with 512k on-board VRAM
54	54	Card is branded "Union UTD73" - these are all over eBay, for instance
55	55	RAM is AS4C256K16EO-50JC (x2)
56	56	Trident BIOS V5.5 (DIP28). Actual size unknown, dumped as 64k, 128k, 256k and 512k (can only be one of these sizes)
r32760	r32761
78	78	The HDD is DOS-readable and in fact the OS is just Windows 98 DOS and can
79	79	be easily copied. Tested with another HDD.... formatted with DOS, copied
80	80	all files across to new HDD, boots up fine.
81
82
83		Host Invaders is the same motherboard and video card as above, but instead of an HDD,
84		there is a CD-ROM drive.
85
	81
	82
	83	Host Invaders is the same motherboard and video card as above, but instead of an HDD,
	84	there is a CD-ROM drive.
	85
86	86	************************************************************************************/
87	87	/*
88	88	Grull Osgo - Improvements
r32760	r32761
744	744
745	745	ROM_START( hostinv )
746	746	ROM_REGION( 0x40000, "bios", 0 )
747		ROM_LOAD( "hostinv_bios.bin", 0x000000, 0x020000, CRC(5111e4b8) SHA1(20ab93150b61fd068f269368450734bba5dcb284) )
	747	ROM_LOAD( "hostinv_bios.bin", 0x000000, 0x020000, CRC(5111e4b8) SHA1(20ab93150b61fd068f269368450734bba5dcb284) )
748	748
749	749	ROM_REGION( 0x8000, "video_bios", 0 )
750	750	ROM_LOAD16_BYTE( "trident_tgui9680_bios.bin", 0x0000, 0x4000, CRC(1eebde64) SHA1(67896a854d43a575037613b3506aea6dae5d6a19) )
r32760	r32761
759	759
760	760	ROM_START( eggsplc )
761	761	ROM_REGION( 0x40000, "bios", 0 )
762		ROM_LOAD( "hostinv_bios.bin", 0x000000, 0x020000, CRC(5111e4b8) SHA1(20ab93150b61fd068f269368450734bba5dcb284) )
	762	ROM_LOAD( "hostinv_bios.bin", 0x000000, 0x020000, CRC(5111e4b8) SHA1(20ab93150b61fd068f269368450734bba5dcb284) )
763	763
764	764	ROM_REGION( 0x8000, "video_bios", 0 )
765	765	ROM_LOAD16_BYTE( "trident_tgui9680_bios.bin", 0x0000, 0x4000, CRC(1eebde64) SHA1(67896a854d43a575037613b3506aea6dae5d6a19) )
r32760	r32761
775	775	GAME( 1998, hostinv, 0, hostinv, calchase, calchase_state, hostinv, ROT0, "The Game Room", "Host Invaders", GAME_NOT_WORKING\|GAME_IMPERFECT_GRAPHICS )
776	776	GAME( 1999, calchase, 0, calchase, calchase, calchase_state, calchase, ROT0, "The Game Room", "California Chase", GAME_NOT_WORKING\|GAME_IMPERFECT_GRAPHICS )
777	777	GAME( 2002, eggsplc, 0, calchase, calchase, calchase_state, hostinv, ROT0, "The Game Room", "Eggs Playing Chicken", GAME_NOT_WORKING\|GAME_IMPERFECT_GRAPHICS )
778

trunk/src/mame/drivers/bfm_sc2.c
r32760	r32761
185	185	m_vfd0(*this, "vfd0"),
186	186	m_vfd1(*this, "vfd1"),
187	187	m_dm01(*this, "dm01") { }
188
	188
189	189	required_device<cpu_device> m_maincpu;
190	190	required_device<upd7759_device> m_upd7759;
191	191	optional_device<bfm_bd1_t> m_vfd0;
r32760	r32761
1389	1389	void bfm_sc2_state::save_state()
1390	1390	{
1391	1391	/* TODO: Split between the different machine types */
1392
	1392
1393	1393	save_item(NAME(m_key));
1394	1394	save_item(NAME(m_mmtr_latch));
1395	1395	save_item(NAME(m_irq_status));
r32760	r32761
2147	2147	nvram_device *e2ram = subdevice<nvram_device>("e2ram");
2148	2148	if (e2ram != NULL)
2149	2149	e2ram->set_base(m_e2ram, sizeof(m_e2ram));
2150
	2150
2151	2151	save_state();
2152	2152	}
2153	2153

trunk/src/mame/drivers/galpanic.c
r32760	r32761
1123	1123
1124	1124	GAME( 1994, supmodel, 0, supmodel, fantasia, driver_device, 0, ROT90, "Comad & New Japan System", "Super Model",GAME_NO_COCKTAIL )
1125	1125
1126		GAME( 1994, fantasian,fantasia, comad, fantasia, driver_device, 0, ROT90, "Comad & New Japan System", "Fantasia (940803 PCB)", GAME_NO_COCKTAIL )
	1126	GAME( 1994, fantasian,fantasia, comad, fantasia, driver_device, 0, ROT90, "Comad & New Japan System", "Fantasia (940803 PCB)", GAME_NO_COCKTAIL )
1127	1127
1128	1128	GAME( 1995, newfant, 0, comad, fantasia, driver_device, 0, ROT90, "Comad & New Japan System", "New Fantasia (1995 copyright)", GAME_NO_COCKTAIL ) // the only difference between the two is the gfx rom containing the copyright
1129	1129	GAME( 1994, newfanta, newfant, comad, fantasia, driver_device, 0, ROT90, "Comad & New Japan System", "New Fantasia (1994 copyright)", GAME_NO_COCKTAIL )

trunk/src/mame/drivers/mazerbla.c
r32760	r32761
1411	1411
1412	1412	save_item(NAME(m_vsb_ls273));
1413	1413	save_item(NAME(m_soundlatch));
1414
	1414
1415	1415	machine().save().register_postload(save_prepost_delegate(FUNC(mazerbla_state::rom_bank_select), this));
1416	1416	}
1417	1417

trunk/src/mame/mame.lst
r32760	r32761
48	48	pacmanf // hack
49	49	puckmod // (c) 1981 Namco
50	50	pacmod // (c) 1981 Midway
51		pacmanjpm // bootleg
	51	pacmanjpm // bootleg
52	52	newpuc2 // hack
53	53	newpuc2b // hack
54	54	pacuman // bootleg
r32760	r32761
103	103	mspacmanbg // bootleg
104	104	mspacmanbgd // bootleg
105	105	mspacmanbcc // bootleg
106		mspacmanblt // bootleg
	106	mspacmanblt // bootleg
107	107	woodpeck // (c) 1981 Amenip (Palcom Queen River)
108	108	woodpeca // (c) 1981 Amenip Nova Games Ltd.
109	109	mspacmab // bootleg
r32760	r32761
136	136	cannonbp // hack
137	137	superabc // hack
138	138	superabco // hack
139		pengojpm // bootleg
140		pengopac // bootleg
	139	pengojpm // bootleg
	140	pengopac // bootleg
141	141
142	142	// S2650 Pacman Kits
143	143	drivfrcp // (c) 1984 Shinkai Inc. (Magic Eletronics Inc. license)
r32760	r32761
333	333	froggers // bootleg
334	334	frogf // bootleg
335	335	quaak // bootleg
336		froggeram // bootleg
	336	froggeram // bootleg
337	337	amidars // GX337 (c) 1982 Konami
338	338	triplep // (c) 1982 KKI / made by Sanritsu?
339	339	triplepa // (c) 1982 KKI / made by Sanritsu?
r32760	r32761
471	471	itaten // (c) 1984 + Alice
472	472	friskyt // (c) 1981
473	473	friskyta // (c) 1981
474		friskytb // (c) 1981
	474	friskytb // (c) 1981
475	475	radrad // (c) 1982 Nichibutsu USA
476	476	seicross // (c) 1984 + Alice
477	477	sectrzon // (c) 1984 + Alice
r32760	r32761
693	693	phoenixt // (c) 1980 Taito
694	694	phoenixj // (c) 1980 Taito
695	695	phoenix3 // bootleg
696		phoenixdal // bootleg D&L (No copyright/title)
	696	phoenixdal // bootleg D&L (No copyright/title)
697	697	phoenixc // bootleg
698	698	phoenixc2 // bootleg
699	699	phoenixc3 // bootleg
r32760	r32761
810	810	gaplus // (c) 1984
811	811	gaplusa // (c) 1984
812	812	gaplusd // (c) 1984
813		gaplust // (c) 1984
	813	gaplust // (c) 1984
814	814	galaga3 // (c) 1984
815	815	galaga3a // (c) 1984
816	816	galaga3b // (c) 1984
r32760	r32761
876	876	quester // (c) 1987 (Japan)
877	877	questers // (c) 1987 (Japan)
878	878	pacmania // (c) 1987
879		pacmaniao // (c) 1987
	879	pacmaniao // (c) 1987
880	880	pacmaniaj // (c) 1987 (Japan)
881	881	galaga88 // (c) 1987
882	882	galaga88a // (c) 1987
r32760	r32761
1166	1166	cheekyms // 8004 (c) [1980?]
1167	1167	zerohour // 8011 (c) Universal
1168	1168	zerohoura // 8011 (c) Universal
1169		zerohouri //
	1169	zerohouri //
1170	1170	redclash // (c) 1981 Tehkan
1171	1171	redclasha // (c) 1981 Tehkan
1172	1172	redclashk // (c) Kaneko (bootleg?)
r32760	r32761
1244	1244	marioo // (c) 1983 Nintendo of America
1245	1245	marioj // (c) 1983 Nintendo
1246	1246	masao // bootleg
1247		mariobl // bootleg
1248		dkong3abl //
	1247	mariobl // bootleg
	1248	dkong3abl //
1249	1249	pestplce // bootleg on donkey kong hw
1250	1250	spclforc // (c) 1985 Senko Industries (Magic Eletronics Inc. license)
1251	1251	spcfrcii // (c) 1985 Senko Industries (Magic Eletronics Inc. license)
r32760	r32761
1765	1765	mototour // (c) 1983 Tecfri
1766	1766	shtrider // (c) 1984 Seibu Kaihatsu
1767	1767	shtridera // (c) 1984 Seibu Kaihatsu
1768		shtriderb // bootleg
	1768	shtriderb // bootleg
1769	1769	wilytowr // M63 (c) 1984
1770	1770	atomboy // M63 (c) 1985 Irem + Memetron license
1771	1771	atomboya // M63 (c) 1985 Irem + Memetron license
r32760	r32761
2133	2133	arkatour // ??? (c) 1987 Taito America Corporation + Romstar license (US)
2134	2134	tetrsark // ??? (c) D.R.Korea
2135	2135	hexa // D. R. Korea
2136		hexaa //
	2136	hexaa //
2137	2137	brixian // (c) 1993 Cheil Computer System
2138	2138	sqix // B03 1987
2139	2139	sqixr1 // B03 1987
r32760	r32761
2678	2678	3in1semi // (c) 1998 SemiCom
2679	2679	moremore // (c) 1999 SemiCom + Exit
2680	2680	moremorp // (c) 1999 SemiCom + Exit
2681		suhosong // (c) 199? SemiCom
	2681	suhosong // (c) 199? SemiCom
2682	2682	4in1boot // (c) 2002 KISoft (includes hacks of Semicom games + Snowbros)
2683	2683
2684	2684	// More Toaplan Games
r32760	r32761
3039	3039	tigeroadb // bootleg
3040	3040	f1dream // 4/1988 (c) 1988 + Romstar
3041	3041	f1dreamb // bootleg
3042		f1dreamba // bootleg
	3042	f1dreamba // bootleg
3043	3043	1943kai // 6/1988 (c) 1987 (Japan)
3044	3044	lastduel // 7/1988 (c) 1988 (US)
3045	3045	lastduelo // 7/1988 (c) 1988 (US)
r32760	r32761
3364	3364	sfzb // 09/11/1995 (c) 1995 (Brazil)
3365	3365	sfzbr1 // 27/07/1995 (c) 1995 (Brazil)
3366	3366	mmancp2u // 06/10/1995 (c) 1995 (USA)
3367		mmancp2ur1 // 26/09/1995 (c) 1995 (USA)
	3367	mmancp2ur1 // 26/09/1995 (c) 1995 (USA)
3368	3368	rmancp2j // 22/09/1995 (c) 1995 (Japan)
3369	3369	msh // 24/10/1995 (c) 1995 (Euro)
3370	3370	mshu // 24/10/1995 (c) 1995 (USA)
r32760	r32761
4687	4687	astormbl // BOOTLEG
4688	4688	astormb2 // BOOTLEG
4689	4689	shdancbl // BOOTLEG
4690		shdancbla // BOOTLEG
	4690	shdancbla // BOOTLEG
4691	4691	mwalkbl // BOOTLEG
4692	4692
4693	4693
r32760	r32761
4812	4812	spidmanu // 1991.09 Spiderman (US)
4813	4813	spidmanj // 1991.09 Spiderman (Japan)
4814	4814	f1en // 1991.?? F-1 Exhaust Note (World)
4815		f1enu // 1992.01 F-1 Exhaust Note (US)
	4815	f1enu // 1992.01 F-1 Exhaust Note (US)
4816	4816	// 1991.11 F-1 Exhaust Note (Japan)
4817	4817	arabfgt // 1992.?? Arabian Fight (World)
4818	4818	arabfgtu // 1992.03 Arabian Fight (US)
r32760	r32761
5423	5423	mushik2e // 2005.?? Mushiking The King Of Beetles II ENG (Ver. 1.001)
5424	5424	mushi2ea // 2005.?? Mushiking The King Of Beetles II ENG (Ver. 2.001)
5425	5425	// 2005.?? MushiKing The King Of Beetle III
5426		mushi2k5 // 2005.?? MushiKing The King Of Beetle 2K5 1st
	5426	mushi2k5 // 2005.?? MushiKing The King Of Beetle 2K5 1st
5427	5427	kurucham // 2006.03 Kurukuru Chameleon
5428	5428	trgheart // 2006.05 Trigger Heart Exelica (Rev A)
5429	5429	zunou // 2006.07 Touch de Zunou
r32760	r32761
5482	5482	kingrt66 // 2002.02 The King of Route 66 (Rev A)
5483	5483	// 2002.02.14 Initial D Arcade Stage (Japan)
5484	5484	initd // 2002.03 Initial D Arcade Stage (Japan) (Rev B)
5485		initdo // 2002.03 Initial D Arcade Stage (Japan)
	5485	initdo // 2002.03 Initial D Arcade Stage (Japan)
5486	5486	// 2002.06 World Club Champion Football Serie A 2001-2002
5487	5487	soulsurf // 2002.07 Soul Surfer
5488	5488	initdexp // 2002.07.18 Initial D Arcade Stage (Export) (Rev A)
r32760	r32761
5893	5893	chelnov // (c) 1988 Data East USA (World)
5894	5894	chelnovu // (c) 1988 Data East USA (US)
5895	5895	chelnovj // (c) 1988 Data East Corporation (Japan)
5896		chelnovjbl // bootleg
5897		chelnovjbla // bootleg
	5896	chelnovjbl // bootleg
	5897	chelnovjbla // bootleg
5898	5898	// the following ones all run on similar hardware
5899	5899	hbarrel // (c) 1987 Data East USA (US)
5900	5900	hbarrelw // (c) 1987 Data East Corporation (World)
r32760	r32761
6356	6356	simpsons4pa // GX072 (c) 1991
6357	6357	simpsons2p // GX072 (c) 1991
6358	6358	simpsons2p2 // GX072 (c) 1991
6359		simpsons2p3 // GX072 (c) 1991
	6359	simpsons2p3 // GX072 (c) 1991
6360	6360	simpsons2pa // GX072 (c) 1991 (Asia)
6361	6361	simpsons2pj // GX072 (c) 1991 (Japan)
6362	6362	esckids // GX975 (c) 1991 (Asia)
r32760	r32761
6364	6364	vendetta // GX081 (c) 1991 (World)
6365	6365	vendettar // GX081 (c) 1991 (World)
6366	6366	vendetta2p // GX081 (c) 1991 (World)
6367		vendetta2peba // GX081 (c) 1991 (World)
	6367	vendetta2peba // GX081 (c) 1991 (World)
6368	6368	vendetta2pu // GX081 (c) 1991 (Asia)
6369	6369	vendetta2pd // GX081 (c) 1991 (Asia)
6370	6370	vendettaj // GX081 (c) 1991 (Japan)
r32760	r32761
7936	7936	tdragon // (c) 1991 NMK / Tecmo
7937	7937	tdragon1 // (c) 1991 NMK / Tecmo
7938	7938	hachamf // (c) 1991 NMK
7939		hachamfb // bootleg
	7939	hachamfb // bootleg
7940	7940	macross // (c) 1992 Banpresto
7941	7941	riot // (c) 1992 NMK
7942	7942	gunnail // (c) 1993 NMK / Tecmo
r32760	r32761
8345	8345	goodejana // (c) 1991 Seibu/Tecmo
8346	8346
8347	8347	raiden2 // (c) 1993 Seibu Kaihatsu + Fabtek license
8348		raiden2u // (c) 1993 Seibu Kaihatsu + Fabtek license
	8348	raiden2u // (c) 1993 Seibu Kaihatsu + Fabtek license
8349	8349	raiden2hk // (c) 1993 Seibu Kaihatsu + Metrotainment license
8350	8350	raiden2j // (c) 1993 Seibu Kaihatsu
8351	8351	raiden2i // (c) 1993 Seibu Kaihatsu
r32760	r32761
8354	8354	raiden2eu // (c) 1993 Seibu Kaihatsu + Fabtek license
8355	8355	raiden2eua // (c) 1993 Seibu Kaihatsu + Fabtek license
8356	8356	raiden2nl // (c) 1993 Seibu Kaihatsu
8357		raiden2g // (c) 1993 Seibu Kaihatsu + Tuning license
8358		raiden2dx // (c) 1993 Seibu Kaihatsu
	8357	raiden2g // (c) 1993 Seibu Kaihatsu + Tuning license
	8358	raiden2dx // (c) 1993 Seibu Kaihatsu
8359	8359
8360	8360	raidendx // (c) 1994 Seibu Kaihatsu
8361	8361	raidendxk // (c) 1994 Seibu Kaihatsu
r32760	r32761
8377	8377
8378	8378	// Newer V33 PCB with COP3 protection
8379	8379	r2dx_v33 // (c) 1996 Seibu Kaihatsu
8380		r2dx_v33_r2 // (c) 1996 Seibu Kaihatsu
	8380	r2dx_v33_r2 // (c) 1996 Seibu Kaihatsu
8381	8381	nzeroteam // (c) 1997 Seibu Kaihatsu
8382	8382	zerotm2k // (c) 2000 Seibu Kaihatsu
8383	8383
r32760	r32761
8687	8687	tengaij // (c) 1996
8688	8688	// Semicom games on "Psikyo 68020"-like hardware
8689	8689	baryon // (c) 1997 SemiCom
8690		baryona // (c) 1997 SemiCom
	8690	baryona // (c) 1997 SemiCom
8691	8691	dreamwld // (c) 2000 SemiCom
8692	8692	rolcrush // (c) 1999 Trust
8693	8693
r32760	r32761
9061	9061	nratechu // (c) 1996 Seta
9062	9062	dcrown // 199? unknown
9063	9063	dcrowna // 199? unknown
9064		gostop // 2001 Visco
	9064	gostop // 2001 Visco
9065	9065	// R3000 + ST-0016
9066	9066	srmp5 // (c) 199? Seta
9067	9067	speglsht // (c) 1994 Seta
r32760	r32761
9223	9223	fantasiaa // (c) 1994 Comad & New Japan System
9224	9224	fantasiab // (c) 1994 Comad & New Japan System
9225	9225	supmodel // (c) 1994 Comad & New Japan System
9226		fantasian //
	9226	fantasian //
9227	9227	newfant // (c) 1994 Comad & New Japan System
9228	9228	newfanta // (c) 1995 Comad & New Japan System
9229	9229	fantsy95 // (c) 1995 Hi-max Technology Inc.
r32760	r32761
9708	9708	orlegendc //
9709	9709	orlegendca //
9710	9710	orlegend111c //
9711		orlegend111t //
	9711	orlegend111t //
9712	9712	orlegend105k //
9713	9713	drgw2 // (c) 1997 Dragon World 2
9714	9714	dw2v100x //
r32760	r32761
10312	10312	eggventr2 // (c) 1997 The Game Room
10313	10313	eggventra // (c) 1997 The Game Room (Allied Leisure license)
10314	10314	eggventrd // (c) 1997 The Game Room
10315		hostinv // (c) 1998 The Game Room
	10315	hostinv // (c) 1998 The Game Room
10316	10316	calchase // (c) 1999 The Game Room
10317		eggsplc // (c) 2002 The Game Room
	10317	eggsplc // (c) 2002 The Game Room
10318	10318	ripribit // (c) 1997 LAI Games
10319	10319	cfarm // (c) 1999 LAI Games
10320	10320	cclownz // (c) 1999 LAI Games

trunk/src/mame/audio/mario.c
r32760	r32761
414	414
415	415	void mario_state::sound_start()
416	416	{
417
418	417	device_t *audiocpu = machine().device("audiocpu");
419	418
420	419	if (!audiocpu) return;

trunk/src/mame/audio/cclimber.h
r32760	r32761
41	41	DECLARE_WRITE8_MEMBER( sample_rate_w );
42	42	DECLARE_WRITE8_MEMBER( sample_volume_w );
43	43	DECLARE_WRITE8_MEMBER( sample_select_w );
44
	44
45	45	SAMPLES_START_CB_MEMBER( sh_start );
46	46
47	47	protected:
r32760	r32761
50	50	virtual machine_config_constructor device_mconfig_additions() const;
51	51
52	52	void play_sample(int start,int freq,int volume);
53
	53
54	54	private:
55	55	INT16 m_sample_buf; / buffer to decode samples at run time */
56	56	int m_sample_num;

trunk/src/mame/audio/leland.c
r32760	r32761
257	257	save_item(NAME(m_ext_active));
258	258	save_item(NAME(m_dac_sample));
259	259	save_item(NAME(m_dac_volume));
260
	260
261	261	// zerofill
262	262	m_peripheral = 0;
263	263	m_last_control = 0;
r32760	r32761
566	566	if (ACCESSING_BITS_0_7)
567	567	dac_w(space, 1, data, mem_mask);
568	568	return;
569
	569
570	570	default:
571	571	break;
572	572	}
r32760	r32761
599	599	m_ext_stop <<= 4;
600	600	if (LOG_EXTERN) logerror("External DAC stop = %05X\n", m_ext_stop);
601	601	return;
602
	602
603	603	default:
604	604	break;
605	605	}

trunk/src/mame/machine/st0016.c
r32760	r32761
9	9
10	10	static ADDRESS_MAP_START(st0016_cpu_internal_map, AS_PROGRAM, 8, st0016_cpu_device)
11	11	AM_RANGE(0xc000, 0xcfff) AM_READ(st0016_sprite_ram_r) AM_WRITE(st0016_sprite_ram_w)
12		AM_RANGE(0xd000, 0xdfff) AM_READ(st0016_sprite2_ram_r) AM_WRITE(st0016_sprite2_ram_w)
	12	AM_RANGE(0xd000, 0xdfff) AM_READ(st0016_sprite2_ram_r) AM_WRITE(st0016_sprite2_ram_w)
13	13	AM_RANGE(0xea00, 0xebff) AM_READ(st0016_palette_ram_r) AM_WRITE(st0016_palette_ram_w)
14	14	AM_RANGE(0xec00, 0xec1f) AM_READ(st0016_character_ram_r) AM_WRITE(st0016_character_ram_w)
15	15	AM_RANGE(0xe900, 0xe9ff) AM_DEVREADWRITE("stsnd", st0016_device, st0016_snd_r, st0016_snd_w) /* sound regs 8 x $20 bytes, see notes */
r32760	r32761
29	29
30	30	st0016_cpu_device::st0016_cpu_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
31	31	: z80_device(mconfig, ST0016_CPU, "ST0016", tag, owner, clock, "st0016_cpu", __FILE__),
32		st0016_game(-1),
33		st0016_spr_bank(0),
34		st0016_spr2_bank(0),
35		st0016_pal_bank(0),
36		st0016_char_bank(0),
37		spr_dx(0),
38		spr_dy(0),
39		st0016_ramgfx(0),
40
41		m_io_space_config("io", ENDIANNESS_LITTLE, 8, 16, 0, ADDRESS_MAP_NAME(st0016_cpu_internal_io_map)),
42		m_space_config("regs", ENDIANNESS_LITTLE, 8, 16, 0, ADDRESS_MAP_NAME(st0016_cpu_internal_map)),
	32	st0016_game(-1),
	33	st0016_spr_bank(0),
	34	st0016_spr2_bank(0),
	35	st0016_pal_bank(0),
	36	st0016_char_bank(0),
	37	spr_dx(0),
	38	spr_dy(0),
	39	st0016_ramgfx(0),
43	40
	41	m_io_space_config("io", ENDIANNESS_LITTLE, 8, 16, 0, ADDRESS_MAP_NAME(st0016_cpu_internal_io_map)),
	42	m_space_config("regs", ENDIANNESS_LITTLE, 8, 16, 0, ADDRESS_MAP_NAME(st0016_cpu_internal_map)),
44	43
45		m_screen(*this, ":screen"),
46		m_gfxdecode(*this, "gfxdecode"),
47		m_palette(*this, "palette")
48	44
	45	m_screen(*this, ":screen"),
	46	m_gfxdecode(*this, "gfxdecode"),
	47	m_palette(*this, "palette")
	48
49	49	{
50	50	for (int i = 0; i < 0xc0; i++)
51	51	st0016_vregs[i] = 0;
r32760	r32761
302	302	UINT32 srcadr=(st0016_vregs[0xa0]\|(st0016_vregs[0xa1]<<8)\|(st0016_vregs[0xa2]<<16))<<1;
303	303	UINT32 dstadr=(st0016_vregs[0xa3]\|(st0016_vregs[0xa4]<<8)\|(st0016_vregs[0xa5]<<16))<<1;
304	304	UINT32 length=((st0016_vregs[0xa6]\|(st0016_vregs[0xa7]<<8)\|((st0016_vregs[0xa8]&0x1f)<<16))+1)<<1;
305
	305
306	306	// todo : dma callback so macs_cart_slot can be local to MACs driver?
307	307
308	308	UINT32 srclen = (memregion(":maincpu")->bytes());
r32760	r32761
354	354	o - sublist offset (*8 to get real offset)
355	355	f - end of list flag
356	356	x,y - sprite coords
357
	357
358	358	(complete guess)
359	359	g - use tile sizes specified in list (global / fixed ones if not set?) (gostop)
360	360	X = global X size?
r32760	r32761
455	455	sx += x;
456	456	sy += y;
457	457	color = st0016_spriteram[offset + 2] & 0x3f;
458
	458
459	459	if (use_sizes)
460	460	{
461	461	lx = (st0016_spriteram[offset + 5] >> 2) & 3;
r32760	r32761
469	469	}
470	470
471	471	/*
472		if(plx \|ply) //parent
473		{
474		lx=plx;
475		ly=ply;
476		}
477		*/
	472	if(plx \|ply) //parent
	473	{
	474	lx=plx;
	475	ly=ply;
	476	}
	477	*/
478	478
479	479	flipx = st0016_spriteram[offset + 3] & 0x80;
480	480	flipy = st0016_spriteram[offset + 3] & 0x40;
r32760	r32761
737	737	st0016_draw_screen(screen, bitmap, cliprect);
738	738	return 0;
739	739	}
740

trunk/src/mame/machine/st0016.h
r32760	r32761
53	53	DECLARE_WRITE8_MEMBER(st0016_vregs_w);
54	54	DECLARE_READ8_MEMBER(soundram_read);
55	55
56
	56
57	57	void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect);
58	58	void st0016_save_init();
59	59	void draw_bgmap(bitmap_ind16 &bitmap,const rectangle &cliprect, int priority);

trunk/src/mame/machine/atari.c
r32760	r32761
167	167	case pokey_device::POK_KEY_SHIFT:
168	168	// button 2 from joypads
169	169	ipt = m_djoy_b->read() & (0x10 << ((k543210 >> 3) & 0x03));
170		ret \|= !ipt ? 0x02 : 0;
	170	ret \|= !ipt ? 0x02 : 0;
171	171	break;
172	172	}
173	173

trunk/src/mame/machine/inder_vid.c
r32760	r32761
90	90	MCFG_CPU_PROGRAM_MAP(megaphx_tms_map)
91	91	MCFG_TMS340X0_HALT_ON_RESET(TRUE) /* halt on reset */
92	92	MCFG_TMS340X0_PIXEL_CLOCK(XTAL_40MHz/12) /* pixel clock */
93		MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
	93	MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
94	94	MCFG_TMS340X0_SCANLINE_RGB32_CB(inder_vid_device, scanline) /* scanline updater (RGB32) */
95	95	MCFG_TMS340X0_OUTPUT_INT_CB(WRITELINE(inder_vid_device, m68k_gen_int))
96	96	MCFG_TMS340X0_TO_SHIFTREG_CB(inder_vid_device, to_shiftreg) /* write to shiftreg function */

trunk/src/mame/machine/inder_vid.h
r32760	r32761
29	29	required_shared_ptr<UINT16> m_vram;
30	30	required_device<palette_device> m_palette;
31	31	required_device<tms34010_device> m_tms;
32
	32
33	33	DECLARE_WRITE_LINE_MEMBER(m68k_gen_int);
34	34
35	35	int m_shiftfull; // this might be a driver specific hack for a TMS bug.
r32760	r32761
41	41	virtual machine_config_constructor device_mconfig_additions() const;
42	42	virtual void device_start();
43	43	virtual void device_reset();
44
	44
45	45	private:
46	46	};
47	47

trunk/src/mame/machine/315_5296.c
r32760	r32761
1	1	/**********************************************************************
2	2
3	3	Sega 315-5296 I/O chip
4
	4
5	5	Sega 100-pin QFP, with 8 bidirectional I/O ports, and 3 output pins.
6	6	It also has chip select(/FMCS) and clock(CKOT) for a peripheral device.
7	7	Commonly used from the late 80s up until Sega Model 2.
r32760	r32761
68	68	m_in_pf_cb.resolve_safe(0xff); m_in_port_cb[5] = &m_in_pf_cb;
69	69	m_in_pg_cb.resolve_safe(0xff); m_in_port_cb[6] = &m_in_pg_cb;
70	70	m_in_ph_cb.resolve_safe(0xff); m_in_port_cb[7] = &m_in_ph_cb;
71
	71
72	72	m_out_pa_cb.resolve_safe(); m_out_port_cb[0] = &m_out_pa_cb;
73	73	m_out_pb_cb.resolve_safe(); m_out_port_cb[1] = &m_out_pb_cb;
74	74	m_out_pc_cb.resolve_safe(); m_out_port_cb[2] = &m_out_pc_cb;
r32760	r32761
77	77	m_out_pf_cb.resolve_safe(); m_out_port_cb[5] = &m_out_pf_cb;
78	78	m_out_pg_cb.resolve_safe(); m_out_port_cb[6] = &m_out_pg_cb;
79	79	m_out_ph_cb.resolve_safe(); m_out_port_cb[7] = &m_out_ph_cb;
80
	80
81	81	m_out_cnt0_cb.resolve_safe(); m_out_cnt_cb[0] = &m_out_cnt0_cb;
82	82	m_out_cnt1_cb.resolve_safe(); m_out_cnt_cb[1] = &m_out_cnt1_cb;
83	83	m_out_cnt2_cb.resolve_safe(); m_out_cnt_cb[2] = &m_out_cnt2_cb;
84
	84
85	85	// register for savestates
86	86	save_item(NAME(m_output_latch));
87	87	save_item(NAME(m_cnt));
r32760	r32761
96	96	{
97	97	// all ports are set to input
98	98	m_dir = 0;
99
	99
100	100	// clear output ports
101	101	memset(m_output_latch, 0, sizeof(m_output_latch));
102	102	m_cnt = 0;
r32760	r32761
113	113	READ8_MEMBER( sega_315_5296_device::read )
114	114	{
115	115	offset &= 0x3f;
116
	116
117	117	switch (offset)
118	118	{
119	119	// port A to H
r32760	r32761
121	121	// if the port is configured as an output, return the last thing written
122	122	if (m_dir & 1 << offset)
123	123	return m_output_latch[offset];
124
	124
125	125	// otherwise, return an input port
126	126	return (*m_in_port_cb[offset])(offset);
127
	127
128	128	// 'SEGA' protection
129	129	case 0x8:
130	130	return 'S';
r32760	r32761
142	142	// port direction register & mirror
143	143	case 0xd: case 0xf:
144	144	return m_dir;
145
	145
146	146	default:
147	147	break;
148	148	}
149
	149
150	150	return 0xff;
151	151	}
152	152
r32760	r32761
165	165
166	166	m_output_latch[offset] = data;
167	167	break;
168
	168
169	169	// CNT register
170	170	case 0xe:
171	171	// d0-2: CNT0-2 output pins
r32760	r32761
173	173	// no effect on the output level of CNT2.
174	174	for (int i = 0; i < 3; i++)
175	175	(*m_out_cnt_cb[i])(data >> i & 1);
176
	176
177	177	// d3: CNT2 output mode (1= Clock output, 0= Programmable output)
178	178	// d4,5: CNT2 clock divider (0= CLK/4, 1= CLK/8, 2= CLK/16, 3= CLK/2)
179	179	// d6,7: CKOT clock divider (0= CLK/4, 1= CLK/8, 2= CLK/16, 3= CLK/2)
r32760	r32761
189	189	if ((m_dir ^ data) & (1 << i))
190	190	(*m_out_port_cb[i])((offs_t)i, (data & 1 << i) ? m_output_latch[i] : 0);
191	191	}
192
	192
193	193	m_dir = data;
194	194	break;
195
	195
196	196	default:
197	197	break;
198	198	}

trunk/src/mame/machine/seicop.c
r32760	r32761
3	3	OLD Seibu Cop simulation code.
4	4
5	5	this is currently only used by the Seibu Cup Soccer BOOTLEG
6
	6
7	7	*/
8	8
9	9	/********************************************************************************************
r32760	r32761
25	25	m_cop_mcu_ram(NULL),
26	26	m_raiden2cop(*this, ":raiden2cop")
27	27	{
28
29
30	28	}
31	29
32	30	#define seibu_cop_log logerror
r32760	r32761
101	99	break;
102	100	}
103	101
104
	102
105	103	case (0x500/2):
106	104	case (0x502/2):
107	105	case (0x504/2):
r32760	r32761
152	150
153	151	space.write_dword(m_raiden2cop->cop_regs[0] + 4 + offs, npos);
154	152	space.write_word(m_raiden2cop->cop_regs[0] + 0x1c + offs, space.read_word(m_raiden2cop->cop_regs[0] + 0x1c + offs) + delta);
155
	153
156	154	break;
157	155	}
158	156	case 0x130e:
r32760	r32761
199	197	break;
200	198	}
201	199	break;
202
	200
203	201	/TODO: kludge on x-axis./
204	202	case (0x660/2): { state->m_scrollram16[0] = m_cop_mcu_ram[offset] - 0x1f0; break; }
205	203	case (0x662/2): { state->m_scrollram16[1] = m_cop_mcu_ram[offset]; break; }
r32760	r32761
218	216	}
219	217	}
220	218	}
221
222

trunk/src/mame/machine/seicop.h
r32760	r32761
30	30
31	31	#define MCFG_SEIBU_COP_ADD(_tag) \
32	32	MCFG_DEVICE_ADD(_tag, SEIBU_COP_BOOTLEG, 0)
33

trunk/src/mame/machine/nmk004.c
r32760	r32761
25	25	{
26	26	// bit 0x08 toggles frequently but is connected to nothing?
27	27
28		// bit 0x01 is set to reset the 68k
	28	// bit 0x01 is set to reset the 68k
29	29	m_systemcpu->set_input_line(INPUT_LINE_RESET, (data & 1) ? ASSERT_LINE : CLEAR_LINE);
30	30	}
31	31

trunk/src/mame/machine/asic65.c
r32760	r32761
251	251	}
252	252
253	253	int command = (m_command < MAX_COMMANDS) ? command_map[m_asic65_type][m_command] : OP_UNKNOWN;
254
	254
255	255	/* update results */
256	256	switch (command)
257	257	{

trunk/src/mame/machine/vectrex.c
r32760	r32761
328	328	m_maincpu->space(AS_PROGRAM).install_read_handler(0x0000, 0x7fff, read8_delegate(FUNC(vectrex_cart_slot_device::read_rom),(vectrex_cart_slot_device*)m_cart));
329	329
330	330	// setup 3d imager and refresh timer
331
	331
332	332	// If VIA T2 starts, reset refresh timer. This is the best strategy for most games.
333	333	m_reset_refresh = 1;
334	334	m_imager_angles = narrow_escape_angles;
335
	335
336	336	// let's do this 3D detection
337	337	switch (m_cart->get_vec3d())
338	338	{

trunk/src/mame/machine/kaneko_toybox.h
r32760	r32761
353	353	UINT16 m_mcu_com[4];
354	354	int m_gametype;
355	355	int m_tabletype;
356
	356
357	357	void mcu_com_w(offs_t offset, UINT16 data, UINT16 mem_mask, int _n_);
358	358	void decrypt_rom();
359	359	void handle_04_subcommand(UINT8 mcu_subcmd, UINT16 *mcu_ram);
r32760	r32761
366	366
367	367	#define MCFG_TOYBOX_TABLE_TYPE(_type) \
368	368	kaneko_toybox_device::set_table(*device, _type);
369
	369
370	370	#define MCFG_TOYBOX_GAME_TYPE(_type) \
371	371	kaneko_toybox_device::set_game_type(*device, _type);

trunk/src/mame/machine/awboard.h
r32760	r32761
22	22	DECLARE_WRITE16_MEMBER(mpr_first_file_index_w); // 5f7010
23	23	DECLARE_WRITE16_MEMBER(mpr_file_offsetl_w); // 5f7014
24	24	DECLARE_WRITE16_MEMBER(mpr_file_offseth_w); // 5f7018
25		DECLARE_READ16_MEMBER(adj_offset_r); // 5f7080
26		DECLARE_WRITE16_MEMBER(adj_offset_w); // 5f7080
	25	DECLARE_READ16_MEMBER(adj_offset_r); // 5f7080
	26	DECLARE_WRITE16_MEMBER(adj_offset_w); // 5f7080
27	27
28	28	protected:
29	29	virtual void device_start();

trunk/src/mame/machine/model1.c
r32760	r32761
1584	1584	{ &model1_state::fsub, 2 },
1585	1585	{ &model1_state::fmul, 2 },
1586	1586	{ &model1_state::fdiv, 2 },
1587		{ NULL, 0 },
	1587	{ NULL, 0 },
1588	1588	{ &model1_state::matrix_push, 0 },
1589	1589	{ &model1_state::matrix_pop, 0 },
1590	1590	{ &model1_state::matrix_write, 12 },
1591	1591	{ &model1_state::clear_stack, 0 },
1592		{ NULL, 0 },
	1592	{ NULL, 0 },
1593	1593	{ &model1_state::anglev, 2 },
1594		{ NULL, 0 },
1595		{ NULL, 0 },
	1594	{ NULL, 0 },
	1595	{ NULL, 0 },
1596	1596	{ &model1_state::track_select, 1 },
1597	1597	{ &model1_state::f14, 4 },
1598	1598	{ &model1_state::anglep, 4 },
r32760	r32761
1604	1604	{ &model1_state::matrix_rotx, 1 },
1605	1605	{ &model1_state::matrix_roty, 1 },
1606	1606	{ &model1_state::matrix_rotz, 1 },
1607		{ NULL, 0 },
	1607	{ NULL, 0 },
1608	1608	{ &model1_state::track_read_quad, 1 },
1609		{ NULL, 0 },
	1609	{ NULL, 0 },
1610	1610	{ &model1_state::transform_point, 3 },
1611	1611	{ &model1_state::fsin_m1, 1 },
1612	1612	{ &model1_state::fcos_m1, 1 },
r32760	r32761
1614	1614	{ &model1_state::fcosm_m1, 2 },
1615	1615	{ &model1_state::distance3, 6 },
1616	1616
1617		{ NULL, 0 }, /* 0x20 */
1618		{ NULL, 0 },
1619		{ NULL, 0 },
1620		{ NULL, 0 },
	1617	{ NULL, 0 }, /* 0x20 */
	1618	{ NULL, 0 },
	1619	{ NULL, 0 },
	1620	{ NULL, 0 },
1621	1621	{ &model1_state::acc_set, 1 },
1622	1622	{ &model1_state::acc_get, 0 },
1623	1623	{ &model1_state::acc_add, 1 },
r32760	r32761
1629	1629	{ &model1_state::f44, 1 },
1630	1630	{ &model1_state::f45, 1 },
1631	1631	{ &model1_state::vlength, 3 },
1632		{ NULL, 0 },
	1632	{ NULL, 0 },
1633	1633
1634	1634	{ &model1_state::track_read_info, 1 }, /* 0x30 */
1635	1635	{ &model1_state::colbox_set, 12 },
1636	1636	{ &model1_state::colbox_test, 3 },
1637		{ NULL, 0 },
1638		{ NULL, 0 },
1639		{ NULL, 0 },
	1637	{ NULL, 0 },
	1638	{ NULL, 0 },
	1639	{ NULL, 0 },
1640	1640	{ &model1_state::track_lookup, 4 },
1641		{ NULL, 0 },
1642		{ NULL, 0 },
1643		{ NULL, 0 },
1644		{ NULL, 0 },
1645		{ NULL, 0 },
1646		{ NULL, 0 },
1647		{ NULL, 0 },
1648		{ NULL, 0 },
1649		{ NULL, 0 },
	1641	{ NULL, 0 },
	1642	{ NULL, 0 },
	1643	{ NULL, 0 },
	1644	{ NULL, 0 },
	1645	{ NULL, 0 },
	1646	{ NULL, 0 },
	1647	{ NULL, 0 },
	1648	{ NULL, 0 },
	1649	{ NULL, 0 },
1650	1650
1651	1651	{ &model1_state::col_setcirc, 3 }, /* 0x40 */
1652	1652	{ &model1_state::col_testpt, 2 },
1653		{ NULL, 0 },
	1653	{ NULL, 0 },
1654	1654	{ &model1_state::distance, 4 },
1655		{ NULL, 0 },
1656		{ NULL, 0 },
1657		{ NULL, 0 },
	1655	{ NULL, 0 },
	1656	{ NULL, 0 },
	1657	{ NULL, 0 },
1658	1658	{ &model1_state::car_move, 4 },
1659	1659	{ &model1_state::cpa, 12 },
1660		{ NULL, 0 },
	1660	{ NULL, 0 },
1661	1661	{ &model1_state::vmat_store, 1 },
1662	1662	{ &model1_state::vmat_restore, 1 },
1663		{ NULL, 0 },
	1663	{ NULL, 0 },
1664	1664	{ &model1_state::vmat_mul, 2 },
1665	1665	{ &model1_state::vmat_read, 1 },
1666	1666	{ &model1_state::matrix_unrot, 0 },
1667	1667
1668	1668	{ &model1_state::f80, 0 }, /* 0x50 */
1669		{ NULL, 0 },
	1669	{ NULL, 0 },
1670	1670	{ &model1_state::matrix_rtrans, 0 },
1671		{ NULL, 0 },
	1671	{ NULL, 0 },
1672	1672	{ &model1_state::vmat_save, 1 },
1673	1673	{ &model1_state::vmat_load, 1 },
1674	1674	{ &model1_state::ram_setadr, 1 },
1675	1675	{ &model1_state::groundbox_test, 3 },
1676		{ NULL, 0 },
	1676	{ NULL, 0 },
1677	1677	{ &model1_state::f89, 4 },
1678		{ NULL, 0 },
1679		{ NULL, 0 },
	1678	{ NULL, 0 },
	1679	{ NULL, 0 },
1680	1680	{ &model1_state::f92, 4 },
1681	1681	{ &model1_state::f93, 1 },
1682	1682	{ &model1_state::f94, 1 },
r32760	r32761
1702	1702	{ &model1_state::fsub, 2 },
1703	1703	{ &model1_state::fmul, 2 },
1704	1704	{ &model1_state::fdiv, 2 },
1705		{ NULL, 0 },
	1705	{ NULL, 0 },
1706	1706	{ &model1_state::matrix_push, 0 },
1707	1707	{ &model1_state::matrix_pop, 0 },
1708	1708	{ &model1_state::matrix_write, 12 },
r32760	r32761
1722	1722	{ &model1_state::matrix_rotx, 1 },
1723	1723	{ &model1_state::matrix_roty, 1 },
1724	1724	{ &model1_state::matrix_rotz, 1 },
1725		{ NULL, 0 },
	1725	{ NULL, 0 },
1726	1726	{ &model1_state::f24_swa, 7 },
1727		{ NULL, 0 },
	1727	{ NULL, 0 },
1728	1728	{ &model1_state::transform_point, 3 },
1729	1729	{ &model1_state::fsin_m1, 1 },
1730	1730	{ &model1_state::fcos_m1, 1 },
r32760	r32761
1732	1732	{ &model1_state::fcosm_m1, 2 },
1733	1733	{ &model1_state::distance3, 6 },
1734	1734
1735		{ NULL, 0 }, /* 0x20 */
1736		{ NULL, 0 },
	1735	{ NULL, 0 }, /* 0x20 */
	1736	{ NULL, 0 },
1737	1737	{ &model1_state::ftoi, 1 },
1738	1738	{ &model1_state::itof, 1 },
1739	1739	{ &model1_state::acc_set, 1 },
r32760	r32761
1749	1749	{ &model1_state::vlength, 3 },
1750	1750	{ &model1_state::f47, 3 },
1751	1751
1752		{ NULL, 0 }, /* 0x30 */
	1752	{ NULL, 0 }, /* 0x30 */
1753	1753	{ &model1_state::f49_swa, 6 },
1754	1754	{ &model1_state::f50_swa, 4 },
1755		{ NULL, 0 },
	1755	{ NULL, 0 },
1756	1756	{ &model1_state::f52, 0 },
1757	1757	{ &model1_state::matrix_rdir, 3 },
1758		{ NULL, 0 },
1759		{ NULL, 0 },
	1758	{ NULL, 0 },
	1759	{ NULL, 0 },
1760	1760	{ &model1_state::f56, 7 },
1761	1761	{ &model1_state::f57, 0 },
1762	1762	{ &model1_state::matrix_readt, 0 },
1763	1763	{ &model1_state::acc_geti, 0 },
1764	1764	{ &model1_state::f60, 0 },
1765		{ NULL, 0 },
1766		{ NULL, 0 },
1767		{ NULL, 0 },
1768		{ NULL, 0 },
	1765	{ NULL, 0 },
	1766	{ NULL, 0 },
	1767	{ NULL, 0 },
	1768	{ NULL, 0 },
1769	1769
1770	1770	{ &model1_state::push_and_ident, 0 }, /* 0x40 */
1771		{ NULL, 0 },
	1771	{ NULL, 0 },
1772	1772	{ &model1_state::catmull_rom, 13 }
1773	1773	};
1774	1774

trunk/src/mame/machine/raiden2cop.c
r32760	r32761
27	27	cop_latch_addr(0),
28	28	cop_latch_trigger(0),
29	29	cop_latch_value(0),
30		cop_latch_mask(0),
	30	cop_latch_mask(0),
31	31	cop_dma_v1(0),
32	32	cop_dma_v2(0),
33	33	cop_dma_mode(0),
r32760	r32761
78	78	memset(cop_func_value, 0, sizeof(UINT16)*(0x100/8));
79	79	memset(cop_func_mask, 0, sizeof(UINT16)*(0x100/8));
80	80	memset(cop_program, 0, sizeof(UINT16)*(0x100));
81
	81
82	82	memset(cop_dma_src, 0, sizeof(UINT16)*(0x200));
83	83	memset(cop_dma_dst, 0, sizeof(UINT16)*(0x200));
84	84	memset(cop_dma_size, 0, sizeof(UINT16)*(0x200));
r32760	r32761
362	362	/* search the uploaded 'trigger' table for a matching trigger*/
363	363	/* note, I don't know what the 'mask' or 'value' tables are... probably important, might determine what actually gets executed! */
364	364	/* note: Zero Team triggers macro 0x904 instead of 0x905, Seibu Cup Soccer triggers 0xe30e instead of 0xe38e. I highly doubt that AT LEAST
365		it isn't supposed to do anything, especially in the former case (it definitely NEEDS that sprites have an arc movement when they are knocked down). */
	365	it isn't supposed to do anything, especially in the former case (it definitely NEEDS that sprites have an arc movement when they are knocked down). */
366	366	// we currently pass in mask 0xff00 to look at only match the top bits, but this is wrong, only specific bits are ignored (maybe depends on the 'mask' value uploaded with each trigger?)
367	367	int matched = 0;
368	368	int command = -1;
r32760	r32761
374	374	if ((triggerval & mask) == (cop_func_trigger[i] & mask) && cop_func_trigger[i] != 0) /* cop_func_trigger[i] != 0 is just being used to prevent matching against empty / unused slots */
375	375	{
376	376	int otherlog = 1;
377
	377
378	378	// just some per-game debug code so that we have a record of exactly which triggers each game is known to use
379	379
380	380
r32760	r32761
382	382	{
383	383	// enemies often walk on the spot, bosses often walk above / below playable game area (the >>16 in the sqrt commands seems responsible)
384	384	// player doesn't walk off screen after end of level (walks on spot, different cause?)
385		if (triggerval == 0x0205 \|\| triggerval == 0x0905 \|\|
	385	if (triggerval == 0x0205 \|\| triggerval == 0x0905 \|\|
386	386	triggerval == 0x8100 \|\| triggerval == 0x8900 \|\| /* sin / cos */
387	387	triggerval == 0x138e \|\| // atan?
388	388	triggerval == 0x3bb0 \|\| // distance?
r32760	r32761
413	413
414	414	if (triggerval == 0x0205 \|\|
415	415	triggerval == 0x8100 \|\| triggerval == 0x8900 \|\| /* sin / cos */
416		triggerval == 0x138e \|\|
	416	triggerval == 0x138e \|\|
417	417	triggerval == 0x3bb0 \|\|
418	418	triggerval == 0x42c2 \|\|
419	419	triggerval == 0xa100 \|\| triggerval == 0xa900 \|\| triggerval == 0xb080 \|\| triggerval == 0xb880) /* collisions */
r32760	r32761
494	494	{
495	495	if (triggerval == 0x0205 \|\| triggerval == 0x0905 \|\|
496	496	triggerval == 0x8100 \|\| triggerval == 0x8900 \|\| /* sin / cos */
497		triggerval == 0x130e \|\| triggerval == 0x138e \|\|
	497	triggerval == 0x130e \|\| triggerval == 0x138e \|\|
498	498	triggerval == 0x2a05 \|\|
499		triggerval == 0x2208 \|\| triggerval == 0x2288 \|\|
	499	triggerval == 0x2208 \|\| triggerval == 0x2288 \|\|
500	500	triggerval == 0x338e \|\|
501		triggerval == 0x39b0 \|\| triggerval == 0x3bb0 \|\|
502		triggerval == 0x4aa0 \|\|
503		triggerval == 0x42c2 \|\|
	501	triggerval == 0x39b0 \|\| triggerval == 0x3bb0 \|\|
	502	triggerval == 0x4aa0 \|\|
	503	triggerval == 0x42c2 \|\|
504	504	triggerval == 0x5205 \|\|
505	505	triggerval == 0x5a05 \|\|
506	506	triggerval == 0x6200 \|\|
r32760	r32761
508	508	triggerval == 0xa100 \|\| triggerval == 0xa900 \|\| triggerval == 0xb100 \|\| triggerval == 0xb900 /* collisions */
509	509	)
510	510	otherlog = 0;
511		}
	511	}
512	512	else
513	513	{
514	514	otherlog = 0;
r32760	r32761
525	525
526	526	if (matched == 1)
527	527	{
528
529	528	int j;
530	529	seibu_cop_log(" Sequence: ");
531	530	for (j=0;j<0x8;j++)
r32760	r32761
554	553	command *= 8;
555	554
556	555	if (cop_program[command+0] == seq0 && cop_program[command+1] == seq1 && cop_program[command+2] == seq2 && cop_program[command+3] == seq3 &&
557		cop_program[command+4] == seq4 && cop_program[command+5] == seq5 && cop_program[command+6] == seq6 && cop_program[command+7] == seq7 &&
558		cop_func_value[command/8] == _funcval_ &&
559		cop_func_mask[command/8] == _funcmask_)
	556	cop_program[command+4] == seq4 && cop_program[command+5] == seq5 && cop_program[command+6] == seq6 && cop_program[command+7] == seq7 &&
	557	cop_func_value[command/8] == _funcval_ &&
	558	cop_func_mask[command/8] == _funcmask_)
560	559	return 1;
561	560	else
562	561	return 0;
r32760	r32761
877	876
878	877	/* Number Conversion */
879	878
880		// according to score display in https://www.youtube.com/watch?v=T1M8sxYgt9A
	879	// according to score display in https://www.youtube.com/watch?v=T1M8sxYgt9A
881	880	// we should return 0x30 for unused digits? according to Raiden 2 and Zero
882	881	// Team the value should be 0x20, can this be configured?
883	882	// grainbow doesn't like this implementation at all (21 credits, 2 digit high scores etc.)
r32760	r32761
890	889
891	890	if(digits > 9)
892	891	digits = 9;
893
	892
894	893	for (int i = 0; i < digits; i++)
895	894	{
896	895	if (!val && i)
r32760	r32761
903	902	val = val / 10;
904	903	}
905	904	}
906
	905
907	906	cop_itoa_digits[9] = 0;
908	907	}
909	908
r32760	r32761
1106	1105
1107	1106	/*
1108	1107	## - trig (up5) (low11) : (sq0, sq1, sq2, sq3, sq4, sq5, sq6, sq7) valu mask
1109		07 - 3bb0 ( 07) ( 3b0) : (f9c, b9c, b9c, b9c, b9c, b9c, b9c, 99c) 4 007f (legionna, heatbrl, cupsoc, grainbow, godzilla, denjinmk, raiden2, raidendx,
	1108	07 - 3bb0 ( 07) ( 3b0) : (f9c, b9c, b9c, b9c, b9c, b9c, b9c, 99c) 4 007f (legionna, heatbrl, cupsoc, grainbow, godzilla, denjinmk, raiden2, raidendx,
1110	1109	07 - 3b30 ( 07) ( 330) : (f9c, b9c, b9c, b9c, b9c, b9c, b9c, 99c) 4 007f (zeroteam, xsedae)
1111	1110	*/
1112	1111
r32760	r32761
1262	1261	else
1263	1262	angle -= cop_angle_step;
1264	1263	}
1265
	1264
1266	1265	cop_write_word(space, cop_regs[primary_reg], flags);
1267	1266
1268	1267	if (!m_cpu_is_68k)
r32760	r32761
1304	1303	else
1305	1304	angle -= cop_angle_step;
1306	1305	}
1307
	1306
1308	1307	cop_write_word(space, cop_regs[primary_reg], flags);
1309	1308
1310	1309	if (!m_cpu_is_68k)
r32760	r32761
1716	1715	//printf("%02x %02x %02x %02x %02x %02x\n", (UINT8)size[i], (UINT8)dx[i], (UINT8)size[1], (UINT8)dx[1], (UINT8)size[2], (UINT8)dx[2]);
1717	1716
1718	1717	int j = slot;
1719
	1718
1720	1719	UINT8 res;
1721	1720
1722	1721	if (num_axis==3) res = 7;
r32760	r32761
1791	1790	case 0x39b0:
1792	1791	case 0x3b30:
1793	1792	case 0x3bb0: { // 3bb0 0004 007f 0038 - 0f9c 0b9c 0b9c 0b9c 0b9c 0b9c 0b9c 099c
1794		execute_3b30(space, offset, data);
	1793	execute_3b30(space, offset, data);
1795	1794
1796	1795	break;
1797	1796	}
r32760	r32761
1829	1828	case 0x5a05: // 5a05 0006 fff7 0058 - 0180 02e0 03a0 00a0 03a0 0000 0000 0000
1830	1829	// fprintf(stderr, "sprcpt 5a05 %04x %04x %04x %08x %08x\n", cop_regs[0], cop_regs[1], cop_regs[3], space.read_dword(cop_regs[0]), space.read_dword(cop_regs[3]));
1831	1830	execute_5a05(space, offset, data);
1832
	1831
1833	1832	break;
1834	1833
1835	1834	case 0xf205: // f205 0006 fff7 00f0 - 0182 02e0 03c0 00c0 03c0 0000 0000 0000
r32760	r32761
2064	2063	WRITE16_MEMBER(raiden2cop_device::LEGACY_cop_cmd_w)
2065	2064	{
2066	2065	int command;
2067
2068	2066
	2067
2069	2068	seibu_cop_log("%06x: COPX execute table macro command %04x \| regs %08x %08x %08x %08x %08x\n", space.device().safe_pc(), data, cop_regs[0], cop_regs[1], cop_regs[2], cop_regs[3], cop_regs[4]);
2070	2069
2071	2070
r32760	r32761
2117	2116
2118	2117	/* SINE math - 0x8100 */
2119	2118	/*
2120		00000-0ffff:
2121		amp = x/256
2122		ang = x & 255
2123		s = sin(ang2pi/256)
2124		val = trunc(s*amp)
2125		if(s<0)
2126		val--
2127		if(s == 192)
2128		val = -2*amp
2129		*/
	2119	00000-0ffff:
	2120	amp = x/256
	2121	ang = x & 255
	2122	s = sin(ang2pi/256)
	2123	val = trunc(s*amp)
	2124	if(s<0)
	2125	val--
	2126	if(s == 192)
	2127	val = -2*amp
	2128	*/
2130	2129	if (check_command_matches(command, 0xb9a, 0xb88, 0x888, 0x000, 0x000, 0x000, 0x000, 0x000, 7, 0xfdfb))
2131	2130	{
2132	2131	executed = 1;
r32760	r32761
2136	2135
2137	2136	/* COSINE math - 0x8900 */
2138	2137	/*
2139		10000-1ffff:
2140		amp = x/256
2141		ang = x & 255
2142		s = cos(ang2pi/256)
2143		val = trunc(s*amp)
2144		if(s<0)
2145		val--
2146		if(s == 128)
2147		val = -2*amp
2148		*/
	2138	10000-1ffff:
	2139	amp = x/256
	2140	ang = x & 255
	2141	s = cos(ang2pi/256)
	2142	val = trunc(s*amp)
	2143	if(s<0)
	2144	val--
	2145	if(s == 128)
	2146	val = -2*amp
	2147	*/
2149	2148	if (check_command_matches(command, 0xb9a, 0xb8a, 0x88a, 0x000, 0x000, 0x000, 0x000, 0x000, 7, 0xfdfb))
2150	2149	{
2151	2150	executed = 1;
r32760	r32761
2173	2172	/* Pythagorean theorem, hypotenuse length - 0x3bb0 */
2174	2173	//(grainbow) \| 4 \| 007f \| 3bb0 \| f9c b9c b9c b9c b9c b9c b9c 99c
2175	2174	/*
2176		40000-7ffff:
2177		v1 = (x / 32768)*64
2178		v2 = (x & 255)*32767/255
2179		val = sqrt(v1v1+v2v2) (unsigned)
2180		*/
	2175	40000-7ffff:
	2176	v1 = (x / 32768)*64
	2177	v2 = (x & 255)*32767/255
	2178	val = sqrt(v1v1+v2v2) (unsigned)
	2179	*/
2181	2180	if (check_command_matches(command, 0xf9c, 0xb9c, 0xb9c, 0xb9c, 0xb9c, 0xb9c, 0xb9c, 0x99c, 4, 0x007f))
2182	2181	{
2183	2182	executed = 1;
r32760	r32761
2187	2186
2188	2187	/* Division - 0x42c2 */
2189	2188	/*
2190		20000-2ffff:
2191		v1 = x / 1024
2192		v2 = x & 1023
2193		val = !v1 ? 32767 : trunc(v2/v1+0.5)
2194		30000-3ffff:
2195		v1 = x / 1024
2196		v2 = (x & 1023)*32
2197		val = !v1 ? 32767 : trunc(v2/v1+0.5)
2198		*/
	2189	20000-2ffff:
	2190	v1 = x / 1024
	2191	v2 = x & 1023
	2192	val = !v1 ? 32767 : trunc(v2/v1+0.5)
	2193	30000-3ffff:
	2194	v1 = x / 1024
	2195	v2 = (x & 1023)*32
	2196	val = !v1 ? 32767 : trunc(v2/v1+0.5)
	2197	*/
2199	2198	if (check_command_matches(command, 0xf9a, 0xb9a, 0xb9c, 0xb9c, 0xb9c, 0x29c, 0x000, 0x000, 5, 0xfcdd))
2200	2199	{
2201	2200	executed = 1;
r32760	r32761
2204	2203	}
2205	2204
2206	2205	/*
2207		collision detection:
	2206	collision detection:
2208	2207
2209		int dy_0 = space.read_dword(cop_regs[0]+4);
2210		int dx_0 = space.read_dword(cop_regs[0]+8);
2211		int dy_1 = space.read_dword(cop_regs[1]+4);
2212		int dx_1 = space.read_dword(cop_regs[1]+8);
2213		int hitbox_param1 = space.read_dword(cop_regs[2]);
2214		int hitbox_param2 = space.read_dword(cop_regs[3]);
	2208	int dy_0 = space.read_dword(cop_regs[0]+4);
	2209	int dx_0 = space.read_dword(cop_regs[0]+8);
	2210	int dy_1 = space.read_dword(cop_regs[1]+4);
	2211	int dx_1 = space.read_dword(cop_regs[1]+8);
	2212	int hitbox_param1 = space.read_dword(cop_regs[2]);
	2213	int hitbox_param2 = space.read_dword(cop_regs[3]);
2215	2214
2216		TODO: we are ignoring the funcval / funcmask params for now
2217		*/
	2215	TODO: we are ignoring the funcval / funcmask params for now
	2216	*/
2218	2217
2219	2218	if (check_command_matches(command, 0xb80, 0xb82, 0xb84, 0xb86, 0x000, 0x000, 0x000, 0x000, funcval, funcmask))
2220	2219	{
r32760	r32761
2287	2286	if (check_command_matches(command, 0x380, 0x39a, 0x380, 0xa80, 0x29a, 0x000, 0x000, 0x000, 8, 0xf3e7))
2288	2287	{
2289	2288	executed = 1;
2290		execute_6200(space, offset, data);
	2289	execute_6200(space, offset, data);
2291	2290	return;
2292	2291	}
2293	2292
r32760	r32761
2311	2310	if (executed == 0)
2312	2311	printf("did not execute %04x\n", data); // cup soccer triggers this a lot (and others)
2313	2312	}
2314
2315
2316
2317

trunk/src/mame/machine/raiden2cop.h
r32760	r32761
87	87	DECLARE_WRITE16_MEMBER( cop_itoa_high_w );
88	88	DECLARE_WRITE16_MEMBER( cop_itoa_digit_count_w );
89	89	DECLARE_READ16_MEMBER ( cop_itoa_digits_r );
90
	90
91	91	UINT32 cop_itoa;
92	92	UINT16 cop_itoa_digit_count;
93	93	UINT8 cop_itoa_digits[10];
r32760	r32761
122	122
123	123	UINT32 cop_regs[8];
124	124	UINT16 cop_status, cop_scale, cop_angle, cop_dist;
125
126	125
	126
127	127	UINT16 cop_angle_target;
128	128	UINT16 cop_angle_step;
129	129
130	130
131	131	struct colinfo {
132
133	132	colinfo()
134	133	{
135	134	pos[0] = pos[1] = pos[2] = 0;
r32760	r32761
140	139	spradr = 0;
141	140	min[0] = min[1] = min[2] = 0;
142	141	max[0] = max[1] = max[2] = 0;
143
	142
144	143	}
145	144
146	145

trunk/src/mame/machine/amiga.c
r32760	r32761
358	358	m_pot1y += !(m_potgo_port->read() & 0x4000);
359	359	}
360	360	}
361
	361
362	362	// render up to this scanline
363	363	if (!m_screen->update_partial(scanline))
364	364	{

trunk/src/mame/machine/konppc.c
r32760	r32761
18	18	: device_t(mconfig, KONPPC, "Konami PowerPC Common Functions", tag, owner, clock, "konppc", __FILE__),
19	19	cgboard_type(0),
20	20	num_cgboards(0)/*,
21		cgboard_id(MAX_CG_BOARDS)*/
	21	cgboard_id(MAX_CG_BOARDS)*/
22	22	{
23	23	}
24	24

trunk/src/mame/machine/kaneko_calc3.h
r32760	r32761
16	16
17	17	void reset_run_timer();
18	18	void mcu_run();
19
	19
20	20	protected:
21	21	virtual void device_start();
22	22	virtual void device_reset();
r32760	r32761
43	43	UINT16 m_poll_addr;
44	44	UINT16 m_checksumaddress;
45	45	emu_timer* m_runtimer;
46
	46
47	47	enum
48	48	{
49	49	MCU_RUN_TIMER
50	50	};
51
	51
52	52	void mcu_init();
53	53	void initial_scan_tables();
54	54	void mcu_com_w(offs_t offset, UINT16 data, UINT16 mem_mask, int _n_);

199869 Revisions