trunk/src/mame/drivers/midvunit.c
r32682 | r32683 | |
439 | 439 | * |
440 | 440 | *************************************/ |
441 | 441 | |
442 | | static void midvplus_xf1_w(tms3203x_device &device, UINT8 val) |
| 442 | WRITE8_MEMBER(midvunit_state::midvplus_xf1_w) |
443 | 443 | { |
444 | | midvunit_state *state = device.machine().driver_data<midvunit_state>(); |
445 | | // osd_printf_debug("xf1_w = %d\n", val); |
| 444 | // osd_printf_debug("xf1_w = %d\n", data); |
446 | 445 | |
447 | | if (state->m_lastval && !val) |
448 | | memcpy(state->m_ram_base, state->m_fastram_base, 0x20000*4); |
| 446 | if (m_lastval && !data) |
| 447 | memcpy(m_ram_base, m_fastram_base, 0x20000*4); |
449 | 448 | |
450 | | state->m_lastval = val; |
| 449 | m_lastval = data; |
451 | 450 | } |
452 | 451 | |
453 | 452 | |
r32682 | r32683 | |
489 | 488 | ADDRESS_MAP_END |
490 | 489 | |
491 | 490 | |
492 | | static const tms3203x_config midvplus_config = { false, NULL, midvplus_xf1_w }; |
493 | | |
494 | 491 | static ADDRESS_MAP_START( midvplus_map, AS_PROGRAM, 32, midvunit_state ) |
495 | 492 | AM_RANGE(0x000000, 0x01ffff) AM_RAM AM_SHARE("ram_base") |
496 | 493 | AM_RANGE(0x400000, 0x41ffff) AM_RAM AM_SHARE("fastram_base") |
r32682 | r32683 | |
1045 | 1042 | MCFG_MIDWAY_SERIAL_PIC2_YEAR_OFFS(94) |
1046 | 1043 | MACHINE_CONFIG_END |
1047 | 1044 | |
1048 | | |
1049 | 1045 | static MACHINE_CONFIG_DERIVED( midvplus, midvcommon ) |
1050 | 1046 | |
1051 | 1047 | /* basic machine hardware */ |
1052 | 1048 | MCFG_CPU_MODIFY("maincpu") |
1053 | | MCFG_TMS3203X_CONFIG(midvplus_config) |
1054 | 1049 | MCFG_CPU_PROGRAM_MAP(midvplus_map) |
| 1050 | MCFG_TMS3203X_XF1_CB(WRITE8(midvunit_state, midvplus_xf1_w)) |
1055 | 1051 | |
1056 | 1052 | MCFG_MACHINE_RESET_OVERRIDE(midvunit_state,midvplus) |
1057 | 1053 | MCFG_DEVICE_REMOVE("nvram") |
trunk/src/mame/drivers/rastersp.c
r32682 | r32683 | |
840 | 840 | SLOT_INTERFACE_END |
841 | 841 | |
842 | 842 | |
843 | | |
844 | 843 | /************************************* |
845 | 844 | * |
846 | | * TMS32031 |
847 | | * |
848 | | *************************************/ |
849 | | |
850 | | static const tms3203x_config tms_config = |
851 | | { |
852 | | true // Boot-loader mode |
853 | | }; |
854 | | |
855 | | |
856 | | |
857 | | /************************************* |
858 | | * |
859 | 845 | * Machine driver |
860 | 846 | * |
861 | 847 | *************************************/ |
r32682 | r32683 | |
868 | 854 | MCFG_CPU_IRQ_ACKNOWLEDGE_DRIVER(rastersp_state,irq_callback) |
869 | 855 | |
870 | 856 | MCFG_CPU_ADD("dsp", TMS32031, 33330000) |
871 | | MCFG_TMS3203X_CONFIG(tms_config) |
872 | 857 | MCFG_CPU_PROGRAM_MAP(dsp_map) |
| 858 | MCFG_TMS3203X_MCBL(true) // Boot-loader mode |
873 | 859 | |
874 | 860 | /* Devices */ |
875 | 861 | MCFG_TIMER_DRIVER_ADD("tms_timer1", rastersp_state, tms_timer1) |
trunk/src/mame/drivers/gaelco3d.c
r32682 | r32683 | |
465 | 465 | } |
466 | 466 | |
467 | 467 | |
468 | | static void iack_w(tms3203x_device &device, UINT8 state, offs_t addr) |
| 468 | WRITE8_MEMBER(gaelco3d_state::tms_iack_w) |
469 | 469 | { |
470 | 470 | if (LOG) |
471 | | logerror("iack_w(%d) - %06X\n", state, addr); |
472 | | device.set_input_line(0, CLEAR_LINE); |
| 471 | logerror("iack_w(%d) - %06X\n", data, offset); |
| 472 | m_tms->set_input_line(0, CLEAR_LINE); |
473 | 473 | } |
474 | 474 | |
475 | 475 | |
r32682 | r32683 | |
949 | 949 | * |
950 | 950 | *************************************/ |
951 | 951 | |
952 | | static const tms3203x_config tms_config = |
953 | | { |
954 | | true, |
955 | | 0, |
956 | | 0, |
957 | | iack_w |
958 | | }; |
959 | | |
960 | | |
961 | 952 | static MACHINE_CONFIG_START( gaelco3d, gaelco3d_state ) |
962 | 953 | |
963 | 954 | /* basic machine hardware */ |
r32682 | r32683 | |
966 | 957 | MCFG_CPU_VBLANK_INT_DRIVER("screen", gaelco3d_state, vblank_gen) |
967 | 958 | |
968 | 959 | MCFG_CPU_ADD("tms", TMS32031, 60000000) |
969 | | MCFG_TMS3203X_CONFIG(tms_config) |
970 | 960 | MCFG_CPU_PROGRAM_MAP(tms_map) |
| 961 | MCFG_TMS3203X_MCBL(true) |
| 962 | MCFG_TMS3203X_IACK_CB(WRITE8(gaelco3d_state, tms_iack_w)) |
971 | 963 | |
972 | 964 | MCFG_CPU_ADD("adsp", ADSP2115, 16000000) |
973 | 965 | MCFG_ADSP21XX_SPORT_TX_CB(WRITE32(gaelco3d_state, adsp_tx_callback)) |
trunk/src/mame/audio/cage.c
r32682 | r32683 | |
593 | 593 | * |
594 | 594 | *************************************/ |
595 | 595 | |
596 | | static const tms3203x_config cage_config = |
597 | | { |
598 | | true |
599 | | }; |
600 | | |
601 | | |
602 | 596 | static ADDRESS_MAP_START( cage_map, AS_PROGRAM, 32, atari_cage_device ) |
603 | 597 | AM_RANGE(0x000000, 0x00ffff) AM_RAM |
604 | 598 | AM_RANGE(0x200000, 0x200000) AM_WRITENOP |
r32682 | r32683 | |
634 | 628 | |
635 | 629 | /* basic machine hardware */ |
636 | 630 | MCFG_CPU_ADD("cage", TMS32031, 33868800) |
637 | | MCFG_TMS3203X_CONFIG(cage_config) |
638 | 631 | MCFG_CPU_PROGRAM_MAP(cage_map) |
| 632 | MCFG_TMS3203X_MCBL(true) |
639 | 633 | |
640 | 634 | MCFG_TIMER_DEVICE_ADD("cage_dma_timer", DEVICE_SELF, atari_cage_device, dma_timer_callback) |
641 | 635 | MCFG_TIMER_DEVICE_ADD("cage_timer0", DEVICE_SELF, atari_cage_device, cage_timer_callback) |
trunk/src/emu/cpu/tms32031/32031ops.c
r32682 | r32683 | |
108 | 108 | } |
109 | 109 | else if (dreg == TMR_IOF) |
110 | 110 | { |
111 | | if (m_xf0_w != NULL && IREG(TMR_IOF) & 0x002) |
112 | | (*m_xf0_w)(*this, (IREG(TMR_IOF) >> 2) & 1); |
113 | | if (m_xf1_w != NULL && IREG(TMR_IOF) & 0x020) |
114 | | (*m_xf1_w)(*this, (IREG(TMR_IOF) >> 6) & 1); |
| 111 | if (IREG(TMR_IOF) & 0x002) |
| 112 | m_xf0_cb((offs_t)0, (IREG(TMR_IOF) >> 2) & 1); |
| 113 | if (IREG(TMR_IOF) & 0x020) |
| 114 | m_xf1_cb((offs_t)0, (IREG(TMR_IOF) >> 6) & 1); |
115 | 115 | } |
116 | 116 | else if (dreg == TMR_ST || dreg == TMR_IF || dreg == TMR_IE) |
117 | 117 | check_irqs(); |
r32682 | r32683 | |
3132 | 3132 | void tms3203x_device::iack_dir(UINT32 op) |
3133 | 3133 | { |
3134 | 3134 | offs_t addr = DIRECT(op); |
3135 | | if (m_iack_w) |
3136 | | (*m_iack_w)(*this, ASSERT_LINE, addr); |
| 3135 | m_iack_cb(addr, ASSERT_LINE); |
3137 | 3136 | RMEM(addr); |
3138 | | if (m_iack_w) |
3139 | | (*m_iack_w)(*this, CLEAR_LINE, addr); |
| 3137 | m_iack_cb(addr, CLEAR_LINE); |
3140 | 3138 | } |
3141 | 3139 | |
3142 | 3140 | void tms3203x_device::iack_ind(UINT32 op) |
3143 | 3141 | { |
3144 | 3142 | offs_t addr = INDIRECT_D(op, op >> 8); |
3145 | | if (m_iack_w) |
3146 | | (*m_iack_w)(*this, ASSERT_LINE, addr); |
| 3143 | m_iack_cb(addr, ASSERT_LINE); |
3147 | 3144 | RMEM(addr); |
3148 | | if (m_iack_w) |
3149 | | (*m_iack_w)(*this, CLEAR_LINE, addr); |
| 3145 | m_iack_cb(addr, CLEAR_LINE); |
3150 | 3146 | } |
3151 | 3147 | |
3152 | 3148 | /*-----------------------------------------------------*/ |
trunk/src/emu/cpu/tms32031/tms32031.c
r32682 | r32683 | |
263 | 263 | m_is_idling(false), |
264 | 264 | m_icount(0), |
265 | 265 | m_program(0), |
266 | | m_direct(0) |
| 266 | m_direct(0), |
| 267 | m_mcbl_mode(false), |
| 268 | m_xf0_cb(*this), |
| 269 | m_xf1_cb(*this), |
| 270 | m_iack_cb(*this) |
267 | 271 | { |
268 | | m_mcbl_mode = false; |
269 | | m_xf0_w = NULL; |
270 | | m_xf1_w = NULL; |
271 | | m_iack_w = NULL; |
272 | | |
273 | 272 | // initialize remaining state |
274 | 273 | memset(&m_r, 0, sizeof(m_r)); |
275 | 274 | |
r32682 | r32683 | |
320 | 319 | |
321 | 320 | |
322 | 321 | //------------------------------------------------- |
323 | | // static_set_config - set the configuration |
324 | | // structure |
325 | | //------------------------------------------------- |
326 | | |
327 | | void tms3203x_device::static_set_config(device_t &device, const tms3203x_config &config) |
328 | | { |
329 | | tms3203x_device &tms = downcast<tms3203x_device &>(device); |
330 | | static_cast<tms3203x_config &>(tms) = config; |
331 | | } |
332 | | |
333 | | |
334 | | //------------------------------------------------- |
335 | 322 | // rom_region - return a pointer to the device's |
336 | 323 | // internal ROM region |
337 | 324 | //------------------------------------------------- |
r32682 | r32683 | |
389 | 376 | m_program = &space(AS_PROGRAM); |
390 | 377 | m_direct = &m_program->direct(); |
391 | 378 | |
| 379 | // resolve devcb handlers |
| 380 | m_xf0_cb.resolve_safe(); |
| 381 | m_xf1_cb.resolve_safe(); |
| 382 | m_iack_cb.resolve_safe(); |
| 383 | |
392 | 384 | // set up the internal boot loader ROM |
393 | 385 | m_bootrom = reinterpret_cast<UINT32*>(memregion(shortname())->base()); |
394 | 386 | m_direct->set_direct_update(direct_update_delegate(FUNC(tms3203x_device::direct_handler), this)); |
trunk/src/emu/cpu/tms32031/tms32031.h
r32682 | r32683 | |
90 | 90 | // INTERFACE CONFIGURATION MACROS |
91 | 91 | //************************************************************************** |
92 | 92 | |
93 | | #define MCFG_TMS3203X_CONFIG(_config) \ |
94 | | tms3203x_device::static_set_config(*device, _config); |
| 93 | #define MCFG_TMS3203X_MCBL(_mode) \ |
| 94 | tms3203x_device::set_mcbl_mode(*device, _mode); |
95 | 95 | |
| 96 | #define MCFG_TMS3203X_XF0_CB(_devcb) \ |
| 97 | devcb = &tms3203x_device::set_xf0_callback(*device, DEVCB_##_devcb); |
96 | 98 | |
| 99 | #define MCFG_TMS3203X_XF1_CB(_devcb) \ |
| 100 | devcb = &tms3203x_device::set_xf1_callback(*device, DEVCB_##_devcb); |
| 101 | |
| 102 | #define MCFG_TMS3203X_IACK_CB(_devcb) \ |
| 103 | devcb = &tms3203x_device::set_iack_callback(*device, DEVCB_##_devcb); |
| 104 | |
| 105 | |
97 | 106 | //************************************************************************** |
98 | 107 | // TYPE DEFINITIONS |
99 | 108 | //************************************************************************** |
100 | 109 | |
101 | | class tms3203x_device; |
102 | | |
103 | | // I/O callback types |
104 | | typedef void (*tms3203x_xf_func)(tms3203x_device &device, UINT8 val); |
105 | | typedef void (*tms3203x_iack_func)(tms3203x_device &device, UINT8 val, offs_t address); |
106 | | |
107 | | |
108 | | // ======================> tms3203x_config |
109 | | |
110 | | struct tms3203x_config |
111 | | { |
112 | | bool m_mcbl_mode; |
113 | | tms3203x_xf_func m_xf0_w; |
114 | | tms3203x_xf_func m_xf1_w; |
115 | | tms3203x_iack_func m_iack_w; |
116 | | }; |
117 | | |
118 | | |
119 | | |
120 | 110 | // ======================> tms3203x_device |
121 | 111 | |
122 | | class tms3203x_device : public cpu_device, |
123 | | public tms3203x_config |
| 112 | class tms3203x_device : public cpu_device |
124 | 113 | { |
125 | 114 | struct tmsreg |
126 | 115 | { |
r32682 | r32683 | |
159 | 148 | |
160 | 149 | public: |
161 | 150 | // inline configuration helpers |
162 | | static void static_set_config(device_t &device, const tms3203x_config &config); |
| 151 | static void set_mcbl_mode(device_t &device, bool mode) { downcast<tms3203x_device &>(device).m_mcbl_mode = mode; } |
| 152 | template<class _Object> static devcb_base &set_xf0_callback(device_t &device, _Object object) { return downcast<tms3203x_device &>(device).m_xf0_cb.set_callback(object); } |
| 153 | template<class _Object> static devcb_base &set_xf1_callback(device_t &device, _Object object) { return downcast<tms3203x_device &>(device).m_xf1_cb.set_callback(object); } |
| 154 | template<class _Object> static devcb_base &set_iack_callback(device_t &device, _Object object) { return downcast<tms3203x_device &>(device).m_iack_cb.set_callback(object); } |
163 | 155 | |
164 | 156 | // public interfaces |
165 | 157 | static float fp_to_float(UINT32 floatdata); |
r32682 | r32683 | |
779 | 771 | direct_read_data * m_direct; |
780 | 772 | UINT32 * m_bootrom; |
781 | 773 | |
| 774 | bool m_mcbl_mode; |
| 775 | devcb_write8 m_xf0_cb; |
| 776 | devcb_write8 m_xf1_cb; |
| 777 | devcb_write8 m_iack_cb; |
| 778 | |
782 | 779 | // tables |
783 | 780 | static void (tms3203x_device::*const s_tms32031ops[])(UINT32 op); |
784 | 781 | static UINT32 (tms3203x_device::*const s_indirect_d[0x20])(UINT32, UINT8); |