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r32637 Saturday 11th October, 2014 at 00:49:55 UTC by Robbbert
(MESS) spc1000: added fdd code [Meeso Kim] Note: I was unable to get the system to boot the floppy.

[src/mess/drivers]

spc1000.c

trunk/src/mess/drivers/spc1000.c

r32636	r32637
35	35	#include "imagedev/cassette.h"
36	36	#include "machine/ram.h"
37	37	#include "formats/spc1000_cas.h"
	38	#include "machine/i8255.h"
	39	#include "machine/upd765.h"
38	40
39	41
40	42	class spc1000_state : public driver_device
r32636	r32637
45	47	, m_p_videoram(*this, "videoram")
46	48	, m_vdg(*this, "mc6847")
47	49	, m_maincpu(*this, "maincpu")
	50	, m_fdccpu(*this, "fdccpu")
	51	, m_fdc(*this, "upd765")
	52	, m_pio(*this, "d8255_master")
48	53	, m_ram(*this, RAM_TAG)
49	54	, m_cass(*this, "cassette")
50	55	{}
r32636	r32637
57	62	DECLARE_READ8_MEMBER(porta_r);
58	63	DECLARE_READ8_MEMBER(mc6847_videoram_r);
59	64	DECLARE_WRITE8_MEMBER(cass_w);
60		///DECLARE_WRITE8_MEMBER(spc1000_sd725_w);
61		///DECLARE_READ8_MEMBER(spc1000_sd725_r);
62
	65	DECLARE_WRITE8_MEMBER(spc1000_sd725_w);
	66	DECLARE_READ8_MEMBER(spc1000_sd725_r);
	67	DECLARE_WRITE8_MEMBER(fdc_8255_b_w);
	68	DECLARE_READ8_MEMBER(fdc_8255_c_r);
	69	DECLARE_WRITE8_MEMBER(fdc_8255_c_w);
	70	DECLARE_READ8_MEMBER( upd765_tc_r );
	71	DECLARE_WRITE8_MEMBER( fdc_control_w );
63	72	MC6847_GET_CHARROM_MEMBER(get_char_rom)
64	73	{
65	74	return m_p_videoram[0x1000 + (ch & 0x7f) * 16 + line];
r32636	r32637
70	79	UINT8 m_IPLK;
71	80	UINT8 m_GMODE;
72	81	UINT16 m_page;
	82	UINT8 *m_work_ram;
73	83	virtual void machine_reset();
74		///FloppyDisk fdd;
75		///void initDisk(void);
76	84	required_device<mc6847_base_device> m_vdg;
77	85	required_device<cpu_device> m_maincpu;
	86	required_device<cpu_device> m_fdccpu;
	87	required_device<upd765a_device> m_fdc;
	88	required_device<i8255_device> m_pio;
78	89	required_device<ram_device> m_ram;
79	90	required_device<cassette_image_device> m_cass;
	91
	92	floppy_image_device *m_fd0;
	93	floppy_image_device *m_fd1;
	94
	95	emu_timer *m_timer_tc;
	96
	97	UINT8 m_i8255_0_pc;
	98	UINT8 m_i8255_1_pc;
	99	UINT8 m_i8255_portb;
	100
	101	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
80	102	};
81	103
	104	void spc1000_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
	105	{
	106	m_fdc->tc_w(false);
	107	}
82	108
83
84	109	static ADDRESS_MAP_START(spc1000_mem, AS_PROGRAM, 8, spc1000_state )
85	110	ADDRESS_MAP_UNMAP_HIGH
86	111	AM_RANGE( 0x0000, 0x7fff ) AM_READ_BANK("bank1") AM_WRITE_BANK("bank2")
r32636	r32637
139	164	return m_GMODE;
140	165	}
141	166
	167	READ8_MEMBER(spc1000_state::spc1000_sd725_r)
	168	{
	169	UINT8 data = 0;
	170	switch (offset)
	171	{
	172	case 1:
	173	data = m_i8255_portb;
	174	break;
	175	case 2:
	176	data = m_i8255_1_pc >> 4;
	177	break;
	178	}
	179	return data;
	180	}
	181
	182	WRITE8_MEMBER(spc1000_state::spc1000_sd725_w)
	183	{
	184	switch (offset)
	185	{
	186	case 0:
	187	m_pio->write(space, offset+1, data);
	188	break;
	189	case 2:
	190	m_i8255_0_pc = data;
	191	break;
	192	}
	193	}
	194
	195	READ8_MEMBER(spc1000_state::fdc_8255_c_r)
	196	{
	197	return m_i8255_0_pc >> 4;
	198	}
	199
	200	WRITE8_MEMBER(spc1000_state::fdc_8255_b_w)
	201	{
	202	m_i8255_portb = data;
	203	}
	204
	205	WRITE8_MEMBER(spc1000_state::fdc_8255_c_w)
	206	{
	207	m_i8255_1_pc = data;
	208	}
	209
	210	//-------------------------------------------------
	211	//  fdc interrupt
	212	//-------------------------------------------------
	213
	214	READ8_MEMBER( spc1000_state::upd765_tc_r )
	215	{
	216	logerror("%s: upd765_tc_r\n", space.machine().describe_context());
	217
	218	// toggle tc on read
	219	m_fdc->tc_w(true);
	220	m_timer_tc->adjust(attotime::zero);
	221
	222	return 0xff;
	223	}
	224
	225	WRITE8_MEMBER( spc1000_state::fdc_control_w )
	226	{
	227	logerror("%s: sd725_fdc_control_w(%02x)\n", space.machine().describe_context(), data);
	228
	229	// bit 0, motor on signal
	230	if (m_fd0)
	231	m_fd0->mon_w(!BIT(data, 0));
	232	if (m_fd1)
	233	m_fd1->mon_w(!BIT(data, 0));
	234	}
	235
	236
142	237	static ADDRESS_MAP_START( spc1000_io , AS_IO, 8, spc1000_state )
143	238	ADDRESS_MAP_UNMAP_HIGH
144	239	AM_RANGE(0x0000, 0x1fff) AM_RAM AM_SHARE("videoram")
r32636	r32637
157	252	AM_RANGE(0x8008, 0x8008) AM_READ_PORT("LINE8")
158	253	AM_RANGE(0x8009, 0x8009) AM_READ_PORT("LINE9")
159	254	AM_RANGE(0xA000, 0xA000) AM_READWRITE(spc1000_iplk_r, spc1000_iplk_w)
160		///AM_RANGE(0xC000, 0xC002) AM_READWRITE(spc1000_sd725_r, spc1000_sd725_w)
	255	AM_RANGE(0xC000, 0xC002) AM_READWRITE(spc1000_sd725_r, spc1000_sd725_w)
	256	//   AM_RANGE(0xC000, 0xC003) AM_DEVREADWRITE("d8255_master", i8255_device, read, write)
161	257	ADDRESS_MAP_END
162	258
163	259	/* Input ports */
r32636	r32637
244	340	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("I") PORT_CODE(KEYCODE_I) PORT_CHAR('i') PORT_CHAR('I') PORT_CHAR(0x09)
245	341	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("8 (") PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(')
246	342	PORT_START("LINE9")
247		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_UNUSED) ///   PORT_NAME("IPL") PORT_CODE(KEYCODE_F6)
	343	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_START)   PORT_NAME("IPL") PORT_CODE(KEYCODE_END)
248	344	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F5") PORT_CODE(KEYCODE_F5)
249	345	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("- =") PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-') PORT_CHAR('=')
250	346	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("0") PORT_CODE(KEYCODE_0) PORT_CHAR('0')
r32636	r32637
254	350	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("9 )") PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')')
255	351	INPUT_PORTS_END
256	352
257		#if 0
258		typedef union PC
259		{
260		struct {
261		unsigned char rDAV : 1;
262		unsigned char rRFD : 1;
263		unsigned char rDAC : 1;
264		unsigned char rNON : 1;
265		unsigned char wDAV : 1;
266		unsigned char wRFD : 1;
267		unsigned char wDAC : 1;
268		unsigned char wATN : 1;
269		} bits;
270		unsigned char b;
271		} pc_t;
272	353
273		typedef char byte;
274
275		typedef struct
276		{
277		byte rdVal;
278		byte wrVal;
279		byte rSize;
280		UINT16 seq;
281		byte isCmd;
282		byte cmd;
283		UINT8 sdata[6];
284		pc_t PC;
285		char diskfile[1024];
286		char diskfile2[1024];
287		UINT8 diskdata[80*16*256]; // 80 tracks 16 sectors 256 byte
288		UINT8 diskdata2[80*16*256];
289		byte modified;
290		byte modified2;
291		byte write;
292		byte write2;
293		byte *buffer;
294		byte idx;
295		int datasize;
296		int dataidx;
297		} FloppyDisk;
298
299		void spc1000_state::initDisk(void)
300		{
301		FILE *f;
302		strcpy(fdd.diskfile, "system.dsk");
303		strcpy(fdd.diskfile2, "disk.dsk");
304		printf("ddd\n");
305		if (strlen(fdd.diskfile) > 4)
306		{
307		f = fopen(fdd.diskfile, "rb");
308		if (f > 0) {
309		fread(fdd.diskdata, 1, sizeof(fdd.diskdata), f);
310		fclose(f);
311		}
312		}
313		if (strlen(fdd.diskfile2) > 4)
314		{
315		f = fopen(fdd.diskfile2, "rb");
316		if (f > 0) {
317		fread(fdd.diskdata2, 1, sizeof(fdd.diskdata2), f);
318		printf("disk.dsk\n");
319		fclose(f);
320		}
321		}
322		}
323
324		WRITE8_MEMBER(spc1000_state::spc1000_sd725_w)
325		{
326		//printf("write 0x%04x=%d\n", (0xc000+offset), data);
327		if (offset == 0) {
328		fdd.wrVal = data;
329		} else if (offset == 2) {
330		if (data != 0)
331		{
332		fdd.PC.b = (data & 0xf0) | (fdd.PC.b & 0xf);
333		}
334		else
335		{
336		fdd.PC.b = fdd.PC.b & 0xf;
337		}
338		if (data & 0x10) // DAV=1
339		{
340		//printf("FDD Data Valid (c000 bit4 on)\n");
341		if (fdd.isCmd == 1) // command
342		{
343		fdd.isCmd = 0;
344		printf("FDD Command(Data) = 0h%02x\n", fdd.wrVal);
345		fdd.cmd = fdd.wrVal;
346		switch (fdd.wrVal)
347		{
348		case 0x00: // FDD Initialization
349		printf("*FDD Initialization\n");
350		break;
351		case 0x01: // FDD Write
352		printf("*FDD Write\n");
353		fdd.rSize = 4;
354		fdd.seq = 0;
355		break;
356		case 0x02: // FDD Read
357		printf("*FDD Read\n");
358		//                            fdd.PC.bits.rRFD = 1;
359		fdd.rSize = 4;
360		fdd.seq = 0;
361		break;
362		case 0x03: // FDD Send Data
363		//printf("*FDD Send Data\n");
364		if (fdd.seq == 4)
365		{
366		printf("seq=%d,(%d,%d,%d,%d)\n", fdd.seq, fdd.sdata[0], fdd.sdata[1], fdd.sdata[2], fdd.sdata[3]);
367		fdd.buffer = (byte*)(fdd.sdata[1] != 0 ? fdd.diskdata2 : fdd.diskdata);
368		fdd.buffer += (fdd.sdata[2] * 16 + fdd.sdata[3]-1) * 256;
369		fdd.datasize = fdd.sdata[0] * 256;
370		fdd.dataidx = 0;
371
372		}
373		fdd.rdVal = 0;
374		break;
375		case 0x04: // FDD Copy
376		printf("*FDD Copy\n");
377		fdd.rSize = 7;
378		fdd.seq = 0;
379		break;
380		case 0x05: // FDD Format
381		printf("*FDD Format\n");
382		break;
383		case 0x06: // FDD Send Status
384		printf("*FDD Send Status\n");
385		#define DATA_OK 0x40
386		fdd.rdVal = 0x80 & DATA_OK;
387		break;
388		case 0x07: // FDD Send Drive State
389		printf("*FDD Send Drive State\n");
390		#define DRIVE0 0x10
391		fdd.rdVal = 0x0f | DRIVE0;
392		break;
393		case 0x08: // FDD RAM Test
394		printf("*FDD RAM Test\n");
395		fdd.rSize = 4;
396		fdd.seq = 0;
397		break;
398		case 0x09: // FDD Transmit 2
399		printf("*FDD Transmit 2\n");
400		fdd.rSize = 4;
401		fdd.seq = 0;
402		break;
403		case 0x0A: // FDD Action
404		printf("*FDD No Action\n");
405		break;
406		case 0x0B: // FDD Transmit 1
407		printf("*FDD Transmit 1\n");
408		fdd.rSize = 4;
409		fdd.seq = 0;
410		break;
411		case 0x0C: // FDD Receive
412		printf("*FDD Receive\n");
413		fdd.rSize = 4;
414		fdd.seq = 0;
415		break;
416		case 0x0D: // FDD Go
417		printf("*FDD Go\n");
418		fdd.rSize = 2;
419		fdd.seq = 0;
420		break;
421		case 0x0E: // FDD Load
422		printf("*FDD Load\n");
423		fdd.rSize = 6;
424		fdd.seq = 0;
425		break;
426		case 0x0F: // FDD Save
427		printf("FDD Save\n");
428		fdd.rSize = 6;
429		fdd.seq = 0;
430		break;
431		case 0x10: // FDD Load and Go
432		printf("*FDD Load and Go\n");
433		break;
434
435		}
436		}
437		else
438		{
439		if (fdd.rSize-- > 0)
440		{
441		fdd.sdata[fdd.seq++] = (char) fdd.wrVal;
442		printf("seq=%d, data = 0x%02x\n", fdd.seq-1, fdd.sdata[fdd.seq-1]);
443		// printf("cmd=%d\n", fdd.cmd);
444		if (fdd.rSize == 0)
445		{
446		printf("Fdd Command(%d) Fired\n", fdd.cmd);
447		if (fdd.cmd == 0x0e)
448		{
449		int offset = (int)((int)fdd.sdata[2] * 16 + (int)fdd.sdata[3]-1) * 256;
450		int size = fdd.sdata[0] * 256;
451		printf("load(%d,%d,%d,%d),offset=%d, size=%d\n", fdd.sdata[0], fdd.sdata[1], fdd.sdata[2], fdd.sdata[3], offset, size);
452		fdd.buffer = (byte*)(fdd.sdata[1] != 0 ? fdd.diskdata2 : fdd.diskdata);
453		//fdd.buffer += offset;
454		fdd.datasize = size;
455		unsigned short addr = ((unsigned short)fdd.sdata[4]) * 0x100 + (unsigned short)fdd.sdata[5];
456		printf("target addr=%04x, %02x, %02x, size=%d\n", addr, fdd.sdata[4], fdd.sdata[5], fdd.datasize);
457		UINT8 *mem = m_ram->pointer();
458		memcpy(&mem[addr], &fdd.buffer[offset], fdd.datasize);
459		}
460		else if (fdd.cmd == 0x0f)
461		{
462		int offset = (int)((int)fdd.sdata[2] * 16 + (int)fdd.sdata[3]-1) * 256;
463		int size = fdd.sdata[0] * 256;
464		printf("save(%d,%d,%d,%d),offset=%d, size=%d\n", fdd.sdata[0], fdd.sdata[1], fdd.sdata[2], fdd.sdata[3], offset, size);
465		fdd.buffer = (byte*)(fdd.sdata[1] != 0 ? fdd.diskdata2 : fdd.diskdata);
466		fdd.buffer += offset;
467		fdd.datasize = size;
468		unsigned short addr = ((unsigned short)fdd.sdata[4]) * 0x100 + (unsigned short)fdd.sdata[5];
469		printf("target addr=%04x, %02x, %02x, size=%d\n", addr, fdd.sdata[4], fdd.sdata[5], fdd.datasize);
470		UINT8 *mem = m_ram->pointer();
471		memcpy(fdd.buffer, &mem[addr], fdd.datasize);
472		}
473		}
474		}
475		}
476		fdd.PC.bits.rDAC = 1;
477
478		}
479		else if (fdd.PC.bits.rDAC == 1) // DAV=0
480		{
481		//printf("FDD Ouput Data Cleared (c000 bit4 off)\n");
482		fdd.wrVal = 0;
483		//              printf("FDD_Read = 0h%02x (cleared)\n", fdd.wrVal);
484		fdd.PC.bits.rDAC = 0;
485		}
486		if (data & 0x20) // RFD=1
487		{
488		//                printf("FDD Ready for Data Read (c000 bit5 on)\n");
489		fdd.PC.bits.rDAV = 1;
490		}
491		else if (fdd.PC.bits.rDAV == 1) // RFD=0
492		{
493		//fdd.rdVal = 0;
494		//printf("FDD Input Data = 0h%02x\n", fdd.rdVal);
495		fdd.PC.bits.rDAV = 0;
496		}
497		if (data & 0x40) // DAC=1
498		{
499		//                printf("FDD Data accepted (c000 bit6 on)\n");
500		}
501		if (data & 0x80) // ATN=1
502		{
503		//              printf("FDD Attention (c000 bit7 on)\n");
504		//printf("Command = 0x%02x\n", fdd.rdVal);
505		//printf("FDD Ready for Data\n", fdd.rdVal);
506		fdd.PC.bits.rRFD = 1;
507		fdd.isCmd = 1;
508		}
509		}
510		return;
511		}
512
513		READ8_MEMBER(spc1000_state::spc1000_sd725_r)
514		{
515		//printf("read %04x\n", (0xc000+offset));
516		if (offset == 1)
517		{
518		if (fdd.cmd == 3)
519		{
520		fdd.rdVal = *(fdd.buffer + fdd.dataidx++);
521		}
522		//printf("FDD_Data > 0h%02x\n", spcsys.fdd.rdVal);
523		return fdd.rdVal;
524		}
525		else if (offset == 2)
526		{
527		//printf("FDD_PC > 0h%02x\n", spcsys.fdd.PC.b);
528		return fdd.PC.b;
529		}
530		return 0;
531		}
532		#endif
533
534
535	354	void spc1000_state::machine_reset()
536	355	{
537	356	address_space &space = m_maincpu->space(AS_PROGRAM);
r32636	r32637
548	367	membank("bank2")->set_base(ram);
549	368	membank("bank3")->set_base(mem);
550	369	membank("bank4")->set_base(ram + 0x8000);
551		///initDisk();
	370
	371	m_work_ram = auto_alloc_array_clear(machine(), UINT8, 0x10000);
	372	m_fdccpu->set_input_line_vector(0, 0);
	373
	374	m_fd0 = machine().device<floppy_connector>("upd765:0")->get_device();
	375	m_fd1 = machine().device<floppy_connector>("upd765:1")->get_device();
552	376
553		m_IPLK = 1;
	377	m_timer_tc = timer_alloc(1, NULL);
	378	m_timer_tc->adjust(attotime::never);
	379
	380	// enable rom
	381	m_fdccpu->space(AS_PROGRAM).install_rom(0x0000, 0xfff, 0, 0x2000, memregion("rom")->base());
	382
	383	m_IPLK = 1;
554	384	}
555	385
556	386	READ8_MEMBER(spc1000_state::mc6847_videoram_r)
r32636	r32637
588	418	m_maincpu->set_input_line(0, state ? CLEAR_LINE : HOLD_LINE);
589	419	}
590	420
	421	static SLOT_INTERFACE_START( sd725_floppies )
	422	SLOT_INTERFACE( "sd320", EPSON_SD_320 )
	423	SLOT_INTERFACE_END
	424
	425	//-------------------------------------------------
	426	//  address maps
	427	//-------------------------------------------------
	428
	429	static ADDRESS_MAP_START( sd725_mem, AS_PROGRAM, 8, spc1000_state )
	430	ADDRESS_MAP_UNMAP_HIGH
	431	AM_RANGE(0x0000, 0x1fff) AM_ROM
	432	AM_RANGE(0x2000, 0xffff) AM_RAM
	433	ADDRESS_MAP_END
	434
	435	static ADDRESS_MAP_START( sd725_io, AS_IO, 8, spc1000_state )
	436	ADDRESS_MAP_UNMAP_HIGH
	437	ADDRESS_MAP_GLOBAL_MASK(0xff)
	438	AM_RANGE(0xf8, 0xf8) AM_READWRITE(upd765_tc_r,fdc_control_w) // (R) Terminal Count Port (W) Motor Control Port
	439	AM_RANGE(0xfa, 0xfb) AM_DEVICE("upd765", upd765a_device, map )
	440	AM_RANGE(0xfc, 0xff) AM_DEVREADWRITE("d8255_master", i8255_device, read, write)
	441	ADDRESS_MAP_END
	442
591	443	static MACHINE_CONFIG_START( spc1000, spc1000_state )
592	444	/* basic machine hardware */
593	445	MCFG_CPU_ADD("maincpu",Z80, XTAL_4MHz)
594	446	MCFG_CPU_PROGRAM_MAP(spc1000_mem)
595	447	MCFG_CPU_IO_MAP(spc1000_io)
596	448
	449	/* sub CPU(5 inch floppy drive) */
	450	MCFG_CPU_ADD("fdccpu", Z80, XTAL_4MHz)       /* 4 MHz */
	451	MCFG_CPU_PROGRAM_MAP(sd725_mem)
	452	MCFG_CPU_IO_MAP(sd725_io)
	453
	454	MCFG_DEVICE_ADD("d8255_master", I8255, 0)
	455	MCFG_I8255_IN_PORTA_CB(DEVREAD8("d8255_master", i8255_device, pb_r))
	456	MCFG_I8255_IN_PORTB_CB(DEVREAD8("d8255_master", i8255_device, pa_r))
	457	MCFG_I8255_OUT_PORTB_CB(WRITE8(spc1000_state, fdc_8255_b_w))
	458	MCFG_I8255_IN_PORTC_CB(READ8(spc1000_state, fdc_8255_c_r))
	459	MCFG_I8255_OUT_PORTC_CB(WRITE8(spc1000_state, fdc_8255_c_w))
	460
	461	// floppy disk controller
	462	MCFG_UPD765A_ADD("upd765", true, true)
	463	MCFG_UPD765_INTRQ_CALLBACK(INPUTLINE("fdccpu", INPUT_LINE_IRQ0))
	464
	465	// floppy drives
	466	MCFG_FLOPPY_DRIVE_ADD("upd765:0", sd725_floppies, "sd320", floppy_image_device::default_floppy_formats)
	467	MCFG_FLOPPY_DRIVE_ADD("upd765:1", sd725_floppies, "sd320", floppy_image_device::default_floppy_formats)
	468	//CFG_SOFTWARE_LIST_ADD("disk_list","spc1000_flop")
	469
597	470	/* video hardware */
598	471	MCFG_SCREEN_MC6847_NTSC_ADD("screen", "mc6847")
599	472
r32636	r32637
625	498	ROM_START( spc1000 )
626	499	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASEFF )
627	500	ROM_LOAD( "spcall.rom", 0x0000, 0x8000, CRC(19638fc9) SHA1(489f1baa7aebf3c8c660325fb1fd790d84203284))
	501
	502	ROM_REGION( 0x10000, "fdccpu", 0)
	503	ROM_LOAD("sd725a.bin", 0x0000, 0x1000, CRC(96ac2eb8) SHA1(8e9d8f63a7fb87af417e95603e71cf537a6e83f1))
628	504	ROM_END
629	505
630	506	#if 0

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