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r32633 Friday 10th October, 2014 at 21:11:16 UTC by David Haywood
untangle some drivers from st0016_state now that it's a device (nw)

[src/mame]	mame.mak
[src/mame/drivers]	jclub2.c macs.c simple_st0016.c* speglsht.c srmp5.c st0016.c
[src/mame/includes]	simple_st0016.h* st0016.h
[src/mame/video]	st0016.c

trunk/src/mame/includes/st0016.h

r32632	r32633
1
2		#include "machine/st0016.h"
3
4		class st0016_state : public driver_device
5		{
6		public:
7		st0016_state(const machine_config &mconfig, device_type type, const char *tag)
8		: driver_device(mconfig, type, tag),
9		m_maincpu(*this,"maincpu"),
10		m_subcpu(*this, "sub"),
11		m_screen(*this, "screen")
12		{ }
13
14		int mux_port;
15		UINT32 m_st0016_rom_bank;
16
17		optional_device<st0016_cpu_device> m_maincpu;
18		DECLARE_READ8_MEMBER(mux_r);
19		DECLARE_WRITE8_MEMBER(mux_select_w);
20		DECLARE_READ32_MEMBER(latch32_r);
21		DECLARE_WRITE32_MEMBER(latch32_w);
22		DECLARE_READ8_MEMBER(latch8_r);
23		DECLARE_WRITE8_MEMBER(latch8_w);
24
25		DECLARE_WRITE8_MEMBER(st0016_rom_bank_w);
26		DECLARE_DRIVER_INIT(nratechu);
27		DECLARE_DRIVER_INIT(mayjinsn);
28		DECLARE_DRIVER_INIT(mayjisn2);
29		DECLARE_DRIVER_INIT(renju);
30		DECLARE_VIDEO_START(st0016);
31		void st0016_draw_screen(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
32		UINT32 screen_update_st0016(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
33		TIMER_DEVICE_CALLBACK_MEMBER(st0016_int);
34		optional_device<cpu_device> m_subcpu;
35		required_device<screen_device> m_screen;
36		};
37
38
39		/*----------- defined in video/st0016.c -----------*/
40
41		extern UINT8 macs_cart_slot;

trunk/src/mame/includes/simple_st0016.h

r0	r32633
	1
	2	#include "machine/st0016.h"
	3
	4	class st0016_state : public driver_device
	5	{
	6	public:
	7	st0016_state(const machine_config &mconfig, device_type type, const char *tag)
	8	: driver_device(mconfig, type, tag),
	9	m_maincpu(*this,"maincpu"),
	10	m_subcpu(*this, "sub"),
	11	m_screen(*this, "screen")
	12	{ }
	13
	14	int mux_port;
	15	//   UINT32 m_st0016_rom_bank;
	16
	17	optional_device<st0016_cpu_device> m_maincpu;
	18	DECLARE_READ8_MEMBER(mux_r);
	19	DECLARE_WRITE8_MEMBER(mux_select_w);
	20	DECLARE_READ32_MEMBER(latch32_r);
	21	DECLARE_WRITE32_MEMBER(latch32_w);
	22	DECLARE_READ8_MEMBER(latch8_r);
	23	DECLARE_WRITE8_MEMBER(latch8_w);
	24
	25	DECLARE_WRITE8_MEMBER(st0016_rom_bank_w);
	26	DECLARE_DRIVER_INIT(nratechu);
	27	DECLARE_DRIVER_INIT(mayjinsn);
	28	DECLARE_DRIVER_INIT(mayjisn2);
	29	DECLARE_DRIVER_INIT(renju);
	30	DECLARE_VIDEO_START(st0016);
	31	void st0016_draw_screen(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	32	UINT32 screen_update_st0016(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	33	TIMER_DEVICE_CALLBACK_MEMBER(st0016_int);
	34	optional_device<cpu_device> m_subcpu;
	35	required_device<screen_device> m_screen;
	36	};
	37
	38
	39	/*----------- defined in video/st0016.c -----------*/
	40
	41	extern UINT8 macs_cart_slot;

Property changes on: trunk/src/mame/includes/simple_st0016.h

Added: svn:eol-style    + native Added: svn:mime-type    + text/plain

trunk/src/mame/mame.mak

r32632	r32633
1791	1791	$(DRIVERS)/srmp6.o \
1792	1792	$(DRIVERS)/ssv.o $(VIDEO)/ssv.o \
1793	1793	$(VIDEO)/st0020.o \
1794		$(MACHINE)/st0016.o $(DRIVERS)/st0016.o $(VIDEO)/st0016.o \
	1794	$(MACHINE)/st0016.o $(DRIVERS)/simple_st0016.o \
1795	1795	$(VIDEO)/seta001.o \
1796	1796
1797	1797	$(MAMEOBJ)/sigma.a: \

trunk/src/mame/video/st0016.c

r32632	r32633
1		/************************************
2		Seta custom ST-0016 chip
3		driver by Tomasz Slanina
4		************************************/
5
6		#include "emu.h"
7		#include "includes/st0016.h"
8
9		UINT32 st0016_state::screen_update_st0016(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
10		{
11		return m_maincpu->update(screen,bitmap,cliprect);
12		}
13
14		VIDEO_START_MEMBER(st0016_state, st0016)
15		{
16		}
17

trunk/src/mame/drivers/st0016.c

r32632	r32633
1		/*******************************************
2		Seta custom ST-0016 chip based games.
3		driver by Tomasz Slanina
4		********************************************
5
6		Todo:
7		- find NMI source, and NMI enable/disable (timer ? video hw ?)
8
9		Dips verified for Neratte Chu (nratechu) from manual
10		*/
11
12		#include "emu.h"
13		#include "cpu/v810/v810.h"
14		#include "cpu/z80/z80.h"
15		#include "sound/st0016.h"
16		#include "includes/st0016.h"
17		#include "machine/st0016.h"
18
19
20		UINT32 st0016_rom_bank;
21
22		/*************************************
23		*
24		*  Machine's structure ST0016
25		*
26		*************************************/
27
28		static ADDRESS_MAP_START( st0016_mem, AS_PROGRAM, 8, st0016_state )
29		AM_RANGE(0x0000, 0x7fff) AM_ROM
30		AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1")
31		AM_RANGE(0xe000, 0xe7ff) AM_RAM
32		AM_RANGE(0xe800, 0xe87f) AM_RAM /* common ram */
33		AM_RANGE(0xf000, 0xffff) AM_RAM /* work ram */
34		ADDRESS_MAP_END
35
36		static ADDRESS_MAP_START( renju_mem, AS_PROGRAM, 8, st0016_state )
37		AM_RANGE(0x0000, 0x7fff) AM_ROM AM_REGION("maincpu", 0x200000 )
38		AM_IMPORT_FROM( st0016_mem )
39		ADDRESS_MAP_END
40
41
42		READ8_MEMBER(st0016_state::mux_r)
43		{
44		/*
45		76543210
46		xxxx - input port #2
47		xxxx     - dip switches (2x8 bits) (multiplexed)
48		*/
49		int retval = ioport("SYSTEM")->read() & 0x0f;
50
51		switch(mux_port & 0x30)
52		{
53		case 0x00: retval |= ((ioport("DSW1")->read() & 1) << 4) | ((ioport("DSW1")->read() & 0x10) << 1)
54		| ((ioport("DSW2")->read() & 1) << 6) | ((ioport("DSW2")->read() & 0x10) <<3); break;
55		case 0x10: retval |= ((ioport("DSW1")->read() & 2) << 3) | ((ioport("DSW1")->read() & 0x20)   )
56		| ((ioport("DSW2")->read() & 2) << 5) | ((ioport("DSW2")->read() & 0x20) <<2); break;
57		case 0x20: retval |= ((ioport("DSW1")->read() & 4) << 2) | ((ioport("DSW1")->read() & 0x40) >> 1)
58		| ((ioport("DSW2")->read() & 4) << 4) | ((ioport("DSW2")->read() & 0x40) <<1); break;
59		case 0x30: retval |= ((ioport("DSW1")->read() & 8) << 1) | ((ioport("DSW1")->read() & 0x80) >> 2)
60		| ((ioport("DSW2")->read() & 8) << 3) | ((ioport("DSW2")->read() & 0x80)    ); break;
61		}
62
63		return retval;
64		}
65
66		WRITE8_MEMBER(st0016_state::mux_select_w)
67		{
68		mux_port=data;
69		}
70
71		WRITE8_MEMBER(st0016_state::st0016_rom_bank_w)
72		{
73		membank("bank1")->set_base(memregion("maincpu")->base() + (data* 0x4000));
74		st0016_rom_bank=data;
75		}
76
77		static ADDRESS_MAP_START( st0016_io, AS_IO, 8, st0016_state )
78		ADDRESS_MAP_GLOBAL_MASK(0xff)
79		AM_RANGE(0xc0, 0xc0) AM_READ_PORT("P1") AM_WRITE(mux_select_w)
80		AM_RANGE(0xc1, 0xc1) AM_READ_PORT("P2") AM_WRITENOP
81		AM_RANGE(0xc2, 0xc2) AM_READ(mux_r) AM_WRITENOP
82		AM_RANGE(0xc3, 0xc3) AM_READ_PORT("P2") AM_WRITENOP
83		AM_RANGE(0xe0, 0xe0) AM_WRITENOP /* renju = $40, neratte = 0 */
84		AM_RANGE(0xe1, 0xe1) AM_WRITE(st0016_rom_bank_w)
85		AM_RANGE(0xe6, 0xe6) AM_WRITENOP /* banking ? ram bank ? shared rambank ? */
86		AM_RANGE(0xe7, 0xe7) AM_WRITENOP /* watchdog */
87		ADDRESS_MAP_END
88
89
90		/*************************************
91		*
92		*  Machine's structure ST0016 + V810
93		*
94		*************************************/
95
96		static UINT32 latches[8];
97
98		READ32_MEMBER(st0016_state::latch32_r)
99		{
100		if(!offset)
101		latches[2]&=~2;
102		return latches[offset];
103		}
104
105		WRITE32_MEMBER(st0016_state::latch32_w)
106		{
107		if(!offset)
108		latches[2]|=1;
109		COMBINE_DATA(&latches[offset]);
110		machine().scheduler().synchronize();
111		}
112
113		READ8_MEMBER(st0016_state::latch8_r)
114		{
115		if(!offset)
116		latches[2]&=~1;
117		return latches[offset];
118		}
119
120		WRITE8_MEMBER(st0016_state::latch8_w)
121		{
122		if(!offset)
123		latches[2]|=2;
124		latches[offset]=data;
125		machine().scheduler().synchronize();
126		}
127
128		static ADDRESS_MAP_START( v810_mem,AS_PROGRAM, 32, st0016_state )
129		AM_RANGE(0x00000000, 0x0001ffff) AM_RAM
130		AM_RANGE(0x80000000, 0x8001ffff) AM_RAM
131		AM_RANGE(0xc0000000, 0xc001ffff) AM_RAM
132		AM_RANGE(0x40000000, 0x4000000f) AM_READ(latch32_r) AM_WRITE(latch32_w)
133		AM_RANGE(0xfff80000, 0xffffffff) AM_ROMBANK("bank2")
134		ADDRESS_MAP_END
135
136		static ADDRESS_MAP_START( st0016_m2_io, AS_IO, 8, st0016_state )
137		ADDRESS_MAP_GLOBAL_MASK(0xff)
138		AM_RANGE(0xc0, 0xc3) AM_READ(latch8_r) AM_WRITE(latch8_w)
139		AM_RANGE(0xd0, 0xd0) AM_READ_PORT("P1") AM_WRITE(mux_select_w)
140		AM_RANGE(0xd1, 0xd1) AM_READ_PORT("P2") AM_WRITENOP
141		AM_RANGE(0xd2, 0xd2) AM_READ(mux_r) AM_WRITENOP
142		AM_RANGE(0xd3, 0xd3) AM_READ_PORT("P2") AM_WRITENOP
143		AM_RANGE(0xe0, 0xe0) AM_WRITENOP
144		AM_RANGE(0xe1, 0xe1) AM_WRITE(st0016_rom_bank_w)
145		AM_RANGE(0xe6, 0xe6) AM_WRITENOP /* banking ? ram bank ? shared rambank ? */
146		AM_RANGE(0xe7, 0xe7) AM_WRITENOP /* watchdog */
147		ADDRESS_MAP_END
148
149		/*************************************
150		*
151		*  Generic port definitions
152		*
153		*************************************/
154		static INPUT_PORTS_START( st0016 )
155		PORT_START("P1")
156		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
157		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
158		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
159		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
160		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
161		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
162		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
163		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
164
165		PORT_START("P2")
166		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
167		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
168		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
169		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
170		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
171		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
172		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
173		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
174
175		PORT_START("SYSTEM")
176		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
177		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
178		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
179		PORT_SERVICE( 0x08, IP_ACTIVE_LOW)
180
181		PORT_START("UNK")
182		PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* unused ? */
183
184		PORT_START("DSW1")
185		PORT_DIPUNKNOWN_DIPLOC( 0x01, IP_ACTIVE_LOW, "SW1:1" )
186		PORT_DIPUNKNOWN_DIPLOC( 0x02, IP_ACTIVE_LOW, "SW1:2" )
187		PORT_DIPUNKNOWN_DIPLOC( 0x04, IP_ACTIVE_LOW, "SW1:3" )
188		PORT_DIPUNKNOWN_DIPLOC( 0x08, IP_ACTIVE_LOW, "SW1:4" )
189		PORT_DIPUNKNOWN_DIPLOC( 0x10, IP_ACTIVE_LOW, "SW1:5" )
190		PORT_DIPUNKNOWN_DIPLOC( 0x20, IP_ACTIVE_LOW, "SW1:6" )
191		PORT_DIPUNKNOWN_DIPLOC( 0x40, IP_ACTIVE_LOW, "SW1:7" )
192		PORT_DIPUNKNOWN_DIPLOC( 0x80, IP_ACTIVE_LOW, "SW1:8" )
193
194		PORT_START("DSW2")
195		PORT_DIPUNKNOWN_DIPLOC( 0x01, IP_ACTIVE_LOW, "SW2:1" )
196		PORT_DIPUNKNOWN_DIPLOC( 0x02, IP_ACTIVE_LOW, "SW2:2" )
197		PORT_DIPUNKNOWN_DIPLOC( 0x04, IP_ACTIVE_LOW, "SW2:3" )
198		PORT_DIPUNKNOWN_DIPLOC( 0x08, IP_ACTIVE_LOW, "SW2:4" )
199		PORT_DIPUNKNOWN_DIPLOC( 0x10, IP_ACTIVE_LOW, "SW2:5" )
200		PORT_DIPUNKNOWN_DIPLOC( 0x20, IP_ACTIVE_LOW, "SW2:6" )
201		PORT_DIPUNKNOWN_DIPLOC( 0x40, IP_ACTIVE_LOW, "SW2:7" )
202		PORT_DIPUNKNOWN_DIPLOC( 0x80, IP_ACTIVE_LOW, "SW2:8" )
203		INPUT_PORTS_END
204
205		/*************************************
206		*
207		*  Game-specific port definitions
208		*
209		*************************************/
210
211		static INPUT_PORTS_START( renju )
212		PORT_INCLUDE( st0016 )
213
214		PORT_MODIFY("SYSTEM")
215		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
216		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
217
218		PORT_MODIFY("DSW1") /* Dip switch A  */
219		PORT_DIPNAME( 0x02, 0x02, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:2")
220		PORT_DIPSETTING(    0x02, DEF_STR( Off ) )
221		PORT_DIPSETTING(    0x00, DEF_STR( On ) )
222		PORT_SERVICE_DIPLOC(  0x04, IP_ACTIVE_LOW, "SW1:3" )
223		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:4")
224		PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
225		PORT_DIPSETTING(    0x08, DEF_STR( On ) )
226		PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SW1:5,6")
227		PORT_DIPSETTING(    0x20, DEF_STR( 2C_1C ) )
228		PORT_DIPSETTING(    0x30, DEF_STR( 1C_1C ) )
229		PORT_DIPSETTING(    0x00, DEF_STR( 2C_3C ) )
230		PORT_DIPSETTING(    0x10, DEF_STR( 1C_2C ) )
231		PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SW1:7,8")
232		PORT_DIPSETTING(    0x80, DEF_STR( 2C_1C ) )
233		PORT_DIPSETTING(    0xc0, DEF_STR( 1C_1C ) )
234		PORT_DIPSETTING(    0x00, DEF_STR( 2C_3C ) )
235		PORT_DIPSETTING(    0x80, DEF_STR( 1C_2C ) )
236
237		PORT_MODIFY("DSW2") /* Dip switch B */
238		PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:1,2")
239		PORT_DIPSETTING(    0x00, DEF_STR( Very_Hard ) )
240		PORT_DIPSETTING(    0x01, DEF_STR( Hard ) )
241		PORT_DIPSETTING(    0x02, DEF_STR( Easy ) )
242		PORT_DIPSETTING(    0x03, DEF_STR( Normal ) )
243		INPUT_PORTS_END
244
245		static INPUT_PORTS_START( koikois )
246		PORT_INCLUDE( st0016 )
247
248		PORT_MODIFY("P1")
249		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
250		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
251		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
252
253		PORT_MODIFY("SYSTEM")
254		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
255		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
256
257		PORT_MODIFY("DSW1") /* Dip switch A  */
258		PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:1")
259		PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
260		PORT_DIPSETTING(    0x00, DEF_STR( On ) )
261		PORT_DIPNAME( 0x02, 0x02, "Crt Mode" ) PORT_DIPLOCATION("SW1:2") // flip screen ?
262		PORT_DIPSETTING(    0x02, DEF_STR( Off ) )
263		PORT_DIPSETTING(    0x00, DEF_STR( On ) )
264		PORT_SERVICE_DIPLOC(  0x04, IP_ACTIVE_LOW, "SW1:3" )
265		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:4")
266		PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
267		PORT_DIPSETTING(    0x08, DEF_STR( On ) )
268		PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SW1:5,6")
269		PORT_DIPSETTING(    0x10, DEF_STR( 2C_1C ) )
270		PORT_DIPSETTING(    0x30, DEF_STR( 1C_1C ) )
271		PORT_DIPSETTING(    0x00, DEF_STR( 2C_3C ) )
272		PORT_DIPSETTING(    0x20, DEF_STR( 1C_2C ) )
273		PORT_DIPNAME( 0x40, 0x40,  DEF_STR( Controls ) ) PORT_DIPLOCATION("SW1:7")
274		PORT_DIPSETTING(    0x00, "Majyan Panel" )
275		PORT_DIPSETTING(    0x40, DEF_STR( Joystick ) )
276
277		PORT_MODIFY("DSW2") /* Dip switch B */
278		PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:1,2")
279		PORT_DIPSETTING(    0x00, DEF_STR( Very_Hard ) )
280		PORT_DIPSETTING(    0x01, DEF_STR( Hard ) )
281		PORT_DIPSETTING(    0x02, DEF_STR( Easy ) )
282		PORT_DIPSETTING(    0x03, DEF_STR( Normal ) )
283		INPUT_PORTS_END
284
285		static INPUT_PORTS_START( nratechu )
286		PORT_INCLUDE( st0016 )
287
288		PORT_MODIFY("SYSTEM")
289		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
290		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
291
292		PORT_MODIFY("DSW1") /* Dip switch A  */
293		PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:1,2,3")
294		PORT_DIPSETTING(    0x00, DEF_STR( 5C_1C ) )
295		PORT_DIPSETTING(    0x01, DEF_STR( 4C_1C ) )
296		PORT_DIPSETTING(    0x02, DEF_STR( 3C_1C ) )
297		PORT_DIPSETTING(    0x03, DEF_STR( 2C_1C ) )
298		PORT_DIPSETTING(    0x07, DEF_STR( 1C_1C ) )
299		PORT_DIPSETTING(    0x06, DEF_STR( 1C_2C ) )
300		PORT_DIPSETTING(    0x05, DEF_STR( 1C_3C ) )
301		PORT_DIPSETTING(    0x04, DEF_STR( 1C_4C ) )
302		PORT_DIPUNUSED_DIPLOC( 0x08, 0x08, "SW1:4" )
303		PORT_DIPUNUSED_DIPLOC( 0x10, 0x10, "SW1:5" )
304		PORT_DIPUNUSED_DIPLOC( 0x20, 0x20, "SW1:6" )
305		PORT_DIPNAME( 0x40, 0x40, "How To Play" ) PORT_DIPLOCATION("SW1:7")
306		PORT_DIPSETTING(    0x00, DEF_STR( No ) )
307		PORT_DIPSETTING(    0x40, DEF_STR( Yes ) )
308		PORT_DIPNAME( 0x80, 0x80, DEF_STR( Language ) ) PORT_DIPLOCATION("SW1:8")
309		PORT_DIPSETTING(    0x00, DEF_STR( English ) )
310		PORT_DIPSETTING(    0x80, DEF_STR( Japanese ) )
311
312		PORT_MODIFY("DSW2") /* Dip switch B */
313		PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:1,2") //  speed / time..
314		PORT_DIPSETTING(    0x02, DEF_STR( Easy ) )
315		PORT_DIPSETTING(    0x03, DEF_STR( Normal ))
316		PORT_DIPSETTING(    0x01, DEF_STR( Hard ) )
317		PORT_DIPSETTING(    0x00, DEF_STR( Hardest ) )
318		PORT_DIPNAME( 0x0C, 0x0c, "VS Round" ) PORT_DIPLOCATION("SW2:3,4")
319		PORT_DIPSETTING(    0x00, "First one to win" )
320		PORT_DIPSETTING(    0x04, "Best 4 out of 7" )
321		PORT_DIPSETTING(    0x08, "Best 3 out of 5" )
322		PORT_DIPSETTING(    0x0C, "Best 2 out of 3" )
323		PORT_DIPUNUSED_DIPLOC( 0x10, 0x10, "SW2:5" )
324		PORT_DIPNAME( 0x20, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW2:6") // Manual has this Defaulted OFF
325		PORT_DIPSETTING(    0x20, DEF_STR( Off ) )
326		PORT_DIPSETTING(    0x00, DEF_STR( On ) )
327		PORT_DIPNAME( 0x40, 0x40, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW2:7")
328		PORT_DIPSETTING(    0x40, DEF_STR( Off ) )
329		PORT_DIPSETTING(    0x00, DEF_STR( On ) )
330		PORT_SERVICE_DIPLOC(  0x80, IP_ACTIVE_LOW, "SW2:8" )
331		INPUT_PORTS_END
332
333		static INPUT_PORTS_START( mayjisn2 )
334		PORT_INCLUDE( st0016 )
335
336		PORT_MODIFY("SYSTEM")
337		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
338
339		PORT_MODIFY("DSW1") /* Dip switch A  */
340		PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:1,2,3")
341		PORT_DIPSETTING(    0x01, DEF_STR( 4C_1C ) )
342		PORT_DIPSETTING(    0x02, DEF_STR( 3C_1C ) )
343		PORT_DIPSETTING(    0x03, DEF_STR( 2C_1C ) )
344		PORT_DIPSETTING(    0x07, DEF_STR( 1C_1C ) )
345		PORT_DIPSETTING(    0x06, DEF_STR( 1C_2C ) )
346		PORT_DIPSETTING(    0x05, DEF_STR( 1C_3C ) )
347		PORT_DIPSETTING(    0x04, DEF_STR( 1C_4C ) )
348		PORT_DIPNAME( 0x18, 0x18, "Timer" ) PORT_DIPLOCATION("SW1:4,5")
349		PORT_DIPSETTING(    0x00, "6:00" )
350		PORT_DIPSETTING(    0x08, "5:00" )
351		PORT_DIPSETTING(    0x18, "4:00" )
352		PORT_DIPSETTING(    0x10, "3:00" )
353
354		PORT_MODIFY("DSW2") /* Dip switch B */
355		PORT_DIPNAME( 0x18, 0x18, "Music in Game"  ) PORT_DIPLOCATION("SW2:4,5")
356		PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
357		PORT_DIPSETTING(    0x08, "Remixed" )
358		PORT_DIPSETTING(    0x18, "Only Intro" )
359		PORT_DIPSETTING(    0x10, "Classic" )
360		PORT_DIPNAME( 0x20, 0x20, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW2:6")
361		PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
362		PORT_DIPSETTING(    0x20, DEF_STR( On ) )
363		PORT_DIPNAME( 0x40, 0x40, "Position of Title" ) PORT_DIPLOCATION("SW2:7")
364		PORT_DIPSETTING(    0x00, "B" )
365		PORT_DIPSETTING(    0x40, "A" )
366		INPUT_PORTS_END
367
368		static GFXDECODE_START( st0016 )
369		//  GFXDECODE_ENTRY( NULL, 0, charlayout,      0, 16*4  )
370		GFXDECODE_END
371
372		TIMER_DEVICE_CALLBACK_MEMBER(st0016_state::st0016_int)
373		{
374		int scanline = param;
375
376		if(scanline == 240)
377		m_maincpu->set_input_line(0,HOLD_LINE);
378		else if((scanline % 64) == 0)
379		if(m_maincpu->state_int(Z80_IFF1)) /* dirty hack ... */
380		m_maincpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE );
381		}
382
383
384
385
386		/*************************************
387		*
388		*  Machine driver(s)
389		*
390		*************************************/
391
392		static MACHINE_CONFIG_START( st0016, st0016_state )
393		/* basic machine hardware */
394		MCFG_CPU_ADD("maincpu",ST0016_CPU,8000000) /* 8 MHz ? */
395		MCFG_CPU_PROGRAM_MAP(st0016_mem)
396		MCFG_CPU_IO_MAP(st0016_io)
397		MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", st0016_state, st0016_int, "screen", 0, 1)
398
399		/* video hardware */
400		MCFG_SCREEN_ADD("screen", RASTER)
401		MCFG_SCREEN_REFRESH_RATE(60)
402		MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
403		MCFG_SCREEN_SIZE(48*8, 48*8)
404		MCFG_SCREEN_VISIBLE_AREA(0*8, 48*8-1, 0*8, 48*8-1)
405		MCFG_SCREEN_UPDATE_DRIVER(st0016_state, screen_update_st0016)
406		MCFG_SCREEN_PALETTE("maincpu:palette")
407
408
409		MCFG_VIDEO_START_OVERRIDE(st0016_state,st0016)
410
411		MACHINE_CONFIG_END
412
413		static MACHINE_CONFIG_DERIVED( mayjinsn, st0016 )
414		MCFG_CPU_MODIFY("maincpu")
415		MCFG_CPU_IO_MAP(st0016_m2_io)
416		MCFG_CPU_ADD("sub", V810, 10000000)//25 Mhz ?
417		MCFG_CPU_PROGRAM_MAP(v810_mem)
418		MCFG_QUANTUM_TIME(attotime::from_hz(60))
419		MACHINE_CONFIG_END
420
421		static MACHINE_CONFIG_DERIVED( renju, st0016 )
422		MCFG_CPU_MODIFY("maincpu")
423		MCFG_CPU_PROGRAM_MAP(renju_mem)
424		MACHINE_CONFIG_END
425
426		/*************************************
427		*
428		*  ROM definition(s)
429		*
430		*************************************/
431		/*
432		Renjyu Kizoku
433		Visco, 1994
434
435		PCB Layout
436
437		E51-00001-A
438		|------------------------------------|
439		|AMP       UPD6376    424400  62256  |
440		|    VOL      RESET   424400  62256  |
441		|                                    |
442		| TD62064 74273                      |
443		|J        74273                      |
444		|A        74273            42.9545MHz|
445		|M                                   |
446		|M        74245         UNKNOWN      |
447		|A        74245          QFP208      |
448		|         74245                      |
449		|         74245                 48MHz|
450		|                                    |
451		|  74138  74138                      |
452		|  74253  74253       RNJ2           |
453		|                                    |
454		|  DSW1   DSW2        RENJYU-1  6264 |
455		|------------------------------------|
456
457		Note:
458		Unknown QFP (surface scratched off) is the CPU
459		+ GFX generator - it's possibly NEC V70/V810
460		*/
461
462		ROM_START( renju )
463		ROM_REGION( 0x280000, "maincpu", 0 )
464		ROM_LOAD( "renjyu-1.u31",0x000000, 0x200000, CRC(e0fdbe9b) SHA1(52d31024d1a88b8fcca1f87366fcaf80e3c387a1) )
465		ROM_LOAD( "rnj2.u32",    0x200000, 0x080000, CRC(2015289c) SHA1(5223b6d3dbe4657cd63cf5b527eaab84cf23587a ) )
466		ROM_END
467
468		ROM_START( nratechu )
469		ROM_REGION( 0x200000, "maincpu", 0 )
470		ROM_LOAD( "sx012-01",   0x000000, 0x080000, CRC(6ca01d57) SHA1(065848f19ecf2dc1f7bbc7ddd87bca502e4b8b16) )
471		ROM_LOAD( "sx012-02",   0x100000, 0x100000, CRC(40a4e354) SHA1(8120ce8deee6805050a5b083a334c3743c09566b) )
472		ROM_END
473
474		/* PCB E51-00001 (almost identical to above) */
475
476		ROM_START( dcrown )
477		ROM_REGION( 0x200000, "maincpu", 0 )
478		ROM_LOAD( "dc1.u31",0x000000, 0x80000, CRC(e55200b8) SHA1(20a968dc895bb636b064c29b4b53c6ffa49fea36) )
479		ROM_LOAD( "dc2.u32",0x080000, 0x80000, CRC(05b6192f) SHA1(6af6e7b2c681f2791a7f89a528a95eb976c8ba84) )
480		ROM_LOAD( "dc3.u33",0x100000, 0x80000, CRC(f23c1975) SHA1(118d6054922a733d23363c53bb331d84c78e50ad) )
481		ROM_LOAD( "dc4.u34",0x180000, 0x80000, CRC(0d1c2c61) SHA1(7e4dc20ab683ce0f61dd939cfd9b17714ba2343a) )
482		ROM_END
483
484		ROM_START( dcrowna )
485		ROM_REGION( 0x200000, "maincpu", 0 )
486		ROM_LOAD( "dcn-0.1c",     0x000000, 0x080000, CRC(5dd0615d) SHA1(b859994bd79229da4c687deefe1997313724b26e) )
487		ROM_LOAD( "dcn-1.1d",     0x080000, 0x080000, CRC(6c6f14e7) SHA1(2a3474e44420cc78e3ead777eb91481c4bb46eef) )
488		ROM_LOAD( "dcn-2.1e",     0x100000, 0x080000, CRC(e9401a5e) SHA1(db24ebe5a0073c7c1c2da957772e223545f3c778) )
489		ROM_LOAD( "dcn-3.1f",     0x180000, 0x080000, CRC(ec2e88bc) SHA1(2a8deee63e123dae411e2b834eca69be6f646d66) )
490		ROM_END
491
492		ROM_START( gostop )
493		ROM_REGION( 0x200000, "maincpu", 0 )
494		ROM_LOAD( "go-stop_rom1.u31",0x000000, 0x80000, CRC(93decaa2) SHA1(a30958b76dfe5752a341ecdc950119c10e864586) )
495		ROM_LOAD( "go-stop_rom2.u32",0x080000, 0x80000, CRC(3c5402ff) SHA1(bdc38922b5cbad0150adf9c6cc0fefc5705a16a2) )
496		ROM_END
497
498		/*
499		Koi Koi Shimasho
500		Visco
501
502		PCB Layout
503		----------
504
505		E63-00001
506		|---------------------------------------|
507		|VOL     RESET     TC514400   62256     |
508		|        UPD6376   TC514400   62256     |
509		|MJM2904                                |
510		|                                       |
511		|M                            42.9545MHz|
512		|A                   |----------|       |
513		|H                   |          |       |
514		|J                   | ST-0016  |       |
515		|O                   |          |  48MHz|
516		|N                   |          |       |
517		|G                   |          |       |
518		|5                   |----------|       |
519		|6                          BATTERY     |
520		|                                       |
521		|                                       |
522		|                              KOI-5    |
523		|   KOI-4   KOI-2   KOI-3  KOI-1    6264|
524		|---------------------------------------|
525
526		*/
527
528		ROM_START( koikois )
529		ROM_REGION( 0x400000, "maincpu", 0 )
530		ROM_LOAD16_BYTE( "koi-2.6c", 0x000001, 0x080000, CRC(2722be71) SHA1(1aa3d819eef01db042ee04a01c1b18c4d9dae65e) )
531		ROM_LOAD16_BYTE( "koi-1.4c", 0x000000, 0x080000, CRC(c79e2b43) SHA1(868174f7ab8e68e31d3302ae94dd742048deed9f) )
532		ROM_LOAD16_BYTE( "koi-4.8c", 0x100001, 0x080000, CRC(ace236df) SHA1(4bf56affe5b6d0ba3cc677eaa91f9be77f26c654) )
533		ROM_LOAD16_BYTE( "koi-3.5c", 0x100000, 0x080000, CRC(6fd88149) SHA1(87b1be32770232eb041e3ef9d1da45282af8a5d4) )
534		ROM_LOAD( "koi-5.2c", 0x200000, 0x200000, CRC(561e12c8) SHA1(a7aedf549bc3141fc01bc4a10c235af265ba4ee9) )
535		ROM_END
536
537
538		/*
539		Mayjinsen (JPN Ver.)
540		(c)1994 Seta
541
542		CPU:    UPD70732-25 V810 ?
543		Sound:  Custom (ST-0016 ?)
544
545		sx003.01    main prg
546		sx003.02
547		sx003.03
548		sx003.04    /
549
550		sx003.05d   chr
551		sx003.06
552		sx003.07d   /
553
554		-----------
555
556		Mayjinsen II
557		Seta, 1994
558
559		This game runs on Seta hardware. The game is similar to Shougi.
560
561		PCB Layout
562		----------
563
564		E52-00001
565		|----------------------------------------------------|
566		|                  62256    62256    62256    62256  |
567		| D70732GD-25                                        |
568		| NEC 1991 V810    62256    62256    62256    62256  |
569		|                                                    |
570		|                  62256    62256    62256    62256  |
571		|                                                    |
572		|                SX007-01 SX007-02  SX007-03 SX007-04|
573		|                                                    |
574		|                                   6264             |
575		|                                                    |
576		|                   62256      42.9545MHz  48MHz     |
577		|      PAL                                           |
578		|                   62256                            |
579		| 46MHz                          ST-0016   SX007-05  |
580		|                                TC6210AF            |
581		|                                                    |
582		|                   TC514800                         |
583		|                                                    |
584		|                                           DSW1-8   |
585		|                                                    |
586		|                                           DSW2-8   |
587		|                           JAMMA                    |
588		|----------------------------------------------------|
589		*/
590
591		ROM_START(mayjinsn )
592		ROM_REGION( 0x180000, "maincpu", 0 )
593		ROM_LOAD( "sx003.05d",   0x000000, 0x80000, CRC(2be6d620) SHA1(113db888fb657d45be55708bbbf9a9ac159a9636) )
594		ROM_LOAD( "sx003.06",    0x080000, 0x80000, CRC(f0553386) SHA1(8915cb3ce03b9a12612694caec9bbec6de4dd070) )
595		ROM_LOAD( "sx003.07d",   0x100000, 0x80000, CRC(8db281c3) SHA1(f8b488dd28010f01f789217a4d62ba2116e06e94) )
596
597		ROM_REGION32_LE( 0x20000*4, "user1", 0 ) /* V810 code */
598		ROM_LOAD32_BYTE( "sx003.04",   0x00003, 0x20000,   CRC(fa15459f) SHA1(4163ab842943705c550f137abbdd2cb51ba5390f) )
599		ROM_LOAD32_BYTE( "sx003.03",   0x00002, 0x20000,   CRC(71a438ea) SHA1(613bab6a59aa1bced2ab37177c61a0fd7ce7e64f) )
600		ROM_LOAD32_BYTE( "sx003.02",   0x00001, 0x20000,   CRC(61911eed) SHA1(1442b3867b85120ba652ec8205d74332addffb67) )
601		ROM_LOAD32_BYTE( "sx003.01",   0x00000, 0x20000,   CRC(d210bfe5) SHA1(96d9f2b198d98125df4bd6b15705646d472a8a87) )
602		ROM_END
603
604		ROM_START(mayjisn2 )
605		ROM_REGION( 0x100000, "maincpu", 0 )
606		ROM_LOAD( "sx007-05.8b",   0x00000, 0x100000,  CRC(b13ea605) SHA1(75c067df02c988f170c24153d3852c472355fc9d) )
607
608		ROM_REGION32_LE( 0x20000*4, "user1", 0 ) /* V810 code */
609		ROM_LOAD32_BYTE( "sx007-04.4b",   0x00003, 0x20000,   CRC(fa15459f) SHA1(4163ab842943705c550f137abbdd2cb51ba5390f) )
610		ROM_LOAD32_BYTE( "sx007-03.4j",   0x00002, 0x20000,   CRC(71a438ea) SHA1(613bab6a59aa1bced2ab37177c61a0fd7ce7e64f) )
611		ROM_LOAD32_BYTE( "sx007-02.4m",   0x00001, 0x20000,   CRC(61911eed) SHA1(1442b3867b85120ba652ec8205d74332addffb67) )
612		ROM_LOAD32_BYTE( "sx007-01.4s",   0x00000, 0x20000,   CRC(d210bfe5) SHA1(96d9f2b198d98125df4bd6b15705646d472a8a87) )
613		ROM_END
614
615		/*************************************
616		*
617		*  Game-specific driver inits
618		*
619		*************************************/
620
621		DRIVER_INIT_MEMBER(st0016_state,renju)
622		{
623		m_maincpu->st0016_game=0;
624		}
625
626		DRIVER_INIT_MEMBER(st0016_state,nratechu)
627		{
628		m_maincpu->st0016_game=1;
629		}
630
631		DRIVER_INIT_MEMBER(st0016_state,mayjinsn)
632		{
633		m_maincpu->st0016_game=4;//|0x80;
634		membank("bank2")->set_base(memregion("user1")->base());
635		}
636
637		DRIVER_INIT_MEMBER(st0016_state,mayjisn2)
638		{
639		m_maincpu->st0016_game=4;
640		membank("bank2")->set_base(memregion("user1")->base());
641		}
642
643
644
645
646
647		/*************************************
648		*
649		*  Game driver(s)
650		*
651		*************************************/
652
653		GAME(  1994, renju,     0,      renju,    renju,   st0016_state,    renju,    ROT0, "Visco",     "Renju Kizoku", 0)
654		GAME(  1996, nratechu,  0,      st0016,   nratechu, st0016_state, nratechu, ROT0, "Seta",      "Neratte Chu", 0)
655		GAME(  1994, mayjisn2,  0,      mayjinsn, mayjisn2, st0016_state, mayjisn2, ROT0, "Seta",      "Mayjinsen 2", 0)
656		GAME(  1995, koikois,   0,      st0016,   koikois, st0016_state,  renju,    ROT0, "Visco",     "Koi Koi Shimasho", GAME_IMPERFECT_GRAPHICS)
657		/* Not working */
658		GAME( 1994, mayjinsn,   0,      mayjinsn, st0016, st0016_state,   mayjinsn, ROT0, "Seta",      "Mayjinsen",GAME_IMPERFECT_GRAPHICS|GAME_NOT_WORKING)
659		GAME( 1994, dcrown,     0,      st0016,   renju, st0016_state,    renju,    ROT0, "Nippon Data Kiki", "Dream Crown (Set 1)", GAME_NOT_WORKING) // (c) 1994 Nippon Data Kiki is uploaded near the Japanese Insert coin text
660		GAME( 1994, dcrowna,    dcrown, st0016,   renju, st0016_state,    renju,    ROT0, "Nippon Data Kiki", "Dream Crown (Set 2)", GAME_NOT_WORKING) // the Insert Coin text has been translated to English and no (c) is uploaded
661		GAME( 2001, gostop,     0,      st0016,   renju, st0016_state,    renju,    ROT0, "Visco", "Kankoku Hanafuda Go-Stop", GAME_NOT_WORKING)

trunk/src/mame/drivers/jclub2.c

r32632	r32633
96	96	#include "cpu/m68000/m68000.h"
97	97	#include "machine/eepromser.h"
98	98	#include "sound/okim6295.h"
99		#include "includes/st0016.h"
100	99	#include "machine/st0016.h"
101	100	#include "video/st0020.h"
102	101	#include "machine/nvram.h"
103	102
104		class darkhors_state : public st0016_state
	103	class darkhors_state : public driver_device
105	104	{
106	105	public:
107	106	darkhors_state(const machine_config &mconfig, device_type type, const char *tag)
108		: st0016_state(mconfig, type, tag),
	107	: driver_device(mconfig, type, tag),
109	108	m_tmapram(*this, "tmapram"),
110	109	m_tmapscroll(*this, "tmapscroll"),
111	110	m_tmapram2(*this, "tmapram2"),
r32632	r32633
158	157	TIMER_DEVICE_CALLBACK_MEMBER(darkhors_irq);
159	158	void draw_sprites_darkhors(bitmap_ind16 &bitmap, const rectangle &cliprect);
160	159	required_device<gfxdecode_device> m_gfxdecode;
	160
	161	WRITE8_MEMBER(st0016_rom_bank_w); // temp?
161	162	};
162	163
163	164
r32632	r32633
1046	1047	AM_RANGE(0xf000, 0xffff) AM_RAM
1047	1048	ADDRESS_MAP_END
1048	1049
	1050	// common rombank? should go in machine/st0016 with larger address space exposed?
	1051	WRITE8_MEMBER(darkhors_state::st0016_rom_bank_w)
	1052	{
	1053	membank("bank1")->set_base(memregion("maincpu")->base() + (data* 0x4000));
	1054	}
	1055
	1056
1049	1057	static ADDRESS_MAP_START( st0016_io, AS_IO, 8, darkhors_state )
1050	1058	ADDRESS_MAP_GLOBAL_MASK(0xff)
1051	1059	//AM_RANGE(0x00, 0xbf) AM_READ(st0016_vregs_r) AM_WRITE(st0016_vregs_w)

trunk/src/mame/drivers/srmp5.c

r32632	r32633
39	39	#include "emu.h"
40	40	#include "machine/st0016.h"
41	41	#include "cpu/mips/r3000.h"
42		#include "includes/st0016.h"
43	42
44	43	#define DEBUG_CHAR
45	44
r32632	r32633
62	61
63	62	#define SPRITE_DATA_GRANULARITY 0x80
64	63
65		class srmp5_state : public st0016_state
	64	class srmp5_state : public driver_device
66	65	{
67	66	public:
68	67	srmp5_state(const machine_config &mconfig, device_type type, const char *tag)
69		: st0016_state(mconfig, type, tag),
	68	: driver_device(mconfig, type, tag),
70	69	m_gfxdecode(*this, "gfxdecode"),
71		m_palette(*this, "palette")
	70	m_palette(*this, "palette"),
	71	m_maincpu(*this,"maincpu"),
	72	m_subcpu(*this, "sub")
72	73
73	74	{ }
74	75
r32632	r32633
110	111	UINT32 screen_update_srmp5(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
111	112	required_device<gfxdecode_device> m_gfxdecode;
112	113	required_device<palette_device> m_palette;
	114	optional_device<st0016_cpu_device> m_maincpu;
	115	optional_device<cpu_device> m_subcpu;
	116
	117	DECLARE_WRITE8_MEMBER(st0016_rom_bank_w);
113	118	};
114	119
115	120
r32632	r32633
398	403	return m_cmd_stat;
399	404	}
400	405
	406	// common rombank? should go in machine/st0016 with larger address space exposed?
	407	WRITE8_MEMBER(srmp5_state::st0016_rom_bank_w)
	408	{
	409	membank("bank1")->set_base(memregion("maincpu")->base() + (data* 0x4000));
	410	}
	411
	412
401	413	static ADDRESS_MAP_START( st0016_io, AS_IO, 8, srmp5_state )
402	414	ADDRESS_MAP_GLOBAL_MASK(0xff)
403	415	//AM_RANGE(0x00, 0xbf) AM_READ(st0016_vregs_r) AM_WRITE(st0016_vregs_w)
r32632	r32633
560	572	#ifdef DEBUG_CHAR
561	573	MCFG_GFXDECODE_ADD("gfxdecode", "palette", srmp5 )
562	574	#endif
563		MCFG_VIDEO_START_OVERRIDE(st0016_state,st0016)
	575	//MCFG_VIDEO_START_OVERRIDE(st0016_state,st0016)
564	576
565	577	MACHINE_CONFIG_END
566	578

trunk/src/mame/drivers/speglsht.c

r32632	r32633
106	106	#include "emu.h"
107	107	#include "machine/st0016.h"
108	108	#include "cpu/mips/r3000.h"
109		#include "includes/st0016.h"
110	109
111	110
112		class speglsht_state : public st0016_state
	111	class speglsht_state : public driver_device
113	112	{
114	113	public:
115	114	speglsht_state(const machine_config &mconfig, device_type type, const char *tag)
116		: st0016_state(mconfig, type, tag),
	115	: driver_device(mconfig, type, tag),
117	116	m_shared(*this, "shared"),
118	117	m_framebuffer(*this, "framebuffer"),
119	118	m_cop_ram(*this, "cop_ram"),
120		m_palette(*this, "palette")
	119	m_palette(*this, "palette"),
	120	m_maincpu(*this,"maincpu"),
	121	m_subcpu(*this, "sub")
121	122	{ }
122	123
123	124	required_shared_ptr<UINT8> m_shared;
r32632	r32633
136	137	DECLARE_VIDEO_START(speglsht);
137	138	UINT32 screen_update_speglsht(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
138	139	required_device<palette_device> m_palette;
	140	optional_device<st0016_cpu_device> m_maincpu;
	141	optional_device<cpu_device> m_subcpu;
139	142
	143	DECLARE_WRITE8_MEMBER(st0016_rom_bank_w);
140	144	};
141	145
142	146
r32632	r32633
153	157	AM_RANGE(0xf000, 0xffff) AM_RAM AM_SHARE("shared")
154	158	ADDRESS_MAP_END
155	159
	160	// common rombank? should go in machine/st0016 with larger address space exposed?
	161	WRITE8_MEMBER(speglsht_state::st0016_rom_bank_w)
	162	{
	163	membank("bank1")->set_base(memregion("maincpu")->base() + (data* 0x4000));
	164	}
	165
	166
156	167	static ADDRESS_MAP_START( st0016_io, AS_IO, 8, speglsht_state )
157	168	ADDRESS_MAP_GLOBAL_MASK(0xff)
158	169	//AM_RANGE(0x00, 0xbf) AM_READ(st0016_vregs_r) AM_WRITE(st0016_vregs_w)
r32632	r32633
333	344	VIDEO_START_MEMBER(speglsht_state,speglsht)
334	345	{
335	346	m_bitmap = auto_bitmap_ind16_alloc(machine(), 512, 5122 );
336		VIDEO_START_CALL_MEMBER(st0016);
	347	//   VIDEO_START_CALL_MEMBER(st0016);
337	348	}
338	349
339	350	#define PLOT_PIXEL_RGB(x,y,r,g,b)   if(y>=0 && x>=0 && x<512 && y<512) \

trunk/src/mame/drivers/macs.c

r32632	r32633
57	57
58	58	#include "emu.h"
59	59	#include "machine/st0016.h"
60		#include "includes/st0016.h"
61	60
62	61
63		class macs_state : public st0016_state
	62	class macs_state : public driver_device
64	63	{
65	64	public:
66	65	macs_state(const machine_config &mconfig, device_type type, const char *tag)
67		: st0016_state(mconfig, type, tag),
68		m_ram2(*this, "ram2") { }
	66	: driver_device(mconfig, type, tag),
	67	m_ram2(*this, "ram2"),
	68	m_maincpu(*this,"maincpu")
69	69
	70	{ }
	71
70	72	UINT8 m_mux_data;
71	73	UINT8 m_rev;
72	74	UINT8 *m_ram1;
r32632	r32633
80	82	DECLARE_DRIVER_INIT(kisekaem);
81	83	DECLARE_DRIVER_INIT(macs2);
82	84	DECLARE_MACHINE_RESET(macs);
	85
	86	UINT32 screen_update_macs(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	87
	88	optional_device<st0016_cpu_device> m_maincpu;
	89
83	90	};
84	91
85	92
r32632	r32633
142	149	{
143	150	membank("bank1")->set_base(memregion("maincpu")->base() + (data* 0x4000) + macs_cart_slot*0x400000 );
144	151
145		m_st0016_rom_bank=data;
	152	//   m_st0016_rom_bank=data;
146	153	}
147	154
148	155	WRITE8_MEMBER(macs_state::macs_output_w)
r32632	r32633
469	476	INPUT_PORTS_END
470	477
471	478
	479	UINT32 macs_state::screen_update_macs(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
	480	{
	481	return m_maincpu->update(screen,bitmap,cliprect);
	482	}
472	483
473	484
474	485	static MACHINE_CONFIG_START( macs, macs_state )
r32632	r32633
487	498	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
488	499	MCFG_SCREEN_SIZE(128*8, 128*8)
489	500	MCFG_SCREEN_VISIBLE_AREA(0*8, 128*8-1, 0*8, 128*8-1)
490		MCFG_SCREEN_UPDATE_DRIVER(st0016_state, screen_update_st0016)
	501	MCFG_SCREEN_UPDATE_DRIVER(macs_state, screen_update_macs)
491	502	MCFG_SCREEN_PALETTE("maincpu:palette")
492
493		MCFG_VIDEO_START_OVERRIDE(st0016_state,st0016)
494	503	MACHINE_CONFIG_END
495	504
496	505

trunk/src/mame/drivers/simple_st0016.c

r0	r32633
	1	/*******************************************
	2
	3	Seta custom ST-0016 chip based games.
	4	driver by Tomasz Slanina
	5
	6	this is for 'simple' games using the chip
	7	where the chip is providing the maincpu
	8	video, and sound functionality of the game
	9	rather than acting as a sub-cpu
	10
	11	********************************************
	12
	13	Todo:
	14	- find NMI source, and NMI enable/disable (timer ? video hw ?)
	15
	16	Dips verified for Neratte Chu (nratechu) from manual
	17	*/
	18
	19	#include "emu.h"
	20	#include "cpu/v810/v810.h"
	21	#include "cpu/z80/z80.h"
	22	#include "sound/st0016.h"
	23	#include "includes/simple_st0016.h"
	24	#include "machine/st0016.h"
	25
	26
	27
	28	/*************************************
	29	*
	30	*  Machine's structure ST0016
	31	*
	32	*************************************/
	33
	34	static ADDRESS_MAP_START( st0016_mem, AS_PROGRAM, 8, st0016_state )
	35	AM_RANGE(0x0000, 0x7fff) AM_ROM
	36	AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1")
	37	AM_RANGE(0xe000, 0xe7ff) AM_RAM
	38	AM_RANGE(0xe800, 0xe87f) AM_RAM /* common ram */
	39	AM_RANGE(0xf000, 0xffff) AM_RAM /* work ram */
	40	ADDRESS_MAP_END
	41
	42	static ADDRESS_MAP_START( renju_mem, AS_PROGRAM, 8, st0016_state )
	43	AM_RANGE(0x0000, 0x7fff) AM_ROM AM_REGION("maincpu", 0x200000 )
	44	AM_IMPORT_FROM( st0016_mem )
	45	ADDRESS_MAP_END
	46
	47
	48	READ8_MEMBER(st0016_state::mux_r)
	49	{
	50	/*
	51	76543210
	52	xxxx - input port #2
	53	xxxx     - dip switches (2x8 bits) (multiplexed)
	54	*/
	55	int retval = ioport("SYSTEM")->read() & 0x0f;
	56
	57	switch(mux_port & 0x30)
	58	{
	59	case 0x00: retval |= ((ioport("DSW1")->read() & 1) << 4) | ((ioport("DSW1")->read() & 0x10) << 1)
	60	| ((ioport("DSW2")->read() & 1) << 6) | ((ioport("DSW2")->read() & 0x10) <<3); break;
	61	case 0x10: retval |= ((ioport("DSW1")->read() & 2) << 3) | ((ioport("DSW1")->read() & 0x20)   )
	62	| ((ioport("DSW2")->read() & 2) << 5) | ((ioport("DSW2")->read() & 0x20) <<2); break;
	63	case 0x20: retval |= ((ioport("DSW1")->read() & 4) << 2) | ((ioport("DSW1")->read() & 0x40) >> 1)
	64	| ((ioport("DSW2")->read() & 4) << 4) | ((ioport("DSW2")->read() & 0x40) <<1); break;
	65	case 0x30: retval |= ((ioport("DSW1")->read() & 8) << 1) | ((ioport("DSW1")->read() & 0x80) >> 2)
	66	| ((ioport("DSW2")->read() & 8) << 3) | ((ioport("DSW2")->read() & 0x80)    ); break;
	67	}
	68
	69	return retval;
	70	}
	71
	72	WRITE8_MEMBER(st0016_state::mux_select_w)
	73	{
	74	mux_port=data;
	75	}
	76
	77	WRITE8_MEMBER(st0016_state::st0016_rom_bank_w)
	78	{
	79	membank("bank1")->set_base(memregion("maincpu")->base() + (data* 0x4000));
	80	//   st0016_rom_bank=data;
	81	}
	82
	83	static ADDRESS_MAP_START( st0016_io, AS_IO, 8, st0016_state )
	84	ADDRESS_MAP_GLOBAL_MASK(0xff)
	85	AM_RANGE(0xc0, 0xc0) AM_READ_PORT("P1") AM_WRITE(mux_select_w)
	86	AM_RANGE(0xc1, 0xc1) AM_READ_PORT("P2") AM_WRITENOP
	87	AM_RANGE(0xc2, 0xc2) AM_READ(mux_r) AM_WRITENOP
	88	AM_RANGE(0xc3, 0xc3) AM_READ_PORT("P2") AM_WRITENOP
	89	AM_RANGE(0xe0, 0xe0) AM_WRITENOP /* renju = $40, neratte = 0 */
	90	AM_RANGE(0xe1, 0xe1) AM_WRITE(st0016_rom_bank_w)
	91	AM_RANGE(0xe6, 0xe6) AM_WRITENOP /* banking ? ram bank ? shared rambank ? */
	92	AM_RANGE(0xe7, 0xe7) AM_WRITENOP /* watchdog */
	93	ADDRESS_MAP_END
	94
	95
	96	/*************************************
	97	*
	98	*  Machine's structure ST0016 + V810
	99	*
	100	*************************************/
	101
	102	static UINT32 latches[8];
	103
	104	READ32_MEMBER(st0016_state::latch32_r)
	105	{
	106	if(!offset)
	107	latches[2]&=~2;
	108	return latches[offset];
	109	}
	110
	111	WRITE32_MEMBER(st0016_state::latch32_w)
	112	{
	113	if(!offset)
	114	latches[2]|=1;
	115	COMBINE_DATA(&latches[offset]);
	116	machine().scheduler().synchronize();
	117	}
	118
	119	READ8_MEMBER(st0016_state::latch8_r)
	120	{
	121	if(!offset)
	122	latches[2]&=~1;
	123	return latches[offset];
	124	}
	125
	126	WRITE8_MEMBER(st0016_state::latch8_w)
	127	{
	128	if(!offset)
	129	latches[2]|=2;
	130	latches[offset]=data;
	131	machine().scheduler().synchronize();
	132	}
	133
	134	static ADDRESS_MAP_START( v810_mem,AS_PROGRAM, 32, st0016_state )
	135	AM_RANGE(0x00000000, 0x0001ffff) AM_RAM
	136	AM_RANGE(0x80000000, 0x8001ffff) AM_RAM
	137	AM_RANGE(0xc0000000, 0xc001ffff) AM_RAM
	138	AM_RANGE(0x40000000, 0x4000000f) AM_READ(latch32_r) AM_WRITE(latch32_w)
	139	AM_RANGE(0xfff80000, 0xffffffff) AM_ROMBANK("bank2")
	140	ADDRESS_MAP_END
	141
	142	static ADDRESS_MAP_START( st0016_m2_io, AS_IO, 8, st0016_state )
	143	ADDRESS_MAP_GLOBAL_MASK(0xff)
	144	AM_RANGE(0xc0, 0xc3) AM_READ(latch8_r) AM_WRITE(latch8_w)
	145	AM_RANGE(0xd0, 0xd0) AM_READ_PORT("P1") AM_WRITE(mux_select_w)
	146	AM_RANGE(0xd1, 0xd1) AM_READ_PORT("P2") AM_WRITENOP
	147	AM_RANGE(0xd2, 0xd2) AM_READ(mux_r) AM_WRITENOP
	148	AM_RANGE(0xd3, 0xd3) AM_READ_PORT("P2") AM_WRITENOP
	149	AM_RANGE(0xe0, 0xe0) AM_WRITENOP
	150	AM_RANGE(0xe1, 0xe1) AM_WRITE(st0016_rom_bank_w)
	151	AM_RANGE(0xe6, 0xe6) AM_WRITENOP /* banking ? ram bank ? shared rambank ? */
	152	AM_RANGE(0xe7, 0xe7) AM_WRITENOP /* watchdog */
	153	ADDRESS_MAP_END
	154
	155	/*************************************
	156	*
	157	*  Generic port definitions
	158	*
	159	*************************************/
	160	static INPUT_PORTS_START( st0016 )
	161	PORT_START("P1")
	162	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
	163	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
	164	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
	165	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
	166	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
	167	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
	168	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
	169	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
	170
	171	PORT_START("P2")
	172	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
	173	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
	174	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
	175	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
	176	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
	177	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
	178	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
	179	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
	180
	181	PORT_START("SYSTEM")
	182	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
	183	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
	184	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
	185	PORT_SERVICE( 0x08, IP_ACTIVE_LOW)
	186
	187	PORT_START("UNK")
	188	PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* unused ? */
	189
	190	PORT_START("DSW1")
	191	PORT_DIPUNKNOWN_DIPLOC( 0x01, IP_ACTIVE_LOW, "SW1:1" )
	192	PORT_DIPUNKNOWN_DIPLOC( 0x02, IP_ACTIVE_LOW, "SW1:2" )
	193	PORT_DIPUNKNOWN_DIPLOC( 0x04, IP_ACTIVE_LOW, "SW1:3" )
	194	PORT_DIPUNKNOWN_DIPLOC( 0x08, IP_ACTIVE_LOW, "SW1:4" )
	195	PORT_DIPUNKNOWN_DIPLOC( 0x10, IP_ACTIVE_LOW, "SW1:5" )
	196	PORT_DIPUNKNOWN_DIPLOC( 0x20, IP_ACTIVE_LOW, "SW1:6" )
	197	PORT_DIPUNKNOWN_DIPLOC( 0x40, IP_ACTIVE_LOW, "SW1:7" )
	198	PORT_DIPUNKNOWN_DIPLOC( 0x80, IP_ACTIVE_LOW, "SW1:8" )
	199
	200	PORT_START("DSW2")
	201	PORT_DIPUNKNOWN_DIPLOC( 0x01, IP_ACTIVE_LOW, "SW2:1" )
	202	PORT_DIPUNKNOWN_DIPLOC( 0x02, IP_ACTIVE_LOW, "SW2:2" )
	203	PORT_DIPUNKNOWN_DIPLOC( 0x04, IP_ACTIVE_LOW, "SW2:3" )
	204	PORT_DIPUNKNOWN_DIPLOC( 0x08, IP_ACTIVE_LOW, "SW2:4" )
	205	PORT_DIPUNKNOWN_DIPLOC( 0x10, IP_ACTIVE_LOW, "SW2:5" )
	206	PORT_DIPUNKNOWN_DIPLOC( 0x20, IP_ACTIVE_LOW, "SW2:6" )
	207	PORT_DIPUNKNOWN_DIPLOC( 0x40, IP_ACTIVE_LOW, "SW2:7" )
	208	PORT_DIPUNKNOWN_DIPLOC( 0x80, IP_ACTIVE_LOW, "SW2:8" )
	209	INPUT_PORTS_END
	210
	211	/*************************************
	212	*
	213	*  Game-specific port definitions
	214	*
	215	*************************************/
	216
	217	static INPUT_PORTS_START( renju )
	218	PORT_INCLUDE( st0016 )
	219
	220	PORT_MODIFY("SYSTEM")
	221	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
	222	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
	223
	224	PORT_MODIFY("DSW1") /* Dip switch A  */
	225	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:2")
	226	PORT_DIPSETTING(    0x02, DEF_STR( Off ) )
	227	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	228	PORT_SERVICE_DIPLOC(  0x04, IP_ACTIVE_LOW, "SW1:3" )
	229	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:4")
	230	PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
	231	PORT_DIPSETTING(    0x08, DEF_STR( On ) )
	232	PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SW1:5,6")
	233	PORT_DIPSETTING(    0x20, DEF_STR( 2C_1C ) )
	234	PORT_DIPSETTING(    0x30, DEF_STR( 1C_1C ) )
	235	PORT_DIPSETTING(    0x00, DEF_STR( 2C_3C ) )
	236	PORT_DIPSETTING(    0x10, DEF_STR( 1C_2C ) )
	237	PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SW1:7,8")
	238	PORT_DIPSETTING(    0x80, DEF_STR( 2C_1C ) )
	239	PORT_DIPSETTING(    0xc0, DEF_STR( 1C_1C ) )
	240	PORT_DIPSETTING(    0x00, DEF_STR( 2C_3C ) )
	241	PORT_DIPSETTING(    0x80, DEF_STR( 1C_2C ) )
	242
	243	PORT_MODIFY("DSW2") /* Dip switch B */
	244	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:1,2")
	245	PORT_DIPSETTING(    0x00, DEF_STR( Very_Hard ) )
	246	PORT_DIPSETTING(    0x01, DEF_STR( Hard ) )
	247	PORT_DIPSETTING(    0x02, DEF_STR( Easy ) )
	248	PORT_DIPSETTING(    0x03, DEF_STR( Normal ) )
	249	INPUT_PORTS_END
	250
	251	static INPUT_PORTS_START( koikois )
	252	PORT_INCLUDE( st0016 )
	253
	254	PORT_MODIFY("P1")
	255	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
	256	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
	257	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
	258
	259	PORT_MODIFY("SYSTEM")
	260	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
	261	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
	262
	263	PORT_MODIFY("DSW1") /* Dip switch A  */
	264	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:1")
	265	PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
	266	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	267	PORT_DIPNAME( 0x02, 0x02, "Crt Mode" ) PORT_DIPLOCATION("SW1:2") // flip screen ?
	268	PORT_DIPSETTING(    0x02, DEF_STR( Off ) )
	269	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	270	PORT_SERVICE_DIPLOC(  0x04, IP_ACTIVE_LOW, "SW1:3" )
	271	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:4")
	272	PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
	273	PORT_DIPSETTING(    0x08, DEF_STR( On ) )
	274	PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SW1:5,6")
	275	PORT_DIPSETTING(    0x10, DEF_STR( 2C_1C ) )
	276	PORT_DIPSETTING(    0x30, DEF_STR( 1C_1C ) )
	277	PORT_DIPSETTING(    0x00, DEF_STR( 2C_3C ) )
	278	PORT_DIPSETTING(    0x20, DEF_STR( 1C_2C ) )
	279	PORT_DIPNAME( 0x40, 0x40,  DEF_STR( Controls ) ) PORT_DIPLOCATION("SW1:7")
	280	PORT_DIPSETTING(    0x00, "Majyan Panel" )
	281	PORT_DIPSETTING(    0x40, DEF_STR( Joystick ) )
	282
	283	PORT_MODIFY("DSW2") /* Dip switch B */
	284	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:1,2")
	285	PORT_DIPSETTING(    0x00, DEF_STR( Very_Hard ) )
	286	PORT_DIPSETTING(    0x01, DEF_STR( Hard ) )
	287	PORT_DIPSETTING(    0x02, DEF_STR( Easy ) )
	288	PORT_DIPSETTING(    0x03, DEF_STR( Normal ) )
	289	INPUT_PORTS_END
	290
	291	static INPUT_PORTS_START( nratechu )
	292	PORT_INCLUDE( st0016 )
	293
	294	PORT_MODIFY("SYSTEM")
	295	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
	296	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
	297
	298	PORT_MODIFY("DSW1") /* Dip switch A  */
	299	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:1,2,3")
	300	PORT_DIPSETTING(    0x00, DEF_STR( 5C_1C ) )
	301	PORT_DIPSETTING(    0x01, DEF_STR( 4C_1C ) )
	302	PORT_DIPSETTING(    0x02, DEF_STR( 3C_1C ) )
	303	PORT_DIPSETTING(    0x03, DEF_STR( 2C_1C ) )
	304	PORT_DIPSETTING(    0x07, DEF_STR( 1C_1C ) )
	305	PORT_DIPSETTING(    0x06, DEF_STR( 1C_2C ) )
	306	PORT_DIPSETTING(    0x05, DEF_STR( 1C_3C ) )
	307	PORT_DIPSETTING(    0x04, DEF_STR( 1C_4C ) )
	308	PORT_DIPUNUSED_DIPLOC( 0x08, 0x08, "SW1:4" )
	309	PORT_DIPUNUSED_DIPLOC( 0x10, 0x10, "SW1:5" )
	310	PORT_DIPUNUSED_DIPLOC( 0x20, 0x20, "SW1:6" )
	311	PORT_DIPNAME( 0x40, 0x40, "How To Play" ) PORT_DIPLOCATION("SW1:7")
	312	PORT_DIPSETTING(    0x00, DEF_STR( No ) )
	313	PORT_DIPSETTING(    0x40, DEF_STR( Yes ) )
	314	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Language ) ) PORT_DIPLOCATION("SW1:8")
	315	PORT_DIPSETTING(    0x00, DEF_STR( English ) )
	316	PORT_DIPSETTING(    0x80, DEF_STR( Japanese ) )
	317
	318	PORT_MODIFY("DSW2") /* Dip switch B */
	319	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:1,2") //  speed / time..
	320	PORT_DIPSETTING(    0x02, DEF_STR( Easy ) )
	321	PORT_DIPSETTING(    0x03, DEF_STR( Normal ))
	322	PORT_DIPSETTING(    0x01, DEF_STR( Hard ) )
	323	PORT_DIPSETTING(    0x00, DEF_STR( Hardest ) )
	324	PORT_DIPNAME( 0x0C, 0x0c, "VS Round" ) PORT_DIPLOCATION("SW2:3,4")
	325	PORT_DIPSETTING(    0x00, "First one to win" )
	326	PORT_DIPSETTING(    0x04, "Best 4 out of 7" )
	327	PORT_DIPSETTING(    0x08, "Best 3 out of 5" )
	328	PORT_DIPSETTING(    0x0C, "Best 2 out of 3" )
	329	PORT_DIPUNUSED_DIPLOC( 0x10, 0x10, "SW2:5" )
	330	PORT_DIPNAME( 0x20, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW2:6") // Manual has this Defaulted OFF
	331	PORT_DIPSETTING(    0x20, DEF_STR( Off ) )
	332	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	333	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW2:7")
	334	PORT_DIPSETTING(    0x40, DEF_STR( Off ) )
	335	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	336	PORT_SERVICE_DIPLOC(  0x80, IP_ACTIVE_LOW, "SW2:8" )
	337	INPUT_PORTS_END
	338
	339	static INPUT_PORTS_START( mayjisn2 )
	340	PORT_INCLUDE( st0016 )
	341
	342	PORT_MODIFY("SYSTEM")
	343	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
	344
	345	PORT_MODIFY("DSW1") /* Dip switch A  */
	346	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:1,2,3")
	347	PORT_DIPSETTING(    0x01, DEF_STR( 4C_1C ) )
	348	PORT_DIPSETTING(    0x02, DEF_STR( 3C_1C ) )
	349	PORT_DIPSETTING(    0x03, DEF_STR( 2C_1C ) )
	350	PORT_DIPSETTING(    0x07, DEF_STR( 1C_1C ) )
	351	PORT_DIPSETTING(    0x06, DEF_STR( 1C_2C ) )
	352	PORT_DIPSETTING(    0x05, DEF_STR( 1C_3C ) )
	353	PORT_DIPSETTING(    0x04, DEF_STR( 1C_4C ) )
	354	PORT_DIPNAME( 0x18, 0x18, "Timer" ) PORT_DIPLOCATION("SW1:4,5")
	355	PORT_DIPSETTING(    0x00, "6:00" )
	356	PORT_DIPSETTING(    0x08, "5:00" )
	357	PORT_DIPSETTING(    0x18, "4:00" )
	358	PORT_DIPSETTING(    0x10, "3:00" )
	359
	360	PORT_MODIFY("DSW2") /* Dip switch B */
	361	PORT_DIPNAME( 0x18, 0x18, "Music in Game"  ) PORT_DIPLOCATION("SW2:4,5")
	362	PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
	363	PORT_DIPSETTING(    0x08, "Remixed" )
	364	PORT_DIPSETTING(    0x18, "Only Intro" )
	365	PORT_DIPSETTING(    0x10, "Classic" )
	366	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW2:6")
	367	PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
	368	PORT_DIPSETTING(    0x20, DEF_STR( On ) )
	369	PORT_DIPNAME( 0x40, 0x40, "Position of Title" ) PORT_DIPLOCATION("SW2:7")
	370	PORT_DIPSETTING(    0x00, "B" )
	371	PORT_DIPSETTING(    0x40, "A" )
	372	INPUT_PORTS_END
	373
	374	static GFXDECODE_START( st0016 )
	375	//  GFXDECODE_ENTRY( NULL, 0, charlayout,      0, 16*4  )
	376	GFXDECODE_END
	377
	378	TIMER_DEVICE_CALLBACK_MEMBER(st0016_state::st0016_int)
	379	{
	380	int scanline = param;
	381
	382	if(scanline == 240)
	383	m_maincpu->set_input_line(0,HOLD_LINE);
	384	else if((scanline % 64) == 0)
	385	if(m_maincpu->state_int(Z80_IFF1)) /* dirty hack ... */
	386	m_maincpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE );
	387	}
	388
	389
	390
	391
	392	/*************************************
	393	*
	394	*  Machine driver(s)
	395	*
	396	*************************************/
	397
	398	UINT32 st0016_state::screen_update_st0016(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
	399	{
	400	return m_maincpu->update(screen,bitmap,cliprect);
	401	}
	402
	403
	404	static MACHINE_CONFIG_START( st0016, st0016_state )
	405	/* basic machine hardware */
	406	MCFG_CPU_ADD("maincpu",ST0016_CPU,8000000) /* 8 MHz ? */
	407	MCFG_CPU_PROGRAM_MAP(st0016_mem)
	408	MCFG_CPU_IO_MAP(st0016_io)
	409	MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", st0016_state, st0016_int, "screen", 0, 1)
	410
	411	/* video hardware */
	412	MCFG_SCREEN_ADD("screen", RASTER)
	413	MCFG_SCREEN_REFRESH_RATE(60)
	414	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
	415	MCFG_SCREEN_SIZE(48*8, 48*8)
	416	MCFG_SCREEN_VISIBLE_AREA(0*8, 48*8-1, 0*8, 48*8-1)
	417	MCFG_SCREEN_UPDATE_DRIVER(st0016_state, screen_update_st0016)
	418	MCFG_SCREEN_PALETTE("maincpu:palette")
	419
	420
	421	//   MCFG_VIDEO_START_OVERRIDE(st0016_state,st0016)
	422
	423	MACHINE_CONFIG_END
	424
	425	static MACHINE_CONFIG_DERIVED( mayjinsn, st0016 )
	426	MCFG_CPU_MODIFY("maincpu")
	427	MCFG_CPU_IO_MAP(st0016_m2_io)
	428	MCFG_CPU_ADD("sub", V810, 10000000)//25 Mhz ?
	429	MCFG_CPU_PROGRAM_MAP(v810_mem)
	430	MCFG_QUANTUM_TIME(attotime::from_hz(60))
	431	MACHINE_CONFIG_END
	432
	433	static MACHINE_CONFIG_DERIVED( renju, st0016 )
	434	MCFG_CPU_MODIFY("maincpu")
	435	MCFG_CPU_PROGRAM_MAP(renju_mem)
	436	MACHINE_CONFIG_END
	437
	438	/*************************************
	439	*
	440	*  ROM definition(s)
	441	*
	442	*************************************/
	443	/*
	444	Renjyu Kizoku
	445	Visco, 1994
	446
	447	PCB Layout
	448
	449	E51-00001-A
	450	|------------------------------------|
	451	|AMP       UPD6376    424400  62256  |
	452	|    VOL      RESET   424400  62256  |
	453	|                                    |
	454	| TD62064 74273                      |
	455	|J        74273                      |
	456	|A        74273            42.9545MHz|
	457	|M                                   |
	458	|M        74245         UNKNOWN      |
	459	|A        74245          QFP208      |
	460	|         74245                      |
	461	|         74245                 48MHz|
	462	|                                    |
	463	|  74138  74138                      |
	464	|  74253  74253       RNJ2           |
	465	|                                    |
	466	|  DSW1   DSW2        RENJYU-1  6264 |
	467	|------------------------------------|
	468
	469	Note:
	470	Unknown QFP (surface scratched off) is the CPU
	471	+ GFX generator - it's possibly NEC V70/V810
	472	*/
	473
	474	ROM_START( renju )
	475	ROM_REGION( 0x280000, "maincpu", 0 )
	476	ROM_LOAD( "renjyu-1.u31",0x000000, 0x200000, CRC(e0fdbe9b) SHA1(52d31024d1a88b8fcca1f87366fcaf80e3c387a1) )
	477	ROM_LOAD( "rnj2.u32",    0x200000, 0x080000, CRC(2015289c) SHA1(5223b6d3dbe4657cd63cf5b527eaab84cf23587a ) )
	478	ROM_END
	479
	480	ROM_START( nratechu )
	481	ROM_REGION( 0x200000, "maincpu", 0 )
	482	ROM_LOAD( "sx012-01",   0x000000, 0x080000, CRC(6ca01d57) SHA1(065848f19ecf2dc1f7bbc7ddd87bca502e4b8b16) )
	483	ROM_LOAD( "sx012-02",   0x100000, 0x100000, CRC(40a4e354) SHA1(8120ce8deee6805050a5b083a334c3743c09566b) )
	484	ROM_END
	485
	486	/* PCB E51-00001 (almost identical to above) */
	487
	488	ROM_START( dcrown )
	489	ROM_REGION( 0x200000, "maincpu", 0 )
	490	ROM_LOAD( "dc1.u31",0x000000, 0x80000, CRC(e55200b8) SHA1(20a968dc895bb636b064c29b4b53c6ffa49fea36) )
	491	ROM_LOAD( "dc2.u32",0x080000, 0x80000, CRC(05b6192f) SHA1(6af6e7b2c681f2791a7f89a528a95eb976c8ba84) )
	492	ROM_LOAD( "dc3.u33",0x100000, 0x80000, CRC(f23c1975) SHA1(118d6054922a733d23363c53bb331d84c78e50ad) )
	493	ROM_LOAD( "dc4.u34",0x180000, 0x80000, CRC(0d1c2c61) SHA1(7e4dc20ab683ce0f61dd939cfd9b17714ba2343a) )
	494	ROM_END
	495
	496	ROM_START( dcrowna )
	497	ROM_REGION( 0x200000, "maincpu", 0 )
	498	ROM_LOAD( "dcn-0.1c",     0x000000, 0x080000, CRC(5dd0615d) SHA1(b859994bd79229da4c687deefe1997313724b26e) )
	499	ROM_LOAD( "dcn-1.1d",     0x080000, 0x080000, CRC(6c6f14e7) SHA1(2a3474e44420cc78e3ead777eb91481c4bb46eef) )
	500	ROM_LOAD( "dcn-2.1e",     0x100000, 0x080000, CRC(e9401a5e) SHA1(db24ebe5a0073c7c1c2da957772e223545f3c778) )
	501	ROM_LOAD( "dcn-3.1f",     0x180000, 0x080000, CRC(ec2e88bc) SHA1(2a8deee63e123dae411e2b834eca69be6f646d66) )
	502	ROM_END
	503
	504	ROM_START( gostop )
	505	ROM_REGION( 0x200000, "maincpu", 0 )
	506	ROM_LOAD( "go-stop_rom1.u31",0x000000, 0x80000, CRC(93decaa2) SHA1(a30958b76dfe5752a341ecdc950119c10e864586) )
	507	ROM_LOAD( "go-stop_rom2.u32",0x080000, 0x80000, CRC(3c5402ff) SHA1(bdc38922b5cbad0150adf9c6cc0fefc5705a16a2) )
	508	ROM_END
	509
	510	/*
	511	Koi Koi Shimasho
	512	Visco
	513
	514	PCB Layout
	515	----------
	516
	517	E63-00001
	518	|---------------------------------------|
	519	|VOL     RESET     TC514400   62256     |
	520	|        UPD6376   TC514400   62256     |
	521	|MJM2904                                |
	522	|                                       |
	523	|M                            42.9545MHz|
	524	|A                   |----------|       |
	525	|H                   |          |       |
	526	|J                   | ST-0016  |       |
	527	|O                   |          |  48MHz|
	528	|N                   |          |       |
	529	|G                   |          |       |
	530	|5                   |----------|       |
	531	|6                          BATTERY     |
	532	|                                       |
	533	|                                       |
	534	|                              KOI-5    |
	535	|   KOI-4   KOI-2   KOI-3  KOI-1    6264|
	536	|---------------------------------------|
	537
	538	*/
	539
	540	ROM_START( koikois )
	541	ROM_REGION( 0x400000, "maincpu", 0 )
	542	ROM_LOAD16_BYTE( "koi-2.6c", 0x000001, 0x080000, CRC(2722be71) SHA1(1aa3d819eef01db042ee04a01c1b18c4d9dae65e) )
	543	ROM_LOAD16_BYTE( "koi-1.4c", 0x000000, 0x080000, CRC(c79e2b43) SHA1(868174f7ab8e68e31d3302ae94dd742048deed9f) )
	544	ROM_LOAD16_BYTE( "koi-4.8c", 0x100001, 0x080000, CRC(ace236df) SHA1(4bf56affe5b6d0ba3cc677eaa91f9be77f26c654) )
	545	ROM_LOAD16_BYTE( "koi-3.5c", 0x100000, 0x080000, CRC(6fd88149) SHA1(87b1be32770232eb041e3ef9d1da45282af8a5d4) )
	546	ROM_LOAD( "koi-5.2c", 0x200000, 0x200000, CRC(561e12c8) SHA1(a7aedf549bc3141fc01bc4a10c235af265ba4ee9) )
	547	ROM_END
	548
	549
	550	/*
	551	Mayjinsen (JPN Ver.)
	552	(c)1994 Seta
	553
	554	CPU:    UPD70732-25 V810 ?
	555	Sound:  Custom (ST-0016 ?)
	556
	557	sx003.01    main prg
	558	sx003.02
	559	sx003.03
	560	sx003.04    /
	561
	562	sx003.05d   chr
	563	sx003.06
	564	sx003.07d   /
	565
	566	-----------
	567
	568	Mayjinsen II
	569	Seta, 1994
	570
	571	This game runs on Seta hardware. The game is similar to Shougi.
	572
	573	PCB Layout
	574	----------
	575
	576	E52-00001
	577	|----------------------------------------------------|
	578	|                  62256    62256    62256    62256  |
	579	| D70732GD-25                                        |
	580	| NEC 1991 V810    62256    62256    62256    62256  |
	581	|                                                    |
	582	|                  62256    62256    62256    62256  |
	583	|                                                    |
	584	|                SX007-01 SX007-02  SX007-03 SX007-04|
	585	|                                                    |
	586	|                                   6264             |
	587	|                                                    |
	588	|                   62256      42.9545MHz  48MHz     |
	589	|      PAL                                           |
	590	|                   62256                            |
	591	| 46MHz                          ST-0016   SX007-05  |
	592	|                                TC6210AF            |
	593	|                                                    |
	594	|                   TC514800                         |
	595	|                                                    |
	596	|                                           DSW1-8   |
	597	|                                                    |
	598	|                                           DSW2-8   |
	599	|                           JAMMA                    |
	600	|----------------------------------------------------|
	601	*/
	602
	603	ROM_START(mayjinsn )
	604	ROM_REGION( 0x180000, "maincpu", 0 )
	605	ROM_LOAD( "sx003.05d",   0x000000, 0x80000, CRC(2be6d620) SHA1(113db888fb657d45be55708bbbf9a9ac159a9636) )
	606	ROM_LOAD( "sx003.06",    0x080000, 0x80000, CRC(f0553386) SHA1(8915cb3ce03b9a12612694caec9bbec6de4dd070) )
	607	ROM_LOAD( "sx003.07d",   0x100000, 0x80000, CRC(8db281c3) SHA1(f8b488dd28010f01f789217a4d62ba2116e06e94) )
	608
	609	ROM_REGION32_LE( 0x20000*4, "user1", 0 ) /* V810 code */
	610	ROM_LOAD32_BYTE( "sx003.04",   0x00003, 0x20000,   CRC(fa15459f) SHA1(4163ab842943705c550f137abbdd2cb51ba5390f) )
	611	ROM_LOAD32_BYTE( "sx003.03",   0x00002, 0x20000,   CRC(71a438ea) SHA1(613bab6a59aa1bced2ab37177c61a0fd7ce7e64f) )
	612	ROM_LOAD32_BYTE( "sx003.02",   0x00001, 0x20000,   CRC(61911eed) SHA1(1442b3867b85120ba652ec8205d74332addffb67) )
	613	ROM_LOAD32_BYTE( "sx003.01",   0x00000, 0x20000,   CRC(d210bfe5) SHA1(96d9f2b198d98125df4bd6b15705646d472a8a87) )
	614	ROM_END
	615
	616	ROM_START(mayjisn2 )
	617	ROM_REGION( 0x100000, "maincpu", 0 )
	618	ROM_LOAD( "sx007-05.8b",   0x00000, 0x100000,  CRC(b13ea605) SHA1(75c067df02c988f170c24153d3852c472355fc9d) )
	619
	620	ROM_REGION32_LE( 0x20000*4, "user1", 0 ) /* V810 code */
	621	ROM_LOAD32_BYTE( "sx007-04.4b",   0x00003, 0x20000,   CRC(fa15459f) SHA1(4163ab842943705c550f137abbdd2cb51ba5390f) )
	622	ROM_LOAD32_BYTE( "sx007-03.4j",   0x00002, 0x20000,   CRC(71a438ea) SHA1(613bab6a59aa1bced2ab37177c61a0fd7ce7e64f) )
	623	ROM_LOAD32_BYTE( "sx007-02.4m",   0x00001, 0x20000,   CRC(61911eed) SHA1(1442b3867b85120ba652ec8205d74332addffb67) )
	624	ROM_LOAD32_BYTE( "sx007-01.4s",   0x00000, 0x20000,   CRC(d210bfe5) SHA1(96d9f2b198d98125df4bd6b15705646d472a8a87) )
	625	ROM_END
	626
	627	/*************************************
	628	*
	629	*  Game-specific driver inits
	630	*
	631	*************************************/
	632
	633	DRIVER_INIT_MEMBER(st0016_state,renju)
	634	{
	635	m_maincpu->st0016_game=0;
	636	}
	637
	638	DRIVER_INIT_MEMBER(st0016_state,nratechu)
	639	{
	640	m_maincpu->st0016_game=1;
	641	}
	642
	643	DRIVER_INIT_MEMBER(st0016_state,mayjinsn)
	644	{
	645	m_maincpu->st0016_game=4;//|0x80;
	646	membank("bank2")->set_base(memregion("user1")->base());
	647	}
	648
	649	DRIVER_INIT_MEMBER(st0016_state,mayjisn2)
	650	{
	651	m_maincpu->st0016_game=4;
	652	membank("bank2")->set_base(memregion("user1")->base());
	653	}
	654
	655
	656
	657
	658
	659	/*************************************
	660	*
	661	*  Game driver(s)
	662	*
	663	*************************************/
	664
	665	GAME(  1994, renju,     0,      renju,    renju,   st0016_state,    renju,    ROT0, "Visco",     "Renju Kizoku", 0)
	666	GAME(  1996, nratechu,  0,      st0016,   nratechu, st0016_state, nratechu, ROT0, "Seta",      "Neratte Chu", 0)
	667	GAME(  1994, mayjisn2,  0,      mayjinsn, mayjisn2, st0016_state, mayjisn2, ROT0, "Seta",      "Mayjinsen 2", 0)
	668	GAME(  1995, koikois,   0,      st0016,   koikois, st0016_state,  renju,    ROT0, "Visco",     "Koi Koi Shimasho", GAME_IMPERFECT_GRAPHICS)
	669	/* Not working */
	670	GAME( 1994, mayjinsn,   0,      mayjinsn, st0016, st0016_state,   mayjinsn, ROT0, "Seta",      "Mayjinsen",GAME_IMPERFECT_GRAPHICS|GAME_NOT_WORKING)
	671	GAME( 1994, dcrown,     0,      st0016,   renju, st0016_state,    renju,    ROT0, "Nippon Data Kiki", "Dream Crown (Set 1)", GAME_NOT_WORKING) // (c) 1994 Nippon Data Kiki is uploaded near the Japanese Insert coin text
	672	GAME( 1994, dcrowna,    dcrown, st0016,   renju, st0016_state,    renju,    ROT0, "Nippon Data Kiki", "Dream Crown (Set 2)", GAME_NOT_WORKING) // the Insert Coin text has been translated to English and no (c) is uploaded
	673	GAME( 2001, gostop,     0,      st0016,   renju, st0016_state,    renju,    ROT0, "Visco", "Kankoku Hanafuda Go-Stop", GAME_NOT_WORKING)

Property changes on: trunk/src/mame/drivers/simple_st0016.c

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