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r32614 Friday 10th October, 2014 at 07:00:38 UTC by Curt Coder
(MESS) vic20: Emulated the Final Expansion 3 cartridge (only RAM/FlashROM supported). [Curt Coder]
[src/emu/bus]bus.mak
[src/emu/bus/vic20]exp.c fe3.c* fe3.h*

trunk/src/emu/bus/bus.mak
r32613r32614
735735ifneq ($(filter VIC20,$(BUSES)),)
736736OBJDIRS += $(BUSOBJ)/vic20
737737BUSOBJS += $(BUSOBJ)/vic20/exp.o
738BUSOBJS += $(BUSOBJ)/vic20/fe3.o
738739BUSOBJS += $(BUSOBJ)/vic20/megacart.o
739740BUSOBJS += $(BUSOBJ)/vic20/std.o
740741BUSOBJS += $(BUSOBJ)/vic20/vic1010.o
trunk/src/emu/bus/vic20/exp.c
r32613r32614
209209//-------------------------------------------------
210210
211211// slot devices
212#include "fe3.h"
212213#include "megacart.h"
213214#include "std.h"
214215#include "vic1010.h"
r32613r32614
222223   SLOT_INTERFACE("3k", VIC1210)
223224   SLOT_INTERFACE("8k", VIC1110)
224225   SLOT_INTERFACE("16k", VIC1111)
226   SLOT_INTERFACE("fe3", VIC20_FE3)
225227
226228   // the following need ROMs from the software list
227229   SLOT_INTERFACE_INTERNAL("standard", VIC20_STD)
trunk/src/emu/bus/vic20/fe3.c
r0r32614
1// license:BSD-3-Clause
2// copyright-holders:Curt Coder
3/**********************************************************************
4
5    Final Expansion v3 cartridge emulation
6
7    Copyright MESS Team.
8    Visit http://mamedev.org for licensing and usage restrictions.
9
10**********************************************************************/
11
12/*
13
14   TODO:
15
16   - fe3diag register error#2 hp=5592 (same error in VICE)
17   - SD card
18   - RTC
19
20*/
21
22#include "fe3.h"
23
24
25
26//**************************************************************************
27//  MACROS/CONSTANTS
28//**************************************************************************
29
30#define AM29F040_TAG  "am29f040"
31
32#define REG1_BANK \
33    ((m_reg1 & 0x7f) << 15)
34
35#define REG2_BLK0_VISIBLE \
36    (!(m_reg2 & REG2_BLK0))
37
38#define REG2_BLK1_VISIBLE \
39    (!(m_reg2 & REG2_BLK1))
40
41#define REG2_BLK2_VISIBLE \
42    (!(m_reg2 & REG2_BLK2))
43
44#define REG2_BLK3_VISIBLE \
45    (!(m_reg2 & REG2_BLK3))
46
47#define REG2_BLK5_VISIBLE \
48    (!(m_reg2 & REG2_BLK5))
49
50
51
52//**************************************************************************
53//  DEVICE DEFINITIONS
54//**************************************************************************
55
56const device_type VIC20_FE3 = &device_creator<vic20_final_expansion_3_t>;
57
58
59//-------------------------------------------------
60//  ROM( vic20_fe3 )
61//-------------------------------------------------
62
63ROM_START( vic20_fe3 )
64   ROM_REGION( 0x80000, AM29F040_TAG, 0 )
65   ROM_LOAD( "fe3r022d.bin", 0x00000, 0x80000, CRC(f4ff4aee) SHA1(1a389120159dee09c0f03ecb8fcd51ea2a2d2306) )
66ROM_END
67
68
69//-------------------------------------------------
70//  rom_region - device-specific ROM region
71//-------------------------------------------------
72
73const rom_entry *vic20_final_expansion_3_t::device_rom_region() const
74{
75   return ROM_NAME( vic20_fe3 );
76}
77
78
79//-------------------------------------------------
80//  MACHINE_DRIVER( vic20_fe3 )
81//-------------------------------------------------
82
83static MACHINE_CONFIG_FRAGMENT( vic20_fe3 )
84   MCFG_AMD_29F040_ADD(AM29F040_TAG)
85MACHINE_CONFIG_END
86
87
88//-------------------------------------------------
89//  machine_config_additions - device-specific
90//  machine configurations
91//-------------------------------------------------
92
93machine_config_constructor vic20_final_expansion_3_t::device_mconfig_additions() const
94{
95   return MACHINE_CONFIG_NAME( vic20_fe3 );
96}
97
98
99
100//**************************************************************************
101//  LIVE DEVICE
102//**************************************************************************
103
104//-------------------------------------------------
105//  vic20_final_expansion_3_t - constructor
106//-------------------------------------------------
107
108vic20_final_expansion_3_t::vic20_final_expansion_3_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
109   device_t(mconfig, VIC20_FE3, "Final Expansion v3", tag, owner, clock, "vic20_fe3", __FILE__),
110   device_vic20_expansion_card_interface(mconfig, *this),
111   m_flash_rom(*this, AM29F040_TAG),
112   m_ram(*this, "sram")
113{
114}
115
116
117//-------------------------------------------------
118//  device_start - device-specific startup
119//-------------------------------------------------
120
121void vic20_final_expansion_3_t::device_start()
122{
123   m_ram.allocate(0x80000);
124
125   // state saving
126   save_item(NAME(m_reg1));
127   save_item(NAME(m_reg2));
128   save_item(NAME(m_lockbit));
129}
130
131
132//-------------------------------------------------
133//  device_reset - device-specific reset
134//-------------------------------------------------
135
136void vic20_final_expansion_3_t::device_reset()
137{
138   m_reg1 = 0;
139   m_reg2 = 0;
140   m_lockbit = true;
141}
142
143
144//-------------------------------------------------
145//  vic20_cd_r - cartridge data read
146//-------------------------------------------------
147
148UINT8 vic20_final_expansion_3_t::vic20_cd_r(address_space &space, offs_t offset, UINT8 data, int ram1, int ram2, int ram3, int blk1, int blk2, int blk3, int blk5, int io2, int io3)
149{
150   switch (m_reg1 & REG1_MODE_MASK)
151   {
152   case REG1_START:
153      // read from ROM
154      if (!blk5)
155      {
156         data = m_flash_rom->read(get_address(0, 3, offset));
157
158         m_lockbit = true;
159      }
160
161      // read from registers
162      if (!io3 && !m_lockbit && ((offset & 0x1c02) == 0x1c02))
163      {
164         data = read_register(BIT(offset, 0));
165      }
166      break;
167
168   case REG1_SUPER_ROM:
169      // read from RAM bank 0
170      if ((!ram1 || !ram2 || !ram3) && REG2_BLK0_VISIBLE)
171      {
172         data = m_ram[get_address(0, 0, offset)];
173      }
174     
175      // read from ROM
176      if (!blk1 && REG2_BLK1_VISIBLE)
177      {
178         data = m_flash_rom->read(get_address(REG1_BANK, 0, offset));
179      }
180      if (!blk2 && REG2_BLK2_VISIBLE)
181      {
182         data = m_flash_rom->read(get_address(REG1_BANK, 1, offset));
183      }
184      if (!blk3 && REG2_BLK3_VISIBLE)
185      {
186         data = m_flash_rom->read(get_address(REG1_BANK, 2, offset));
187      }
188      if (!blk5 && REG2_BLK5_VISIBLE)
189      {
190         data = m_flash_rom->read(get_address(REG1_BANK, 3, offset));
191      }
192
193      // read from registers
194      if (!io3 && !(m_reg2 & REG2_IO3) && ((offset & 0x1c02) == 0x1c02))
195      {
196         data = read_register(BIT(offset, 0));
197      }
198      break;
199     
200   case REG1_RAM_1:
201      // read from RAM bank 0
202      if ((!ram1 || !ram2 || !ram3) && REG2_BLK0_VISIBLE)
203      {
204         data = m_ram[get_address(0, 0, offset)];
205      }
206
207      // read from RAM bank 1
208      if (!blk1 && REG2_BLK1_VISIBLE)
209      {
210         data = m_ram[get_address(1, 0, offset)];
211      }
212      if (!blk2 && REG2_BLK2_VISIBLE)
213      {
214         data = m_ram[get_address(1, 1, offset)];
215      }
216      if (!blk3 && REG2_BLK3_VISIBLE)
217      {
218         data = m_ram[get_address(1, 2, offset)];
219      }
220      if (!blk5 && REG2_BLK5_VISIBLE)
221      {
222         data = m_ram[get_address(1, 3, offset)];
223      }
224
225      // read from registers
226      if (!io3 && !(m_reg2 & REG2_IO3) && ((offset & 0x1c02) == 0x1c02))
227      {
228         data = read_register(BIT(offset, 0));
229      }
230      break;
231     
232   case REG1_RAM_2:
233      // read from RAM bank 0
234      if ((!ram1 || !ram2 || !ram3) && REG2_BLK0_VISIBLE)
235      {
236         data = m_ram[get_address(0, 0, offset)];
237      }
238
239      // read from RAM bank 1 or 2
240      if (!blk1 && REG2_BLK1_VISIBLE)
241      {
242         data = m_ram[get_address((m_reg1 & REG1_BLK1) ? 2 : 1, 0, offset)];
243      }
244      if (!blk2 && REG2_BLK2_VISIBLE)
245      {
246         data = m_ram[get_address((m_reg1 & REG1_BLK2) ? 2 : 1, 1, offset)];
247      }
248      if (!blk3 && REG2_BLK3_VISIBLE)
249      {
250         data = m_ram[get_address((m_reg1 & REG1_BLK3) ? 2 : 1, 2, offset)];
251      }
252      if (!blk5 && REG2_BLK5_VISIBLE)
253      {
254         data = m_ram[get_address((m_reg1 & REG1_BLK5) ? 2 : 1, 3, offset)];
255      }
256
257      // read from registers
258      if (!io3 && !(m_reg2 & REG2_IO3) && ((offset & 0x1c02) == 0x1c02))
259      {
260         data = read_register(BIT(offset, 0));
261      }
262      break;
263     
264   case REG1_SUPER_RAM:
265      // read from RAM bank 0
266      if ((!ram1 || !ram2 || !ram3) && REG2_BLK0_VISIBLE)
267      {
268         data = m_ram[get_address(0, 0, offset)];
269      }
270
271      // read from any RAM bank
272      if (!blk1 && REG2_BLK1_VISIBLE)
273      {
274         data = m_ram[get_address(REG1_BANK, 0, offset)];
275      }
276      if (!blk2 && REG2_BLK2_VISIBLE)
277      {
278         data = m_ram[get_address(REG1_BANK, 1, offset)];
279      }
280      if (!blk3 && REG2_BLK3_VISIBLE)
281      {
282         data = m_ram[get_address(REG1_BANK, 2, offset)];
283      }
284      if (!blk5 && REG2_BLK5_VISIBLE)
285      {
286         data = m_ram[get_address(REG1_BANK, 3, offset)];
287      }
288
289      // read from registers
290      if (!io3 && !(m_reg2 & REG2_IO3) && ((offset & 0x1c02) == 0x1c02))
291      {
292         data = read_register(BIT(offset, 0));
293      }
294      break;
295     
296   case REG1_RAM_ROM:
297      // read from RAM bank 0
298      if ((!ram1 || !ram2 || !ram3) && REG2_BLK0_VISIBLE)
299      {
300         data = m_ram[get_address(0, 0, offset)];
301      }
302     
303      // read from ROM bank 0 or RAM bank 1
304      if (!blk1 && REG2_BLK1_VISIBLE)
305      {
306         data = (m_reg1 & REG1_BLK1) ? m_flash_rom->read(get_address(0, 0, offset)) : m_ram[get_address(1, 0, offset)];
307      }
308      if (!blk2 && REG2_BLK2_VISIBLE)
309      {
310         data = (m_reg1 & REG1_BLK2) ? m_flash_rom->read(get_address(0, 1, offset)) : m_ram[get_address(1, 1, offset)];
311      }
312      if (!blk3 && REG2_BLK3_VISIBLE)
313      {
314         data = (m_reg1 & REG1_BLK3) ? m_flash_rom->read(get_address(0, 2, offset)) : m_ram[get_address(1, 2, offset)];
315      }
316      if (!blk5 && REG2_BLK5_VISIBLE)
317      {
318         data = (m_reg1 & REG1_BLK5) ? m_flash_rom->read(get_address(0, 3, offset)) : m_ram[get_address(1, 3, offset)];
319      }
320
321      // read from registers
322      if (!io3 && !(m_reg2 & REG2_IO3) && ((offset & 0x1c02) == 0x1c02))
323      {
324         data = read_register(BIT(offset, 0));
325      }
326      break;
327     
328   case REG1_FLASH:
329      // read from RAM bank 0
330      if ((!ram1 || !ram2 || !ram3) && REG2_BLK0_VISIBLE)
331      {
332         data = m_ram[get_address(0, 0, offset)];
333      }
334
335      // read from ROM
336      if (!blk1 && REG2_BLK1_VISIBLE)
337      {
338         data = m_flash_rom->read(get_address(REG1_BANK, 0, offset));
339      }
340      if (!blk2 && REG2_BLK2_VISIBLE)
341      {
342         data = m_flash_rom->read(get_address(REG1_BANK, 1, offset));
343      }
344      if (!blk3 && REG2_BLK3_VISIBLE)
345      {
346         data = m_flash_rom->read(get_address(REG1_BANK, 2, offset));
347      }
348      if (!blk5 && REG2_BLK5_VISIBLE)
349      {
350         data = m_flash_rom->read(get_address(REG1_BANK, 3, offset));
351      }
352
353      // read from registers
354      if (!io3 && !(m_reg2 & REG2_IO3) && ((offset & 0x1c02) == 0x1c02))
355      {
356         data = read_register(BIT(offset, 0));
357      }
358      break;
359   }
360
361   return data;
362}
363
364
365//-------------------------------------------------
366//  vic20_cd_w - cartridge data write
367//-------------------------------------------------
368
369void vic20_final_expansion_3_t::vic20_cd_w(address_space &space, offs_t offset, UINT8 data, int ram1, int ram2, int ram3, int blk1, int blk2, int blk3, int blk5, int io2, int io3)
370{
371   offs_t addr = 0;
372
373   switch (m_reg1 & REG1_MODE_MASK)
374   {
375   case REG1_START:
376      // write to RAM bank 1
377      if (!blk5)
378      {
379         m_ram[get_address(1, 3, offset)] = data;
380
381         m_lockbit = false;
382      }
383
384      // write to registers
385      if (!io3 && !m_lockbit && ((offset & 0x1c02) == 0x1c02))
386      {
387         write_register(BIT(offset, 0), data);
388      }
389      break;
390     
391   case REG1_SUPER_ROM:
392      addr = 0x8000 | offset;
393
394      // write to RAM bank 0
395      if ((!ram1 || !ram2 || !ram3) && REG2_BLK0_VISIBLE)
396      {
397         m_ram[get_address(0, 0, offset)] = data;
398      }
399
400      // write to RAM bank 1
401      if (!blk1 && REG2_BLK1_VISIBLE)
402      {
403         m_ram[get_address(1, 0, offset)] = data;
404      }
405      if (!blk2 && REG2_BLK2_VISIBLE)
406      {
407         m_ram[get_address(1, 1, offset)] = data;
408      }
409      if (!blk3 && REG2_BLK3_VISIBLE)
410      {
411         m_ram[get_address(1, 2, offset)] = data;
412      }
413      if (!blk5 && REG2_BLK5_VISIBLE)
414      {
415         m_ram[get_address(1, 3, offset)] = data;
416      }
417
418      // write to registers
419      if (!io3 && !(m_reg2 & REG2_IO3) && ((offset & 0x1c02) == 0x1c02))
420      {
421         write_register(BIT(offset, 0), data);
422      }
423      break;
424     
425   case REG1_RAM_1:
426      // write to RAM bank 0
427      if ((!ram1 || !ram2 || !ram3) && REG2_BLK0_VISIBLE && REG1_BLK0)
428      {
429         m_ram[get_address(0, 0, offset)] = data;
430      }
431
432      // write to RAM bank 1 or 2
433      if (!blk1 && REG2_BLK1_VISIBLE)
434      {
435         m_ram[get_address((m_reg1 & REG1_BLK1) ? 2 : 1, 0, offset)] = data;
436      }
437      if (!blk2 && REG2_BLK2_VISIBLE)
438      {
439         m_ram[get_address((m_reg1 & REG1_BLK2) ? 2 : 1, 1, offset)] = data;
440      }
441      if (!blk3 && REG2_BLK3_VISIBLE)
442      {
443         m_ram[get_address((m_reg1 & REG1_BLK3) ? 2 : 1, 2, offset)] = data;
444      }
445      if (!blk5 && REG2_BLK5_VISIBLE)
446      {
447         m_ram[get_address((m_reg1 & REG1_BLK5) ? 2 : 1, 3, offset)] = data;
448      }
449
450      // write to registers
451      if (!io3 && !(m_reg2 & REG2_IO3) && ((offset & 0x1c02) == 0x1c02))
452      {
453         write_register(BIT(offset, 0), data);
454      }
455      break;
456     
457   case REG1_RAM_2:
458      // write to RAM bank 0
459      if ((!ram1 || !ram2 || !ram3) && REG2_BLK0_VISIBLE && REG1_BLK0)
460      {
461         m_ram[get_address(0, 0, offset)] = data;
462      }
463
464      // write to RAM bank 1
465      if (!blk1 && REG2_BLK1_VISIBLE)
466      {
467         m_ram[get_address(1, 0, offset)] = data;
468      }
469      if (!blk2 && REG2_BLK2_VISIBLE)
470      {
471         m_ram[get_address(1, 1, offset)] = data;
472      }
473      if (!blk3 && REG2_BLK3_VISIBLE)
474      {
475         m_ram[get_address(1, 2, offset)] = data;
476      }
477      if (!blk5 && REG2_BLK5_VISIBLE)
478      {
479         m_ram[get_address(1, 3, offset)] = data;
480      }
481
482      // write to registers
483      if (!io3 && !(m_reg2 & REG2_IO3) && ((offset & 0x1c02) == 0x1c02))
484      {
485         write_register(BIT(offset, 0), data);
486      }
487      break;
488     
489   case REG1_SUPER_RAM:
490      // write to RAM bank 0
491      if ((!ram1 || !ram2 || !ram3) && REG2_BLK0_VISIBLE)
492      {
493         m_ram[get_address(0, 0, offset)] = data;
494      }
495
496      // write whole RAM
497      if (!blk1 && REG2_BLK1_VISIBLE)
498      {
499         m_ram[get_address(REG1_BANK, 0, offset)] = data;
500      }
501      if (!blk2 && REG2_BLK2_VISIBLE)
502      {
503         m_ram[get_address(REG1_BANK, 1, offset)] = data;
504      }
505      if (!blk3 && REG2_BLK3_VISIBLE)
506      {
507         m_ram[get_address(REG1_BANK, 2, offset)] = data;
508      }
509      if (!blk5 && REG2_BLK5_VISIBLE)
510      {
511         m_ram[get_address(REG1_BANK, 3, offset)] = data;
512      }
513
514      // write to registers
515      if (!io3 && !(m_reg2 & REG2_IO3) && ((offset & 0x1c02) == 0x1c02))
516      {
517         write_register(BIT(offset, 0), data);
518      }
519      break;
520     
521   case REG1_RAM_ROM:
522      // write to RAM bank 0
523      if ((!ram1 || !ram2 || !ram3) && REG2_BLK0_VISIBLE && REG1_BLK0)
524      {
525         m_ram[get_address(0, 0, offset)] = data;
526      }
527
528      // write to RAM bank 1 or 2
529      if (!blk1 && REG2_BLK1_VISIBLE)
530      {
531         m_ram[get_address((m_reg1 & REG1_BLK1) ? 2 : 1, 0, offset)] = data;
532      }
533      if (!blk2 && REG2_BLK2_VISIBLE)
534      {
535         m_ram[get_address((m_reg1 & REG1_BLK2) ? 2 : 1, 1, offset)] = data;
536      }
537      if (!blk3 && REG2_BLK3_VISIBLE)
538      {
539         m_ram[get_address((m_reg1 & REG1_BLK3) ? 2 : 1, 2, offset)] = data;
540      }
541      if (!blk5 && REG2_BLK5_VISIBLE)
542      {
543         m_ram[get_address((m_reg1 & REG1_BLK5) ? 2 : 1, 3, offset)] = data;
544      }
545
546      // write to registers
547      if (!io3 && !(m_reg2 & REG2_IO3) && ((offset & 0x1c02) == 0x1c02))
548      {
549         write_register(BIT(offset, 0), data);
550      }
551      break;
552     
553   case REG1_FLASH:
554      // write to RAM bank 0
555      if ((!ram1 || !ram2 || !ram3) && REG2_BLK0_VISIBLE)
556      {
557         m_ram[get_address(0, 0, offset)] = data;
558      }
559
560      // write to ROM
561      if (!blk1 && REG2_BLK1_VISIBLE)
562      {
563         m_flash_rom->write(get_address(REG1_BANK, 0, offset), data);
564      }
565      if (!blk2 && REG2_BLK2_VISIBLE)
566      {
567         m_flash_rom->write(get_address(REG1_BANK, 1, offset), data);
568      }
569      if (!blk3 && REG2_BLK3_VISIBLE)
570      {
571         m_flash_rom->write(get_address(REG1_BANK, 2, offset), data);
572      }
573      if (!blk5 && REG2_BLK5_VISIBLE)
574      {
575         m_flash_rom->write(get_address(REG1_BANK, 3, offset), data);
576      }
577
578      // write to registers
579      if (!io3 && !(m_reg2 & REG2_IO3) && ((offset & 0x1c02) == 0x1c02))
580      {
581         write_register(BIT(offset, 0), data);
582      }
583   }
584}
585
586
587//-------------------------------------------------
588//  get_address -
589//-------------------------------------------------
590
591offs_t vic20_final_expansion_3_t::get_address(int bank, int block, offs_t offset)
592{
593   block ^= (m_reg2 >> 5) & 0x03;
594
595   return bank << 15 | block << 13 | offset;
596}
597
598
599//-------------------------------------------------
600//  read_register -
601//-------------------------------------------------
602
603UINT8 vic20_final_expansion_3_t::read_register(offs_t offset)
604{
605   UINT8 data = 0;
606
607   switch (offset)
608   {
609   case 0:
610      data = m_reg1;
611      break;
612
613   case 1:
614      data = m_reg2;
615      break;
616   }
617
618   return data;
619}
620
621
622//-------------------------------------------------
623//  write_register -
624//-------------------------------------------------
625
626void vic20_final_expansion_3_t::write_register(offs_t offset, UINT8 data)
627{
628   switch (offset)
629   {
630   case 0:
631      m_reg1 = data;
632      break;
633
634   case 1:
635      m_reg2 = data;
636      break;
637   }
638}
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trunk/src/emu/bus/vic20/fe3.h
r0r32614
1// license:BSD-3-Clause
2// copyright-holders:Curt Coder
3/**********************************************************************
4
5    Final Expansion v3 cartridge emulation
6
7    Copyright MESS Team.
8    Visit http://mamedev.org for licensing and usage restrictions.
9
10**********************************************************************/
11
12#pragma once
13
14#ifndef __VIC20_FE3__
15#define __VIC20_FE3__
16
17#include "emu.h"
18#include "exp.h"
19#include "machine/intelfsh.h"
20
21
22
23//**************************************************************************
24//  TYPE DEFINITIONS
25//**************************************************************************
26
27// ======================> vic20_final_expansion_3_t
28
29class vic20_final_expansion_3_t :  public device_t,
30                           public device_vic20_expansion_card_interface
31{
32public:
33   // construction/destruction
34   vic20_final_expansion_3_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
35
36   // optional information overrides
37   virtual const rom_entry *device_rom_region() const;
38   virtual machine_config_constructor device_mconfig_additions() const;
39
40protected:
41   // device-level overrides
42   virtual void device_start();
43   virtual void device_reset();
44
45   // device_vic20_expansion_card_interface overrides
46   virtual UINT8 vic20_cd_r(address_space &space, offs_t offset, UINT8 data, int ram1, int ram2, int ram3, int blk1, int blk2, int blk3, int blk5, int io2, int io3);
47   virtual void vic20_cd_w(address_space &space, offs_t offset, UINT8 data, int ram1, int ram2, int ram3, int blk1, int blk2, int blk3, int blk5, int io2, int io3);
48
49private:
50   enum
51   {
52      REG1_BLK0      = 0x01,
53      REG1_BLK1      = 0x02,
54      REG1_BLK2      = 0x04,
55      REG1_BLK3      = 0x08,
56      REG1_BLK5      = 0x10,
57      REG1_START     = 0x00,
58      REG1_SUPER_ROM = 0x40,
59      REG1_RAM_1     = 0x80,
60      REG1_RAM_2     = 0xc0,
61      REG1_SUPER_RAM = 0xa0,
62      REG1_RAM_ROM   = 0x60,
63      REG1_FLASH     = 0x20,
64      REG1_MODE_MASK = 0xe0
65   };
66
67   enum
68   {
69      REG2_BLK0 = 0x01,
70      REG2_BLK1 = 0x02,
71      REG2_BLK2 = 0x04,
72      REG2_BLK3 = 0x08,
73      REG2_BLK5 = 0x10,
74      REG2_A13  = 0x20,
75      REG2_A14  = 0x40,
76      REG2_IO3  = 0x80
77   };
78
79   offs_t get_address(int bank, int block, offs_t offset);
80   UINT8 read_register(offs_t offset);
81   void write_register(offs_t offset, UINT8 data);
82
83   required_device<amd_29f040_device> m_flash_rom;
84   optional_shared_ptr<UINT8> m_ram;
85
86   UINT8 m_reg1;
87   UINT8 m_reg2;
88   bool m_lockbit;
89};
90
91
92// device type definition
93extern const device_type VIC20_FE3;
94
95
96
97#endif
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