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r32591 Thursday 9th October, 2014 at 03:12:07 UTC by Robbbert
gts80.c : WIP
[src/mame/drivers]gts80.c spectra.c
[src/mame/layout]gts80.lay

trunk/src/mame/layout/gts80.lay
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99         <color red="0.0" green="0.75" blue="1.0" />
1010      </led14seg>
1111   </element>
12   <element name="digit7" defstate="0">
13      <led7seg>
14         <color red="0.0" green="0.75" blue="1.0" />
15      </led7seg>
16   </element>
1217   <element name="red_led">
1318      <disk><color red="1.0" green="0.0" blue="0.0" /></disk>
1419   </element>
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5661      </bezel>
5762
5863      <!-- Player 2 Score -->
59      <bezel name="digit15" element="digit">
64      <bezel name="digit11" element="digit">
6065         <bounds left="10" top="105" right="44" bottom="144" />
6166      </bezel>
62      <bezel name="digit14" element="digit">
67      <bezel name="digit10" element="digit">
6368         <bounds left="54" top="105" right="88" bottom="144" />
6469      </bezel>
65      <bezel name="digit13" element="digit">
70      <bezel name="digit9" element="digit">
6671         <bounds left="98" top="105" right="132" bottom="144" />
6772      </bezel>
68      <bezel name="digit12" element="digit">
73      <bezel name="digit8" element="digit">
6974         <bounds left="142" top="105" right="176" bottom="144" />
7075      </bezel>
71      <bezel name="digit11" element="digit">
76      <bezel name="digit7" element="digit">
7277         <bounds left="186" top="105" right="220" bottom="144" />
7378      </bezel>
74      <bezel name="digit10" element="digit">
79      <bezel name="digit6" element="digit">
7580         <bounds left="230" top="105" right="264" bottom="144" />
7681      </bezel>
7782
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96101      </bezel>
97102
98103      <!-- Player 4 Score -->
99      <bezel name="digit35" element="digit">
104      <bezel name="digit31" element="digit">
100105         <bounds left="10" top="225" right="44" bottom="264" />
101106      </bezel>
102      <bezel name="digit34" element="digit">
107      <bezel name="digit30" element="digit">
103108         <bounds left="54" top="225" right="88" bottom="264" />
104109      </bezel>
105      <bezel name="digit33" element="digit">
110      <bezel name="digit29" element="digit">
106111         <bounds left="98" top="225" right="132" bottom="264" />
107112      </bezel>
108      <bezel name="digit32" element="digit">
113      <bezel name="digit28" element="digit">
109114         <bounds left="142" top="225" right="176" bottom="264" />
110115      </bezel>
111      <bezel name="digit31" element="digit">
116      <bezel name="digit27" element="digit">
112117         <bounds left="186" top="225" right="220" bottom="264" />
113118      </bezel>
114      <bezel name="digit30" element="digit">
119      <bezel name="digit26" element="digit">
115120         <bounds left="230" top="225" right="264" bottom="264" />
116121      </bezel>
117122
118123      <!-- Credits and Balls -->
119      <bezel name="digit41" element="digit">
124      <bezel name="digit41" element="digit7">
120125         <bounds left="30" top="345" right="64" bottom="384" />
121126      </bezel>
122      <bezel name="digit40" element="digit">
127      <bezel name="digit40" element="digit7">
123128         <bounds left="69" top="345" right="103" bottom="384" />
124129      </bezel>
125      <bezel name="digit44" element="digit">
130      <bezel name="digit44" element="digit7">
126131         <bounds left="171" top="345" right="205" bottom="384" />
127132      </bezel>
128      <bezel name="digit43" element="digit">
133      <bezel name="digit43" element="digit7">
129134         <bounds left="210" top="345" right="244" bottom="384" />
130135      </bezel>
131136      <bezel element="P1"><bounds left="200" right="258" top="330" bottom="342" /></bezel>
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134139      <bezel name="text2" element="P4"><bounds left="100" right="180" top="90" bottom="102" /></bezel>
135140      <bezel name="text1" element="P5"><bounds left="100" right="180" top="150" bottom="162" /></bezel>
136141      <bezel name="text0" element="P6"><bounds left="100" right="180" top="210" bottom="222" /></bezel>
137      <bezel name="led0" element="red_led">
138         <bounds left="10" right="25" top="360" bottom="375" /></bezel>
139142   </view>
140143</mamelayout>
trunk/src/mame/drivers/gts80.c
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55
66
77ToDO:
8- Everything
8- Switches
9- Outputs
10- Mechanical sounds
11- Sound
912
1013
1114************************************************************************************************************/
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3336   DECLARE_WRITE8_MEMBER(port3a_w);
3437   DECLARE_WRITE8_MEMBER(port3b_w);
3538private:
39   UINT8 m_port2;
40   UINT8 m_segment;
41   UINT8 m_row;
42   UINT8 m_kbdrow;
3643   virtual void machine_reset();
3744   required_device<cpu_device> m_maincpu;
3845};
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4451   AM_RANGE(0x0280, 0x02ff) AM_DEVREADWRITE("riot2", riot6532_device, read, write)
4552   AM_RANGE(0x0300, 0x037f) AM_DEVREADWRITE("riot3", riot6532_device, read, write)
4653   AM_RANGE(0x1000, 0x17ff) AM_ROM
47   AM_RANGE(0x1800, 0x18ff) AM_RAM AM_MIRROR(0x700) // the existence of this ram isn't confirmed yet
54   AM_RANGE(0x1800, 0x18ff) AM_RAM AM_SHARE("nvram") // 5101L-1 256x4
4855   AM_RANGE(0x2000, 0x2fff) AM_ROM
4956   AM_RANGE(0x3000, 0x3fff) AM_ROM
5057ADDRESS_MAP_END
5158
5259
5360static INPUT_PORTS_START( gts80 )
61   PORT_START("DSW.0")
62   PORT_DIPNAME( 0x80, 0x00, "SW 1")
63   PORT_DIPSETTING(    0x00, DEF_STR(Off))
64   PORT_DIPSETTING(    0x80, DEF_STR(On))
65   PORT_DIPNAME( 0x40, 0x00, "SW 2")
66   PORT_DIPSETTING(    0x00, DEF_STR(Off))
67   PORT_DIPSETTING(    0x40, DEF_STR(On))
68   PORT_DIPNAME( 0x20, 0x00, "SW 3")
69   PORT_DIPSETTING(    0x00, DEF_STR(Off))
70   PORT_DIPSETTING(    0x20, DEF_STR(On))
71   PORT_DIPNAME( 0x10, 0x00, "SW 4")
72   PORT_DIPSETTING(    0x00, DEF_STR(Off))
73   PORT_DIPSETTING(    0x10, DEF_STR(On))
74   PORT_DIPNAME( 0x08, 0x00, "SW 5")
75   PORT_DIPSETTING(    0x00, DEF_STR(Off))
76   PORT_DIPSETTING(    0x08, DEF_STR(On))
77   PORT_DIPNAME( 0x04, 0x00, "SW 6")
78   PORT_DIPSETTING(    0x00, DEF_STR(Off))
79   PORT_DIPSETTING(    0x04, DEF_STR(On))
80   PORT_DIPNAME( 0x02, 0x00, "SW 7")
81   PORT_DIPSETTING(    0x00, DEF_STR(Off))
82   PORT_DIPSETTING(    0x02, DEF_STR(On))
83   PORT_DIPNAME( 0x01, 0x00, "SW 8")
84   PORT_DIPSETTING(    0x00, DEF_STR(Off))
85   PORT_DIPSETTING(    0x01, DEF_STR(On))
86
87   PORT_START("DSW.1")
88   PORT_DIPNAME( 0x80, 0x00, "SW 9")
89   PORT_DIPSETTING(    0x00, DEF_STR(Off))
90   PORT_DIPSETTING(    0x80, DEF_STR(On))
91   PORT_DIPNAME( 0x40, 0x00, "SW 10")
92   PORT_DIPSETTING(    0x00, DEF_STR(Off))
93   PORT_DIPSETTING(    0x40, DEF_STR(On))
94   PORT_DIPNAME( 0x20, 0x00, "SW 11")
95   PORT_DIPSETTING(    0x00, DEF_STR(Off))
96   PORT_DIPSETTING(    0x20, DEF_STR(On))
97   PORT_DIPNAME( 0x10, 0x00, "SW 12")
98   PORT_DIPSETTING(    0x00, DEF_STR(Off))
99   PORT_DIPSETTING(    0x10, DEF_STR(On))
100   PORT_DIPNAME( 0x08, 0x00, "SW 13")
101   PORT_DIPSETTING(    0x00, DEF_STR(Off))
102   PORT_DIPSETTING(    0x08, DEF_STR(On))
103   PORT_DIPNAME( 0x04, 0x00, "SW 14")
104   PORT_DIPSETTING(    0x00, DEF_STR(Off))
105   PORT_DIPSETTING(    0x04, DEF_STR(On))
106   PORT_DIPNAME( 0x02, 0x02, "SW 15")
107   PORT_DIPSETTING(    0x00, DEF_STR(Off))
108   PORT_DIPSETTING(    0x02, DEF_STR(On))
109   PORT_DIPNAME( 0x01, 0x00, "SW 16")
110   PORT_DIPSETTING(    0x00, DEF_STR(Off))
111   PORT_DIPSETTING(    0x01, DEF_STR(On))
112
113   PORT_START("DSW.2")
114   PORT_DIPNAME( 0x80, 0x80, "SW 17")
115   PORT_DIPSETTING(    0x00, DEF_STR(Off))
116   PORT_DIPSETTING(    0x80, DEF_STR(On))
117   PORT_DIPNAME( 0x40, 0x40, "SW 18")
118   PORT_DIPSETTING(    0x00, DEF_STR(Off))
119   PORT_DIPSETTING(    0x40, DEF_STR(On))
120   PORT_DIPNAME( 0x20, 0x00, "SW 19")
121   PORT_DIPSETTING(    0x00, DEF_STR(Off))
122   PORT_DIPSETTING(    0x20, DEF_STR(On))
123   PORT_DIPNAME( 0x10, 0x00, "SW 20")
124   PORT_DIPSETTING(    0x00, DEF_STR(Off))
125   PORT_DIPSETTING(    0x10, DEF_STR(On))
126   PORT_DIPNAME( 0x08, 0x00, "SW 21")
127   PORT_DIPSETTING(    0x00, DEF_STR(Off))
128   PORT_DIPSETTING(    0x08, DEF_STR(On))
129   PORT_DIPNAME( 0x04, 0x00, "SW 22")
130   PORT_DIPSETTING(    0x00, DEF_STR(Off))
131   PORT_DIPSETTING(    0x04, DEF_STR(On))
132   PORT_DIPNAME( 0x02, 0x02, "SW 23")
133   PORT_DIPSETTING(    0x00, DEF_STR(Off))
134   PORT_DIPSETTING(    0x02, DEF_STR(On))
135   PORT_DIPNAME( 0x01, 0x01, "SW 24")
136   PORT_DIPSETTING(    0x00, DEF_STR(Off))
137   PORT_DIPSETTING(    0x01, DEF_STR(On))
138
139   PORT_START("DSW.3")
140   PORT_DIPNAME( 0x80, 0x80, "SW 25")
141   PORT_DIPSETTING(    0x00, DEF_STR(Off))
142   PORT_DIPSETTING(    0x80, DEF_STR(On))
143   PORT_DIPNAME( 0x40, 0x40, "SW 26")
144   PORT_DIPSETTING(    0x00, DEF_STR(Off))
145   PORT_DIPSETTING(    0x40, DEF_STR(On))
146   PORT_DIPNAME( 0x20, 0x20, "SW 27")
147   PORT_DIPSETTING(    0x00, DEF_STR(Off))
148   PORT_DIPSETTING(    0x20, DEF_STR(On))
149   PORT_DIPNAME( 0x10, 0x10, "SW 28")
150   PORT_DIPSETTING(    0x00, DEF_STR(Off))
151   PORT_DIPSETTING(    0x10, DEF_STR(On))
152   PORT_DIPNAME( 0x08, 0x08, "SW 29")
153   PORT_DIPSETTING(    0x00, DEF_STR(Off))
154   PORT_DIPSETTING(    0x08, DEF_STR(On))
155   PORT_DIPNAME( 0x04, 0x04, "SW 30")
156   PORT_DIPSETTING(    0x00, DEF_STR(Off))
157   PORT_DIPSETTING(    0x04, DEF_STR(On))
158   PORT_DIPNAME( 0x02, 0x00, "SW 31")
159   PORT_DIPSETTING(    0x00, DEF_STR(Off))
160   PORT_DIPSETTING(    0x02, DEF_STR(On))
161   PORT_DIPNAME( 0x01, 0x00, "SW 32")
162   PORT_DIPSETTING(    0x00, DEF_STR(Off))
163   PORT_DIPSETTING(    0x01, DEF_STR(On))
164
165   PORT_START("X0")
166   PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
167
168   PORT_START("X1")
169   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_TILT )
170   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER )
171   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START )
172   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN3 )
173   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN2 )
174   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN1 )
175   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER )
176   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER )
177
178   PORT_START("X2")
179   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_X)
180   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_S)
181   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_D)
182   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_F)
183   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_G)
184   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_H)
185   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_J)
186   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_K)
187
188   PORT_START("X4")
189   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_L)
190   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Z)
191   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_C)
192   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_V)
193   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_B)
194   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_N)
195   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_M)
196   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_COMMA)
197
198   PORT_START("X8")
199   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_STOP)
200   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_SLASH)
201   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_COLON)
202   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_QUOTE)
203   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_A)
204   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_MINUS)
205   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_EQUALS)
206   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_BACKSPACE)
207
208   PORT_START("X10")
209   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_OPENBRACE)
210   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_CLOSEBRACE)
211   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_BACKSLASH)
212   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_ENTER)
213   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_LEFT)
214   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_RIGHT)
215   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_UP)
216   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_DOWN)
217
218   PORT_START("X20")
219//   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Q)
220//   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_W)
221//   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_E)
222//   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_R)
223//   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Y)
224//   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_U)
225//   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_I)
226//   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_O)
227
228   PORT_START("X40")
229//   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Q)
230//   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_W)
231//   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_E)
232//   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_R)
233//   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Y)
234//   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_U)
235//   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_I)
236//   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_O)
237
238   PORT_START("X80")
239   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Q)
240   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_W)
241   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_E)
242   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_R)
243   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Y)
244   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_U)
245   PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_I)
246   PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_O)
54247INPUT_PORTS_END
55248
56249READ8_MEMBER( gts80_state::port1a_r )
57250{
58   return 0xff;
251   char kbdrow[8];
252   if ((m_row < 4) && (m_segment==0x80))
253   {
254      sprintf(kbdrow,"DSW.%d",m_row);
255      return ioport(kbdrow)->read();
256   }
257   else
258   {
259      sprintf(kbdrow,"X%X",m_kbdrow);
260      return ioport(kbdrow)->read() ^ 0xff; // inverted through 7404
261   }
262
263   return 0;
59264}
60265
61266READ8_MEMBER( gts80_state::port2a_r )
62267{
63   return 0xff;
268   return m_port2 | 0x80; // slam tilt off
64269}
65270
66271WRITE8_MEMBER( gts80_state::port1b_w )
67272{
273   m_kbdrow = data & 15;//printf("%X ",data);
68274}
69275
276// schematic and pinmame say '1' is indicated by m_segment !bits 4,5,6, but it is !bit 7
70277WRITE8_MEMBER( gts80_state::port2a_w )
71278{
72//printf("A:%X ",data);
279   m_port2 = data;
280   static const UINT8 patterns[16] = { 0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7c,0x07,0x7f,0x67,0x58,0x4c,0x62,0x69,0x78,0 }; // 7448
281   UINT16 seg1 = (UINT16)patterns[m_segment & 15];
282   UINT16 seg2 = BITSWAP16(seg1, 8, 8, 8, 8, 8, 8, 7, 7, 6, 6, 5, 4, 3, 2, 1, 0);
283   switch (data & 0x70)
284   {
285      case 0x10: // player 1&2
286         if (!BIT(m_segment, 7)) seg2 |= 0x300; // put '1' in the middle
287         output_set_digit_value(data & 15, seg2);
288         break;
289      case 0x20: // player 3&4
290         if (!BIT(m_segment, 7)) seg2 |= 0x300; // put '1' in the middle
291         output_set_digit_value((data & 15)+20, seg2);
292         break;
293      case 0x40: // credits & balls
294         if (!BIT(m_segment, 7)) m_segment = 1; // turn '1' back to normal
295         output_set_digit_value((data & 15)+40, patterns[m_segment & 15]);
296         break;
297   }
73298}
74299
300//d0-3 bcd data; d4-6 = centre segment; d7 = dipsw enable
75301WRITE8_MEMBER( gts80_state::port2b_w )
76302{
77//printf("B:%X ",data);
303   m_segment = data;//printf("%s:%X ",machine().describe_context(),data);
78304}
79305
80306WRITE8_MEMBER( gts80_state::port3a_w )
r32590r32591
83309
84310WRITE8_MEMBER( gts80_state::port3b_w )
85311{
312   m_row = data >> 4;
86313}
87314
88315void gts80_state::machine_reset()
r32590r32591
96323/* with Sound Board */
97324static MACHINE_CONFIG_START( gts80_s, gts80_state )
98325   /* basic machine hardware */
99   MCFG_CPU_ADD("maincpu", M6502, 850000) // xtal frequency not shown
326   MCFG_CPU_ADD("maincpu", M6502, XTAL_3_579545MHz/4)
100327   MCFG_CPU_PROGRAM_MAP(gts80_map)
101328
329   MCFG_NVRAM_ADD_1FILL("nvram") // must be 1
330
102331   /* Video */
103332   MCFG_DEFAULT_LAYOUT(layout_gts80)
104333
105334   /* Devices */
106   MCFG_DEVICE_ADD("riot1", RIOT6532, 850000)
335   MCFG_DEVICE_ADD("riot1", RIOT6532, XTAL_3_579545MHz/4)
107336   MCFG_RIOT6532_IN_PA_CB(READ8(gts80_state, port1a_r)) // sw_r
108337   //MCFG_RIOT6532_OUT_PA_CB(WRITE8(gts80_state, port1a_w))
109338   //MCFG_RIOT6532_IN_PB_CB(READ8(gts80_state, port1b_r))
trunk/src/mame/drivers/spectra.c
r32590r32591
248248
249249static MACHINE_CONFIG_START( spectra, spectra_state )
250250   /* basic machine hardware */
251   MCFG_CPU_ADD("maincpu", M6502, 3579545/4)  // actually a M6503
251   MCFG_CPU_ADD("maincpu", M6502, XTAL_3_579545MHz/4)  // actually a M6503
252252   MCFG_CPU_PROGRAM_MAP(spectra_map)
253253
254   MCFG_DEVICE_ADD("riot", RIOT6532, 3579545/4)
254   MCFG_DEVICE_ADD("riot", RIOT6532, XTAL_3_579545MHz/4)
255255   MCFG_RIOT6532_IN_PA_CB(READ8(spectra_state, porta_r))
256256   MCFG_RIOT6532_OUT_PA_CB(WRITE8(spectra_state, porta_w))
257257   MCFG_RIOT6532_IN_PB_CB(READ8(spectra_state, portb_r))

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