trunk/src/mess/drivers/pc9801.c
| r32557 | r32558 | |
| 649 | 649 | DECLARE_READ8_MEMBER(pic_r); |
| 650 | 650 | DECLARE_WRITE8_MEMBER(pic_w); |
| 651 | 651 | |
| 652 | | DECLARE_READ8_MEMBER(pc9801rs_ide_io_0_r); |
| 653 | | DECLARE_READ16_MEMBER(pc9801rs_ide_io_1_r); |
| 654 | | DECLARE_READ16_MEMBER(pc9801rs_ide_io_2_r); |
| 655 | | DECLARE_WRITE8_MEMBER(pc9801rs_ide_io_0_w); |
| 656 | | DECLARE_WRITE16_MEMBER(pc9801rs_ide_io_1_w); |
| 657 | | DECLARE_WRITE16_MEMBER(pc9801rs_ide_io_2_w); |
| 658 | | |
| 659 | 652 | DECLARE_READ8_MEMBER(sdip_0_r); |
| 660 | 653 | DECLARE_READ8_MEMBER(sdip_1_r); |
| 661 | 654 | DECLARE_READ8_MEMBER(sdip_2_r); |
| r32557 | r32558 | |
| 2054 | 2047 | else if(offset >= 0x000b8000 && offset <= 0x000bffff) { return m_pc9801rs_grcg_r(offset & 0x7fff,3); } |
| 2055 | 2048 | else if(offset >= 0x000cc000 && offset <= 0x000cffff) { return pc9801rs_soundrom_r(space,offset & 0x3fff);} |
| 2056 | 2049 | else if(offset >= 0x000d8000 && offset <= 0x000d9fff) { return pc9801rs_ide_r(space,offset & 0x1fff); } |
| 2050 | else if(offset >= 0x000da000 && offset <= 0x000dbfff) { return pc9821_ideram_r(space,offset & 0x1fff); } |
| 2057 | 2051 | else if(offset >= 0x000e0000 && offset <= 0x000e7fff) { return m_pc9801rs_grcg_r(offset & 0x7fff,0); } |
| 2058 | 2052 | else if(offset >= 0x000e0000 && offset <= 0x000fffff) { return pc9801rs_ipl_r(space,offset & 0x1ffff); } |
| 2059 | 2053 | else if(offset >= 0x00100000 && offset <= 0x00100000+m_ram_size-1) { return pc9801rs_ex_wram_r(space,offset-0x00100000); } |
| r32557 | r32558 | |
| 2075 | 2069 | else if(offset >= 0x000a8000 && offset <= 0x000affff) { m_pc9801rs_grcg_w(offset & 0x7fff,1,data); } |
| 2076 | 2070 | else if(offset >= 0x000b0000 && offset <= 0x000b7fff) { m_pc9801rs_grcg_w(offset & 0x7fff,2,data); } |
| 2077 | 2071 | else if(offset >= 0x000b8000 && offset <= 0x000bffff) { m_pc9801rs_grcg_w(offset & 0x7fff,3,data); } |
| 2072 | else if(offset >= 0x000da000 && offset <= 0x000dbfff) { pc9821_ideram_w(space,offset & 0x1fff,data); } |
| 2078 | 2073 | else if(offset >= 0x000e0000 && offset <= 0x000e7fff) { m_pc9801rs_grcg_w(offset & 0x7fff,0,data); } |
| 2079 | 2074 | else if(offset >= 0x00100000 && offset <= 0x00100000+m_ram_size-1) { pc9801rs_ex_wram_w(space,offset-0x00100000,data); } |
| 2080 | 2075 | //else |
| r32557 | r32558 | |
| 2308 | 2303 | } |
| 2309 | 2304 | } |
| 2310 | 2305 | |
| 2311 | | READ8_MEMBER(pc9801_state::pc9801rs_ide_io_0_r) |
| 2312 | | { |
| 2313 | | printf("IDE r %02x\n",offset); |
| 2314 | | return m_ide_bank[offset]; |
| 2315 | | } |
| 2316 | | |
| 2317 | | WRITE8_MEMBER(pc9801_state::pc9801rs_ide_io_0_w) |
| 2318 | | { |
| 2319 | | /* |
| 2320 | | [0x430] |
| 2321 | | [Read/write] |
| 2322 | | bit 7-0: unknown |
| 2323 | | 00 h = IDE Bank # 1 |
| 2324 | | 01 h = IDE Bank # 2 |
| 2325 | | |
| 2326 | | [0x432] |
| 2327 | | bit 7-0: Bank select |
| 2328 | | 80 h = readout for dummy (only [WRITE]) |
| 2329 | | 00 h = IDE Bank # 1 choice |
| 2330 | | 01 h = IDE Bank # 2 selection |
| 2331 | | */ |
| 2332 | | |
| 2333 | | printf("IDE w %02x %02x\n",offset,data); |
| 2334 | | |
| 2335 | | if ((data & 0x80) == 0x00) |
| 2336 | | m_ide_bank[offset] = data & 0x7f; |
| 2337 | | } |
| 2338 | | |
| 2339 | | /* TODO: is mapping correct? */ |
| 2340 | | READ16_MEMBER(pc9801_state::pc9801rs_ide_io_1_r) |
| 2341 | | { |
| 2342 | | return m_ide->read_cs0(space, offset, mem_mask); |
| 2343 | | } |
| 2344 | | |
| 2345 | | WRITE16_MEMBER(pc9801_state::pc9801rs_ide_io_1_w) |
| 2346 | | { |
| 2347 | | m_ide->write_cs0(space, offset, data, mem_mask); |
| 2348 | | } |
| 2349 | | |
| 2350 | | READ16_MEMBER(pc9801_state::pc9801rs_ide_io_2_r) |
| 2351 | | { |
| 2352 | | return m_ide->read_cs1(space, offset + 6, mem_mask); |
| 2353 | | } |
| 2354 | | |
| 2355 | | WRITE16_MEMBER(pc9801_state::pc9801rs_ide_io_2_w) |
| 2356 | | { |
| 2357 | | m_ide->write_cs1(space, offset + 6, data, mem_mask); |
| 2358 | | } |
| 2359 | | |
| 2360 | 2306 | static ADDRESS_MAP_START( pc9801rs_map, AS_PROGRAM, 32, pc9801_state ) |
| 2361 | 2307 | AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE8(pc9801rs_memory_r,pc9801rs_memory_w,0xffffffff) |
| 2362 | 2308 | ADDRESS_MAP_END |
| r32557 | r32558 | |
| 2381 | 2327 | // AM_RANGE(0x00ec, 0x00ef) PC-9801-86 sound board |
| 2382 | 2328 | AM_RANGE(0x00f0, 0x00ff) AM_READWRITE8(pc9801rs_f0_r, pc9801rs_f0_w, 0xffffffff) |
| 2383 | 2329 | // AM_RANGE(0x0188, 0x018f) AM_READWRITE8(pc9801_opn_r, pc9801_opn_w, 0xffffffff) //ym2203 opn / <undefined> |
| 2384 | | AM_RANGE(0x0430, 0x0433) AM_READWRITE8(pc9801rs_ide_io_0_r, pc9801rs_ide_io_0_w,0x00ff00ff) |
| 2385 | 2330 | |
| 2386 | 2331 | AM_RANGE(0x0438, 0x043b) AM_READWRITE8(pc9801rs_access_ctrl_r,pc9801rs_access_ctrl_w,0xffffffff) |
| 2387 | 2332 | AM_RANGE(0x043c, 0x043f) AM_WRITE8(pc9801rs_bank_w, 0xffffffff) //ROM/RAM bank |
| 2388 | 2333 | |
| 2389 | | AM_RANGE(0x0640, 0x064f) AM_READWRITE16(pc9801rs_ide_io_1_r, pc9801rs_ide_io_1_w,0xffffffff) |
| 2390 | | AM_RANGE(0x074c, 0x074f) AM_READWRITE16(pc9801rs_ide_io_2_r, pc9801rs_ide_io_2_w,0xffffffff) |
| 2334 | AM_RANGE(0x0640, 0x064f) AM_DEVREADWRITE16("ide", ata_interface_device, read_cs0, write_cs0, 0xffffffff) |
| 2335 | AM_RANGE(0x0740, 0x074f) AM_DEVREADWRITE16("ide", ata_interface_device, read_cs1, write_cs1, 0xffffffff) |
| 2391 | 2336 | |
| 2392 | 2337 | AM_RANGE(0x3fd8, 0x3fdf) AM_READWRITE8(pc9801rs_pit_mirror_r, pc9801rs_pit_mirror_w, 0xffffffff) // <undefined> / pit mirror ports |
| 2393 | 2338 | AM_RANGE(0x7fd8, 0x7fdf) AM_READWRITE8(pc9801_mouse_r, pc9801_mouse_w, 0xffffffff) // <undefined> / mouse ppi8255 ports |
| r32557 | r32558 | |
| 2751 | 2696 | AM_RANGE(0x00f0, 0x00ff) AM_READWRITE8(pc9801rs_f0_r, pc9801rs_f0_w, 0xffffffff) |
| 2752 | 2697 | // AM_RANGE(0x0188, 0x018f) AM_READWRITE8(pc9801_opn_r, pc9801_opn_w, 0xffffffff) //ym2203 opn / <undefined> |
| 2753 | 2698 | // AM_RANGE(0x018c, 0x018f) YM2203 OPN extended ports / <undefined> |
| 2754 | | AM_RANGE(0x0430, 0x0433) AM_READWRITE8(pc9801rs_ide_io_0_r, pc9801rs_ide_io_0_w,0x00ff00ff) // IDE bank register |
| 2755 | 2699 | AM_RANGE(0x0438, 0x043b) AM_READWRITE8(pc9801rs_access_ctrl_r,pc9801rs_access_ctrl_w,0xffffffff) |
| 2756 | 2700 | // AM_RANGE(0x043d, 0x043d) ROM/RAM bank (NEC) |
| 2757 | 2701 | AM_RANGE(0x043c, 0x043f) AM_WRITE8(pc9801rs_bank_w, 0xffffffff) //ROM/RAM bank (EPSON) |
| 2758 | 2702 | AM_RANGE(0x0460, 0x0463) AM_READWRITE8(pc9821_window_bank_r,pc9821_window_bank_w, 0xffffffff) |
| 2759 | 2703 | // AM_RANGE(0x04a0, 0x04af) EGC |
| 2760 | 2704 | // AM_RANGE(0x04be, 0x04be) FDC "RPM" register |
| 2761 | | AM_RANGE(0x0640, 0x064f) AM_READWRITE16(pc9801rs_ide_io_1_r, pc9801rs_ide_io_1_w,0xffffffff) // IDE registers / <undefined> |
| 2762 | | AM_RANGE(0x074c, 0x074f) AM_READWRITE16(pc9801rs_ide_io_2_r, pc9801rs_ide_io_2_w,0xffffffff) // IDE status (r) - IDE control registers (w) / <undefined> |
| 2705 | AM_RANGE(0x0640, 0x064f) AM_DEVREADWRITE16("ide", ata_interface_device, read_cs0, write_cs0, 0xffffffff) |
| 2706 | AM_RANGE(0x0740, 0x074f) AM_DEVREADWRITE16("ide", ata_interface_device, read_cs1, write_cs1, 0xffffffff) |
| 2763 | 2707 | // AM_RANGE(0x08e0, 0x08ea) <undefined> / EMM SIO registers |
| 2764 | 2708 | AM_RANGE(0x09a0, 0x09a3) AM_READWRITE8(pc9821_ext2_video_ff_r, pc9821_ext2_video_ff_w, 0xffffffff) // GDC extended register r/w |
| 2765 | 2709 | // AM_RANGE(0x09a8, 0x09a8) GDC 31KHz register r/w |
| r32557 | r32558 | |
| 3393 | 3337 | } |
| 3394 | 3338 | |
| 3395 | 3339 | m_ide_rom = memregion("ide")->base(); |
| 3340 | m_ide_ram = auto_alloc_array(machine(), UINT8, 0x2000); |
| 3396 | 3341 | m_sys_type = 0x80 >> 6; |
| 3342 | save_pointer(NAME(m_ide_ram), 0x2000); |
| 3397 | 3343 | } |
| 3398 | 3344 | |
| 3399 | 3345 | MACHINE_START_MEMBER(pc9801_state,pc9801bx2) |
| r32557 | r32558 | |
| 3408 | 3354 | { |
| 3409 | 3355 | MACHINE_START_CALL_MEMBER(pc9801rs); |
| 3410 | 3356 | |
| 3411 | | m_ide_ram = auto_alloc_array(machine(), UINT8, 0x2000); |
| 3412 | 3357 | m_ext_gvram = auto_alloc_array(machine(), UINT8, 0xa0000); |
| 3413 | 3358 | |
| 3414 | 3359 | save_pointer(NAME(m_sdip), 24); |
| 3415 | | save_pointer(NAME(m_ide_ram), 0x2000); |
| 3416 | 3360 | save_pointer(NAME(m_ext_gvram), 0xa0000); |
| 3417 | 3361 | } |
| 3418 | 3362 | |
| r32557 | r32558 | |
| 3431 | 3375 | int i; |
| 3432 | 3376 | static const UINT8 default_memsw_data[0x10] = |
| 3433 | 3377 | { |
| 3378 | // set high nibble of byte 9 to 0xa and comment ROM_FILL below to boot from hdd |
| 3434 | 3379 | 0xe1, 0x48, 0xe1, 0x05, 0xe1, 0x04, 0xe1, 0x00, 0xe1, 0x01, 0xe1, 0x00, 0xe1, 0x00, 0xe1, 0x6e |
| 3435 | 3380 | // 0xe1, 0xff, 0xe1, 0xff, 0xe1, 0xff, 0xe1, 0xff, 0xe1, 0xff, 0xe1, 0xff, 0xe1, 0xff, 0xe1, 0xff |
| 3436 | 3381 | }; |