trunk/src/emu/bus/isa/trident.c
| r32523 | r32524 | |
|---|
| 173 | 173 | save_pointer(vga.sequencer.data,"Sequencer Registers",0x100); |
| 174 | 174 | save_pointer(vga.attribute.data,"Attribute Registers", 0x15); |
| 175 | 175 | save_pointer(tri.accel_pattern,"Pattern Data", 0x80); |
| 176 | save_pointer(tri.lutdac_reg,"LUTDAC registers", 0x100); |
| 176 | 177 | |
| 177 | 178 | m_vblank_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(vga_device::vblank_timer_cb),this)); |
| 178 | 179 | vga.svga_intf.seq_regcount = 0x0f; |
| r32523 | r32524 | |
|---|
| 371 | 372 | case 0: |
| 372 | 373 | default: xtal = XTAL_25_1748MHz; break; |
| 373 | 374 | case 1: xtal = XTAL_28_63636MHz; break; |
| 374 | | case 2: xtal = calculate_clock(); break; // how to divide the clock? Needed for higher refresh rates (75Hz+) |
| 375 | case 2: xtal = calculate_clock(); break; |
| 375 | 376 | } |
| 376 | 377 | |
| 378 | if(tri.gc0f & 0x08) // 16 pixels per character clock |
| 379 | xtal = xtal / 2; |
| 377 | 380 | |
| 381 | if(tri.port_3db & 0x20) |
| 382 | xtal = xtal / 2; // correct? |
| 383 | |
| 378 | 384 | svga.rgb8_en = svga.rgb15_en = svga.rgb16_en = svga.rgb32_en = 0; |
| 379 | 385 | switch((tri.pixel_depth & 0x0c) >> 2) |
| 380 | 386 | { |
| r32523 | r32524 | |
|---|
| 438 | 444 | |
| 439 | 445 | void trident_vga_device::trident_seq_reg_write(UINT8 index, UINT8 data) |
| 440 | 446 | { |
| 447 | vga.sequencer.data[vga.sequencer.index] = data; |
| 441 | 448 | if(index <= 0x04) |
| 442 | 449 | { |
| 443 | | vga.sequencer.data[vga.sequencer.index] = data; |
| 444 | 450 | seq_reg_write(vga.sequencer.index,data); |
| 445 | 451 | recompute_params(); |
| 446 | 452 | } |
| r32523 | r32524 | |
|---|
| 745 | 751 | break; |
| 746 | 752 | case 0x0f: |
| 747 | 753 | tri.gc0f = data; |
| 754 | trident_define_video_mode(); |
| 748 | 755 | break; |
| 749 | 756 | case 0x2f: // XFree86 refers to this register as "MiscIntContReg", setting bit 2, but gives no indication as to what it does |
| 750 | 757 | tri.gc2f = data; |
| r32523 | r32524 | |
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| 855 | 862 | else |
| 856 | 863 | res = 0xff; |
| 857 | 864 | break; |
| 865 | case 11: |
| 866 | res = tri.port_3db; |
| 867 | break; |
| 858 | 868 | default: |
| 859 | 869 | res = vga_device::port_03d0_r(space,offset,mem_mask); |
| 860 | 870 | break; |
| r32523 | r32524 | |
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| 896 | 906 | } |
| 897 | 907 | } |
| 898 | 908 | break; |
| 909 | case 11: |
| 910 | tri.port_3db = data; // no info on this port? Bit 5 appears to be a clock divider... |
| 911 | break; |
| 899 | 912 | default: |
| 900 | 913 | vga_device::port_03d0_w(space,offset,data,mem_mask); |
| 901 | 914 | break; |