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r32358 Wednesday 24th September, 2014 at 19:52:39 UTC by Fabio Priuli
(MESS) added handling for a generic rom+ram cart (as needed by x07 expansion cards) and converted x07 and vii to use generic cartslot code. nw.

[src/emu/bus/generic]	carts.c carts.h rom.c rom.h slot.c slot.h
[src/mess/drivers]	vii.c x07.c
[src/mess/includes]	x07.h

trunk/src/emu/bus/generic/carts.c

r32357	r32358
14	14	SLOT_INTERFACE_START(generic_linear_slot)
15	15	SLOT_INTERFACE_INTERNAL("rom", GENERIC_ROM_LINEAR)
16	16	SLOT_INTERFACE_END
	17
	18	SLOT_INTERFACE_START(generic_romram_plain_slot)
	19	SLOT_INTERFACE_INTERNAL("rom", GENERIC_ROMRAM_PLAIN)
	20	SLOT_INTERFACE_END

trunk/src/emu/bus/generic/rom.c

r32357	r32358
8	8	generic_rom_plain  : returns 0xff when the system reads beyond the end of the ROM
9	9	generic_rom_linear : maps linearly the ROM in the accessed area (i.e., read offset is masked with (ROM size - 1) )
10	10
	11	generic_romram_plain  : allows support for carts always containing ROM + RAM (e.g. X07)
	12
	13
11	14	TODO:
12	15	- possibly support linear mapping when non-power of 2 ROMs are mapped
13	16
r32357	r32358
23	26
24	27	const device_type GENERIC_ROM_PLAIN  = &device_creator<generic_rom_plain_device>;
25	28	const device_type GENERIC_ROM_LINEAR = &device_creator<generic_rom_linear_device>;
	29	const device_type GENERIC_ROMRAM_PLAIN = &device_creator<generic_romram_plain_device>;
26	30
27	31
28	32	generic_rom_device::generic_rom_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
r32357	r32358
31	35	{
32	36	}
33	37
	38	generic_rom_plain_device::generic_rom_plain_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
	39	: generic_rom_device(mconfig, type, name, tag, owner, clock, shortname, source)
	40	{
	41	}
	42
34	43	generic_rom_plain_device::generic_rom_plain_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
35	44	: generic_rom_device(mconfig, GENERIC_ROM_PLAIN, "Generic ROM (plain mapping)", tag, owner, clock, "generic_rom_plain", __FILE__)
36	45	{
r32357	r32358
41	50	{
42	51	}
43	52
	53	generic_romram_plain_device::generic_romram_plain_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	54	: generic_rom_plain_device(mconfig, GENERIC_ROMRAM_PLAIN, "Generic ROM + RAM (plain mapping)", tag, owner, clock, "generic_romram_plain", __FILE__)
	55	{
	56	}
44	57
	58
45	59	/*-------------------------------------------------
46	60	mapper specific handlers
47	61	-------------------------------------------------*/
r32357	r32358
90	104	return ROM[offset % (m_rom_size/4)];
91	105	}
92	106
	107
	108	READ8_MEMBER(generic_romram_plain_device::read_ram)
	109	{
	110	if (offset < m_ram.bytes())
	111	return m_ram[offset];
	112	else
	113	return 0xff;
	114	}
	115
	116	WRITE8_MEMBER(generic_romram_plain_device::write_ram)
	117	{
	118	if (offset < m_ram.bytes())
	119	m_ram[offset] = data;
	120	}
	121

trunk/src/emu/bus/generic/carts.h

r32357	r32358
17	17
18	18	SLOT_INTERFACE_EXTERN( generic_plain_slot );
19	19	SLOT_INTERFACE_EXTERN( generic_linear_slot );
	20	SLOT_INTERFACE_EXTERN( generic_romram_plain_slot );
20	21
21	22	#endif

trunk/src/emu/bus/generic/slot.c

r32357	r32358
59	59
60	60	void device_generic_cart_interface::ram_alloc(UINT32 size)
61	61	{
62		if (m_ram == NULL)
63		{
64		m_ram.resize(size);
65		device().save_item(NAME(m_ram));
66		}
	62	m_ram.resize(size);
67	63	}
68	64
69	65

trunk/src/emu/bus/generic/rom.h

r32357	r32358
24	24	{
25	25	public:
26	26	// construction/destruction
	27	generic_rom_plain_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
27	28	generic_rom_plain_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
28	29
29	30	// reading and writing
r32357	r32358
33	34	};
34	35
35	36
	37	// ======================> generic_romram_plain_device
	38
	39	class generic_romram_plain_device : public generic_rom_plain_device
	40	{
	41	public:
	42	// construction/destruction
	43	generic_romram_plain_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	44
	45	// reading and writing
	46	virtual DECLARE_READ8_MEMBER(read_ram);
	47	virtual DECLARE_WRITE8_MEMBER(write_ram);
	48	};
	49
	50
36	51	// ======================> generic_rom_linear_device
37	52
38	53	class generic_rom_linear_device : public generic_rom_device
r32357	r32358
52	67	// device type definition
53	68	extern const device_type GENERIC_ROM_PLAIN;
54	69	extern const device_type GENERIC_ROM_LINEAR;
	70	extern const device_type GENERIC_ROMRAM_PLAIN;
55	71
56	72
57
58	73	#endif

trunk/src/emu/bus/generic/slot.h

r32357	r32358
32	32	UINT8* get_ram_base() { return m_ram; }
33	33	UINT32 get_ram_size() { return m_ram.count(); }
34	34
	35	void save_ram()   { device().save_item(NAME(m_ram)); }
	36
35	37	// internal state
36	38	UINT8  *m_rom;
37	39	UINT32  m_rom_size;
r32357	r32358
136	138	UINT8* get_rom_base()  { if (m_cart) return m_cart->get_rom_base(); return NULL; }
137	139	UINT8* get_ram_base() { if (m_cart) return m_cart->get_ram_base(); return NULL; }
138	140	UINT32 get_rom_size() { if (m_cart) return m_cart->get_rom_size(); return 0; }
139
	141
	142	void save_ram()   { if (m_cart && m_cart->get_ram_size()) m_cart->save_ram(); }
	143
140	144	protected:
141	145
142	146	const char *m_interface;

trunk/src/mess/drivers/x07.c

r32357	r32358
1037	1037
1038	1038	DEVICE_IMAGE_LOAD_MEMBER( x07_state, x07_card )
1039	1039	{
1040		address_space &space = m_maincpu->space( AS_PROGRAM );
1041		UINT16 ram_size = m_ram->size();
1042
1043		if (image.software_entry() == NULL)
	1040	UINT32 size = m_card->common_get_size("rom");
	1041
	1042	// check card type
	1043	if (image.software_entry() != NULL)
1044	1044	{
1045		UINT8 *rom = machine().memory().region_alloc( "card", image.length(), 1, ENDIANNESS_LITTLE )->base();
1046		image.fread(rom, image.length());
1047
1048		space.install_ram(ram_size, ram_size + 0xfff);
1049		space.install_rom(0x6000, 0x7fff, rom);
1050		}
1051		else
1052		{
1053	1045	const char *card_type = image.get_feature("card_type");
1054
1055		if (!strcmp(card_type, "xp140"))
	1046
	1047	if (strcmp(card_type, "xp140"))
1056	1048	{
1057		// 0x4000 - 0x4fff   4KB RAM
1058		// 0x6000 - 0x7fff   8KB ROM
1059		space.install_ram(ram_size, ram_size + 0xfff);
1060		space.install_rom(0x6000, 0x7fff, image.get_software_region("rom"));
1061		}
1062		else
1063		{
	1049	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported card type");
1064	1050	return IMAGE_INIT_FAIL;
1065	1051	}
1066	1052	}
1067	1053
	1054	m_card->rom_alloc(size, GENERIC_ROM8_WIDTH, ENDIANNESS_BIG);
	1055	m_card->common_load_rom(m_card->get_rom_base(), size, "rom");
	1056
	1057	m_card->ram_alloc(0x1000);
	1058
1068	1059	return IMAGE_INIT_PASS;
1069	1060	}
1070	1061
r32357	r32358
1368	1359
1369	1360	void x07_state::machine_start()
1370	1361	{
	1362	UINT32 ram_size = m_ram->size();
1371	1363	m_rsta_clear = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(x07_state::rsta_clear),this));
1372	1364	m_rstb_clear = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(x07_state::rstb_clear),this));
1373	1365	m_beep_stop = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(x07_state::beep_stop),this));
r32357	r32358
1375	1367	m_cass_tick = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(x07_state::cassette_tick),this));
1376	1368
1377	1369	m_nvram1->set_base(&m_t6834_ram, 0x800);
1378		m_nvram2->set_base(m_ram->pointer(), m_ram->size());
	1370	m_nvram2->set_base(m_ram->pointer(), ram_size);
1379	1371
1380	1372	/* Save State */
1381	1373	save_item(NAME(m_sleep));
r32357	r32358
1418	1410	save_item(NAME(m_cursor.y));
1419	1411	save_item(NAME(m_cursor.on));
1420	1412
1421		/* install RAM */
	1413	// install RAM
1422	1414	address_space &program = m_maincpu->space(AS_PROGRAM);
1423		program.install_ram(0x0000, m_ram->size() - 1, m_ram->pointer());
	1415	program.install_ram(0x0000, ram_size - 1, m_ram->pointer());
	1416
	1417	// card
	1418	if (m_card->exists())
	1419	{
	1420	// 0x4000 - 0x4fff   4KB RAM
	1421	// 0x6000 - 0x7fff   8KB ROM
	1422	program.install_read_handler(ram_size, ram_size + 0xfff, read8_delegate(FUNC(generic_slot_device::read_ram),(generic_slot_device*)m_card));
	1423	program.install_write_handler(ram_size, ram_size + 0xfff, write8_delegate(FUNC(generic_slot_device::write_ram),(generic_slot_device*)m_card));
	1424	program.install_read_handler(0x6000, 0x7fff, read8_delegate(FUNC(generic_slot_device::read_rom),(generic_slot_device*)m_card));
	1425
	1426	m_card->save_ram();
	1427	}
1424	1428	}
1425	1429
1426	1430	void x07_state::machine_reset()
r32357	r32358
1504	1508	MCFG_RAM_EXTRA_OPTIONS("8K,12K,20K,24k")
1505	1509
1506	1510	/* Memory Card */
1507		MCFG_CARTSLOT_ADD("card")
1508		MCFG_CARTSLOT_EXTENSION_LIST("rom,bin")
1509		MCFG_CARTSLOT_NOT_MANDATORY
1510		MCFG_CARTSLOT_LOAD(x07_state,x07_card)
1511		MCFG_CARTSLOT_INTERFACE("x07_card")
	1511	MCFG_GENERIC_CARTSLOT_ADD("cardslot", generic_romram_plain_slot, "x07_card")
	1512	MCFG_GENERIC_EXTENSIONS("rom,bin")
	1513	MCFG_GENERIC_LOAD(x07_state, x07_card)
1512	1514
1513	1515	/* cassette */
1514	1516	MCFG_CASSETTE_ADD( "cassette" )

trunk/src/mess/drivers/vii.c

r32357	r32358
70	70
71	71	#include "emu.h"
72	72	#include "cpu/unsp/unsp.h"
73		#include "imagedev/cartslot.h"
74	73	#include "machine/i2cmem.h"
75		#include "formats/imageutl.h"
76	74
	75	#include "bus/generic/slot.h"
	76	#include "bus/generic/carts.h"
	77
	78
77	79	#define PAGE_ENABLE_MASK        0x0008
78	80
79	81	#define PAGE_DEPTH_FLAG_MASK    0x3000
r32357	r32358
91	93	vii_state(const machine_config &mconfig, device_type type, const char *tag)
92	94	: driver_device(mconfig, type, tag),
93	95	m_maincpu(*this, "maincpu"),
	96	m_cart(*this, "cartslot"),
94	97	m_p_ram(*this, "p_ram"),
95	98	m_p_rowscroll(*this, "p_rowscroll"),
96	99	m_p_palette(*this, "p_palette"),
97	100	m_p_spriteram(*this, "p_spriteram"),
98		m_p_cart(*this, "p_cart"),
99		m_region_cpu(*this, "maincpu"),
100		m_region_cart(*this, "cart"),
	101	m_bios_rom(*this, "bios"),
101	102	m_io_p1(*this, "P1")
102	103	{ }
103	104
104	105	required_device<cpu_device> m_maincpu;
105		DECLARE_READ16_MEMBER(vii_video_r);
106		DECLARE_WRITE16_MEMBER(vii_video_w);
107		DECLARE_READ16_MEMBER(vii_audio_r);
108		DECLARE_WRITE16_MEMBER(vii_audio_w);
109		DECLARE_READ16_MEMBER(vii_io_r);
110		DECLARE_WRITE16_MEMBER(vii_io_w);
111		DECLARE_WRITE16_MEMBER(vii_rowscroll_w);
112		DECLARE_WRITE16_MEMBER(vii_spriteram_w);
	106	optional_device<generic_slot_device> m_cart;
	107	DECLARE_READ16_MEMBER(video_r);
	108	DECLARE_WRITE16_MEMBER(video_w);
	109	DECLARE_READ16_MEMBER(audio_r);
	110	DECLARE_WRITE16_MEMBER(audio_w);
	111	DECLARE_READ16_MEMBER(io_r);
	112	DECLARE_WRITE16_MEMBER(io_w);
	113	DECLARE_WRITE16_MEMBER(rowscroll_w);
	114	DECLARE_WRITE16_MEMBER(spriteram_w);
	115	DECLARE_READ16_MEMBER(rom_r);
113	116	required_shared_ptr<UINT16> m_p_ram;
114	117	required_shared_ptr<UINT16> m_p_rowscroll;
115	118	required_shared_ptr<UINT16> m_p_palette;
116	119	required_shared_ptr<UINT16> m_p_spriteram;
117		required_shared_ptr<UINT16> m_p_cart;
118	120
	121	dynamic_array<UINT16> m_p_cart;
	122
119	123	UINT32 m_current_bank;
120	124
121	125	UINT16 m_video_regs[0x100];
122	126	UINT32 m_centered_coordinates;
	127	void test_centered(UINT8 *ROM);
123	128
124	129	struct
125	130	{
r32357	r32358
134	139
135	140	emu_timer *m_tmb1;
136	141	emu_timer *m_tmb2;
137		void vii_do_dma(UINT32 len);
138		void vii_do_gpio(UINT32 offset);
139		void vii_switch_bank(UINT32 bank);
140		void vii_do_i2c();
	142	void do_dma(UINT32 len);
	143	void do_gpio(UINT32 offset);
	144	void switch_bank(UINT32 bank);
	145	void do_i2c();
141	146	void spg_do_dma(UINT32 len);
142	147	DECLARE_DRIVER_INIT(vsmile);
143	148	DECLARE_DRIVER_INIT(walle);
r32357	r32358
154	159	DECLARE_DEVICE_IMAGE_LOAD_MEMBER(vsmile_cart);
155	160
156	161	protected:
157		required_memory_region m_region_cpu;
158		optional_memory_region m_region_cart;
	162	optional_memory_region m_bios_rom;
159	163	required_ioport m_io_p1;
160	164
161		void vii_blit(bitmap_rgb32 &bitmap, const rectangle &cliprect, UINT32 xoff, UINT32 yoff, UINT32 attr, UINT32 ctrl, UINT32 bitmap_addr, UINT16 tile);
162		void vii_blit_page(bitmap_rgb32 &bitmap, const rectangle &cliprect, int depth, UINT32 bitmap_addr, UINT16 *regs);
163		void vii_blit_sprite(bitmap_rgb32 &bitmap, const rectangle &cliprect, int depth, UINT32 base_addr);
164		void vii_blit_sprites(bitmap_rgb32 &bitmap, const rectangle &cliprect, int depth);
	165	memory_region *m_cart_rom;
	166
	167	void blit(bitmap_rgb32 &bitmap, const rectangle &cliprect, UINT32 xoff, UINT32 yoff, UINT32 attr, UINT32 ctrl, UINT32 bitmap_addr, UINT16 tile);
	168	void blit_page(bitmap_rgb32 &bitmap, const rectangle &cliprect, int depth, UINT32 bitmap_addr, UINT16 *regs);
	169	void blit_sprite(bitmap_rgb32 &bitmap, const rectangle &cliprect, int depth, UINT32 base_addr);
	170	void blit_sprites(bitmap_rgb32 &bitmap, const rectangle &cliprect, int depth);
165	171	inline void verboselog(int n_level, const char *s_fmt, ...) ATTR_PRINTF(3,4);
166	172	inline UINT8 expand_rgb5_to_rgb8(UINT8 val);
167		inline UINT8 vii_mix_channel(UINT8 a, UINT8 b);
168		void vii_mix_pixel(UINT32 offset, UINT16 rgb);
169		void vii_set_pixel(UINT32 offset, UINT16 rgb);
	173	inline UINT8 mix_channel(UINT8 a, UINT8 b);
	174	void mix_pixel(UINT32 offset, UINT16 rgb);
	175	void set_pixel(UINT32 offset, UINT16 rgb);
170	176	};
171	177
172	178	enum
r32357	r32358
217	223	}
218	224
219	225	// Perform a lerp between a and b
220		inline UINT8 vii_state::vii_mix_channel(UINT8 a, UINT8 b)
	226	inline UINT8 vii_state::mix_channel(UINT8 a, UINT8 b)
221	227	{
222	228	UINT8 alpha = m_video_regs[0x1c] & 0x00ff;
223	229	return ((64 - alpha) * a + alpha * b) / 64;
224	230	}
225	231
226		void vii_state::vii_mix_pixel(UINT32 offset, UINT16 rgb)
	232	void vii_state::mix_pixel(UINT32 offset, UINT16 rgb)
227	233	{
228		m_screenram[offset].r = vii_mix_channel(m_screenram[offset].r, expand_rgb5_to_rgb8(rgb >> 10));
229		m_screenram[offset].g = vii_mix_channel(m_screenram[offset].g, expand_rgb5_to_rgb8(rgb >> 5));
230		m_screenram[offset].b = vii_mix_channel(m_screenram[offset].b, expand_rgb5_to_rgb8(rgb));
	234	m_screenram[offset].r = mix_channel(m_screenram[offset].r, expand_rgb5_to_rgb8(rgb >> 10));
	235	m_screenram[offset].g = mix_channel(m_screenram[offset].g, expand_rgb5_to_rgb8(rgb >> 5));
	236	m_screenram[offset].b = mix_channel(m_screenram[offset].b, expand_rgb5_to_rgb8(rgb));
231	237	}
232	238
233		void vii_state::vii_set_pixel(UINT32 offset, UINT16 rgb)
	239	void vii_state::set_pixel(UINT32 offset, UINT16 rgb)
234	240	{
235	241	m_screenram[offset].r = expand_rgb5_to_rgb8(rgb >> 10);
236	242	m_screenram[offset].g = expand_rgb5_to_rgb8(rgb >> 5);
237	243	m_screenram[offset].b = expand_rgb5_to_rgb8(rgb);
238	244	}
239	245
240		void vii_state::vii_blit(bitmap_rgb32 &bitmap, const rectangle &cliprect, UINT32 xoff, UINT32 yoff, UINT32 attr, UINT32 ctrl, UINT32 bitmap_addr, UINT16 tile)
	246	void vii_state::blit(bitmap_rgb32 &bitmap, const rectangle &cliprect, UINT32 xoff, UINT32 yoff, UINT32 attr, UINT32 ctrl, UINT32 bitmap_addr, UINT16 tile)
241	247	{
242	248	address_space &space = m_maincpu->space(AS_PROGRAM);
243	249
r32357	r32358
293	299	{
294	300	if (attr & 0x4000)
295	301	{
296		vii_mix_pixel(xx + 320*yy, rgb);
	302	mix_pixel(xx + 320*yy, rgb);
297	303	}
298	304	else
299	305	{
300		vii_set_pixel(xx + 320*yy, rgb);
	306	set_pixel(xx + 320*yy, rgb);
301	307	}
302	308	}
303	309	}
r32357	r32358
305	311	}
306	312	}
307	313
308		void vii_state::vii_blit_page(bitmap_rgb32 &bitmap, const rectangle &cliprect, int depth, UINT32 bitmap_addr, UINT16 *regs)
	314	void vii_state::blit_page(bitmap_rgb32 &bitmap, const rectangle &cliprect, int depth, UINT32 bitmap_addr, UINT16 *regs)
309	315	{
310	316	UINT32 x0, y0;
311	317	UINT32 xscroll = regs[0];
r32357	r32358
369	375	yy = ((h*y0 - yscroll + 0x10) & 0xff) - 0x10;
370	376	xx = (w*x0 - xscroll) & 0x1ff;
371	377
372		vii_blit(bitmap, cliprect, xx, yy, tileattr, tilectrl, bitmap_addr, tile);
	378	blit(bitmap, cliprect, xx, yy, tileattr, tilectrl, bitmap_addr, tile);
373	379	}
374	380	}
375	381	}
376	382
377		void vii_state::vii_blit_sprite(bitmap_rgb32 &bitmap, const rectangle &cliprect, int depth, UINT32 base_addr)
	383	void vii_state::blit_sprite(bitmap_rgb32 &bitmap, const rectangle &cliprect, int depth, UINT32 base_addr)
378	384	{
379	385	address_space &space = m_maincpu->space(AS_PROGRAM);
380	386	UINT16 tile, attr;
r32357	r32358
412	418	x &= 0x01ff;
413	419	y &= 0x01ff;
414	420
415		vii_blit(bitmap, cliprect, x, y, attr, 0, bitmap_addr, tile);
	421	blit(bitmap, cliprect, x, y, attr, 0, bitmap_addr, tile);
416	422	}
417	423
418		void vii_state::vii_blit_sprites(bitmap_rgb32 &bitmap, const rectangle &cliprect, int depth)
	424	void vii_state::blit_sprites(bitmap_rgb32 &bitmap, const rectangle &cliprect, int depth)
419	425	{
420	426	UINT32 n;
421	427
r32357	r32358
428	434	{
429	435	//if(space.read_word((0x2c00 + 4*n) << 1))
430	436	{
431		vii_blit_sprite(bitmap, cliprect, depth, 0x2c00 + 4*n);
	437	blit_sprite(bitmap, cliprect, depth, 0x2c00 + 4*n);
432	438	}
433	439	}
434	440	}
r32357	r32358
443	449
444	450	for(i = 0; i < 4; i++)
445	451	{
446		vii_blit_page(bitmap, cliprect, i, 0x40 * m_video_regs[0x20], m_video_regs + 0x10);
447		vii_blit_page(bitmap, cliprect, i, 0x40 * m_video_regs[0x21], m_video_regs + 0x16);
448		vii_blit_sprites(bitmap, cliprect, i);
	452	blit_page(bitmap, cliprect, i, 0x40 * m_video_regs[0x20], m_video_regs + 0x10);
	453	blit_page(bitmap, cliprect, i, 0x40 * m_video_regs[0x21], m_video_regs + 0x16);
	454	blit_sprites(bitmap, cliprect, i);
449	455	}
450	456
451	457	for(y = 0; y < 240; y++)
r32357	r32358
463	469	*    Machine Hardware    *
464	470	*************************/
465	471
466		void vii_state::vii_do_dma(UINT32 len)
	472	void vii_state::do_dma(UINT32 len)
467	473	{
468	474	address_space &mem = m_maincpu->space(AS_PROGRAM);
469	475	UINT32 src = m_video_regs[0x70];
r32357	r32358
479	485	m_video_regs[0x63] |= 4;
480	486	}
481	487
482		READ16_MEMBER( vii_state::vii_video_r )
	488	READ16_MEMBER( vii_state::video_r )
483	489	{
484	490	switch(offset)
485	491	{
486	492	case 0x62: // Video IRQ Enable
487		verboselog(0, "vii_video_r: Video IRQ Enable: %04x\n", VII_VIDEO_IRQ_ENABLE);
	493	verboselog(0, "video_r: Video IRQ Enable: %04x\n", VII_VIDEO_IRQ_ENABLE);
488	494	return VII_VIDEO_IRQ_ENABLE;
489	495
490	496	case 0x63: // Video IRQ Status
491		verboselog(0, "vii_video_r: Video IRQ Status: %04x\n", VII_VIDEO_IRQ_STATUS);
	497	verboselog(0, "video_r: Video IRQ Status: %04x\n", VII_VIDEO_IRQ_STATUS);
492	498	return VII_VIDEO_IRQ_STATUS;
493	499
494	500	default:
495		verboselog(0, "vii_video_r: Unknown register %04x = %04x\n", 0x2800 + offset, m_video_regs[offset]);
	501	verboselog(0, "video_r: Unknown register %04x = %04x\n", 0x2800 + offset, m_video_regs[offset]);
496	502	break;
497	503	}
498	504	return m_video_regs[offset];
499	505	}
500	506
501		WRITE16_MEMBER( vii_state::vii_video_w )
	507	WRITE16_MEMBER( vii_state::video_w )
502	508	{
503	509	switch(offset)
504	510	{
r32357	r32358
517	523	COMBINE_DATA(&m_video_regs[offset]);
518	524	break;
519	525	case 0x62: // Video IRQ Enable
520		verboselog(0, "vii_video_w: Video IRQ Enable = %04x (%04x)\n", data, mem_mask);
	526	verboselog(0, "video_w: Video IRQ Enable = %04x (%04x)\n", data, mem_mask);
521	527	COMBINE_DATA(&VII_VIDEO_IRQ_ENABLE);
522	528	break;
523	529
524	530	case 0x63: // Video IRQ Acknowledge
525		verboselog(0, "vii_video_w: Video IRQ Acknowledge = %04x (%04x)\n", data, mem_mask);
	531	verboselog(0, "video_w: Video IRQ Acknowledge = %04x (%04x)\n", data, mem_mask);
526	532	VII_VIDEO_IRQ_STATUS &= ~data;
527	533	if(!VII_VIDEO_IRQ_STATUS)
528	534	{
r32357	r32358
531	537	break;
532	538
533	539	case 0x70: // Video DMA Source
534		verboselog(0, "vii_video_w: Video DMA Source = %04x (%04x)\n", data, mem_mask);
	540	verboselog(0, "video_w: Video DMA Source = %04x (%04x)\n", data, mem_mask);
535	541	COMBINE_DATA(&m_video_regs[offset]);
536	542	break;
537	543
538	544	case 0x71: // Video DMA Dest
539		verboselog(0, "vii_video_w: Video DMA Dest = %04x (%04x)\n", data, mem_mask);
	545	verboselog(0, "video_w: Video DMA Dest = %04x (%04x)\n", data, mem_mask);
540	546	COMBINE_DATA(&m_video_regs[offset]);
541	547	break;
542	548
543	549	case 0x72: // Video DMA Length
544		verboselog(0, "vii_video_w: Video DMA Length = %04x (%04x)\n", data, mem_mask);
545		vii_do_dma(data);
	550	verboselog(0, "video_w: Video DMA Length = %04x (%04x)\n", data, mem_mask);
	551	do_dma(data);
546	552	break;
547	553
548	554	default:
549		verboselog(0, "vii_video_w: Unknown register %04x = %04x (%04x)\n", 0x2800 + offset, data, mem_mask);
	555	verboselog(0, "video_w: Unknown register %04x = %04x (%04x)\n", 0x2800 + offset, data, mem_mask);
550	556	COMBINE_DATA(&m_video_regs[offset]);
551	557	break;
552	558	}
553	559	}
554	560
555		READ16_MEMBER( vii_state::vii_audio_r )
	561	READ16_MEMBER( vii_state::audio_r )
556	562	{
557	563	switch(offset)
558	564	{
559	565	default:
560		verboselog(4, "vii_audio_r: Unknown register %04x\n", 0x3000 + offset);
	566	verboselog(4, "audio_r: Unknown register %04x\n", 0x3000 + offset);
561	567	break;
562	568	}
563	569	return 0;
564	570	}
565	571
566		WRITE16_MEMBER( vii_state::vii_audio_w )
	572	WRITE16_MEMBER( vii_state::audio_w )
567	573	{
568	574	switch(offset)
569	575	{
570	576	default:
571		verboselog(4, "vii_audio_w: Unknown register %04x = %04x (%04x)\n", 0x3000 + offset, data, mem_mask);
	577	verboselog(4, "audio_w: Unknown register %04x = %04x (%04x)\n", 0x3000 + offset, data, mem_mask);
572	578	break;
573	579	}
574	580	}
575	581
576		void vii_state::vii_switch_bank(UINT32 bank)
	582	void vii_state::switch_bank(UINT32 bank)
577	583	{
578		UINT8 *cart = m_region_cart->base();
579
580		if(bank != m_current_bank)
	584	if (bank != m_current_bank)
581	585	{
582	586	m_current_bank = bank;
583
584		memcpy(m_p_cart, cart + 0x400000 * bank * 2 + 0x4000*2, (0x400000 - 0x4000) * 2);
	587	if (m_cart_rom)
	588	memcpy(m_p_cart, m_cart_rom->base() + 0x400000 * bank * 2, 0x400000 * 2);
	589	else
	590	memcpy(m_p_cart, m_bios_rom->base() + 0x400000 * bank * 2, 0x400000 * 2);
585	591	}
586	592	}
587	593
588		void vii_state::vii_do_gpio(UINT32 offset)
	594	void vii_state::do_gpio(UINT32 offset)
589	595	{
590	596	UINT32 index  = (offset - 1) / 5;
591	597	UINT16 buffer = m_io_regs[5*index + 2];
r32357	r32358
604	610	if(index == 1)
605	611	{
606	612	UINT32 bank = ((what & 0x80) >> 7) | ((what & 0x20) >> 4);
607		vii_switch_bank(bank);
	613	switch_bank(bank);
608	614	}
609	615	}
610	616	else if (m_spg243_mode == SPG243_BATMAN)
r32357	r32358
626	632	{
627	633	}
628	634	}
	635	else if (m_spg243_mode == SPG243_VSMILE)
	636	{
	637	// TODO: find out how vsmile accesses these GPIO regs!
	638	}
629	639
630	640	m_io_regs[5*index + 1] = what;
631	641	}
632	642
633		void vii_state::vii_do_i2c()
	643	void vii_state::do_i2c()
634	644	{
635	645	}
636	646
r32357	r32358
648	658	m_io_regs[0x102] = 0;
649	659	}
650	660
651		READ16_MEMBER( vii_state::vii_io_r )
	661	READ16_MEMBER( vii_state::io_r )
652	662	{
653	663	static const char *const gpioregs[] = { "GPIO Data Port", "GPIO Buffer Port", "GPIO Direction Port", "GPIO Attribute Port", "GPIO IRQ/Latch Port" };
654	664	static const char gpioports[] = { 'A', 'B', 'C' };
r32357	r32358
660	670	switch(offset)
661	671	{
662	672	case 0x01: case 0x06: case 0x0b: // GPIO Data Port A/B/C
663		vii_do_gpio(offset);
664		verboselog(3, "vii_io_r: %s %c = %04x (%04x)\n", gpioregs[(offset - 1) % 5], gpioports[(offset - 1) / 5], m_io_regs[offset], mem_mask);
	673	do_gpio(offset);
	674	verboselog(3, "io_r: %s %c = %04x (%04x)\n", gpioregs[(offset - 1) % 5], gpioports[(offset - 1) / 5], m_io_regs[offset], mem_mask);
665	675	val = m_io_regs[offset];
666	676	break;
667	677
668	678	case 0x02: case 0x03: case 0x04: case 0x05:
669	679	case 0x07: case 0x08: case 0x09: case 0x0a:
670	680	case 0x0c: case 0x0d: case 0x0e: case 0x0f: // Other GPIO regs
671		verboselog(3, "vii_io_r: %s %c = %04x (%04x)\n", gpioregs[(offset - 1) % 5], gpioports[(offset - 1) / 5], m_io_regs[offset], mem_mask);
	681	verboselog(3, "io_r: %s %c = %04x (%04x)\n", gpioregs[(offset - 1) % 5], gpioports[(offset - 1) / 5], m_io_regs[offset], mem_mask);
672	682	break;
673	683
674	684	case 0x1c: // Random
675	685	val = machine().rand() & 0x00ff;
676		verboselog(3, "vii_io_r: Random = %04x (%04x)\n", val, mem_mask);
	686	verboselog(3, "io_r: Random = %04x (%04x)\n", val, mem_mask);
677	687	break;
678	688
679	689	case 0x21: // IRQ Control
680		verboselog(3, "vii_io_r: Controller IRQ Control = %04x (%04x)\n", val, mem_mask);
	690	verboselog(3, "io_r: Controller IRQ Control = %04x (%04x)\n", val, mem_mask);
681	691	break;
682	692
683	693	case 0x22: // IRQ Status
684		verboselog(3, "vii_io_r: Controller IRQ Status = %04x (%04x)\n", val, mem_mask);
	694	verboselog(3, "io_r: Controller IRQ Status = %04x (%04x)\n", val, mem_mask);
685	695	break;
686	696
687	697	case 0x2c: case 0x2d: // Timers?
688	698	val = machine().rand() & 0x0000ffff;
689		verboselog(3, "vii_io_r: Unknown Timer %d Register = %04x (%04x)\n", offset - 0x2c, val, mem_mask);
	699	verboselog(3, "io_r: Unknown Timer %d Register = %04x (%04x)\n", offset - 0x2c, val, mem_mask);
690	700	break;
691	701
692	702	case 0x2f: // Data Segment
693	703	val = m_maincpu->state_int(UNSP_SR) >> 10;
694		verboselog(3, "vii_io_r: Data Segment = %04x (%04x)\n", val, mem_mask);
	704	verboselog(3, "io_r: Data Segment = %04x (%04x)\n", val, mem_mask);
695	705	break;
696	706
697	707	case 0x31: // Unknown, UART Status?
698		verboselog(3, "vii_io_r: Unknown (UART Status?) = %04x (%04x)\n", 3, mem_mask);
	708	verboselog(3, "io_r: Unknown (UART Status?) = %04x (%04x)\n", 3, mem_mask);
699	709	val = 3;
700	710	break;
701	711
702	712	case 0x36: // UART RX Data
703	713	val = m_controller_input[m_uart_rx_count];
704	714	m_uart_rx_count = (m_uart_rx_count + 1) % 8;
705		verboselog(3, "vii_io_r: UART RX Data = %04x (%04x)\n", val, mem_mask);
	715	verboselog(3, "io_r: UART RX Data = %04x (%04x)\n", val, mem_mask);
706	716	break;
707	717
708	718	case 0x59: // I2C Status
709		verboselog(3, "vii_io_r: I2C Status = %04x (%04x)\n", val, mem_mask);
	719	verboselog(3, "io_r: I2C Status = %04x (%04x)\n", val, mem_mask);
710	720	break;
711	721
712	722	case 0x5e: // I2C Data In
713		verboselog(3, "vii_io_r: I2C Data In = %04x (%04x)\n", val, mem_mask);
	723	verboselog(3, "io_r: I2C Data In = %04x (%04x)\n", val, mem_mask);
714	724	break;
715	725
716	726	default:
717		verboselog(3, "vii_io_r: Unknown register %04x\n", 0x3d00 + offset);
	727	verboselog(3, "io_r: Unknown register %04x\n", 0x3d00 + offset);
718	728	break;
719	729	}
720	730
721	731	return val;
722	732	}
723	733
724		WRITE16_MEMBER( vii_state::vii_io_w )
	734	WRITE16_MEMBER( vii_state::io_w )
725	735	{
726	736	static const char *const gpioregs[] = { "GPIO Data Port", "GPIO Buffer Port", "GPIO Direction Port", "GPIO Attribute Port", "GPIO IRQ/Latch Port" };
727	737	static const char gpioports[3] = { 'A', 'B', 'C' };
r32357	r32358
733	743	switch(offset)
734	744	{
735	745	case 0x00: // GPIO special function select
736		verboselog(3, "vii_io_w: GPIO Function Select = %04x (%04x)\n", data, mem_mask);
	746	verboselog(3, "io_w: GPIO Function Select = %04x (%04x)\n", data, mem_mask);
737	747	COMBINE_DATA(&m_io_regs[offset]);
738	748	break;
739	749
r32357	r32358
744	754	case 0x02: case 0x03: case 0x04: case 0x05: // Port A
745	755	case 0x07: case 0x08: case 0x09: case 0x0a: // Port B
746	756	case 0x0c: case 0x0d: case 0x0e: case 0x0f: // Port C
747		verboselog(3, "vii_io_w: %s %c = %04x (%04x)\n", gpioregs[(offset - 1) % 5], gpioports[(offset - 1) / 5], data, mem_mask);
	757	verboselog(3, "io_w: %s %c = %04x (%04x)\n", gpioregs[(offset - 1) % 5], gpioports[(offset - 1) / 5], data, mem_mask);
748	758	COMBINE_DATA(&m_io_regs[offset]);
749		vii_do_gpio(offset);
	759	do_gpio(offset);
750	760	break;
751	761
752	762	case 0x10:      // timebase control
r32357	r32358
763	773	COMBINE_DATA(&m_io_regs[offset]);
764	774	break;
765	775	case 0x21: // IRQ Enable
766		verboselog(3, "vii_io_w: Controller IRQ Control = %04x (%04x)\n", data, mem_mask);
	776	verboselog(3, "io_w: Controller IRQ Control = %04x (%04x)\n", data, mem_mask);
767	777	COMBINE_DATA(&VII_CTLR_IRQ_ENABLE);
768	778	if(!VII_CTLR_IRQ_ENABLE)
769	779	{
r32357	r32358
772	782	break;
773	783
774	784	case 0x22: // IRQ Acknowledge
775		verboselog(3, "vii_io_w: Controller IRQ Acknowledge = %04x (%04x)\n", data, mem_mask);
	785	verboselog(3, "io_w: Controller IRQ Acknowledge = %04x (%04x)\n", data, mem_mask);
776	786	m_io_regs[0x22] &= ~data;
777	787	if(!m_io_regs[0x22])
778	788	{
r32357	r32358
783	793	case 0x2f: // Data Segment
784	794	temp = m_maincpu->state_int(UNSP_SR);
785	795	m_maincpu->set_state_int(UNSP_SR, (temp & 0x03ff) | ((data & 0x3f) << 10));
786		verboselog(3, "vii_io_w: Data Segment = %04x (%04x)\n", data, mem_mask);
	796	verboselog(3, "io_w: Data Segment = %04x (%04x)\n", data, mem_mask);
787	797	break;
788	798
789	799	case 0x31: // Unknown UART
790		verboselog(3, "vii_io_w: Unknown UART = %04x (%04x)\n", data, mem_mask);
	800	verboselog(3, "io_w: Unknown UART = %04x (%04x)\n", data, mem_mask);
791	801	COMBINE_DATA(&m_io_regs[offset]);
792	802	break;
793	803
794	804	case 0x32: // UART Reset
795		verboselog(3, "vii_io_r: UART Reset\n");
	805	verboselog(3, "io_w: UART Reset\n");
796	806	break;
797	807
798	808	case 0x33: // UART Baud Rate
799		verboselog(3, "vii_io_w: UART Baud Rate = %u\n", 27000000 / 16 / (0x10000 - (m_io_regs[0x34] << 8) - data));
	809	verboselog(3, "io_w: UART Baud Rate = %u\n", 27000000 / 16 / (0x10000 - (m_io_regs[0x34] << 8) - data));
800	810	COMBINE_DATA(&m_io_regs[offset]);
801	811	break;
802	812
803	813	case 0x35: // UART TX Data
804		verboselog(3, "vii_io_w: UART Baud Rate = %u\n", 27000000 / 16 / (0x10000 - (data << 8) - m_io_regs[0x33]));
	814	verboselog(3, "io_w: UART Baud Rate = %u\n", 27000000 / 16 / (0x10000 - (data << 8) - m_io_regs[0x33]));
805	815	COMBINE_DATA(&m_io_regs[offset]);
806	816	break;
807	817
808	818	case 0x5a: // I2C Access Mode
809		verboselog(3, "vii_io_w: I2C Access Mode = %04x (%04x)\n", data, mem_mask);
	819	verboselog(3, "io_w: I2C Access Mode = %04x (%04x)\n", data, mem_mask);
810	820	COMBINE_DATA(&m_io_regs[offset]);
811	821	break;
812	822
813	823	case 0x5b: // I2C Device Address
814		verboselog(3, "vii_io_w: I2C Device Address = %04x (%04x)\n", data, mem_mask);
	824	verboselog(3, "io_w: I2C Device Address = %04x (%04x)\n", data, mem_mask);
815	825	COMBINE_DATA(&m_io_regs[offset]);
816	826	break;
817	827
818	828	case 0x5c: // I2C Sub-Address
819		verboselog(3, "vii_io_w: I2C Sub-Address = %04x (%04x)\n", data, mem_mask);
	829	verboselog(3, "io_w: I2C Sub-Address = %04x (%04x)\n", data, mem_mask);
820	830	COMBINE_DATA(&m_io_regs[offset]);
821	831	break;
822	832
823	833	case 0x5d: // I2C Data Out
824		verboselog(3, "vii_io_w: I2C Data Out = %04x (%04x)\n", data, mem_mask);
	834	verboselog(3, "io_w: I2C Data Out = %04x (%04x)\n", data, mem_mask);
825	835	COMBINE_DATA(&m_io_regs[offset]);
826	836	break;
827	837
828	838	case 0x5e: // I2C Data In
829		verboselog(3, "vii_io_w: I2C Data In = %04x (%04x)\n", data, mem_mask);
	839	verboselog(3, "io_w: I2C Data In = %04x (%04x)\n", data, mem_mask);
830	840	COMBINE_DATA(&m_io_regs[offset]);
831	841	break;
832	842
833	843	case 0x5f: // I2C Controller Mode
834		verboselog(3, "vii_io_w: I2C Controller Mode = %04x (%04x)\n", data, mem_mask);
	844	verboselog(3, "io_w: I2C Controller Mode = %04x (%04x)\n", data, mem_mask);
835	845	COMBINE_DATA(&m_io_regs[offset]);
836	846	break;
837	847
838	848	case 0x58: // I2C Command
839		verboselog(3, "vii_io_w: I2C Command = %04x (%04x)\n", data, mem_mask);
	849	verboselog(3, "io_w: I2C Command = %04x (%04x)\n", data, mem_mask);
840	850	COMBINE_DATA(&m_io_regs[offset]);
841		vii_do_i2c();
	851	do_i2c();
842	852	break;
843	853
844	854	case 0x59: // I2C Status / IRQ Acknowledge(?)
845		verboselog(3, "vii_io_w: I2C Status / Ack = %04x (%04x)\n", data, mem_mask);
	855	verboselog(3, "io_w: I2C Status / Ack = %04x (%04x)\n", data, mem_mask);
846	856	m_io_regs[offset] &= ~data;
847	857	break;
848	858
r32357	r32358
857	867	break;
858	868
859	869	default:
860		verboselog(3, "vii_io_w: Unknown register %04x = %04x (%04x)\n", 0x3d00 + offset, data, mem_mask);
	870	verboselog(3, "io_w: Unknown register %04x = %04x (%04x)\n", 0x3d00 + offset, data, mem_mask);
861	871	COMBINE_DATA(&m_io_regs[offset]);
862	872	break;
863	873	}
864	874	}
865	875
866	876	/*
867		WRITE16_MEMBER( vii_state::vii_rowscroll_w )
	877	WRITE16_MEMBER( vii_state::rowscroll_w )
868	878	{
869	879	switch(offset)
870	880	{
871	881	default:
872		verboselog(0, "vii_rowscroll_w: %04x = %04x (%04x)\n", 0x2900 + offset, data, mem_mask);
	882	verboselog(0, "rowscroll_w: %04x = %04x (%04x)\n", 0x2900 + offset, data, mem_mask);
873	883	break;
874	884	}
875	885	}
876	886
877		WRITE16_MEMBER( vii_state::vii_spriteram_w )
	887	WRITE16_MEMBER( vii_state::spriteram_w )
878	888	{
879	889	switch(offset)
880	890	{
881	891	default:
882		verboselog(0, "vii_spriteram_w: %04x = %04x (%04x)\n", 0x2c00 + offset, data, mem_mask);
	892	verboselog(0, "spriteram_w: %04x = %04x (%04x)\n", 0x2c00 + offset, data, mem_mask);
883	893	break;
884	894	}
885	895	}
886	896	*/
887	897
	898	READ16_MEMBER( vii_state::rom_r )
	899	{
	900	return m_p_cart[offset + 0x4000];
	901	}
	902
888	903	static ADDRESS_MAP_START( vii_mem, AS_PROGRAM, 16, vii_state )
889	904	AM_RANGE( 0x000000, 0x004fff ) AM_RAM AM_SHARE("p_ram")
890		AM_RANGE( 0x005000, 0x0051ff ) AM_READWRITE(vii_video_r, vii_video_w)
	905	AM_RANGE( 0x005000, 0x0051ff ) AM_READWRITE(video_r, video_w)
891	906	AM_RANGE( 0x005200, 0x0055ff ) AM_RAM AM_SHARE("p_rowscroll")
892	907	AM_RANGE( 0x005600, 0x0057ff ) AM_RAM AM_SHARE("p_palette")
893	908	AM_RANGE( 0x005800, 0x005fff ) AM_RAM AM_SHARE("p_spriteram")
894		AM_RANGE( 0x006000, 0x006fff ) AM_READWRITE(vii_audio_r, vii_audio_w)
895		AM_RANGE( 0x007000, 0x007fff ) AM_READWRITE(vii_io_r,    vii_io_w)
896		AM_RANGE( 0x008000, 0x7fffff ) AM_ROM AM_SHARE("p_cart")
	909	AM_RANGE( 0x006000, 0x006fff ) AM_READWRITE(audio_r, audio_w)
	910	AM_RANGE( 0x007000, 0x007fff ) AM_READWRITE(io_r,    io_w)
	911	AM_RANGE( 0x008000, 0x7fffff ) AM_READ(rom_r)
897	912	ADDRESS_MAP_END
898	913
899	914	static INPUT_PORTS_START( vii )
r32357	r32358
943	958	INPUT_PORTS_END
944	959
945	960
946		DEVICE_IMAGE_LOAD_MEMBER( vii_state, vii_cart )
	961	void vii_state::test_centered(UINT8 *ROM)
947	962	{
948		UINT8 *cart = m_region_cart->base();
949		if (image.software_entry() == NULL)
	963	if (ROM[0x3cd808] == 0x99 &&
	964	ROM[0x3cd809] == 0x99 &&
	965	ROM[0x3cd80a] == 0x83 &&
	966	ROM[0x3cd80b] == 0x5e &&
	967	ROM[0x3cd80c] == 0x52 &&
	968	ROM[0x3cd80d] == 0x6b &&
	969	ROM[0x3cd80e] == 0x78 &&
	970	ROM[0x3cd80f] == 0x7f)
950	971	{
951		int size = image.length();
952
953		if( image.fread(cart, size ) != size )
954		{
955		image.seterror( IMAGE_ERROR_UNSPECIFIED, "Unable to fully read from file" );
956		return IMAGE_INIT_FAIL;
957		}
958		} else {
959		int filesize = image.get_software_region_length("rom");
960		memcpy(cart, image.get_software_region("rom"), filesize);
	972	m_centered_coordinates = 0;
961	973	}
	974	}
962	975
963		memcpy(m_p_cart, cart + 0x4000*2, (0x400000 - 0x4000) * 2);
	976	DEVICE_IMAGE_LOAD_MEMBER( vii_state, vii_cart )
	977	{
	978	UINT32 size = m_cart->common_get_size("rom");
964	979
965		if( cart[0x3cd808] == 0x99 &&
966		cart[0x3cd809] == 0x99 &&
967		cart[0x3cd80a] == 0x83 &&
968		cart[0x3cd80b] == 0x5e &&
969		cart[0x3cd80c] == 0x52 &&
970		cart[0x3cd80d] == 0x6b &&
971		cart[0x3cd80e] == 0x78 &&
972		cart[0x3cd80f] == 0x7f )
	980	if (size < 0x800000)
973	981	{
974		m_centered_coordinates = 0;
	982	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
	983	return IMAGE_INIT_FAIL;
975	984	}
	985
	986	m_cart->rom_alloc(size, GENERIC_ROM16_WIDTH, ENDIANNESS_LITTLE);
	987	m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
	988
	989	test_centered(m_cart->get_rom_base());
	990
976	991	return IMAGE_INIT_PASS;
977	992	}
978	993
979	994	DEVICE_IMAGE_LOAD_MEMBER( vii_state, vsmile_cart )
980	995	{
981		UINT8 *CART = m_region_cart->base();
982		UINT16 *ROM = (UINT16 *) m_region_cpu->base();
983		if (image.software_entry() == NULL)
984		{
985		int size = image.length();
986		image.fread(CART, size);
987		}
988		else
989		{
990		int size = image.get_software_region_length("rom");
991		memcpy(CART, image.get_software_region("rom"), size);
992		}
993
994		// for whatever reason if we copy more than this, the CPU
995		// is not happy and VSmile won't show anything... bankswitch?
996		for (int i = 0; i < 0x800000; i += 2)
997		ROM[i / 2] = pick_integer_le(CART, i, 2);
998
	996	UINT32 size = m_cart->common_get_size("rom");
	997
	998	m_cart->rom_alloc(size, GENERIC_ROM16_WIDTH, ENDIANNESS_LITTLE);
	999	m_cart->common_load_rom(m_cart->get_rom_base(), size, "rom");
	1000
999	1001	return IMAGE_INIT_PASS;
1000	1002	}
1001	1003
r32357	r32358
1021	1023	m_controller_input[6] = 0xff;
1022	1024	m_controller_input[7] = 0;
1023	1025
1024		if ( m_region_cart && m_spg243_mode == SPG243_VII)
	1026	m_p_cart.resize(0x400000);
	1027
	1028	if (m_cart && m_cart->exists())
1025	1029	{
1026		UINT8 *rom = m_region_cart->base();
1027		memcpy(m_p_cart, rom + 0x4000*2, (0x400000 - 0x4000) * 2);
	1030	astring region_tag;
	1031	m_cart_rom = memregion(region_tag.cpy(m_cart->tag()).cat(GENERIC_ROM_REGION_TAG));
	1032	memcpy(m_p_cart, m_cart_rom->base(), 0x400000 * 2);
1028	1033	}
1029
	1034	else if (m_spg243_mode == SPG243_VII)   // Vii bios is banked
	1035	memcpy(m_p_cart, m_bios_rom->base(), 0x400000 * 2);
	1036	else
	1037	memcpy(m_p_cart, memregion("maincpu")->base(), 0x400000 * 2);
	1038
1030	1039	m_video_regs[0x36] = 0xffff;
1031	1040	m_video_regs[0x37] = 0xffff;
1032	1041
r32357	r32358
1122	1131	MCFG_SCREEN_UPDATE_DRIVER(vii_state, screen_update_vii)
1123	1132	MCFG_PALETTE_ADD("palette", 32768)
1124	1133
1125		MCFG_CARTSLOT_ADD( "cart" )
1126		MCFG_CARTSLOT_EXTENSION_LIST( "bin" )
1127		MCFG_CARTSLOT_LOAD( vii_state, vii_cart )
1128		MCFG_CARTSLOT_INTERFACE("vii_cart")
	1134	MCFG_GENERIC_CARTSLOT_ADD("cartslot", generic_plain_slot, "vii_cart")
	1135	MCFG_GENERIC_WIDTH(GENERIC_ROM16_WIDTH)
	1136	MCFG_GENERIC_LOAD(vii_state, vii_cart)
1129	1137
1130	1138	MCFG_SOFTWARE_LIST_ADD("vii_cart","vii")
1131	1139	MACHINE_CONFIG_END
r32357	r32358
1144	1152	MCFG_SCREEN_UPDATE_DRIVER(vii_state, screen_update_vii)
1145	1153	MCFG_PALETTE_ADD("palette", 32768)
1146	1154
1147		MCFG_CARTSLOT_ADD( "cart" )
1148		MCFG_CARTSLOT_EXTENSION_LIST( "bin" )
1149		MCFG_CARTSLOT_LOAD( vii_state, vsmile_cart )
1150		MCFG_CARTSLOT_INTERFACE("vsmile_cart")
	1155	MCFG_GENERIC_CARTSLOT_ADD("cartslot", generic_plain_slot, "vsmile_cart")
	1156	MCFG_GENERIC_WIDTH(GENERIC_ROM16_WIDTH)
	1157	MCFG_GENERIC_LOAD(vii_state, vsmile_cart)
1151	1158
1152	1159	MCFG_SOFTWARE_LIST_ADD("cart_list","vsmile_cart")
1153	1160	MACHINE_CONFIG_END
r32357	r32358
1184	1191
1185	1192	DRIVER_INIT_MEMBER(vii_state,vsmile)
1186	1193	{
1187		m_spg243_mode = SPG243_BATMAN;//SPG243_VSMILE;
	1194	m_spg243_mode = SPG243_VSMILE;
1188	1195	m_centered_coordinates = 1;
1189	1196	}
1190	1197
r32357	r32358
1197	1204	ROM_START( vii )
1198	1205	ROM_REGION( 0x800000, "maincpu", ROMREGION_ERASEFF )      /* dummy region for u'nSP */
1199	1206
1200		ROM_REGION( 0x2000000, "cart", ROMREGION_ERASE00 )
	1207	ROM_REGION( 0x2000000, "bios", 0 )
1201	1208	ROM_LOAD( "vii.bin", 0x0000, 0x2000000, CRC(04627639) SHA1(f883a92d31b53c9a5b0cdb112d07cd793c95fc43))
1202		ROM_CART_LOAD("cart", 0x0000, 0x2000000, ROM_MIRROR)
1203	1209	ROM_END
1204	1210
1205	1211	ROM_START( batmantv )
r32357	r32358
1210	1216	ROM_START( vsmile )
1211	1217	ROM_REGION( 0x800000, "maincpu", ROMREGION_ERASEFF )      /* dummy region for u'nSP */
1212	1218	ROM_LOAD16_WORD_SWAP( "bios german.bin", 0x000000, 0x200000, CRC(205c5296) SHA1(7fbcf761b5885c8b1524607aabaf364b4559c8cc) )
1213
1214		ROM_REGION( 0x2000000, "cart", ROMREGION_ERASE00 )
1215	1219	ROM_END
1216	1220
1217	1221	ROM_START( walle )

trunk/src/mess/includes/x07.h

r32357	r32358
12	12	#include "machine/nvram.h"
13	13	#include "machine/ram.h"
14	14	#include "sound/wave.h"
15		#include "imagedev/cartslot.h"
16	15	#include "imagedev/cassette.h"
17	16	#include "imagedev/printer.h"
18	17	#include "formats/x07_cas.h"
	18	#include "bus/generic/slot.h"
	19	#include "bus/generic/carts.h"
19	20	#include "rendlay.h"
20	21
21	22	//default value for user defined keys, taken for official documentation
r32357	r32358
168	169	m_nvram1(*this, "nvram1"),
169	170	m_nvram2(*this, "nvram2"),
170	171	m_cassette(*this, "cassette"),
	172	m_card(*this, "cardslot"),
171	173	m_warm_start(1)
172	174	{ }
173	175
r32357	r32358
178	180	required_device<nvram_device> m_nvram1;
179	181	required_device<nvram_device> m_nvram2;
180	182	required_device<cassette_image_device> m_cassette;
	183	required_device<generic_slot_device> m_card;
181	184
182	185	void machine_start();
183	186	void machine_reset();

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