MAME SVN History

199869 Revisions

r32353 Wednesday 24th September, 2014 at 14:46:27 UTC by Osso
tms340x0_device: converted to use inline config, devcb and delegates. (nw)

[src/emu/cpu/tms34010]	34010gfx.c tms34010.c tms34010.h
[src/mame/drivers]	artmagic.c btoads.c coolpool.c exterm.c harddriv.c jpmimpct.c lethalj.c metalmx.c micro3d.c midtunit.c midwunit.c midxunit.c midyunit.c midzeus.c potgoldu.c skeetsht.c skimaxx.c tickee.c xtheball.c
[src/mame/includes]	artmagic.h btoads.h coolpool.h exterm.h harddriv.h jpmimpct.h lethalj.h metalmx.h micro3d.h midtunit.h midxunit.h midyunit.h
[src/mame/machine]	harddriv.c inder_vid.c inder_vid.h midtunit.c
[src/mame/video]	artmagic.c btoads.c exterm.c harddriv.c jpmimpct.c lethalj.c micro3d.c midtunit.c midyunit.c

trunk/src/mame/drivers/micro3d.c
r32352	r32353
282	282
283	283	/*************************************
284	284	*
285		* Device Configuration
286		*
287		*************************************/
288
289		static const tms340x0_config vgb_config =
290		{
291		FALSE, /* halt on reset */
292		"screen", /* the screen operated on */
293		XTAL_40MHz / 8, /* pixel clock */
294		4, /* pixels per clock */
295		micro3d_scanline_update, /* scanline updater (indexed16) */
296		NULL, /* scanline updater (rgb32) */
297		micro3d_tms_interrupt, /* Generate interrupt */
298		NULL,
299		NULL
300		};
301
302		/*************************************
303		*
304	285	* Machine driver
305	286	*
306	287	*************************************/
r32352	r32353
312	293	MCFG_CPU_VBLANK_INT_DRIVER("screen", micro3d_state, micro3d_vblank)
313	294
314	295	MCFG_CPU_ADD("vgb", TMS34010, XTAL_40MHz)
315		MCFG_TMS340X0_CONFIG(vgb_config)
316	296	MCFG_CPU_PROGRAM_MAP(vgbmem)
	297	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
	298	MCFG_TMS340X0_PIXEL_CLOCK(XTAL_40MHz / 8) /* pixel clock */
	299	MCFG_TMS340X0_PIXELS_PER_CLOCK(4) /* pixels per clock */
	300	MCFG_TMS340X0_SCANLINE_IND16_CB(micro3d_state, scanline_update) /* scanline updater (indexed16) */
	301	MCFG_TMS340X0_OUTPUT_INT_CB(WRITELINE(micro3d_state, tms_interrupt))
317	302
318	303	MCFG_CPU_ADD("drmath", AM29000, XTAL_32MHz / 2)
319	304	MCFG_CPU_PROGRAM_MAP(drmath_prg)

trunk/src/mame/drivers/jpmimpct.c
r32352	r32353
819	819	*
820	820	*************************************/
821	821
822		~~static void~~ jpmimpct_tms_irq~~(device_t *device, int state~~)
	822	WRITE_LINE_MEMBER(jpmimpct_state::tms_irq)
823	823	{
824		jpmimpct_state *drvstate = device->machine().driver_data<jpmimpct_state>();
825		drvstate->m_tms_irq = state;
826		drvstate->update_irqs();
	824	m_tms_irq = state;
	825	update_irqs();
827	826	}
828	827
829		static const tms340x0_config tms_config =
830		{
831		TRUE, /* halt on reset */
832		"screen", /* the screen operated on */
833		40000000/16, /* pixel clock */
834		4, /* pixels per clock */
835		NULL, /* scanline updater (indexed16) */
836		jpmimpct_scanline_update, /* scanline updater (rgb32) */
837		jpmimpct_tms_irq, /* generate interrupt */
838		jpmimpct_to_shiftreg, /* write to shiftreg function */
839		jpmimpct_from_shiftreg /* read from shiftreg function */
840		};
841	828
842
843	829	/*************************************
844	830	*
845	831	* Machine driver
r32352	r32353
851	837	MCFG_CPU_PROGRAM_MAP(m68k_program_map)
852	838
853	839	MCFG_CPU_ADD("dsp", TMS34010, 40000000)
854		MCFG_TMS340X0_CONFIG(tms_config)
855	840	MCFG_CPU_PROGRAM_MAP(tms_program_map)
	841	MCFG_TMS340X0_HALT_ON_RESET(TRUE) /* halt on reset */
	842	MCFG_TMS340X0_PIXEL_CLOCK(40000000/16) /* pixel clock */
	843	MCFG_TMS340X0_PIXELS_PER_CLOCK(4) /* pixels per clock */
	844	MCFG_TMS340X0_SCANLINE_RGB32_CB(jpmimpct_state, scanline_update) /* scanline updater (rgb32) */
	845	MCFG_TMS340X0_OUTPUT_INT_CB(WRITELINE(jpmimpct_state, tms_irq))
	846	MCFG_TMS340X0_TO_SHIFTREG_CB(jpmimpct_state, to_shiftreg) /* write to shiftreg function */
	847	MCFG_TMS340X0_FROM_SHIFTREG_CB(jpmimpct_state, from_shiftreg) /* read from shiftreg function */
856	848
857	849	MCFG_QUANTUM_TIME(attotime::from_hz(30000))
858	850	MCFG_MACHINE_START_OVERRIDE(jpmimpct_state,jpmimpct)

trunk/src/mame/drivers/btoads.c
r32352	r32353
292	292	INPUT_PORTS_END
293	293
294	294
295
296	295	/*************************************
297	296	*
298		* 34010 configuration
299		*
300		*************************************/
301
302		static const tms340x0_config tms_config =
303		{
304		FALSE, /* halt on reset */
305		"screen", /* the screen operated on */
306		VIDEO_CLOCK/2, /* pixel clock */
307		1, /* pixels per clock */
308		NULL, /* scanline callback (indexed16) */
309		btoads_state::static_scanline_update, /* scanline callback (rgb32) */
310		NULL, /* generate interrupt */
311		btoads_state::static_to_shiftreg, /* write to shiftreg function */
312		btoads_state::static_from_shiftreg /* read from shiftreg function */
313		};
314
315
316
317		/*************************************
318		*
319	297	* Machine drivers
320	298	*
321	299	*************************************/
r32352	r32353
323	301	static MACHINE_CONFIG_START( btoads, btoads_state )
324	302
325	303	MCFG_CPU_ADD("maincpu", TMS34020, CPU_CLOCK/2)
326		MCFG_TMS340X0_CONFIG(tms_config)
327	304	MCFG_CPU_PROGRAM_MAP(main_map)
	305	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
	306	MCFG_TMS340X0_PIXEL_CLOCK(VIDEO_CLOCK/2) /* pixel clock */
	307	MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
	308	MCFG_TMS340X0_SCANLINE_RGB32_CB(btoads_state, scanline_update) /* scanline updater (RGB32) */
	309	MCFG_TMS340X0_TO_SHIFTREG_CB(btoads_state, to_shiftreg) /* write to shiftreg function */
	310	MCFG_TMS340X0_FROM_SHIFTREG_CB(btoads_state, from_shiftreg) /* read from shiftreg function */
328	311
329	312	MCFG_CPU_ADD("audiocpu", Z80, SOUND_CLOCK/4)
330	313	MCFG_CPU_PROGRAM_MAP(sound_map)

trunk/src/mame/drivers/midwunit.c
r32352	r32353
611	611
612	612	/*************************************
613	613	*
614		* 34010 configuration
615		*
616		*************************************/
617
618		static const tms340x0_config tms_config =
619		{
620		FALSE, /* halt on reset */
621		"screen", /* the screen operated on */
622		PIXEL_CLOCK, /* pixel clock */
623		1, /* pixels per clock */
624		midtunit_scanline_update, /* scanline updater (indexed16) */
625		NULL, /* scanline updater (rgb32) */
626		NULL, /* generate interrupt */
627		midtunit_to_shiftreg, /* write to shiftreg function */
628		midtunit_from_shiftreg /* read from shiftreg function */
629		};
630
631
632
633		/*************************************
634		*
635	614	* Machine drivers
636	615	*
637	616	*************************************/
r32352	r32353
639	618	static MACHINE_CONFIG_START( wunit, midwunit_state )
640	619
641	620	MCFG_CPU_ADD("maincpu", TMS34010, 50000000)
642		MCFG_TMS340X0_CONFIG(tms_config)
643	621	MCFG_CPU_PROGRAM_MAP(main_map)
	622	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
	623	MCFG_TMS340X0_PIXEL_CLOCK(PIXEL_CLOCK) /* pixel clock */
	624	MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
	625	MCFG_TMS340X0_SCANLINE_IND16_CB(midtunit_state, scanline_update) /* scanline updater (indexed16) */
	626	MCFG_TMS340X0_TO_SHIFTREG_CB(midtunit_state, to_shiftreg) /* write to shiftreg function */
	627	MCFG_TMS340X0_FROM_SHIFTREG_CB(midtunit_state, from_shiftreg) /* read from shiftreg function */
644	628
645	629	MCFG_MACHINE_RESET_OVERRIDE(midwunit_state,midwunit)
646	630	MCFG_NVRAM_ADD_0FILL("nvram")

trunk/src/mame/drivers/lethalj.c
r32352	r32353
625	625
626	626	/*************************************
627	627	*
628		* 34010 configuration
629		*
630		*************************************/
631
632		static const tms340x0_config tms_config =
633		{
634		FALSE, /* halt on reset */
635		"screen", /* the screen operated on */
636		VIDEO_CLOCK, /* pixel clock */
637		1, /* pixels per clock */
638		lethalj_scanline_update, /* scanline update */
639		NULL, /* generate interrupt */
640		NULL, /* write to shiftreg function */
641		NULL /* read from shiftreg function */
642		};
643
644		static const tms340x0_config tms_config_lethalj =
645		{
646		FALSE, /* halt on reset */
647		"screen", /* the screen operated on */
648		VIDEO_CLOCK_LETHALJ, /* pixel clock */
649		1, /* pixels per clock */
650		lethalj_scanline_update, /* scanline update */
651		NULL, /* generate interrupt */
652		NULL, /* write to shiftreg function */
653		NULL /* read from shiftreg function */
654		};
655
656
657
658		/*************************************
659		*
660	628	* Machine drivers
661	629	*
662	630	*************************************/
r32352	r32353
665	633
666	634	/* basic machine hardware */
667	635	MCFG_CPU_ADD("maincpu", TMS34010, MASTER_CLOCK)
668		MCFG_TMS340X0_CONFIG(tms_config)
669	636	MCFG_CPU_PROGRAM_MAP(lethalj_map)
	637	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
	638	MCFG_TMS340X0_PIXEL_CLOCK(VIDEO_CLOCK) /* pixel clock */
	639	MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
	640	MCFG_TMS340X0_SCANLINE_IND16_CB(lethalj_state, scanline_update) /* scanline updater (indexed16) */
670	641
671	642	MCFG_TICKET_DISPENSER_ADD("ticket", attotime::from_msec(200), TICKET_MOTOR_ACTIVE_HIGH, TICKET_STATUS_ACTIVE_HIGH)
672	643
r32352	r32353
695	666	static MACHINE_CONFIG_DERIVED( lethalj, gameroom )
696	667
697	668	MCFG_CPU_MODIFY("maincpu")
698		MCFG_TMS340X0_CO~~NFIG~~(~~tms~~_~~config~~_le~~tha~~lj)
	669	MCFG_TMS340X0_PIXEL_CLOCK(VIDEO_CLOCK_LETHALJ) /* pixel clock */
699	670
700	671	MCFG_SCREEN_MODIFY("screen")
701	672	MCFG_SCREEN_RAW_PARAMS(VIDEO_CLOCK_LETHALJ, 689, 0, 512, 259, 0, 236)

trunk/src/mame/drivers/tickee.c
r32352	r32353
42	42
43	43	tickee_state(const machine_config &mconfig, device_type type, const char *tag)
44	44	: driver_device(mconfig, type, tag),
45		m_tlc34076(*this, "tlc34076"),
46		m_vram(*this, "vram"),
47		m_control(*this, "control"),
48	45	m_maincpu(*this, "maincpu"),
49	46	m_oki(*this, "oki"),
50		m_screen(*this, "screen") { }
	47	m_screen(*this, "screen"),
	48	m_tlc34076(*this, "tlc34076"),
	49	m_vram(*this, "vram"),
	50	m_control(*this, "control") { }
51	51
	52	required_device<cpu_device> m_maincpu;
	53	optional_device<okim6295_device> m_oki;
	54	required_device<screen_device> m_screen;
52	55	required_device<tlc34076_device> m_tlc34076;
	56
53	57	required_shared_ptr<UINT16> m_vram;
54	58	optional_shared_ptr<UINT16> m_control;
	59
55	60	emu_timer *m_setup_gun_timer;
56	61	int m_beamxadd;
57	62	int m_beamyadd;
58	63	int m_palette_bank;
59	64	UINT8 m_gunx[2];
60	65	void get_crosshair_xy(int player, int &x, int &y);
	66
61	67	DECLARE_WRITE16_MEMBER(rapidfir_transparent_w);
62	68	DECLARE_READ16_MEMBER(rapidfir_transparent_r);
63	69	DECLARE_WRITE16_MEMBER(tickee_control_w);
r32352	r32353
74	80	TIMER_CALLBACK_MEMBER(trigger_gun_interrupt);
75	81	TIMER_CALLBACK_MEMBER(clear_gun_interrupt);
76	82	TIMER_CALLBACK_MEMBER(setup_gun_interrupts);
77		required_device<cpu_device> m_maincpu;
78		optional_device<okim6295_device> m_oki;
79		required_device<screen_device> m_screen;
	83
	84	TMS340X0_TO_SHIFTREG_CB_MEMBER(rapidfir_to_shiftreg);
	85	TMS340X0_FROM_SHIFTREG_CB_MEMBER(rapidfir_from_shiftreg);
	86	TMS340X0_SCANLINE_RGB32_CB_MEMBER(scanline_update);
	87	TMS340X0_SCANLINE_RGB32_CB_MEMBER(rapidfir_scanline_update);
80	88
81	89	protected:
82	90	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
r32352	r32353
195	203	*
196	204	*************************************/
197	205
198		static ~~void scanlin~~e~~_updat~~e~~(screen~~_~~device &~~s~~creen, bi~~tma~~p_rgb32 &bi~~t~~map, int~~ scanline~~, const tms34010~~_~~dis~~pla~~y_params *params~~)
	206	TMS340X0_SCANLINE_RGB32_CB_MEMBER(tickee_state::scanline_update)
199	207	{
200		tickee_state *state = screen.machine().driver_data<tickee_state>();
201		UINT16 *src = &state->m_vram[(params->rowaddr << 8) & 0x3ff00];
	208	UINT16 *src = &m_vram[(params->rowaddr << 8) & 0x3ff00];
202	209	UINT32 *dest = &bitmap.pix32(scanline);
203		const rgb_t *pens = ~~state->~~m_tlc34076->get_pens();
	210	const rgb_t *pens = m_tlc34076->get_pens();
204	211	int coladdr = params->coladdr << 1;
205	212	int x;
206	213
207	214	/* blank palette: fill with pen 255 */
208		if (~~state->~~m_control[2])
	215	if (m_control[2])
209	216	{
210	217	for (x = params->heblnk; x < params->hsblnk; x++)
211	218	dest[x] = pens[0xff];
r32352	r32353
221	228	}
222	229
223	230
224		stat~~ic void~~ rapidfir_scanline_update~~(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params~~)
	231	TMS340X0_SCANLINE_RGB32_CB_MEMBER(tickee_state::rapidfir_scanline_update)
225	232	{
226		tickee_state *state = screen.machine().driver_data<tickee_state>();
227		UINT16 *src = &state->m_vram[(params->rowaddr << 8) & 0x3ff00];
	233	UINT16 *src = &m_vram[(params->rowaddr << 8) & 0x3ff00];
228	234	UINT32 *dest = &bitmap.pix32(scanline);
229		const rgb_t *pens = ~~state->~~m_tlc34076->get_pens();
	235	const rgb_t *pens = m_tlc34076->get_pens();
230	236	int coladdr = params->coladdr << 1;
231	237	int x;
232	238
233		if (~~state->~~m_palette_bank)
	239	if (m_palette_bank)
234	240	{
235	241	/* blank palette: fill with pen 255 */
236	242	for (x = params->heblnk; x < params->hsblnk; x += 2)
r32352	r32353
291	297	}
292	298
293	299
294		stat~~ic void~~ rapidfir_to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
	300	TMS340X0_TO_SHIFTREG_CB_MEMBER(tickee_state::rapidfir_to_shiftreg)
295	301	{
296		tickee_state *state = space.machine().driver_data<tickee_state>();
297	302	if (address < 0x800000)
298		memcpy(shiftreg, &~~state->~~m_vram[TOWORD(address)], TOBYTE(0x2000));
	303	memcpy(shiftreg, &m_vram[TOWORD(address)], TOBYTE(0x2000));
299	304	}
300	305
301	306
302		stat~~ic void~~ rapidfir_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
	307	TMS340X0_FROM_SHIFTREG_CB_MEMBER(tickee_state::rapidfir_from_shiftreg)
303	308	{
304		tickee_state *state = space.machine().driver_data<tickee_state>();
305	309	if (address < 0x800000)
306		memcpy(&~~state->~~m_vram[TOWORD(address)], shiftreg, TOBYTE(0x2000));
	310	memcpy(&m_vram[TOWORD(address)], shiftreg, TOBYTE(0x2000));
307	311	}
308	312
309	313
r32352	r32353
731	735
732	736	/*************************************
733	737	*
734		* 34010 configuration
735		*
736		*************************************/
737
738		static const tms340x0_config tms_config =
739		{
740		FALSE, /* halt on reset */
741		"screen", /* the screen operated on */
742		VIDEO_CLOCK/2, /* pixel clock */
743		1, /* pixels per clock */
744		NULL, /* scanline callback (indexed16) */
745		scanline_update, /* scanline callback (rgb32) */
746		NULL, /* generate interrupt */
747		NULL, /* write to shiftreg function */
748		NULL /* read from shiftreg function */
749		};
750
751
752		static const tms340x0_config rapidfir_tms_config =
753		{
754		FALSE, /* halt on reset */
755		"screen", /* the screen operated on */
756		VIDEO_CLOCK/2, /* pixel clock */
757		1, /* pixels per clock */
758		NULL, /* scanline callback (indexed16) */
759		rapidfir_scanline_update, /* scanline callback (rgb32) */
760		NULL, /* generate interrupt */
761		rapidfir_to_shiftreg, /* write to shiftreg function */
762		rapidfir_from_shiftreg /* read from shiftreg function */
763		};
764
765
766
767		/*************************************
768		*
769	738	* Machine drivers
770	739	*
771	740	*************************************/
r32352	r32353
774	743
775	744	/* basic machine hardware */
776	745	MCFG_CPU_ADD("maincpu", TMS34010, XTAL_40MHz)
777		MCFG_TMS340X0_CONFIG(tms_config)
778	746	MCFG_CPU_PROGRAM_MAP(tickee_map)
	747	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
	748	MCFG_TMS340X0_PIXEL_CLOCK(VIDEO_CLOCK/2) /* pixel clock */
	749	MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
	750	MCFG_TMS340X0_SCANLINE_RGB32_CB(tickee_state, scanline_update) /* scanline callback (rgb32) */
779	751
780	752	MCFG_MACHINE_RESET_OVERRIDE(tickee_state,tickee)
781	753	MCFG_NVRAM_ADD_1FILL("nvram")
r32352	r32353
819	791
820	792	/* basic machine hardware */
821	793	MCFG_CPU_ADD("maincpu", TMS34010, XTAL_50MHz)
822		MCFG_TMS340X0_CONFIG(rapidfir_tms_config)
823		MCFG_CPU_PROGRAM_MAP(rapidfir_map)
	794	MCFG_CPU_PROGRAM_MAP(rapidfir_map)
	795	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
	796	MCFG_TMS340X0_PIXEL_CLOCK(VIDEO_CLOCK/2) /* pixel clock */
	797	MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
	798	MCFG_TMS340X0_SCANLINE_RGB32_CB(tickee_state, rapidfir_scanline_update) /* scanline callback (rgb32) */
	799	MCFG_TMS340X0_TO_SHIFTREG_CB(tickee_state, rapidfir_to_shiftreg) /* write to shiftreg function */
	800	MCFG_TMS340X0_FROM_SHIFTREG_CB(tickee_state, rapidfir_from_shiftreg) /* read from shiftreg function */
824	801
825	802	MCFG_MACHINE_RESET_OVERRIDE(tickee_state,rapidfir)
826	803	MCFG_NVRAM_ADD_1FILL("nvram")
r32352	r32353
846	823
847	824	/* basic machine hardware */
848	825	MCFG_CPU_ADD("maincpu", TMS34010, XTAL_40MHz)
849		MCFG_TMS340X0_CONFIG(tms_config)
850	826	MCFG_CPU_PROGRAM_MAP(mouseatk_map)
	827	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
	828	MCFG_TMS340X0_PIXEL_CLOCK(VIDEO_CLOCK/2) /* pixel clock */
	829	MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
	830	MCFG_TMS340X0_SCANLINE_RGB32_CB(tickee_state, scanline_update) /* scanline callback (rgb32) */
851	831
852	832	MCFG_MACHINE_RESET_OVERRIDE(tickee_state,tickee)
853	833	MCFG_NVRAM_ADD_1FILL("nvram")

trunk/src/mame/drivers/midyunit.c
r32352	r32353
1062	1062
1063	1063	/*************************************
1064	1064	*
1065		* 34010 configuration
1066		*
1067		*************************************/
1068
1069		static const tms340x0_config zunit_tms_config =
1070		{
1071		FALSE, /* halt on reset */
1072		"screen", /* the screen operated on */
1073		MEDRES_PIXEL_CLOCK, /* pixel clock */
1074		2, /* pixels per clock */
1075		midyunit_scanline_update, /* scanline updater (indexed16) */
1076		NULL, /* scanline updater (rgb32) */
1077		NULL, /* generate interrupt */
1078		midyunit_to_shiftreg, /* write to shiftreg function */
1079		midyunit_from_shiftreg /* read from shiftreg function */
1080		};
1081
1082		static const tms340x0_config yunit_tms_config =
1083		{
1084		FALSE, /* halt on reset */
1085		"screen", /* the screen operated on */
1086		STDRES_PIXEL_CLOCK, /* pixel clock */
1087		2, /* pixels per clock */
1088		midyunit_scanline_update, /* scanline updater (indexed16) */
1089		NULL, /* scanline updater (rgb32) */
1090		NULL, /* generate interrupt */
1091		midyunit_to_shiftreg, /* write to shiftreg function */
1092		midyunit_from_shiftreg /* read from shiftreg function */
1093		};
1094
1095
1096
1097		/*************************************
1098		*
1099	1065	* Z-unit machine driver
1100	1066	*
1101	1067	*************************************/
r32352	r32353
1104	1070
1105	1071	/* basic machine hardware */
1106	1072	MCFG_CPU_ADD("maincpu", TMS34010, FAST_MASTER_CLOCK)
1107		MCFG_TMS340X0_CONFIG(zunit_tms_config)
1108	1073	MCFG_CPU_PROGRAM_MAP(main_map)
	1074	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
	1075	MCFG_TMS340X0_PIXEL_CLOCK(MEDRES_PIXEL_CLOCK) /* pixel clock */
	1076	MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
	1077	MCFG_TMS340X0_SCANLINE_IND16_CB(midyunit_state, scanline_update) /* scanline updater (indexed16) */
	1078	MCFG_TMS340X0_TO_SHIFTREG_CB(midyunit_state, to_shiftreg) /* write to shiftreg function */
	1079	MCFG_TMS340X0_FROM_SHIFTREG_CB(midyunit_state, from_shiftreg) /* read from shiftreg function */
1109	1080
1110	1081	MCFG_MACHINE_RESET_OVERRIDE(midyunit_state,midyunit)
1111	1082	MCFG_NVRAM_ADD_0FILL("nvram")
r32352	r32353
1141	1112
1142	1113	/* basic machine hardware */
1143	1114	MCFG_CPU_ADD("maincpu", TMS34010, SLOW_MASTER_CLOCK)
1144		MCFG_TMS340X0_CONFIG(yunit_tms_config)
1145	1115	MCFG_CPU_PROGRAM_MAP(main_map)
	1116	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
	1117	MCFG_TMS340X0_PIXEL_CLOCK(STDRES_PIXEL_CLOCK) /* pixel clock */
	1118	MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
	1119	MCFG_TMS340X0_SCANLINE_IND16_CB(midyunit_state, scanline_update) /* scanline updater (indexed16) */
	1120	MCFG_TMS340X0_TO_SHIFTREG_CB(midyunit_state, to_shiftreg) /* write to shiftreg function */
	1121	MCFG_TMS340X0_FROM_SHIFTREG_CB(midyunit_state, from_shiftreg) /* read from shiftreg function */
1146	1122
1147	1123	MCFG_MACHINE_RESET_OVERRIDE(midyunit_state,midyunit)
1148	1124	MCFG_NVRAM_ADD_0FILL("nvram")

trunk/src/mame/drivers/artmagic.c
r32352	r32353
44	44	*
45	45	*************************************/
46	46
47		~~static~~ void update_irq_state(~~running_machine &machine~~)
	47	void artmagic_state::update_irq_state()
48	48	{
49		artmagic_state *state = machine.driver_data<artmagic_state>();
50		state->m_maincpu->set_input_line(4, state->m_tms_irq ? ASSERT_LINE : CLEAR_LINE);
51		state->m_maincpu->set_input_line(5, state->m_hack_irq ? ASSERT_LINE : CLEAR_LINE);
	49	m_maincpu->set_input_line(4, m_tms_irq ? ASSERT_LINE : CLEAR_LINE);
	50	m_maincpu->set_input_line(5, m_hack_irq ? ASSERT_LINE : CLEAR_LINE);
52	51	}
53	52
54	53
55		static ~~void~~ m68k_gen_int~~(device_t *device, int state~~)
	54	WRITE_LINE_MEMBER(artmagic_state::m68k_gen_int)
56	55	{
57		artmagic_state *drvstate = device->machine().driver_data<artmagic_state>();
58		drvstate->m_tms_irq = state;
59		update_irq_state(device->machine());
	56	m_tms_irq = state;
	57	update_irq_state();
60	58	}
61	59
62	60
r32352	r32353
83	81	void artmagic_state::machine_reset()
84	82	{
85	83	m_tms_irq = m_hack_irq = 0;
86		update_irq_state(~~machine()~~);
	84	update_irq_state();
87	85	}
88	86
89	87
r32352	r32353
121	119	{
122	120	case TIMER_IRQ_OFF:
123	121	m_hack_irq = 0;
124		update_irq_state(~~machine()~~);
	122	update_irq_state();
125	123	break;
126	124	default:
127	125	assert_always(FALSE, "Unknown id in artmagic_state::device_timer");
r32352	r32353
136	134	if (pc == 0x18c2 \|\| pc == 0x18e4)
137	135	{
138	136	m_hack_irq = 1;
139		update_irq_state(~~machine()~~);
	137	update_irq_state();
140	138	timer_set(attotime::from_usec(1), TIMER_IRQ_OFF);
141	139	}
142	140	return ioport("300000")->read();
r32352	r32353
475	473	*
476	474	*************************************/
477	475
478		static const tms340x0_config tms_config =
479		{
480		TRUE, /* halt on reset */
481		"screen", /* the screen operated on */
482		MASTER_CLOCK_40MHz/6, /* pixel clock */
483		1, /* pixels per clock */
484		NULL, /* scanline update (indexed16) */
485		artmagic_scanline, /* scanline update (rgb32) */
486		m68k_gen_int, /* generate interrupt */
487		artmagic_to_shiftreg, /* write to shiftreg function */
488		artmagic_from_shiftreg /* read from shiftreg function */
489		};
490
491
492	476	static ADDRESS_MAP_START( tms_map, AS_PROGRAM, 16, artmagic_state )
493	477	AM_RANGE(0x00000000, 0x001fffff) AM_RAM AM_SHARE("vram0")
494	478	AM_RANGE(0x00400000, 0x005fffff) AM_RAM AM_SHARE("vram1")
r32352	r32353
827	811	MCFG_CPU_PROGRAM_MAP(main_map)
828	812
829	813	MCFG_CPU_ADD("tms", TMS34010, MASTER_CLOCK_40MHz)
830		MCFG_TMS340X0_CONFIG(tms_config)
831	814	MCFG_CPU_PROGRAM_MAP(tms_map)
	815	MCFG_TMS340X0_HALT_ON_RESET(TRUE) /* halt on reset */
	816	MCFG_TMS340X0_PIXEL_CLOCK(MASTER_CLOCK_40MHz/6) /* pixel clock */
	817	MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
	818	MCFG_TMS340X0_SCANLINE_RGB32_CB(artmagic_state, scanline) /* scanline update (rgb32) */
	819	MCFG_TMS340X0_OUTPUT_INT_CB(WRITELINE(artmagic_state, m68k_gen_int))
	820	MCFG_TMS340X0_TO_SHIFTREG_CB(artmagic_state, to_shiftreg) /* write to shiftreg function */
	821	MCFG_TMS340X0_FROM_SHIFTREG_CB(artmagic_state, from_shiftreg) /* read from shiftreg function */
832	822
833	823	MCFG_QUANTUM_TIME(attotime::from_hz(6000))
834	824	MCFG_NVRAM_ADD_1FILL("nvram")

trunk/src/mame/drivers/coolpool.c
r32352	r32353
57	57	*
58	58	*************************************/
59	59
60		stat~~ic void~~ amerdart_scanline~~(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params~~)
	60	TMS340X0_SCANLINE_RGB32_CB_MEMBER(coolpool_state::amerdart_scanline)
61	61	{
62		coolpool_state *state = screen.machine().driver_data<coolpool_state>();
63
64		UINT16 *vram = &state->m_vram_base[(params->rowaddr << 8) & 0xff00];
	62	UINT16 *vram = &m_vram_base[(params->rowaddr << 8) & 0xff00];
65	63	UINT32 *dest = &bitmap.pix32(scanline);
66	64	rgb_t pens[16];
67	65	int coladdr = params->coladdr;
r32352	r32353
71	69	if (scanline < 256)
72	70	for (x = 0; x < 16; x++)
73	71	{
74		UINT16 pal = ~~state->~~m_vram_base[x];
	72	UINT16 pal = m_vram_base[x];
75	73	pens[x] = rgb_t(pal4bit(pal >> 4), pal4bit(pal >> 8), pal4bit(pal >> 12));
76	74	}
77	75
r32352	r32353
86	84	}
87	85
88	86
89		~~stati~~c vo~~id c~~oolpool_sca~~nlin~~e(sc~~reen_device &screen, bitma~~p_~~rgb32 &bitmap, int~~ scanline~~, const tms34010_display_params *params~~)
	87	TMS340X0_SCANLINE_RGB32_CB_MEMBER(coolpool_state::coolpool_scanline)
90	88	{
91		coolpool_state *state = screen.machine().driver_data<coolpool_state>();
92
93		UINT16 *vram = &state->m_vram_base[(params->rowaddr << 8) & 0x1ff00];
	89	UINT16 *vram = &m_vram_base[(params->rowaddr << 8) & 0x1ff00];
94	90	UINT32 *dest = &bitmap.pix32(scanline);
95		const rgb_t *pens = ~~state->~~m_tlc34076->get_pens();
	91	const rgb_t *pens = m_tlc34076->get_pens();
96	92	int coladdr = params->coladdr;
97	93	int x;
98	94
r32352	r32353
112	108	*
113	109	*************************************/
114	110
115		~~stati~~c vo~~id c~~oolpool_~~to_~~s~~hif~~t~~reg(~~a~~ddr~~ess_space &space, UINT32 address, UINT16 *shiftreg)
	111	TMS340X0_TO_SHIFTREG_CB_MEMBER(coolpool_state::to_shiftreg)
116	112	{
117		coolpool_state *state = space.machine().driver_data<coolpool_state>();
118
119		memcpy(shiftreg, &state->m_vram_base[TOWORD(address) & ~TOWORD(0xfff)], TOBYTE(0x1000));
	113	memcpy(shiftreg, &m_vram_base[TOWORD(address) & ~TOWORD(0xfff)], TOBYTE(0x1000));
120	114	}
121	115
122	116
123		~~stati~~c vo~~id c~~oolpool_~~from_~~s~~hif~~t~~reg(~~a~~ddr~~e~~ss_space &space, UINT32 add~~ress, UINT16 *shiftreg)
	117	TMS340X0_FROM_SHIFTREG_CB_MEMBER(coolpool_state::from_shiftreg)
124	118	{
125		coolpool_state *state = space.machine().driver_data<coolpool_state>();
126
127		memcpy(&state->m_vram_base[TOWORD(address) & ~TOWORD(0xfff)], shiftreg, TOBYTE(0x1000));
	119	memcpy(&m_vram_base[TOWORD(address) & ~TOWORD(0xfff)], shiftreg, TOBYTE(0x1000));
128	120	}
129	121
130	122
r32352	r32353
790	782	INPUT_PORTS_END
791	783
792	784
793
794	785	/*************************************
795	786	*
796		* 34010 configuration
797		*
798		*************************************/
799
800		static const tms340x0_config tms_config_amerdart =
801		{
802		FALSE, /* halt on reset */
803		"screen", /* the screen operated on */
804		XTAL_40MHz/12, /* pixel clock */
805		2, /* pixels per clock */
806		NULL, /* scanline callback (indexed16) */
807		amerdart_scanline, /* scanline callback (rgb32) */
808		NULL, /* generate interrupt */
809		coolpool_to_shiftreg, /* write to shiftreg function */
810		coolpool_from_shiftreg /* read from shiftreg function */
811		};
812
813
814		static const tms340x0_config tms_config_coolpool =
815		{
816		FALSE, /* halt on reset */
817		"screen", /* the screen operated on */
818		XTAL_40MHz/6, /* pixel clock */
819		1, /* pixels per clock */
820		NULL, /* scanline callback (indexed16) */
821		coolpool_scanline, /* scanline callback (rgb32) */
822		NULL, /* generate interrupt */
823		coolpool_to_shiftreg, /* write to shiftreg function */
824		coolpool_from_shiftreg /* read from shiftreg function */
825		};
826
827
828
829		/*************************************
830		*
831	787	* Machine drivers
832	788	*
833	789	*************************************/
r32352	r32353
836	792
837	793	/* basic machine hardware */
838	794	MCFG_CPU_ADD("maincpu", TMS34010, XTAL_40MHz)
839		MCFG_TMS340X0_CONFIG(tms_config_amerdart)
840	795	MCFG_CPU_PROGRAM_MAP(amerdart_map)
	796	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
	797	MCFG_TMS340X0_PIXEL_CLOCK(XTAL_40MHz/12) /* pixel clock */
	798	MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
	799	MCFG_TMS340X0_SCANLINE_RGB32_CB(coolpool_state, amerdart_scanline) /* scanline callback (rgb32) */
	800	MCFG_TMS340X0_TO_SHIFTREG_CB(coolpool_state, to_shiftreg) /* write to shiftreg function */
	801	MCFG_TMS340X0_FROM_SHIFTREG_CB(coolpool_state, from_shiftreg) /* read from shiftreg function */
841	802
842	803	MCFG_CPU_ADD("dsp", TMS32015, XTAL_40MHz/2)
843	804	MCFG_CPU_PROGRAM_MAP(amerdart_dsp_pgm_map)
r32352	r32353
867	828
868	829	/* basic machine hardware */
869	830	MCFG_CPU_ADD("maincpu", TMS34010, XTAL_40MHz)
870		MCFG_TMS340X0_CONFIG(tms_config_coolpool)
871	831	MCFG_CPU_PROGRAM_MAP(coolpool_map)
872
	832	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
	833	MCFG_TMS340X0_PIXEL_CLOCK(XTAL_40MHz/6) /* pixel clock */
	834	MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
	835	MCFG_TMS340X0_SCANLINE_RGB32_CB(coolpool_state, coolpool_scanline) /* scanline callback (rgb32) */
	836	MCFG_TMS340X0_TO_SHIFTREG_CB(coolpool_state, to_shiftreg) /* write to shiftreg function */
	837	MCFG_TMS340X0_FROM_SHIFTREG_CB(coolpool_state, from_shiftreg) /* read from shiftreg function */
	838
873	839	MCFG_CPU_ADD("dsp", TMS32026,XTAL_40MHz)
874	840	MCFG_CPU_PROGRAM_MAP(coolpool_dsp_pgm_map)
875	841	MCFG_CPU_IO_MAP(coolpool_dsp_io_map)

trunk/src/mame/drivers/midtunit.c
r32352	r32353
573	573	INPUT_PORTS_END
574	574
575	575
576		/*************************************
577		*
578		* 34010 configuration
579		*
580		*************************************/
581	576
582		static const tms340x0_config tms_config =
583		{
584		FALSE, /* halt on reset */
585		"screen", /* the screen operated on */
586		PIXEL_CLOCK, /* pixel clock */
587		2, /* pixels per clock */
588		midtunit_scanline_update, /* scanline updater (indexed16) */
589		NULL, /* scanline updater (rgb32) */
590		NULL, /* generate interrupt */
591		midtunit_to_shiftreg, /* write to shiftreg function */
592		midtunit_from_shiftreg /* read from shiftreg function */
593		};
594
595
596
597	577	/*************************************
598	578	*
599	579	* Machine drivers
r32352	r32353
604	584
605	585	/* basic machine hardware */
606	586	MCFG_CPU_ADD("maincpu", TMS34010, CPU_CLOCK)
607		MCFG_TMS340X0_CONFIG(tms_config)
608	587	MCFG_CPU_PROGRAM_MAP(main_map)
	588	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
	589	MCFG_TMS340X0_PIXEL_CLOCK(PIXEL_CLOCK) /* pixel clock */
	590	MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
	591	MCFG_TMS340X0_SCANLINE_IND16_CB(midtunit_state, scanline_update) /* scanline updater (indexed16) */
	592	MCFG_TMS340X0_TO_SHIFTREG_CB(midtunit_state, to_shiftreg) /* write to shiftreg function */
	593	MCFG_TMS340X0_FROM_SHIFTREG_CB(midtunit_state, from_shiftreg) /* read from shiftreg function */
609	594
610	595	MCFG_MACHINE_RESET_OVERRIDE(midtunit_state,midtunit)
611	596	MCFG_NVRAM_ADD_0FILL("nvram")

trunk/src/mame/drivers/exterm.c
r32352	r32353
393	393	INPUT_PORTS_END
394	394
395	395
396
397	396	/*************************************
398	397	*
399		* 34010 configurations
400		*
401		*************************************/
402
403		static const tms340x0_config master_config =
404		{
405		FALSE, /* halt on reset */
406		"screen", /* the screen operated on */
407		40000000/8, /* pixel clock */
408		1, /* pixels per clock */
409		exterm_scanline_update, /* scanline updater (indexed16) */
410		NULL, /* scanline updater (rgb32) */
411		NULL, /* generate interrupt */
412		exterm_to_shiftreg_master, /* write to shiftreg function */
413		exterm_from_shiftreg_master /* read from shiftreg function */
414		};
415
416		static const tms340x0_config slave_config =
417		{
418		TRUE, /* halt on reset */
419		"screen", /* the screen operated on */
420		40000000/8, /* pixel clock */
421		1, /* pixels per clock */
422		NULL, /* scanline updater (indexed16) */
423		NULL, /* scanline updater (rgb32) */
424		NULL, /* generate interrupt */
425		exterm_to_shiftreg_slave, /* write to shiftreg function */
426		exterm_from_shiftreg_slave /* read from shiftreg function */
427		};
428
429
430
431		/*************************************
432		*
433	398	* Machine drivers
434	399	*
435	400	*************************************/
r32352	r32353
438	403
439	404	/* basic machine hardware */
440	405	MCFG_CPU_ADD("maincpu", TMS34010, 40000000)
441		MCFG_TMS340X0_CONFIG(master_config)
442	406	MCFG_CPU_PROGRAM_MAP(master_map)
	407	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
	408	MCFG_TMS340X0_PIXEL_CLOCK(40000000/8) /* pixel clock */
	409	MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
	410	MCFG_TMS340X0_SCANLINE_IND16_CB(exterm_state, scanline_update) /* scanline updater (indexed16) */
	411	MCFG_TMS340X0_TO_SHIFTREG_CB(exterm_state, to_shiftreg_master) /* write to shiftreg function */
	412	MCFG_TMS340X0_FROM_SHIFTREG_CB(exterm_state, from_shiftreg_master) /* read from shiftreg function */
443	413
444	414	MCFG_CPU_ADD("slave", TMS34010, 40000000)
445		MCFG_TMS340X0_CONFIG(slave_config)
446	415	MCFG_CPU_PROGRAM_MAP(slave_map)
	416	MCFG_TMS340X0_HALT_ON_RESET(TRUE) /* halt on reset */
	417	MCFG_TMS340X0_PIXEL_CLOCK(40000000/8) /* pixel clock */
	418	MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
	419	MCFG_TMS340X0_TO_SHIFTREG_CB(exterm_state, to_shiftreg_slave) /* write to shiftreg function */
	420	MCFG_TMS340X0_FROM_SHIFTREG_CB(exterm_state, from_shiftreg_slave) /* read from shiftreg function */
447	421
448	422	MCFG_CPU_ADD("audiocpu", M6502, 2000000)
449	423	MCFG_CPU_PROGRAM_MAP(sound_master_map)

trunk/src/mame/drivers/metalmx.c
r32352	r32353
480	480	COMBINE_DATA(m_gsp_vram + offset * 2);
481	481	}
482	482
483		stat~~ic void~~ tms_interrupt~~(device_t *device, int state~~)
	483	WRITE_LINE_MEMBER(metalmx_state::tms_interrupt)
484	484	{
485		metalmx_state *drvstate = device->machine().driver_data<metalmx_state>();
486		drvstate->m_maincpu->set_input_line(4, state ? HOLD_LINE : CLEAR_LINE);
	485	m_maincpu->set_input_line(4, state ? HOLD_LINE : CLEAR_LINE);
487	486	}
488	487
489	488
r32352	r32353
684	683
685	684	/*************************************
686	685	*
687		* CPU configuration
688		*
689		*************************************/
690
691		static const tms340x0_config gsp_config =
692		{
693		TRUE, /* halt on reset */
694		"screen", /* the screen operated on */
695		4000000, /* pixel clock */
696		2, /* pixels per clock */
697		NULL, /* scanline callback (indexed16) */
698		NULL, /* scanline callback (rgb32) */
699		tms_interrupt, /* generate interrupt */
700		};
701
702		/*************************************
703		*
704	686	* Machine driver
705	687	*
706	688	*************************************/
r32352	r32353
715	697	MCFG_CPU_DATA_MAP(adsp_data_map)
716	698
717	699	MCFG_CPU_ADD("gsp", TMS34020, 40000000) /* Unverified */
718		MCFG_TMS340X0_CONFIG(gsp_config)
719	700	MCFG_CPU_PROGRAM_MAP(gsp_map)
	701	MCFG_TMS340X0_HALT_ON_RESET(TRUE) /* halt on reset */
	702	MCFG_TMS340X0_PIXEL_CLOCK(4000000) /* pixel clock */
	703	MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
	704	MCFG_TMS340X0_OUTPUT_INT_CB(WRITELINE(metalmx_state, tms_interrupt))
720	705
721	706	MCFG_CPU_ADD("dsp32c_1", DSP32C, 40000000) /* Unverified */
722	707	MCFG_CPU_PROGRAM_MAP(dsp32c_1_map)

trunk/src/mame/drivers/skimaxx.c
r32352	r32353
45	45	public:
46	46	skimaxx_state(const machine_config &mconfig, device_type type, const char *tag)
47	47	: driver_device(mconfig, type, tag),
48		m_blitter_regs(*this, "blitter_regs"),
49		m_fpga_ctrl(*this, "fpga_ctrl"),
50		m_fg_buffer(*this, "fg_buffer"),
51	48	m_maincpu(*this, "maincpu"),
52	49	m_subcpu(*this, "subcpu"),
53		m_tms(*this, "tms") { }
	50	m_tms(*this, "tms"),
	51	m_blitter_regs(*this, "blitter_regs"),
	52	m_fpga_ctrl(*this, "fpga_ctrl"),
	53	m_fg_buffer(*this, "fg_buffer") { }
54	54
	55	required_device<cpu_device> m_maincpu;
	56	required_device<cpu_device> m_subcpu;
	57	required_device<tms34010_device> m_tms;
	58
55	59	required_shared_ptr<UINT32> m_blitter_regs;
56	60	required_shared_ptr<UINT32> m_fpga_ctrl;
57	61	required_shared_ptr<UINT16> m_fg_buffer;
	62
58	63	UINT32 *m_bg_buffer;
59	64	UINT32 *m_bg_buffer_front;
60	65	UINT32 *m_bg_buffer_back;
r32352	r32353
64	69	UINT32 m_blitter_src_dx;
65	70	UINT32 m_blitter_src_y;
66	71	UINT32 m_blitter_src_dy;
	72
67	73	DECLARE_WRITE32_MEMBER(skimaxx_blitter_w);
68	74	DECLARE_READ32_MEMBER(skimaxx_blitter_r);
69	75	DECLARE_WRITE32_MEMBER(skimaxx_fpga_ctrl_w);
r32352	r32353
72	78	DECLARE_WRITE32_MEMBER(skimaxx_unk1_w);
73	79	DECLARE_WRITE32_MEMBER(skimaxx_sub_ctrl_w);
74	80	DECLARE_READ32_MEMBER(skimaxx_analog_r);
	81	DECLARE_WRITE_LINE_MEMBER(tms_irq);
	82
	83	TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg);
	84	TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg);
	85	TMS340X0_SCANLINE_IND16_CB_MEMBER(scanline_update);
	86
75	87	virtual void machine_reset();
76	88	virtual void video_start();
77		required_device<cpu_device> m_maincpu;
78		required_device<cpu_device> m_subcpu;
79		required_device<tms34010_device> m_tms;
80	89	};
81	90
82	91
r32352	r32353
160	169	*************************************/
161	170
162	171	// TODO: Might not be used
163		s~~tatic void s~~kimaxx_~~to_~~s~~hif~~t~~reg(~~a~~ddr~~ess_space &space, UINT32 address, UINT16 *shiftreg)
	172	TMS340X0_TO_SHIFTREG_CB_MEMBER(skimaxx_state::to_shiftreg)
164	173	{
165		skimaxx_state *state = space.machine().driver_data<skimaxx_state>();
166		memcpy(shiftreg, &state->m_fg_buffer[TOWORD(address)], 512 * sizeof(UINT16));
	174	memcpy(shiftreg, &m_fg_buffer[TOWORD(address)], 512 * sizeof(UINT16));
167	175	}
168	176
169		s~~tatic void s~~kimaxx_~~from_~~s~~hif~~t~~reg(~~a~~ddr~~e~~ss_space &space, UINT32 add~~ress, UINT16 *shiftreg)
	177	TMS340X0_FROM_SHIFTREG_CB_MEMBER(skimaxx_state::from_shiftreg)
170	178	{
171		skimaxx_state *state = space.machine().driver_data<skimaxx_state>();
172		memcpy(&state->m_fg_buffer[TOWORD(address)], shiftreg, 512 * sizeof(UINT16));
	179	memcpy(&m_fg_buffer[TOWORD(address)], shiftreg, 512 * sizeof(UINT16));
173	180	}
174	181
175	182
r32352	r32353
179	186	*
180	187	*************************************/
181	188
182		s~~tatic void s~~kimaxx_sca~~nline_upda~~te(sc~~reen_device &screen, bitm~~a~~p_i~~n~~d16 &bitmap, int scan~~line~~, const tms34010~~_~~dis~~pla~~y_params *params~~)
	189	TMS340X0_SCANLINE_IND16_CB_MEMBER(skimaxx_state::scanline_update)
183	190	{
184		skimaxx_state *state = screen.machine().driver_data<skimaxx_state>();
185	191	// TODO: This isn't correct. I just hacked it together quickly so I could see something!
186	192
187	193	if (params->rowaddr >= 0x220)
188	194	{
189	195	UINT32 rowaddr = (params->rowaddr - 0x220);
190		UINT16 *fg = &state->m_fg_buffer[rowaddr << 8];
191		UINT32 bg = &state->m_bg_buffer_front[rowaddr/2 1024/2];
	196	UINT16 *fg = &m_fg_buffer[rowaddr << 8];
	197	UINT32 bg = &m_bg_buffer_front[rowaddr/2 1024/2];
192	198	UINT16 *dest = &bitmap.pix16(scanline);
193	199	//int coladdr = params->coladdr;
194	200	int x;
r32352	r32353
462	468	*
463	469	*************************************/
464	470
465		s~~tatic void s~~kimaxx_tms_irq~~(device_t *device, int state~~)
	471	WRITE_LINE_MEMBER(skimaxx_state::tms_irq)
466	472	{
467	473	// TODO
468	474	}
469	475
470		static const tms340x0_config tms_config =
471		{
472		FALSE, /* halt on reset */
473		"screen", /* the screen operated on */
474		50000000/8, /* pixel clock */
475		2, /* pixels per clock */
476		skimaxx_scanline_update, /* scanline updater (indexed16) */
477		NULL, /* scanline updater (rgb32) */
478		skimaxx_tms_irq, /* generate interrupt */
479		skimaxx_to_shiftreg, /* write to shiftreg function */
480		skimaxx_from_shiftreg /* read from shiftreg function */
481		};
482
483
484	476	/*************************************
485	477	*
486	478	* Initialisation
r32352	r32353
508	500
509	501	/* video hardware */
510	502	MCFG_CPU_ADD("tms", TMS34010, XTAL_50MHz)
511		MCFG_TMS340X0_CONFIG(tms_config)
512	503	MCFG_CPU_PROGRAM_MAP(tms_program_map)
	504	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
	505	MCFG_TMS340X0_PIXEL_CLOCK(50000000/8) /* pixel clock */
	506	MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
	507	MCFG_TMS340X0_SCANLINE_IND16_CB(skimaxx_state, scanline_update) /* scanline updater (indexed16) */
	508	MCFG_TMS340X0_OUTPUT_INT_CB(WRITELINE(skimaxx_state, tms_irq))
	509	MCFG_TMS340X0_TO_SHIFTREG_CB(skimaxx_state, to_shiftreg) /* write to shiftreg function */
	510	MCFG_TMS340X0_FROM_SHIFTREG_CB(skimaxx_state, from_shiftreg) /* read from shiftreg function */
513	511
514	512	MCFG_SCREEN_ADD("screen", RASTER)
515	513	// MCFG_SCREEN_RAW_PARAMS(40000000/4, 1564, 0, 1004, 328, 0, 300) // TODO - Wrong but TMS overrides it anyway

trunk/src/mame/drivers/midzeus.c
r32352	r32353
28	28
29	29	#include "emu.h"
30	30	#include "cpu/tms32031/tms32031.h"
31		#include "cpu/tms34010/tms34010.h"
32	31	#include "cpu/adsp2100/adsp2100.h"
33	32	#include "cpu/pic16c5x/pic16c5x.h"
34	33	#include "includes/midzeus.h"

trunk/src/mame/drivers/harddriv.c
r32352	r32353
333	333
334	334	/*************************************
335	335	*
336		* CPU configs
337		*
338		*************************************/
339
340		/* used on the medium-resolution driver boards */
341		static const tms340x0_config gsp_config_driver =
342		{
343		TRUE, /* halt on reset */
344		"screen", /* the screen operated on */
345		4000000, /* pixel clock */
346		4, /* pixels per clock */
347		harddriv_scanline_driver, /* scanline callback (indexed16) */
348		NULL, /* scanline callback (rgb32) */
349		hdgsp_irq_gen, /* generate interrupt */
350		hdgsp_write_to_shiftreg, /* write to shiftreg function */
351		hdgsp_read_from_shiftreg /* read from shiftreg function */
352		};
353
354
355		/* used on the low-resolution multisync boards for harddrivc, racedrivc, steeltal */
356		static const tms340x0_config gsp_config_multisync =
357		{
358		TRUE, /* halt on reset */
359		"screen", /* the screen operated on */
360		6000000, /* pixel clock */
361		2, /* pixels per clock */
362		harddriv_scanline_multisync, /* scanline callback (indexed16) */
363		NULL, /* scanline callback (rgb32 */
364		hdgsp_irq_gen, /* generate interrupt */
365		hdgsp_write_to_shiftreg, /* write to shiftreg function */
366		hdgsp_read_from_shiftreg /* read from shiftreg function */
367		};
368
369
370		/* used on the low-resolution multisync board for stunrun */
371		static const tms340x0_config gsp_config_multisync_stunrun =
372		{
373		TRUE, /* halt on reset */
374		"screen", /* the screen operated on */
375		5000000, /* pixel clock */
376		2, /* pixels per clock */
377		harddriv_scanline_multisync, /* scanline callback (indexed16) */
378		NULL, /* scanline callback (rgb32 */
379		hdgsp_irq_gen, /* generate interrupt */
380		hdgsp_write_to_shiftreg, /* write to shiftreg function */
381		hdgsp_read_from_shiftreg /* read from shiftreg function */
382		};
383
384
385		static const tms340x0_config msp_config =
386		{
387		TRUE, /* halt on reset */
388		"screen", /* the screen operated on */
389		5000000, /* pixel clock */
390		2, /* pixels per clock */
391		NULL, /* scanline callback (indexed16) */
392		NULL, /* scanline callback (rgb32 */
393		hdmsp_irq_gen /* generate interrupt */
394		};
395
396		/*************************************
397		*
398	336	* Driver board memory maps
399	337	*
400	338	*************************************/
r32352	r32353
1296	1234
1297	1235	MCFG_CPU_ADD("gsp", TMS34010, HARDDRIV_GSP_CLOCK)
1298	1236	MCFG_CPU_PROGRAM_MAP(driver_gsp_map)
1299		MCFG_TMS340X0_CONFIG(gsp_config_driver)
	1237	MCFG_TMS340X0_HALT_ON_RESET(TRUE) /* halt on reset */
	1238	MCFG_TMS340X0_PIXEL_CLOCK(4000000) /* pixel clock */
	1239	MCFG_TMS340X0_PIXELS_PER_CLOCK(4) /* pixels per clock */
	1240	MCFG_TMS340X0_SCANLINE_IND16_CB(harddriv_state, scanline_driver) /* scanline callback (indexed16) */
	1241	MCFG_TMS340X0_OUTPUT_INT_CB(WRITELINE(harddriv_state, hdgsp_irq_gen))
	1242	MCFG_TMS340X0_TO_SHIFTREG_CB(harddriv_state, hdgsp_write_to_shiftreg)
	1243	MCFG_TMS340X0_FROM_SHIFTREG_CB(harddriv_state, hdgsp_read_from_shiftreg)
1300	1244
1301	1245	MCFG_QUANTUM_TIME(attotime::from_hz(30000))
1302	1246
r32352	r32353
1328	1272	/* basic machine hardware */
1329	1273	MCFG_CPU_ADD("msp", TMS34010, XTAL_50MHz)
1330	1274	MCFG_CPU_PROGRAM_MAP(driver_msp_map)
1331		MCFG_TMS340X0_CONFIG(msp_config)
	1275	MCFG_TMS340X0_HALT_ON_RESET(TRUE) /* halt on reset */
	1276	MCFG_TMS340X0_PIXEL_CLOCK(5000000) /* pixel clock */
	1277	MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
	1278	MCFG_TMS340X0_OUTPUT_INT_CB(WRITELINE(harddriv_state, hdmsp_irq_gen))
1332	1279	MACHINE_CONFIG_END
1333	1280
1334	1281
r32352	r32353
1340	1287	MCFG_CPU_PROGRAM_MAP(multisync_68k_map)
1341	1288
1342	1289	MCFG_CPU_MODIFY("gsp")
1343		MCFG_TMS340X0_CONFIG(gsp_config_multisync)
1344	1290	MCFG_CPU_PROGRAM_MAP(multisync_gsp_map)
	1291	MCFG_TMS340X0_PIXEL_CLOCK(6000000) /* pixel clock */
	1292	MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
	1293	MCFG_TMS340X0_SCANLINE_IND16_CB(harddriv_state, scanline_multisync) /* scanline callback (indexed16) */
1345	1294
1346	1295	/* video hardware */
1347	1296	MCFG_SCREEN_MODIFY("screen")
r32352	r32353
1355	1304	/* basic machine hardware */
1356	1305	MCFG_CPU_ADD("msp", TMS34010, XTAL_50MHz)
1357	1306	MCFG_CPU_PROGRAM_MAP(driver_msp_map)
1358		MCFG_TMS340X0_CONFIG(msp_config)
	1307	MCFG_TMS340X0_HALT_ON_RESET(TRUE) /* halt on reset */
	1308	MCFG_TMS340X0_PIXEL_CLOCK(5000000) /* pixel clock */
	1309	MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
	1310	MCFG_TMS340X0_OUTPUT_INT_CB(WRITELINE(harddriv_state, hdmsp_irq_gen))
1359	1311	MACHINE_CONFIG_END
1360	1312
1361	1313
r32352	r32353
1530	1482
1531	1483	/* basic machine hardware / / multisync board without MSP */
1532	1484	MCFG_CPU_MODIFY("gsp")
1533		MCFG_TMS340X0_CO~~NFIG~~(gsp~~_conf~~i~~g_mu~~l~~tisyn~~c~~_stunrun)~~
	1485	MCFG_TMS340X0_PIXEL_CLOCK(5000000) /* pixel clock */
1534	1486	MCFG_FRAGMENT_ADD( adsp ) /* ADSP board */
1535	1487
1536	1488	/* video hardware */

trunk/src/mame/drivers/midxunit.c
r32352	r32353
232	232	INPUT_PORTS_END
233	233
234	234
235
236	235	/*************************************
237	236	*
238		* 34010 configuration
239		*
240		*************************************/
241
242		static const tms340x0_config tms_config =
243		{
244		FALSE, /* halt on reset */
245		"screen", /* the screen operated on */
246		PIXEL_CLOCK, /* pixel clock */
247		1, /* pixels per clock */
248		midxunit_scanline_update, /* scanline updater (indexed16) */
249		NULL, /* scanline updater (rgb32) */
250		NULL, /* generate interrupt */
251		midtunit_to_shiftreg, /* write to shiftreg function */
252		midtunit_from_shiftreg /* read from shiftreg function */
253		};
254
255
256
257		/*************************************
258		*
259	237	* Machine drivers
260	238	*
261	239	*************************************/
r32352	r32353
264	242
265	243	/* basic machine hardware */
266	244	MCFG_CPU_ADD("maincpu", TMS34020, 40000000)
267		MCFG_TMS340X0_CONFIG(tms_config)
268	245	MCFG_CPU_PROGRAM_MAP(main_map)
	246	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
	247	MCFG_TMS340X0_PIXEL_CLOCK(PIXEL_CLOCK) /* pixel clock */
	248	MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
	249	MCFG_TMS340X0_SCANLINE_IND16_CB(midxunit_state, scanline_update) /* scanline updater (indexed16) */
	250	MCFG_TMS340X0_TO_SHIFTREG_CB(midtunit_state, to_shiftreg) /* write to shiftreg function */
	251	MCFG_TMS340X0_FROM_SHIFTREG_CB(midtunit_state, from_shiftreg) /* read from shiftreg function */
269	252
270	253	MCFG_MACHINE_RESET_OVERRIDE(midxunit_state,midxunit)
271	254	MCFG_NVRAM_ADD_0FILL("nvram")

trunk/src/mame/drivers/potgoldu.c
r32352	r32353
27	27	potgold_state(const machine_config &mconfig, device_type type, const char *tag)
28	28	: driver_device(mconfig, type, tag),
29	29	m_maincpu(*this, "maincpu") { }
	30
	31	required_device<cpu_device> m_maincpu;
	32
30	33	virtual void machine_reset();
31	34	virtual void video_start();
32		required_device<cpu_device> m_maincpu;
	35
	36	TMS340X0_SCANLINE_RGB32_CB_MEMBER(scanline_update);
33	37	};
34	38
35	39
r32352	r32353
45	49	{
46	50	}
47	51
48		st~~atic v~~o~~id scan~~l~~ine_up~~d~~ate(screen~~_~~device &~~s~~creen, bi~~tma~~p_rgb32 &bi~~t~~map, int~~ scanline~~, const tms34010~~_~~dis~~pla~~y_params *params~~)
	52	TMS340X0_SCANLINE_RGB32_CB_MEMBER(potgold_state::scanline_update)
49	53	{
50	54	}
51	55
r32352	r32353
64	68	INPUT_PORTS_END
65	69
66	70
67		static const tms340x0_config tms_config =
68		{
69		FALSE, /* halt on reset */
70		"screen", /* the screen operated on */
71		VIDEO_CLOCK/2, /* pixel clock */
72		1, /* pixels per clock */
73		NULL, /* scanline callback (indexed16) */
74		scanline_update, /* scanline callback (rgb32) */
75		NULL, /* generate interrupt */
76		NULL, /* write to shiftreg function */
77		NULL /* read from shiftreg function */
78		};
79
80
81	71	static MACHINE_CONFIG_START( potgold, potgold_state )
82	72
83	73	/* basic machine hardware */
84	74	MCFG_CPU_ADD("maincpu", TMS34010, XTAL_40MHz)
85		MCFG_TMS340X0_CONFIG(tms_config)
86	75	MCFG_CPU_PROGRAM_MAP(potgold_map)
	76	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
	77	MCFG_TMS340X0_PIXEL_CLOCK(VIDEO_CLOCK/2) /* pixel clock */
	78	MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
	79	MCFG_TMS340X0_SCANLINE_RGB32_CB(potgold_state, scanline_update) /* scanline callback (rgb32) */
87	80
88
89
90	81	MCFG_SCREEN_ADD("screen", RASTER)
91	82	MCFG_SCREEN_RAW_PARAMS(VIDEO_CLOCK/2, 444, 0, 320, 233, 0, 200)
92	83	MCFG_SCREEN_UPDATE_DEVICE("maincpu", tms34010_device, tms340x0_rgb32)

trunk/src/mame/drivers/skeetsht.c
r32352	r32353
46	46	DECLARE_READ8_MEMBER(hc11_porta_r);
47	47	DECLARE_WRITE8_MEMBER(hc11_porta_w);
48	48	DECLARE_WRITE8_MEMBER(ay8910_w);
	49	DECLARE_WRITE_LINE_MEMBER(tms_irq);
	50	TMS340X0_SCANLINE_RGB32_CB_MEMBER(scanline_update);
49	51	virtual void machine_reset();
50	52	virtual void video_start();
51	53	required_device<cpu_device> m_68hc11;
r32352	r32353
75	77	{
76	78	}
77	79
78		s~~tatic void s~~keetsht_sca~~nline_upda~~te(sc~~reen_device &screen, bitm~~a~~p_rgb32 &bitmap, i~~n~~t scan~~line~~, const tms34010~~_~~dis~~pla~~y_params *params~~)
	80	TMS340X0_SCANLINE_RGB32_CB_MEMBER(skeetsht_state::scanline_update)
79	81	{
80		skeetsht_state *state = screen.machine().driver_data<skeetsht_state>();
81		const rgb_t *const pens = state->m_tlc34076->get_pens();
82		UINT16 *vram = &state->m_tms_vram[(params->rowaddr << 8) & 0x3ff00];
	82	const rgb_t *const pens = m_tlc34076->get_pens();
	83	UINT16 *vram = &m_tms_vram[(params->rowaddr << 8) & 0x3ff00];
83	84	UINT32 *dest = &bitmap.pix32(scanline);
84	85	int coladdr = params->coladdr;
85	86	int x;
r32352	r32353
119	120	*
120	121	*************************************/
121	122
122		s~~tatic void s~~keetsht_tms_irq~~(device_t *device, int state~~)
	123	WRITE_LINE_MEMBER(skeetsht_state::tms_irq)
123	124	{
124		skeetsht_state *drvstate = device->machine().driver_data<skeetsht_state>();
125		drvstate->m_68hc11->set_input_line(MC68HC11_IRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
	125	m_68hc11->set_input_line(MC68HC11_IRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
126	126	}
127	127
128	128
r32352	r32353
213	213	INPUT_PORTS_END
214	214
215	215
216		/*************************************
217		*
218		* TMS34010 configuration
219		*
220		*************************************/
221	216
222		static const tms340x0_config tms_config =
223		{
224		TRUE, /* halt on reset */
225		"screen", /* the screen operated on */
226		48000000 / 8, /* pixel clock */
227		1, /* pixels per clock */
228		NULL, /* scanline updater (indexed16) */
229		skeetsht_scanline_update, /* scanline updater (rgb32) */
230		skeetsht_tms_irq, /* generate interrupt */
231		NULL, /* write to shiftreg function */
232		NULL /* read from shiftreg function */
233		};
234
235
236
237	217	/*************************************
238	218	*
239	219	* Machine driver
r32352	r32353
248	228	MCFG_MC68HC11_CONFIG( 0, 0x100, 0x01 ) // And 512 bytes EEPROM? (68HC11A1)
249	229
250	230	MCFG_CPU_ADD("tms", TMS34010, 48000000)
251		MCFG_TMS340X0_CONFIG(tms_config)
252	231	MCFG_CPU_PROGRAM_MAP(tms_program_map)
	232	MCFG_TMS340X0_HALT_ON_RESET(TRUE) /* halt on reset */
	233	MCFG_TMS340X0_PIXEL_CLOCK(48000000 / 8) /* pixel clock */
	234	MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
	235	MCFG_TMS340X0_SCANLINE_RGB32_CB(skeetsht_state, scanline_update) /* scanline updater (rgb32) */
	236	MCFG_TMS340X0_OUTPUT_INT_CB(WRITELINE(skeetsht_state, tms_irq))
253	237
254
255	238	MCFG_TLC34076_ADD("tlc34076", TLC34076_6_BIT)
256	239
257	240	MCFG_SCREEN_ADD("screen", RASTER)

trunk/src/mame/drivers/xtheball.c
r32352	r32353
21	21	public:
22	22	xtheball_state(const machine_config &mconfig, device_type type, const char *tag)
23	23	: driver_device(mconfig, type, tag),
	24	m_maincpu(*this, "maincpu"),
24	25	m_tlc34076(*this, "tlc34076"),
25	26	m_vram_bg(*this, "vrabg"),
26	27	m_vram_fg(*this, "vrafg"),
27	28	m_analog_x(*this, "ANALOGX"),
28		m_analog_y(*this, "ANALOGY"),
29		m_maincpu(*this, "maincpu") { }
	29	m_analog_y(*this, "ANALOGY") { }
30	30
	31	required_device<cpu_device> m_maincpu;
31	32	required_device<tlc34076_device> m_tlc34076;
32	33	required_shared_ptr<UINT16> m_vram_bg;
33	34	required_shared_ptr<UINT16> m_vram_fg;
r32352	r32353
37	38	DECLARE_WRITE16_MEMBER(bit_controls_w);
38	39	DECLARE_READ16_MEMBER(analogx_r);
39	40	DECLARE_READ16_MEMBER(analogy_watchdog_r);
40		required_device<cpu_device> m_maincpu;
	41	TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg);
	42	TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg);
	43	TMS340X0_SCANLINE_RGB32_CB_MEMBER(scanline_update);
41	44	};
42	45
43	46
r32352	r32353
49	52	*
50	53	*************************************/
51	54
52		~~static void~~ xtheball_sca~~nline_upda~~te(sc~~reen_device &screen, bitm~~a~~p_rgb32 &bitmap, i~~n~~t scan~~line~~, const tms34010~~_~~dis~~pla~~y_params *params~~)
	55	TMS340X0_SCANLINE_RGB32_CB_MEMBER(xtheball_state::scanline_update)
53	56	{
54		xtheball_state *state = screen.machine().driver_data<xtheball_state>();
55		UINT16 *srcbg = &state->m_vram_bg[(params->rowaddr << 8) & 0xff00];
	57	UINT16 *srcbg = &m_vram_bg[(params->rowaddr << 8) & 0xff00];
56	58	UINT32 *dest = &bitmap.pix32(scanline);
57		const rgb_t *pens = ~~state->~~m_tlc34076->get_pens();
	59	const rgb_t *pens = m_tlc34076->get_pens();
58	60	int coladdr = params->coladdr;
59	61	int x;
60	62
61	63	/* bit value 0x13 controls which foreground mode to use */
62		if (!~~state->~~m_bitvals[0x13])
	64	if (!m_bitvals[0x13])
63	65	{
64	66	/* mode 0: foreground is the same as background */
65		UINT16 *srcfg = &~~state->~~m_vram_fg[(params->rowaddr << 8) & 0xff00];
	67	UINT16 *srcfg = &m_vram_fg[(params->rowaddr << 8) & 0xff00];
66	68
67	69	for (x = params->heblnk; x < params->hsblnk; x += 2, coladdr++)
68	70	{
r32352	r32353
77	79	{
78	80	/* mode 1: foreground is half background resolution in */
79	81	/* X and supports two pages */
80		UINT16 *srcfg = &~~state->~~m_vram_fg[(params->rowaddr << 7) & 0xff00];
	82	UINT16 *srcfg = &m_vram_fg[(params->rowaddr << 7) & 0xff00];
81	83
82	84	for (x = params->heblnk; x < params->hsblnk; x += 2, coladdr++)
83	85	{
r32352	r32353
99	101	*
100	102	*************************************/
101	103
102		~~static void~~ xtheball_~~to_~~s~~hif~~t~~reg(~~a~~ddr~~ess_space &space, UINT32 address, UINT16 *shiftreg)
	104	TMS340X0_TO_SHIFTREG_CB_MEMBER(xtheball_state::to_shiftreg)
103	105	{
104		xtheball_state *state = space.machine().driver_data<xtheball_state>();
105	106	if (address >= 0x01000000 && address <= 0x010fffff)
106		memcpy(shiftreg, &~~state->~~m_vram_bg[TOWORD(address & 0xff000)], TOBYTE(0x1000));
	107	memcpy(shiftreg, &m_vram_bg[TOWORD(address & 0xff000)], TOBYTE(0x1000));
107	108	else if (address >= 0x02000000 && address <= 0x020fffff)
108		memcpy(shiftreg, &~~state->~~m_vram_fg[TOWORD(address & 0xff000)], TOBYTE(0x1000));
	109	memcpy(shiftreg, &m_vram_fg[TOWORD(address & 0xff000)], TOBYTE(0x1000));
109	110	else
110	111	logerror("%s:xtheball_to_shiftreg(%08X)\n", space.machine().describe_context(), address);
111	112	}
112	113
113	114
114		~~static void~~ xtheball_~~from_~~s~~hif~~t~~reg(~~a~~ddr~~e~~ss_space &space, UINT32 add~~ress, UINT16 *shiftreg)
	115	TMS340X0_FROM_SHIFTREG_CB_MEMBER(xtheball_state::from_shiftreg)
115	116	{
116		xtheball_state *state = space.machine().driver_data<xtheball_state>();
117	117	if (address >= 0x01000000 && address <= 0x010fffff)
118		memcpy(&~~state->~~m_vram_bg[TOWORD(address & 0xff000)], shiftreg, TOBYTE(0x1000));
	118	memcpy(&m_vram_bg[TOWORD(address & 0xff000)], shiftreg, TOBYTE(0x1000));
119	119	else if (address >= 0x02000000 && address <= 0x020fffff)
120		memcpy(&~~state->~~m_vram_fg[TOWORD(address & 0xff000)], shiftreg, TOBYTE(0x1000));
	120	memcpy(&m_vram_fg[TOWORD(address & 0xff000)], shiftreg, TOBYTE(0x1000));
121	121	else
122	122	logerror("%s:xtheball_from_shiftreg(%08X)\n", space.machine().describe_context(), address);
123	123	}
r32352	r32353
315	315	INPUT_PORTS_END
316	316
317	317
318
319	318	/*************************************
320	319	*
321		* 34010 configuration
322		*
323		*************************************/
324
325		static const tms340x0_config tms_config =
326		{
327		FALSE, /* halt on reset */
328		"screen", /* the screen operated on */
329		10000000, /* pixel clock */
330		1, /* pixels per clock */
331		NULL, /* scanline callback (indexed16) */
332		xtheball_scanline_update, /* scanline callback (rgb32) */
333		NULL, /* generate interrupt */
334		xtheball_to_shiftreg, /* write to shiftreg function */
335		xtheball_from_shiftreg /* read from shiftreg function */
336		};
337
338
339
340		/*************************************
341		*
342	320	* Machine drivers
343	321	*
344	322	*************************************/
r32352	r32353
346	324	static MACHINE_CONFIG_START( xtheball, xtheball_state )
347	325
348	326	MCFG_CPU_ADD("maincpu", TMS34010, 40000000)
349		MCFG_TMS340X0_CONFIG(tms_config)
350	327	MCFG_CPU_PROGRAM_MAP(main_map)
	328	MCFG_TMS340X0_HALT_ON_RESET(FALSE) /* halt on reset */
	329	MCFG_TMS340X0_PIXEL_CLOCK(10000000) /* pixel clock */
	330	MCFG_TMS340X0_PIXELS_PER_CLOCK(1) /* pixels per clock */
	331	MCFG_TMS340X0_SCANLINE_RGB32_CB(xtheball_state, scanline_update) /* scanline updater (rgb32) */
	332	MCFG_TMS340X0_TO_SHIFTREG_CB(xtheball_state, to_shiftreg) /* write to shiftreg function */
	333	MCFG_TMS340X0_FROM_SHIFTREG_CB(xtheball_state, from_shiftreg) /* read from shiftreg function */
351	334	MCFG_CPU_PERIODIC_INT_DRIVER(xtheball_state, irq1_line_hold, 15000)
352	335
353	336	MCFG_NVRAM_ADD_1FILL("nvram")

trunk/src/mame/machine/harddriv.c
r32352	r32353
118	118	}
119	119
120	120
121		~~voi~~d hdgsp_irq_gen~~(device_t *device, int irqstate~~)
	121	WRITE_LINE_MEMBER(harddriv_state::hdgsp_irq_gen)
122	122	{
123		harddriv_state *state = device->machine().driver_data<harddriv_state>();
124		state->m_gsp_irq_state = irqstate;
125		state->update_interrupts();
	123	m_gsp_irq_state = state;
	124	update_interrupts();
126	125	}
127	126
128	127
129		~~voi~~d hdmsp_irq_gen~~(device_t *device, int irqstate~~)
	128	WRITE_LINE_MEMBER(harddriv_state::hdmsp_irq_gen)
130	129	{
131		harddriv_state *state = device->machine().driver_data<harddriv_state>();
132		state->m_msp_irq_state = irqstate;
133		state->update_interrupts();
	130	m_msp_irq_state = state;
	131	update_interrupts();
134	132	}
135	133
136	134

trunk/src/mame/machine/inder_vid.c
r32352	r32353
33	33	ADDRESS_MAP_END
34	34
35	35
36		~~static void megaphx~~_~~scanl~~ine~~(sc~~r~~een~~_device &sc~~reen, bitm~~a~~p_rgb32 &bitmap, i~~n~~t scan~~line~~, const tms34010_display_params *params~~)
	36	TMS340X0_SCANLINE_RGB32_CB_MEMBER(inder_vid_device::scanline)
37	37	{
38		inder_vid_device state = (inder_vid_device)screen.machine().device("inder_vid");
39
40		UINT16 *vram = &state->m_vram[(params->rowaddr << 8) & 0x3ff00];
	38	UINT16 *vram = &m_vram[(params->rowaddr << 8) & 0x3ff00];
41	39	UINT32 *dest = &bitmap.pix32(scanline);
42	40
43		const pen_t *paldata = ~~state->~~m_palette->pens();
	41	const pen_t *paldata = m_palette->pens();
44	42
45	43	int coladdr = params->coladdr;
46	44	int x;
r32352	r32353
55	53	}
56	54
57	55
58		~~stat~~i~~c voi~~d me~~gaphx~~_~~to_sh~~i~~ftreg(a~~ddre~~ss_spa~~ce &space, UINT32 address, UINT16 *shiftreg)
	56	TMS340X0_TO_SHIFTREG_CB_MEMBER(inder_vid_device::to_shiftreg)
59	57	{
60		inder_vid_device state = (inder_vid_device)space.machine().device("inder_vid");
61
62		if (state->m_shiftfull == 0)
	58	if (m_shiftfull == 0)
63	59	{
64	60	//printf("read to shift regs address %08x (%08x)\n", address, TOWORD(address) * 2);
65	61
66		memcpy(shiftreg, &state->m_vram[TOWORD(address) & ~TOWORD(0x1fff)], TOBYTE(0x2000)); // & ~TOWORD(0x1fff) is needed for round 6
67		state->m_shiftfull = 1;
	62	memcpy(shiftreg, &m_vram[TOWORD(address) & ~TOWORD(0x1fff)], TOBYTE(0x2000)); // & ~TOWORD(0x1fff) is needed for round 6
	63	m_shiftfull = 1;
68	64	}
69	65	}
70	66
71		~~stat~~i~~c voi~~d me~~gaphx_f~~rom_shi~~ftreg(a~~ddre~~ss_spa~~ce ~~&space, UINT32 add~~ress, UINT16 *shiftreg)
	67	TMS340X0_FROM_SHIFTREG_CB_MEMBER(inder_vid_device::from_shiftreg)
72	68	{
73	69	// printf("write from shift regs address %08x (%08x)\n", address, TOWORD(address) * 2);
74	70
75		~~ind~~er_vid_device s~~tate~~ = (inder_vid_device)s~~pace.mac~~hine()~~.device("inder_vid"~~);
	71	memcpy(&m_vram[TOWORD(address) & ~TOWORD(0x1fff)], shiftreg, TOBYTE(0x2000));
76	72
77		memcpy(&state->m_vram[TOWORD(address) & ~TOWORD(0x1fff)], shiftreg, TOBYTE(0x2000));
78
79		state->m_shiftfull = 0;
	73	m_shiftfull = 0;
80	74	}
81	75
82
83
84		static void m68k_gen_int(device_t *device, int state)
	76	WRITE_LINE_MEMBER(inder_vid_device::m68k_gen_int)
85	77	{
86		cpu_device maincpu = (cpu_device)~~device->~~machine().device("maincpu");
	78	cpu_device maincpu = (cpu_device)machine().device("maincpu");
87	79	if (state) maincpu->set_input_line(4, ASSERT_LINE);
88	80	else maincpu->set_input_line(4, CLEAR_LINE);
89
90	81	}
91	82
92	83
93		static const tms340x0_config tms_config_megaphx =
94		{
95		TRUE, /* halt on reset */
96		"inder_vid:inder_screen", /* the screen operated on */
97		XTAL_40MHz/12, /* pixel clock */
98		2, /* pixels per clock */
99		NULL, /* scanline callback (indexed16) */
100		megaphx_scanline, /* scanline callback (rgb32) */
101		m68k_gen_int, /* generate interrupt */
102		megaphx_to_shiftreg, /* write to shiftreg function */
103		megaphx_from_shiftreg /* read from shiftreg function */
104		};
105
106
107	84	static ADDRESS_MAP_START( ramdac_map, AS_0, 8, inder_vid_device )
108	85	AM_RANGE(0x000, 0x3ff) AM_DEVREADWRITE("ramdac",ramdac_device,ramdac_pal_r,ramdac_rgb888_w)
109	86	ADDRESS_MAP_END
110	87
111	88	static MACHINE_CONFIG_FRAGMENT( inder_vid )
112	89	MCFG_CPU_ADD("tms", TMS34010, XTAL_40MHz)
113		MCFG_TMS340X0_CONFIG(tms_config_megaphx)
114	90	MCFG_CPU_PROGRAM_MAP(megaphx_tms_map)
	91	MCFG_TMS340X0_HALT_ON_RESET(TRUE) /* halt on reset */
	92	MCFG_TMS340X0_PIXEL_CLOCK(XTAL_40MHz/12) /* pixel clock */
	93	MCFG_TMS340X0_PIXELS_PER_CLOCK(2) /* pixels per clock */
	94	MCFG_TMS340X0_SCANLINE_RGB32_CB(inder_vid_device, scanline) /* scanline updater (RGB32) */
	95	MCFG_TMS340X0_OUTPUT_INT_CB(WRITELINE(inder_vid_device, m68k_gen_int))
	96	MCFG_TMS340X0_TO_SHIFTREG_CB(inder_vid_device, to_shiftreg) /* write to shiftreg function */
	97	MCFG_TMS340X0_FROM_SHIFTREG_CB(inder_vid_device, from_shiftreg) /* read from shiftreg function */
115	98
116	99	MCFG_SCREEN_ADD("inder_screen", RASTER)
117	100	MCFG_SCREEN_RAW_PARAMS(XTAL_40MHz/12, 424, 0, 338-1, 262, 0, 246-1)

trunk/src/mame/machine/inder_vid.h
r32352	r32353
29	29	required_shared_ptr<UINT16> m_vram;
30	30	required_device<palette_device> m_palette;
31	31	required_device<tms34010_device> m_tms;
	32
	33	DECLARE_WRITE_LINE_MEMBER(m68k_gen_int);
32	34
33	35	int m_shiftfull; // this might be a driver specific hack for a TMS bug.
	36	TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg);
	37	TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg);
	38	TMS340X0_SCANLINE_RGB32_CB_MEMBER(scanline);
34	39
35	40	protected:
36	41	virtual machine_config_constructor device_mconfig_additions() const;
37	42	virtual void device_start();
38	43	virtual void device_reset();
39
40
41
	44
42	45	private:
43
44
45	46	};
46	47
47	48	#endif

trunk/src/mame/machine/midtunit.c
r32352	r32353
396	396
397	397
398	398	/* default graphics functionality */
399		m~~idtunit~~_gfx_rom_large = 0;
	399	m_gfx_rom_large = 0;
400	400	}
401	401
402	402
r32352	r32353
500	500	{
501	501	/* common init */
502	502	init_tunit_generic(SOUND_DCS);
503		m~~idtunit~~_gfx_rom_large = 1;
	503	m_gfx_rom_large = 1;
504	504
505	505	/* protection */
506	506	m_maincpu->space(AS_PROGRAM).install_write_handler(0x00f20c60, 0x00f20c7f, write16_delegate(FUNC(midtunit_state::mk2_prot_w),this));

trunk/src/mame/includes/micro3d.h
r32352	r32353
137	137	DECLARE_READ8_MEMBER(duart_input_r);
138	138	DECLARE_WRITE8_MEMBER(duart_output_w);
139	139	DECLARE_WRITE_LINE_MEMBER(duart_txb);
	140	DECLARE_WRITE_LINE_MEMBER(tms_interrupt);
	141	TMS340X0_SCANLINE_IND16_CB_MEMBER(scanline_update);
140	142
141	143	required_device<cpu_device> m_maincpu;
142	144	required_device<i8051_device> m_audiocpu;
r32352	r32353
220	222	};
221	223
222	224	extern const device_type MICRO3D;
223
224		/----------- defined in video/micro3d.c -----------/
225		void micro3d_tms_interrupt(device_t *device, int state);
226		void micro3d_scanline_update(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params);

trunk/src/mame/includes/metalmx.h
r32352	r32353
49	49	DECLARE_WRITE32_MEMBER(timer_w);
50	50	DECLARE_DRIVER_INIT(metalmx);
51	51	DECLARE_WRITE8_MEMBER(cage_irq_callback);
	52	DECLARE_WRITE_LINE_MEMBER(tms_interrupt);
52	53	virtual void machine_reset();
53	54	virtual void video_start();
54	55	UINT32 screen_update_metalmx(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);

trunk/src/mame/includes/midyunit.h
r32352	r32353
99	99	DECLARE_CUSTOM_INPUT_MEMBER(narc_talkback_data_r);
100	100	DECLARE_CUSTOM_INPUT_MEMBER(adpcm_irq_state_r);
101	101	DECLARE_WRITE8_MEMBER(yawdim_oki_bank_w);
	102	TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg);
	103	TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg);
	104	TMS340X0_SCANLINE_IND16_CB_MEMBER(scanline_update);
102	105	DECLARE_DRIVER_INIT(smashtv);
103	106	DECLARE_DRIVER_INIT(strkforc);
104	107	DECLARE_DRIVER_INIT(narc);
r32352	r32353
129	132	protected:
130	133	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
131	134	};
132
133		/----------- defined in video/midyunit.c -----------/
134		void midyunit_to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg);
135		void midyunit_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg);
136		void midyunit_scanline_update(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params);

trunk/src/mame/includes/artmagic.h
r32352	r32353
58	58	DECLARE_READ16_MEMBER(unk_r);
59	59	DECLARE_READ16_MEMBER(artmagic_blitter_r);
60	60	DECLARE_WRITE16_MEMBER(artmagic_blitter_w);
	61	DECLARE_WRITE_LINE_MEMBER(m68k_gen_int);
	62	TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg);
	63	TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg);
	64	TMS340X0_SCANLINE_RGB32_CB_MEMBER(scanline);
61	65	DECLARE_CUSTOM_INPUT_MEMBER(prot_r);
62	66	DECLARE_DRIVER_INIT(shtstar);
63	67	DECLARE_DRIVER_INIT(cheesech);
r32352	r32353
69	73	void decrypt_cheesech();
70	74	void decrypt_ultennis();
71	75	void execute_blit();
	76	void update_irq_state();
72	77	inline UINT16 address_to_vram(offs_t address);
73	78
74	79	protected:
75	80	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
76	81	};
77
78
79		/----------- defined in video/artmagic.c -----------/
80		void artmagic_to_shiftreg(address_space &space, offs_t address, UINT16 *data);
81		void artmagic_from_shiftreg(address_space &space, offs_t address, UINT16 *data);
82		void artmagic_scanline(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params);

trunk/src/mame/includes/coolpool.h
r32352	r32353
61	61	DECLARE_WRITE16_MEMBER(dsp_romaddr_w);
62	62	DECLARE_READ16_MEMBER(coolpool_input_r);
63	63	DECLARE_WRITE16_MEMBER(dsp_dac_w);
	64	TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg);
	65	TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg);
	66	TMS340X0_SCANLINE_RGB32_CB_MEMBER(amerdart_scanline);
	67	TMS340X0_SCANLINE_RGB32_CB_MEMBER(coolpool_scanline);
64	68	DECLARE_DRIVER_INIT(coolpool);
65	69	DECLARE_DRIVER_INIT(amerdart);
66	70	DECLARE_DRIVER_INIT(9ballsht);

trunk/src/mame/includes/midtunit.h
r32352	r32353
66	66	DECLARE_READ16_MEMBER(midxunit_paletteram_r);
67	67	DECLARE_READ16_MEMBER(midtunit_dma_r);
68	68	DECLARE_WRITE16_MEMBER(midtunit_dma_w);
	69	TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg);
	70	TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg);
	71	TMS340X0_SCANLINE_IND16_CB_MEMBER(scanline_update);
69	72	DECLARE_DRIVER_INIT(mktunit);
70	73	DECLARE_DRIVER_INIT(mkturbo);
71	74	DECLARE_DRIVER_INIT(nbajamte);
r32352	r32353
101	104	const UINT8 *jdredd_prot_table;
102	105	UINT8 jdredd_prot_index;
103	106	UINT8 jdredd_prot_max;
	107
	108	UINT8 m_gfx_rom_large;
104	109
105	110	protected:
106	111	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
107	112	};
108
109
110		/----------- defined in video/midtunit.c -----------/
111		extern UINT8 midtunit_gfx_rom_large;
112
113		void midtunit_to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg);
114		void midtunit_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg);
115
116		void midtunit_scanline_update(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params);
117		void midxunit_scanline_update(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params);

trunk/src/mame/includes/jpmimpct.h
r32352	r32353
106	106	DECLARE_READ8_MEMBER(hopper_c_r);
107	107	DECLARE_WRITE8_MEMBER(payen_a_w);
108	108	DECLARE_WRITE8_MEMBER(display_c_w);
109
	109
	110	DECLARE_WRITE_LINE_MEMBER(tms_irq);
	111	TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg);
	112	TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg);
	113	TMS340X0_SCANLINE_RGB32_CB_MEMBER(scanline_update);
	114
110	115	DECLARE_MACHINE_START(jpmimpct);
111	116	DECLARE_MACHINE_RESET(jpmimpct);
112	117	DECLARE_VIDEO_START(jpmimpct);
r32352	r32353
119	124	optional_device<palette_device> m_palette;
120	125	optional_device<tms34010_device> m_dsp;
121	126	};
122
123
124		/----------- defined in video/jpmimpct.c -----------/
125		void jpmimpct_to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg);
126		void jpmimpct_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg);
127		void jpmimpct_scanline_update(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params);

trunk/src/mame/includes/exterm.h
r32352	r32353
44	44	DECLARE_PALETTE_INIT(exterm);
45	45	TIMER_CALLBACK_MEMBER(sound_delayed_w);
46	46	TIMER_DEVICE_CALLBACK_MEMBER(master_sound_nmi_callback);
	47	TMS340X0_SCANLINE_IND16_CB_MEMBER(scanline_update);
	48	TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg_master);
	49	TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg_master);
	50	TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg_slave);
	51	TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg_slave);
47	52	required_device<cpu_device> m_maincpu;
48	53	required_device<cpu_device> m_audiocpu;
49	54	required_device<cpu_device> m_audioslave;
50	55	required_device<tms34010_device> m_slave;
51	56	required_device<dac_device> m_dac;
52	57	};
53
54		/----------- defined in video/exterm.c -----------/
55		void exterm_scanline_update(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params);
56
57		void exterm_to_shiftreg_master(address_space &space, UINT32 address, UINT16* shiftreg);
58		void exterm_from_shiftreg_master(address_space &space, UINT32 address, UINT16* shiftreg);
59		void exterm_to_shiftreg_slave(address_space &space, UINT32 address, UINT16* shiftreg);
60		void exterm_from_shiftreg_slave(address_space &space, UINT32 address, UINT16* shiftreg);

trunk/src/mame/includes/lethalj.h
r32352	r32353
19	19	m_maincpu(*this, "maincpu"),
20	20	m_screen(*this, "screen") { }
21	21
	22	required_device<cpu_device> m_maincpu;
	23	required_device<screen_device> m_screen;
22	24	UINT16 m_blitter_data[8];
23	25	UINT16 *m_screenram;
24	26	UINT8 m_vispage;
r32352	r32353
39	41	DECLARE_DRIVER_INIT(cclownz);
40	42	virtual void video_start();
41	43	inline void get_crosshair_xy(int player, int x, int y);
42		required_device<cpu_device> m_maincpu;
43		required_device<screen_device> m_screen;
	44	TMS340X0_SCANLINE_IND16_CB_MEMBER(scanline_update);
44	45
45	46	protected:
46	47	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);

trunk/src/mame/includes/harddriv.h
r32352	r32353
331	331	DECLARE_WRITE16_MEMBER( hdgsp_io_w );
332	332
333	333	DECLARE_WRITE16_MEMBER( hdgsp_protection_w );
	334
	335	DECLARE_WRITE_LINE_MEMBER( hdgsp_irq_gen );
	336	DECLARE_WRITE_LINE_MEMBER( hdmsp_irq_gen );
334	337
335	338	/* ADSP board */
336	339	DECLARE_READ16_MEMBER( hd68k_adsp_program_r );
r32352	r32353
436	439	DECLARE_READ32_MEMBER(hdds3xdsp_serial_rx_callback);
437	440
438	441	/----------- defined in video/harddriv.c -----------/
	442	TMS340X0_TO_SHIFTREG_CB_MEMBER(hdgsp_write_to_shiftreg);
	443	TMS340X0_FROM_SHIFTREG_CB_MEMBER(hdgsp_read_from_shiftreg);
	444
	445	void update_palette_bank(int newbank);
	446
439	447	DECLARE_READ16_MEMBER( hdgsp_control_lo_r );
440	448	DECLARE_WRITE16_MEMBER( hdgsp_control_lo_w );
441	449	DECLARE_READ16_MEMBER( hdgsp_control_hi_r );
r32352	r32353
456	464	/* DS III/IV board */
457	465	TIMER_DEVICE_CALLBACK_MEMBER( ds3sdsp_internal_timer_callback );
458	466	TIMER_DEVICE_CALLBACK_MEMBER( ds3xdsp_internal_timer_callback );
459
	467
	468	TMS340X0_SCANLINE_IND16_CB_MEMBER(scanline_driver);
	469	TMS340X0_SCANLINE_IND16_CB_MEMBER(scanline_multisync);
460	470	};
461
462
463		/----------- defined in machine/harddriv.c -----------/
464
465		/* Driver/Multisync board */
466		void hdgsp_irq_gen(device_t *device, int state);
467		void hdmsp_irq_gen(device_t *device, int state);
468
469
470
471		/----------- defined in video/harddriv.c -----------/
472
473		void hdgsp_write_to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg);
474		void hdgsp_read_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg);
475
476		void harddriv_scanline_driver(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params);
477		void harddriv_scanline_multisync(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params);

trunk/src/mame/includes/btoads.h
r32352	r32353
61	61	DECLARE_READ16_MEMBER( vram_fg_display_r );
62	62	DECLARE_READ16_MEMBER( vram_fg_draw_r );
63	63	void render_sprite_row(UINT16 *sprite_source, UINT32 address);
64		void to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg);
65		static void static_to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg) { space.machine().driver_data<btoads_state>()->to_shiftreg(space, address, shiftreg); }
66		void from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg);
67		static void static_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg) { space.machine().driver_data<btoads_state>()->from_shiftreg(space, address, shiftreg); }
68		void scanline_update(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params);
69		static void static_scanline_update(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params) { screen.machine().driver_data<btoads_state>()->scanline_update(screen, bitmap, scanline, params); }
	64	TMS340X0_TO_SHIFTREG_CB_MEMBER(to_shiftreg);
	65	TMS340X0_FROM_SHIFTREG_CB_MEMBER(from_shiftreg);
	66	TMS340X0_SCANLINE_RGB32_CB_MEMBER(scanline_update);
70	67
71	68	protected:
72	69	// device overrides

trunk/src/mame/includes/midxunit.h
r32352	r32353
45	45	DECLARE_MACHINE_RESET(midxunit);
46	46	DECLARE_VIDEO_START(midxunit);
47	47	void register_state_saving();
	48	TMS340X0_SCANLINE_IND16_CB_MEMBER(scanline_update);
48	49	};

trunk/src/mame/video/btoads.c
r32352	r32353
259	259	*
260	260	*************************************/
261	261
262		~~void~~ btoads_state::to_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
	262	TMS340X0_TO_SHIFTREG_CB_MEMBER(btoads_state::to_shiftreg)
263	263	{
264	264	address &= ~0x40000000;
265	265
r32352	r32353
286	286	}
287	287
288	288
289		~~void~~ btoads_state::from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
	289	TMS340X0_FROM_SHIFTREG_CB_MEMBER(btoads_state::from_shiftreg)
290	290	{
291	291	address &= ~0x40000000;
292	292
r32352	r32353
318	318	*
319	319	*************************************/
320	320
321		~~void~~ btoads_state::scanline_update~~(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params~~)
	321	TMS340X0_SCANLINE_RGB32_CB_MEMBER(btoads_state::scanline_update)
322	322	{
323	323	UINT32 fulladdr = ((params->rowaddr << 16) \| params->coladdr) >> 4;
324	324	UINT16 *bg0_base = &m_vram_bg0[(fulladdr + (m_yscroll0 << 10)) & 0x3fc00];

trunk/src/mame/video/jpmimpct.c
r32352	r32353
86	86	*
87	87	*************************************/
88	88
89		~~void~~ jpmimpct_~~to_~~s~~hif~~t~~reg(~~a~~ddr~~ess_space &space, UINT32 address, UINT16 *shiftreg)
	89	TMS340X0_TO_SHIFTREG_CB_MEMBER(jpmimpct_state::to_shiftreg)
90	90	{
91		jpmimpct_state *state = space.machine().driver_data<jpmimpct_state>();
92		memcpy(shiftreg, &state->m_vram[TOWORD(address)], 512 * sizeof(UINT16));
	91	memcpy(shiftreg, &m_vram[TOWORD(address)], 512 * sizeof(UINT16));
93	92	}
94	93
95		~~void~~ jpmimpct_~~from_~~s~~hif~~t~~reg(~~a~~ddr~~e~~ss_space &space, UINT32 add~~ress, UINT16 *shiftreg)
	94	TMS340X0_FROM_SHIFTREG_CB_MEMBER(jpmimpct_state::from_shiftreg)
96	95	{
97		jpmimpct_state *state = space.machine().driver_data<jpmimpct_state>();
98		memcpy(&state->m_vram[TOWORD(address)], shiftreg, 512 * sizeof(UINT16));
	96	memcpy(&m_vram[TOWORD(address)], shiftreg, 512 * sizeof(UINT16));
99	97	}
100	98
101	99
r32352	r32353
105	103	*
106	104	*************************************/
107	105
108		~~void~~ jpmimpct_sca~~nline_upda~~te(sc~~reen_device &screen, bitm~~a~~p_rgb32 &bitmap, i~~n~~t scan~~line~~, const tms34010~~_~~dis~~pla~~y_params *params~~)
	106	TMS340X0_SCANLINE_RGB32_CB_MEMBER(jpmimpct_state::scanline_update)
109	107	{
110		jpmimpct_state *state = screen.machine().driver_data<jpmimpct_state>();
111		UINT16 *vram = &state->m_vram[(params->rowaddr << 8) & 0x3ff00];
	108	UINT16 *vram = &m_vram[(params->rowaddr << 8) & 0x3ff00];
112	109	UINT32 *dest = &bitmap.pix32(scanline);
113	110	int coladdr = params->coladdr;
114	111	int x;
r32352	r32353
116	113	for (x = params->heblnk; x < params->hsblnk; x += 2)
117	114	{
118	115	UINT16 pixels = vram[coladdr++ & 0xff];
119		dest[x + 0] = state->m_palette->pen(pixels & 0xff);
120		dest[x + 1] = state->m_palette->pen(pixels >> 8);
	116	dest[x + 0] = m_palette->pen(pixels & 0xff);
	117	dest[x + 1] = m_palette->pen(pixels >> 8);
121	118	}
122	119	}
123	120

trunk/src/mame/video/lethalj.c
r32352	r32353
178	178	*
179	179	*************************************/
180	180
181		~~void~~ lethalj_sca~~nline_upda~~te(sc~~reen_device &screen, bitm~~a~~p_i~~n~~d16 &bitmap, int scan~~line~~, const tms34010~~_~~dis~~pla~~y_params *params~~)
	181	TMS340X0_SCANLINE_IND16_CB_MEMBER(lethalj_state::scanline_update)
182	182	{
183		lethalj_state *state = screen.machine().driver_data<lethalj_state>();
184		UINT16 *src = &state->m_screenram[(state->m_vispage << 17) \| ((params->rowaddr << 9) & 0x3fe00)];
	183	UINT16 *src = &m_screenram[(m_vispage << 17) \| ((params->rowaddr << 9) & 0x3fe00)];
185	184	UINT16 *dest = &bitmap.pix16(scanline);
186	185	int coladdr = params->coladdr << 1;
187	186	int x;
188	187
189	188	/* blank palette: fill with white */
190		if (~~state->~~m_blank_palette)
	189	if (m_blank_palette)
191	190	{
192	191	for (x = params->heblnk; x < params->hsblnk; x++)
193	192	dest[x] = 0x7fff;
194	193	if (scanline == screen.visible_area().max_y)
195		~~state->~~m_blank_palette = 0;
	194	m_blank_palette = 0;
196	195	return;
197	196	}
198	197

trunk/src/mame/video/harddriv.c
r32352	r32353
97	97	*
98	98	*************************************/
99	99
100		~~void hdgsp~~_~~write~~_to_~~shiftreg~~(addr~~ess~~_space &sp~~ace, UINT32 add~~ress, UINT16 *shiftreg)
	100	TMS340X0_TO_SHIFTREG_CB_MEMBER(harddriv_state::hdgsp_write_to_shiftreg)
101	101	{
102		harddriv_state *state = space.machine().driver_data<harddriv_state>();
103
104	102	/* access to the 1bpp/2bpp area */
105	103	if (address >= 0x02000000 && address <= 0x020fffff)
106	104	{
107	105	address -= 0x02000000;
108		address >>= state->m_gsp_multisync;
109		address &= state->m_vram_mask;
110		address &= ~((512*8 >> state->m_gsp_multisync) - 1);
111		state->m_gsp_shiftreg_source = &state->m_gsp_vram[address];
	106	address >>= m_gsp_multisync;
	107	address &= m_vram_mask;
	108	address &= ~((512*8 >> m_gsp_multisync) - 1);
	109	m_gsp_shiftreg_source = &m_gsp_vram[address];
112	110	}
113	111
114	112	/* access to normal VRAM area */
r32352	r32353
116	114	{
117	115	address -= 0xff800000;
118	116	address /= 8;
119		address &= ~~state->~~m_vram_mask;
	117	address &= m_vram_mask;
120	118	address &= ~511;
121		~~state->~~m_gsp_shiftreg_source = &~~state->~~m_gsp_vram[address];
	119	m_gsp_shiftreg_source = &m_gsp_vram[address];
122	120	}
123	121	else
124	122	logerror("Unknown shiftreg write %08X\n", address);
125	123	}
126	124
127	125
128		~~void hdgsp~~_~~read~~_~~from~~_~~shiftreg~~(addr~~ess~~_space &space~~, UINT32~~ address, UINT16 *shiftreg)
	126	TMS340X0_FROM_SHIFTREG_CB_MEMBER(harddriv_state::hdgsp_read_from_shiftreg)
129	127	{
130		harddriv_state *state = space.machine().driver_data<harddriv_state>();
131
132		if (!state->m_shiftreg_enable)
	128	if (!m_shiftreg_enable)
133	129	return;
134	130
135	131	/* access to the 1bpp/2bpp area */
136	132	if (address >= 0x02000000 && address <= 0x020fffff)
137	133	{
138	134	address -= 0x02000000;
139		address >>= state->m_gsp_multisync;
140		address &= state->m_vram_mask;
141		address &= ~((512*8 >> state->m_gsp_multisync) - 1);
142		memmove(&state->m_gsp_vram[address], state->m_gsp_shiftreg_source, 512*8 >> state->m_gsp_multisync);
	135	address >>= m_gsp_multisync;
	136	address &= m_vram_mask;
	137	address &= ~((512*8 >> m_gsp_multisync) - 1);
	138	memmove(&m_gsp_vram[address], m_gsp_shiftreg_source, 512*8 >> m_gsp_multisync);
143	139	}
144	140
145	141	/* access to normal VRAM area */
r32352	r32353
147	143	{
148	144	address -= 0xff800000;
149	145	address /= 8;
150		address &= ~~state->~~m_vram_mask;
	146	address &= m_vram_mask;
151	147	address &= ~511;
152		memmove(&~~state->~~m_gsp_vram[address], ~~state->~~m_gsp_shiftreg_source, 512);
	148	memmove(&m_gsp_vram[address], m_gsp_shiftreg_source, 512);
153	149	}
154	150	else
155	151	logerror("Unknown shiftreg read %08X\n", address);
r32352	r32353
163	159	*
164	160	*************************************/
165	161
166		~~static~~ void update_palette_bank(~~running_machine &machine,~~ int newbank)
	162	void harddriv_state::update_palette_bank(int newbank)
167	163	{
168		harddriv_state *state = machine.driver_data<harddriv_state>();
169		machine.first_screen()->update_partial(machine.first_screen()->vpos());
170		state->m_gfx_palettebank = newbank;
	164	m_screen->update_partial(m_screen->vpos());
	165	m_gfx_palettebank = newbank;
171	166	}
172	167
173	168
r32352	r32353
233	228	break;
234	229
235	230	case 0x02:
236		update_palette_bank(~~space.machine(),~~ (m_gfx_palettebank & ~1) \| val);
	231	update_palette_bank((m_gfx_palettebank & ~1) \| val);
237	232	break;
238	233
239	234	case 0x03:
240		update_palette_bank(~~space.machine(),~~ (m_gfx_palettebank & ~2) \| (val << 1));
	235	update_palette_bank((m_gfx_palettebank & ~2) \| (val << 1));
241	236	break;
242	237
243	238	case 0x04:
244	239	if (m_palette->entries() >= 256 * 8)
245		update_palette_bank(~~space.machine(),~~ (m_gfx_palettebank & ~4) \| (val << 2));
	240	update_palette_bank((m_gfx_palettebank & ~4) \| (val << 2));
246	241	break;
247	242
248	243	case 0x07:
r32352	r32353
410	405	}
411	406
412	407
413		~~void~~ harddriv_s~~canline_driver(screen_device &screen, bi~~tma~~p_ind16 &bi~~t~~map, int~~ scanline~~, const tms34010~~_di~~splay_pa~~r~~ams *params~~)
	408	TMS340X0_SCANLINE_IND16_CB_MEMBER(harddriv_state::scanline_driver)
414	409	{
415		harddriv_state *state = screen.machine().driver_data<harddriv_state>();
416		UINT8 *vram_base = &state->m_gsp_vram[(params->rowaddr << 12) & state->m_vram_mask];
	410	UINT8 *vram_base = &m_gsp_vram[(params->rowaddr << 12) & m_vram_mask];
417	411	UINT16 *dest = &bitmap.pix16(scanline);
418		int coladdr = (params->yoffset << 9) + ((params->coladdr & 0xff) << 4) - 15 + (~~state->~~m_gfx_finescroll & 0x0f);
	412	int coladdr = (params->yoffset << 9) + ((params->coladdr & 0xff) << 4) - 15 + (m_gfx_finescroll & 0x0f);
419	413	int x;
420	414
421	415	for (x = params->heblnk; x < params->hsblnk; x++)
422		dest[x] = ~~state->~~m_gfx_palettebank * 256 + vram_base[BYTE_XOR_LE(coladdr++ & 0xfff)];
	416	dest[x] = m_gfx_palettebank * 256 + vram_base[BYTE_XOR_LE(coladdr++ & 0xfff)];
423	417
424	418	if (scanline == screen.visible_area().max_y)
425	419	display_speedups();
426	420	}
427	421
428	422
429		~~void~~ harddriv_scanline_multisync~~(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params~~)
	423	TMS340X0_SCANLINE_IND16_CB_MEMBER(harddriv_state::scanline_multisync)
430	424	{
431		harddriv_state *state = screen.machine().driver_data<harddriv_state>();
432		UINT8 *vram_base = &state->m_gsp_vram[(params->rowaddr << 11) & state->m_vram_mask];
	425	UINT8 *vram_base = &m_gsp_vram[(params->rowaddr << 11) & m_vram_mask];
433	426	UINT16 *dest = &bitmap.pix16(scanline);
434		int coladdr = (params->yoffset << 9) + ((params->coladdr & 0xff) << 3) - 7 + (~~state->~~m_gfx_finescroll & 0x07);
	427	int coladdr = (params->yoffset << 9) + ((params->coladdr & 0xff) << 3) - 7 + (m_gfx_finescroll & 0x07);
435	428	int x;
436	429
437	430	for (x = params->heblnk; x < params->hsblnk; x++)
438		dest[x] = ~~state->~~m_gfx_palettebank * 256 + vram_base[BYTE_XOR_LE(coladdr++ & 0x7ff)];
	431	dest[x] = m_gfx_palettebank * 256 + vram_base[BYTE_XOR_LE(coladdr++ & 0x7ff)];
439	432
440	433	if (scanline == screen.visible_area().max_y)
441	434	display_speedups();

trunk/src/mame/video/exterm.c
r32352	r32353
32	32	*
33	33	*************************************/
34	34
35		~~void~~ exterm_to_shiftreg_master~~(address_space &space, UINT32 address, UINT16 *shiftreg~~)
	35	TMS340X0_TO_SHIFTREG_CB_MEMBER(exterm_state::to_shiftreg_master)
36	36	{
37		exterm_state *state = space.machine().driver_data<exterm_state>();
38		memcpy(shiftreg, &state->m_master_videoram[TOWORD(address)], 256 * sizeof(UINT16));
	37	memcpy(shiftreg, &m_master_videoram[TOWORD(address)], 256 * sizeof(UINT16));
39	38	}
40	39
41	40
42		~~void~~ exterm_from_shiftreg_master~~(address_space &space, UINT32 address, UINT16 *shiftreg~~)
	41	TMS340X0_FROM_SHIFTREG_CB_MEMBER(exterm_state::from_shiftreg_master)
43	42	{
44		exterm_state *state = space.machine().driver_data<exterm_state>();
45		memcpy(&state->m_master_videoram[TOWORD(address)], shiftreg, 256 * sizeof(UINT16));
	43	memcpy(&m_master_videoram[TOWORD(address)], shiftreg, 256 * sizeof(UINT16));
46	44	}
47	45
48	46
49		~~void~~ exterm_to_shiftreg_slave~~(address_space &space, UINT32 address, UINT16 *shiftreg~~)
	47	TMS340X0_TO_SHIFTREG_CB_MEMBER(exterm_state::to_shiftreg_slave)
50	48	{
51		exterm_state *state = space.machine().driver_data<exterm_state>();
52		memcpy(shiftreg, &state->m_slave_videoram[TOWORD(address)], 256 * 2 * sizeof(UINT8));
	49	memcpy(shiftreg, &m_slave_videoram[TOWORD(address)], 256 * 2 * sizeof(UINT8));
53	50	}
54	51
55	52
56		~~void~~ exterm_from_shiftreg_slave~~(address_space &space, UINT32 address, UINT16 *shiftreg~~)
	53	TMS340X0_FROM_SHIFTREG_CB_MEMBER(exterm_state::from_shiftreg_slave)
57	54	{
58		exterm_state *state = space.machine().driver_data<exterm_state>();
59		memcpy(&state->m_slave_videoram[TOWORD(address)], shiftreg, 256 * 2 * sizeof(UINT8));
	55	memcpy(&m_slave_videoram[TOWORD(address)], shiftreg, 256 * 2 * sizeof(UINT8));
60	56	}
61	57
62	58
r32352	r32353
67	63	*
68	64	*************************************/
69	65
70		~~void~~ exterm_sca~~nline_upda~~te(sc~~reen_device &screen, bitm~~a~~p_i~~n~~d16 &bitmap, int scan~~line~~, const tms34010~~_~~dis~~pla~~y_params *params~~)
	66	TMS340X0_SCANLINE_IND16_CB_MEMBER(exterm_state::scanline_update)
71	67	{
72		exterm_state *state = screen.machine().driver_data<exterm_state>();
73		UINT16 *bgsrc = &state->m_master_videoram[(params->rowaddr << 8) & 0xff00];
	68	UINT16 *bgsrc = &m_master_videoram[(params->rowaddr << 8) & 0xff00];
74	69	UINT16 *fgsrc = NULL;
75	70	UINT16 *dest = &bitmap.pix16(scanline);
76	71	tms34010_display_params fgparams;
r32352	r32353
79	74	int x;
80	75
81	76	/* get parameters for the slave CPU */
82		~~state->~~m_slave->get_display_params(&fgparams);
	77	m_slave->get_display_params(&fgparams);
83	78
84	79	/* compute info about the slave vram */
85	80	if (fgparams.enabled && scanline >= fgparams.veblnk && scanline < fgparams.vsblnk && fgparams.heblnk < fgparams.hsblnk)
86	81	{
87		fgsrc = &~~state->~~m_slave_videoram[((fgparams.rowaddr << 8) + (fgparams.yoffset << 7)) & 0xff80];
	82	fgsrc = &m_slave_videoram[((fgparams.rowaddr << 8) + (fgparams.yoffset << 7)) & 0xff80];
88	83	fgcoladdr = (fgparams.coladdr >> 1);
89	84	}
90	85

trunk/src/mame/video/midyunit.c
r32352	r32353
171	171	*
172	172	*************************************/
173	173
174		~~void~~ midyunit_~~to_~~s~~hif~~t~~reg(~~a~~ddr~~ess_space &space, UINT32 address, UINT16 *shiftreg)
	174	TMS340X0_TO_SHIFTREG_CB_MEMBER(midyunit_state::to_shiftreg)
175	175	{
176		midyunit_state *state = space.machine().driver_data<midyunit_state>();
177		memcpy(shiftreg, &state->m_local_videoram[address >> 3], 2 * 512 * sizeof(UINT16));
	176	memcpy(shiftreg, &m_local_videoram[address >> 3], 2 * 512 * sizeof(UINT16));
178	177	}
179	178
180	179
181		~~void~~ midyunit_~~from_~~s~~hif~~t~~reg(~~a~~ddr~~e~~ss_space &space, UINT32 add~~ress, UINT16 *shiftreg)
	180	TMS340X0_FROM_SHIFTREG_CB_MEMBER(midyunit_state::from_shiftreg)
182	181	{
183		midyunit_state *state = space.machine().driver_data<midyunit_state>();
184		memcpy(&state->m_local_videoram[address >> 3], shiftreg, 2 * 512 * sizeof(UINT16));
	182	memcpy(&m_local_videoram[address >> 3], shiftreg, 2 * 512 * sizeof(UINT16));
185	183	}
186	184
187	185
r32352	r32353
552	550	}
553	551
554	552
555		~~void~~ midyunit_sca~~nline_upda~~te(sc~~reen_device &screen, bitm~~a~~p_i~~n~~d16 &bitmap, int scan~~line~~, const tms34010~~_~~dis~~pla~~y_params *params~~)
	553	TMS340X0_SCANLINE_IND16_CB_MEMBER(midyunit_state::scanline_update)
556	554	{
557		midyunit_state *state = screen.machine().driver_data<midyunit_state>();
558		UINT16 *src = &state->m_local_videoram[(params->rowaddr << 9) & 0x3fe00];
	555	UINT16 *src = &m_local_videoram[(params->rowaddr << 9) & 0x3fe00];
559	556	UINT16 *dest = &bitmap.pix16(scanline);
560	557	int coladdr = params->coladdr << 1;
561	558	int x;
562	559
563	560	/* adjust the display address to account for ignored bits */
564	561	for (x = params->heblnk; x < params->hsblnk; x++)
565		dest[x] = ~~state->~~m_pen_map[src[coladdr++ & 0x1ff]];
	562	dest[x] = m_pen_map[src[coladdr++ & 0x1ff]];
566	563
567	564	/* handle autoerase on the previous line */
568		~~state->~~autoerase_line(NULL, params->rowaddr - 1);
	565	autoerase_line(NULL, params->rowaddr - 1);
569	566
570	567	/* if this is the last update of the screen, set a timer to clear out the final line */
571	568	/* (since we update one behind) */
572	569	if (scanline == screen.visible_area().max_y)
573		~~state->~~timer_set(screen.time_until_pos(scanline + 1), midyunit_state::TIMER_AUTOERASE_LINE, params->rowaddr);
	570	timer_set(screen.time_until_pos(scanline + 1), midyunit_state::TIMER_AUTOERASE_LINE, params->rowaddr);
574	571	}

trunk/src/mame/video/artmagic.c
r32352	r32353
59	59	*
60	60	*************************************/
61	61
62		~~void~~ artmagic_to_shiftreg~~(address_space &space, offs_t address, UINT16 *data~~)
	62	TMS340X0_TO_SHIFTREG_CB_MEMBER(artmagic_state::to_shiftreg)
63	63	{
64		artmagic_state *state = space.machine().driver_data<artmagic_state>();
65		UINT16 *vram = state->address_to_vram(&address);
	64	UINT16 *vram = address_to_vram(&address);
66	65	if (vram)
67		memcpy(data, &vram[address], TOBYTE(0x2000));
	66	memcpy(shiftreg, &vram[address], TOBYTE(0x2000));
68	67	}
69	68
70	69
71		~~void~~ artmagic_from_shiftreg~~(address_space &space, offs_t address, UINT16 *data~~)
	70	TMS340X0_FROM_SHIFTREG_CB_MEMBER(artmagic_state::from_shiftreg)
72	71	{
73		artmagic_state *state = space.machine().driver_data<artmagic_state>();
74		UINT16 *vram = state->address_to_vram(&address);
	72	UINT16 *vram = address_to_vram(&address);
75	73	if (vram)
76		memcpy(&vram[address], data, TOBYTE(0x2000));
	74	memcpy(&vram[address], shiftreg, TOBYTE(0x2000));
77	75	}
78	76
79	77
r32352	r32353
336	334	*
337	335	*************************************/
338	336
339		~~void~~ artmagic_s~~canline(screen_device &screen, bi~~tma~~p_rgb32 &bi~~t~~map, int~~ scanline~~, const tms34010_display_params *params~~)
	337	TMS340X0_SCANLINE_RGB32_CB_MEMBER(artmagic_state::scanline)
340	338	{
341		artmagic_state *state = screen.machine().driver_data<artmagic_state>();
342	339	offs_t offset = (params->rowaddr << 12) & 0x7ff000;
343		UINT16 *vram = ~~state->~~address_to_vram(&offset);
	340	UINT16 *vram = address_to_vram(&offset);
344	341	UINT32 *dest = &bitmap.pix32(scanline);
345		const rgb_t *pens = ~~state->~~m_tlc34076->get_pens();
	342	const rgb_t *pens = m_tlc34076->get_pens();
346	343	int coladdr = params->coladdr << 1;
347	344	int x;
348	345

trunk/src/mame/video/midtunit.c
r32352	r32353
41	41
42	42
43	43	/* graphics-related variables */
44		UINT8 midtunit_gfx_rom_large;
45	44	static UINT16 midtunit_control;
46	45
47	46	/* videoram-related variables */
r32352	r32353
111	110	VIDEO_START_MEMBER(midwunit_state,midwunit)
112	111	{
113	112	VIDEO_START_CALL_MEMBER(midtunit);
114		m~~idtunit~~_gfx_rom_large = 1;
	113	m_gfx_rom_large = 1;
115	114	}
116	115
117	116
118	117	VIDEO_START_MEMBER(midxunit_state,midxunit)
119	118	{
120	119	VIDEO_START_CALL_MEMBER(midtunit);
121		m~~idtunit~~_gfx_rom_large = 1;
	120	m_gfx_rom_large = 1;
122	121	videobank_select = 1;
123	122	}
124	123
r32352	r32353
224	223	*
225	224	*************************************/
226	225
227		~~void~~ midtunit_~~to_~~s~~hif~~t~~reg(~~a~~ddr~~ess_space &space, UINT32 address, UINT16 *shiftreg)
	226	TMS340X0_TO_SHIFTREG_CB_MEMBER(midtunit_state::to_shiftreg)
228	227	{
229	228	memcpy(shiftreg, &local_videoram[address >> 3], 2 * 512 * sizeof(UINT16));
230	229	}
231	230
232	231
233		~~void~~ midtunit_~~from_~~s~~hif~~t~~reg(~~a~~ddr~~e~~ss_space &space, UINT32 add~~ress, UINT16 *shiftreg)
	232	TMS340X0_FROM_SHIFTREG_CB_MEMBER(midtunit_state::from_shiftreg)
234	233	{
235	234	memcpy(&local_videoram[address >> 3], shiftreg, 2 * 512 * sizeof(UINT16));
236	235	}
r32352	r32353
254	253	COMBINE_DATA(&midtunit_control);
255	254
256	255	/* gfx bank select is bit 7 */
257		if (!(midtunit_control & 0x0080) \|\| !m~~idtunit~~_gfx_rom_large)
	256	if (!(midtunit_control & 0x0080) \|\| !m_gfx_rom_large)
258	257	gfxbank_offset[0] = 0x000000;
259	258	else
260	259	gfxbank_offset[0] = 0x800000;
r32352	r32353
745	744	gfxoffset = 0;
746	745
747	746	/* determine the location */
748		if (!m~~idtunit~~_gfx_rom_large && gfxoffset >= 0x2000000)
	747	if (!m_gfx_rom_large && gfxoffset >= 0x2000000)
749	748	gfxoffset -= 0x2000000;
750	749	if (gfxoffset >= 0xf8000000)
751	750	gfxoffset -= 0xf8000000;
r32352	r32353
811	810	*
812	811	*************************************/
813	812
814		~~void~~ midtunit_sca~~nline_upda~~te(sc~~reen_device &screen, bitm~~a~~p_i~~n~~d16 &bitmap, int scan~~line~~, const tms34010~~_~~dis~~pla~~y_params *params~~)
	813	TMS340X0_SCANLINE_IND16_CB_MEMBER(midtunit_state::scanline_update)
815	814	{
816	815	UINT16 *src = &local_videoram[(params->rowaddr << 9) & 0x3fe00];
817	816	UINT16 *dest = &bitmap.pix16(scanline);
r32352	r32353
823	822	dest[x] = src[coladdr++ & 0x1ff] & 0x7fff;
824	823	}
825	824
826		~~void~~ midxunit_sca~~nline_upda~~te(sc~~reen_device &screen, bitm~~a~~p_i~~n~~d16 &bitmap, int scan~~line~~, const tms34010~~_~~dis~~pla~~y_params *params~~)
	825	TMS340X0_SCANLINE_IND16_CB_MEMBER(midxunit_state::scanline_update)
827	826	{
828	827	UINT32 fulladdr = ((params->rowaddr << 16) \| params->coladdr) >> 3;
829	828	UINT16 *src = &local_videoram[fulladdr & 0x3fe00];

trunk/src/mame/video/micro3d.c
r32352	r32353
60	60	*
61	61	*************************************/
62	62
63		~~void~~ micro3d_sca~~nline_upda~~te(sc~~reen_device &screen, bitm~~a~~p_i~~n~~d16 &bitmap, int scan~~line~~, const tms34010~~_~~dis~~pla~~y_params *params~~)
	63	TMS340X0_SCANLINE_IND16_CB_MEMBER(micro3d_state::scanline_update)
64	64	{
65		micro3d_state *state = screen.machine().driver_data<micro3d_state>();
66
67		UINT16 *src = &state->m_micro3d_sprite_vram[(params->rowaddr << 8) & 0x7fe00];
	65	UINT16 *src = &m_micro3d_sprite_vram[(params->rowaddr << 8) & 0x7fe00];
68	66	UINT16 *dest = &bitmap.pix16(scanline);
69	67	int coladdr = params->coladdr;
70		int sd_11_7 = (~~state->~~m_creg & 0x1f) << 7;
	68	int sd_11_7 = (m_creg & 0x1f) << 7;
71	69	int x;
72	70
73	71	UINT16 *frame_src;
74	72
75	73	scanline = MAX((scanline - params->veblnk), 0);
76		frame_src = ~~state->~~m_frame_buffers[~~state->~~m_display_buffer] + (scanline << 10);
	74	frame_src = m_frame_buffers[m_display_buffer] + (scanline << 10);
77	75
78	76	/* TODO: XFER3DK - X/Y offsets for 3D */
79	77
r32352	r32353
125	123	m_xfer3dk = data;
126	124	}
127	125
128		~~void~~ micro3d_tms_interrupt~~(device_t *device, int state~~)
	126	WRITE_LINE_MEMBER(micro3d_state::tms_interrupt)
129	127	{
130	128	// mc68901_int_gen(device->machine(), GPIP4);
131	129	}

trunk/src/emu/cpu/tms34010/34010gfx.c
r32352	r32353
215	215
216	216	void tms340x0_device::shiftreg_w(address_space &space, offs_t offset,UINT16 data)
217	217	{
218		if (m_config->from_shiftreg)
219		(*m_config->from_shiftreg)(space, (UINT32)(offset << 3) & ~15, &m_shiftreg[0]);
	218	if (!m_from_shiftreg_cb.isnull())
	219	m_from_shiftreg_cb(space, (UINT32)(offset << 3) & ~15, &m_shiftreg[0]);
220	220	else
221	221	logerror("From ShiftReg function not set. PC = %08X\n", m_pc);
222	222	}
223	223
224	224	UINT16 tms340x0_device::shiftreg_r(address_space &space, offs_t offset)
225	225	{
226		if (m_config->to_shiftreg)
227		(*m_config->to_shiftreg)(space, (UINT32)(offset << 3) & ~15, &m_shiftreg[0]);
	226	if (!m_to_shiftreg_cb.isnull())
	227	m_to_shiftreg_cb(space, (UINT32)(offset << 3) & ~15, &m_shiftreg[0]);
228	228	else
229	229	logerror("To ShiftReg function not set. PC = %08X\n", m_pc);
230	230	return m_shiftreg[0];

trunk/src/emu/cpu/tms34010/tms34010.h
r32352	r32353
188	188	};
189	189
190	190
191		struct tms340x0_config
192		{
193		UINT8 halt_on_reset; /* /HCS pin, which determines HALT state after reset */
194		const char screen_tag; / the screen operated on */
195		UINT32 pixclock; /* the pixel clock (0 means don't adjust screen size) */
196		int pixperclock; /* pixels per clock */
197		void (scanline_callback_ind16)(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params params);
198		void (scanline_callback_rgb32)(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params params);
199		void (output_int)(device_t device, int state); /* output interrupt callback */
200		void (to_shiftreg)(address_space &space, offs_t, UINT16 ); /* shift register write */
201		void (from_shiftreg)(address_space &space, offs_t, UINT16 ); /* shift register read */
202		};
	191	#define MCFG_TMS340X0_HALT_ON_RESET(_value) \
	192	tms340x0_device::set_halt_on_reset(*device, _value);
	193
	194	#define MCFG_TMS340X0_PIXEL_CLOCK(_value) \
	195	tms340x0_device::set_pixel_clock(*device, _value);
	196
	197	#define MCFG_TMS340X0_PIXELS_PER_CLOCK(_value) \
	198	tms340x0_device::set_pixels_per_clock(*device, _value);
	199
	200	typedef device_delegate<void (screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params)> scanline_ind16_cb_delegate;
203	201
	202	#define TMS340X0_SCANLINE_IND16_CB_MEMBER(_name) void _name(screen_device &screen, bitmap_ind16 &bitmap, int scanline, const tms34010_display_params *params)
	203
	204	#define MCFG_TMS340X0_SCANLINE_IND16_CB(_class, _method) \
	205	tms340x0_device::set_scanline_ind16_callback(device, scanline_ind16_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class >(owner)));
	206
204	207
205		#define MCFG_TMS340X0_CONFIG(_config) \
206		tms340x0_device::set_tms340x0_config(*device, &_config);
	208	typedef device_delegate<void (screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params)> scanline_rgb32_cb_delegate;
207	209
	210	#define TMS340X0_SCANLINE_RGB32_CB_MEMBER(_name) void _name(screen_device &screen, bitmap_rgb32 &bitmap, int scanline, const tms34010_display_params *params)
208	211
209		class tms340x0_device : public cpu_device
	212	#define MCFG_TMS340X0_SCANLINE_RGB32_CB(_class, _method) \
	213	tms340x0_device::set_scanline_rgb32_callback(device, scanline_rgb32_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class >(owner)));
	214
	215
	216	#define MCFG_TMS340X0_OUTPUT_INT_CB(_devcb) \
	217	devcb = &tms340x0_device::set_output_int_callback(*device, DEVCB_##_devcb);
	218
	219
	220	typedef device_delegate<void (address_space &space, offs_t address, UINT16 *shiftreg)> to_shiftreg_cb_delegate;
	221
	222	#define TMS340X0_TO_SHIFTREG_CB_MEMBER(_name) void _name(address_space &space, offs_t address, UINT16 *shiftreg)
	223
	224	#define MCFG_TMS340X0_TO_SHIFTREG_CB(_class, _method) \
	225	tms340x0_device::set_to_shiftreg_callback(device, to_shiftreg_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class >(owner)));
	226
	227
	228	typedef device_delegate<void (address_space &space, offs_t address, UINT16 *shiftreg)> from_shiftreg_cb_delegate;
	229
	230	#define TMS340X0_FROM_SHIFTREG_CB_MEMBER(_name) void _name(address_space &space, offs_t address, UINT16 *shiftreg)
	231
	232	#define MCFG_TMS340X0_FROM_SHIFTREG_CB(_class, _method) \
	233	tms340x0_device::set_from_shiftreg_callback(device, from_shiftreg_cb_delegate(&_class::_method, #_class "::" #_method, downcast<_class >(owner)));
	234
	235
	236	class tms340x0_device : public cpu_device,
	237	public device_video_interface
210	238	{
211	239	public:
212	240	// construction/destruction
213	241	tms340x0_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname);
214	242
215		static void set_tms340x0_config(device_t &device, const tms340x0_config *config) { downcast<tms340x0_device &>(device).m_config = config; }
	243	static void set_halt_on_reset(device_t &device, bool reset_deferred) { downcast<tms340x0_device &>(device).m_reset_deferred = reset_deferred; }
	244	static void set_pixel_clock(device_t &device, UINT32 pixclock) { downcast<tms340x0_device &>(device).m_pixclock = pixclock; }
	245	static void set_pixels_per_clock(device_t &device, int pixperclock) { downcast<tms340x0_device &>(device).m_pixperclock = pixperclock; }
	246	static void set_scanline_ind16_callback(device_t &device, scanline_ind16_cb_delegate callback) { downcast<tms340x0_device &>(device).m_scanline_ind16_cb = callback; }
	247	static void set_scanline_rgb32_callback(device_t &device, scanline_rgb32_cb_delegate callback) { downcast<tms340x0_device &>(device).m_scanline_rgb32_cb = callback; }
	248	template<class _Object> static devcb_base &set_output_int_callback(device_t &device, _Object object) { return downcast<tms340x0_device &>(device).m_output_int_cb.set_callback(object); }
	249	static void set_to_shiftreg_callback(device_t &device, to_shiftreg_cb_delegate callback) { downcast<tms340x0_device &>(device).m_to_shiftreg_cb = callback; }
	250	static void set_from_shiftreg_callback(device_t &device, from_shiftreg_cb_delegate callback) { downcast<tms340x0_device &>(device).m_from_shiftreg_cb = callback; }
216	251
217	252	void get_display_params(tms34010_display_params *params);
218	253	void tms34010_state_postload();
r32352	r32353
292	327	INT32 m_gfxcycles;
293	328	UINT8 m_pixelshift;
294	329	UINT8 m_is_34020;
295		~~UINT8~~ m_reset_deferred;
	330	bool m_reset_deferred; /* /HCS pin, which determines HALT state after reset */
296	331	UINT8 m_hblank_stable;
297	332	UINT8 m_external_host_access;
298	333	UINT8 m_executing;
299	334	address_space *m_program;
300	335	direct_read_data *m_direct;
301		const tms340x0_config *m_config;
302		screen_device *m_screen;
	336	UINT32 m_pixclock; /* the pixel clock (0 means don't adjust screen size) */
	337	int m_pixperclock; /* pixels per clock */
303	338	emu_timer *m_scantimer;
304	339	int m_icount;
	340
	341	scanline_ind16_cb_delegate m_scanline_ind16_cb;
	342	scanline_rgb32_cb_delegate m_scanline_rgb32_cb;
	343	devcb_write_line m_output_int_cb; /* output interrupt callback */
	344	to_shiftreg_cb_delegate m_to_shiftreg_cb; /* shift register write */
	345	from_shiftreg_cb_delegate m_from_shiftreg_cb; /* shift register read */
305	346
306	347	struct XY
307	348	{

trunk/src/emu/cpu/tms34010/tms34010.c
r32352	r32353
31	31	GLOBAL VARIABLES
32	32	***************************************************************************/
33	33
34		/* default configuration */
35		static const tms340x0_config default_config =
36		{
37		0
38		};
39
40
41	34	tms340x0_device::tms340x0_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, const char shortname)
42	35	: cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__)
	36	, device_video_interface(mconfig, *this)
43	37	, m_program_config("program", ENDIANNESS_LITTLE, 16, 32, 3)
44		, m_config(&default_config)
	38	, m_reset_deferred(FALSE)
	39	, m_pixclock(0)
	40	, m_pixperclock(0)
	41	, m_output_int_cb(*this)
45	42	{
46	43	}
47	44
r32352	r32353
271	268	/* Shift register read */
272	269	UINT32 tms340x0_device::read_pixel_shiftreg(offs_t offset)
273	270	{
274		if (m_config->to_shiftreg)
275		m_config->to_shiftreg(*m_program, offset, &m_shiftreg[0]);
	271	if (!m_to_shiftreg_cb.isnull())
	272	m_to_shiftreg_cb(*m_program, offset, &m_shiftreg[0]);
276	273	else
277	274	fatalerror("To ShiftReg function not set. PC = %08X\n", m_pc);
278	275	return m_shiftreg[0];
r32352	r32353
413	410	/* Shift register write */
414	411	void tms340x0_device::write_pixel_shiftreg(offs_t offset, UINT32 data)
415	412	{
416		if (m_config->from_shiftreg)
417		m_config->from_shiftreg(*m_program, offset, &m_shiftreg[0]);
	413	if (!m_from_shiftreg_cb.isnull())
	414	m_from_shiftreg_cb(*m_program, offset, &m_shiftreg[0]);
418	415	else
419	416	fatalerror("From ShiftReg function not set. PC = %08X\n", m_pc);
420	417	}
r32352	r32353
572	569
573	570	void tms340x0_device::device_start()
574	571	{
	572	m_scanline_ind16_cb.bind_relative_to(*owner());
	573	m_scanline_rgb32_cb.bind_relative_to(*owner());
	574	m_output_int_cb.resolve();
	575	m_to_shiftreg_cb.bind_relative_to(*owner());
	576	m_from_shiftreg_cb.bind_relative_to(*owner());
	577
575	578	m_external_host_access = FALSE;
576	579
577	580	m_program = &space(AS_PROGRAM);
578	581	m_direct = &m_program->direct();
579		m_screen = downcast<screen_device *>(machine().device(m_config->screen_tag));
580	582
581	583	/* set up the state table */
582	584	{
r32352	r32353
646	648
647	649	/* HALT the CPU if requested, and remember to re-read the starting PC */
648	650	/* the first time we are run */
649		m_reset_deferred = m_config->halt_on_reset;
650		if (m_config->halt_on_reset)
	651	if (m_reset_deferred)
651	652	{
652	653	io_register_w(*m_program, REG_HSTCTLH, 0x8000, 0xffff);
653	654	}
r32352	r32353
883	884	{
884	885	/* only do this if we have an incoming pixel clock */
885	886	/* also, only do it if the HEBLNK/HSBLNK values are stable */
886		if (master && (m_~~config->~~scanline_~~callback_~~ind16 ~~!= NULL~~ \|\| m_~~config->~~scanline_~~callback_~~rgb32 ~~!= NULL~~))
	887	if (master && (!m_scanline_ind16_cb.isnull() \|\| !m_scanline_rgb32_cb.isnull()))
887	888	{
888	889	int htotal = SMART_IOREG(HTOTAL);
889	890	if (htotal > 0 && vtotal > 0)
890	891	{
891		attoseconds_t refresh = HZ_TO_ATTOSECONDS(m_config->pixclock) * (htotal + 1) * (vtotal + 1);
892		int width = (htotal + 1) * m_config->pixperclock;
	892	attoseconds_t refresh = HZ_TO_ATTOSECONDS(m_pixclock) * (htotal + 1) * (vtotal + 1);
	893	int width = (htotal + 1) * m_pixperclock;
893	894	int height = vtotal + 1;
894	895	rectangle visarea;
895	896
896	897	/* extract the visible area */
897		visarea.min_x = SMART_IOREG(HEBLNK) * m_config->pixperclock;
898		visarea.max_x = SMART_IOREG(HSBLNK) * m_config->pixperclock - 1;
	898	visarea.min_x = SMART_IOREG(HEBLNK) * m_pixperclock;
	899	visarea.max_x = SMART_IOREG(HSBLNK) * m_pixperclock - 1;
899	900	visarea.min_y = veblnk;
900	901	visarea.max_y = vsblnk - 1;
901	902
r32352	r32353
927	928	}
928	929
929	930	/* force a partial update within the visible area */
930		if (vcount >= current_visarea.min_y && vcount <= current_visarea.max_y && (m_~~config->~~scanline_~~callback_~~ind16 ~~!= NULL~~ \|\| m_~~config->~~scanline_~~callback_~~rgb32 ~~!= NULL~~))
	931	if (vcount >= current_visarea.min_y && vcount <= current_visarea.max_y && (!m_scanline_ind16_cb.isnull() \|\| !m_scanline_rgb32_cb.isnull()))
931	932	m_screen->update_partial(vcount);
932	933
933	934	/* if we are in the visible area, increment DPYADR by DUDATE */
r32352	r32353
974	975	params->vcount = SMART_IOREG(VCOUNT);
975	976	params->veblnk = SMART_IOREG(VEBLNK);
976	977	params->vsblnk = SMART_IOREG(VSBLNK);
977		params->heblnk = SMART_IOREG(HEBLNK) * m_config->pixperclock;
978		params->hsblnk = SMART_IOREG(HSBLNK) * m_config->pixperclock;
	978	params->heblnk = SMART_IOREG(HEBLNK) * m_pixperclock;
	979	params->hsblnk = SMART_IOREG(HSBLNK) * m_pixperclock;
979	980
980	981	/* 34010 gets its address from DPYADR and DPYTAP */
981	982	if (!m_is_34020)
r32352	r32353
1013	1014	{
1014	1015	/* call through to the callback */
1015	1016	LOG((" Update: scan=%3d ROW=%04X COL=%04X\n", cliprect.min_y, params.rowaddr, params.coladdr));
1016		(*m_~~config->~~scanline_~~callback_~~ind16)(screen, bitmap, cliprect.min_y, &params);
	1017	m_scanline_ind16_cb(screen, bitmap, cliprect.min_y, &params);
1017	1018	}
1018	1019
1019	1020	/* otherwise, just blank the current scanline */
r32352	r32353
1044	1045	{
1045	1046	/* call through to the callback */
1046	1047	LOG((" Update: scan=%3d ROW=%04X COL=%04X\n", cliprect.min_y, params.rowaddr, params.coladdr));
1047		(*m_~~config->~~scanline_~~callback_~~rgb32)(screen, bitmap, cliprect.min_y, &params);
	1048	m_scanline_rgb32_cb(screen, bitmap, cliprect.min_y, &params);
1048	1049	}
1049	1050
1050	1051	/* otherwise, just blank the current scanline */
r32352	r32353
1155	1156	/* the TMS34010 can set output interrupt? */
1156	1157	if (!(oldreg & 0x0080) && (newreg & 0x0080))
1157	1158	{
1158		if (m_config->output_int)
1159		(*m_config->output_int)(&space.device(), 1);
	1159	if (!m_output_int_cb.isnull())
	1160	m_output_int_cb(1);
1160	1161	}
1161	1162	else if ((oldreg & 0x0080) && !(newreg & 0x0080))
1162	1163	{
1163		if (m_config->output_int)
1164		(*m_config->output_int)(&space.device(), 0);
	1164	if (!m_output_int_cb.isnull())
	1165	m_output_int_cb(0);
1165	1166	}
1166	1167
1167	1168	/* input interrupt? (should really be state-based, but the functions don't exist!) */
r32352	r32353
1308	1309	/* the TMS34010 can set output interrupt? */
1309	1310	if (!(oldreg & 0x0080) && (newreg & 0x0080))
1310	1311	{
1311		if (m_config->output_int)
1312		(*m_config->output_int)(&space.device(), 1);
	1312	if (!m_output_int_cb.isnull())
	1313	m_output_int_cb(1);
1313	1314	}
1314	1315	else if ((oldreg & 0x0080) && !(newreg & 0x0080))
1315	1316	{
1316		if (m_config->output_int)
1317		(*m_config->output_int)(&space.device(), 0);
	1317	if (!m_output_int_cb.isnull())
	1318	m_output_int_cb(0);
1318	1319	}
1319	1320
1320	1321	/* input interrupt? (should really be state-based, but the functions don't exist!) */

199869 Revisions