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r32283 Monday 22nd September, 2014 at 14:21:32 UTC by Michael Zapf
(MESS) HDC9234 WIP: formatting floppy disks working; some HFDC fixes. (nw)

[src/emu/bus/ti99_peb]	hfdc.c
[src/emu/machine]	hdc9234.c hdc9234.h

trunk/src/emu/machine/hdc9234.c

r32282	r32283
23	23	#include "emu.h"
24	24	#include "hdc9234.h"
25	25
26		#define TRACE_REG 0
27		#define TRACE_ACT 0
	26	// Per-command debugging
	27	#define TRACE_SELECT 0
	28	#define TRACE_STEP 0
	29	#define TRACE_RESTORE 0
	30	#define TRACE_SUBSTATES 0
	31	#define TRACE_READ 0
	32	#define TRACE_WRITE 0
	33	#define TRACE_READREG 0
	34	#define TRACE_SETREG 0
	35	#define TRACE_SETPTR 0
	36	#define TRACE_FORMAT 0
	37
	38	// Common states
	39	#define TRACE_READID 0
	40	#define TRACE_VERIFY 0
	41	#define TRACE_TRANSFER 0
	42
	43	// Live states debugging
	44	#define TRACE_LIVE 0
28	45	#define TRACE_SHIFT 0
29		#define TRACE_LIVE 0
30		#define TRACE_RWSEC 0
	46	#define TRACE_SYNC 0
	47
	48	// Misc debugging
	49	#define TRACE_DELAY 0
	50	#define TRACE_INT 0
31	51	#define TRACE_LINES 0
32		#define TRACE_AUXBUS 0
33		#define TRACE_COMMAND 0
34		#define TRACE_DELAY 0
35		#define TRACE_WRITE 0
36	52	#define TRACE_INDEX 0
37		#define TRACE_INT 0
38		#define TRACE_SETREG 0
	53	#define TRACE_DMA 0
39	54	#define TRACE_DONE 0
40		#define TRACE_VERIFY 0
	55	#define TRACE_FAIL 0
	56	#define TRACE_AUXBUS 0
41	57
	58	#define TRACE_DETAIL 0
	59
42	60	#define UNRELIABLE_MEDIA 0
43	61
	62	// Not implemented:
	63	// Poll drives
	64	// Seek/Read ID
	65	// Read track
	66	// Write long (variant of the write operation, selectable by MODE register)
	67	// Tape operations
	68
44	69	// Untested:
45		// Multi-sector read
	70	// Multi-sector read/write
46	71	// Seek complete
47		// read sectors physical
	72	// Read/write sectors physical
48	73
	74	// TDF
	75
49	76	/*
50	77	Register names of the HDC. The left part is the set of write registers,
51	78	while the right part are the read registers.
r32282	r32283
277	304	RESTORE_CHECK2,
278	305	SEEK_COMPLETE,
279	306	HEAD_DELAY,
	307	WAITINDEX0,
	308	WAITINDEX1,
	309	TRACKSTART,
	310	TRACKDONE,
280	311
281	312	READ_ID = 0x40,
282	313	READ_ID1,
r32282	r32283
307	338	WRITE_SEC_SKIP_GAP2,
308	339	WRITE_SEC_SKIP_GAP2_LOOP,
309	340	WRITE_SEC_BYTE,
310		WRITE_SEC_NEXT_BYTE
	341	WRITE_SEC_NEXT_BYTE,
	342
	343	WRITE_TRACK_BYTE,
	344	WRITE_TRACK_NEXT_BYTE,
	345
	346	READ_TRACK_BYTE,
	347	READ_TRACK_NEXT_BYTE,
	348
	349	FORMAT_TRACK,
	350	WRITE_GAP0,
	351	WRITE_GAP1,
	352	WRITE_GAP2,
	353	WRITE_GAP3,
	354	WRITE_GAP4,
	355	WRITE_IXAM_SYNC,
	356	WRITE_IXAM,
	357	WRITE_FC,
	358	WRITE_IDAM_SYNC,
	359	WRITE_IDAM,
	360	WRITE_HEADER,
	361	WRITE_IDENT,
	362
	363	WRITE_DAM_SYNC,
	364	WRITE_A1,
	365	WRITE_DATAMARK,
	366	WRITE_SECDATA,
	367	WRITE_DATA_CRC,
	368	WRITE_DONE,
	369	WRITE_HEADER_CRC,
	370
	371	NO_DMA_ACK
311	372	};
312	373
313	374	/*
	375	Event lines
	376	*/
	377	enum
	378	{
	379	INDEX_LINE = 1,
	380	READY_LINE,
	381	SEEKCOMP_LINE
	382	};
	383
	384	/*
314	385	State machine metastates.
315	386	*/
316	387	enum
r32282	r32283
328	399	{ 0x01, 0xff, &hdc9234_device::drive_deselect },
329	400	{ 0x02, 0xfe, &hdc9234_device::restore_drive },
330	401	{ 0x04, 0xfc, &hdc9234_device::step_drive },
	402	{ 0x08, 0xf8, &hdc9234_device::tape_backup },
	403	{ 0x10, 0xf0, &hdc9234_device::poll_drives },
331	404	{ 0x20, 0xe0, &hdc9234_device::drive_select },
332	405	{ 0x40, 0xf0, &hdc9234_device::set_register_pointer },
	406	{ 0x50, 0xf8, &hdc9234_device::seek_read_id },
333	407	{ 0x58, 0xfe, &hdc9234_device::read_sectors },
	408	{ 0x5a, 0xfe, &hdc9234_device::read_track },
334	409	{ 0x5c, 0xfc, &hdc9234_device::read_sectors },
335		{ 0xa0, 0xa0, &hdc9234_device::write_sector_logical },
	410	{ 0x60, 0xe0, &hdc9234_device::format_track },
	411	{ 0x80, 0x80, &hdc9234_device::write_sectors },
336	412	{ 0, 0, 0 }
337	413	};
338	414
r32282	r32283
369	445	}
370	446
371	447	/*
	448	Are we back on track 0?
	449	*/
	450	bool hdc9234_device::on_track00()
	451	{
	452	return (m_register_r[DRIVE_STATUS] & HDC_DS_TRK00)!=0;
	453	}
	454
	455	/*
372	456	Accessor functions for specific parameters.
373	457	*/
374	458	int hdc9234_device::desired_head()
r32282	r32283
505	589	{
506	590	case READ_ID:
507	591	// Implied seek: Enter the READ_ID subprogram.
508		if (TRACE_ACT) logerror("%s: substate READ_ID\n", tag());
	592	if (TRACE_READID && TRACE_SUBSTATES) logerror("%s: substate READ_ID\n", tag());
509	593
510	594	m_substate = implied_seek? READ_ID1 : VERIFY;
511	595
r32282	r32283
522	606	// If an error occured (no IDAM found), terminate the command
523	607	if ((m_register_r[CHIP_STATUS] & CS_SYNCERR) != 0)
524	608	{
525		logerror("%s: READ_ID failed to find any IDAM\n", tag());
	609	if (TRACE_FAIL) logerror("%s: READ_ID failed to find any IDAM\n", tag());
526	610	cont = ERROR;
527	611	break;
528	612	}
529	613
530		if (TRACE_ACT)
	614	if (TRACE_READID && TRACE_SUBSTATES)
531	615	{
532	616	logerror("%s: substate READ_ID1\n", tag());
533	617	logerror("%s: DESIRED_CYL = %d; CURRENT_CYL = %d\n", tag(), desired_cylinder(), current_cylinder());
r32282	r32283
537	621	// We just need to check whether it ended in 0000
538	622	if (m_live_state.crc != 0)
539	623	{
540		logerror("%s: CRC error in sector header\n", tag());
	624	if (TRACE_FAIL) logerror("%s: CRC error in sector header\n", tag());
541	625	set_bits(m_register_r[CHIP_STATUS], CS_CRCERR, true);
542	626	cont = ERROR;
543	627	break;
r32282	r32283
560	644	break;
561	645	}
562	646
563		if (TRACE_ACT) logerror("%s: substate STEP_ON\n", tag());
	647	if (TRACE_READID && TRACE_SUBSTATES) logerror("%s: substate STEP_ON\n", tag());
564	648	// STEPDIR = 0 -> towards TRK00
565	649	set_bits(m_output2, OUT2_STEPDIR, (m_track_delta>0));
566	650	set_bits(m_output2, OUT2_STEPPULSE, true);
r32282	r32283
570	654	break;
571	655
572	656	case READ_ID_STEPOFF:
573		if (TRACE_ACT) logerror("%s: substate STEP_OFF\n", tag());
	657	if (TRACE_READID && TRACE_SUBSTATES) logerror("%s: substate STEP_OFF\n", tag());
574	658	set_bits(m_output2, OUT2_STEPPULSE, false);
575	659	auxbus_out();
576	660	m_track_delta += (m_track_delta<0)? 1 : -1;
r32282	r32283
580	664	break;
581	665
582	666	default:
583		if (TRACE_ACT) logerror("%s: unknown substate %d in read_id\n", tag(), m_substate);
	667	logerror("%s: unknown substate %d in read_id\n", tag(), m_substate);
584	668	cont = ERROR;
585	669	}
586	670	}
587	671
588	672	//  When an error occurs, the COMMAND_TERMINATION bits are set to 01
589		if (cont == ERROR) set_command_done(TC_RDIDERR);
	673	if (cont == ERROR)
	674	{
	675	live_abort();
	676	set_command_done(TC_RDIDERR);
	677	}
590	678	}
591	679
592	680	/*
r32282	r32283
608	696	// After seeking (or immediately when implied seek has been disabled),
609	697	// find the desired sector.
610	698
611		if (TRACE_ACT) logerror("%s: substate VERIFY\n", tag());
	699	if (TRACE_VERIFY && TRACE_SUBSTATES) logerror("%s: substate VERIFY\n", tag());
612	700
613	701	// If an error occured (no IDAM found), terminate the command
614	702	// (This test is only relevant when we did not have a seek phase before)
615	703	if ((m_register_r[CHIP_STATUS] & CS_SYNCERR) != 0)
616	704	{
617		logerror("%s: VERIFY failed to find any IDAM\n", tag());
	705	if (TRACE_FAIL) logerror("%s: VERIFY failed to find any IDAM\n", tag());
618	706	cont = ERROR;
619	707	break;
620	708	}
r32282	r32283
630	718	&& desired_head() == current_head()
631	719	&& desired_sector() == current_sector())
632	720	{
633		if (TRACE_ACT) logerror("%s: Found the desired sector CHS=(%d,%d,%d)\n", tag(),
	721	if (TRACE_VERIFY) logerror("%s: Found the desired sector CHS=(%d,%d,%d)\n", tag(),
634	722	desired_cylinder(),
635	723	desired_head(),
636	724	desired_sector());
r32282	r32283
639	727	}
640	728	else
641	729	{
642		if (TRACE_VERIFY) logerror("%s: Current CHS=(%d,%d,%d), desired CHS=(%d,%d,%d).\n", tag(),
	730	if (TRACE_VERIFY && TRACE_DETAIL) logerror("%s: Current CHS=(%d,%d,%d), desired CHS=(%d,%d,%d).\n", tag(),
643	731	current_cylinder(),
644	732	current_head(),
645	733	current_sector(),
r32282	r32283
660	748	case VERIFY3:
661	749	if ((m_register_r[CHIP_STATUS] & CS_SYNCERR) != 0)
662	750	{
663		logerror("%s: VERIFY failed to find sector CHS=(%d,%d,%d)\n", tag(),
664		desired_cylinder(),
665		desired_head(),
666		desired_sector());
	751	if (TRACE_FAIL) logerror("%s: VERIFY failed to find sector CHS=(%d,%d,%d)\n", tag(), desired_cylinder(), desired_head(), desired_sector());
667	752	// live_run has set the sync error; clear it
668	753	set_bits(m_register_r[CHIP_STATUS], CS_SYNCERR, false);
669	754	// and set the compare error bit instead
r32282	r32283
675	760	// Continue with the loop
676	761	if (verify_all)
677	762	{
678		// this is for the logical sector reading
	763	// this is for the logical sector reading/writing
679	764	m_substate = VERIFY1;
680	765	}
681	766	else
682	767	{
683		// this is for the physical sector reading
	768	// this is for the physical sector reading/writing
684	769	// do not verify the next ID field
685	770	m_substate = DATA_TRANSFER;
686	771	m_wait_for_index = true;
r32282	r32283
695	780	}
696	781
697	782	// When an error occurs, the COMMAND_TERMINATION bits are set to 10
698		if (cont == ERROR) set_command_done(TC_VRFYERR);
	783	if (cont == ERROR)
	784	{
	785	live_abort();
	786	set_command_done(TC_VRFYERR);
	787	}
699	788	}
700	789
701	790	/*
r32282	r32283
716	805	switch (m_substate)
717	806	{
718	807	case DATA_TRANSFER:
719		if (TRACE_ACT) logerror("%s: substate DATA_TRANSFER\n", tag());
	808	if (TRACE_TRANSFER && TRACE_SUBSTATES) logerror("%s: substate DATA_TRANSFER\n", tag());
720	809
721	810	// Count from 0 again
722	811	m_live_state.bit_count_total = 0;
723	812
724		if (m_transfer_enabled) dma_address_out();
	813	if (m_transfer_enabled) dma_address_out(m_register_w[DMA23_16], m_register_w[DMA15_8], m_register_w[DMA7_0]);
725	814
726		if (TRACE_RWSEC) logerror("%s: %s sector CHS=(%d,%d,%d)\n", tag(), m_write? "write" : "read",
	815	if (TRACE_TRANSFER && TRACE_DETAIL) logerror("%s: %s sector CHS=(%d,%d,%d)\n", tag(), m_write? "write" : "read",
727	816	desired_cylinder(),
728	817	desired_head(),
729	818	desired_sector());
r32282	r32283
753	842	// Decrement the retry register (one's complemented value; 0000 = 15)
754	843	int retry = 15-((m_register_w[RETRY_COUNT] >> 4)&0x0f);
755	844
756		logerror("%s: DATA TRANSFER got CRC error in sector data, retries = %d\n", tag(), retry);
	845	if (TRACE_FAIL) logerror("%s: DATA TRANSFER got CRC error in sector data, retries = %d\n", tag(), retry);
757	846	m_register_w[RETRY_COUNT] = (m_register_w[RETRY_COUNT] & 0x0f) | ((15-(retry-1))<<4);
758	847
759	848	if (retry == 0)
760	849	{
761		if (TRACE_ACT) logerror("%s: CRC error; no retries left\n", tag());
	850	if (TRACE_FAIL) logerror("%s: CRC error; no retries left\n", tag());
762	851	set_bits(m_register_r[CHIP_STATUS], CS_CRCERR, true);
763	852	cont = ERROR;
764	853	}
r32282	r32283
776	865	}
777	866	else
778	867	{
779		if (TRACE_ACT) logerror("%s: Sector successfully read\n", tag());
	868	if (TRACE_TRANSFER) logerror("%s: Sector successfully read\n", tag());
780	869
781	870	// Update the DMA registers for multi-sector operations
782	871	if (m_multi_sector)
r32282	r32283
818	907	break;
819	908
820	909	case DATA_TRANSFER_WRITE:
821		if (TRACE_ACT) logerror("%s: Sector successfully written\n", tag());
	910	if (TRACE_TRANSFER) logerror("%s: Sector successfully written\n", tag());
822	911
823	912	// Update the DMA registers for multi-sector operations
824	913	if (m_multi_sector)
r32282	r32283
857	946	if (cont==SUCCESS) set_command_done(TC_SUCCESS);
858	947
859	948	//  When an error occurs, the COMMAND_TERMINATION bits are set to 11
860		if (cont==ERROR) set_command_done(TC_DATAERR);
	949	if (cont==ERROR)
	950	{
	951	live_abort();
	952	set_command_done(TC_DATAERR);
	953	}
861	954	}
862	955
863	956	// ===========================================================================
r32282	r32283
869	962	*/
870	963	void hdc9234_device::reset_controller()
871	964	{
872		if (TRACE_COMMAND) logerror("%s: RESET command\n", tag());
	965	logerror("%s: RESET command\n", tag());
873	966	device_reset();
874	967	}
875	968	/*
r32282	r32283
877	970	*/
878	971	void hdc9234_device::drive_deselect()
879	972	{
880		if (TRACE_COMMAND) logerror("%s: DESELECT command\n", tag());
	973	if (TRACE_SELECT) logerror("%s: DESELECT command\n", tag());
881	974	m_selected_drive_number = NODRIVE;
882	975	auxbus_out();
883	976	set_command_done(TC_SUCCESS);
r32282	r32283
898	991	// In wd_fdc this is solved using two methods <command>_start and <command>_continue
899	992	if (m_substate == UNDEF)
900	993	{
901		if (TRACE_COMMAND) logerror("%s: RESTORE command %02x\n", tag(), current_command());
	994	if (TRACE_RESTORE) logerror("%s: RESTORE command %02x\n", tag(), current_command());
902	995	m_seek_count = 0;
903	996	m_substate = RESTORE_CHECK1;
904	997	}
r32282	r32283
908	1001	switch (m_substate)
909	1002	{
910	1003	case RESTORE_CHECK1:
911		if (TRACE_ACT) logerror("%s: substate RESTORE_CHECK; seek count = %d\n", tag(), m_seek_count);
	1004	if (TRACE_RESTORE && TRACE_SUBSTATES) logerror("%s: substate RESTORE_CHECK; seek count = %d\n", tag(), m_seek_count);
912	1005	// If the drive is on track 0 or not ready (no drive), terminate the command
913	1006	if (on_track00())
914	1007	{
915		if (TRACE_ACT) logerror("%s: restore command TRK00 reached\n", tag());
	1008	if (TRACE_RESTORE) logerror("%s: restore command TRK00 reached\n", tag());
916	1009	if (current_command() & 1)
917	1010	{
918	1011	// Buffered seek; wait for SEEK_COMPLETE
919		wait_line(SEEK_COMPLETE);
	1012	wait_line(SEEKCOMP_LINE, ASSERT_LINE, SEEK_COMPLETE, false);
920	1013	cont = WAIT;
921	1014	}
922	1015	else
r32282	r32283
932	1025	// Track 0 has not been reached yet
933	1026	if ((m_register_r[DRIVE_STATUS] & HDC_DS_READY)==0)
934	1027	{
935		if (TRACE_COMMAND) logerror("%s: restore command: drive not ready\n", tag());
	1028	if (TRACE_RESTORE) logerror("%s: restore command: drive not ready\n", tag());
936	1029	// Does not look like a success, but this takes into account
937	1030	// that if a drive is not connected we do not want an error message
938	1031	cont = SUCCESS;
r32282	r32283
943	1036	m_seek_count++;
944	1037	if (m_seek_count>=4096)
945	1038	{
946		logerror("%s: restore command: failed to reach track 00\n", tag());
	1039	if (TRACE_FAIL) logerror("%s: restore command: failed to reach track 00\n", tag());
947	1040	set_command_done(TC_VRFYERR);
948	1041	cont = ERROR;
949	1042	break;
r32282	r32283
975	1068
976	1069	if (m_substate == UNDEF)
977	1070	{
978		if (TRACE_COMMAND) logerror("%s: STEP IN/OUT command %02x\n", tag(), current_command());
	1071	if (TRACE_STEP) logerror("%s: STEP IN/OUT command %02x\n", tag(), current_command());
979	1072	m_substate = STEP_ON;
980	1073	}
981	1074
r32282	r32283
1000	1093	}
1001	1094
1002	1095	/*
	1096	TAPE BACKUP
	1097	Not implemented
	1098	*/
	1099	void hdc9234_device::tape_backup()
	1100	{
	1101	logerror("%s: TAPE BACKUP command %02x not implemented\n", tag(), current_command());
	1102	set_command_done(TC_SUCCESS);
	1103	}
	1104
	1105	/*
	1106	POLL DRIVES
	1107	Not implemented
	1108	*/
	1109	void hdc9234_device::poll_drives()
	1110	{
	1111	logerror("%s: POLL DRIVES command %02x not implemented\n", tag(), current_command());
	1112	set_command_done(TC_SUCCESS);
	1113	}
	1114
	1115	/*
1003	1116	DRIVE SELECT
1004	1117
1005	1118	Command word
r32282	r32283
1035	1148	head_load_delay = head_load_delay_enable? m_register_w[DATA] * head_load_timer_increment[m_selected_drive_type] : 0;
1036	1149	if (fm_mode()) head_load_delay <<= 1;
1037	1150
1038		if (TRACE_COMMAND) logerror("%s: DRIVE SELECT command (%02x): head load delay=%d, type=%d, drive=%d, pout=%02x\n", tag(), current_command(), head_load_delay, m_selected_drive_type, driveparm&3, m_register_w[RETRY_COUNT]&0x0f);
	1151	if (TRACE_SELECT) logerror("%s: DRIVE SELECT command (%02x): head load delay=%d, type=%d, drive=%d, pout=%02x, step_rate=%d\n", tag(), current_command(), head_load_delay, m_selected_drive_type, driveparm&3, m_register_w[RETRY_COUNT]&0x0f, pulse_width() + step_time());
1039	1152
1040	1153	// Copy the DMA registers to registers CURRENT_HEAD, CURRENT_CYLINDER,
1041	1154	// and CURRENT_IDENT. This is required during formatting ([1], p. 14)
r32282	r32283
1046	1159
1047	1160	// Copy the selected drive number to the chip status register
1048	1161	m_register_r[CHIP_STATUS] = (m_register_r[CHIP_STATUS] & 0xfc) | m_selected_drive_number;
	1162
	1163	m_output1 = (m_selected_drive_number != NODRIVE)? (0x10 << m_selected_drive_number) : 0;
	1164	m_output1 |= (m_register_w[RETRY_COUNT]&0x0f);
	1165	if (TRACE_AUXBUS) logerror("%s: Setting OUTPUT1 to %02x\n", tag(), m_output1);
	1166
1049	1167	auxbus_out();
1050	1168
1051	1169	m_substate = (head_load_delay>0)? HEAD_DELAY : DONE;
r32282	r32283
1078	1196	void hdc9234_device::set_register_pointer()
1079	1197	{
1080	1198	m_register_pointer = current_command() & 0xf;
1081		if (TRACE_SETREG) logerror("%s: SET REGISTER POINTER command; start reg=%d\n", tag(), m_register_pointer);
	1199	if (TRACE_SETPTR) logerror("%s: SET REGISTER POINTER command; start reg=%d\n", tag(), m_register_pointer);
1082	1200	// The specification does not say anything about the effect of setting an
1083	1201	// invalid value (only "care should be taken")
1084	1202	if (m_register_pointer > 10)
r32282	r32283
1090	1208	}
1091	1209
1092	1210	/*
	1211	SEEK / READ ID
	1212	Not implemented
	1213	*/
	1214	void hdc9234_device::seek_read_id()
	1215	{
	1216	logerror("%s: SEEK / READ ID command %02x not implemented\n", tag(), current_command());
	1217	set_command_done(TC_SUCCESS);
	1218	}
	1219
	1220	/*
1093	1221	READ SECTORS PHYSICAL / LOGICAL
1094	1222	Read the desired sectors, maximum count being specified in SECTOR_COUNT
1095	1223
1096	1224	Physical:
1097	1225	For multiple sectors, read the sectors in the order as they appear on the track.
1098	1226	The command terminates with the next index pulse or when all sectors have been read before.
1099		Implied seek (locate the correct track) is always true.
1100		Opcodes:
1101		58 = transfer disabled
1102		59 = transfer enabled
	1227	Implied seek (locate the correct track) is always true (opcodes 5a and 5b
	1228	are used for READ TRACK).
1103	1229
1104	1230	Logical:
1105	1231	For multiple sectors, read the sectors in ascending order of their sector field (sector n, n+1, n+2 ...).
1106		Opcodes:
1107		5c = implied seek / transfer disabled
1108		5d = implied seek / transfer enabled
1109		5e = no implied seek / transfer disabled
1110		5f = no implied seek / transfer enabled
	1232
	1233	Command flags
	1234	[ 0 ]  [ 1 ]  [ 0 ]  [ 1 ]   [ 1 ] [ Logical ] [ NoImplSeek ] [ Transfer ]
1111	1235	*/
1112	1236	void hdc9234_device::read_sectors()
1113	1237	{
1114		bool logical = (current_command() & 0xfc)==0x5c;
	1238	bool logical = (current_command() & 0x04)!=0;
1115	1239
1116	1240	if (m_substate == UNDEF)
1117	1241	{
1118	1242	// Command init
1119		if (TRACE_COMMAND) logerror("%s: READ SECTORS %s command %02x, CHS=(%d,%d,%d)\n", tag(), logical? "LOGICAL": "PHYSICAL", current_command(), desired_cylinder(), desired_head(), desired_sector());
	1243	if (TRACE_READ) logerror("%s: READ SECTORS %s command %02x, CHS=(%d,%d,%d)\n", tag(), logical? "LOGICAL": "PHYSICAL", current_command(), desired_cylinder(), desired_head(), desired_sector());
1120	1244	m_retry_save = m_register_w[RETRY_COUNT];
1121	1245	m_multi_sector = (m_register_w[SECTOR_COUNT] != 1);
1122	1246
r32282	r32283
1124	1248	}
1125	1249
1126	1250	int cont = NEXT;
1127		bool implied_seek = !logical || (current_command() & 0x02)==0;
1128		m_transfer_enabled = (current_command()&0x01)!=0;
	1251	bool implied_seek = (current_command() & 0x02)==0;
	1252	m_transfer_enabled = (current_command() & 0x01)!=0;
1129	1253
1130	1254	while (cont == NEXT)
1131	1255	{
r32282	r32283
1149	1273	}
1150	1274
1151	1275	/*
1152		Write the desired sector. For multiple sectors, write the sectors in
1153		ascending order (sector n, n+1, n+2 ...).
1154		Opcodes: A0 - BF, E0 - FF
	1276	READ TRACK
	1277	Not implemented
	1278	*/
	1279	void hdc9234_device::read_track()
	1280	{
	1281	logerror("%s: READ TRACK command %02x not implemented\n", tag(), current_command());
	1282	set_command_done(TC_SUCCESS);
	1283	}
1155	1284
1156		[  1  ] [ ImplSeek ] [  1  ]  [ NormalData ]  [ ReducedWC ]  [ PreC2 ] [ PreC1 ] [ PreC0 ]
	1285	/*
	1286	FORMAT TRACK
	1287	Writes a track on the selected drive at the current cylinder. The write
	1288	process starts with the falling edge of the index hole and stops with
	1289	the rising edge of the next index hole.
	1290
	1291	The formatting is done exclusively by the controller; user programs may
	1292	set parameters for gaps and interleaving.
	1293
	1294	1. Before starting the command, the user program must have set up a
	1295	sector sequence table in the controller RAM (located on the PCB):
	1296	(ident, cylinder, head, sector1, size)  (5 bytes)
	1297	(ident, cylinder, head, sector2, size)
	1298	(ident, cylinder, head, sector3, size)
	1299	...
	1300	ident is not required for floppy FM operation. size is not required
	1301	for IBM AT-compatible hard disks.
	1302
	1303	2. The DMA registers must point to the beginning of the table
	1304
	1305	3. DRIVE_SELECT must be executed (which moves DMA regs to CUR_HEAD ...)
	1306
	1307	4. DESIRED_HEAD register must be loaded
	1308
	1309	5. The following setup must be done:
	1310
	1311	GAP 0 size            DMA7_0              (2s comp)
	1312	GAP 1 size            DMA15_8             (2s comp)
	1313	GAP 2 size            DMA23_16            (2s comp)
	1314	GAP 3 size            DESIRED_SECTOR      (2s comp)
	1315	Sync size             DESIRED_CYLINDER    (1s comp)
	1316	Sector count          SECTOR_COUNT        (1s comp)
	1317	Sector size multiple  RETRY_COUNT         (1s comp)
	1318
	1319	GAP4 is variable and fills the rest of the track until the next
	1320	index hole.
	1321
	1322	6. The step rate and density must be loaded into the MODE register
	1323
	1324	7. The drive must be stepped to the desired track.
	1325
	1326	8. Now this command may be started.
	1327
	1328	All data bytes of a sector are filled with 0xe5. The gaps will be filled
	1329	with 0x4e (MFM) or 0xff (FM).
	1330
	1331	To format another track, the sector id table must be updated, and steps
	1332	7 and 8 must be repeated. If the DESIRED_HEAD register must be updated,
	1333	the complete setup process must be done.
	1334
	1335	Command flags
	1336	[  0  ] [  1  ] [  1  ] [ NormalData ] [ ReducedWC ] [ PreC2, PreC1, PreC0 ]
1157	1337	*/
1158		void hdc9234_device::write_sector_logical()
	1338	void hdc9234_device::format_track()
1159	1339	{
1160	1340	if (m_substate == UNDEF)
1161	1341	{
1162		if (TRACE_COMMAND) logerror("%s: write sectors logical command %02x, CHS=(%d,%d,%d)\n", tag(), current_command(), desired_cylinder(), desired_head(), desired_sector());
	1342	if (TRACE_FORMAT) logerror("%s: FORMAT TRACK command %02x, head = %d\n", tag(), current_command(), desired_head());
	1343	m_substate = WAITINDEX0;
	1344	m_deleted = (current_command() & 0x10)==0;
	1345	m_reduced_write_current = (current_command() & 0x08)!=0;
	1346	m_precompensation = (current_command() & 0x07);
	1347
	1348	m_gap0_size = -m_register_w[DMA7_0] & 0xff;
	1349	m_gap1_size = -m_register_w[DMA15_8] & 0xff;
	1350	m_gap2_size = -m_register_w[DMA23_16] & 0xff;
	1351	m_gap3_size = -m_register_w[DESIRED_SECTOR] & 0xff;
	1352	m_sync_size = ~m_register_w[DESIRED_CYLINDER] & 0xff;
	1353	m_sector_count = ~m_register_w[SECTOR_COUNT] & 0xff;
	1354	m_sector_size = (~m_register_w[RETRY_COUNT] & 0xff) * 128;
	1355
	1356	if (TRACE_FORMAT && TRACE_DETAIL)
	1357	{
	1358	logerror("%s: GAP0 length  = %d\n", tag(), m_gap0_size);
	1359	logerror("%s: GAP1 length  = %d\n", tag(), m_gap1_size);
	1360	logerror("%s: GAP2 length  = %d\n", tag(), m_gap2_size);
	1361	logerror("%s: GAP3 length  = %d\n", tag(), m_gap3_size);
	1362	logerror("%s: Sync size    = %d\n", tag(), m_sync_size);
	1363	logerror("%s: Sector count = %d\n", tag(), m_sector_count);
	1364	logerror("%s: Sector size  = %d\n", tag(), m_sector_size);
	1365	}
	1366
	1367	dma_address_out(m_register_r[CURRENT_IDENT], m_register_r[CURRENT_CYLINDER], m_register_r[CURRENT_HEAD]);
	1368	}
	1369
	1370	int cont = NEXT;
	1371	while (cont == NEXT)
	1372	{
	1373	switch (m_substate)
	1374	{
	1375	case WAITINDEX0:
	1376	// Do we happen to have an index hole right now?
	1377	if ((m_register_r[DRIVE_STATUS] & HDC_DS_INDEX)==0)
	1378	{
	1379	m_substate = WAITINDEX1;
	1380	cont = NEXT;
	1381	}
	1382	else
	1383	{
	1384	// Waiting for the index line going down
	1385	wait_line(INDEX_LINE, ASSERT_LINE, WAITINDEX1, false);
	1386	cont = WAIT;
	1387	}
	1388	break;
	1389	case WAITINDEX1:
	1390	// Waiting for the next rising edge
	1391	wait_line(INDEX_LINE, ASSERT_LINE, TRACKSTART, false);
	1392	cont = WAIT;
	1393	break;
	1394	case TRACKSTART:
	1395	live_start(FORMAT_TRACK);
	1396	wait_line(INDEX_LINE, ASSERT_LINE, TRACKDONE, true);
	1397	cont = WAIT;
	1398	break;
	1399	case TRACKDONE:
	1400	if (FORMAT_TRACK && TRACE_SUBSTATES) logerror("%s: Track writing done\n", tag());
	1401	cont = SUCCESS;
	1402	break;
	1403	}
	1404	}
	1405
	1406	if (cont==SUCCESS) set_command_done(TC_SUCCESS);
	1407	}
	1408
	1409	/*
	1410	WRITE SECTORS PHYSICAL / LOGICAL
	1411
	1412	Write the desired sectors, maximum count being specified in SECTOR_COUNT
	1413
	1414	Physical:
	1415	For multiple sectors, write sector contents into the data fields of
	1416	the sectors as they are arranged on the track.
	1417	The command terminates with the next index pulse or when all sectors have been written before.
	1418
	1419	Logical:
	1420	For multiple sectors, write the sectors in ascending order of their
	1421	sector field (sector n, n+1, n+2 ...).
	1422
	1423	Command flags
	1424	[  1  ] [ NoImplSeek ] [  Logical  ]  [ NormalData ]  [ ReducedWC ]  [ PreC2, PreC1, PreC0 ]
	1425
	1426	*/
	1427	void hdc9234_device::write_sectors()
	1428	{
	1429	bool logical = (current_command() & 0x20)!=0;
	1430
	1431	if (m_substate == UNDEF)
	1432	{
	1433	if (TRACE_WRITE) logerror("%s: WRITE SECTORS %s command %02x, CHS=(%d,%d,%d)\n", tag(), logical? "LOGICAL" : "PHYSICAL", current_command(), desired_cylinder(), desired_head(), desired_sector());
1163	1434	m_multi_sector = (m_register_w[SECTOR_COUNT] != 1);
1164	1435	m_substate = READ_ID;
	1436
	1437	m_deleted = (current_command() & 0x10)==0;
	1438	m_reduced_write_current = (current_command() & 0x08)!=0;
	1439	m_precompensation = (current_command() & 0x07);
	1440	// Important for DATA TRANSFER
	1441	m_transfer_enabled = true;
	1442	m_write = true;
	1443	m_sync_size = fm_mode()? 6 : 12;
	1444	m_gap2_size = fm_mode()? 11 : 22;
1165	1445	}
1166	1446
1167	1447	int cont = NEXT;
	1448	bool implied_seek = (current_command() & 0x40)==0;
1168	1449
1169		m_write = true;
1170		m_transfer_enabled = true;
1171
1172		m_deleted = (current_command() & 0x10)==0;
1173		m_precompensation = (current_command() & 0x07);
1174		m_reduced_write_current = (current_command() & 0x08)!=0;
1175
1176	1450	while (cont == NEXT)
1177	1451	{
1178	1452	// We're dispatching by substate value range
1179	1453	switch (m_substate & 0xf0)
1180	1454	{
1181	1455	case READ_ID:
1182		read_id(cont, (current_command() & 0x02)==0);
	1456	read_id(cont, implied_seek);
1183	1457	break;
1184	1458	case VERIFY:
1185		verify(cont, true);
	1459	verify(cont, logical);
1186	1460	break;
1187	1461	case DATA_TRANSFER:
1188	1462	data_transfer(cont);
1189	1463	break;
1190	1464	default:
1191		logerror("%s: unknown substate %d in write_sector_logical\n", tag(), m_substate);
	1465	logerror("%s: unknown substate %d in write_sectors\n", tag(), m_substate);
1192	1466	cont = ERROR;
1193	1467	}
1194	1468	}
r32282	r32283
1217	1491	*/
1218	1492	void hdc9234_device::step_on(bool towards00, int next)
1219	1493	{
1220		if (TRACE_ACT) logerror("%s: substate STEP_ON\n", tag());
	1494	if ((TRACE_RESTORE | TRACE_STEP) && TRACE_SUBSTATES) logerror("%s: substate STEP_ON\n", tag());
1221	1495
1222	1496	// STEPDIR = 0 -> towards TRK00
1223	1497	set_bits(m_output2, OUT2_STEPDIR, !towards00);
r32282	r32283
1230	1504
1231	1505	void hdc9234_device::step_off(int next)
1232	1506	{
1233		if (TRACE_ACT) logerror("%s: substate STEP_OFF\n", tag());
	1507	if ((TRACE_RESTORE | TRACE_STEP) && TRACE_SUBSTATES) logerror("%s: substate STEP_OFF\n", tag());
1234	1508	set_bits(m_output2, OUT2_STEPPULSE, false);
1235	1509	auxbus_out();
1236	1510	wait_time(m_timer, step_time(), next);
r32282	r32283
1330	1604	m_live_state.byte_counter = 0;
1331	1605	m_live_state.data_separator_phase = false;
1332	1606	m_live_state.data_reg = 0;
	1607	m_live_state.last_data_bit = false;
1333	1608
1334	1609	pll_reset(m_live_state.time);
1335	1610	m_checkpoint_state = m_live_state;
r32282	r32283
1356	1631	{
1357	1632	int slot = 0;
1358	1633
1359		if (TRACE_LIVE) logerror("%s: [%s] live_run, live_state=%d, fm_mode=%d\n", tag(), tts(m_live_state.time).cstr(), m_live_state.state, fm_mode()? 1:0);
	1634	if (m_live_state.state == IDLE || m_live_state.next_state != -1)
	1635	return;
1360	1636
1361		if (m_live_state.state == IDLE || m_live_state.next_state != -1)
	1637	if (TRACE_LIVE)
1362	1638	{
1363		if (TRACE_LIVE) logerror("%s: [%s] live_run, state=%d, next_state=%d\n", tag(), tts(m_live_state.time).cstr(), m_live_state.state,m_live_state.next_state);
1364		return;
	1639	if (limit == attotime::never)
	1640	logerror("%s: [%s] live_run, live_state=%d, mode=%s\n", tag(), tts(m_live_state.time).cstr(), m_live_state.state, fm_mode()? "FM":"MFM");
	1641	else
	1642	logerror("%s: [%s] live_run until %s, live_state=%d, mode=%s\n", tag(), tts(m_live_state.time).cstr(), tts(limit).cstr(), m_live_state.state, fm_mode()? "FM":"MFM");
1365	1643	}
1366	1644
1367	1645	if (limit == attotime::never)
r32282	r32283
1392	1670	// control this loggind.
1393	1671
1394	1672	if (TRACE_LIVE && m_last_live_state != SEARCH_IDAM)
	1673	{
1395	1674	logerror("%s: [%s] SEARCH_IDAM [limit %s]\n", tag(),tts(m_live_state.time).cstr(), tts(limit).cstr());
1396		m_last_live_state = m_live_state.state;
	1675	m_last_live_state = m_live_state.state;
	1676	}
1397	1677
1398	1678	// This bit will be set when the IDAM cannot be found
1399	1679	set_bits(m_register_r[CHIP_STATUS], CS_SYNCERR, false);
r32282	r32283
1405	1685	}
1406	1686	// logerror("%s: SEARCH_IDAM\n", tts(m_live_state.time).cstr());
1407	1687	if (TRACE_SHIFT) logerror("%s: shift = %04x data=%02x c=%d\n", tts(m_live_state.time).cstr(), m_live_state.shift_reg,
1408		(m_live_state.shift_reg & 0x4000 ? 0x80 : 0x00) |
1409		(m_live_state.shift_reg & 0x1000 ? 0x40 : 0x00) |
1410		(m_live_state.shift_reg & 0x0400 ? 0x20 : 0x00) |
1411		(m_live_state.shift_reg & 0x0100 ? 0x10 : 0x00) |
1412		(m_live_state.shift_reg & 0x0040 ? 0x08 : 0x00) |
1413		(m_live_state.shift_reg & 0x0010 ? 0x04 : 0x00) |
1414		(m_live_state.shift_reg & 0x0004 ? 0x02 : 0x00) |
1415		(m_live_state.shift_reg & 0x0001 ? 0x01 : 0x00),
1416		m_live_state.bit_counter);
	1688	get_data_from_encoding(m_live_state.shift_reg), m_live_state.bit_counter);
1417	1689
1418	1690	// [1] p. 9: The ID field sync mark must be found within 33,792 byte times
1419	1691	if (m_live_state.bit_count_total > 33792*16)
r32282	r32283
1457	1729	case READ_TWO_MORE_A1_IDAM:     // This state only applies for MFM mode.
1458	1730
1459	1731	if (TRACE_LIVE && m_last_live_state != READ_TWO_MORE_A1_IDAM)
	1732	{
1460	1733	logerror("%s: [%s] READ_TWO_MORE_A1\n", tag(),tts(m_live_state.time).cstr());
1461		m_last_live_state = m_live_state.state;
	1734	m_last_live_state = m_live_state.state;
	1735	}
1462	1736
1463	1737	// Beyond time limit?
1464	1738	if (read_one_bit(limit)) return;
1465	1739
1466	1740	if (TRACE_SHIFT) logerror("%s: shift = %04x data=%02x c=%d\n", tts(m_live_state.time).cstr(), m_live_state.shift_reg,
1467		(m_live_state.shift_reg & 0x4000 ? 0x80 : 0x00) |
1468		(m_live_state.shift_reg & 0x1000 ? 0x40 : 0x00) |
1469		(m_live_state.shift_reg & 0x0400 ? 0x20 : 0x00) |
1470		(m_live_state.shift_reg & 0x0100 ? 0x10 : 0x00) |
1471		(m_live_state.shift_reg & 0x0040 ? 0x08 : 0x00) |
1472		(m_live_state.shift_reg & 0x0010 ? 0x04 : 0x00) |
1473		(m_live_state.shift_reg & 0x0004 ? 0x02 : 0x00) |
1474		(m_live_state.shift_reg & 0x0001 ? 0x01 : 0x00),
1475		m_live_state.bit_counter);
	1741	get_data_from_encoding(m_live_state.shift_reg), m_live_state.bit_counter);
1476	1742
1477	1743	if (m_live_state.bit_count_total > 33792*16)
1478	1744	{
r32282	r32283
1518	1784
1519	1785	case READ_ID_FIELDS_INTO_REGS:
1520	1786	if (TRACE_LIVE && m_last_live_state != READ_ID_FIELDS_INTO_REGS)
	1787	{
1521	1788	logerror("%s: [%s] READ_ID_FIELDS_INTO_REGS\n", tag(),tts(m_live_state.time).cstr());
1522		m_last_live_state = m_live_state.state;
	1789	m_last_live_state = m_live_state.state;
	1790	}
1523	1791
1524	1792	if (read_one_bit(limit))
1525	1793	{
r32282	r32283
1552	1820
1553	1821	case SEARCH_DAM:
1554	1822	if (TRACE_LIVE && m_last_live_state != SEARCH_DAM)
	1823	{
1555	1824	logerror("%s: [%s] SEARCH_DAM\n", tag(),tts(m_live_state.time).cstr());
1556		m_last_live_state = m_live_state.state;
	1825	m_last_live_state = m_live_state.state;
	1826	}
1557	1827
1558	1828	set_bits(m_register_r[CHIP_STATUS], CS_DELDATA, false);
1559	1829
r32282	r32283
1561	1831	return;
1562	1832
1563	1833	if (TRACE_SHIFT) logerror("%s: shift = %04x data=%02x c=%d\n", tts(m_live_state.time).cstr(), m_live_state.shift_reg,
1564		(m_live_state.shift_reg & 0x4000 ? 0x80 : 0x00) |
1565		(m_live_state.shift_reg & 0x1000 ? 0x40 : 0x00) |
1566		(m_live_state.shift_reg & 0x0400 ? 0x20 : 0x00) |
1567		(m_live_state.shift_reg & 0x0100 ? 0x10 : 0x00) |
1568		(m_live_state.shift_reg & 0x0040 ? 0x08 : 0x00) |
1569		(m_live_state.shift_reg & 0x0010 ? 0x04 : 0x00) |
1570		(m_live_state.shift_reg & 0x0004 ? 0x02 : 0x00) |
1571		(m_live_state.shift_reg & 0x0001 ? 0x01 : 0x00),
1572		m_live_state.bit_counter);
	1834	get_data_from_encoding(m_live_state.shift_reg), m_live_state.bit_counter);
1573	1835
1574	1836	if (!fm_mode())
1575	1837	{   // MFM
1576	1838	if(m_live_state.bit_counter > 43*16)
1577	1839	{
1578		logerror("%s: SEARCH_DAM failed\n", tag());
	1840	if (TRACE_FAIL) logerror("%s: SEARCH_DAM failed\n", tag());
1579	1841	wait_for_realtime(SEARCH_DAM_FAILED);
1580	1842	return;
1581	1843	}
r32282	r32283
1593	1855	{   // FM
1594	1856	if (m_live_state.bit_counter > 23*16)
1595	1857	{
1596		logerror("%s: SEARCH_DAM failed\n", tag());
	1858	if (TRACE_FAIL) logerror("%s: SEARCH_DAM failed\n", tag());
1597	1859	wait_for_realtime(SEARCH_DAM_FAILED);
1598	1860	return;
1599	1861	}
r32282	r32283
1615	1877
1616	1878	case READ_TWO_MORE_A1_DAM: {
1617	1879	if (TRACE_LIVE && m_last_live_state != READ_TWO_MORE_A1_DAM)
	1880	{
1618	1881	logerror("%s: [%s] READ_TWO_MORE_A1_DAM\n", tag(),tts(m_live_state.time).cstr());
1619		m_last_live_state = m_live_state.state;
	1882	m_last_live_state = m_live_state.state;
	1883	}
1620	1884
1621	1885	if(read_one_bit(limit))
1622	1886	return;
1623	1887
1624	1888	if (TRACE_SHIFT) logerror("%s: shift = %04x data=%02x c=%d\n", tts(m_live_state.time).cstr(), m_live_state.shift_reg,
1625		(m_live_state.shift_reg & 0x4000 ? 0x80 : 0x00) |
1626		(m_live_state.shift_reg & 0x1000 ? 0x40 : 0x00) |
1627		(m_live_state.shift_reg & 0x0400 ? 0x20 : 0x00) |
1628		(m_live_state.shift_reg & 0x0100 ? 0x10 : 0x00) |
1629		(m_live_state.shift_reg & 0x0040 ? 0x08 : 0x00) |
1630		(m_live_state.shift_reg & 0x0010 ? 0x04 : 0x00) |
1631		(m_live_state.shift_reg & 0x0004 ? 0x02 : 0x00) |
1632		(m_live_state.shift_reg & 0x0001 ? 0x01 : 0x00),
1633		m_live_state.bit_counter);
	1889	get_data_from_encoding(m_live_state.shift_reg), m_live_state.bit_counter);
1634	1890
1635	1891	// Repeat until we have collected 16 bits
1636	1892	if (m_live_state.bit_counter & 15) break;
r32282	r32283
1662	1918	{
1663	1919	if ((m_live_state.data_reg & 0xff) != 0xfb)
1664	1920	{
1665		if (TRACE_LIVE) logerror("%s: Missing FB/F8 data mark after DAM sync\n", tag());
	1921	if (TRACE_FAIL) logerror("%s: Missing FB/F8 data mark after DAM sync\n", tag());
1666	1922	wait_for_realtime(SEARCH_DAM_FAILED);
1667	1923	return;
1668	1924	}
r32282	r32283
1673	1929	break;
1674	1930	}
1675	1931	case SEARCH_DAM_FAILED:
1676		logerror("%s: SEARCH_DAM failed\n", tag());
	1932	if (TRACE_FAIL) logerror("%s: SEARCH_DAM failed\n", tag());
1677	1933	m_live_state.state = IDLE;
1678	1934	return;
1679	1935
1680	1936	case READ_SECTOR_DATA:
1681	1937	{
1682	1938	if (TRACE_LIVE && m_last_live_state != READ_SECTOR_DATA)
	1939	{
1683	1940	logerror("%s: [%s] READ_SECTOR_DATA\n", tag(),tts(m_live_state.time).cstr());
1684		m_last_live_state = m_live_state.state;
	1941	m_last_live_state = m_live_state.state;
	1942	}
1685	1943
1686	1944	if(read_one_bit(limit))
1687	1945	return;
r32282	r32283
1723	1981
1724	1982	case READ_SECTOR_DATA1:
1725	1983	if (TRACE_LIVE && m_last_live_state != READ_SECTOR_DATA1)
	1984	{
1726	1985	logerror("%s: [%s] READ_SECTOR_DATA1\n", tag(),tts(m_live_state.time).cstr());
1727		m_last_live_state = m_live_state.state;
	1986	m_last_live_state = m_live_state.state;
	1987	}
1728	1988
1729	1989	// Did the system CPU send the DMA ACK in the meantime?
1730	1990	if ((m_register_r[INT_STATUS] & ST_OVRUN)!=0)
1731	1991	{
1732		if (TRACE_LIVE) logerror("%s: No DMA ACK - buffer overrun\n", tag());
	1992	if (TRACE_FAIL) logerror("%s: No DMA ACK - buffer overrun\n", tag());
1733	1993	set_bits(m_register_r[INT_STATUS], TC_DATAERR, true);
1734	1994	m_live_state.state = IDLE;
1735	1995	return;
r32282	r32283
1760	2020	// 4. Write the sector content and calculate the CRC on the fly
1761	2021	// 5. Write the CRC bytes
1762	2022
1763		if (TRACE_LIVE && m_last_live_state != WRITE_DAM_AND_SECTOR)
	2023	if (TRACE_LIVE)
1764	2024	logerror("%s: [%s] WRITE_DAM_AND_SECTOR\n", tag(), tts(m_live_state.time).cstr());
1765		m_last_live_state = m_live_state.state;
1766		m_live_state.state = WRITE_SEC_SKIP_GAP2;
	2025
	2026	skip_on_track(m_gap2_size, WRITE_DAM_SYNC);
1767	2027	break;
1768	2028
1769		case WRITE_SEC_SKIP_GAP2:
1770		// The pause is implemented by doing dummy reads on the floppy
1771		if (read_one_bit(limit))
1772		return;
	2029	case WRITE_DAM_SYNC:
	2030	if (TRACE_WRITE && TRACE_DETAIL) logerror("%s: Write sync zeros\n", tag());
1773	2031
1774		// Repeat until we have collected 16 bits
1775		if (m_live_state.bit_counter & 15) break;
	2032	// Clear the overrun/underrun flag
	2033	set_bits(m_register_r[INT_STATUS], ST_OVRUN, false);
	2034	write_on_track(encode(0x00), m_sync_size, fm_mode()? WRITE_DATAMARK : WRITE_A1);
	2035	break;
1776	2036
1777		wait_for_realtime(WRITE_SEC_SKIP_GAP2_LOOP);
1778		return;
	2037	case WRITE_A1:
	2038	if (TRACE_WRITE && TRACE_DETAIL) logerror("%s: Write three A1\n", tag());
	2039	write_on_track(0x4489, 3, WRITE_DATAMARK);
	2040	break;
1779	2041
1780		case WRITE_SEC_SKIP_GAP2_LOOP:
1781		m_live_state.state = WRITE_SEC_SKIP_GAP2;
1782		m_live_state.byte_counter++;
1783		m_live_state.bit_counter = 0;
1784		if (TRACE_LIVE) logerror("%s: [%s] %d bytes skipped\n", tag(), tts(m_live_state.time).cstr(), m_live_state.byte_counter);
	2042	case WRITE_DATAMARK:
	2043	if (TRACE_WRITE && TRACE_DETAIL) logerror("%s: Write data mark and sector contents\n", tag());
	2044	if (fm_mode())
	2045	{
	2046	// Init the CRC for the DAM and sector
	2047	m_live_state.crc = 0xffff;
1785	2048
1786		if (m_live_state.byte_counter == (fm_mode()? 11 : 22))
	2049	// 1111 0101 0110 1010 = F8 deleted
	2050	// 1111 0101 0110 1111 = FB normal
	2051	write_on_track(m_deleted? 0xf56a : 0xf56f, 1, WRITE_SECDATA);
	2052	}
	2053	else
1787	2054	{
1788		if (TRACE_LIVE) logerror("%s: [%s] Skipped over gap2\n", tag(), tts(m_live_state.time).cstr());
1789		if (TRACE_WRITE) logerror("%s: [%s] Write 00\n", tag(), tts(m_live_state.time).cstr());
1790		// Start writing 0x00
1791		m_live_state.state = WRITE_SEC_BYTE;
1792		m_live_state.bit_counter = 16;
1793		m_live_state.byte_counter = 0;
1794		// The bit context is actually not used in FM
1795		m_live_state.last_data_bit = m_live_state.data_reg & 1;
1796		m_pll.start_writing(m_live_state.time);
1797		encode_byte(0x00);
	2055	// Init the CRC for the ident byte and sector
	2056	m_live_state.crc = 0xcdb4; // value for 3*A1
	2057	write_on_track(encode(m_deleted? 0xf8 : 0xfb), 1, WRITE_SECDATA);
	2058	}
	2059	m_live_state.byte_counter = calc_sector_size();
1798	2060
1799		// Clear the overrun/underrun flag
1800		set_bits(m_register_r[INT_STATUS], ST_OVRUN, false);
	2061	// Set the over/underrun flag and hope that it will be cleared before we start writing
	2062	// (only for sector writing)
	2063	if (m_substate == DATA_TRANSFER_WRITE)
	2064	{
	2065	set_bits(m_register_r[INT_STATUS], ST_OVRUN, true);
	2066	m_out_dmarq(ASSERT_LINE);
1801	2067	}
1802	2068	break;
1803	2069
1804		case WRITE_SEC_BYTE:
1805		if (write_one_bit(limit))
1806		return;
	2070	case WRITE_SECDATA:
	2071	if (m_substate == DATA_TRANSFER_WRITE)
	2072	{
	2073	// Check whether DMA has been acknowledged
	2074	if ((m_register_r[INT_STATUS] & ST_OVRUN)!=0)
	2075	{
	2076	// No, then stop here
	2077	m_live_state.state= NO_DMA_ACK;
	2078	}
	2079	else
	2080	{
	2081	m_out_dip(ASSERT_LINE);
	2082	m_register_r[DATA] = m_register_w[DATA] = m_in_dma(0, 0xff);
	2083	m_out_dip(CLEAR_LINE);
	2084	m_out_dmarq(CLEAR_LINE);
1807	2085
1808		if (m_live_state.bit_counter == 0)
	2086	if (m_live_state.byte_counter > 0)
	2087	{
	2088	m_live_state.byte_counter--;
	2089	write_on_track(encode(m_register_r[DATA]), 1, WRITE_SECDATA);
	2090	m_out_dmarq(ASSERT_LINE);
	2091	}
	2092	else
	2093	{
	2094	m_live_state.state = WRITE_DATA_CRC;
	2095	m_live_state.byte_counter = 2;
	2096	}
	2097	}
	2098	}
	2099	else
1809	2100	{
1810		// All bits written; get the next byte into the shift register
1811		wait_for_realtime(WRITE_SEC_NEXT_BYTE);
1812		return;
	2101	// We are here in the context of track formatting. Write a
	2102	// blank sector
	2103	write_on_track(encode(0xe5), m_sector_size, WRITE_DATA_CRC);
	2104	m_live_state.byte_counter = 2;
1813	2105	}
1814	2106	break;
1815	2107
1816		case WRITE_SEC_NEXT_BYTE:
1817		{
1818		if ((m_register_r[INT_STATUS] & ST_OVRUN)!=0)
	2108	case WRITE_DATA_CRC:
	2109	// N.B.: when we write the first CRC byte, the value of the CRC will
	2110	// change to the previous second byte, so we can write the first
	2111	// byte in two iterations to get both
	2112	if (m_live_state.byte_counter > 0)
1819	2113	{
1820		if (TRACE_LIVE) logerror("%s: No DMA ACK - buffer underrun\n", tag());
1821		set_bits(m_register_r[INT_STATUS], TC_DATAERR, true);
	2114	if (TRACE_WRITE && TRACE_DETAIL) logerror("%s: Write CRC\n", tag());
	2115	m_live_state.byte_counter--;
	2116	write_on_track(encode((m_live_state.crc >> 8) & 0xff), 1, WRITE_DATA_CRC);
	2117	}
	2118	else
	2119	m_live_state.state = WRITE_DONE;
	2120
	2121	break;
	2122
	2123	case WRITE_DONE:
	2124	if (m_substate == DATA_TRANSFER_WRITE)
	2125	{
	2126	if (TRACE_WRITE) logerror("%s: Write sector complete\n", tag());
1822	2127	m_pll.stop_writing(m_floppy, m_live_state.time);
1823	2128	m_live_state.state = IDLE;
1824	2129	return;
1825	2130	}
	2131	else
	2132	{
	2133	// Continue for track writing: Write GAP3
	2134	m_live_state.state = WRITE_GAP3;
	2135	}
	2136	break;
1826	2137
1827		int sector_start = fm_mode()? 7 : 16;
1828		int sync0_length = fm_mode()? 6 : 12;
1829		int sector_end = sector_start + calc_sector_size();
	2138	// --------------------------------------------------------
1830	2139
1831		m_live_state.state = WRITE_SEC_BYTE;
1832		m_live_state.bit_counter = 16;
1833		m_live_state.byte_counter++;
	2140	// ==================================================
	2141	// Live states for track formatting
	2142	// Write GAP 0
	2143	// Write Sync+IXAM
	2144	// Write GAP 1
	2145	// Per sector
	2146	//    Write Sync+IDAM
	2147	//    Write Sector header+CRC
	2148	//    Write GAP2
	2149	//    Write Sync+DAM
	2150	//    Write Sector data
	2151	//    Write CRC bytes
	2152	//    Write GAP3
	2153	// Write GAP4 until the next pulse
	2154	// ==================================================
1834	2155
1835		// Write all sync zeros
1836		if (m_live_state.byte_counter < sync0_length)
	2156	case FORMAT_TRACK:
	2157	if (TRACE_LIVE) logerror("%s: FORMAT_TRACK\n", tag());
	2158	m_live_state.state = WRITE_GAP0;
	2159	m_pll.start_writing(m_live_state.time);
	2160	break;
	2161
	2162	case WRITE_GAP0:
	2163	// GAP0 length is in DMA7_0 (negated, 2s comp)
	2164	if (TRACE_WRITE && TRACE_DETAIL) logerror("%s: Writing GAP0\n", tag());
	2165	write_on_track(encode(fm_mode()? 0xff : 0x4e), m_gap0_size, WRITE_IXAM_SYNC);
	2166	break;
	2167
	2168	case WRITE_IXAM_SYNC:
	2169	if (TRACE_WRITE && TRACE_DETAIL) logerror("%s: Writing IXAM sync\n", tag());
	2170	write_on_track(encode(0x00), m_sync_size, WRITE_IXAM);
	2171	break;
	2172
	2173	case WRITE_IXAM:
	2174	// FM: FC with clock D7 = 1111 -111 -111 1010
	2175	// MFM: C2 = 11000010
	2176	// 0101 0010 -010 0100
	2177	if (TRACE_WRITE && TRACE_DETAIL) logerror("%s: Writing IXAM\n", tag());
	2178	if (fm_mode())
	2179	write_on_track(0xf77a, 1, WRITE_GAP1);
	2180	else
	2181	write_on_track(0x5224, 3, WRITE_FC);
	2182
	2183	break;
	2184
	2185	case WRITE_FC:
	2186	// Only for MFM
	2187	write_on_track(encode(0xfc), 1, WRITE_GAP1);
	2188	break;
	2189
	2190	case WRITE_GAP1:
	2191	// GAP1 length is in DMA15_8
	2192	if (TRACE_WRITE && TRACE_DETAIL) logerror("%s: Writing GAP1\n", tag());
	2193	write_on_track(encode(fm_mode()? 0xff : 0x4e), m_gap1_size, WRITE_IDAM_SYNC);
	2194	break;
	2195
	2196	// When does the HDC actually fetch the per-sector data? All data
	2197	// at the beginning? Only the bytes for the next sector?
	2198	// We assume it reads the bytes and writes them directly on the disk
	2199
	2200	case WRITE_IDAM_SYNC:
	2201	if (TRACE_WRITE && TRACE_DETAIL) logerror("%s: Writing IDAM sync\n", tag());
	2202	write_on_track(encode(0x00), m_sync_size, WRITE_IDAM);
	2203	break;
	2204
	2205	case WRITE_IDAM:
	2206	// Set the over/underrun flag and hope that it will be cleared before we enter the next state (after writing)
	2207	set_bits(m_register_r[INT_STATUS], ST_OVRUN, true);
	2208	m_out_dmarq(ASSERT_LINE);
	2209
	2210	if (TRACE_WRITE && TRACE_DETAIL) logerror("%s: Writing IDAM and header\n", tag());
	2211	if (fm_mode())
1837	2212	{
1838		if (TRACE_WRITE) logerror("%s: [%s] Write 00\n", tag(), tts(m_live_state.time).cstr());
1839		encode_byte(0x00);
1840		checkpoint();
1841		break;
	2213	write_on_track(0xf57e, 1, WRITE_HEADER);
	2214	m_live_state.byte_counter = 4;
1842	2215	}
	2216	else
	2217	{
	2218	write_on_track(0x4489, 3, WRITE_HEADER);
	2219	m_live_state.byte_counter = 5;
	2220	}
	2221	m_live_state.crc = 0xffff;
	2222	break;
1843	2223
1844		// Write the DAM (MFM)
1845		if (m_live_state.byte_counter >= sync0_length && m_live_state.byte_counter < sector_start-1)
	2224	case WRITE_HEADER:
	2225	if ((m_register_r[INT_STATUS] & ST_OVRUN)!=0)
	2226	// No DMA (we do not get access to the ID table); exit
	2227	m_live_state.state= NO_DMA_ACK;
	2228	else
1846	2229	{
1847		if (TRACE_WRITE) logerror("%s: [%s] Write A1\n", tag(), tts(m_live_state.time).cstr());
1848		// only applies for MFM since sector_start-1 = 6 = sync0_length
1849		encode_raw(0x4489);
1850		checkpoint();
1851		break;
	2230	m_out_dip(ASSERT_LINE);
	2231	m_live_state.byte_counter--;
	2232	UINT8 headbyte = m_in_dma(0, 0xff);
	2233	write_on_track(encode(headbyte), 1, (m_live_state.byte_counter>0)? WRITE_HEADER : WRITE_HEADER_CRC);
	2234	m_out_dip(CLEAR_LINE);
	2235	m_out_dmarq(CLEAR_LINE);
	2236	// Writing will occur after the break; set the DMARQ again
	2237	if (m_live_state.byte_counter>0)
	2238	m_out_dmarq(ASSERT_LINE);
	2239	else
	2240	// we will go to WRITE_HEADER_CRC state; set the byte counter for CRC
	2241	m_live_state.byte_counter = 2;
1852	2242	}
	2243	break;
1853	2244
1854		// Ident byte (and DAM for FM)
1855		if (m_live_state.byte_counter == sector_start-1)
	2245	case WRITE_HEADER_CRC:
	2246	if (m_live_state.byte_counter > 0)
1856	2247	{
1857		if (TRACE_WRITE) logerror("%s: [%s] Write ident\n", tag(), tts(m_live_state.time).cstr());
1858		if (fm_mode())
1859		{
1860		// Init the CRC for the DAM and sector
1861		m_live_state.crc = 0xffff;
	2248	UINT8 crct = (m_live_state.crc >> 8) & 0xff;
	2249	if (TRACE_WRITE && TRACE_DETAIL) logerror("%s: Write CRC byte %02x\n", tag(), crct);
	2250	m_live_state.byte_counter--;
	2251	write_on_track(encode(crct), 1, WRITE_HEADER_CRC);
	2252	}
	2253	else
	2254	m_live_state.state = WRITE_GAP2;
1862	2255
1863		// 1111 0101 0110 1010 = F8 deleted
1864		// 1111 0101 0110 1111 = FB normal
1865		encode_raw(m_deleted? 0xf56a : 0xf56f);
1866		}
1867		else
1868		{
1869		// Init the CRC for the ident byte and sector
1870		m_live_state.crc = 0xcdb4; // value for 3*A1
1871		encode_byte(m_deleted? 0xf8 : 0xfb);
1872		}
	2256	break;
1873	2257
1874		// Set the over/underrun flag and hope that it will be cleared before we return here
1875		set_bits(m_register_r[INT_STATUS], ST_OVRUN, true);
1876		m_out_dmarq(ASSERT_LINE);
	2258	case WRITE_GAP2:
	2259	if (TRACE_WRITE && TRACE_DETAIL) logerror("%s: Writing GAP2\n", tag());
	2260	write_on_track(encode(fm_mode()? 0xff : 0x4e), m_gap2_size, WRITE_DAM_SYNC);
	2261	break;
1877	2262
1878		checkpoint();
1879		break;
	2263	case WRITE_GAP3:
	2264	m_sector_count--;
	2265	if (TRACE_WRITE && TRACE_DETAIL) logerror("%s: Writing GAP3\n", tag());
	2266	write_on_track(encode(fm_mode()? 0xff : 0x4e), m_gap3_size, (m_sector_count>0)? WRITE_IDAM_SYNC : WRITE_GAP4);
	2267	break;
	2268
	2269	case WRITE_GAP4:
	2270	// Write bytes up to the end of the track
	2271	if (TRACE_WRITE && TRACE_DETAIL && m_last_live_state != WRITE_GAP4)
	2272	{
	2273	logerror("%s: Writing GAP4\n", tag());
	2274	m_last_live_state = WRITE_GAP4;
1880	2275	}
	2276	// Write a single byte; when the index hole shows up, the live run will be aborted
	2277	write_on_track(encode(fm_mode()? 0xff : 0x4e), 1, WRITE_GAP4);
	2278	break;
1881	2279
1882		// Write the sector contents
1883		if (m_live_state.byte_counter >= sector_start && m_live_state.byte_counter < sector_end)
	2280	//  =================================================================
	2281
	2282	case READ_TRACK_BYTE:
	2283	// The pause is implemented by doing dummy reads on the floppy
	2284	if (read_one_bit(limit))
1884	2285	{
1885		// Read byte via DMA
1886		m_out_dip(ASSERT_LINE);
1887		m_register_r[DATA] = m_register_w[DATA] = m_in_dma(0, 0xff);
1888		if (TRACE_WRITE) logerror("%s: [%s] Write %02x\n", tag(), tts(m_live_state.time).cstr(), m_register_r[DATA]);
1889		encode_byte(m_register_r[DATA]);
1890		m_out_dip(CLEAR_LINE);
1891		m_out_dmarq(CLEAR_LINE);
1892
1893		if (m_live_state.byte_counter < sector_end - 1)
1894		{
1895		// Set the underrun flag and hope that it will be cleared before we return here
1896		set_bits(m_register_r[INT_STATUS], ST_OVRUN, true);
1897		m_out_dmarq(ASSERT_LINE);
1898		}
1899		checkpoint();
1900		break;
	2286	if (TRACE_LIVE) logerror("%s: [%s] return; limit=%s\n", tag(), tts(m_live_state.time).cstr(), tts(limit).cstr());
	2287	return;
1901	2288	}
1902	2289
1903		// CRC (two passes)
1904		// N.B.: when we write the first CRC byte, the value of the CRC will
1905		// change to the previous second byte, so we can write the first
1906		// byte in two iterations to get both
1907		if (m_live_state.byte_counter >= sector_end && m_live_state.byte_counter < sector_end + 2)
	2290	// Repeat until we have collected 16 bits
	2291	if ((m_live_state.bit_counter & 15)==0)
1908	2292	{
1909		if (TRACE_WRITE) logerror("%s: [%s] Write CRC\n", tag(), tts(m_live_state.time).cstr());
1910		encode_byte(m_live_state.crc >> 8);
1911		checkpoint();
1912		break;
	2293	if (TRACE_READ && TRACE_DETAIL) logerror("%s: [%s] Read byte %02x, repeat = %d\n", tag(), tts(m_live_state.time).cstr(), m_live_state.data_reg, m_live_state.repeat);
	2294	wait_for_realtime(READ_TRACK_NEXT_BYTE);
	2295	return;
1913	2296	}
	2297	break;
1914	2298
1915		// Write a FF behind
1916		if (m_live_state.byte_counter == sector_end + 2)
	2299	case READ_TRACK_NEXT_BYTE:
	2300	m_live_state.state = READ_TRACK_BYTE;
	2301	m_live_state.repeat--;
	2302	if (m_live_state.repeat == 0)
1917	2303	{
1918		encode_byte(0xff);
	2304	// All bytes read
	2305	m_live_state.state = m_live_state.return_state;
1919	2306	checkpoint();
1920		break;
1921	2307	}
	2308	break;
1922	2309
1923		// Done
1924		if (m_live_state.byte_counter > sector_end + 2)
	2310	case WRITE_TRACK_BYTE:
	2311	if (write_one_bit(limit))
	2312	return;
	2313
	2314	if (m_live_state.bit_counter == 0)
1925	2315	{
1926		if (TRACE_LIVE) logerror("%s: [%s] Write sector complete\n", tag(), tts(m_live_state.time).cstr());
1927		m_pll.stop_writing(m_floppy, m_live_state.time);
1928		m_live_state.state = IDLE;
	2316	// All bits written; get the next byte into the shift register
	2317	wait_for_realtime(WRITE_TRACK_NEXT_BYTE);
1929	2318	return;
1930	2319	}
1931		}
	2320	break;
1932	2321
	2322	case WRITE_TRACK_NEXT_BYTE:
	2323	m_live_state.state = WRITE_TRACK_BYTE;
	2324	m_live_state.repeat--;
	2325
	2326	// Write all bytes
	2327	if (m_live_state.repeat == 0)
	2328	{
	2329	// All bytes written
	2330	m_live_state.state = m_live_state.return_state;
	2331	checkpoint();
	2332	}
	2333	else
	2334	encode_again();
	2335
	2336	break;
	2337
	2338	case NO_DMA_ACK:
	2339	if (TRACE_FAIL) logerror("%s: No DMA ACK - buffer underrun\n", tag());
	2340	set_bits(m_register_r[INT_STATUS], TC_DATAERR, true);
	2341	m_pll.stop_writing(m_floppy, m_live_state.time);
	2342	m_live_state.state = IDLE;
	2343	return;
	2344
1933	2345	default:
1934	2346	logerror("%s: Unknown live state: %02x\n", tag(), m_live_state.state);
1935	2347	m_last_live_state = m_live_state.state;
r32282	r32283
1953	2365	if(m_live_state.time > machine().time())
1954	2366	{
1955	2367	// If so, we must roll back to the last checkpoint
1956		if (TRACE_LIVE) logerror("%s: [%s] Rolling back and replaying (%s)\n", tag(), ttsn().cstr(), tts(m_live_state.time).cstr());
	2368	if (TRACE_SYNC) logerror("%s: [%s] Rolling back and replaying (%s)\n", tag(), ttsn().cstr(), tts(m_live_state.time).cstr());
1957	2369	rollback();
1958	2370	// and replay until we reach the machine time
1959	2371	live_run_until(machine().time());
1960		// Caught up, commit that
	2372	// Caught up, write on floppy image
1961	2373	m_pll.commit(m_floppy, m_live_state.time);
1962	2374	}
1963	2375	else
1964	2376	{
1965	2377	// We are behind machine time, so we will never get back to that
1966	2378	// time, thus we can commit that position
1967		if (TRACE_LIVE) logerror("%s: [%s] Committing (%s)\n", tag(), ttsn().cstr(), tts(m_live_state.time).cstr());
	2379	if (TRACE_SYNC) logerror("%s: [%s] Committing (%s)\n", tag(), ttsn().cstr(), tts(m_live_state.time).cstr());
	2380	// Write on floppy image
1968	2381	m_pll.commit(m_floppy, m_live_state.time);
1969	2382
1970	2383	if (m_live_state.next_state != -1)
r32282	r32283
1984	2397	}
1985	2398	}
1986	2399
	2400	void hdc9234_device::live_abort()
	2401	{
	2402	if (!m_live_state.time.is_never() && m_live_state.time > machine().time())
	2403	{
	2404	if (TRACE_LIVE) logerror("%s: Abort; rolling back and replaying (%s)\n", ttsn().cstr(), tts(m_live_state.time).cstr());
	2405	rollback();
	2406	live_run_until(machine().time());
	2407	}
	2408
	2409	m_pll.stop_writing(m_floppy, m_live_state.time);
	2410	m_live_state.time = attotime::never;
	2411	m_live_state.state = IDLE;
	2412	m_live_state.next_state = -1;
	2413	}
	2414
	2415	/*
	2416	Brings the live state machine into the WRITE substate part
	2417	comprised by WRITE_TRACK_(NEXT_)BYTE
	2418	Arguments: byte to be written, number, state on return
	2419	*/
	2420	void hdc9234_device::write_on_track(UINT16 encoded, int repeat, int next_state)
	2421	{
	2422	m_live_state.repeat = repeat;
	2423	m_live_state.state = WRITE_TRACK_BYTE;
	2424	m_live_state.return_state = next_state;
	2425	encode_raw(encoded);
	2426	}
	2427
	2428	/*
	2429	Brings the live state machine into the READ substate part. This is
	2430	only intended for skipping bytes.
	2431	Arguments: number, state on return
	2432	*/
	2433	void hdc9234_device::skip_on_track(int repeat, int next_state)
	2434	{
	2435	m_live_state.bit_counter = 0;
	2436	m_live_state.repeat = repeat;
	2437	m_live_state.state = READ_TRACK_BYTE;
	2438	m_live_state.return_state = next_state;
	2439	}
	2440
	2441	UINT8 hdc9234_device::get_data_from_encoding(UINT16 raw)
	2442	{
	2443	return (raw & 0x4000 ? 0x80 : 0x00) |
	2444	(raw & 0x1000 ? 0x40 : 0x00) |
	2445	(raw & 0x0400 ? 0x20 : 0x00) |
	2446	(raw & 0x0100 ? 0x10 : 0x00) |
	2447	(raw & 0x0040 ? 0x08 : 0x00) |
	2448	(raw & 0x0010 ? 0x04 : 0x00) |
	2449	(raw & 0x0004 ? 0x02 : 0x00) |
	2450	(raw & 0x0001 ? 0x01 : 0x00);
	2451	}
	2452
1987	2453	void hdc9234_device::rollback()
1988	2454	{
1989	2455	m_live_state = m_checkpoint_state;
r32282	r32283
2067	2533	return false;
2068	2534	}
2069	2535
2070		/*
2071		Encode a byte for FM or MFM recording. Result is returned in the
2072		shift register of m_live_state.
2073		*/
2074		void hdc9234_device::encode_byte(UINT8 byte)
	2536	UINT16 hdc9234_device::encode(UINT8 byte)
2075	2537	{
2076	2538	UINT16 raw;
2077	2539	UINT8 check_pos;
r32282	r32283
2111	2573	check_pos >>= 1;
2112	2574	}
2113	2575	}
2114		m_live_state.last_data_bit = last_bit_set;
2115		m_live_state.shift_reg = raw;
2116	2576	m_live_state.data_reg = byte;
	2577	return raw;
2117	2578	}
2118	2579
	2580	/*
	2581	Encode a byte for FM or MFM recording. Result is returned in the
	2582	shift register of m_live_state.
	2583	*/
	2584	void hdc9234_device::encode_byte(UINT8 byte)
	2585	{
	2586	UINT16 raw = encode(byte);
	2587	m_live_state.bit_counter = 16;
	2588	m_live_state.last_data_bit = raw & 1;
	2589	m_live_state.shift_reg = m_live_state.shift_reg_save = raw;
	2590	if (TRACE_WRITE && TRACE_DETAIL) logerror("%s: [%s] Write %02x (%04x)\n", tag(), tts(m_live_state.time).cstr(), byte, raw);
	2591	checkpoint();
	2592	}
	2593
	2594	void hdc9234_device::encode_again()
	2595	{
	2596	encode_raw(m_live_state.shift_reg_save);
	2597	}
	2598
2119	2599	void hdc9234_device::encode_raw(UINT16 raw)
2120	2600	{
2121		m_live_state.shift_reg = raw;
	2601	m_live_state.bit_counter = 16;
	2602	m_live_state.shift_reg = m_live_state.shift_reg_save = raw;
2122	2603	m_live_state.last_data_bit = raw & 1;
	2604	if (TRACE_WRITE && TRACE_DETAIL) logerror("%s: [%s] Write %02x (%04x)\n", tag(), tts(m_live_state.time).cstr(), get_data_from_encoding(raw), raw);
	2605	checkpoint();
2123	2606	}
2124	2607
2125	2608	void hdc9234_device::pll_reset(const attotime &when)
r32282	r32283
2131	2614
2132	2615	void hdc9234_device::checkpoint()
2133	2616	{
	2617	// Write on floppy image
2134	2618	m_pll.commit(m_floppy, m_live_state.time);
2135	2619	m_checkpoint_state = m_live_state;
2136	2620	m_checkpoint_pll = m_pll;
r32282	r32283
2159	2643	{
2160	2644	// Data register
2161	2645	reply = m_register_r[m_register_pointer];
2162		if (TRACE_REG) logerror("%s: read register[%d] -> %02x\n", tag(), m_register_pointer, reply);
	2646	if (TRACE_READREG) logerror("%s: read register[%d] -> %02x\n", tag(), m_register_pointer, reply);
2163	2647
2164	2648	// Autoincrement until DATA is reached.
2165	2649	if (m_register_pointer < DATA)  m_register_pointer++;
r32282	r32283
2171	2655
2172	2656	// "The interrupt pin is reset to its inactive state
2173	2657	// when the UDC interrupt status register is read." [1] (p.3)
2174		if (TRACE_REG) logerror("%s: read interrupt status register -> %02x\n", tag(), reply);
	2658	if (TRACE_READREG) logerror("%s: read interrupt status register -> %02x\n", tag(), reply);
2175	2659	set_interrupt(CLEAR_LINE);
2176	2660
2177	2661	// Clear the bits due to interrupt status register read.
r32282	r32283
2217	2701	{
2218	2702	// Writing data to registers
2219	2703	// Data register
2220		if (TRACE_REG)
	2704	if (TRACE_SETREG)
2221	2705	{
2222	2706	if (m_register_pointer == INT_COMM_TERM)
2223	2707	logerror("%s: Setting interrupt trigger DONE=%d READY=%d\n", tag(), (m_regvalue & TC_INTDONE)? 1:0, (m_regvalue & TC_INTRDCH)? 1:0);
r32282	r32283
2367	2851	if (m_wait_for_index) m_stop_after_index = true;
2368	2852	}
2369	2853
	2854	if (m_event_line == INDEX_LINE && level == m_line_level && m_state_after_line != UNDEF)
	2855	{
	2856	if (TRACE_LINES) logerror("%s: [%s] Index pulse level=%d triggers event\n", tag(), ttsn().cstr(), level);
	2857	m_substate = m_state_after_line;
	2858	m_state_after_line = UNDEF;
	2859	if (m_stopwrite)
	2860	{
	2861	m_pll.stop_writing(m_floppy, m_live_state.time);
	2862	m_live_state.state = IDLE;
	2863	}
	2864	}
	2865
2370	2866	reenter_command_processing();
2371	2867	}
2372	2868
r32282	r32283
2387	2883	set_interrupt(ASSERT_LINE);
2388	2884	}
2389	2885
2390		// reenter_command_processing();
	2886	if (m_event_line == READY_LINE && level == m_line_level && m_state_after_line != UNDEF)
	2887	{
	2888	m_substate = m_state_after_line;
	2889	m_state_after_line = UNDEF;
	2890	reenter_command_processing();
	2891	}
2391	2892	}
2392	2893
2393	2894	void hdc9234_device::seek_complete_callback(int level)
r32282	r32283
2397	2898	// Synchronize our position on the track
2398	2899	live_sync();
2399	2900
2400		if (level==ASSERT_LINE && m_state_after_line != UNDEF)
	2901	if (m_event_line == SEEKCOMP_LINE && level == m_line_level && m_state_after_line != UNDEF)
2401	2902	{
2402	2903	m_substate = m_state_after_line;
2403	2904	m_state_after_line = UNDEF;
r32282	r32283
2405	2906	}
2406	2907	}
2407	2908
2408		void hdc9234_device::wait_line(int substate)
	2909	/*
	2910	Set the hook for line level handling
	2911	*/
	2912	void hdc9234_device::wait_line(int line, line_state level, int substate, bool stopwrite)
2409	2913	{
	2914	m_event_line = line;
	2915	m_line_level = level;
2410	2916	m_state_after_line = substate;
	2917	m_stopwrite = stopwrite;
2411	2918	}
2412	2919
2413		bool hdc9234_device::on_track00()
2414		{
2415		return (m_register_r[DRIVE_STATUS] & HDC_DS_TRK00)!=0;
2416		}
2417
2418	2920	/*
2419	2921	Push the output registers over the auxiliary bus. It is expected that
2420	2922	the PCB contains latches to store the values.
r32282	r32283
2443	2945	*/
2444	2946	void hdc9234_device::auxbus_out()
2445	2947	{
2446		m_output1 = (m_selected_drive_number != NODRIVE)? (0x10 << m_selected_drive_number) : 0;
2447		m_output1 |= (m_register_w[RETRY_COUNT]&0x0f);
2448
2449		if (TRACE_AUXBUS) logerror("%s: Setting OUTPUT1 to %02x\n", tag(), m_output1);
2450	2948	m_out_auxbus((offs_t)HDC_OUTPUT_1, m_output1);
2451	2949
2452	2950	// prepare output2
r32282	r32283
2459	2957	m_out_auxbus((offs_t)HDC_OUTPUT_2, m_output2);
2460	2958	}
2461	2959
2462		void hdc9234_device::dma_address_out()
	2960	void hdc9234_device::dma_address_out(UINT8 addrub, UINT8 addrhb, UINT8 addrlb)
2463	2961	{
2464		if (TRACE_ACT) logerror("%s: Setting DMA address %06x\n", tag(), (m_register_w[DMA23_16]<<16 | m_register_w[DMA15_8]<<8 | m_register_w[DMA7_0])&0xffffff);
2465		m_out_auxbus((offs_t)HDC_OUTPUT_DMA_ADDR, m_register_w[DMA23_16]);
2466		m_out_auxbus((offs_t)HDC_OUTPUT_DMA_ADDR, m_register_w[DMA15_8]);
2467		m_out_auxbus((offs_t)HDC_OUTPUT_DMA_ADDR, m_register_w[DMA7_0]);
	2962	if (TRACE_DMA) logerror("%s: Setting DMA address %06x\n", tag(), (addrub<<16 | addrhb<<8 | addrlb)&0xffffff);
	2963	m_out_auxbus((offs_t)HDC_OUTPUT_DMA_ADDR, addrub);
	2964	m_out_auxbus((offs_t)HDC_OUTPUT_DMA_ADDR, addrhb);
	2965	m_out_auxbus((offs_t)HDC_OUTPUT_DMA_ADDR, addrlb);
2468	2966	}
2469	2967
2470	2968	/*
r32282	r32283
2495	2993	{
2496	2994	if (state==ASSERT_LINE)
2497	2995	{
2498		if (TRACE_LIVE) logerror("%s: [%s] DMA acknowledged\n", tag(), ttsn().cstr());
	2996	if (TRACE_DMA) logerror("%s: [%s] DMA acknowledged\n", tag(), ttsn().cstr());
2499	2997	set_bits(m_register_r[INT_STATUS], ST_OVRUN, false);
2500	2998	}
2501	2999	}
r32282	r32283
2533	3031	{
2534	3032	m_deleted = false;
2535	3033	m_executing = false;
	3034	m_event_line = UNDEF;
2536	3035	m_initialized = true;
	3036	m_line_level = CLEAR_LINE;
2537	3037	m_live_state.state = IDLE;
2538	3038	m_live_state.time = attotime::never;
2539	3039	m_multi_sector = false;

trunk/src/emu/machine/hdc9234.h

r32282	r32283
138	138	void auxbus_out();
139	139
140	140	// Write the DMA address to the external latches
141		void dma_address_out();
	141	void dma_address_out(UINT8 addrub, UINT8 addrhb, UINT8 addrlb);
142	142
143	143	// Intermediate storage for register
144	144	UINT8 m_regvalue;
r32282	r32283
165	165	void index_callback(int level);
166	166	void seek_complete_callback(int level);
167	167
168		// Wait for some time to pass or for a line to be raised
	168	// Wait for some time to pass or for a line to change level
169	169	void wait_time(emu_timer *tm, int microsec, int next_substate);
170	170	void wait_time(emu_timer *tm, attotime delay, int param);
171		void wait_line(int substate);
	171	void wait_line(int line, line_state level, int substate, bool stopwrite);
172	172
173	173	// Converts attotime to a string
174	174	astring tts(const attotime &t);
r32282	r32283
179	179	// Utility routine to set or reset bits
180	180	void set_bits(UINT8& byte, int mask, bool set);
181	181
	182	// Event handling
	183	line_state m_line_level;
	184	int m_event_line;
	185	int m_state_after_line;
	186
182	187	// ==============================================
183	188	//   Live state machine
184	189	// ==============================================
r32282	r32283
187	192	{
188	193	attotime time;
189	194	UINT16 shift_reg;
	195	UINT16 shift_reg_save;
190	196	UINT16 crc;
191	197	int bit_counter;
192	198	int bit_count_total;    // used for timeout handling
r32282	r32283
196	202	UINT8 data_reg;
197	203	int state;
198	204	int next_state;
	205	int repeat; // for formatting
	206	int return_state; // for formatting
199	207	};
200	208
201	209	live_info m_live_state, m_checkpoint_state;
r32282	r32283
213	221	// Control functions for syncing the track analyser with the machine time
214	222	void wait_for_realtime(int state);
215	223	void live_sync();
	224	void live_abort();
216	225	void rollback();
217	226	void checkpoint();
218	227
	228	// Delivers the data bits from the given encoding
	229	UINT8 get_data_from_encoding(UINT16 raw);
	230
219	231	// ==============================================
220	232	//    PLL functions and interface to floppy
221	233	// ==============================================
r32282	r32283
234	246	// shift_reg, and last_data_bit
235	247	void encode_raw(UINT16 word);
236	248
	249	// Encodes a byte in FM or MFM. Called by encode_byte.
	250	UINT16 encode(UINT8 byte);
	251
	252	// Encode the latest byte again
	253	void encode_again();
	254
237	255	// Reads from the current position on the track
238	256	bool read_one_bit(const attotime &limit);
239	257
240	258	// Writes to the current position on the track
241	259	bool write_one_bit(const attotime &limit);
242	260
	261	// Writes to the current position on the track
	262	void write_on_track(UINT16 raw, int count, int next_state);
	263
	264	// Skips bytes on the track
	265	void skip_on_track(int count, int next_state);
	266
243	267	// ==============================================
244	268	//   Command state machine
245	269	// ==============================================
246	270
247	271	int m_substate;
248		int m_state_after_line;
249	272
250	273	typedef void (hdc9234_device::*cmdfunc)(void);
251	274
r32282	r32283
311	334	// Used in RESTORE to find out when to give up
312	335	int m_seek_count;
313	336
	337	// Signals to abort writing
	338	bool m_stopwrite;
	339
	340	// Used for formatting
	341	int m_sector_count;
	342	int m_sector_size;
	343	int m_gap0_size;
	344	int m_gap1_size;
	345	int m_gap2_size;
	346	int m_gap3_size;
	347	int m_sync_size;
	348
314	349	// Are we in FM mode?
315	350	bool fm_mode();
316	351
r32282	r32283
363	398	// ===================================================
364	399
365	400	void reset_controller();
366		void drive_select();
367	401	void drive_deselect();
368	402	void restore_drive();
369	403	void step_drive();
	404	void tape_backup();
	405	void poll_drives();
	406	void drive_select();
370	407	void set_register_pointer();
	408	void seek_read_id();
371	409	void read_sectors();
372		void write_sector_logical();
	410	void read_track();
	411	void format_track();
	412	void write_sectors();
373	413	};
374	414
375	415	#endif

trunk/src/emu/bus/ti99_peb/hfdc.c

r32282	r32283
29	29	never was a support from the DSR (firmware), so this feature was eliminated
30	30	in later releases.
31	31
	32	DIP switches
	33	- Settings for step rate and track count for each floppy drive (DSK1-DSK4)
	34	- CRU base address. Note that only on all other addresses than 1100, the
	35	floppy drives are labeled DSK5-DSK8 by the card software.
	36
	37
32	38	Components
33	39
34	40	HDC 9234      - Universal Disk Controller
r32282	r32283
43	49	Author: Michael Zapf
44	50	September 2014: Rewritten for modern floppy implementation
45	51
	52	References:
	53	[1] Myarc Inc.: Hard and Floppy Disk Controller / Users Manual
	54
46	55	WORK IN PROGRESS
47	56
48	57	*****************************************************************************/
49	58
50		/*
51		FIXME: HFDC does not work at CRU addresses other than 1100
52		(test shows
53		hfdc: reado 41f5 (00): 00
54		hfdc: reado 41f4 (00): 00 -> wrong rom page? (should be (02)))
55		*/
56
57	59	#include "emu.h"
58	60	#include "peribox.h"
59	61	#include "hfdc.h"
r32282	r32283
181	183	0x4fd0 - 0x4fdf HDC 9234 ports
182	184	0x4fe0 - 0x4fff RTC chip ports
183	185
184		0x5000 - 0x53ff static RAM page 0x10
	186	0x5000 - 0x53ff static RAM page 0x08
185	187	0x5400 - 0x57ff static RAM page any of 32 pages
186	188	0x5800 - 0x5bff static RAM page any of 32 pages
187	189	0x5c00 - 0x5fff static RAM page any of 32 pages
r32282	r32283
320	322
321	323	m_see_switches == true:
322	324
323		7     6     5     4     3     2     1     0
	325	7     6     5     4     3     2     1     0      CRU bit
324	326	+-----+-----+-----+-----+-----+-----+-----+-----+
325		|DIP1*|DIP2*|DIP3*|DIP4*|DIP5*|DIP6*|DIP7*|DIP8*|
	327	|DIP5*|DIP6*|DIP7*|DIP8*|DIP1*|DIP2*|DIP3*|DIP4*|
326	328	+-----+-----+-----+-----+-----+-----+-----+-----+
	329	|   DSK3    |   DSK4    |   DSK1    |   DSK2    |
	330	+-----+-----+-----+-----+-----+-----+-----+-----+
327	331
328		MZ: The setting 00 (all switches on) is a valid setting according to the
329		HFDC manual and indicates 36 sectors/track, 80 tracks; however, this
330		setting is intended "for possible future expansion" and cannot fall
331		back to lower formats, hence, single density disks cannot be read.
	332	Settings for DSKn: (n=1..4)
	333
	334	DIP(2n-1) DIP(2n)   Tracks     Step(ms)    Sectors (256 byte)
	335	off       off        40        16          18/16/9
	336	on        off        40        8           18/16/9
	337	off       on         80/40     2           18/16/9
	338	on        on         80        2           36
	339
	340	Inverted logic: switch=on means a 0 bit, off is a 1 bit when read by the CRU
	341
	342	Caution: The last setting is declared as "future expansion" and is
	343	locked to a 1.44 MiB capacity. No lower formats can be used.
	344
332	345	---
333	346
334	347	m_see_switches == false:
r32282	r32283
353	366	{
354	367	if (m_see_switches)
355	368	{
356		// DIP switches.  Logic levels are inverted (on->0, off->1).  CRU
357		// bit order is the reverse of DIP-switch order, too (dip 1 -> bit 7,
358		// dip 8 -> bit 0).
359		// MZ: 00 should not be used since there is a bug in the
360		// DSR of the HFDC which causes problems with SD disks
361		// (controller tries DD and then fails to fall back to SD) */
362	369	reply = ~(ioport("HFDCDIP")->read());
363	370	}
364	371	else
r32282	r32283
384	391
385	392	7     6     5     4     3     2     1     0
386	393	+-----+-----+-----+-----+-----+-----+-----+-----+
387		|  0  | MON | DIP | ROM1| ROM0| MON | RES*| SEL |
	394	|  -  |  -  | - | ROM1| ROM0| MON | RES*| SEL |
388	395	|     |     |     | CSEL| CD1 | CD0 |     |     |
389	396	+-----+-----+-----+-----+-----+-----+-----+-----+
390	397
r32282	r32283
449	456
450	457	// Activate motor
451	458	// When 1, let motor run continuously. When 0, a simple monoflop circuit keeps the line active for another 4 sec
452		// We keep triggering the monoflop for data==1
453	459	if (data==1)
454	460	{
455		if (TRACE_CRU) logerror("%s: trigger motor\n", tag());
	461	m_motor_on_timer->reset();
456	462	set_floppy_motors_running(true);
457	463	}
	464	else
	465	{
	466	m_motor_on_timer->adjust(attotime::from_msec(4230));
	467	}
458	468	m_lastval = data;
459	469	break;
460	470
r32282	r32283
667	677	// READY is asserted when DSKx = 1
668	678	// The controller fetches the state with the auxbus access
669	679	if (TRACE_LINES) logerror("%s: Connect index callback DSK%d\n", tag(), index+1);
670		m_current_floppy->setup_index_pulse_cb(floppy_image_device::index_pulse_cb(FUNC(myarc_hfdc_device::floppy_index_callback), this));
	680	if (m_current_floppy != NULL)
	681	m_current_floppy->setup_index_pulse_cb(floppy_image_device::index_pulse_cb(FUNC(myarc_hfdc_device::floppy_index_callback), this));
	682	else
	683	logerror("%s: Connection to DSK%d failed because no drive is connected\n", tag(), index+1);
671	684	m_hdc9234->connect_floppy_drive(m_floppy_unit[index]);
672	685	}
673	686	}
r32282	r32283
704	717	if (TRACE_MOTOR)
705	718	if (m_MOTOR_ON==CLEAR_LINE) logerror("%s: Motor START\n", tag());
706	719	m_MOTOR_ON = ASSERT_LINE;
707		m_motor_on_timer->adjust(attotime::from_msec(4230));
708	720	}
709	721	else
710	722	{
r32282	r32283
759	771	READ8_MEMBER( myarc_hfdc_device::read_buffer )
760	772	{
761	773	if (TRACE_DMA) logerror("%s: Read access to onboard SRAM at %04x\n", tag(), m_dma_address);
	774	if (m_dma_address > 0x8000) logerror("%s: Read access beyond RAM size: %06x\n", tag(), m_dma_address);
762	775	UINT8 value = m_buffer_ram[m_dma_address & 0x7fff];
763	776	m_dma_address = (m_dma_address+1) & 0x7fff;
764	777	return value;
r32282	r32283
770	783	WRITE8_MEMBER( myarc_hfdc_device::write_buffer )
771	784	{
772	785	if (TRACE_DMA) logerror("%s: Write access to onboard SRAM at %04x: %02x\n", tag(), m_dma_address, data);
	786	if (m_dma_address > 0x8000) logerror("%s: Write access beyond RAM size: %06x\n", tag(), m_dma_address);
773	787	m_buffer_ram[m_dma_address & 0x7fff] = data;
774	788	m_dma_address = (m_dma_address+1) & 0x7fff;
775	789	}
r32282	r32283
845	859	if (subdevice("3")!=NULL) m_floppy_unit[3] = static_cast<floppy_image_device*>(subdevice("3")->first_subdevice());
846	860	}
847	861
	862	/*
	863	The HFDC controller can be configured for different CRU base addresses,
	864	but DSK1-DSK4 are only available for CRU 1100. For all other addresses,
	865	the drives 1 to 4 are renamed to DSK5-DSK8 (see [1] p. 7).
	866	*/
848	867	INPUT_PORTS_START( ti99_hfdc )
849	868	PORT_START( "CRUHFDC" )
850	869	PORT_DIPNAME( 0x1f00, 0x1100, "HFDC CRU base" )
r32282	r32283
866	885	PORT_DIPSETTING( 0x1f00, "1F00" )
867	886
868	887	PORT_START( "HFDCDIP" )
869		PORT_DIPNAME( 0xff, 0x00, "HFDC drive config" )
	888	PORT_DIPNAME( 0x0c, 0x00, "HFDC drive 1 config" )
870	889	PORT_DIPSETTING( 0x00, "40 track, 16 ms")
871		PORT_DIPSETTING( 0xaa, "40 track, 8 ms")
872		PORT_DIPSETTING( 0x55, "80 track, 2 ms")
873		PORT_DIPSETTING( 0xff, "80 track HD, 2 ms")
	890	PORT_DIPSETTING( 0x08, "40 track, 8 ms")
	891	PORT_DIPSETTING( 0x04, "80 track, 2 ms")
	892	PORT_DIPSETTING( 0x0c, "80 track HD, 2 ms")
	893	PORT_DIPNAME( 0x03, 0x00, "HFDC drive 2 config" )
	894	PORT_DIPSETTING( 0x00, "40 track, 16 ms")
	895	PORT_DIPSETTING( 0x02, "40 track, 8 ms")
	896	PORT_DIPSETTING( 0x01, "80 track, 2 ms")
	897	PORT_DIPSETTING( 0x03, "80 track HD, 2 ms")
	898	PORT_DIPNAME( 0xc0, 0x00, "HFDC drive 3 config" )
	899	PORT_DIPSETTING( 0x00, "40 track, 16 ms")
	900	PORT_DIPSETTING( 0x80, "40 track, 8 ms")
	901	PORT_DIPSETTING( 0x40, "80 track, 2 ms")
	902	PORT_DIPSETTING( 0xc0, "80 track HD, 2 ms")
	903	PORT_DIPNAME( 0x30, 0x00, "HFDC drive 4 config" )
	904	PORT_DIPSETTING( 0x00, "40 track, 16 ms")
	905	PORT_DIPSETTING( 0x20, "40 track, 8 ms")
	906	PORT_DIPSETTING( 0x10, "80 track, 2 ms")
	907	PORT_DIPSETTING( 0x30, "80 track HD, 2 ms")
874	908	INPUT_PORTS_END
875	909
876	910	FLOPPY_FORMATS_MEMBER(myarc_hfdc_device::floppy_formats)

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