Previous

199869 Revisions

Next

r32163 Thursday 18th September, 2014 at 01:07:22 UTC by Alex Jackson

Memory system and Namco improvements: [Alex Jackson] Explicit regions in address maps (AM_REGION) are now looked up relative to the device rather than as siblings when in an internal address map (similar to devices and shared pointers)  Besides being more orthogonal than before, this allows internal ROMs of MCUs and similar devices to be hooked up in a nicer and more foolproof way. Updated the m37710 and m5074x (m6502 derivative) to take advantage of this. Divided the M37702/M37710 into specific models, with each model having its own internal address map containing the correct amounts of internal RAM and ROM. M37702 MCUs found on various Namco PCBs are now all unique devices and have their respective internal ROMs loaded as device ROMs. (nw) Also did some spring (fall) cleaning in addrmap.c/memory.c/dimemory.c m_devbase (the base device used for tagmap lookup when late-binding handlers and finding memory regions and shares) is now a reference rather than a pointer, since we know what it is when the address_map_entry is constructed and it doesn't change (it depends solely on whether it's an entry in an MCFG-provided address map or an internal one) And for the same reason, there's now only one m_devbase per address_map_entry rather than individual copies for read/write/setoffset/sharedptr. Removed mysterious unused address_map_entry member "m_region_string", along with a silly assert probably left over from when Aaron was replacing AM_BASE with AM_SHARE years ago. Added a comment noting that "make sure all devices exist" in device_memory_interface::interface_validity_check() actually does nothing, like the proverbial goggles. The reason there's just a comment and not a fix is I haven't figured out how to fix it yet (is it possible to extract the original device tag that was given to a proto-delegate? Sorry, the template hell in devdelegate.h and lib/util/delegate.h makes me want to run screaming like a little girl)

[src/emu]	addrmap.c addrmap.h dimemory.c memory.c
[src/emu/cpu/m37710]	m37710.c m37710.h
[src/emu/cpu/m6502]	m5074x.c
[src/emu/debug]	debugcmd.c
[src/mame]	mame.mak
[src/mame/drivers]	globalfr.c namcofl.c namcona1.c namconb1.c namcos11.c namcos22.c
[src/mame/machine]	namcomcu.c* namcomcu.h*
[src/mess/drivers]	apple2gs.c

trunk/src/emu/debug/debugcmd.c

r32162	r32163
1995	1995	{
1996	1996	cheat_region[region_count].offset = space->address_to_byte(entry->m_addrstart) & space->bytemask();
1997	1997	cheat_region[region_count].endoffset = space->address_to_byte(entry->m_addrend) & space->bytemask();
1998		cheat_region[region_count].share = entry->m_sharetag;
	1998	cheat_region[region_count].share = entry->m_share;
1999	1999	cheat_region[region_count].disabled = (entry->m_write.m_type == AMH_RAM) ? FALSE : TRUE;
2000	2000
2001	2001	/* disable double share regions */
2002		if (entry->m_sharetag != NULL)
	2002	if (entry->m_share != NULL)
2003	2003	for (i = 0; i < region_count; i++)
2004	2004	if (cheat_region[i].share != NULL)
2005		if (strcmp(cheat_region[i].share, entry->m_sharetag) == 0)
	2005	if (strcmp(cheat_region[i].share, entry->m_share) == 0)
2006	2006	cheat_region[region_count].disabled = TRUE;
2007	2007
2008	2008	region_count++;

trunk/src/emu/cpu/m6502/m5074x.c

r32162	r32163
39	39	//-------------------------------------------------
40	40	m5074x_device::m5074x_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, address_map_constructor internal_map, const char *shortname, const char *source) :
41	41	m740_device(mconfig, type, name, tag, owner, clock, shortname, source),
42		m_program_config("program", ENDIANNESS_LITTLE, 8, 16, 0, internal_map),
	42	m_program_config("program", ENDIANNESS_LITTLE, 8, 13, 0, internal_map),
43	43	read_p0(*this),
44	44	read_p1(*this),
45	45	read_p2(*this),
r32162	r32163
470	470
471	471	/* M50740 - baseline for this familiy */
472	472	static ADDRESS_MAP_START( m50740_map, AS_PROGRAM, 8, m50740_device )
473		ADDRESS_MAP_GLOBAL_MASK(0x1fff)
474	473	AM_RANGE(0x0000, 0x005f) AM_RAM
475	474	AM_RANGE(0x00e0, 0x00e9) AM_READWRITE(ports_r, ports_w)
476	475	AM_RANGE(0x00f9, 0x00ff) AM_READWRITE(tmrirq_r, tmrirq_w)
477		AM_RANGE(0x1400, 0x1fff) AM_ROM AM_REGION(":m50740", 0)
	476	AM_RANGE(0x1400, 0x1fff) AM_ROM AM_REGION("internal", 0)
478	477	ADDRESS_MAP_END
479	478
480	479	m50740_device::m50740_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
r32162	r32163
489	488
490	489	/* M50741 - 50740 with a larger internal ROM */
491	490	static ADDRESS_MAP_START( m50741_map, AS_PROGRAM, 8, m50741_device )
492		ADDRESS_MAP_GLOBAL_MASK(0x1fff)
493	491	AM_RANGE(0x0000, 0x005f) AM_RAM
494	492	AM_RANGE(0x00e0, 0x00e9) AM_READWRITE(ports_r, ports_w)
495	493	AM_RANGE(0x00f9, 0x00ff) AM_READWRITE(tmrirq_r, tmrirq_w)
496		AM_RANGE(0x1000, 0x1fff) AM_ROM AM_REGION(":m50741", 0)
	494	AM_RANGE(0x1000, 0x1fff) AM_ROM AM_REGION("internal", 0)
497	495	ADDRESS_MAP_END
498	496
499	497	m50741_device::m50741_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :

trunk/src/emu/cpu/m37710/m37710.c

r32162	r32163
60	60	#define M37710_DEBUG    (0) // enables verbose logging for peripherals, etc.
61	61
62	62
63		const device_type M37710 = &device_creator<m37710_cpu_device>;
64		const device_type M37702 = &device_creator<m37702_cpu_device>;
	63	const device_type M37702M2 = &device_creator<m37702m2_device>;
	64	const device_type M37702S1 = &device_creator<m37702s1_device>;
	65	const device_type M37710S4 = &device_creator<m37710s4_device>;
65	66
66	67
67		// On-board RAM and peripherals
68		static ADDRESS_MAP_START( m37710_internal_map, AS_PROGRAM, 16, m37710_cpu_device )
	68	// On-board RAM, ROM, and peripherals
	69
	70	// M37702M2: 512 bytes internal RAM, 16K internal mask ROM
	71	// (M37702E2: same with EPROM instead of mask ROM)
	72	DEVICE_ADDRESS_MAP_START( map, 16, m37702m2_device )
69	73	AM_RANGE(0x000000, 0x00007f) AM_READWRITE(m37710_internal_word_r, m37710_internal_word_w)
70	74	AM_RANGE(0x000080, 0x00027f) AM_RAM
	75	AM_RANGE(0x00c000, 0x00ffff) AM_ROM AM_REGION("internal", 0)
71	76	ADDRESS_MAP_END
72	77
73	78
74		m37710_cpu_device::m37710_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
75		: cpu_device(mconfig, M37710, "M37710", tag, owner, clock, "m37710", __FILE__)
76		, m_program_config("program", ENDIANNESS_LITTLE, 16, 24, 0, ADDRESS_MAP_NAME(m37710_internal_map))
	79	// M37702S1: 512 bytes internal RAM, no internal ROM
	80	DEVICE_ADDRESS_MAP_START( map, 16, m37702s1_device )
	81	AM_RANGE(0x000000, 0x00007f) AM_READWRITE(m37710_internal_word_r, m37710_internal_word_w)
	82	AM_RANGE(0x000080, 0x00027f) AM_RAM
	83	ADDRESS_MAP_END
	84
	85
	86	// M37710S4: 2048 bytes internal RAM, no internal ROM
	87	DEVICE_ADDRESS_MAP_START( map, 16, m37710s4_device )
	88	AM_RANGE(0x000000, 0x00007f) AM_READWRITE(m37710_internal_word_r, m37710_internal_word_w)
	89	AM_RANGE(0x000080, 0x00087f) AM_RAM
	90	ADDRESS_MAP_END
	91
	92	// many other combinations of RAM and ROM size exist
	93
	94
	95	m37710_cpu_device::m37710_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, address_map_delegate map_delegate)
	96	: cpu_device(mconfig, type, name, tag, owner, clock, shortname, source)
	97	, m_program_config("program", ENDIANNESS_LITTLE, 16, 24, 0, map_delegate)
77	98	, m_io_config("io", ENDIANNESS_LITTLE, 8, 16, 0)
78	99	{
79	100	}
80	101
81	102
82		m37710_cpu_device::m37710_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
83		: cpu_device(mconfig, type, name, tag, owner, clock, shortname, source)
84		, m_program_config("program", ENDIANNESS_LITTLE, 16, 24, 0, ADDRESS_MAP_NAME(m37710_internal_map))
85		, m_io_config("io", ENDIANNESS_LITTLE, 8, 16, 0)
	103	m37702m2_device::m37702m2_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	104	: m37710_cpu_device(mconfig, M37702M2, "M37702M2", tag, owner, clock, "m37702m2", __FILE__, address_map_delegate(FUNC(m37702m2_device::map), this))
86	105	{
87	106	}
88	107
89	108
90		m37702_cpu_device::m37702_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
91		: m37710_cpu_device(mconfig, M37702, "M37702", tag, owner, clock, "m37702", __FILE__)
	109	m37702m2_device::m37702m2_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
	110	: m37710_cpu_device(mconfig, type, name, tag, owner, clock, shortname, source, address_map_delegate(FUNC(m37702m2_device::map), this))
92	111	{
93	112	}
94	113
95	114
	115	m37702s1_device::m37702s1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	116	: m37710_cpu_device(mconfig, M37702S1, "M37702S1", tag, owner, clock, "m37702s1", __FILE__, address_map_delegate(FUNC(m37702s1_device::map), this))
	117	{
	118	}
	119
	120
	121	m37710s4_device::m37710s4_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	122	: m37710_cpu_device(mconfig, M37710S4, "M37710S4", tag, owner, clock, "m37710s4", __FILE__, address_map_delegate(FUNC(m37710s4_device::map), this))
	123	{
	124	}
	125
	126
96	127	/* interrupt control mapping */
97	128
98	129	const int m37710_cpu_device::m37710_irq_levels[M37710_LINE_MAX] =

trunk/src/emu/cpu/m37710/m37710.h

r32162	r32163
88	88	{
89	89	public:
90	90	// construction/destruction
91		m37710_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
92		m37710_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
	91	m37710_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, address_map_delegate map_delegate);
93	92
94	93	DECLARE_READ16_MEMBER( m37710_internal_word_r );
95	94	DECLARE_WRITE16_MEMBER( m37710_internal_word_w );
r32162	r32163
2005	2004	};
2006	2005
2007	2006
2008		class m37702_cpu_device : public m37710_cpu_device
	2007	class m37702s1_device : public m37710_cpu_device
2009	2008	{
2010	2009	public:
2011	2010	// construction/destruction
2012		m37702_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	2011	m37702s1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	2012	protected:
	2013	DECLARE_ADDRESS_MAP(map, 16);
2013	2014	};
2014	2015
	2016	class m37702m2_device : public m37710_cpu_device
	2017	{
	2018	public:
	2019	// construction/destruction
	2020	m37702m2_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	2021	m37702m2_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
	2022	protected:
	2023	DECLARE_ADDRESS_MAP(map, 16);
	2024	};
2015	2025
2016		extern const device_type M37710;
2017		extern const device_type M37702;
	2026	class m37710s4_device : public m37710_cpu_device
	2027	{
	2028	public:
	2029	// construction/destruction
	2030	m37710s4_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	2031	protected:
	2032	DECLARE_ADDRESS_MAP(map, 16);
	2033	};
2018	2034
2019	2035
	2036	extern const device_type M37702M2;
	2037	extern const device_type M37702S1;
	2038	extern const device_type M37710S4;
	2039
	2040
2020	2041	/* ======================================================================== */
2021	2042	/* ============================== END OF FILE ============================= */
2022	2043	/* ======================================================================== */

trunk/src/emu/addrmap.c

r32162	r32163
19	19	//  address_map_entry - constructor
20	20	//-------------------------------------------------
21	21
22		address_map_entry::address_map_entry(address_map &map, offs_t start, offs_t end)
	22	address_map_entry::address_map_entry(device_t &device, address_map &map, offs_t start, offs_t end)
23	23	: m_next(NULL),
24	24	m_map(map),
	25	m_devbase(device),
25	26	m_addrstart((map.m_globalmask == 0) ? start : start & map.m_globalmask),
26	27	m_addrend((map.m_globalmask == 0) ? end : end & map.m_globalmask),
27	28	m_addrmirror(0),
28	29	m_addrmask(0),
29		m_sharebase(NULL),
30		m_sharetag(NULL),
	30	m_share(NULL),
31	31	m_region(NULL),
32	32	m_rgnoffs(0),
33	33	m_memory(NULL),
r32162	r32163
52	52
53	53
54	54	//-------------------------------------------------
55		//  set_read_port - set up a handler for reading
56		//  an I/O port
57		//-------------------------------------------------
58
59		void address_map_entry::set_read_port(device_t &device, const char *tag)
60		{
61		m_read.m_type = AMH_PORT;
62		m_read.m_tag = tag;
63		m_read.m_devbase = &device;
64		}
65
66
67		//-------------------------------------------------
68		//  set_write_port - set up a handler for writing
69		//  an I/O port
70		//-------------------------------------------------
71
72		void address_map_entry::set_write_port(device_t &device, const char *tag)
73		{
74		m_write.m_type = AMH_PORT;
75		m_write.m_tag = tag;
76		m_write.m_devbase = &device;
77		}
78
79
80		//-------------------------------------------------
81		//  set_readwrite_port - set up a handler for
82		//  reading and writing an I/O port
83		//-------------------------------------------------
84
85		void address_map_entry::set_readwrite_port(device_t &device, const char *tag)
86		{
87		m_read.m_type = AMH_PORT;
88		m_read.m_tag = tag;
89		m_read.m_devbase = &device;
90		m_write.m_type = AMH_PORT;
91		m_write.m_tag = tag;
92		m_write.m_devbase = &device;
93		}
94
95
96		//-------------------------------------------------
97		//  set_read_bank - set up a handler for reading
98		//  from a memory bank
99		//-------------------------------------------------
100
101		void address_map_entry::set_read_bank(device_t &device, const char *tag)
102		{
103		m_read.m_type = AMH_BANK;
104		m_read.m_tag = tag;
105		m_read.m_devbase = &device;
106		}
107
108
109		//-------------------------------------------------
110		//  set_write_bank - set up a handler for writing
111		//  to a memory bank
112		//-------------------------------------------------
113
114		void address_map_entry::set_write_bank(device_t &device, const char *tag)
115		{
116		m_write.m_type = AMH_BANK;
117		m_write.m_tag = tag;
118		m_write.m_devbase = &device;
119		}
120
121
122		//-------------------------------------------------
123		//  set_readwrite_bank - set up a handler for
124		//  reading and writing to a memory bank
125		//-------------------------------------------------
126
127		void address_map_entry::set_readwrite_bank(device_t &device, const char *tag)
128		{
129		m_read.m_type = AMH_BANK;
130		m_read.m_tag = tag;
131		m_read.m_devbase = &device;
132		m_write.m_type = AMH_BANK;
133		m_write.m_tag = tag;
134		m_write.m_devbase = &device;
135		}
136
137
138		//-------------------------------------------------
139	55	//  set_submap - set up a handler for
140	56	//  retrieve a submap from a device
141	57	//-------------------------------------------------
142	58
143		void address_map_entry::set_submap(device_t &device, const char *tag, address_map_delegate func, int bits, UINT64 mask)
	59	void address_map_entry::set_submap(const char *tag, address_map_delegate func, int bits, UINT64 mask)
144	60	{
145	61	if(!bits)
146	62	bits = m_map.m_databits;
r32162	r32163
149	65
150	66	m_read.m_type = AMH_DEVICE_SUBMAP;
151	67	m_read.m_tag = tag;
152		m_read.m_devbase = &device;
153	68	m_read.m_mask = mask;
154	69	m_write.m_type = AMH_DEVICE_SUBMAP;
155	70	m_write.m_tag = tag;
156		m_write.m_devbase = &device;
157	71	m_write.m_mask = mask;
158	72	m_submap_delegate = func;
159	73	m_submap_bits = bits;
r32162	r32163
165	79	//  8-bit read/write handlers
166	80	//-------------------------------------------------
167	81
168		void address_map_entry::internal_set_handler(device_t &device, read8_delegate func, UINT64 unitmask)
	82	void address_map_entry::internal_set_handler(read8_delegate func, UINT64 unitmask)
169	83	{
170	84	assert(!func.isnull());
171	85	assert(unitmask_is_appropriate(8, unitmask, func.name()));
r32162	r32163
173	87	m_read.m_bits = 8;
174	88	m_read.m_mask = unitmask;
175	89	m_read.m_name = func.name();
176		m_read.m_devbase = &device;
177	90	m_rproto8 = func;
178	91	}
179	92
180	93
181		void address_map_entry::internal_set_handler(device_t &device, write8_delegate func, UINT64 unitmask)
	94	void address_map_entry::internal_set_handler(write8_delegate func, UINT64 unitmask)
182	95	{
183	96	assert(!func.isnull());
184	97	assert(unitmask_is_appropriate(8, unitmask, func.name()));
r32162	r32163
186	99	m_write.m_bits = 8;
187	100	m_write.m_mask = unitmask;
188	101	m_write.m_name = func.name();
189		m_write.m_devbase = &device;
190	102	m_wproto8 = func;
191	103	}
192	104
193	105
194		void address_map_entry::internal_set_handler(device_t &device, read8_delegate rfunc, write8_delegate wfunc, UINT64 unitmask)
	106	void address_map_entry::internal_set_handler(read8_delegate rfunc, write8_delegate wfunc, UINT64 unitmask)
195	107	{
196		internal_set_handler(device, rfunc, unitmask);
197		internal_set_handler(device, wfunc, unitmask);
	108	internal_set_handler(rfunc, unitmask);
	109	internal_set_handler(wfunc, unitmask);
198	110	}
199	111
200	112
r32162	r32163
203	115	//  16-bit read/write handlers
204	116	//-------------------------------------------------
205	117
206		void address_map_entry::internal_set_handler(device_t &device, read16_delegate func, UINT64 unitmask)
	118	void address_map_entry::internal_set_handler(read16_delegate func, UINT64 unitmask)
207	119	{
208	120	assert(!func.isnull());
209	121	assert(unitmask_is_appropriate(16, unitmask, func.name()));
r32162	r32163
211	123	m_read.m_bits = 16;
212	124	m_read.m_mask = unitmask;
213	125	m_read.m_name = func.name();
214		m_read.m_devbase = &device;
215	126	m_rproto16 = func;
216	127	}
217	128
218	129
219		void address_map_entry::internal_set_handler(device_t &device, write16_delegate func, UINT64 unitmask)
	130	void address_map_entry::internal_set_handler(write16_delegate func, UINT64 unitmask)
220	131	{
221	132	assert(!func.isnull());
222	133	assert(unitmask_is_appropriate(16, unitmask, func.name()));
r32162	r32163
224	135	m_write.m_bits = 16;
225	136	m_write.m_mask = unitmask;
226	137	m_write.m_name = func.name();
227		m_write.m_devbase = &device;
228	138	m_wproto16 = func;
229	139	}
230	140
231	141
232		void address_map_entry::internal_set_handler(device_t &device, read16_delegate rfunc, write16_delegate wfunc, UINT64 unitmask)
	142	void address_map_entry::internal_set_handler(read16_delegate rfunc, write16_delegate wfunc, UINT64 unitmask)
233	143	{
234		internal_set_handler(device, rfunc, unitmask);
235		internal_set_handler(device, wfunc, unitmask);
	144	internal_set_handler(rfunc, unitmask);
	145	internal_set_handler(wfunc, unitmask);
236	146	}
237	147
238	148
r32162	r32163
241	151	//  32-bit read/write handlers
242	152	//-------------------------------------------------
243	153
244		void address_map_entry::internal_set_handler(device_t &device, read32_delegate func, UINT64 unitmask)
	154	void address_map_entry::internal_set_handler(read32_delegate func, UINT64 unitmask)
245	155	{
246	156	assert(!func.isnull());
247	157	assert(unitmask_is_appropriate(32, unitmask, func.name()));
r32162	r32163
249	159	m_read.m_bits = 32;
250	160	m_read.m_mask = unitmask;
251	161	m_read.m_name = func.name();
252		m_read.m_devbase = &device;
253	162	m_rproto32 = func;
254	163	}
255	164
256	165
257		void address_map_entry::internal_set_handler(device_t &device, write32_delegate func, UINT64 unitmask)
	166	void address_map_entry::internal_set_handler(write32_delegate func, UINT64 unitmask)
258	167	{
259	168	assert(!func.isnull());
260	169	assert(unitmask_is_appropriate(32, unitmask, func.name()));
r32162	r32163
262	171	m_write.m_bits = 32;
263	172	m_write.m_mask = unitmask;
264	173	m_write.m_name = func.name();
265		m_write.m_devbase = &device;
266	174	m_wproto32 = func;
267	175	}
268	176
269	177
270		void address_map_entry::internal_set_handler(device_t &device, read32_delegate rfunc, write32_delegate wfunc, UINT64 unitmask)
	178	void address_map_entry::internal_set_handler(read32_delegate rfunc, write32_delegate wfunc, UINT64 unitmask)
271	179	{
272		internal_set_handler(device, rfunc, unitmask);
273		internal_set_handler(device, wfunc, unitmask);
	180	internal_set_handler(rfunc, unitmask);
	181	internal_set_handler(wfunc, unitmask);
274	182	}
275	183
276	184
r32162	r32163
279	187	//  64-bit read/write handlers
280	188	//-------------------------------------------------
281	189
282		void address_map_entry::internal_set_handler(device_t &device, read64_delegate func, UINT64 unitmask)
	190	void address_map_entry::internal_set_handler(read64_delegate func, UINT64 unitmask)
283	191	{
284	192	assert(!func.isnull());
285	193	assert(unitmask_is_appropriate(64, unitmask, func.name()));
r32162	r32163
287	195	m_read.m_bits = 64;
288	196	m_read.m_mask = 0;
289	197	m_read.m_name = func.name();
290		m_read.m_devbase = &device;
291	198	m_rproto64 = func;
292	199	}
293	200
294	201
295		void address_map_entry::internal_set_handler(device_t &device, write64_delegate func, UINT64 unitmask)
	202	void address_map_entry::internal_set_handler(write64_delegate func, UINT64 unitmask)
296	203	{
297	204	assert(!func.isnull());
298	205	assert(unitmask_is_appropriate(64, unitmask, func.name()));
r32162	r32163
300	207	m_write.m_bits = 64;
301	208	m_write.m_mask = 0;
302	209	m_write.m_name = func.name();
303		m_write.m_devbase = &device;
304	210	m_wproto64 = func;
305	211	}
306	212
307	213
308		void address_map_entry::internal_set_handler(device_t &device, read64_delegate rfunc, write64_delegate wfunc, UINT64 unitmask)
	214	void address_map_entry::internal_set_handler(read64_delegate rfunc, write64_delegate wfunc, UINT64 unitmask)
309	215	{
310		internal_set_handler(device, rfunc, unitmask);
311		internal_set_handler(device, wfunc, unitmask);
	216	internal_set_handler(rfunc, unitmask);
	217	internal_set_handler(wfunc, unitmask);
312	218	}
313	219
314	220
r32162	r32163
316	222	//  set_handler - handler setter for setoffset
317	223	//-------------------------------------------------
318	224
319		void address_map_entry::set_handler(device_t &device, setoffset_delegate func)
	225	void address_map_entry::set_handler(setoffset_delegate func)
320	226	{
321	227	assert(!func.isnull());
322	228	m_setoffsethd.m_type = AMH_DEVICE_DELEGATE;
323	229	m_setoffsethd.m_bits = 0;
324	230	m_setoffsethd.m_mask = 0;
325	231	m_setoffsethd.m_name = func.name();
326		m_setoffsethd.m_devbase = &device;
327	232	m_soproto = func;
328	233	}
329	234
r32162	r32163
368	273	//  address_map_entry8 - constructor
369	274	//-------------------------------------------------
370	275
371		address_map_entry8::address_map_entry8(address_map &map, offs_t start, offs_t end)
372		: address_map_entry(map, start, end)
	276	address_map_entry8::address_map_entry8(device_t &device, address_map &map, offs_t start, offs_t end)
	277	: address_map_entry(device, map, start, end)
373	278	{
374	279	}
375	280
r32162	r32163
378	283	//  address_map_entry16 - constructor
379	284	//-------------------------------------------------
380	285
381		address_map_entry16::address_map_entry16(address_map &map, offs_t start, offs_t end)
382		: address_map_entry(map, start, end)
	286	address_map_entry16::address_map_entry16(device_t &device, address_map &map, offs_t start, offs_t end)
	287	: address_map_entry(device, map, start, end)
383	288	{
384	289	}
385	290
r32162	r32163
388	293	//  address_map_entry32 - constructor
389	294	//-------------------------------------------------
390	295
391		address_map_entry32::address_map_entry32(address_map &map, offs_t start, offs_t end)
392		: address_map_entry(map, start, end)
	296	address_map_entry32::address_map_entry32(device_t &device, address_map &map, offs_t start, offs_t end)
	297	: address_map_entry(device, map, start, end)
393	298	{
394	299	}
395	300
r32162	r32163
398	303	//  address_map_entry64 - constructor
399	304	//-------------------------------------------------
400	305
401		address_map_entry64::address_map_entry64(address_map &map, offs_t start, offs_t end)
402		: address_map_entry(map, start, end)
	306	address_map_entry64::address_map_entry64(device_t &device, address_map &map, offs_t start, offs_t end)
	307	: address_map_entry(device, map, start, end)
403	308	{
404	309	}
405	310
r32162	r32163
478	383	address_map_entry *e;
479	384	switch(m_databits) {
480	385	case 8:
481		e = add(start, end, (address_map_entry8 *)NULL);
	386	e = add(device, start, end, (address_map_entry8 *)NULL);
482	387	break;
483	388	case 16:
484		e = add(start, end, (address_map_entry16 *)NULL);
	389	e = add(device, start, end, (address_map_entry16 *)NULL);
485	390	break;
486	391	case 32:
487		e = add(start, end, (address_map_entry32 *)NULL);
	392	e = add(device, start, end, (address_map_entry32 *)NULL);
488	393	break;
489	394	case 64:
490		e = add(start, end, (address_map_entry64 *)NULL);
	395	e = add(device, start, end, (address_map_entry64 *)NULL);
491	396	break;
492	397	default:
493	398	throw emu_fatalerror("Trying to dynamically map a device on a space with a corrupt databits width");
494	399	}
495		e->set_submap(device, DEVICE_SELF, submap_delegate, bits, unitmask);
	400	e->set_submap(DEVICE_SELF, submap_delegate, bits, unitmask);
496	401	}
497	402
498	403
r32162	r32163
539	444	//  add - add a new entry of the appropriate type
540	445	//-------------------------------------------------
541	446
542		address_map_entry8 *address_map::add(offs_t start, offs_t end, address_map_entry8 *ptr)
	447	address_map_entry8 *address_map::add(device_t &device, offs_t start, offs_t end, address_map_entry8 *ptr)
543	448	{
544		ptr = global_alloc(address_map_entry8(*this, start, end));
	449	ptr = global_alloc(address_map_entry8(device, *this, start, end));
545	450	m_entrylist.append(*ptr);
546	451	return ptr;
547	452	}
548	453
549	454
550		address_map_entry16 *address_map::add(offs_t start, offs_t end, address_map_entry16 *ptr)
	455	address_map_entry16 *address_map::add(device_t &device, offs_t start, offs_t end, address_map_entry16 *ptr)
551	456	{
552		ptr = global_alloc(address_map_entry16(*this, start, end));
	457	ptr = global_alloc(address_map_entry16(device, *this, start, end));
553	458	m_entrylist.append(*ptr);
554	459	return ptr;
555	460	}
556	461
557	462
558		address_map_entry32 *address_map::add(offs_t start, offs_t end, address_map_entry32 *ptr)
	463	address_map_entry32 *address_map::add(device_t &device, offs_t start, offs_t end, address_map_entry32 *ptr)
559	464	{
560		ptr = global_alloc(address_map_entry32(*this, start, end));
	465	ptr = global_alloc(address_map_entry32(device, *this, start, end));
561	466	m_entrylist.append(*ptr);
562	467	return ptr;
563	468	}
564	469
565	470
566		address_map_entry64 *address_map::add(offs_t start, offs_t end, address_map_entry64 *ptr)
	471	address_map_entry64 *address_map::add(device_t &device, offs_t start, offs_t end, address_map_entry64 *ptr)
567	472	{
568		ptr = global_alloc(address_map_entry64(*this, start, end));
	473	ptr = global_alloc(address_map_entry64(device, *this, start, end));
569	474	m_entrylist.append(*ptr);
570	475	return ptr;
571	476	}

trunk/src/emu/memory.c

r32162	r32163
1832	1832	adjust_addresses(entry->m_bytestart, entry->m_byteend, entry->m_bytemask, entry->m_bytemirror);
1833	1833
1834	1834	// if we have a share entry, add it to our map
1835		if (entry->m_sharetag != NULL)
	1835	if (entry->m_share != NULL)
1836	1836	{
1837	1837	// if we can't find it, add it to our map
1838	1838	astring fulltag;
1839		if (manager().m_sharelist.find(entry->m_sharebase->subtag(fulltag, entry->m_sharetag).cstr()) == NULL)
	1839	if (manager().m_sharelist.find(entry->m_devbase.subtag(fulltag, entry->m_share).cstr()) == NULL)
1840	1840	{
1841	1841	VPRINTF(("Creating share '%s' of length 0x%X\n", fulltag.cstr(), entry->m_byteend + 1 - entry->m_bytestart));
1842	1842	memory_share *share = global_alloc(memory_share(m_map->m_databits, entry->m_byteend + 1 - entry->m_bytestart, endianness()));
r32162	r32163
1856	1856	}
1857	1857
1858	1858	// validate adjusted addresses against implicit regions
1859		if (entry->m_region != NULL && entry->m_sharetag == NULL)
	1859	if (entry->m_region != NULL && entry->m_share == NULL)
1860	1860	{
1861	1861	// determine full tag
1862	1862	astring fulltag;
1863		device().siblingtag(fulltag, entry->m_region);
	1863	entry->m_devbase.subtag(fulltag, entry->m_region);
1864	1864
1865	1865	// find the region
1866	1866	memory_region *region = machine().root_device().memregion(fulltag);
r32162	r32163
1877	1877	{
1878	1878	// determine full tag
1879	1879	astring fulltag;
1880		device().siblingtag(fulltag, entry->m_region);
	1880	entry->m_devbase.subtag(fulltag, entry->m_region);
1881	1881
1882	1882	// set the memory address
1883	1883	entry->m_memory = machine().root_device().memregion(fulltag.cstr())->base() + entry->m_rgnoffs;
r32162	r32163
1962	1962	if (readorwrite == ROW_READ)
1963	1963	switch (data.m_bits)
1964	1964	{
1965		case 8:     install_read_handler(entry.m_addrstart, entry.m_addrend, entry.m_addrmask, entry.m_addrmirror, read8_delegate(entry.m_rproto8, *entry.m_read.m_devbase), data.m_mask); break;
1966		case 16:    install_read_handler(entry.m_addrstart, entry.m_addrend, entry.m_addrmask, entry.m_addrmirror, read16_delegate(entry.m_rproto16, *entry.m_read.m_devbase), data.m_mask); break;
1967		case 32:    install_read_handler(entry.m_addrstart, entry.m_addrend, entry.m_addrmask, entry.m_addrmirror, read32_delegate(entry.m_rproto32, *entry.m_read.m_devbase), data.m_mask); break;
1968		case 64:    install_read_handler(entry.m_addrstart, entry.m_addrend, entry.m_addrmask, entry.m_addrmirror, read64_delegate(entry.m_rproto64, *entry.m_read.m_devbase), data.m_mask); break;
	1965	case 8:     install_read_handler(entry.m_addrstart, entry.m_addrend, entry.m_addrmask, entry.m_addrmirror, read8_delegate(entry.m_rproto8, entry.m_devbase), data.m_mask); break;
	1966	case 16:    install_read_handler(entry.m_addrstart, entry.m_addrend, entry.m_addrmask, entry.m_addrmirror, read16_delegate(entry.m_rproto16, entry.m_devbase), data.m_mask); break;
	1967	case 32:    install_read_handler(entry.m_addrstart, entry.m_addrend, entry.m_addrmask, entry.m_addrmirror, read32_delegate(entry.m_rproto32, entry.m_devbase), data.m_mask); break;
	1968	case 64:    install_read_handler(entry.m_addrstart, entry.m_addrend, entry.m_addrmask, entry.m_addrmirror, read64_delegate(entry.m_rproto64, entry.m_devbase), data.m_mask); break;
1969	1969	}
1970	1970	else
1971	1971	switch (data.m_bits)
1972	1972	{
1973		case 8:     install_write_handler(entry.m_addrstart, entry.m_addrend, entry.m_addrmask, entry.m_addrmirror, write8_delegate(entry.m_wproto8, *entry.m_write.m_devbase), data.m_mask); break;
1974		case 16:    install_write_handler(entry.m_addrstart, entry.m_addrend, entry.m_addrmask, entry.m_addrmirror, write16_delegate(entry.m_wproto16, *entry.m_write.m_devbase), data.m_mask); break;
1975		case 32:    install_write_handler(entry.m_addrstart, entry.m_addrend, entry.m_addrmask, entry.m_addrmirror, write32_delegate(entry.m_wproto32, *entry.m_write.m_devbase), data.m_mask); break;
1976		case 64:    install_write_handler(entry.m_addrstart, entry.m_addrend, entry.m_addrmask, entry.m_addrmirror, write64_delegate(entry.m_wproto64, *entry.m_write.m_devbase), data.m_mask); break;
	1973	case 8:     install_write_handler(entry.m_addrstart, entry.m_addrend, entry.m_addrmask, entry.m_addrmirror, write8_delegate(entry.m_wproto8, entry.m_devbase), data.m_mask); break;
	1974	case 16:    install_write_handler(entry.m_addrstart, entry.m_addrend, entry.m_addrmask, entry.m_addrmirror, write16_delegate(entry.m_wproto16, entry.m_devbase), data.m_mask); break;
	1975	case 32:    install_write_handler(entry.m_addrstart, entry.m_addrend, entry.m_addrmask, entry.m_addrmirror, write32_delegate(entry.m_wproto32, entry.m_devbase), data.m_mask); break;
	1976	case 64:    install_write_handler(entry.m_addrstart, entry.m_addrend, entry.m_addrmask, entry.m_addrmirror, write64_delegate(entry.m_wproto64, entry.m_devbase), data.m_mask); break;
1977	1977	}
1978	1978	break;
1979	1979
r32162	r32163
2001	2001	void address_space::populate_map_entry_setoffset(const address_map_entry &entry)
2002	2002	{
2003	2003	install_setoffset_handler(entry.m_addrstart, entry.m_addrend, entry.m_addrmask,
2004		entry.m_addrmirror, setoffset_delegate(entry.m_soproto, *entry.m_setoffsethd.m_devbase), entry.m_setoffsethd.m_mask);
	2004	entry.m_addrmirror, setoffset_delegate(entry.m_soproto, entry.m_devbase), entry.m_setoffsethd.m_mask);
2005	2005	}
2006	2006
2007	2007	//-------------------------------------------------
r32162	r32163
2151	2151	for (address_map_entry *entry = m_map->m_entrylist.first(); entry != NULL; entry = entry->next())
2152	2152	{
2153	2153	// if we haven't assigned this block yet, see if we have a mapped shared pointer for it
2154		if (entry->m_memory == NULL && entry->m_sharetag != NULL)
	2154	if (entry->m_memory == NULL && entry->m_share != NULL)
2155	2155	{
2156	2156	astring fulltag;
2157		memory_share *share = manager().m_sharelist.find(entry->m_sharebase->subtag(fulltag, entry->m_sharetag).cstr());
	2157	memory_share *share = manager().m_sharelist.find(entry->m_devbase.subtag(fulltag, entry->m_share).cstr());
2158	2158	if (share != NULL && share->ptr() != NULL)
2159	2159	{
2160	2160	entry->m_memory = share->ptr();
2161		VPRINTF(("memory range %08X-%08X -> shared_ptr '%s' [%p]\n", entry->m_addrstart, entry->m_addrend, entry->m_sharetag, entry->m_memory));
	2161	VPRINTF(("memory range %08X-%08X -> shared_ptr '%s' [%p]\n", entry->m_addrstart, entry->m_addrend, entry->m_share, entry->m_memory));
2162	2162	}
2163	2163	else
2164	2164	{
2165		VPRINTF(("memory range %08X-%08X -> shared_ptr '%s' but not found\n", entry->m_addrstart, entry->m_addrend, entry->m_sharetag));
	2165	VPRINTF(("memory range %08X-%08X -> shared_ptr '%s' but not found\n", entry->m_addrstart, entry->m_addrend, entry->m_share));
2166	2166	}
2167	2167	}
2168	2168
r32162	r32163
2174	2174	}
2175	2175
2176	2176	// if we're the first match on a shared pointer, assign it now
2177		if (entry->m_memory != NULL && entry->m_sharetag != NULL)
	2177	if (entry->m_memory != NULL && entry->m_share != NULL)
2178	2178	{
2179	2179	astring fulltag;
2180		memory_share *share = manager().m_sharelist.find(entry->m_sharebase->subtag(fulltag, entry->m_sharetag).cstr());
	2180	memory_share *share = manager().m_sharelist.find(entry->m_devbase.subtag(fulltag, entry->m_share).cstr());
2181	2181	if (share != NULL && share->ptr() == NULL)
2182	2182	{
2183	2183	share->set_ptr(entry->m_memory);
2184		VPRINTF(("setting shared_ptr '%s' = %p\n", entry->m_sharetag, entry->m_memory));
	2184	VPRINTF(("setting shared_ptr '%s' = %p\n", entry->m_share, entry->m_memory));
2185	2185	}
2186	2186	}
2187	2187
r32162	r32163
2610	2610	bool address_space::needs_backing_store(const address_map_entry *entry)
2611	2611	{
2612	2612	// if we are sharing, and we don't have a pointer yet, create one
2613		if (entry->m_sharetag != NULL)
	2613	if (entry->m_share != NULL)
2614	2614	{
2615	2615	astring fulltag;
2616		memory_share *share = manager().m_sharelist.find(entry->m_sharebase->subtag(fulltag, entry->m_sharetag).cstr());
	2616	memory_share *share = manager().m_sharelist.find(entry->m_devbase.subtag(fulltag, entry->m_share).cstr());
2617	2617	if (share != NULL && share->ptr() == NULL)
2618	2618	return true;
2619	2619	}

trunk/src/emu/addrmap.h

r32162	r32163
52	52	m_bits(0),
53	53	m_mask(0),
54	54	m_name(NULL),
55		m_devbase(NULL),
56	55	m_tag(NULL) { }
57	56
58	57	map_handler_type        m_type;             // type of the handler
59	58	UINT8                   m_bits;             // width of the handler in bits, or 0 for default
60	59	UINT64                  m_mask;             // mask for which lanes apply
61	60	const char *            m_name;             // name of the handler
62		device_t *              m_devbase;          // pointer to "base" device
63	61	const char *            m_tag;              // tag for I/O ports and banks
64	62	};
65	63
r32162	r32163
72	70	{
73	71	public:
74	72	// construction/destruction
75		address_map_entry(address_map &map, offs_t start, offs_t end);
	73	address_map_entry(device_t &device, address_map &map, offs_t start, offs_t end);
76	74
77	75	// getters
78	76	address_map_entry *next() const { return m_next; }
r32162	r32163
82	80	void set_read_type(map_handler_type _type) { m_read.m_type = _type; }
83	81	void set_write_type(map_handler_type _type) { m_write.m_type = _type; }
84	82	void set_region(const char *tag, offs_t offset) { m_region = tag; m_rgnoffs = offset; }
85		void set_share(device_t &device, const char *tag) { assert(m_sharetag == NULL); m_sharebase = &device; m_sharetag = tag; }
	83	void set_share(const char *tag) { m_share = tag; }
86	84
87	85	// mask setting
88	86	void set_mask(offs_t _mask);
89	87
90	88	// I/O port configuration
91		void set_read_port(device_t &device, const char *tag);
92		void set_write_port(device_t &device, const char *tag);
93		void set_readwrite_port(device_t &device, const char *tag);
	89	void set_read_port(const char *tag) { m_read.m_type = AMH_PORT; m_read.m_tag = tag; }
	90	void set_write_port(const char *tag) { m_write.m_type = AMH_PORT; m_write.m_tag = tag; }
	91	void set_readwrite_port(const char *tag) { set_read_port(tag); set_write_port(tag); }
94	92
95	93	// memory bank configuration
96		void set_read_bank(device_t &device, const char *tag);
97		void set_write_bank(device_t &device, const char *tag);
98		void set_readwrite_bank(device_t &device, const char *tag);
	94	void set_read_bank(const char *tag) { m_read.m_type = AMH_BANK; m_read.m_tag = tag; }
	95	void set_write_bank(const char *tag) { m_write.m_type = AMH_BANK; m_write.m_tag = tag; }
	96	void set_readwrite_bank(const char *tag) { set_read_bank(tag); set_write_bank(tag); }
99	97
100	98	// set offset handler (only one version, since there is no data width to consider)
101		void set_handler(device_t &device, setoffset_delegate func);
	99	void set_handler(setoffset_delegate func);
102	100
103	101	// submap referencing
104		void set_submap(device_t &device, const char *tag, address_map_delegate func, int bits, UINT64 mask);
	102	void set_submap(const char *tag, address_map_delegate func, int bits, UINT64 mask);
105	103
106	104	// public state
107	105	address_map_entry *     m_next;                 // pointer to the next entry
108	106	address_map &           m_map;                  // reference to our owning map
109		astring                 m_region_string;        // string used to hold derived names
	107	device_t &              m_devbase;              // reference to "base" device for tag lookups
110	108
111	109	// basic information
112	110	offs_t                  m_addrstart;            // start address
r32162	r32163
116	114	map_handler_data        m_read;                 // data for read handler
117	115	map_handler_data        m_write;                // data for write handler
118	116	map_handler_data        m_setoffsethd;          // data for setoffset handler
119		device_t *              m_sharebase;            // pointer to the base device for the share tag
120		const char *            m_sharetag;             // tag of a shared memory block
	117	const char *            m_share;                // tag of a shared memory block
121	118	const char *            m_region;               // tag of region containing the memory backing this entry
122	119	offs_t                  m_rgnoffs;              // offset within the region
123	120
r32162	r32163
131	128	write32_delegate        m_wproto32;             // 32-bit write proto-delegate
132	129	write64_delegate        m_wproto64;             // 64-bit write proto-delegate
133	130
134		setoffset_delegate      m_soproto;              // set offset proto-delegate
	131	setoffset_delegate      m_soproto;              // set offset proto-delegate
135	132	address_map_delegate    m_submap_delegate;
136	133	int                     m_submap_bits;
137	134
r32162	r32163
144	141
145	142	protected:
146	143	// internal handler setters for 8-bit functions
147		void internal_set_handler(device_t &device, read8_delegate func, UINT64 mask);
148		void internal_set_handler(device_t &device, write8_delegate func, UINT64 mask);
149		void internal_set_handler(device_t &device, read8_delegate rfunc, write8_delegate wfunc, UINT64 mask);
	144	void internal_set_handler(read8_delegate func, UINT64 mask);
	145	void internal_set_handler(write8_delegate func, UINT64 mask);
	146	void internal_set_handler(read8_delegate rfunc, write8_delegate wfunc, UINT64 mask);
150	147
151	148	// internal handler setters for 16-bit functions
152		void internal_set_handler(device_t &device, read16_delegate func, UINT64 mask);
153		void internal_set_handler(device_t &device, write16_delegate func, UINT64 mask);
154		void internal_set_handler(device_t &device, read16_delegate rfunc, write16_delegate wfunc, UINT64 mask);
	149	void internal_set_handler(read16_delegate func, UINT64 mask);
	150	void internal_set_handler(write16_delegate func, UINT64 mask);
	151	void internal_set_handler(read16_delegate rfunc, write16_delegate wfunc, UINT64 mask);
155	152
156	153	// internal handler setters for 32-bit functions
157		void internal_set_handler(device_t &device, read32_delegate func, UINT64 mask);
158		void internal_set_handler(device_t &device, write32_delegate func, UINT64 mask);
159		void internal_set_handler(device_t &device, read32_delegate rfunc, write32_delegate wfunc, UINT64 mask);
	154	void internal_set_handler(read32_delegate func, UINT64 mask);
	155	void internal_set_handler(write32_delegate func, UINT64 mask);
	156	void internal_set_handler(read32_delegate rfunc, write32_delegate wfunc, UINT64 mask);
160	157
161	158	// internal handler setters for 64-bit functions
162		void internal_set_handler(device_t &device, read64_delegate func, UINT64 mask);
163		void internal_set_handler(device_t &device, write64_delegate func, UINT64 mask);
164		void internal_set_handler(device_t &device, read64_delegate rfunc, write64_delegate wfunc, UINT64 mask);
	159	void internal_set_handler(read64_delegate func, UINT64 mask);
	160	void internal_set_handler(write64_delegate func, UINT64 mask);
	161	void internal_set_handler(read64_delegate rfunc, write64_delegate wfunc, UINT64 mask);
165	162
166	163	private:
167	164	// helper functions
r32162	r32163
175	172	class address_map_entry8 : public address_map_entry
176	173	{
177	174	public:
178		address_map_entry8(address_map &map, offs_t start, offs_t end);
	175	address_map_entry8(device_t &device, address_map &map, offs_t start, offs_t end);
179	176
180	177	// native-size handlers
181		void set_handler(device_t &device, read8_delegate func) { internal_set_handler(device, func, 0); }
182		void set_handler(device_t &device, write8_delegate func) { internal_set_handler(device, func, 0); }
183		void set_handler(device_t &device, read8_delegate rfunc, write8_delegate wfunc) { internal_set_handler(device, rfunc, wfunc, 0); }
	178	void set_handler(read8_delegate func) { internal_set_handler(func, 0); }
	179	void set_handler(write8_delegate func) { internal_set_handler(func, 0); }
	180	void set_handler(read8_delegate rfunc, write8_delegate wfunc) { internal_set_handler(rfunc, wfunc, 0); }
184	181	};
185	182
186	183
r32162	r32163
190	187	class address_map_entry16 : public address_map_entry
191	188	{
192	189	public:
193		address_map_entry16(address_map &map, offs_t start, offs_t end);
	190	address_map_entry16(device_t &device, address_map &map, offs_t start, offs_t end);
194	191
195	192	// native-size handlers
196		void set_handler(device_t &device, read16_delegate func) { internal_set_handler(device, func, 0); }
197		void set_handler(device_t &device, write16_delegate func) { internal_set_handler(device, func, 0); }
198		void set_handler(device_t &device, read16_delegate rfunc, write16_delegate wfunc) { internal_set_handler(device, rfunc, wfunc, 0); }
	193	void set_handler(read16_delegate func) { internal_set_handler(func, 0); }
	194	void set_handler(write16_delegate func) { internal_set_handler(func, 0); }
	195	void set_handler(read16_delegate rfunc, write16_delegate wfunc) { internal_set_handler(rfunc, wfunc, 0); }
199	196
200	197	// 8-bit handlers
201		void set_handler(device_t &device, read8_delegate func, UINT16 mask) { internal_set_handler(device, func, mask); }
202		void set_handler(device_t &device, write8_delegate func, UINT16 mask) { internal_set_handler(device, func, mask); }
203		void set_handler(device_t &device, read8_delegate rfunc, write8_delegate wfunc, UINT16 mask) { internal_set_handler(device, rfunc, wfunc, mask); }
	198	void set_handler(read8_delegate func, UINT16 mask) { internal_set_handler(func, mask); }
	199	void set_handler(write8_delegate func, UINT16 mask) { internal_set_handler(func, mask); }
	200	void set_handler(read8_delegate rfunc, write8_delegate wfunc, UINT16 mask) { internal_set_handler(rfunc, wfunc, mask); }
204	201	};
205	202
206	203
r32162	r32163
210	207	class address_map_entry32 : public address_map_entry
211	208	{
212	209	public:
213		address_map_entry32(address_map &map, offs_t start, offs_t end);
	210	address_map_entry32(device_t &device, address_map &map, offs_t start, offs_t end);
214	211
215	212	// native-size handlers
216		void set_handler(device_t &device, read32_delegate func) { internal_set_handler(device, func, 0); }
217		void set_handler(device_t &device, write32_delegate func) { internal_set_handler(device, func, 0); }
218		void set_handler(device_t &device, read32_delegate rfunc, write32_delegate wfunc) { internal_set_handler(device, rfunc, wfunc, 0); }
	213	void set_handler(read32_delegate func) { internal_set_handler(func, 0); }
	214	void set_handler(write32_delegate func) { internal_set_handler(func, 0); }
	215	void set_handler(read32_delegate rfunc, write32_delegate wfunc) { internal_set_handler(rfunc, wfunc, 0); }
219	216
220	217	// 16-bit handlers
221		void set_handler(device_t &device, read16_delegate func, UINT32 mask) { internal_set_handler(device, func, mask); }
222		void set_handler(device_t &device, write16_delegate func, UINT32 mask) { internal_set_handler(device, func, mask); }
223		void set_handler(device_t &device, read16_delegate rfunc, write16_delegate wfunc, UINT32 mask) { internal_set_handler(device, rfunc, wfunc, mask); }
	218	void set_handler(read16_delegate func, UINT32 mask) { internal_set_handler(func, mask); }
	219	void set_handler(write16_delegate func, UINT32 mask) { internal_set_handler(func, mask); }
	220	void set_handler(read16_delegate rfunc, write16_delegate wfunc, UINT32 mask) { internal_set_handler(rfunc, wfunc, mask); }
224	221
225	222	// 8-bit handlers
226		void set_handler(device_t &device, read8_delegate func, UINT32 mask) { internal_set_handler(device, func, mask); }
227		void set_handler(device_t &device, write8_delegate func, UINT32 mask) { internal_set_handler(device, func, mask); }
228		void set_handler(device_t &device, read8_delegate rfunc, write8_delegate wfunc, UINT32 mask) { internal_set_handler(device, rfunc, wfunc, mask); }
	223	void set_handler(read8_delegate func, UINT32 mask) { internal_set_handler(func, mask); }
	224	void set_handler(write8_delegate func, UINT32 mask) { internal_set_handler(func, mask); }
	225	void set_handler(read8_delegate rfunc, write8_delegate wfunc, UINT32 mask) { internal_set_handler(rfunc, wfunc, mask); }
229	226	};
230	227
231	228
r32162	r32163
235	232	class address_map_entry64 : public address_map_entry
236	233	{
237	234	public:
238		address_map_entry64(address_map &map, offs_t start, offs_t end);
	235	address_map_entry64(device_t &device, address_map &map, offs_t start, offs_t end);
239	236
240	237	// native-size handlers
241		void set_handler(device_t &device, read64_delegate func) { internal_set_handler(device, func, 0); }
242		void set_handler(device_t &device, write64_delegate func) { internal_set_handler(device, func, 0); }
243		void set_handler(device_t &device, read64_delegate rfunc, write64_delegate wfunc) { internal_set_handler(device, rfunc, wfunc, 0); }
	238	void set_handler(read64_delegate func) { internal_set_handler(func, 0); }
	239	void set_handler(write64_delegate func) { internal_set_handler(func, 0); }
	240	void set_handler(read64_delegate rfunc, write64_delegate wfunc) { internal_set_handler(rfunc, wfunc, 0); }
244	241
245	242	// 32-bit handlers
246		void set_handler(device_t &device, read32_delegate func, UINT64 mask) { internal_set_handler(device, func, mask); }
247		void set_handler(device_t &device, write32_delegate func, UINT64 mask) { internal_set_handler(device, func, mask); }
248		void set_handler(device_t &device, read32_delegate rfunc, write32_delegate wfunc, UINT64 mask) { internal_set_handler(device, rfunc, wfunc, mask); }
	243	void set_handler(read32_delegate func, UINT64 mask) { internal_set_handler(func, mask); }
	244	void set_handler(write32_delegate func, UINT64 mask) { internal_set_handler(func, mask); }
	245	void set_handler(read32_delegate rfunc, write32_delegate wfunc, UINT64 mask) { internal_set_handler(rfunc, wfunc, mask); }
249	246
250	247	// 16-bit handlers
251		void set_handler(device_t &device, read16_delegate func, UINT64 mask) { internal_set_handler(device, func, mask); }
252		void set_handler(device_t &device, write16_delegate func, UINT64 mask) { internal_set_handler(device, func, mask); }
253		void set_handler(device_t &device, read16_delegate rfunc, write16_delegate wfunc, UINT64 mask) { internal_set_handler(device, rfunc, wfunc, mask); }
	248	void set_handler(read16_delegate func, UINT64 mask) { internal_set_handler(func, mask); }
	249	void set_handler(write16_delegate func, UINT64 mask) { internal_set_handler(func, mask); }
	250	void set_handler(read16_delegate rfunc, write16_delegate wfunc, UINT64 mask) { internal_set_handler(rfunc, wfunc, mask); }
254	251
255	252	// 8-bit handlers
256		void set_handler(device_t &device, read8_delegate func, UINT64 mask) { internal_set_handler(device, func, mask); }
257		void set_handler(device_t &device, write8_delegate func, UINT64 mask) { internal_set_handler(device, func, mask); }
258		void set_handler(device_t &device, read8_delegate rfunc, write8_delegate wfunc, UINT64 mask) { internal_set_handler(device, rfunc, wfunc, mask); }
	253	void set_handler(read8_delegate func, UINT64 mask) { internal_set_handler(func, mask); }
	254	void set_handler(write8_delegate func, UINT64 mask) { internal_set_handler(func, mask); }
	255	void set_handler(read8_delegate rfunc, write8_delegate wfunc, UINT64 mask) { internal_set_handler(rfunc, wfunc, mask); }
259	256	};
260	257
261	258
r32162	r32163
279	276	void set_unmap_value(UINT8 value) { m_unmapval = value; }
280	277
281	278	// add a new entry of the given type
282		address_map_entry8 *add(offs_t start, offs_t end, address_map_entry8 *ptr);
283		address_map_entry16 *add(offs_t start, offs_t end, address_map_entry16 *ptr);
284		address_map_entry32 *add(offs_t start, offs_t end, address_map_entry32 *ptr);
285		address_map_entry64 *add(offs_t start, offs_t end, address_map_entry64 *ptr);
	279	address_map_entry8 *add(device_t &device, offs_t start, offs_t end, address_map_entry8 *ptr);
	280	address_map_entry16 *add(device_t &device, offs_t start, offs_t end, address_map_entry16 *ptr);
	281	address_map_entry32 *add(device_t &device, offs_t start, offs_t end, address_map_entry32 *ptr);
	282	address_map_entry64 *add(device_t &device, offs_t start, offs_t end, address_map_entry64 *ptr);
286	283
287	284	// public data
288	285	address_spacenum        m_spacenum;         // space number of the map
r32162	r32163
353	350
354	351	// address ranges
355	352	#define AM_RANGE(_start, _end) \
356		curentry = map.add(_start, _end, curentry);
	353	curentry = map.add(device, _start, _end, curentry);
357	354	#define AM_MASK(_mask) \
358	355	curentry->set_mask(_mask);
359	356	#define AM_MIRROR(_mirror) \
r32162	r32163
361	358
362	359	// driver data reads
363	360	#define AM_READ(_handler) \
364		curentry->set_handler(device, read_delegate(&drivdata_class::_handler, "driver_data::" #_handler, DEVICE_SELF, (drivdata_class *)0));
	361	curentry->set_handler(read_delegate(&drivdata_class::_handler, "driver_data::" #_handler, DEVICE_SELF, (drivdata_class *)0));
365	362	#define AM_READ8(_handler, _unitmask) \
366		curentry->set_handler(device, read8_delegate(&drivdata_class::_handler, "driver_data::" #_handler, DEVICE_SELF, (drivdata_class *)0), _unitmask);
	363	curentry->set_handler(read8_delegate(&drivdata_class::_handler, "driver_data::" #_handler, DEVICE_SELF, (drivdata_class *)0), _unitmask);
367	364	#define AM_READ16(_handler, _unitmask) \
368		curentry->set_handler(device, read16_delegate(&drivdata_class::_handler, "driver_data::" #_handler, DEVICE_SELF, (drivdata_class *)0), _unitmask);
	365	curentry->set_handler(read16_delegate(&drivdata_class::_handler, "driver_data::" #_handler, DEVICE_SELF, (drivdata_class *)0), _unitmask);
369	366	#define AM_READ32(_handler, _unitmask) \
370		curentry->set_handler(device, read32_delegate(&drivdata_class::_handler, "driver_data::" #_handler, DEVICE_SELF, (drivdata_class *)0), _unitmask);
	367	curentry->set_handler(read32_delegate(&drivdata_class::_handler, "driver_data::" #_handler, DEVICE_SELF, (drivdata_class *)0), _unitmask);
371	368
372	369	// driver data writes
373	370	#define AM_WRITE(_handler) \
374		curentry->set_handler(device, write_delegate(&drivdata_class::_handler, "driver_data::" #_handler, DEVICE_SELF, (drivdata_class *)0));
	371	curentry->set_handler(write_delegate(&drivdata_class::_handler, "driver_data::" #_handler, DEVICE_SELF, (drivdata_class *)0));
375	372	#define AM_WRITE8(_handler, _unitmask) \
376		curentry->set_handler(device, write8_delegate(&drivdata_class::_handler, "driver_data::" #_handler, DEVICE_SELF, (drivdata_class *)0), _unitmask);
	373	curentry->set_handler(write8_delegate(&drivdata_class::_handler, "driver_data::" #_handler, DEVICE_SELF, (drivdata_class *)0), _unitmask);
377	374	#define AM_WRITE16(_handler, _unitmask) \
378		curentry->set_handler(device, write16_delegate(&drivdata_class::_handler, "driver_data::" #_handler, DEVICE_SELF, (drivdata_class *)0), _unitmask);
	375	curentry->set_handler(write16_delegate(&drivdata_class::_handler, "driver_data::" #_handler, DEVICE_SELF, (drivdata_class *)0), _unitmask);
379	376	#define AM_WRITE32(_handler, _unitmask) \
380		curentry->set_handler(device, write32_delegate(&drivdata_class::_handler, "driver_data::" #_handler, DEVICE_SELF, (drivdata_class *)0), _unitmask);
	377	curentry->set_handler(write32_delegate(&drivdata_class::_handler, "driver_data::" #_handler, DEVICE_SELF, (drivdata_class *)0), _unitmask);
381	378
382	379	// driver data reads/writes
383	380	#define AM_READWRITE(_rhandler, _whandler) \
384		curentry->set_handler(device, read_delegate(&drivdata_class::_rhandler, "driver_data::" #_rhandler, DEVICE_SELF, (drivdata_class *)0), write_delegate(&drivdata_class::_whandler, "driver_data::" #_whandler, DEVICE_SELF, (drivdata_class *)0));
	381	curentry->set_handler(read_delegate(&drivdata_class::_rhandler, "driver_data::" #_rhandler, DEVICE_SELF, (drivdata_class *)0), write_delegate(&drivdata_class::_whandler, "driver_data::" #_whandler, DEVICE_SELF, (drivdata_class *)0));
385	382	#define AM_READWRITE8(_rhandler, _whandler, _unitmask) \
386		curentry->set_handler(device, read8_delegate(&drivdata_class::_rhandler, "driver_data::" #_rhandler, DEVICE_SELF, (drivdata_class *)0), write8_delegate(&drivdata_class::_whandler, "driver_data::" #_whandler, DEVICE_SELF, (drivdata_class *)0), _unitmask);
	383	curentry->set_handler(read8_delegate(&drivdata_class::_rhandler, "driver_data::" #_rhandler, DEVICE_SELF, (drivdata_class *)0), write8_delegate(&drivdata_class::_whandler, "driver_data::" #_whandler, DEVICE_SELF, (drivdata_class *)0), _unitmask);
387	384	#define AM_READWRITE16(_rhandler, _whandler, _unitmask) \
388		curentry->set_handler(device, read16_delegate(&drivdata_class::_rhandler, "driver_data::" #_rhandler, DEVICE_SELF, (drivdata_class *)0), write16_delegate(&drivdata_class::_whandler, "driver_data::" #_whandler, DEVICE_SELF, (drivdata_class *)0), _unitmask);
	385	curentry->set_handler(read16_delegate(&drivdata_class::_rhandler, "driver_data::" #_rhandler, DEVICE_SELF, (drivdata_class *)0), write16_delegate(&drivdata_class::_whandler, "driver_data::" #_whandler, DEVICE_SELF, (drivdata_class *)0), _unitmask);
389	386	#define AM_READWRITE32(_rhandler, _whandler, _unitmask) \
390		curentry->set_handler(device, read32_delegate(&drivdata_class::_rhandler, "driver_data::" #_rhandler, DEVICE_SELF, (drivdata_class *)0), write32_delegate(&drivdata_class::_whandler, "driver_data::" #_whandler, DEVICE_SELF, (drivdata_class *)0), _unitmask);
	387	curentry->set_handler(read32_delegate(&drivdata_class::_rhandler, "driver_data::" #_rhandler, DEVICE_SELF, (drivdata_class *)0), write32_delegate(&drivdata_class::_whandler, "driver_data::" #_whandler, DEVICE_SELF, (drivdata_class *)0), _unitmask);
391	388
392	389	// driver set offset. Upcast to base class because there are no data width variants,
393	390	// and the compiler complains if we don't do it explicitly
394	391	#define AM_SETOFFSET(_handler) \
395		((address_map_entry*)curentry)->set_handler(device, setoffset_delegate(&drivdata_class::_handler, "driver_data::" #_handler, DEVICE_SELF, (drivdata_class *)0));
	392	((address_map_entry*)curentry)->set_handler(setoffset_delegate(&drivdata_class::_handler, "driver_data::" #_handler, DEVICE_SELF, (drivdata_class *)0));
396	393
397	394	// device reads
398	395	#define AM_DEVREAD(_tag, _class, _handler) \
399		curentry->set_handler(device, read_delegate(&_class::_handler, #_class "::" #_handler, _tag, (_class *)0));
	396	curentry->set_handler(read_delegate(&_class::_handler, #_class "::" #_handler, _tag, (_class *)0));
400	397	#define AM_DEVREAD8(_tag, _class, _handler, _unitmask) \
401		curentry->set_handler(device, read8_delegate(&_class::_handler, #_class "::" #_handler, _tag, (_class *)0), _unitmask);
	398	curentry->set_handler(read8_delegate(&_class::_handler, #_class "::" #_handler, _tag, (_class *)0), _unitmask);
402	399	#define AM_DEVREAD16(_tag, _class, _handler, _unitmask) \
403		curentry->set_handler(device, read16_delegate(&_class::_handler, #_class "::" #_handler, _tag, (_class *)0), _unitmask);
	400	curentry->set_handler(read16_delegate(&_class::_handler, #_class "::" #_handler, _tag, (_class *)0), _unitmask);
404	401	#define AM_DEVREAD32(_tag, _class, _handler, _unitmask) \
405		curentry->set_handler(device, read32_delegate(&_class::_handler, #_class "::" #_handler, _tag, (_class *)0), _unitmask);
	402	curentry->set_handler(read32_delegate(&_class::_handler, #_class "::" #_handler, _tag, (_class *)0), _unitmask);
406	403
407	404	// device writes
408	405	#define AM_DEVWRITE(_tag, _class, _handler) \
409		curentry->set_handler(device, write_delegate(&_class::_handler, #_class "::" #_handler, _tag, (_class *)0));
	406	curentry->set_handler(write_delegate(&_class::_handler, #_class "::" #_handler, _tag, (_class *)0));
410	407	#define AM_DEVWRITE8(_tag, _class, _handler, _unitmask) \
411		curentry->set_handler(device, write8_delegate(&_class::_handler, #_class "::" #_handler, _tag, (_class *)0), _unitmask);
	408	curentry->set_handler(write8_delegate(&_class::_handler, #_class "::" #_handler, _tag, (_class *)0), _unitmask);
412	409	#define AM_DEVWRITE16(_tag, _class, _handler, _unitmask) \
413		curentry->set_handler(device, write16_delegate(&_class::_handler, #_class "::" #_handler, _tag, (_class *)0), _unitmask);
	410	curentry->set_handler(write16_delegate(&_class::_handler, #_class "::" #_handler, _tag, (_class *)0), _unitmask);
414	411	#define AM_DEVWRITE32(_tag, _class, _handler, _unitmask) \
415		curentry->set_handler(device, write32_delegate(&_class::_handler, #_class "::" #_handler, _tag, (_class *)0), _unitmask);
	412	curentry->set_handler(write32_delegate(&_class::_handler, #_class "::" #_handler, _tag, (_class *)0), _unitmask);
416	413
417	414	// device reads/writes
418	415	#define AM_DEVREADWRITE(_tag, _class, _rhandler, _whandler) \
419		curentry->set_handler(device, read_delegate(&_class::_rhandler, #_class "::" #_rhandler, _tag, (_class *)0), write_delegate(&_class::_whandler, #_class "::" #_whandler, _tag, (_class *)0));
	416	curentry->set_handler(read_delegate(&_class::_rhandler, #_class "::" #_rhandler, _tag, (_class *)0), write_delegate(&_class::_whandler, #_class "::" #_whandler, _tag, (_class *)0));
420	417	#define AM_DEVREADWRITE8(_tag, _class, _rhandler, _whandler, _unitmask) \
421		curentry->set_handler(device, read8_delegate(&_class::_rhandler, #_class "::" #_rhandler, _tag, (_class *)0), write8_delegate(&_class::_whandler, #_class "::" #_whandler, _tag, (_class *)0), _unitmask);
	418	curentry->set_handler(read8_delegate(&_class::_rhandler, #_class "::" #_rhandler, _tag, (_class *)0), write8_delegate(&_class::_whandler, #_class "::" #_whandler, _tag, (_class *)0), _unitmask);
422	419	#define AM_DEVREADWRITE16(_tag, _class, _rhandler, _whandler, _unitmask) \
423		curentry->set_handler(device, read16_delegate(&_class::_rhandler, #_class "::" #_rhandler, _tag, (_class *)0), write16_delegate(&_class::_whandler, #_class "::" #_whandler, _tag, (_class *)0), _unitmask);
	420	curentry->set_handler(read16_delegate(&_class::_rhandler, #_class "::" #_rhandler, _tag, (_class *)0), write16_delegate(&_class::_whandler, #_class "::" #_whandler, _tag, (_class *)0), _unitmask);
424	421	#define AM_DEVREADWRITE32(_tag, _class, _rhandler, _whandler, _unitmask) \
425		curentry->set_handler(device, read32_delegate(&_class::_rhandler, #_class "::" #_rhandler, _tag, (_class *)0), write32_delegate(&_class::_whandler, #_class "::" #_whandler, _tag, (_class *)0), _unitmask);
	422	curentry->set_handler(read32_delegate(&_class::_rhandler, #_class "::" #_rhandler, _tag, (_class *)0), write32_delegate(&_class::_whandler, #_class "::" #_whandler, _tag, (_class *)0), _unitmask);
426	423
427	424	// device set offset
428	425	#define AM_DEVSETOFFSET(_tag, _class, _handler) \
429		((address_map_entry*)curentry)->set_handler(device, setoffset_delegate(&_class::_handler, #_class "::" #_handler, _tag, (_class *)0));
	426	((address_map_entry*)curentry)->set_handler(setoffset_delegate(&_class::_handler, #_class "::" #_handler, _tag, (_class *)0));
430	427
431	428
432	429	// device mapping
433	430	#define AM_DEVICE(_tag, _class, _handler) \
434		curentry->set_submap(device, _tag, address_map_delegate(&_class::_handler, #_class "::" #_handler, (_class *)0), 0, 0);
	431	curentry->set_submap(_tag, address_map_delegate(&_class::_handler, #_class "::" #_handler, (_class *)0), 0, 0);
435	432	#define AM_DEVICE8(_tag, _class, _handler, _unitmask) \
436		curentry->set_submap(device, _tag, address_map_delegate(&_class::_handler, #_class "::" #_handler, (_class *)0), 8, _unitmask);
	433	curentry->set_submap(_tag, address_map_delegate(&_class::_handler, #_class "::" #_handler, (_class *)0), 8, _unitmask);
437	434	#define AM_DEVICE16(_tag, _class, _handler, _unitmask) \
438		curentry->set_submap(device, _tag, address_map_delegate(&_class::_handler, #_class "::" #_handler, (_class *)0), 16, _unitmask);
	435	curentry->set_submap(_tag, address_map_delegate(&_class::_handler, #_class "::" #_handler, (_class *)0), 16, _unitmask);
439	436	#define AM_DEVICE32(_tag, _class, _handler, _unitmask) \
440		curentry->set_submap(device, _tag, address_map_delegate(&_class::_handler, #_class "::" #_handler, (_class *)0), 32, _unitmask);
	437	curentry->set_submap(_tag, address_map_delegate(&_class::_handler, #_class "::" #_handler, (_class *)0), 32, _unitmask);
441	438
442	439	// special-case accesses
443	440	#define AM_ROM \
r32162	r32163
466	463
467	464	// port accesses
468	465	#define AM_READ_PORT(_tag) \
469		curentry->set_read_port(device, _tag);
	466	curentry->set_read_port(_tag);
470	467	#define AM_WRITE_PORT(_tag) \
471		curentry->set_write_port(device, _tag);
	468	curentry->set_write_port(_tag);
472	469	#define AM_READWRITE_PORT(_tag) \
473		curentry->set_readwrite_port(device, _tag);
	470	curentry->set_readwrite_port(_tag);
474	471
475	472	// bank accesses
476	473	#define AM_READ_BANK(_tag) \
477		curentry->set_read_bank(device, _tag);
	474	curentry->set_read_bank(_tag);
478	475	#define AM_WRITE_BANK(_tag) \
479		curentry->set_write_bank(device, _tag);
	476	curentry->set_write_bank(_tag);
480	477	#define AM_READWRITE_BANK(_tag) \
481		curentry->set_readwrite_bank(device, _tag);
	478	curentry->set_readwrite_bank(_tag);
482	479
483	480	// attributes for accesses
484	481	#define AM_REGION(_tag, _offs) \
485	482	curentry->set_region(_tag, _offs);
486	483	#define AM_SHARE(_tag) \
487		curentry->set_share(device, _tag);
	484	curentry->set_share(_tag);
488	485
489	486	// common shortcuts
490	487	#define AM_ROMBANK(_bank)                   AM_READ_BANK(_bank)

trunk/src/emu/dimemory.c

r32162	r32163
293	293	}
294	294
295	295	// if this entry references a memory region, validate it
296		if (entry->m_region != NULL && entry->m_sharetag == 0)
	296	if (entry->m_region != NULL && entry->m_share == 0)
297	297	{
298	298	// make sure we can resolve the full path to the region
299	299	bool found = false;
300	300	astring entry_region;
301		device().siblingtag(entry_region, entry->m_region);
	301	entry->m_devbase.subtag(entry_region, entry->m_region);
302	302
303	303	// look for the region
304	304	device_iterator deviter(device().mconfig().root_device());
r32162	r32163
323	323	}
324	324
325	325	// make sure all devices exist
	326	// FIXME: This doesn't work! AMH_DEVICE_DELEGATE entries don't even set m_tag, the device tag is inside the proto-delegate
326	327	if (entry->m_read.m_type == AMH_DEVICE_DELEGATE && entry->m_read.m_tag != NULL)
327	328	{
328	329	astring temp(entry->m_read.m_tag);
r32162	r32163
346	347	valid.validate_tag(entry->m_read.m_tag);
347	348	if (entry->m_write.m_type == AMH_BANK)
348	349	valid.validate_tag(entry->m_write.m_tag);
349		if (entry->m_sharetag != NULL)
350		valid.validate_tag(entry->m_sharetag);
	350	if (entry->m_share != NULL)
	351	valid.validate_tag(entry->m_share);
351	352	}
352	353
353	354	// release the address map

trunk/src/mess/drivers/apple2gs.c

r32162	r32163
427	427
428	428	ROM_START(apple2gs)
429	429	// M50740/50741 ADB MCU inside the IIgs system unit
430		ROM_REGION(0x1000,"m50741",0)
	430	ROM_REGION(0x1000,ADBMICRO_TAG":internal",0)
431	431	ROM_LOAD( "341s0632-2.bin", 0x000000, 0x001000, CRC(e1c11fb0) SHA1(141d18c36a617ab9dce668445440d34354be0672) )
432	432
433	433	// i8048 microcontroller inside the IIgs ADB Standard Keyboard
r32162	r32163
454	454	ROM_END
455	455
456	456	ROM_START(apple2gsr3p)
457		ROM_REGION(0x1000,"m50741",0)
	457	ROM_REGION(0x1000,ADBMICRO_TAG":internal",0)
458	458	ROM_LOAD( "341s0632-2.bin", 0x000000, 0x001000, CRC(e1c11fb0) SHA1(141d18c36a617ab9dce668445440d34354be0672) )
459	459
460	460	ROM_REGION(0x400, "kmcu", 0)
r32162	r32163
476	476	ROM_END
477	477
478	478	ROM_START(apple2gsr3lp)
479		ROM_REGION(0x1000,"m50741",0)
	479	ROM_REGION(0x1000,ADBMICRO_TAG":internal",0)
480	480	ROM_LOAD( "341s0632-2.bin", 0x000000, 0x001000, CRC(e1c11fb0) SHA1(141d18c36a617ab9dce668445440d34354be0672) )
481	481
482	482	ROM_REGION(0x400, "kmcu", 0)
r32162	r32163
498	498	ROM_END
499	499
500	500	ROM_START(apple2gsr1)
501		ROM_REGION(0xc00,"m50740",0)
	501	ROM_REGION(0xc00,ADBMICRO_TAG":internal",0)
502	502	ROM_LOAD( "341s0345.bin", 0x000000, 0x000c00, CRC(48cd5779) SHA1(97e421f5247c00a0ca34cd08b6209df573101480) )
503	503
504	504	ROM_REGION(0x400, "kmcu", 0)
r32162	r32163
519	519	ROM_END
520	520
521	521	ROM_START(apple2gsr0)
522		ROM_REGION(0xc00,"m50740",0)
	522	ROM_REGION(0xc00,ADBMICRO_TAG":internal",0)
523	523	ROM_LOAD( "341s0345.bin", 0x000000, 0x000c00, CRC(48cd5779) SHA1(97e421f5247c00a0ca34cd08b6209df573101480) )
524	524
525	525	ROM_REGION(0x400, "kmcu", 0)
r32162	r32163
544	544	ROM_END
545	545
546	546	ROM_START(apple2gsr0p)  // 6/19/1986 Cortland prototype
547		ROM_REGION(0xc00,"m50740",0)
	547	ROM_REGION(0xc00,ADBMICRO_TAG":internal",0)
548	548	ROM_LOAD( "341s0345.bin", 0x000000, 0x000c00, CRC(48cd5779) SHA1(97e421f5247c00a0ca34cd08b6209df573101480) )
549	549
550	550	ROM_REGION(0x400, "kmcu", 0)
r32162	r32163
565	565	ROM_END
566	566
567	567	ROM_START(apple2gsr0p2)  // 3/10/1986 Cortland prototype, boots as "Apple //'ing - Alpha 2.0"
568		ROM_REGION(0xc00,"m50740",0)
	568	ROM_REGION(0xc00,ADBMICRO_TAG":internal",0)
569	569	ROM_LOAD( "341s0345.bin", 0x000000, 0x000c00, CRC(48cd5779) SHA1(97e421f5247c00a0ca34cd08b6209df573101480) )
570	570
571	571	ROM_REGION(0x400, "kmcu", 0)

trunk/src/mame/machine/namcomcu.c

r0	r32163
	1	/*
	2	Mitsubishi M37702 MCUs with Namco custom labels.
	3
	4	Label   Used by system(s)
	5	-------------------------
	6	C69     NA-1
	7	C70     NA-2
	8	C74     System 22
	9	C75     NB-1, NB-2, System FL
	10	C76     System 11
	11	*/
	12
	13	#include "emu.h"
	14	#include "namcomcu.h"
	15
	16
	17	const device_type NAMCO_C69 = &device_creator<namco_c69_device>;
	18	const device_type NAMCO_C70 = &device_creator<namco_c70_device>;
	19	const device_type NAMCO_C74 = &device_creator<namco_c74_device>;
	20	const device_type NAMCO_C75 = &device_creator<namco_c75_device>;
	21	const device_type NAMCO_C76 = &device_creator<namco_c76_device>;
	22
	23
	24	ROM_START( c69 )
	25	ROM_REGION16_LE( 0x4000, "internal", 0 )
	26	ROM_LOAD( "c69.bin", 0, 0x4000, CRC(349134d9) SHA1(61a4981fc2716c228b6121fedcbf1ed6f34dc2de) )
	27	ROM_END
	28
	29
	30	ROM_START( c70 )
	31	ROM_REGION16_LE( 0x4000, "internal", 0 )
	32	ROM_LOAD( "c70.bin", 0, 0x4000, CRC(b4015f23) SHA1(7ce91eda76e86b5cab625e2b67c463b7d143832e) )
	33	ROM_END
	34
	35
	36	ROM_START( c74 )
	37	ROM_REGION16_LE( 0x4000, "internal", 0 )
	38	ROM_LOAD( "c74.bin", 0, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
	39	ROM_END
	40
	41
	42	ROM_START( c75 )
	43	ROM_REGION16_LE( 0x4000, "internal", 0 )
	44	ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )
	45	ROM_END
	46
	47
	48	ROM_START( c76 )
	49	ROM_REGION16_LE( 0x4000, "internal", 0 )
	50	ROM_LOAD( "c76.bin", 0, 0x4000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
	51	ROM_END
	52
	53
	54	namco_c69_device::namco_c69_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	55	: m37702m2_device(mconfig, NAMCO_C69, "C69 (M37702)", tag, owner, clock, "namcoc69", __FILE__)
	56	{
	57	}
	58
	59	namco_c70_device::namco_c70_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	60	: m37702m2_device(mconfig, NAMCO_C70, "C70 (M37702)", tag, owner, clock, "namcoc70", __FILE__)
	61	{
	62	}
	63
	64	namco_c74_device::namco_c74_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	65	: m37702m2_device(mconfig, NAMCO_C74, "C74 (M37702)", tag, owner, clock, "namcoc74", __FILE__)
	66	{
	67	}
	68
	69	namco_c75_device::namco_c75_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	70	: m37702m2_device(mconfig, NAMCO_C75, "C75 (M37702)", tag, owner, clock, "namcoc75", __FILE__)
	71	{
	72	}
	73
	74	namco_c76_device::namco_c76_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	75	: m37702m2_device(mconfig, NAMCO_C76, "C76 (M37702)", tag, owner, clock, "namcoc76", __FILE__)
	76	{
	77	}
	78
	79	const rom_entry *namco_c69_device::device_rom_region() const
	80	{
	81	return ROM_NAME(c69);
	82	}
	83
	84	const rom_entry *namco_c70_device::device_rom_region() const
	85	{
	86	return ROM_NAME(c70);
	87	}
	88
	89	const rom_entry *namco_c74_device::device_rom_region() const
	90	{
	91	return ROM_NAME(c74);
	92	}
	93
	94	const rom_entry *namco_c75_device::device_rom_region() const
	95	{
	96	return ROM_NAME(c75);
	97	}
	98
	99	const rom_entry *namco_c76_device::device_rom_region() const
	100	{
	101	return ROM_NAME(c76);
	102	}

Property changes on: trunk/src/mame/machine/namcomcu.c

Added: svn:eol-style    + native Added: svn:mime-type    + text/plain

trunk/src/mame/machine/namcomcu.h

r0	r32163
	1	#pragma once
	2
	3	#ifndef __NAMCOMCU_H__
	4	#define __NAMCOMCU_H__
	5
	6	#include "cpu/m37710/m37710.h"
	7
	8
	9	class namco_c69_device : public m37702m2_device
	10	{
	11	public:
	12	namco_c69_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	13	protected:
	14	virtual const rom_entry *device_rom_region() const;
	15	};
	16
	17
	18	class namco_c70_device : public m37702m2_device
	19	{
	20	public:
	21	namco_c70_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	22	protected:
	23	virtual const rom_entry *device_rom_region() const;
	24	};
	25
	26
	27	class namco_c74_device : public m37702m2_device
	28	{
	29	public:
	30	namco_c74_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	31	protected:
	32	virtual const rom_entry *device_rom_region() const;
	33	};
	34
	35
	36	class namco_c75_device : public m37702m2_device
	37	{
	38	public:
	39	namco_c75_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	40	protected:
	41	virtual const rom_entry *device_rom_region() const;
	42	};
	43
	44
	45	class namco_c76_device : public m37702m2_device
	46	{
	47	public:
	48	namco_c76_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	49	protected:
	50	virtual const rom_entry *device_rom_region() const;
	51	};
	52
	53
	54	extern const device_type NAMCO_C69;
	55	extern const device_type NAMCO_C70;
	56	extern const device_type NAMCO_C74;
	57	extern const device_type NAMCO_C75;
	58	extern const device_type NAMCO_C76;
	59
	60
	61	#endif

Property changes on: trunk/src/mame/machine/namcomcu.h

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/mame/mame.mak

r32162	r32163
1517	1517	$(MACHINE)/namco51.o \
1518	1518	$(MACHINE)/namco53.o \
1519	1519	$(MACHINE)/namco62.o \
	1520	$(MACHINE)/namcomcu.o \
1520	1521	$(AUDIO)/namco52.o \
1521	1522	$(AUDIO)/namco54.o \
1522	1523	$(VIDEO)/c116.o \

trunk/src/mame/drivers/namcona1.c

r32162	r32163
166	166	#include "emu.h"
167	167	#include "cpu/m68000/m68000.h"
168	168	#include "includes/namcona1.h"
169		#include "cpu/m37710/m37710.h"
	169	#include "machine/namcomcu.h"
170	170
171	171	#define MASTER_CLOCK    XTAL_50_113MHz
172	172
r32162	r32163
612	612	AM_RANGE(0x001000, 0x001fff) AM_READWRITE(snd_r, snd_w) // C140-alike sound chip
613	613	AM_RANGE(0x002000, 0x002fff) AM_READWRITE(na1mcu_shared_r, na1mcu_shared_w) // mirror of first page of shared work RAM
614	614	AM_RANGE(0x003000, 0x00afff) AM_RAM                     // there is a 32k RAM chip according to CGFM
615		AM_RANGE(0x00c000, 0x00ffff) AM_ROM AM_REGION("mcu", 0)         // internal ROM BIOS
616	615	AM_RANGE(0x200000, 0x27ffff) AM_READWRITE(na1mcu_shared_r, na1mcu_shared_w) // shared work RAM
617	616	ADDRESS_MAP_END
618	617
r32162	r32163
928	927	MCFG_CPU_ADD("maincpu", M68000, MASTER_CLOCK/4)
929	928	MCFG_CPU_PROGRAM_MAP(namcona1_main_map)
930	929
931		MCFG_CPU_ADD("mcu", M37702, MASTER_CLOCK/4)
	930	MCFG_CPU_ADD("mcu", NAMCO_C69, MASTER_CLOCK/4)
932	931	MCFG_CPU_PROGRAM_MAP(namcona1_mcu_map)
933	932	MCFG_CPU_IO_MAP( namcona1_mcu_io_map)
934	933
r32162	r32163
974	973	/* basic machine hardware */
975	974	MCFG_CPU_MODIFY("maincpu")
976	975	MCFG_CPU_PROGRAM_MAP(namcona2_main_map)
	976
	977	MCFG_CPU_REPLACE("mcu", NAMCO_C70, MASTER_CLOCK/4)
	978	MCFG_CPU_PROGRAM_MAP(namcona1_mcu_map)
	979	MCFG_CPU_IO_MAP( namcona1_mcu_io_map)
977	980	MACHINE_CONFIG_END
978	981
979	982
r32162	r32163
1002	1005	ROM_LOAD16_BYTE( "mq1-ma0u.bin", 0x000000, 0x100000, CRC(23442ac0) SHA1(fac706f24045d51a2712f51530967140ea8e875f) )
1003	1006	ROM_LOAD16_BYTE( "mq1-ma1l.bin", 0x200001, 0x100000, CRC(fe82205f) SHA1(860cc7a96ae3f848ce594077c1362e4e22a36908) )
1004	1007	ROM_LOAD16_BYTE( "mq1-ma1u.bin", 0x200000, 0x100000, CRC(0cdb6bd0) SHA1(b8b398477c9654e96921110fb30c754240183897) )
1005
1006		/* M37702 BIOS - labeled as Namco custom C69 */
1007		ROM_REGION16_LE( 0x4000, "mcu", 0 )
1008		ROM_LOAD( "c69.bin",      0x000000, 0x004000, CRC(349134d9) SHA1(61a4981fc2716c228b6121fedcbf1ed6f34dc2de) )
1009	1008	ROM_END
1010	1009
1011	1010	ROM_START( cgangpzl )
r32162	r32163
1016	1015	ROM_REGION16_BE( 0x800000, "maskrom", ROMREGION_ERASE00 )
1017	1016	/* no mask roms */
1018	1017
1019		/* M37702 BIOS - labeled as Namco custom C69 */
1020		ROM_REGION16_LE( 0x4000, "mcu", 0 )
1021		ROM_LOAD( "c69.bin",      0x000000, 0x004000, CRC(349134d9) SHA1(61a4981fc2716c228b6121fedcbf1ed6f34dc2de) )
1022
1023	1018	ROM_REGION( 0x0800, "eeprom", 0 ) // default eeprom, otherwise game would lock up on 1st boot
1024	1019	ROM_LOAD( "eeprom_cgangpzl", 0x0000, 0x0800, CRC(5f8dfe9e) SHA1(81cc9cdbd8b5d6092a292309f78e3037233078f9) )
1025	1020	ROM_END
r32162	r32163
1032	1027	ROM_REGION16_BE( 0x800000, "maskrom", ROMREGION_ERASE00 )
1033	1028	/* no mask roms */
1034	1029
1035		/* M37702 BIOS - labeled as Namco custom C69 */
1036		ROM_REGION16_LE( 0x4000, "mcu", 0 )
1037		ROM_LOAD( "c69.bin",      0x000000, 0x004000, CRC(349134d9) SHA1(61a4981fc2716c228b6121fedcbf1ed6f34dc2de) )
1038
1039	1030	ROM_REGION( 0x0800, "eeprom", 0 ) // default eeprom, otherwise game would lock up on 1st boot
1040	1031	ROM_LOAD( "eeprom_cgangpzlj", 0x0000, 0x0800, CRC(ef5ddff2) SHA1(ea3f8e4da119e27c27f66f169bbf19bc37499048) )
1041	1032	ROM_END
r32162	r32163
1049	1040
1050	1041	ROM_REGION16_BE( 0x800000, "maskrom", ROMREGION_ERASE00 )
1051	1042	/* no mask roms */
1052
1053		/* M37702 BIOS - labeled as Namco custom C69 */
1054		ROM_REGION16_LE( 0x4000, "mcu", 0 )
1055		ROM_LOAD( "c69.bin",      0x000000, 0x004000, CRC(349134d9) SHA1(61a4981fc2716c228b6121fedcbf1ed6f34dc2de) )
1056	1043	ROM_END
1057	1044
1058	1045	ROM_START( emeraldaja ) /* NA-1 Game PCB, parent is NA-2 version listed below */
r32162	r32163
1064	1051
1065	1052	ROM_REGION16_BE( 0x800000, "maskrom", ROMREGION_ERASE00 )
1066	1053	/* no mask roms */
1067
1068		/* M37702 BIOS - labeled as Namco custom C69 */
1069		ROM_REGION16_LE( 0x4000, "mcu", 0 )
1070		ROM_LOAD( "c69.bin",      0x000000, 0x004000, CRC(349134d9) SHA1(61a4981fc2716c228b6121fedcbf1ed6f34dc2de) )
1071	1054	ROM_END
1072	1055
1073	1056	ROM_START( exvania )
r32162	r32163
1081	1064	ROM_LOAD16_BYTE( "ex1-ma1l.3c", 0x200001, 0x100000, CRC(e4bba6ed) SHA1(6483ef91e5a5b8ddd13a3d889936c39829fa50d6) )
1082	1065	ROM_LOAD16_BYTE( "ex1-ma1u.3f", 0x200000, 0x100000, CRC(04e7c4b0) SHA1(78180d96cd1fae583617d4d227ed4ee24f2f9e29) )
1083	1066
1084		/* M37702 BIOS - labeled as Namco custom C69 */
1085		ROM_REGION16_LE( 0x4000, "mcu", 0 )
1086		ROM_LOAD( "c69.bin",      0x000000, 0x004000, CRC(349134d9) SHA1(61a4981fc2716c228b6121fedcbf1ed6f34dc2de) )
1087
1088	1067	ROM_REGION( 0x0800, "eeprom", 0 ) // default eeprom, otherwise game would lock up on 1st boot
1089	1068	ROM_LOAD( "eeprom", 0x0000, 0x0800, CRC(0f46389d) SHA1(5706a46b02a667f5bddaa3842bb009ea07d23603) )
1090	1069	ROM_END
r32162	r32163
1100	1079	ROM_LOAD16_BYTE( "ex1-ma1l.3c", 0x200001, 0x100000, CRC(e4bba6ed) SHA1(6483ef91e5a5b8ddd13a3d889936c39829fa50d6) )
1101	1080	ROM_LOAD16_BYTE( "ex1-ma1u.3f", 0x200000, 0x100000, CRC(04e7c4b0) SHA1(78180d96cd1fae583617d4d227ed4ee24f2f9e29) )
1102	1081
1103		/* M37702 BIOS - labeled as Namco custom C69 */
1104		ROM_REGION16_LE( 0x4000, "mcu", 0 )
1105		ROM_LOAD( "c69.bin",      0x000000, 0x004000, CRC(349134d9) SHA1(61a4981fc2716c228b6121fedcbf1ed6f34dc2de) )
1106
1107	1082	ROM_REGION( 0x0800, "eeprom", 0 ) // default eeprom, otherwise game would lock up on 1st boot
1108	1083	ROM_LOAD( "eeprom", 0x0000, 0x0800, CRC(0f46389d) SHA1(5706a46b02a667f5bddaa3842bb009ea07d23603) )
1109	1084	ROM_END
r32162	r32163
1120	1095	ROM_LOAD16_BYTE( "fa1-ma0u.bin", 0x000000, 0x100000, CRC(1d0135bd) SHA1(2a7f8d09c213629a68376ce0379be61b37711d0a) )
1121	1096	ROM_LOAD16_BYTE( "fa1-ma1l.bin", 0x200001, 0x100000, CRC(c4adf0a2) SHA1(4cc7adc68b1db7e725a973b31d52720bd7dc1140) )
1122	1097	ROM_LOAD16_BYTE( "fa1-ma1u.bin", 0x200000, 0x100000, CRC(900297be) SHA1(57bb2078ff104c6f631c67219f80f8ede5ddbd09) )
1123
1124		/* M37702 BIOS - labeled as Namco custom C69 */
1125		ROM_REGION16_LE( 0x4000, "mcu", 0 )
1126		ROM_LOAD( "c69.bin",      0x000000, 0x004000, CRC(349134d9) SHA1(61a4981fc2716c228b6121fedcbf1ed6f34dc2de) )
1127	1098	ROM_END
1128	1099
1129	1100	ROM_START( fa )
r32162	r32163
1138	1109	ROM_LOAD16_BYTE( "fa1-ma0u.bin", 0x000000, 0x100000, CRC(1d0135bd) SHA1(2a7f8d09c213629a68376ce0379be61b37711d0a) )
1139	1110	ROM_LOAD16_BYTE( "fa1-ma1l.bin", 0x200001, 0x100000, CRC(c4adf0a2) SHA1(4cc7adc68b1db7e725a973b31d52720bd7dc1140) )
1140	1111	ROM_LOAD16_BYTE( "fa1-ma1u.bin", 0x200000, 0x100000, CRC(900297be) SHA1(57bb2078ff104c6f631c67219f80f8ede5ddbd09) )
1141
1142		/* M37702 BIOS - labeled as Namco custom C69 */
1143		ROM_REGION16_LE( 0x4000, "mcu", 0 )
1144		ROM_LOAD( "c69.bin",      0x000000, 0x004000, CRC(349134d9) SHA1(61a4981fc2716c228b6121fedcbf1ed6f34dc2de) )
1145	1112	ROM_END
1146	1113
1147	1114	ROM_START( swcourt )
r32162	r32163
1156	1123	ROM_LOAD16_BYTE( "sc1-ma0u.bin", 0x000000, 0x100000, CRC(31e76a45) SHA1(5c278c167c1025c648ce2da2c3764645e96dcd55) )
1157	1124	ROM_LOAD16_BYTE( "sc1-ma1l.bin", 0x200001, 0x100000, CRC(8ba3a4ec) SHA1(f881e7b4728f388d18450ba85e13e233071fbc88) )
1158	1125	ROM_LOAD16_BYTE( "sc1-ma1u.bin", 0x200000, 0x100000, CRC(252dc4b7) SHA1(f1be6bd045495c7a0ecd97f01d1dc8ad341fecfd) )
1159
1160		/* M37702 BIOS - labeled as Namco custom C69 */
1161		ROM_REGION16_LE( 0x4000, "mcu", 0 )
1162		ROM_LOAD( "c69.bin",      0x000000, 0x004000, CRC(349134d9) SHA1(61a4981fc2716c228b6121fedcbf1ed6f34dc2de) )
1163	1126	ROM_END
1164	1127
1165	1128	ROM_START( swcourtj )
r32162	r32163
1174	1137	ROM_LOAD16_BYTE( "sc1-ma0u.bin", 0x000000, 0x100000, CRC(31e76a45) SHA1(5c278c167c1025c648ce2da2c3764645e96dcd55) )
1175	1138	ROM_LOAD16_BYTE( "sc1-ma1l.bin", 0x200001, 0x100000, CRC(8ba3a4ec) SHA1(f881e7b4728f388d18450ba85e13e233071fbc88) )
1176	1139	ROM_LOAD16_BYTE( "sc1-ma1u.bin", 0x200000, 0x100000, CRC(252dc4b7) SHA1(f1be6bd045495c7a0ecd97f01d1dc8ad341fecfd) )
1177
1178		/* M37702 BIOS - labeled as Namco custom C69 */
1179		ROM_REGION16_LE( 0x4000, "mcu", 0 )
1180		ROM_LOAD( "c69.bin",      0x000000, 0x004000, CRC(349134d9) SHA1(61a4981fc2716c228b6121fedcbf1ed6f34dc2de) )
1181	1140	ROM_END
1182	1141
1183	1142	ROM_START( tinklpit )
r32162	r32163
1194	1153	ROM_LOAD16_BYTE( "tk1-ma1u.bin", 0x200000, 0x100000, CRC(54b77816) SHA1(9341d07858623e1920eaae7b2b90126c7057297e) )
1195	1154	ROM_LOAD16_BYTE( "tk1-ma2l.bin", 0x400001, 0x100000, CRC(087311d2) SHA1(6fe50f9e08551e57d15a15b01e3822a6cb7c8352) )
1196	1155	ROM_LOAD16_BYTE( "tk1-ma2u.bin", 0x400000, 0x100000, CRC(5ce20c2c) SHA1(7eaff21714bae44f8b21b6db98f055e04bfbae18) )
1197
1198		/* M37702 BIOS - labeled as Namco custom C69 */
1199		ROM_REGION16_LE( 0x4000, "mcu", 0 )
1200		ROM_LOAD( "c69.bin",      0x000000, 0x004000, CRC(349134d9) SHA1(61a4981fc2716c228b6121fedcbf1ed6f34dc2de) )
1201	1156	ROM_END
1202	1157
1203	1158
r32162	r32163
1215	1170
1216	1171	ROM_REGION16_BE( 0x800000, "maskrom", ROMREGION_ERASE00 )
1217	1172	/* no mask roms */
1218
1219		/* M37702 BIOS - labeled as Namco custom C70 */
1220		ROM_REGION16_LE( 0x4000, "mcu", 0 )
1221		ROM_LOAD( "c70.bin",      0x000000, 0x004000, CRC(b4015f23) SHA1(7ce91eda76e86b5cab625e2b67c463b7d143832e) )
1222	1173	ROM_END
1223	1174
1224	1175	ROM_START( knckhead )
r32162	r32163
1237	1188	ROM_LOAD16_BYTE( "kh1-ma2u.4f", 0x400000, 0x100000, CRC(17fe8c3d) SHA1(88c45076477725faa5f8a23512e65a40385bb27d) )
1238	1189	ROM_LOAD16_BYTE( "kh1-ma3l.5c", 0x600001, 0x100000, CRC(ad9a7807) SHA1(c40f18a68306e76acd89ccb3fc82b8106556912e) )
1239	1190	ROM_LOAD16_BYTE( "kh1-ma3u.5f", 0x600000, 0x100000, CRC(efeb768d) SHA1(15d016244549f3ea0d19f5cfb04bcebd65ac6134) )
1240
1241		/* M37702 BIOS - labeled as Namco custom C70 */
1242		ROM_REGION16_LE( 0x4000, "mcu", 0 )
1243		ROM_LOAD( "c70.bin",      0x000000, 0x004000, CRC(b4015f23) SHA1(7ce91eda76e86b5cab625e2b67c463b7d143832e) )
1244	1191	ROM_END
1245	1192
1246	1193	ROM_START( knckheadj )
r32162	r32163
1259	1206	ROM_LOAD16_BYTE( "kh1-ma2u.4f", 0x400000, 0x100000, CRC(17fe8c3d) SHA1(88c45076477725faa5f8a23512e65a40385bb27d) )
1260	1207	ROM_LOAD16_BYTE( "kh1-ma3l.5c", 0x600001, 0x100000, CRC(ad9a7807) SHA1(c40f18a68306e76acd89ccb3fc82b8106556912e) )
1261	1208	ROM_LOAD16_BYTE( "kh1-ma3u.5f", 0x600000, 0x100000, CRC(efeb768d) SHA1(15d016244549f3ea0d19f5cfb04bcebd65ac6134) )
1262
1263		/* M37702 BIOS - labeled as Namco custom C70 */
1264		ROM_REGION16_LE( 0x4000, "mcu", 0 )
1265		ROM_LOAD( "c70.bin",      0x000000, 0x004000, CRC(b4015f23) SHA1(7ce91eda76e86b5cab625e2b67c463b7d143832e) )
1266	1209	ROM_END
1267	1210
1268	1211	ROM_START( knckheadjp ) /* Older or possible prototype. Doesn't show rom test at boot up */
r32162	r32163
1282	1225	ROM_LOAD16_BYTE( "kh1-ma3l.5c", 0x600001, 0x100000, CRC(ad9a7807) SHA1(c40f18a68306e76acd89ccb3fc82b8106556912e) )
1283	1226	ROM_LOAD16_BYTE( "kh1-ma3u.5f", 0x600000, 0x100000, CRC(efeb768d) SHA1(15d016244549f3ea0d19f5cfb04bcebd65ac6134) )
1284	1227
1285		/* M37702 BIOS - labeled as Namco custom C70 */
1286		ROM_REGION16_LE( 0x4000, "mcu", 0 )
1287		ROM_LOAD( "c70.bin",      0x000000, 0x004000, CRC(b4015f23) SHA1(7ce91eda76e86b5cab625e2b67c463b7d143832e) )
1288
1289	1228	ROM_REGION( 0x0800, "eeprom", 0 ) // default eeprom, otherwise game would lock up on 1st boot
1290	1229	ROM_LOAD( "eeprom", 0x0000, 0x0800, CRC(98875a23) SHA1(2256cd231587351a0768faaedafbd1f80e3fd7c4) )
1291	1230	ROM_END
r32162	r32163
1306	1245	ROM_LOAD16_BYTE( "nm1-ma2u.bin", 0x400000, 0x100000, CRC(03a3f204) SHA1(9cb0422c8ecc819d0cc8a65c29a228369d78d986) )
1307	1246	ROM_LOAD16_BYTE( "nm1-ma3l.bin", 0x600001, 0x100000, CRC(42a539e9) SHA1(1c53a5a031648891ab7a37cf026c979404ce9589) )
1308	1247	ROM_LOAD16_BYTE( "nm1-ma3u.bin", 0x600000, 0x100000, CRC(f79e2112) SHA1(8bb8639a9d3a5d3ac5c9bb78e72b3d76582a9c25) )
1309
1310		/* M37702 BIOS - labeled as Namco custom C70 */
1311		ROM_REGION16_LE( 0x4000, "mcu", 0 )
1312		ROM_LOAD( "c70.bin",      0x000000, 0x004000, CRC(b4015f23) SHA1(7ce91eda76e86b5cab625e2b67c463b7d143832e) )
1313	1248	ROM_END
1314	1249
1315	1250	ROM_START( numanathj )
r32162	r32163
1328	1263	ROM_LOAD16_BYTE( "nm1-ma2u.bin", 0x400000, 0x100000, CRC(03a3f204) SHA1(9cb0422c8ecc819d0cc8a65c29a228369d78d986) )
1329	1264	ROM_LOAD16_BYTE( "nm1-ma3l.bin", 0x600001, 0x100000, CRC(42a539e9) SHA1(1c53a5a031648891ab7a37cf026c979404ce9589) )
1330	1265	ROM_LOAD16_BYTE( "nm1-ma3u.bin", 0x600000, 0x100000, CRC(f79e2112) SHA1(8bb8639a9d3a5d3ac5c9bb78e72b3d76582a9c25) )
1331
1332		/* M37702 BIOS - labeled as Namco custom C70 */
1333		ROM_REGION16_LE( 0x4000, "mcu", 0 )
1334		ROM_LOAD( "c70.bin",      0x000000, 0x004000, CRC(b4015f23) SHA1(7ce91eda76e86b5cab625e2b67c463b7d143832e) )
1335	1266	ROM_END
1336	1267
1337	1268	ROM_START( quiztou )
r32162	r32163
1351	1282	ROM_LOAD16_BYTE( "qt1ma3l.5c", 0x600001, 0x100000, CRC(aa9dc6ff) SHA1(c738f8c59bb5245874576c5bcf88c7138fa9a147) )
1352	1283	ROM_LOAD16_BYTE( "qt1ma3u.5f", 0x600000, 0x100000, CRC(14a5a163) SHA1(1107f50e491bedeb4ab7ac3f32cfe47727274ba9) )
1353	1284
1354		/* M37702 BIOS - labeled as Namco custom C70 */
1355		ROM_REGION16_LE( 0x4000, "mcu", 0 )
1356		ROM_LOAD( "c70.bin",      0x000000, 0x004000, CRC(b4015f23) SHA1(7ce91eda76e86b5cab625e2b67c463b7d143832e) )
1357
1358	1285	ROM_REGION( 0x0800, "eeprom", 0 ) // default eeprom, otherwise game would lock up on 1st boot
1359	1286	ROM_LOAD( "eeprom", 0x0000, 0x0800, CRC(57a478a6) SHA1(b6d66610690f2fdf6643b2de91e2345d15d839b1) )
1360	1287	ROM_END
r32162	r32163
1369	1296	ROM_LOAD16_BYTE( "xds1-dat1.8b", 0x000000, 0x200000, CRC(d250b7e8) SHA1(b99251ae8e25fae062d33e74ff800ab43fb308a2) )
1370	1297	ROM_LOAD16_BYTE( "xds1-dat2.4c", 0x400001, 0x200000, CRC(99d72a08) SHA1(4615b43b9a81240ffee8b0f021037f554f4f1f24) )
1371	1298	ROM_LOAD16_BYTE( "xds1-dat3.8c", 0x400000, 0x200000, CRC(8980acc4) SHA1(ecd94a3d3a38923e8e322cd8863671af26e30812) )
1372
1373		/* M37702 BIOS - labeled as Namco custom C70 */
1374		ROM_REGION16_LE( 0x4000, "mcu", 0 )
1375		ROM_LOAD( "c70.bin",      0x000000, 0x004000, CRC(b4015f23) SHA1(7ce91eda76e86b5cab625e2b67c463b7d143832e) )
1376	1299	ROM_END
1377	1300
1378	1301	// NA-1 (C69 MCU)

trunk/src/mame/drivers/namcos11.c

r32162	r32163
271	271
272	272	#include "emu.h"
273	273	#include "cpu/psx/psx.h"
274		#include "cpu/m37710/m37710.h"
275	274	#include "video/psx.h"
276	275	#include "machine/at28c16.h"
	276	#include "machine/namcomcu.h"
277	277	#include "machine/ns11prot.h"
278	278	#include "sound/c352.h"
279	279
r32162	r32163
466	466	AM_RANGE(0x001004, 0x001005) AM_READ_PORT("PLAYER1")
467	467	AM_RANGE(0x001006, 0x001007) AM_READ_PORT("PLAYER2")
468	468	AM_RANGE(0x004000, 0x00bfff) AM_RAM AM_SHARE("sharedram")
469		AM_RANGE(0x00c000, 0x00ffff) AM_ROM AM_REGION("c76", 0x40000)
470	469	AM_RANGE(0x080000, 0x0fffff) AM_ROM AM_REGION("c76", 0)
471	470	AM_RANGE(0x200000, 0x27ffff) AM_ROM AM_REGION("c76", 0)
472	471	AM_RANGE(0x280000, 0x2fffff) AM_ROM AM_REGION("c76", 0)
r32162	r32163
558	557	MCFG_RAM_DEFAULT_SIZE("4M")
559	558
560	559	/* basic machine hardware */
561		MCFG_CPU_ADD("c76", M37702, 16934400)
	560	MCFG_CPU_ADD("c76", NAMCO_C76, 16934400)
562	561	MCFG_CPU_PROGRAM_MAP(c76_map)
563	562	MCFG_CPU_IO_MAP(c76_io_map)
564	563	/* TODO: irq generation for these */
r32162	r32163
1028	1027	ROM_LOAD16_BYTE( "dc1rom3l.ic1", 0x0c00000, 0x200000, CRC(a76bcd4c) SHA1(817abdc43158b7aaac329c3ea17782277acb36a4) )
1029	1028	ROM_LOAD16_BYTE( "dc1rom3u.ic9", 0x0c00001, 0x200000, CRC(1405d123) SHA1(3d7be5558358740f5a0a3a3022543cf5aca4cf24) )
1030	1029
1031		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1030	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1032	1031	ROM_LOAD( "dc1sprog.6d",  0x0000000, 0x040000, CRC(96cd7788) SHA1(68a5a53a5fc50e2b6b684c99d27d81e3a8c56287) )
1033		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1034	1032
1035	1033	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1036	1034	ROM_LOAD( "dc1wave.8k",   0x000000, 0x400000, CRC(8ba0f6a7) SHA1(e9868debd808e92b196d1baeeeae9c4855356a01) )
r32162	r32163
1054	1052	ROM_LOAD16_BYTE( "dc1rom3l.ic1", 0x0c00000, 0x200000, CRC(a76bcd4c) SHA1(817abdc43158b7aaac329c3ea17782277acb36a4) )
1055	1053	ROM_LOAD16_BYTE( "dc1rom3u.ic9", 0x0c00001, 0x200000, CRC(1405d123) SHA1(3d7be5558358740f5a0a3a3022543cf5aca4cf24) )
1056	1054
1057		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1055	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1058	1056	ROM_LOAD( "dc1sprog.6d",  0x0000000, 0x040000, CRC(96cd7788) SHA1(68a5a53a5fc50e2b6b684c99d27d81e3a8c56287) )
1059		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1060	1057
1061	1058	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1062	1059	ROM_LOAD( "dc1wave.8k",   0x000000, 0x400000, CRC(8ba0f6a7) SHA1(e9868debd808e92b196d1baeeeae9c4855356a01) )
r32162	r32163
1080	1077	ROM_LOAD16_BYTE( "dm1rom1u.ic8", 0x0400001, 0x200000, CRC(01e905d3) SHA1(430b2ae0c67265b6acc8aa4dd50f6144929993f8) )
1081	1078	ROM_CONTINUE( 0x0400001, 0x200000 ) /* first & second half identical */
1082	1079
1083		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1080	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1084	1081	ROM_LOAD( "dm1sprog.6d",  0x0000000, 0x040000, CRC(de1cbc78) SHA1(855ebece1841f50ae324d7d6b8b18ab6f657d28e) )
1085		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1086	1082
1087	1083	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1088	1084	ROM_LOAD( "dm1wave.8k",   0x000000, 0x400000, CRC(4891d53e) SHA1(a1fee060e94d3219174b5974517f4fd3be32aaa5) )
r32162	r32163
1106	1102	ROM_LOAD16_BYTE( "dm1rom1u.ic8", 0x0400001, 0x200000, CRC(01e905d3) SHA1(430b2ae0c67265b6acc8aa4dd50f6144929993f8) )
1107	1103	ROM_CONTINUE( 0x0400001, 0x200000 ) /* first & second half identical */
1108	1104
1109		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1105	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data and MCU BIOS */
1110	1106	ROM_LOAD( "dm1sprog.6d",  0x0000000, 0x040000, CRC(de1cbc78) SHA1(855ebece1841f50ae324d7d6b8b18ab6f657d28e) )
1111		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1112	1107
1113	1108	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1114	1109	ROM_LOAD( "dm1wave.8k",   0x800000, 0x400000, CRC(4891d53e) SHA1(a1fee060e94d3219174b5974517f4fd3be32aaa5) )
r32162	r32163
1125	1120	ROM_LOAD16_BYTE( "kqt1prg1l.ic3", 0x1000000, 0x800000, CRC(298d8eeb) SHA1(c421b1bdd5fd46c026a41e2cec47cafd1a69d33d) )
1126	1121	ROM_LOAD16_BYTE( "kqt1prg1u.ic6", 0x1000001, 0x800000, CRC(911783db) SHA1(1005fc9b38e212844e397150a6f98f43ad88d4b9) )
1127	1122
1128		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1123	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1129	1124	ROM_LOAD( "kqt1sprog.7e", 0x0000000, 0x040000, CRC(bb1888a6) SHA1(4db07738079725413cdba7eb75252ee71ae50a66) )
1130		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1131	1125
1132	1126	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1133	1127	ROM_LOAD( "kqt1wave.8k",  0x000000, 0x400000, CRC(92ca8e4f) SHA1(48d6bdfcc5de1c280afa36c3f0dd6d4177771355) )
r32162	r32163
1143	1137	ROM_LOAD16_BYTE( "pkr1rom0l.ic5", 0x000000, 0x200000, CRC(6c9b074c) SHA1(885f342bd178e4146e1f75259206f6625c0b3c18) )
1144	1138	ROM_LOAD16_BYTE( "pkr1rom0u.ic6", 0x000001, 0x200000, CRC(a55c0906) SHA1(3b6abfa877f88a4d96222d98af02498b0c777af6) )
1145	1139
1146		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1140	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1147	1141	ROM_LOAD( "pkr1verb.6d",  0x000000, 0x040000, CRC(9bf08992) SHA1(fca7943f7bcf0ee758fa63fbdef8f7456b9e46cb) )
1148		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1149	1142
1150	1143	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1151	1144	ROM_LOAD( "pkr1wave.8k",  0x000000, 0x400000, CRC(72517c46) SHA1(d0dcc750fe8eca9e965e7c366ac39a42ffd76557) )
r32162	r32163
1167	1160	ROM_LOAD16_BYTE( "pg1rom1l.ic8", 0x0400001, 0x200000, CRC(59b5a71c) SHA1(ddc1f0a5488466166c21fd0c84ab2b4cf04316bf) )
1168	1161	ROM_CONTINUE( 0x0400001, 0x200000 ) /* first & second half identical */
1169	1162
1170		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1163	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1171	1164	ROM_LOAD( "pg1sprog.6d",  0x0000000, 0x040000, CRC(e7c3396d) SHA1(12bbb8ebcaab1b40462a12917dd9b58bd9ab8663) )
1172		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1173	1165
1174	1166	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1175	1167	ROM_LOAD( "pg1wave.8k",   0x0000000, 0x400000, CRC(fc9ad9eb) SHA1(ce5bb2288ed8cf1348825c39423cbb99d9324b9c) )
r32162	r32163
1187	1179	ROM_LOAD16_BYTE( "gnb1prg0l.ic2", 0x000000, 0x800000, CRC(78746037) SHA1(d130ca1153a730e3c967945248f00662f9fab304) )
1188	1180	ROM_LOAD16_BYTE( "gnb1prg0u.ic5", 0x000001, 0x800000, CRC(697d3279) SHA1(40302780f7494d9413888b2d1da38bd14a9a444f) )
1189	1181
1190		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1182	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1191	1183	ROM_LOAD( "gnb1vera.6d",  0x0000000, 0x040000, CRC(6461ae77) SHA1(1377b716a69ef9d4d2e48083d23f22bd5c103c00) )
1192		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1193	1184
1194	1185	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1195	1186	ROM_LOAD( "gnb1wave.8k",  0x0000000, 0x400000, CRC(4e19d9d6) SHA1(0a92c987536999a789663a30c787950ab6995128) )
r32162	r32163
1213	1204	ROM_LOAD16_BYTE( "so1rom3u.ic1", 0x0c00000, 0x200000, CRC(f11bd521) SHA1(baf936dec58cebfeef1c74f95e455b2fe74eb982) )
1214	1205	ROM_LOAD16_BYTE( "so1rom3l.ic9", 0x0c00001, 0x200000, CRC(84465bcc) SHA1(d8be888d41cfe194c3a1853d9146d3a74ef7bab1) )
1215	1206
1216		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1207	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1217	1208	ROM_LOAD( "so1sprogc.6d", 0x0000000, 0x040000, CRC(2bbc118c) SHA1(4168a9aa525f1f0ce6cf6e14cfe4c118c4c0d773) )
1218		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1219	1209
1220	1210	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1221	1211	ROM_LOAD( "so1wave.8k",   0x000000, 0x400000, CRC(0e68836b) SHA1(c392b370a807803c7ab060105861253e1b407f49) )
r32162	r32163
1239	1229	ROM_LOAD16_BYTE( "so1rom3u.ic1", 0x0c00000, 0x200000, CRC(f11bd521) SHA1(baf936dec58cebfeef1c74f95e455b2fe74eb982) )
1240	1230	ROM_LOAD16_BYTE( "so1rom3l.ic9", 0x0c00001, 0x200000, CRC(84465bcc) SHA1(d8be888d41cfe194c3a1853d9146d3a74ef7bab1) )
1241	1231
1242		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1232	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1243	1233	ROM_LOAD( "so1sprogc.6d", 0x0000000, 0x040000, CRC(2bbc118c) SHA1(4168a9aa525f1f0ce6cf6e14cfe4c118c4c0d773) )
1244		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1245	1234
1246	1235	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1247	1236	ROM_LOAD( "so1wave.8k",   0x000000, 0x400000, CRC(0e68836b) SHA1(c392b370a807803c7ab060105861253e1b407f49) )
r32162	r32163
1265	1254	ROM_LOAD16_BYTE( "so1rom3u.ic1", 0x0c00000, 0x200000, CRC(f11bd521) SHA1(baf936dec58cebfeef1c74f95e455b2fe74eb982) )
1266	1255	ROM_LOAD16_BYTE( "so1rom3l.ic9", 0x0c00001, 0x200000, CRC(84465bcc) SHA1(d8be888d41cfe194c3a1853d9146d3a74ef7bab1) )
1267	1256
1268		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1257	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1269	1258	ROM_LOAD( "so1sprog.6d",  0x0000000, 0x040000, CRC(f6f682b7) SHA1(a64e19be3f6e630b8c34f34b46b95aadfabd3f63) )
1270		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1271	1259
1272	1260	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1273	1261	ROM_LOAD( "so1wave.8k",   0x800000, 0x400000, CRC(0e68836b) SHA1(c392b370a807803c7ab060105861253e1b407f49) )
r32162	r32163
1290	1278	ROM_LOAD16_BYTE( "so1rom3u.ic1", 0x0c00000, 0x200000, CRC(f11bd521) SHA1(baf936dec58cebfeef1c74f95e455b2fe74eb982) )
1291	1279	ROM_LOAD16_BYTE( "so1rom3l.ic9", 0x0c00001, 0x200000, CRC(84465bcc) SHA1(d8be888d41cfe194c3a1853d9146d3a74ef7bab1) )
1292	1280
1293		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1281	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1294	1282	ROM_LOAD( "so1sprog.6d",  0x0000000, 0x040000, CRC(f6f682b7) SHA1(a64e19be3f6e630b8c34f34b46b95aadfabd3f63) )
1295		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1296	1283
1297	1284	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1298	1285	ROM_LOAD( "so1wave.8k",   0x000000, 0x400000, CRC(0e68836b) SHA1(c392b370a807803c7ab060105861253e1b407f49) )
r32162	r32163
1316	1303	ROM_LOAD16_BYTE( "so1rom3u.ic1", 0x0c00000, 0x200000, CRC(f11bd521) SHA1(baf936dec58cebfeef1c74f95e455b2fe74eb982) )
1317	1304	ROM_LOAD16_BYTE( "so1rom3l.ic9", 0x0c00001, 0x200000, CRC(84465bcc) SHA1(d8be888d41cfe194c3a1853d9146d3a74ef7bab1) )
1318	1305
1319		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1306	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1320	1307	ROM_LOAD( "so1sprog.6d",  0x0000000, 0x040000, CRC(f6f682b7) SHA1(a64e19be3f6e630b8c34f34b46b95aadfabd3f63) )
1321		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1322	1308
1323	1309	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1324	1310	ROM_LOAD( "so1wave.8k",   0x000000, 0x400000, CRC(0e68836b) SHA1(c392b370a807803c7ab060105861253e1b407f49) )
r32162	r32163
1330	1316	ROM_LOAD( "stp1vera.1j",         0x0000000, 0x200000, CRC(ef83e126) SHA1(f721b43358cedad0f28af5d2b292b44043fd47a0) )
1331	1317	ROM_LOAD( "stp1vera.1l",         0x0200000, 0x200000, CRC(0ee7fe1e) SHA1(8c2f5b0e7b49dbe0e8105bf55c493acd46a4f59d) )
1332	1318
1333		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1319	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1334	1320	ROM_LOAD( "stp1sprog.7e", 0x0000000, 0x040000, CRC(08aaaf6a) SHA1(51c913a39ff7c154aef8bb10139cc8b92eb4756a) )
1335		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1336	1321
1337	1322	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1338	1323	ROM_LOAD( "stp1wave.8k",  0x000000, 0x400000, CRC(18f30e92) SHA1(b3819455856298527a7224495f541145aecf23dd) )
r32162	r32163
1354	1339	ROM_LOAD16_BYTE( "te1rom2l.ic4", 0x0800000, 0x200000, CRC(41d77846) SHA1(eeab049135c02a255899fe37e225c1111b2fbb7d) )
1355	1340	ROM_LOAD16_BYTE( "te1rom2u.ic7", 0x0800001, 0x200000, CRC(a678987e) SHA1(c62c00ce5cf4d001723c999b2bc3dbb90283def1) )
1356	1341
1357		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1342	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1358	1343	ROM_LOAD( "te1sprog.6d",  0x0000000, 0x040000, CRC(849587e9) SHA1(94c6a757b24758a866a41bd8acd46aa46844f74b) )
1359		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1360	1344
1361	1345	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1362	1346	ROM_LOAD( "te1wave.8k",   0x0000000, 0x200000, CRC(fce6c57a) SHA1(7fb8c69452c92c59a940a2b69d0d73ef7aefcb82) )
r32162	r32163
1377	1361	ROM_LOAD16_BYTE( "te1rom2l.ic4", 0x0800000, 0x200000, CRC(41d77846) SHA1(eeab049135c02a255899fe37e225c1111b2fbb7d) )
1378	1362	ROM_LOAD16_BYTE( "te1rom2u.ic7", 0x0800001, 0x200000, CRC(a678987e) SHA1(c62c00ce5cf4d001723c999b2bc3dbb90283def1) )
1379	1363
1380		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1364	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1381	1365	ROM_LOAD( "te1sprog.6d",  0x0000000, 0x040000, CRC(849587e9) SHA1(94c6a757b24758a866a41bd8acd46aa46844f74b) )
1382		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1383	1366
1384	1367	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1385	1368	ROM_LOAD( "te1wave.8k",   0x0000000, 0x200000, CRC(fce6c57a) SHA1(7fb8c69452c92c59a940a2b69d0d73ef7aefcb82) )
r32162	r32163
1400	1383	ROM_LOAD16_BYTE( "te1rom2l.ic4", 0x0800000, 0x200000, CRC(41d77846) SHA1(eeab049135c02a255899fe37e225c1111b2fbb7d) )
1401	1384	ROM_LOAD16_BYTE( "te1rom2u.ic7", 0x0800001, 0x200000, CRC(a678987e) SHA1(c62c00ce5cf4d001723c999b2bc3dbb90283def1) )
1402	1385
1403		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1386	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1404	1387	ROM_LOAD( "te1sprog.6d",  0x0000000, 0x040000, CRC(849587e9) SHA1(94c6a757b24758a866a41bd8acd46aa46844f74b) )
1405		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1406	1388
1407	1389	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1408	1390	ROM_LOAD( "te1wave.8k",   0x0000000, 0x200000, CRC(fce6c57a) SHA1(7fb8c69452c92c59a940a2b69d0d73ef7aefcb82) )
r32162	r32163
1423	1405	ROM_LOAD16_BYTE( "te1rom2l.ic4", 0x0800000, 0x200000, CRC(41d77846) SHA1(eeab049135c02a255899fe37e225c1111b2fbb7d) )
1424	1406	ROM_LOAD16_BYTE( "te1rom2u.ic7", 0x0800001, 0x200000, CRC(a678987e) SHA1(c62c00ce5cf4d001723c999b2bc3dbb90283def1) )
1425	1407
1426		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1408	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1427	1409	ROM_LOAD( "te1sprog.6d",  0x0000000, 0x040000, CRC(849587e9) SHA1(94c6a757b24758a866a41bd8acd46aa46844f74b) )
1428		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1429	1410
1430	1411	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1431	1412	ROM_LOAD( "te1wave.8k",   0x0000000, 0x200000, CRC(fce6c57a) SHA1(7fb8c69452c92c59a940a2b69d0d73ef7aefcb82) )
r32162	r32163
1448	1429	ROM_LOAD16_BYTE( "tes1rom3l.ic9", 0x0c00000, 0x200000, CRC(d5ac0f18) SHA1(342d063f7974bd1f90b5ca4832dfa4fbc9605453) )
1449	1430	ROM_LOAD16_BYTE( "tes1rom3u.ic1", 0x0c00001, 0x200000, CRC(44ed509d) SHA1(27e26aaf5ce72ab686f3f05743b1d91b5334b4e0) )
1450	1431
1451		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1432	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1452	1433	ROM_LOAD( "tes1sprog.6d", 0x0000000, 0x040000, CRC(af18759f) SHA1(aabd7d1384925781d37f860605a5d4622e0fc2e4) )
1453		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1454	1434
1455	1435	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1456	1436	ROM_LOAD( "tes1wave.8k",  0x800000, 0x400000, CRC(34a34eab) SHA1(8e83a579abdcd419dc5cff8aa4c1d7e6c3add773) )
r32162	r32163
1473	1453	ROM_LOAD16_BYTE( "tes1rom3l.ic9", 0x0c00000, 0x200000, CRC(d5ac0f18) SHA1(342d063f7974bd1f90b5ca4832dfa4fbc9605453) )
1474	1454	ROM_LOAD16_BYTE( "tes1rom3u.ic1", 0x0c00001, 0x200000, CRC(44ed509d) SHA1(27e26aaf5ce72ab686f3f05743b1d91b5334b4e0) )
1475	1455
1476		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1456	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1477	1457	ROM_LOAD( "tes1sprog.6d", 0x0000000, 0x040000, CRC(af18759f) SHA1(aabd7d1384925781d37f860605a5d4622e0fc2e4) )
1478		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1479	1458
1480	1459	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1481	1460	ROM_LOAD( "tes1wave.8k",  0x800000, 0x400000, CRC(34a34eab) SHA1(8e83a579abdcd419dc5cff8aa4c1d7e6c3add773) )
r32162	r32163
1498	1477	ROM_LOAD16_BYTE( "tes1rom3l.ic9", 0x0c00000, 0x200000, CRC(d5ac0f18) SHA1(342d063f7974bd1f90b5ca4832dfa4fbc9605453) )
1499	1478	ROM_LOAD16_BYTE( "tes1rom3u.ic1", 0x0c00001, 0x200000, CRC(44ed509d) SHA1(27e26aaf5ce72ab686f3f05743b1d91b5334b4e0) )
1500	1479
1501		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1480	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1502	1481	ROM_LOAD( "tes1sprog.6d", 0x0000000, 0x040000, CRC(af18759f) SHA1(aabd7d1384925781d37f860605a5d4622e0fc2e4) )
1503		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1504	1482
1505	1483	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1506	1484	ROM_LOAD( "tes1wave.8k",  0x800000, 0x400000, CRC(34a34eab) SHA1(8e83a579abdcd419dc5cff8aa4c1d7e6c3add773) )
r32162	r32163
1523	1501	ROM_LOAD16_BYTE( "tes1rom3l.ic9", 0x0c00000, 0x200000, CRC(d5ac0f18) SHA1(342d063f7974bd1f90b5ca4832dfa4fbc9605453) )
1524	1502	ROM_LOAD16_BYTE( "tes1rom3u.ic1", 0x0c00001, 0x200000, CRC(44ed509d) SHA1(27e26aaf5ce72ab686f3f05743b1d91b5334b4e0) )
1525	1503
1526		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1504	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1527	1505	ROM_LOAD( "tes1sprog.6d", 0x0000000, 0x040000, CRC(af18759f) SHA1(aabd7d1384925781d37f860605a5d4622e0fc2e4) )
1528		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1529	1506
1530	1507	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1531	1508	ROM_LOAD( "tes1wave.8k",  0x800000, 0x400000, CRC(34a34eab) SHA1(8e83a579abdcd419dc5cff8aa4c1d7e6c3add773) )
r32162	r32163
1548	1525	ROM_LOAD16_BYTE( "tes1rom3l.ic9", 0x0c00000, 0x200000, CRC(d5ac0f18) SHA1(342d063f7974bd1f90b5ca4832dfa4fbc9605453) )
1549	1526	ROM_LOAD16_BYTE( "tes1rom3u.ic1", 0x0c00001, 0x200000, CRC(44ed509d) SHA1(27e26aaf5ce72ab686f3f05743b1d91b5334b4e0) )
1550	1527
1551		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1528	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1552	1529	ROM_LOAD( "tes1sprog.6d", 0x0000000, 0x040000, CRC(af18759f) SHA1(aabd7d1384925781d37f860605a5d4622e0fc2e4) )
1553		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1554	1530
1555	1531	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1556	1532	ROM_LOAD( "tes1wave.8k",  0x800000, 0x400000, CRC(34a34eab) SHA1(8e83a579abdcd419dc5cff8aa4c1d7e6c3add773) )
r32162	r32163
1573	1549	ROM_LOAD16_BYTE( "tes1rom3l.ic9", 0x0c00000, 0x200000, CRC(d5ac0f18) SHA1(342d063f7974bd1f90b5ca4832dfa4fbc9605453) )
1574	1550	ROM_LOAD16_BYTE( "tes1rom3u.ic1", 0x0c00001, 0x200000, CRC(44ed509d) SHA1(27e26aaf5ce72ab686f3f05743b1d91b5334b4e0) )
1575	1551
1576		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1552	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1577	1553	ROM_LOAD( "tes1sprog.6d", 0x0000000, 0x040000, CRC(af18759f) SHA1(aabd7d1384925781d37f860605a5d4622e0fc2e4) )
1578		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1579	1554
1580	1555	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1581	1556	ROM_LOAD( "tes1wave.8k",  0x800000, 0x400000, CRC(34a34eab) SHA1(8e83a579abdcd419dc5cff8aa4c1d7e6c3add773) )
r32162	r32163
1596	1571	ROM_LOAD16_BYTE( "xv31rom2l.ic4", 0x0800000, 0x200000, CRC(8403a277) SHA1(35193211351494a086d8422e3b0b71a8d3a262a6) )
1597	1572	ROM_LOAD16_BYTE( "xv31rom2u.ic7", 0x0800001, 0x200000, CRC(ecf70432) SHA1(bec128a215e0aef66e9a8707bb0d1eb7b098a356) )
1598	1573
1599		ROM_REGION16_LE( 0x100000, "c76", 0 ) /* sound data and MCU BIOS */
	1574	ROM_REGION16_LE( 0x80000, "c76", 0 ) /* sound data */
1600	1575	ROM_LOAD( "xv31sprog.6d", 0x0000000, 0x040000, CRC(e50b856a) SHA1(631da4f60c9ce08387fca26a70481a2fdacf9765) )
1601		ROM_LOAD( "c76.bin",      0x040000, 0x004000, CRC(399faac7) SHA1(ceb184ef0486caf715dd997101999785f67a40b8) )
1602	1576
1603	1577	ROM_REGION( 0x1000000, "c352", 0 ) /* samples */
1604	1578	ROM_LOAD( "xv31wave.8k",  0x000000, 0x400000, CRC(14f25ddd) SHA1(4981cf1017432ff85b768ec88c36f535df30b783) )

trunk/src/mame/drivers/globalfr.c

r32162	r32163
63	63
64	64	static MACHINE_CONFIG_START( globalfr, globalfr_state )
65	65	/* basic machine hardware */
66		MCFG_CPU_ADD("maincpu", M37710, 4000000)
	66	MCFG_CPU_ADD("maincpu", M37702S1, 4000000)
67	67	MCFG_CPU_PROGRAM_MAP(globalfr_map)
68	68	MCFG_S16LF01_ADD("vfd",0)
69	69	MCFG_DEFAULT_LAYOUT(layout_globalfr)

trunk/src/mame/drivers/namcos22.c

r32162	r32163
1158	1158	#include "includes/namcos22.h"
1159	1159	#include "cpu/m68000/m68000.h"
1160	1160	#include "cpu/tms32025/tms32025.h"
1161		#include "cpu/m37710/m37710.h"
	1161	#include "machine/namcomcu.h"
1162	1162	#include "sound/c352.h"
1163	1163
1164	1164	#define SS22_MASTER_CLOCK   (XTAL_49_152MHz)    /* info from Guru */
r32162	r32163
2714	2714	static ADDRESS_MAP_START( mcu_s22_program, AS_PROGRAM, 16, namcos22_state )
2715	2715	AM_RANGE(0x002000, 0x002fff) AM_DEVREADWRITE("c352", c352_device, read, write)
2716	2716	AM_RANGE(0x004000, 0x00bfff) AM_READWRITE(s22mcu_shared_r, s22mcu_shared_w )
2717		AM_RANGE(0x00c000, 0x00ffff) AM_ROM AM_REGION("mcu_c74", 0)
2718	2717	AM_RANGE(0x080000, 0x0fffff) AM_ROM AM_REGION("mcu", 0)
2719	2718	AM_RANGE(0x200000, 0x27ffff) AM_ROM AM_REGION("mcu", 0)
2720	2719	AM_RANGE(0x280000, 0x2fffff) AM_ROM AM_REGION("mcu", 0)
r32162	r32163
2723	2722	ADDRESS_MAP_END
2724	2723
2725	2724	static ADDRESS_MAP_START( iomcu_s22_program, AS_PROGRAM, 16, namcos22_state )
2726		AM_RANGE(0x00c000, 0x00ffff) AM_ROM AM_REGION("iomcu", 0)
	2725	// is there any external memory or MMIO on this one?
2727	2726	ADDRESS_MAP_END
2728	2727
2729	2728	static ADDRESS_MAP_START( mcu_s22_io, AS_IO, 8, namcos22_state )
r32162	r32163
3762	3761	MCFG_CPU_IO_MAP(slave_dsp_io)
3763	3762	MCFG_TIMER_DRIVER_ADD_SCANLINE("slave_st", namcos22_state, dsp_slave_serial_irq, "screen", 0, 1)
3764	3763
3765		MCFG_CPU_ADD("mcu", M37702, SS22_MASTER_CLOCK/3) // C74 on the CPU board has no periodic interrupts, it runs entirely off Timer A0
	3764	MCFG_CPU_ADD("mcu", NAMCO_C74, SS22_MASTER_CLOCK/3) // C74 on the CPU board has no periodic interrupts, it runs entirely off Timer A0
3766	3765	MCFG_CPU_PROGRAM_MAP( mcu_s22_program)
3767	3766	MCFG_CPU_IO_MAP( mcu_s22_io)
3768	3767
3769		MCFG_CPU_ADD("iomcu", M37702, XTAL_6_144MHz) // 6.144MHz XTAL on I/O board, not sure if it has a divider
	3768	MCFG_CPU_ADD("iomcu", NAMCO_C74, XTAL_6_144MHz) // 6.144MHz XTAL on I/O board, not sure if it has a divider
3770	3769	MCFG_CPU_PROGRAM_MAP( iomcu_s22_program)
3771	3770	MCFG_CPU_IO_MAP( iomcu_s22_io)
3772	3771
r32162	r32163
3813	3812	MCFG_CPU_IO_MAP(slave_dsp_io)
3814	3813	MCFG_TIMER_DRIVER_ADD_SCANLINE("slave_st", namcos22_state, dsp_slave_serial_irq, "screen", 0, 1)
3815	3814
3816		MCFG_CPU_ADD("mcu", M37710, SS22_MASTER_CLOCK/3)
	3815	MCFG_CPU_ADD("mcu", M37710S4, SS22_MASTER_CLOCK/3)
3817	3816	MCFG_CPU_PROGRAM_MAP(mcu_program)
3818	3817	MCFG_CPU_IO_MAP(mcu_io)
3819	3818	MCFG_TIMER_DRIVER_ADD_SCANLINE("mcu_st", namcos22_state, mcu_irq, "screen", 0, 1)
r32162	r32163
3908	3907	ROM_REGION( 0x10000*2, "slave", 0 ) /* Slave DSP */
3909	3908	ROM_LOAD16_WORD( "c71.bin", 0,0x1000*2, CRC(47c623ab) SHA1(e363ac50f5556f83308d4cc191b455e9b62bcfc8) )
3910	3909
3911		ROM_REGION16_LE( 0x4000, "iomcu", 0 ) /* I/O MCU BIOS */
3912		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
3913
3914		ROM_REGION16_LE( 0x4000, "mcu_c74", 0 ) /* SUB/SOUND MCU BIOS */
3915		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
3916
3917	3910	ROM_REGION16_LE( 0x80000, "mcu", 0 ) /* sound data */
3918	3911	ROM_LOAD( "rr1data.6r", 0, 0x080000, CRC(18f5f748) SHA1(e0d149a66de36156edd9b55f604c9a9801aaefa8) )
3919	3912
r32162	r32163
3960	3953	ROM_REGION( 0x10000*2, "slave", 0 ) /* Slave DSP */
3961	3954	ROM_LOAD16_WORD( "c71.bin", 0,0x1000*2, CRC(47c623ab) SHA1(e363ac50f5556f83308d4cc191b455e9b62bcfc8) )
3962	3955
3963		ROM_REGION16_LE( 0x4000, "iomcu", 0 ) /* I/O MCU BIOS */
3964		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
3965
3966		ROM_REGION16_LE( 0x4000, "mcu_c74", 0 ) /* SUB/SOUND MCU BIOS */
3967		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
3968
3969	3956	ROM_REGION16_LE( 0x80000, "mcu", 0 ) /* sound data */
3970	3957	ROM_LOAD( "rr1data.6r", 0, 0x080000, CRC(18f5f748) SHA1(e0d149a66de36156edd9b55f604c9a9801aaefa8) )
3971	3958
r32162	r32163
4012	3999	ROM_REGION( 0x10000*2, "slave", 0 ) /* Slave DSP */
4013	4000	ROM_LOAD16_WORD( "c71.bin", 0,0x1000*2, CRC(47c623ab) SHA1(e363ac50f5556f83308d4cc191b455e9b62bcfc8) )
4014	4001
4015		ROM_REGION16_LE( 0x4000, "iomcu", 0 ) /* I/O MCU BIOS */
4016		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4017
4018		ROM_REGION16_LE( 0x4000, "mcu_c74", 0 ) /* SUB/SOUND MCU BIOS */
4019		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4020
4021	4002	ROM_REGION16_LE( 0x80000, "mcu", 0 ) /* sound data */
4022	4003	ROM_LOAD( "rr1data.6r", 0, 0x080000, CRC(18f5f748) SHA1(e0d149a66de36156edd9b55f604c9a9801aaefa8) )
4023	4004
r32162	r32163
4064	4045	ROM_REGION( 0x10000*2, "slave", 0 ) /* Slave DSP */
4065	4046	ROM_LOAD16_WORD( "c71.bin", 0,0x1000*2, CRC(47c623ab) SHA1(e363ac50f5556f83308d4cc191b455e9b62bcfc8) )
4066	4047
4067		ROM_REGION16_LE( 0x4000, "iomcu", 0 ) /* I/O MCU BIOS */
4068		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4069
4070		ROM_REGION16_LE( 0x4000, "mcu_c74", 0 ) /* SUB/SOUND MCU BIOS */
4071		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4072
4073	4048	ROM_REGION16_LE( 0x80000, "mcu", 0 ) /* sound data */
4074	4049	ROM_LOAD( "rr1data.6r", 0, 0x080000, CRC(18f5f748) SHA1(e0d149a66de36156edd9b55f604c9a9801aaefa8) )
4075	4050
r32162	r32163
4116	4091	ROM_REGION( 0x10000*2, "slave", 0 ) /* Slave DSP */
4117	4092	ROM_LOAD16_WORD( "c71.bin", 0,0x1000*2, CRC(47c623ab) SHA1(e363ac50f5556f83308d4cc191b455e9b62bcfc8) )
4118	4093
4119		ROM_REGION16_LE( 0x4000, "iomcu", 0 ) /* I/O MCU BIOS */
4120		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4121
4122		ROM_REGION16_LE( 0x4000, "mcu_c74", 0 ) /* SUB/SOUND MCU BIOS */
4123		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4124
4125	4094	ROM_REGION16_LE( 0x80000, "mcu", 0 ) /* sound data */
4126	4095	ROM_LOAD( "rrf1data.6r", 0, 0x080000, CRC(ce3c6ed6) SHA1(23e033364bc967c10c49fd1d5413dda837670633) )
4127	4096
r32162	r32163
4170	4139	ROM_REGION( 0x10000*2, "slave", 0 ) /* Slave DSP */
4171	4140	ROM_LOAD16_WORD( "c71.bin", 0,0x1000*2, CRC(47c623ab) SHA1(e363ac50f5556f83308d4cc191b455e9b62bcfc8) )
4172	4141
4173		ROM_REGION16_LE( 0x4000, "iomcu", 0 ) /* I/O MCU BIOS */
4174		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4175
4176		ROM_REGION16_LE( 0x4000, "mcu_c74", 0 ) /* SUB/SOUND MCU BIOS */
4177		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4178
4179	4142	ROM_REGION16_LE( 0x80000, "mcu", 0 ) /* sound data */
4180	4143	ROM_LOAD( "rrs1data.6r", 0, 0x080000, CRC(b7063aa8) SHA1(08ff689e8dd529b91eee423c93f084945c6de417) )
4181	4144
r32162	r32163
4222	4185	ROM_REGION( 0x10000*2, "slave", 0 ) /* Slave DSP */
4223	4186	ROM_LOAD16_WORD( "c71.bin", 0,0x1000*2, CRC(47c623ab) SHA1(e363ac50f5556f83308d4cc191b455e9b62bcfc8) )
4224	4187
4225		ROM_REGION16_LE( 0x4000, "iomcu", 0 ) /* I/O MCU BIOS */
4226		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4227
4228		ROM_REGION16_LE( 0x4000, "mcu_c74", 0 ) /* SUB/SOUND MCU BIOS */
4229		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4230
4231	4188	ROM_REGION16_LE( 0x80000, "mcu", 0 ) /* sound data */
4232	4189	ROM_LOAD( "rrs1data.6r", 0, 0x080000, CRC(b7063aa8) SHA1(08ff689e8dd529b91eee423c93f084945c6de417) )
4233	4190
r32162	r32163
4274	4231	ROM_REGION( 0x10000*2, "slave", 0 ) /* Slave DSP */
4275	4232	ROM_LOAD16_WORD( "c71.bin", 0,0x1000*2, CRC(47c623ab) SHA1(e363ac50f5556f83308d4cc191b455e9b62bcfc8) )
4276	4233
4277		ROM_REGION16_LE( 0x4000, "iomcu", 0 ) /* I/O MCU BIOS */
4278		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4279
4280		ROM_REGION16_LE( 0x4000, "mcu_c74", 0 ) /* SUB/SOUND MCU BIOS */
4281		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4282
4283	4234	ROM_REGION16_LE( 0x80000, "mcu", 0 ) /* sound data */
4284	4235	ROM_LOAD( "rrs1data.6r", 0, 0x080000, CRC(b7063aa8) SHA1(08ff689e8dd529b91eee423c93f084945c6de417) )
4285	4236
r32162	r32163
4327	4278	ROM_REGION( 0x10000*2, "slave", 0 ) /* Slave DSP */
4328	4279	ROM_LOAD16_WORD( "c71.bin", 0,0x1000*2, CRC(47c623ab) SHA1(e363ac50f5556f83308d4cc191b455e9b62bcfc8) )
4329	4280
4330		ROM_REGION16_LE( 0x4000, "iomcu", 0 ) /* I/O MCU BIOS */
4331		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4332
4333		ROM_REGION16_LE( 0x4000, "mcu_c74", 0 ) /* SUB/SOUND MCU BIOS */
4334		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4335
4336	4281	ROM_REGION16_LE( 0x80000, "mcu", 0 ) /* sound data */
4337	4282	ROM_LOAD( "rv1data.6r", 0, 0x080000, CRC(d358ec20) SHA1(140c513349240417bb546dd2d151f3666b818e91) )
4338	4283
r32162	r32163
4392	4337	ROM_REGION( 0x10000*2, "slave", 0 ) /* Slave DSP */
4393	4338	ROM_LOAD16_WORD( "c71.bin", 0,0x1000*2, CRC(47c623ab) SHA1(e363ac50f5556f83308d4cc191b455e9b62bcfc8) )
4394	4339
4395		ROM_REGION16_LE( 0x4000, "iomcu", 0 ) /* I/O MCU BIOS */
4396		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4397
4398		ROM_REGION16_LE( 0x4000, "mcu_c74", 0 ) /* SUB/SOUND MCU BIOS */
4399		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4400
4401	4340	ROM_REGION16_LE( 0x80000, "mcu", 0 ) /* sound data */
4402	4341	ROM_LOAD( "rv1data.6r", 0, 0x080000, CRC(d358ec20) SHA1(140c513349240417bb546dd2d151f3666b818e91) )
4403	4342
r32162	r32163
4457	4396	ROM_REGION( 0x10000*2, "slave", 0 ) /* Slave DSP */
4458	4397	ROM_LOAD16_WORD( "c71.bin", 0,0x1000*2, CRC(47c623ab) SHA1(e363ac50f5556f83308d4cc191b455e9b62bcfc8) )
4459	4398
4460		ROM_REGION16_LE( 0x4000, "iomcu", 0 ) /* I/O MCU BIOS */
4461		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4462
4463		ROM_REGION16_LE( 0x4000, "mcu_c74", 0 ) /* SUB/SOUND MCU BIOS */
4464		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4465
4466	4399	ROM_REGION16_LE( 0x80000, "mcu", 0 ) /* sound data */
4467	4400	ROM_LOAD( "rv1data.6r", 0, 0x080000, CRC(d358ec20) SHA1(140c513349240417bb546dd2d151f3666b818e91) )
4468	4401
r32162	r32163
4523	4456	ROM_REGION( 0x10000*2, "slave", 0 ) /* Slave DSP */
4524	4457	ROM_LOAD16_WORD( "c71.bin", 0,0x1000*2, CRC(47c623ab) SHA1(e363ac50f5556f83308d4cc191b455e9b62bcfc8) )
4525	4458
4526		ROM_REGION16_LE( 0x4000, "iomcu", 0 ) /* I/O MCU BIOS */
4527		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4528
4529		ROM_REGION16_LE( 0x4000, "mcu_c74", 0 ) /* SUB/SOUND MCU BIOS */
4530		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4531
4532	4459	ROM_REGION16_LE( 0x80000, "mcu", 0 ) /* sound data */
4533	4460	ROM_LOAD( "cy1data.6r", 0x00000, 0x20000, CRC(10d0005b) SHA1(10508eeaf74d24a611b44cd3bb12417ceb78904f) )
4534	4461	ROM_RELOAD(             0x20000, 0x20000)
r32162	r32163
4589	4516	ROM_REGION( 0x10000*2, "slave", 0 ) /* Slave DSP */
4590	4517	ROM_LOAD16_WORD( "c71.bin", 0,0x1000*2, CRC(47c623ab) SHA1(e363ac50f5556f83308d4cc191b455e9b62bcfc8) )
4591	4518
4592		ROM_REGION16_LE( 0x4000, "iomcu", 0 ) /* I/O MCU BIOS */
4593		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4594
4595		ROM_REGION16_LE( 0x4000, "mcu_c74", 0 ) /* SUB/SOUND MCU BIOS */
4596		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4597
4598	4519	ROM_REGION16_LE( 0x80000, "mcu", 0 ) /* sound data */
4599	4520	ROM_LOAD( "ad1data.6r", 0, 0x080000, CRC(82024f74) SHA1(711ab0c4f027716aeab18e3a5d3d06fa82af8007) )
4600	4521
r32162	r32163
4642	4563	ROM_REGION( 0x10000*2, "slave", 0 ) /* Slave DSP */
4643	4564	ROM_LOAD16_WORD( "c71.bin", 0,0x1000*2, CRC(47c623ab) SHA1(e363ac50f5556f83308d4cc191b455e9b62bcfc8) )
4644	4565
4645		ROM_REGION16_LE( 0x4000, "iomcu", 0 ) /* I/O MCU BIOS */
4646		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4647
4648		ROM_REGION16_LE( 0x4000, "mcu_c74", 0 ) /* SUB/SOUND MCU BIOS */
4649		ROM_LOAD( "c74.bin", 0x0000, 0x4000, CRC(a3dce360) SHA1(8f3248b1890abb2e649927240ae46f73bb171e3b) )
4650
4651	4566	ROM_REGION16_LE( 0x80000, "mcu", 0 ) /* sound data */
4652	4567	ROM_LOAD( "adv1data.6r", 0, 0x080000, CRC(10eecdb4) SHA1(aaedeed166614e6670e765e0d7e4e9eb5f38ad10) )
4653	4568

trunk/src/mame/drivers/namcofl.c

r32162	r32163
158	158	#include "emu.h"
159	159	#include "includes/namcoic.h"
160	160	#include "cpu/i960/i960.h"
161		#include "cpu/m37710/m37710.h"
162	161	#include "sound/c352.h"
	162	#include "machine/namcomcu.h"
163	163	#include "machine/nvram.h"
164	164	#include "namcofl.lh"
165	165	#include "includes/namcofl.h"
r32162	r32163
324	324	static ADDRESS_MAP_START( namcoc75_am, AS_PROGRAM, 16, namcofl_state )
325	325	AM_RANGE(0x002000, 0x002fff) AM_DEVREADWRITE("c352", c352_device, read, write)
326	326	AM_RANGE(0x004000, 0x00bfff) AM_RAM_WRITE(mcu_shared_w) AM_SHARE("shareram")
327		AM_RANGE(0x00c000, 0x00ffff) AM_ROM AM_REGION("c75", 0)
328	327	AM_RANGE(0x200000, 0x27ffff) AM_ROM AM_REGION("c75data", 0)
329	328	ADDRESS_MAP_END
330	329
r32162	r32163
582	581	MCFG_CPU_ADD("maincpu", I960, 20000000) // i80960KA-20 == 20 MHz part
583	582	MCFG_CPU_PROGRAM_MAP(namcofl_mem)
584	583
585		MCFG_CPU_ADD("mcu", M37702, 48384000/3)
	584	MCFG_CPU_ADD("mcu", NAMCO_C75, 48384000/3)
586	585	MCFG_CPU_PROGRAM_MAP(namcoc75_am)
587	586	MCFG_CPU_IO_MAP(namcoc75_io)
588	587	/* TODO: irq generation for these */
r32162	r32163
629	628	ROM_LOAD32_BYTE("se1_dat2.15a",   0x000002, 0x080000, CRC(2a29abbb) SHA1(945419ed61e9a656a340214a63a01818396fbe98) )
630	629	ROM_LOAD32_BYTE("se1_dat3.16a",   0x000003, 0x080000, CRC(49849aff) SHA1(b7c7eea1d56304e40e996ee998c971313ff03614) )
631	630
632		ROM_REGION16_LE( 0x4000, "c75", 0 ) // C75 program
633		ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )
634
635	631	ROM_REGION16_LE( 0x80000, "c75data", 0 ) // C75 data
636	632	ROM_LOAD("se1_spr.21l",   0x000000,  0x80000, CRC(850a27ac) SHA1(7d5db840ec67659a1f2e69a62cdb03ce6ee0b47b) )
637	633
r32162	r32163
681	677
682	678	ROM_REGION32_LE( 0x200000, "data", ROMREGION_ERASEFF ) // Data
683	679
684		ROM_REGION16_LE( 0x4000, "c75", 0 ) // C75 program
685		ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )
686
687	680	ROM_REGION16_LE( 0x80000, "c75data", 0 ) // C75 data
688	681	ROM_LOAD("flr1spr.21l",   0x000000,  0x20000, CRC(69bb0f5e) SHA1(6831d618de42a165e508ad37db594d3aa290c530) )
689	682
r32162	r32163
723	716
724	717	ROM_REGION32_LE( 0x200000, "data", ROMREGION_ERASEFF ) // Data
725	718
726		ROM_REGION16_LE( 0x4000, "c75", 0 ) // C75 program
727		ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )
728
729	719	ROM_REGION16_LE( 0x80000, "c75data", 0 ) // C75 data
730	720	ROM_LOAD("flr1spr.21l",   0x000000,  0x20000, CRC(69bb0f5e) SHA1(6831d618de42a165e508ad37db594d3aa290c530) )
731	721
r32162	r32163
766	756
767	757	ROM_REGION32_LE( 0x200000, "data", ROMREGION_ERASEFF ) // Data
768	758
769		ROM_REGION16_LE( 0x4000, "c75", 0 ) // C75 program
770		ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )
771
772	759	ROM_REGION16_LE( 0x80000, "c75data", 0 ) // C75 data
773	760	ROM_LOAD("flr1spr.21l",   0x000000,  0x20000, CRC(69bb0f5e) SHA1(6831d618de42a165e508ad37db594d3aa290c530) )
774	761

trunk/src/mame/drivers/namconb1.c

r32162	r32163
273	273	#include "cpu/m68000/m68000.h"
274	274	#include "includes/namconb1.h"
275	275	#include "includes/namcoic.h"
	276	#include "machine/namcomcu.h"
276	277	#include "sound/c352.h"
277		#include "cpu/m37710/m37710.h"
278	278
279	279	#define MASTER_CLOCK    XTAL_48_384MHz
280	280
r32162	r32163
717	717	static ADDRESS_MAP_START( namcoc75_am, AS_PROGRAM, 16, namconb1_state )
718	718	AM_RANGE(0x002000, 0x002fff) AM_DEVREADWRITE("c352", c352_device, read, write)
719	719	AM_RANGE(0x004000, 0x00bfff) AM_RAM_WRITE(nbmcu_shared_w) AM_SHARE("namconb_share")
720		AM_RANGE(0x00c000, 0x00ffff) AM_ROM AM_REGION("c75", 0)
721	720	AM_RANGE(0x200000, 0x27ffff) AM_ROM AM_REGION("c75data", 0)
722	721	ADDRESS_MAP_END
723	722
r32162	r32163
1099	1098	MCFG_CPU_ADD("maincpu", M68EC020, MASTER_CLOCK/2)
1100	1099	MCFG_CPU_PROGRAM_MAP(namconb1_am)
1101	1100
1102		MCFG_CPU_ADD("mcu", M37702, MASTER_CLOCK/3)
	1101	MCFG_CPU_ADD("mcu", NAMCO_C75, MASTER_CLOCK/3)
1103	1102	MCFG_CPU_PROGRAM_MAP(namcoc75_am)
1104	1103	MCFG_CPU_IO_MAP(namcoc75_io)
1105	1104
r32162	r32163
1136	1135	MCFG_CPU_ADD("maincpu", M68EC020, MASTER_CLOCK/2)
1137	1136	MCFG_CPU_PROGRAM_MAP(namconb2_am)
1138	1137
1139		MCFG_CPU_ADD("mcu", M37702, MASTER_CLOCK/3)
	1138	MCFG_CPU_ADD("mcu", NAMCO_C75, MASTER_CLOCK/3)
1140	1139	MCFG_CPU_PROGRAM_MAP(namcoc75_am)
1141	1140	MCFG_CPU_IO_MAP(namcoc75_io)
1142	1141
r32162	r32163
1177	1176	ROM_LOAD32_WORD( "gn2_mprlb.15b", 0x00002, 0x80000, CRC(fe2d9425) SHA1(51b166a629cbb522720d63720558816b496b6b76) )
1178	1177	ROM_LOAD32_WORD( "gn2_mprub.13b", 0x00000, 0x80000, CRC(3bf4985a) SHA1(f559e0d5f55d23d886fe61bd7d5ca556acc7f87c) )
1179	1178
1180		ROM_REGION16_LE( 0x4000, "c75", 0 ) /* C75 program */
1181		ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )
1182
1183	1179	ROM_REGION16_LE( 0x80000, "c75data", 0 ) /* sound data - JP1 jumper selectable between 1Mb (27C1024) or 4Mb (27C4096) either rom is correct */
1184	1180	//  ROM_LOAD( "gn1_spr0.5b", 0, 0x20000, CRC(6836ba38) SHA1(6ea17ea4bbb59be108e8887acd7871409580732f) ) /* 1Megabit, same data as the 4Mb rom at 0x00000-0x1ffff */
1185	1181	ROM_LOAD( "gn1-spr0.5b", 0, 0x80000, CRC(71773811) SHA1(e482784d9b9ebf8c2e4a2a3f6f6c4dc8304d2251) ) /* 4Megabit, same data at 0x00000-0x1ffff, 0x20000-0x7ffff is 0xff filled */
r32162	r32163
1211	1207	ROM_LOAD32_WORD( "gn3_mprlb.15b", 0x00002, 0x80000, CRC(9260fce5) SHA1(064579be1ac90e04082a8b403c6adf35dbb46a7e) )
1212	1208	ROM_LOAD32_WORD( "gn3_mprub.13b", 0x00000, 0x80000, CRC(6c1ac697) SHA1(7b52b5ef8154a5d741ac24673f3e6bbfa246a494) )
1213	1209
1214		ROM_REGION16_LE( 0x4000, "c75", 0 ) /* C75 program */
1215		ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )
1216
1217	1210	ROM_REGION16_LE( 0x80000, "c75data", 0 ) /* sound data - JP1 jumper selectable between 1Mb (27C1024) or 4Mb (27C4096) either rom is correct */
1218	1211	//  ROM_LOAD( "gn1_spr0.5b", 0, 0x20000, CRC(6836ba38) SHA1(6ea17ea4bbb59be108e8887acd7871409580732f) ) /* 1Megabit, same data as the 4Mb rom at 0x00000-0x1ffff */
1219	1212	ROM_LOAD( "gn1-spr0.5b", 0, 0x80000, CRC(71773811) SHA1(e482784d9b9ebf8c2e4a2a3f6f6c4dc8304d2251) ) /* 4Megabit, same data at 0x00000-0x1ffff, 0x20000-0x7ffff is 0xff filled */
r32162	r32163
1245	1238	ROM_LOAD32_WORD( "gn1_mprl.15b", 0x00002, 0x80000, CRC(f99e309e) SHA1(3fe0ddf756e6849f8effc7672456cbe32f65c98a) )
1246	1239	ROM_LOAD32_WORD( "gn1_mpru.13b", 0x00000, 0x80000, CRC(72a4db07) SHA1(8c5e1e51cd961b311d03f7b21f36a5bd5e8e9104) )
1247	1240
1248		ROM_REGION16_LE( 0x4000, "c75", 0 ) /* C75 program */
1249		ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )
1250
1251	1241	ROM_REGION16_LE( 0x80000, "c75data", 0 ) /* sound data - JP1 jumper selectable between 1Mb (27C1024) or 4Mb (27C4096) either rom is correct */
1252	1242	ROM_LOAD( "gn1_spr0.5b", 0, 0x20000, CRC(6836ba38) SHA1(6ea17ea4bbb59be108e8887acd7871409580732f) ) /* 1Megabit, same data as the 4Mb rom at 0x00000-0x1ffff */
1253	1243	//  ROM_LOAD( "gn1-spr0.5b", 0, 0x80000, CRC(71773811) SHA1(e482784d9b9ebf8c2e4a2a3f6f6c4dc8304d2251) ) /* 4Megabit, same data at 0x00000-0x1ffff, 0x20000-0x7ffff is 0xff filled */
r32162	r32163
1279	1269	ROM_LOAD32_WORD( "nr2_mprl.15b", 0x00002, 0x80000, CRC(0431b6d4) SHA1(54c96e8ac9e753956c31bdef79d390f1c20e10ff) )
1280	1270	ROM_LOAD32_WORD( "nr2_mpru.13b", 0x00000, 0x80000, CRC(049b97cb) SHA1(0e344b29a4d4bdc854fa9849589772df2eeb0a05) )
1281	1271
1282		ROM_REGION16_LE( 0x4000, "c75", 0 ) /* C75 program */
1283		ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )
1284
1285	1272	ROM_REGION16_LE( 0x80000, "c75data", 0 ) /* sound data */
1286	1273	ROM_LOAD( "nr1-spr0", 0, 0x20000, CRC(1cc2b44b) SHA1(161f4ed39fabe89d7ee1d539f8b9f08cd0ff3111) )
1287	1274
r32162	r32163
1316	1303	ROM_LOAD32_WORD( "nr1_mprl.15b", 0x00002, 0x80000, CRC(fae5f62c) SHA1(143d716abbc834aac6270db3bbb89ec71ea3804d) )
1317	1304	ROM_LOAD32_WORD( "nr1_mpru.13b", 0x00000, 0x80000, CRC(42ef71f9) SHA1(20e3cb63e1fde293c60c404b378d901d635c4b79) )
1318	1305
1319		ROM_REGION16_LE( 0x4000, "c75", 0 ) /* C75 program */
1320		ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )
1321
1322	1306	ROM_REGION16_LE( 0x80000, "c75data", 0 ) /* sound data */
1323	1307	ROM_LOAD( "nr1-spr0", 0, 0x20000, CRC(1cc2b44b) SHA1(161f4ed39fabe89d7ee1d539f8b9f08cd0ff3111) )
1324	1308
r32162	r32163
1353	1337	ROM_LOAD32_WORD( "gse2mprl.15b", 0x00002, 0x80000, CRC(a514349c) SHA1(1f7ec81cd6193410d2f01e6f0f84878561fc8035) )
1354	1338	ROM_LOAD32_WORD( "gse2mpru.13b", 0x00000, 0x80000, CRC(b6afd238) SHA1(438a3411ac8ce3d22d5da8c0800738cb8d2994a9) )
1355	1339
1356		ROM_REGION16_LE( 0x4000, "c75", 0 ) /* C75 program */
1357		ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )
1358
1359	1340	ROM_REGION16_LE( 0x80000, "c75data", 0 ) /* sound data */
1360	1341	ROM_LOAD( "gse2spr0.bin", 0, 0x20000, CRC(17e87cfc) SHA1(9cbeadb6dfcb736e8c80eab344f70fc2f58469d6) )
1361	1342
r32162	r32163
1381	1362	ROM_LOAD32_WORD( "gs41mprl.15b", 0x00002, 0x80000, CRC(5759bdb5) SHA1(a0fb332c484e168369a69cd9dd8ea72e5f4565df) )
1382	1363	ROM_LOAD32_WORD( "gs41mpru.13b", 0x00000, 0x80000, CRC(78bde1e7) SHA1(911d33897f03c59c6505f5f755d80471ff019812) )
1383	1364
1384		ROM_REGION16_LE( 0x4000, "c75", 0 ) /* C75 program */
1385		ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )
1386
1387	1365	ROM_REGION16_LE( 0x80000, "c75data", 0 ) /* sound data */
1388	1366	ROM_LOAD( "gs41spr0.5b", 0, 0x80000, CRC(3e2b6d55) SHA1(f6a1ecaee3a9a7a535850084e469aa7f873f301e) )
1389	1367
r32162	r32163
1536	1514	ROM_LOAD32_WORD( "gs1mprl.15b", 0x00002, 0x80000, CRC(1e6c3626) SHA1(56abe21884fd87df10996db19c49ce14214d4b73) )
1537	1515	ROM_LOAD32_WORD( "gs1mpru.13b", 0x00000, 0x80000, CRC(ef355179) SHA1(0ab0ef4301a318681bb5827d35734a0732b35484) )
1538	1516
1539		ROM_REGION16_LE( 0x4000, "c75", 0 ) /* C75 program */
1540		ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )
1541
1542	1517	ROM_REGION16_LE( 0x80000, "c75data", 0 ) /* sound data */
1543	1518	ROM_LOAD( "gs1spr0.5b", 0, 0x80000, CRC(561ea20f) SHA1(adac6b77effc3a82079a9b228bafca0fcef72ba5) )
1544	1519
r32162	r32163
1564	1539	ROM_LOAD32_WORD( "ss51mprl.bin", 0x00002, 0x80000, CRC(c9e0107d) SHA1(0f10582416023a86ea1ef2679f3f06016c086e08) )
1565	1540	ROM_LOAD32_WORD( "ss51mpru.bin", 0x00000, 0x80000, CRC(0d93d261) SHA1(5edef26e2c86dbc09727d910af92747d022e4fed) )
1566	1541
1567		ROM_REGION16_LE( 0x4000, "c75", 0 ) /* C75 program */
1568		ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )
1569
1570	1542	ROM_REGION16_LE( 0x80000, "c75data", 0 ) /* sound data */
1571	1543	ROM_LOAD( "ss51spr0.bin", 0, 0x80000, CRC(71cb12f5) SHA1(6e13bd16a5ba14d6e47a21875db3663ada3c06a5) )
1572	1544
r32162	r32163
1593	1565	ROM_LOAD32_WORD( "ss61mprl.bin", 0x00002, 0x80000, CRC(06f55e73) SHA1(6be26f8a2ef600bf07c580f210d7b265ac464002) )
1594	1566	ROM_LOAD32_WORD( "ss61mpru.bin", 0x00000, 0x80000, CRC(0abdbb83) SHA1(67e8b712291f9bcf2c3a52fbc451fad54679cab8) )
1595	1567
1596		ROM_REGION16_LE( 0x4000, "c75", 0 ) /* C75 program */
1597		ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )
1598
1599	1568	ROM_REGION16_LE( 0x80000, "c75data", 0 ) /* sound data */
1600	1569	ROM_LOAD( "ss61spr0.bin", 0, 0x80000, CRC(71cb12f5) SHA1(6e13bd16a5ba14d6e47a21875db3663ada3c06a5) )
1601	1570
r32162	r32163
1621	1590	ROM_LOAD32_WORD( "ss71mprl.bin", 0x00002, 0x80000, CRC(bd60b50e) SHA1(9e00bacd506182ab2af2c0efdd5cc401b3e46485) )
1622	1591	ROM_LOAD32_WORD( "ss71mpru.bin", 0x00000, 0x80000, CRC(3444f5a8) SHA1(8d0f35b3ba8f65dbc67c3b2d273833227a8b8b2a) )
1623	1592
1624		ROM_REGION16_LE( 0x4000, "c75", 0 ) /* C75 program */
1625		ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )
1626
1627	1593	ROM_REGION16_LE( 0x80000, "c75data", 0 ) /* sound data */
1628	1594	ROM_LOAD( "ss71spr0.bin", 0, 0x80000, CRC(71cb12f5) SHA1(6e13bd16a5ba14d6e47a21875db3663ada3c06a5) )
1629	1595
r32162	r32163
1649	1615	ROM_LOAD32_WORD( "vsj1mprl.15b", 0x00002, 0x80000, CRC(83a60d92) SHA1(c3db0c79f772a79418914353a3d6ecc4883ea54e) )
1650	1616	ROM_LOAD32_WORD( "vsj1mpru.13b", 0x00000, 0x80000, CRC(c63eb92d) SHA1(f93bd4b91daee645677955020dc8df14dc9bfd27) )
1651	1617
1652		ROM_REGION16_LE( 0x4000, "c75", 0 ) /* C75 program */
1653		ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )
1654
1655	1618	ROM_REGION16_LE( 0x80000, "c75data", 0 ) /* sound data */
1656	1619	ROM_LOAD( "vsj1spr0.5b", 0, 0x80000, CRC(b0c71aa6) SHA1(a94fae02b46a645ff728d2f98827c85ff155892b) )
1657	1620
r32162	r32163
1837	1800	ROM_LOAD32_WORD( "ou2_mprl.11c", 0x00002, 0x80000, CRC(f414a32e) SHA1(9733ab087cfde1b8fb5b676d8a2eb5325ebdbb56) )
1838	1801	ROM_LOAD32_WORD( "ou2_mpru.11d", 0x00000, 0x80000, CRC(ab5083fb) SHA1(cb2e7a4838c2b80057edb83ea63116bccb1394d3) )
1839	1802
1840		ROM_REGION( 0x4000, "c75", 0 ) /* C75 program */
1841		ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )
1842
1843	1803	ROM_REGION16_LE( 0x80000, "c75data", 0 ) /* sound data */
1844	1804	ROM_LOAD( "ou1spr0.5b", 0, 0x80000, CRC(60cee566) SHA1(2f3b96793816d90011586e0f9f71c58b636b6d4c) )
1845	1805
r32162	r32163
1882	1842	ROM_LOAD32_WORD( "ou1_mprl.11c", 0x00002, 0x80000, CRC(d3b9e530) SHA1(3f5fe5eea817a23dfe42e76f32912ce94d4c49c9) )
1883	1843	ROM_LOAD32_WORD( "ou1_mpru.11d", 0x00000, 0x80000, CRC(d98308fb) SHA1(fdefeebf56464a20e3aaefd88df4eee9f7b5c4f3) )
1884	1844
1885		ROM_REGION( 0x4000, "c75", 0 ) /* C75 program */
1886		ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )
1887
1888	1845	ROM_REGION16_LE( 0x80000, "c75data", 0 ) /* sound data */
1889	1846	ROM_LOAD( "ou1spr0.5b", 0, 0x80000, CRC(60cee566) SHA1(2f3b96793816d90011586e0f9f71c58b636b6d4c) )
1890	1847
r32162	r32163
1928	1885	ROM_LOAD32_WORD( "mb1_mprl.11c", 0x00002, 0x80000, CRC(86cf0644) SHA1(07eeadda1d94c9be2f882edb6f2eb0b98292e500) )
1929	1886	ROM_LOAD32_WORD( "mb1_mpru.11d", 0x00000, 0x80000, CRC(fb1ff916) SHA1(e0ba96c1f26a60f87d8050e582e164d91e132183) )
1930	1887
1931		ROM_REGION( 0x4000, "c75", 0 ) /* C75 program */
1932		ROM_LOAD( "c75.bin", 0, 0x4000, CRC(42f539a5) SHA1(3103e5a0a2867620309fd4fe478a2be0effbeff8) )
1933
1934	1888	ROM_REGION16_LE( 0x80000, "c75data", 0 ) /* sound data */
1935	1889	ROM_LOAD( "mb1_spr0.5b", 0, 0x80000, CRC(d10f6272) SHA1(cb99e06e050dbf86998ea51ef2ca130b2acfb2f6) )
1936	1890

Previous

199869 Revisions

Next

---

© 1997-2024 The MAME Team