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r32145 Wednesday 17th September, 2014 at 05:38:53 UTC by Fabio Priuli

added generic cartslot / ROM socket slot device, which offers basic allocation and access handlers, and converted a few drivers to use this instead of code from cartslot.c [Fabio Priuli] out of whatsnew: the RAM socket part is just a proof of concept, and the natural extension of the line of thought which lead me to this generic socket/cartslot. it might allow to convert current RAM device to be a slot device as well (after some refactorization, of course, since current code lacks many of the necessary features), or be removed soonish, depending on consensus.

[src/emu/bus]	bus.mak
[src/emu/bus/generic]	carts.c* carts.h* ram.c* ram.h* rom.c* rom.h* slot.c* slot.h*
[src/mess]	mess.mak
[src/mess/drivers]	aim65.c gamepock.c pv2000.c rx78.c supracan.c
[src/mess/includes]	aim65.h gamepock.h
[src/mess/machine]	aim65.c gamepock.c

trunk/src/emu/bus/generic/carts.h

r0	r32145
	1	/**********************************************************************
	2
	3	Generic ROM/RAM socket slots
	4
	5	**********************************************************************/
	6
	7	#pragma once
	8
	9	#ifndef __GENERIC_CARTS_H__
	10	#define __GENERIC_CARTS_H__
	11
	12	#include "emu.h"
	13
	14	#include "rom.h"
	15	#include "ram.h"
	16
	17
	18	SLOT_INTERFACE_EXTERN( generic_plain_slot );
	19	SLOT_INTERFACE_EXTERN( generic_linear_slot );
	20
	21	#endif

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trunk/src/emu/bus/generic/slot.c

r0	r32145
	1	/***********************************************************************************************************
	2
	3	Generic ROM / RAM Socket and Cartslot device
	4
	5	This device offers basic RAM / ROM allocation and access
	6
	7	***********************************************************************************************************/
	8
	9
	10	#include "emu.h"
	11	#include "slot.h"
	12
	13	//**************************************************************************
	14	//  GLOBAL VARIABLES
	15	//**************************************************************************
	16
	17	const device_type GENERIC_SOCKET = &device_creator<generic_slot_device>;
	18
	19
	20	//-------------------------------------------------
	21	//  device_generic_cart_interface - constructor
	22	//-------------------------------------------------
	23
	24	device_generic_cart_interface::device_generic_cart_interface(const machine_config &mconfig, device_t &device)
	25	: device_slot_card_interface(mconfig, device),
	26	m_rom(NULL),
	27	m_rom_size(0)
	28	{
	29	}
	30
	31
	32	//-------------------------------------------------
	33	//  ~device_generic_cart_interface - destructor
	34	//-------------------------------------------------
	35
	36	device_generic_cart_interface::~device_generic_cart_interface()
	37	{
	38	}
	39
	40	//-------------------------------------------------
	41	//  rom_alloc - alloc the space for the cart
	42	//-------------------------------------------------
	43
	44	void device_generic_cart_interface::rom_alloc(size_t size, int width, const char *tag)
	45	{
	46	if (m_rom == NULL)
	47	{
	48	astring tempstring(tag);
	49	tempstring.cat(":cart:rom");
	50	m_rom = device().machine().memory().region_alloc(tempstring, size, width, ENDIANNESS_LITTLE)->base();
	51	m_rom_size = size;
	52	}
	53	}
	54
	55
	56	//-------------------------------------------------
	57	//  ram_alloc - alloc the space for the ram
	58	//-------------------------------------------------
	59
	60	void device_generic_cart_interface::ram_alloc(UINT32 size)
	61	{
	62	if (m_ram == NULL)
	63	{
	64	m_ram.resize(size);
	65	device().save_item(NAME(m_ram));
	66	}
	67	}
	68
	69
	70
	71	//**************************************************************************
	72	//  LIVE DEVICE
	73	//**************************************************************************
	74
	75	//-------------------------------------------------
	76	//  generic_slot_device - constructor
	77	//-------------------------------------------------
	78	generic_slot_device::generic_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
	79	device_t(mconfig, GENERIC_SOCKET, "Generic ROM Socket / RAM Socket / Cartridge Slot", tag, owner, clock, "generic_socket", __FILE__),
	80	device_image_interface(mconfig, *this),
	81	device_slot_interface(mconfig, *this),
	82	m_interface(NULL),
	83	m_default_card("rom"),
	84	m_extensions("bin"),
	85	m_must_be_loaded(FALSE),
	86	m_width(GENERIC_ROM8_WIDTH),
	87	m_empty(TRUE)
	88	{
	89	}
	90
	91
	92	//-------------------------------------------------
	93	//  generic_slot_device - destructor
	94	//-------------------------------------------------
	95
	96	generic_slot_device::~generic_slot_device()
	97	{
	98	}
	99
	100	//-------------------------------------------------
	101	//  device_start - device-specific startup
	102	//-------------------------------------------------
	103
	104	void generic_slot_device::device_start()
	105	{
	106	m_cart = dynamic_cast<device_generic_cart_interface *>(get_card_device());
	107	}
	108
	109	//-------------------------------------------------
	110	//  device_config_complete - perform any
	111	//  operations now that the configuration is
	112	//  complete
	113	//-------------------------------------------------
	114
	115	void generic_slot_device::device_config_complete()
	116	{
	117	// set brief and instance name
	118	update_names();
	119	}
	120
	121
	122	/*-------------------------------------------------
	123	call load
	124	-------------------------------------------------*/
	125
	126	bool generic_slot_device::call_load()
	127	{
	128	if (m_cart)
	129	{
	130	if (!m_device_image_load.isnull())
	131	{
	132	int result = m_device_image_load(*this);
	133	m_empty = (result == IMAGE_INIT_PASS) ? FALSE : TRUE;
	134	return result;
	135	}
	136	else
	137	{
	138	UINT32 len = (software_entry() == NULL) ? length() : get_software_region_length("rom");
	139	UINT8 *ROM;
	140
	141	rom_alloc(len, m_width);
	142	ROM = get_rom_base();
	143
	144	if (software_entry() == NULL)
	145	fread(ROM, len);
	146	else
	147	memcpy(ROM, get_software_region("rom"), len);
	148
	149	m_empty = FALSE;
	150
	151	return IMAGE_INIT_PASS;
	152	}
	153	}
	154
	155	return IMAGE_INIT_PASS;
	156	}
	157
	158
	159	/*-------------------------------------------------
	160	call_unload
	161	-------------------------------------------------*/
	162
	163	void generic_slot_device::call_unload()
	164	{
	165	if (!m_device_image_unload.isnull())
	166	return m_device_image_unload(*this);
	167	}
	168
	169
	170	/*-------------------------------------------------
	171	call softlist load
	172	-------------------------------------------------*/
	173
	174	bool generic_slot_device::call_softlist_load(software_list_device &swlist, const char *swname, const rom_entry *start_entry)
	175	{
	176	load_software_part_region(*this, swlist, swname, start_entry);
	177	return TRUE;
	178	}
	179
	180
	181
	182	/*-------------------------------------------------
	183	get default card software
	184	-------------------------------------------------*/
	185
	186	void generic_slot_device::get_default_card_software(astring &result)
	187	{
	188	software_get_default_slot(result, m_default_card);
	189	}
	190
	191	/*-------------------------------------------------
	192	read_rom
	193	-------------------------------------------------*/
	194
	195	READ8_MEMBER(generic_slot_device::read_rom)
	196	{
	197	if (m_cart)
	198	return m_cart->read_rom(space, offset);
	199	else
	200	return 0xff;
	201	}
	202
	203	/*-------------------------------------------------
	204	read16_rom
	205	-------------------------------------------------*/
	206
	207	READ16_MEMBER(generic_slot_device::read16_rom)
	208	{
	209	if (m_cart)
	210	return m_cart->read16_rom(space, offset, mem_mask);
	211	else
	212	return 0xffff;
	213	}
	214
	215	/*-------------------------------------------------
	216	read_ram
	217	-------------------------------------------------*/
	218
	219	READ8_MEMBER(generic_slot_device::read_ram)
	220	{
	221	if (m_cart)
	222	return m_cart->read_ram(space, offset);
	223	else
	224	return 0xff;
	225	}
	226
	227	/*-------------------------------------------------
	228	write
	229	-------------------------------------------------*/
	230
	231	WRITE8_MEMBER(generic_slot_device::write_ram)
	232	{
	233	if (m_cart)
	234	m_cart->write_ram(space, offset, data);
	235	}
	236

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trunk/src/emu/bus/generic/rom.h

r0	r32145
	1	#ifndef __GENERIC_ROM_H
	2	#define __GENERIC_ROM_H
	3
	4	#include "slot.h"
	5
	6
	7	// ======================> generic_rom_device
	8
	9	class generic_rom_device : public device_t,
	10	public device_generic_cart_interface
	11	{
	12	public:
	13	// construction/destruction
	14	generic_rom_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
	15
	16	// device-level overrides
	17	virtual void device_start() {}
	18	};
	19
	20
	21	// ======================> generic_rom_plain_device
	22
	23	class generic_rom_plain_device : public generic_rom_device
	24	{
	25	public:
	26	// construction/destruction
	27	generic_rom_plain_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	28
	29	// reading and writing
	30	virtual DECLARE_READ8_MEMBER(read_rom);
	31	virtual DECLARE_READ16_MEMBER(read16_rom);
	32	};
	33
	34
	35	// ======================> generic_rom_linear_device
	36
	37	class generic_rom_linear_device : public generic_rom_device
	38	{
	39	public:
	40	// construction/destruction
	41	generic_rom_linear_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	42
	43	// reading and writing
	44	virtual DECLARE_READ8_MEMBER(read_rom);
	45	virtual DECLARE_READ16_MEMBER(read16_rom);
	46	};
	47
	48
	49
	50	// device type definition
	51	extern const device_type GENERIC_ROM_PLAIN;
	52	extern const device_type GENERIC_ROM_LINEAR;
	53
	54
	55
	56	#endif

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trunk/src/emu/bus/generic/ram.h

r0	r32145
	1	#ifndef __GENERIC_RAM_H
	2	#define __GENERIC_RAM_H
	3
	4	#include "slot.h"
	5
	6
	7	// ======================> generic_ram_plain_device
	8
	9	class generic_ram_plain_device : public device_t,
	10	public device_generic_cart_interface
	11	{
	12	public:
	13	// construction/destruction
	14	generic_ram_plain_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 size, const char *shortname, const char *source);
	15
	16	// device-level overrides
	17	virtual void device_start();
	18
	19	// reading and writing
	20	virtual DECLARE_READ8_MEMBER(read_ram);
	21	virtual DECLARE_WRITE8_MEMBER(write_ram);
	22
	23	private:
	24	UINT32 m_size;
	25	};
	26
	27
	28	// ======================> generic_ram_linear_device
	29
	30	class generic_ram_linear_device : public device_t,
	31	public device_generic_cart_interface
	32	{
	33	public:
	34	// construction/destruction
	35	generic_ram_linear_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 size, const char *shortname, const char *source);
	36
	37	// device-level overrides
	38	virtual void device_start();
	39
	40	// reading and writing
	41	virtual DECLARE_READ8_MEMBER(read_ram);
	42	virtual DECLARE_WRITE8_MEMBER(write_ram);
	43
	44	private:
	45	UINT32 m_size;
	46	};
	47
	48
	49	// ======================> generic_ram_*k_plain_device
	50
	51	class generic_ram_32k_plain_device : public generic_ram_plain_device
	52	{
	53	public:
	54	// construction/destruction
	55	generic_ram_32k_plain_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	56	};
	57
	58	class generic_ram_64k_plain_device : public generic_ram_plain_device
	59	{
	60	public:
	61	// construction/destruction
	62	generic_ram_64k_plain_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	63	};
	64
	65	class generic_ram_128k_plain_device : public generic_ram_plain_device
	66	{
	67	public:
	68	// construction/destruction
	69	generic_ram_128k_plain_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	70	};
	71
	72
	73	// ======================> generic_ram_*k_linear_device
	74
	75	class generic_ram_32k_linear_device : public generic_ram_linear_device
	76	{
	77	public:
	78	// construction/destruction
	79	generic_ram_32k_linear_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	80	};
	81
	82	class generic_ram_64k_linear_device : public generic_ram_linear_device
	83	{
	84	public:
	85	// construction/destruction
	86	generic_ram_64k_linear_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	87	};
	88
	89	class generic_ram_128k_linear_device : public generic_ram_linear_device
	90	{
	91	public:
	92	// construction/destruction
	93	generic_ram_128k_linear_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	94	};
	95
	96
	97
	98	// device type definition
	99	extern const device_type GENERIC_RAM_32K_PLAIN;
	100	extern const device_type GENERIC_RAM_64K_PLAIN;
	101	extern const device_type GENERIC_RAM_128K_PLAIN;
	102	extern const device_type GENERIC_RAM_32K_LINEAR;
	103	extern const device_type GENERIC_RAM_64K_LINEAR;
	104	extern const device_type GENERIC_RAM_128K_LINEAR;
	105
	106
	107	#endif

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trunk/src/emu/bus/generic/slot.h

r0	r32145
	1	#ifndef __GENERIC_SLOT_H
	2	#define __GENERIC_SLOT_H
	3
	4	/***************************************************************************
	5	TYPE DEFINITIONS
	6	***************************************************************************/
	7
	8
	9	// ======================> device_generic_cart_interface
	10
	11	class device_generic_cart_interface : public device_slot_card_interface
	12	{
	13	public:
	14	// construction/destruction
	15	device_generic_cart_interface(const machine_config &mconfig, device_t &device);
	16	virtual ~device_generic_cart_interface();
	17
	18	// reading and writing
	19	virtual DECLARE_READ8_MEMBER(read_rom) { return 0xff; }
	20	virtual DECLARE_READ16_MEMBER(read16_rom) { return 0xffff; }
	21
	22	virtual DECLARE_READ8_MEMBER(read_ram) { return 0xff; }
	23	virtual DECLARE_WRITE8_MEMBER(write_ram) {};
	24
	25	virtual void rom_alloc(size_t size, int width, const char *tag);
	26	virtual void ram_alloc(UINT32 size);
	27
	28	UINT8* get_rom_base()  { return m_rom; }
	29	UINT32 get_rom_size() { return m_rom_size; }
	30
	31	UINT8* get_ram_base() { return m_ram; }
	32	UINT32 get_ram_size() { return m_ram.count(); }
	33
	34	// internal state
	35	UINT8  *m_rom;
	36	UINT32  m_rom_size;
	37	dynamic_buffer m_ram;
	38	};
	39
	40
	41	enum
	42	{
	43	GENERIC_ROM8_WIDTH = 1,
	44	GENERIC_ROM16_WIDTH
	45	};
	46
	47
	48	#define MCFG_GENERIC_MANDATORY       \
	49	static_cast<generic_slot_device *>(device)->set_must_be_loaded(TRUE);
	50
	51	#define MCFG_GENERIC_WIDTH(_width)       \
	52	static_cast<generic_slot_device *>(device)->set_width(_width);
	53
	54	#define MCFG_GENERIC_DEFAULT_CARD(_def_card)      \
	55	static_cast<generic_slot_device *>(device)->set_default_card(_def_card);
	56
	57	#define MCFG_GENERIC_INTERFACE(_intf)       \
	58	static_cast<generic_slot_device *>(device)->set_interface(_intf);
	59
	60	#define MCFG_GENERIC_EXTENSIONS(_ext)       \
	61	static_cast<generic_slot_device *>(device)->set_extensions(_ext);
	62
	63	#define MCFG_GENERIC_LOAD(_class, _method)                                \
	64	generic_slot_device::static_set_device_load(*device, device_image_load_delegate(&DEVICE_IMAGE_LOAD_NAME(_class,_method), #_class "::device_image_load_" #_method, downcast<_class *>(owner)));
	65
	66	#define MCFG_GENERIC_UNLOAD(_class, _method)                            \
	67	generic_slot_device::static_set_device_unload(*device, device_image_func_delegate(&DEVICE_IMAGE_UNLOAD_NAME(_class,_method), #_class "::device_image_unload_" #_method, downcast<_class *>(owner)));
	68
	69
	70
	71	typedef device_delegate<void (int layer, int bank, int *code, int *color, int *flags)> generic_load_delegate;
	72
	73
	74	// ======================> generic_slot_device
	75
	76	class generic_slot_device : public device_t,
	77	public device_image_interface,
	78	public device_slot_interface
	79	{
	80	public:
	81	// construction/destruction
	82	generic_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	83	virtual ~generic_slot_device();
	84
	85	static void static_set_device_load(device_t &device, device_image_load_delegate callback) { downcast<generic_slot_device &>(device).m_device_image_load = callback; }
	86	static void static_set_device_unload(device_t &device, device_image_func_delegate callback) { downcast<generic_slot_device &>(device).m_device_image_unload = callback; }
	87
	88	void set_interface(const char * interface) { m_interface = interface; }
	89	void set_default_card(const char * def) { m_default_card = def; }
	90	void set_extensions(const char * exts) { m_extensions = exts; }
	91	void set_must_be_loaded(bool mandatory) { m_must_be_loaded = mandatory; }
	92	void set_width(int width) { m_width = width; }
	93
	94	// device-level overrides
	95	virtual void device_start();
	96	virtual void device_config_complete();
	97
	98	// image-level overrides
	99	virtual bool call_load();
	100	virtual void call_unload();
	101	virtual bool call_softlist_load(software_list_device &swlist, const char *swname, const rom_entry *start_entry);
	102
	103	bool cart_mounted() { return !m_empty; }
	104
	105	virtual iodevice_t image_type() const { return IO_CARTSLOT; }
	106	virtual bool is_readable()  const { return 1; }
	107	virtual bool is_writeable() const { return 0; }
	108	virtual bool is_creatable() const { return 0; }
	109	virtual bool must_be_loaded() const { return m_must_be_loaded; }
	110	virtual bool is_reset_on_load() const { return 1; }
	111	virtual const option_guide *create_option_guide() const { return NULL; }
	112	virtual const char *image_interface() const { return m_interface; }
	113	virtual const char *file_extensions() const { return m_extensions; }
	114
	115	// slot interface overrides
	116	virtual void get_default_card_software(astring &result);
	117
	118	// reading and writing
	119	virtual DECLARE_READ8_MEMBER(read_rom);
	120	virtual DECLARE_READ16_MEMBER(read16_rom);
	121
	122	virtual DECLARE_READ8_MEMBER(read_ram);
	123	virtual DECLARE_WRITE8_MEMBER(write_ram);
	124
	125	virtual void rom_alloc(size_t size, int width) { if (m_cart) m_cart->rom_alloc(size, width, tag()); }
	126	virtual void ram_alloc(UINT32 size)  { if (m_cart) m_cart->ram_alloc(size); }
	127
	128	UINT8* get_rom_base()  { if (m_cart) return m_cart->get_rom_base(); return NULL; }
	129	UINT8* get_ram_base() { if (m_cart) return m_cart->get_ram_base(); return NULL; }
	130
	131	protected:
	132
	133	const char *m_interface;
	134	const char *m_default_card;
	135	const char *m_extensions;
	136	bool        m_must_be_loaded;
	137	int         m_width;
	138	bool        m_empty;
	139	device_generic_cart_interface  *m_cart;
	140	device_image_load_delegate      m_device_image_load;
	141	device_image_func_delegate      m_device_image_unload;
	142	};
	143
	144
	145	// device type definition
	146	extern const device_type GENERIC_SOCKET;
	147
	148
	149	/***************************************************************************
	150	DEVICE CONFIGURATION MACROS
	151	***************************************************************************/
	152
	153	#define MCFG_GENERIC_CARTSLOT_ADD(_tag, _width, _slot_intf, _dev_intf) \
	154	MCFG_DEVICE_ADD(_tag, GENERIC_SOCKET, 0) \
	155	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, NULL, false) \
	156	MCFG_GENERIC_INTERFACE(_dev_intf) \
	157	MCFG_GENERIC_WIDTH(_width)
	158
	159	#define MCFG_GENERIC_SOCKET_ADD(_tag, _width, _slot_intf, _dev_intf) \
	160	MCFG_DEVICE_ADD(_tag, GENERIC_SOCKET, 0) \
	161	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, NULL, false) \
	162	MCFG_GENERIC_INTERFACE(_dev_intf) \
	163	MCFG_GENERIC_WIDTH(_width)
	164
	165	#endif

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trunk/src/emu/bus/generic/carts.c

r0	r32145
	1	/**********************************************************************
	2
	3	Generic ROM / RAM socket slots
	4
	5	**********************************************************************/
	6
	7
	8	#include "carts.h"
	9
	10	SLOT_INTERFACE_START(generic_plain_slot)
	11	SLOT_INTERFACE_INTERNAL("rom", GENERIC_ROM_PLAIN)
	12	SLOT_INTERFACE_END
	13
	14	SLOT_INTERFACE_START(generic_linear_slot)
	15	SLOT_INTERFACE_INTERNAL("rom", GENERIC_ROM_LINEAR)
	16	SLOT_INTERFACE_END

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trunk/src/emu/bus/generic/rom.c

r0	r32145
	1	/***********************************************************************************************************
	2
	3
	4	Generic ROM emulation (for carts and ROM sockets)
	5
	6	This offers generic access to a ROM
	7
	8	generic_rom_plain  : returns 0xff when the system reads beyond the end of the ROM
	9	generic_rom_linear : maps linearly the ROM in the accessed area (i.e., read offset is masked with (ROM size - 1) )
	10
	11	TODO:
	12	- possibly support linear mapping when non-power of 2 ROMs are mapped
	13	- add support for 32bit ROM access
	14
	15	***********************************************************************************************************/
	16
	17
	18	#include "emu.h"
	19	#include "rom.h"
	20
	21	//-------------------------------------------------
	22	//  constructor
	23	//-------------------------------------------------
	24
	25	const device_type GENERIC_ROM_PLAIN  = &device_creator<generic_rom_plain_device>;
	26	const device_type GENERIC_ROM_LINEAR = &device_creator<generic_rom_linear_device>;
	27
	28
	29	generic_rom_device::generic_rom_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
	30	: device_t(mconfig, type, name, tag, owner, clock, shortname, source),
	31	device_generic_cart_interface(mconfig, *this)
	32	{
	33	}
	34
	35	generic_rom_plain_device::generic_rom_plain_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	36	: generic_rom_device(mconfig, GENERIC_ROM_PLAIN, "Generic ROM (plain mapping)", tag, owner, clock, "generic_rom_plain", __FILE__)
	37	{
	38	}
	39
	40	generic_rom_linear_device::generic_rom_linear_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	41	: generic_rom_device(mconfig, GENERIC_ROM_LINEAR, "Generic ROM (linear mapping)", tag, owner, clock, "generic_rom_linear", __FILE__)
	42	{
	43	}
	44
	45
	46	/*-------------------------------------------------
	47	mapper specific handlers
	48	-------------------------------------------------*/
	49
	50	READ8_MEMBER(generic_rom_plain_device::read_rom)
	51	{
	52	if (offset < m_rom_size)
	53	return m_rom[offset];
	54	else
	55	return 0xff;
	56	}
	57
	58	READ16_MEMBER(generic_rom_plain_device::read16_rom)
	59	{
	60	UINT16 *ROM = (UINT16 *)m_rom;
	61	if (offset < m_rom_size/2)
	62	return ROM[offset];
	63	else
	64	return 0xffff;
	65	}
	66
	67
	68	READ8_MEMBER(generic_rom_linear_device::read_rom)
	69	{
	70	return m_rom[offset % m_rom_size];
	71	}
	72
	73	READ16_MEMBER(generic_rom_linear_device::read16_rom)
	74	{
	75	UINT16 *ROM = (UINT16 *)m_rom;
	76	return ROM[offset % (m_rom_size/2)];
	77	}
	78

Property changes on: trunk/src/emu/bus/generic/rom.c

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/emu/bus/generic/ram.c

r0	r32145
	1	/***********************************************************************************************************
	2
	3
	4	Generic RAM socket emulation
	5
	6	This offers generic access to RAM
	7
	8	generic_ram_plain  : returns 0xff when the system reads beyond the end of the RAM
	9	generic_ram_linear : maps linearly the RAM in the accessed area (i.e., read/write offset is masked with
	10	(RAM size - 1) )
	11
	12	TODO:
	13	- support variable RAM size
	14	- possibly support linear mapping when non-power of 2 RAMs are mapped
	15	- add support for 16bit & 32bit RAM access
	16
	17	***********************************************************************************************************/
	18
	19
	20	#include "emu.h"
	21	#include "ram.h"
	22
	23	//-------------------------------------------------
	24	//  constructor
	25	//-------------------------------------------------
	26
	27	const device_type GENERIC_RAM_32K_PLAIN = &device_creator<generic_ram_32k_plain_device>;
	28	const device_type GENERIC_RAM_64K_PLAIN = &device_creator<generic_ram_64k_plain_device>;
	29	const device_type GENERIC_RAM_128K_PLAIN = &device_creator<generic_ram_128k_plain_device>;
	30	const device_type GENERIC_RAM_32K_LINEAR = &device_creator<generic_ram_32k_linear_device>;
	31	const device_type GENERIC_RAM_64K_LINEAR = &device_creator<generic_ram_64k_linear_device>;
	32	const device_type GENERIC_RAM_128K_LINEAR = &device_creator<generic_ram_128k_linear_device>;
	33
	34
	35	generic_ram_plain_device::generic_ram_plain_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 size, const char *shortname, const char *source)
	36	: device_t(mconfig, type, name, tag, owner, clock, shortname, source),
	37	device_generic_cart_interface(mconfig, *this),
	38	m_size(size)
	39	{
	40	}
	41
	42	generic_ram_linear_device::generic_ram_linear_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 size, const char *shortname, const char *source)
	43	: device_t(mconfig, type, name, tag, owner, clock, shortname, source),
	44	device_generic_cart_interface(mconfig, *this),
	45	m_size(size)
	46	{
	47	}
	48
	49
	50	generic_ram_32k_plain_device::generic_ram_32k_plain_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	51	: generic_ram_plain_device(mconfig, GENERIC_RAM_32K_PLAIN, "Generic RAM 32K (plain mapping)", tag, owner, clock, 0x8000, "generic_ram32p", __FILE__)
	52	{
	53	}
	54
	55	generic_ram_64k_plain_device::generic_ram_64k_plain_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	56	: generic_ram_plain_device(mconfig, GENERIC_RAM_64K_PLAIN, "Generic RAM 64K (plain mapping)", tag, owner, clock, 0x10000, "generic_ram64p", __FILE__)
	57	{
	58	}
	59
	60	generic_ram_128k_plain_device::generic_ram_128k_plain_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	61	: generic_ram_plain_device(mconfig, GENERIC_RAM_128K_PLAIN, "Generic RAM 128K (plain mapping)", tag, owner, clock, 0x20000, "generic_ram128p", __FILE__)
	62	{
	63	}
	64
	65	generic_ram_32k_linear_device::generic_ram_32k_linear_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	66	: generic_ram_linear_device(mconfig, GENERIC_RAM_32K_LINEAR, "Generic RAM 32K (linear mapping)", tag, owner, clock, 0x8000, "generic_ram32l", __FILE__)
	67	{
	68	}
	69
	70	generic_ram_64k_linear_device::generic_ram_64k_linear_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	71	: generic_ram_linear_device(mconfig, GENERIC_RAM_64K_LINEAR, "Generic RAM 64K (linear mapping)", tag, owner, clock, 0x10000, "generic_ram64l", __FILE__)
	72	{
	73	}
	74
	75	generic_ram_128k_linear_device::generic_ram_128k_linear_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	76	: generic_ram_linear_device(mconfig, GENERIC_RAM_128K_LINEAR, "Generic RAM 128K (linear mapping)", tag, owner, clock, 0x20000, "generic_ram128l", __FILE__)
	77	{
	78	}
	79
	80
	81	void generic_ram_plain_device::device_start()
	82	{
	83	m_ram.resize(m_size);
	84	save_item(NAME(m_ram));
	85	}
	86
	87	void generic_ram_linear_device::device_start()
	88	{
	89	m_ram.resize(m_size);
	90	save_item(NAME(m_ram));
	91	}
	92
	93
	94	/*-------------------------------------------------
	95	mapper specific handlers
	96	-------------------------------------------------*/
	97
	98	READ8_MEMBER(generic_ram_plain_device::read_ram)
	99	{
	100	if (offset < m_ram.bytes())
	101	return m_ram[offset];
	102	else
	103	return 0xff;
	104	}
	105
	106	WRITE8_MEMBER(generic_ram_plain_device::write_ram)
	107	{
	108	if (offset < m_ram.bytes())
	109	m_ram[offset] = data;
	110	}
	111
	112
	113	READ8_MEMBER(generic_ram_linear_device::read_ram)
	114	{
	115	return m_ram[offset % m_ram.bytes()];
	116	}
	117
	118	WRITE8_MEMBER(generic_ram_linear_device::write_ram)
	119	{
	120	m_ram[offset % m_ram.bytes()] = data;
	121	}
	122

Property changes on: trunk/src/emu/bus/generic/ram.c

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/emu/bus/bus.mak

r32144	r32145
313	313
314	314	#-------------------------------------------------
315	315	#
	316	#@src/emu/bus/generic/slot.h,BUSES += GENERIC
	317	#-------------------------------------------------
	318
	319	ifneq ($(filter GENERIC,$(BUSES)),)
	320	OBJDIRS += $(BUSOBJ)/generic
	321	BUSOBJS += $(BUSOBJ)/generic/slot.o
	322	BUSOBJS += $(BUSOBJ)/generic/carts.o
	323	BUSOBJS += $(BUSOBJ)/generic/ram.o
	324	BUSOBJS += $(BUSOBJ)/generic/rom.o
	325	endif
	326
	327
	328	#-------------------------------------------------
	329	#
316	330	#@src/emu/bus/ieee488/ieee488.h,BUSES += IEEE488
317	331	#-------------------------------------------------
318	332

trunk/src/mess/machine/aim65.c

r32144	r32145
142	142	ram_device *ram = m_ram;
143	143	address_space &space = m_maincpu->space(AS_PROGRAM);
144	144
145		/* Init RAM */
	145	// Init ROM sockets
	146	if (m_z24->cart_mounted())
	147	space.install_read_handler(0xd000, 0xdfff, read8_delegate(FUNC(generic_slot_device::read_rom),(generic_slot_device*)m_z24));
	148	if (m_z25->cart_mounted())
	149	space.install_read_handler(0xc000, 0xcfff, read8_delegate(FUNC(generic_slot_device::read_rom),(generic_slot_device*)m_z25));
	150	if (m_z26->cart_mounted())
	151	space.install_read_handler(0xb000, 0xbfff, read8_delegate(FUNC(generic_slot_device::read_rom),(generic_slot_device*)m_z26));
	152
	153	// Init RAM
146	154	space.install_ram(0x0000, ram->size() - 1, ram->pointer());
147	155
148	156	m_pb_save = 0;

trunk/src/mess/machine/gamepock.c

r32144	r32145
136	136	hd44102ch_init( 0 );
137	137	hd44102ch_init( 1 );
138	138	hd44102ch_init( 2 );
	139
	140	if (m_cart->cart_mounted())
	141	m_maincpu->space(AS_PROGRAM).install_read_handler(0x4000,0xbfff, read8_delegate(FUNC(generic_slot_device::read_rom),(generic_slot_device*)m_cart));
	142
139	143	}
140	144
141	145	UINT32 gamepock_state::screen_update_gamepock(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)

trunk/src/mess/includes/aim65.h

r32144	r32145
16	16	#include "machine/6532riot.h"
17	17	#include "machine/6821pia.h"
18	18	#include "machine/ram.h"
19		#include "imagedev/cartslot.h"
20	19	#include "imagedev/cassette.h"
21	20	#include "sound/wave.h"
	21	#include "bus/generic/slot.h"
	22	#include "bus/generic/carts.h"
22	23
23	24
24	25	/** R6502 Clock.
r32144	r32145
38	39	m_maincpu(*this, "maincpu"),
39	40	m_cassette1(*this, "cassette"),
40	41	m_cassette2(*this, "cassette2"),
	42	m_z24(*this, "z24"),
	43	m_z25(*this, "z25"),
	44	m_z26(*this, "z26"),
41	45	m_ram(*this, RAM_TAG),
42	46	m_ds1(*this, "ds1"),
43	47	m_ds2(*this, "ds2"),
r32144	r32145
62	66	required_device<cpu_device> m_maincpu;
63	67	required_device<cassette_image_device> m_cassette1;
64	68	required_device<cassette_image_device> m_cassette2;
	69	required_device<generic_slot_device> m_z24;
	70	required_device<generic_slot_device> m_z25;
	71	required_device<generic_slot_device> m_z26;
65	72	required_device<ram_device> m_ram;
66	73	required_device<dl1416_device> m_ds1;
67	74	required_device<dl1416_device> m_ds2;
r32144	r32145
80	87
81	88	void dl1416_update(dl1416_device *device, int index);
82	89
83		DECLARE_DEVICE_IMAGE_LOAD_MEMBER(aim65_cart);
	90	int load_cart(device_image_interface &image, generic_slot_device *slot, const char *slot_tag);
	91	DECLARE_DEVICE_IMAGE_LOAD_MEMBER(z24_load) { return load_cart(image, m_z24, "z24"); }
	92	DECLARE_DEVICE_IMAGE_LOAD_MEMBER(z25_load) { return load_cart(image, m_z25, "z25"); }
	93	DECLARE_DEVICE_IMAGE_LOAD_MEMBER(z26_load) { return load_cart(image, m_z26, "z26"); }
84	94	};
85	95
86	96

trunk/src/mess/includes/gamepock.h

r32144	r32145
1	1	#ifndef _GAMEPOCK_H_
2	2	#define _GAMEPOCK_H_
3	3	#include "sound/speaker.h"
	4	#include "bus/generic/slot.h"
4	5
5	6	struct HD44102CH {
6	7	UINT8   enabled;
r32144	r32145
16	17	gamepock_state(const machine_config &mconfig, device_type type, const char *tag)
17	18	: driver_device(mconfig, type, tag),
18	19	m_maincpu(*this, "maincpu"),
19		m_speaker(*this, "speaker") { }
	20	m_speaker(*this, "speaker"),
	21	m_cart(*this, "cartslot")
	22	{ }
20	23
21	24	virtual void machine_reset();
22	25
r32144	r32145
33	36	DECLARE_WRITE8_MEMBER( port_b_w );
34	37	DECLARE_READ8_MEMBER( port_c_r );
35	38	UINT32 screen_update_gamepock(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
36		DECLARE_DEVICE_IMAGE_LOAD_MEMBER(gamepock_cart);
37	39	required_device<cpu_device> m_maincpu;
38	40	required_device<speaker_sound_device> m_speaker;
	41	required_device<generic_slot_device> m_cart;
39	42	DECLARE_WRITE_LINE_MEMBER(gamepock_to_w);
40
41	43	};
42	44
43	45	#endif

trunk/src/mess/drivers/rx78.c

r32144	r32145
43	43	#include "emu.h"
44	44	#include "cpu/z80/z80.h"
45	45	#include "sound/sn76496.h"
46		#include "imagedev/cartslot.h"
47	46	#include "imagedev/cassette.h"
48	47	#include "sound/wave.h"
49	48	#include "machine/ram.h"
	49	#include "bus/generic/slot.h"
	50	#include "bus/generic/carts.h"
50	51
51	52
52	53	class rx78_state : public driver_device
r32144	r32145
56	57	: driver_device(mconfig, type, tag),
57	58	m_maincpu(*this, "maincpu"),
58	59	m_cass(*this, "cassette"),
	60	m_cart(*this, "cartslot"),
59	61	m_ram(*this, RAM_TAG),
60	62	m_palette(*this, "palette")
61	63	{ }
r32144	r32145
82	84	DECLARE_DRIVER_INIT(rx78);
83	85	required_device<cpu_device> m_maincpu;
84	86	required_device<cassette_image_device> m_cass;
	87	required_device<generic_slot_device> m_cart;
85	88	required_device<ram_device> m_ram;
86	89	required_device<palette_device> m_palette;
87	90	DECLARE_DEVICE_IMAGE_LOAD_MEMBER( rx78_cart );
r32144	r32145
256	259	static ADDRESS_MAP_START(rx78_mem, AS_PROGRAM, 8, rx78_state)
257	260	ADDRESS_MAP_UNMAP_HIGH
258	261	AM_RANGE(0x0000, 0x1fff) AM_ROM
259		AM_RANGE(0x2000, 0x5fff) AM_ROM AM_REGION("cart_img", 0x0000)
	262	//AM_RANGE(0x2000, 0x5fff)      // mapped by the cartslot
260	263	AM_RANGE(0x6000, 0xafff) AM_RAM //ext RAM
261	264	AM_RANGE(0xb000, 0xebff) AM_RAM
262	265	AM_RANGE(0xec00, 0xffff) AM_READWRITE(rx78_vram_r, rx78_vram_w)
r32144	r32145
406	409
407	410	void rx78_state::machine_reset()
408	411	{
	412	address_space &prg = m_maincpu->space(AS_PROGRAM);
	413	if (m_cart->cart_mounted())
	414	prg.install_read_handler(0x2000, 0x5fff, read8_delegate(FUNC(generic_slot_device::read_rom),(generic_slot_device*)m_cart));
409	415	}
410	416
411	417	DEVICE_IMAGE_LOAD_MEMBER( rx78_state, rx78_cart )
412	418	{
413		UINT8 *cart = memregion("cart_img")->base();
	419	UINT8 *cart;
414	420	UINT32 size;
415	421
416	422	if (image.software_entry() == NULL)
r32144	r32145
423	429	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
424	430	return IMAGE_INIT_FAIL;
425	431	}
426
	432
	433	m_cart->rom_alloc(size, 1);
	434	cart = m_cart->get_rom_base();
	435
427	436	if (image.software_entry() == NULL)
428		{
429		if (image.fread( cart, size) != size)
430		{
431		image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unable to fully read from file");
432		return IMAGE_INIT_FAIL;
433		}
434		}
	437	image.fread(cart, size);
435	438	else
436	439	memcpy(cart, image.get_software_region("rom"), size);
437
	440
438	441	return IMAGE_INIT_PASS;
439	442	}
440	443
r32144	r32145
476	479	MCFG_PALETTE_ADD("palette", 16+1) //+1 for the background color
477	480	MCFG_GFXDECODE_ADD("gfxdecode", "palette", rx78)
478	481
479		MCFG_CARTSLOT_ADD("cart")
480		MCFG_CARTSLOT_EXTENSION_LIST("rom")
481		MCFG_CARTSLOT_NOT_MANDATORY
482		MCFG_CARTSLOT_LOAD(rx78_state,rx78_cart)
483		MCFG_CARTSLOT_INTERFACE("rx78_cart")
	482	MCFG_GENERIC_CARTSLOT_ADD("cartslot", GENERIC_ROM8_WIDTH, generic_plain_slot, "rx78_cart")
	483	MCFG_GENERIC_EXTENSIONS("bin,rom")
	484	MCFG_GENERIC_LOAD(rx78_state, rx78_cart)
484	485
485	486	MCFG_RAM_ADD(RAM_TAG)
486	487	MCFG_RAM_DEFAULT_SIZE("32k")
r32144	r32145
505	506	ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASEFF )
506	507	ROM_LOAD( "ipl.rom", 0x0000, 0x2000, CRC(a194ea53) SHA1(ba39e73e6eb7cbb8906fff1f81a98964cd62af0d))
507	508
508		ROM_REGION( 0x4000, "cart_img", ROMREGION_ERASEFF )
509		ROM_CART_LOAD("cart", 0x0000, 0x4000, ROM_OPTIONAL | ROM_NOMIRROR)
510
511	509	ROM_REGION( 6 * 0x2000, "vram", ROMREGION_ERASE00 )
512	510	ROM_END
513	511
r32144	r32145
516	514	UINT32 ram_size = m_ram->size();
517	515	address_space &prg = m_maincpu->space(AS_PROGRAM);
518	516
519		if(ram_size == 0x4000)
	517	if (ram_size == 0x4000)
520	518	prg.unmap_readwrite(0x6000, 0xafff);
521	519	}
522	520

trunk/src/mess/drivers/gamepock.c

r32144	r32145
3	3	#include "emu.h"
4	4	#include "cpu/upd7810/upd7810.h"
5	5	#include "sound/speaker.h"
6		#include "imagedev/cartslot.h"
	6	#include "bus/generic/carts.h"
7	7	#include "includes/gamepock.h"
8	8	#include "rendlay.h"
9	9
r32144	r32145
12	12	ADDRESS_MAP_UNMAP_HIGH
13	13	AM_RANGE(0x0000,0x0fff) AM_ROM
14	14	AM_RANGE(0x1000,0x3fff) AM_NOP
15		AM_RANGE(0x4000,0xBfff) AM_ROM AM_REGION("user1", 0)
16		AM_RANGE(0xC000,0xC7ff) AM_MIRROR(0x0800) AM_RAM
	15	//AM_RANGE(0x4000,0xbfff) AM_ROM      // mapped by the cartslot
	16	AM_RANGE(0xc000,0xc7ff) AM_MIRROR(0x0800) AM_RAM
17	17	AM_RANGE(0xff80,0xffff) AM_RAM              /* 128 bytes microcontroller RAM */
18	18	ADDRESS_MAP_END
19	19
r32144	r32145
42	42	INPUT_PORTS_END
43	43
44	44
45		DEVICE_IMAGE_LOAD_MEMBER(gamepock_state,gamepock_cart) {
46		UINT8 *cart = memregion("user1" )->base();
47
48		if ( image.software_entry() == NULL )
49		{
50		int size = image.length();
51		if ( image.fread( cart, size ) != size ) {
52		image.seterror( IMAGE_ERROR_UNSPECIFIED, "Unable to fully read from file" );
53		return IMAGE_INIT_FAIL;
54		}
55		}
56		else
57		{
58		memcpy( cart, image.get_software_region( "rom" ), image.get_software_region_length("rom") );
59		}
60
61		return IMAGE_INIT_PASS;
62		}
63
64
65	45	static MACHINE_CONFIG_START( gamepock, gamepock_state )
66	46	MCFG_CPU_ADD("maincpu", UPD78C06, XTAL_6MHz)    /* uPD78C06AG */
67	47	MCFG_CPU_PROGRAM_MAP( gamepock_mem)
r32144	r32145
85	65	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
86	66
87	67	/* cartridge */
88		MCFG_CARTSLOT_ADD("cart")
89		MCFG_CARTSLOT_INTERFACE("gamepock_cart")
90		MCFG_CARTSLOT_EXTENSION_LIST("bin")
91		MCFG_CARTSLOT_NOT_MANDATORY
92		MCFG_CARTSLOT_LOAD(gamepock_state,gamepock_cart)
	68	MCFG_GENERIC_CARTSLOT_ADD("cartslot", GENERIC_ROM8_WIDTH, generic_plain_slot, "gamepock_cart")
93	69
94	70	/* Software lists */
95	71	MCFG_SOFTWARE_LIST_ADD("cart_list","gamepock")
r32144	r32145
99	75	ROM_START( gamepock )
100	76	ROM_REGION( 0x1000, "maincpu", ROMREGION_ERASEFF )
101	77	ROM_LOAD( "egpcboot.bin", 0x0000, 0x1000, CRC(ee1ea65d) SHA1(9c7731b5ead721d2cc7f7e2655c5fed9e56db8b0) )
102		ROM_REGION( 0x8000, "user1", ROMREGION_ERASEFF )
103	78	ROM_END
104	79
105	80

trunk/src/mess/drivers/pv2000.c

r32144	r32145
30	30	#include "emu.h"
31	31	#include "cpu/z80/z80.h"
32	32	#include "sound/sn76496.h"
	33	#include "sound/wave.h"
33	34	#include "video/tms9928a.h"
34		#include "imagedev/cartslot.h"
35	35	#include "imagedev/cassette.h"
36		#include "sound/wave.h"
	36	#include "bus/generic/slot.h"
	37	#include "bus/generic/carts.h"
37	38
38	39
39	40	class pv2000_state : public driver_device
r32144	r32145
41	42	public:
42	43	pv2000_state(const machine_config &mconfig, device_type type, const char *tag)
43	44	: driver_device(mconfig, type, tag),
44		m_maincpu(*this, "maincpu"),
45		m_cass(*this, "cassette"),
46		m_last_state(0)
47		{ }
	45	m_maincpu(*this, "maincpu"),
	46	m_cass(*this, "cassette"),
	47	m_cart(*this, "cartslot"),
	48	m_last_state(0)
	49	{ }
48	50
49	51	required_device<cpu_device> m_maincpu;
50	52	required_device<cassette_image_device> m_cass;
51		DECLARE_WRITE8_MEMBER(pv2000_cass_conf_w);
52		DECLARE_WRITE8_MEMBER(pv2000_keys_w);
53		DECLARE_READ8_MEMBER(pv2000_keys_hi_r);
54		DECLARE_READ8_MEMBER(pv2000_keys_lo_r);
55		DECLARE_READ8_MEMBER(pv2000_keys_mod_r);
	53	required_device<generic_slot_device> m_cart;
	54	DECLARE_WRITE8_MEMBER(cass_conf_w);
	55	DECLARE_WRITE8_MEMBER(keys_w);
	56	DECLARE_READ8_MEMBER(keys_hi_r);
	57	DECLARE_READ8_MEMBER(keys_lo_r);
	58	DECLARE_READ8_MEMBER(keys_mod_r);
56	59	DECLARE_WRITE_LINE_MEMBER(pv2000_vdp_interrupt);
57	60	DECLARE_READ8_MEMBER(cass_in);
58	61	DECLARE_WRITE8_MEMBER(cass_out);
r32144	r32145
62	65	UINT8 m_cass_conf;
63	66	virtual void machine_start();
64	67	virtual void machine_reset();
65		DECLARE_DEVICE_IMAGE_LOAD_MEMBER( pv2000_cart );
	68	DECLARE_DEVICE_IMAGE_LOAD_MEMBER(pv2000_cart);
66	69	};
67	70
68	71
69		WRITE8_MEMBER( pv2000_state::pv2000_cass_conf_w )
	72	WRITE8_MEMBER( pv2000_state::cass_conf_w )
70	73	{
71		logerror( "%s: pv2000_cass_conf_w %02x\n", machine().describe_context(), data );
	74	logerror( "%s: cass_conf_w %02x\n", machine().describe_context(), data );
72	75
73	76	m_cass_conf = data & 0x0f;
74	77
75	78	if ( m_cass_conf & 0x01 )
76		m_cass->change_state(CASSETTE_MOTOR_ENABLED, CASSETTE_MASK_MOTOR );
	79	m_cass->change_state(CASSETTE_MOTOR_ENABLED, CASSETTE_MASK_MOTOR);
77	80	else
78		m_cass->change_state(CASSETTE_MOTOR_DISABLED, CASSETTE_MASK_MOTOR );
	81	m_cass->change_state(CASSETTE_MOTOR_DISABLED, CASSETTE_MASK_MOTOR);
79	82	}
80	83
81	84
82		WRITE8_MEMBER( pv2000_state::pv2000_keys_w )
	85	WRITE8_MEMBER( pv2000_state::keys_w )
83	86	{
84		logerror( "%s: pv2000_keys_w %02x\n", machine().describe_context(), data );
	87	logerror( "%s: keys_w %02x\n", machine().describe_context(), data );
85	88
86	89	m_keyb_column = data & 0x0f;
87	90
r32144	r32145
89	92	}
90	93
91	94
92		READ8_MEMBER( pv2000_state::pv2000_keys_hi_r )
	95	READ8_MEMBER( pv2000_state::keys_hi_r )
93	96	{
94	97	UINT8 data = 0;
95	98	char kbdrow[6];
r32144	r32145
113	116	}
114	117
115	118
116		READ8_MEMBER( pv2000_state::pv2000_keys_lo_r )
	119	READ8_MEMBER( pv2000_state::keys_lo_r )
117	120	{
118	121	UINT8 data = 0;
119	122	char kbdrow[6];
r32144	r32145
140	143	}
141	144
142	145
143		READ8_MEMBER( pv2000_state::pv2000_keys_mod_r )
	146	READ8_MEMBER( pv2000_state::keys_mod_r )
144	147	{
145	148	return 0xf0 | ioport( "MOD" )->read();
146	149	}
r32144	r32145
169	172	/* Memory Maps */
170	173
171	174	static ADDRESS_MAP_START( pv2000_map, AS_PROGRAM, 8, pv2000_state )
172		AM_RANGE(0x0000, 0x3FFF) AM_ROM
	175	AM_RANGE(0x0000, 0x3fff) AM_ROM
173	176
174	177	AM_RANGE(0x4000, 0x4000) AM_DEVREADWRITE("tms9928a", tms9928a_device, vram_read, vram_write)
175	178	AM_RANGE(0x4001, 0x4001) AM_DEVREADWRITE("tms9928a", tms9928a_device, register_read, register_write)
176	179
177		AM_RANGE(0x7000, 0x7FFF) AM_RAM
178		//AM_RANGE(0x8000, 0xBFFF) ext ram?
179		AM_RANGE(0xC000, 0xFFFF) AM_ROM  //cart
	180	AM_RANGE(0x7000, 0x7fff) AM_RAM
	181	//AM_RANGE(0x8000, 0xbfff) ext ram?
	182	//AM_RANGE(0xc000, 0xffff)      // mapped by the cartslot
180	183	ADDRESS_MAP_END
181	184
182	185
r32144	r32145
184	187	ADDRESS_MAP_GLOBAL_MASK(0xff)
185	188
186	189	//theres also printer and tape I/O (TODO)
187		AM_RANGE(0x00, 0x00) AM_WRITE(pv2000_cass_conf_w)
	190	AM_RANGE(0x00, 0x00) AM_WRITE(cass_conf_w)
188	191
189	192	//keyboard/joystick
190		AM_RANGE(0x10, 0x10) AM_READ(pv2000_keys_hi_r)
191		AM_RANGE(0x20, 0x20) AM_READWRITE(pv2000_keys_lo_r, pv2000_keys_w)
	193	AM_RANGE(0x10, 0x10) AM_READ(keys_hi_r)
	194	AM_RANGE(0x20, 0x20) AM_READWRITE(keys_lo_r, keys_w)
192	195
193	196	//sn76489a
194		AM_RANGE(0x40, 0x40) AM_READ(pv2000_keys_mod_r) AM_DEVWRITE("sn76489a", sn76489a_device, write)
	197	AM_RANGE(0x40, 0x40) AM_READ(keys_mod_r) AM_DEVWRITE("sn76489a", sn76489a_device, write)
195	198
196	199	/* Cassette input. Gets hit a lot after a GLOAD command */
197	200	AM_RANGE(0x60, 0x60) AM_READWRITE(cass_in,cass_out)
r32144	r32145
341	344
342	345	void pv2000_state::machine_start()
343	346	{
	347	if (m_cart->cart_mounted())
	348	m_maincpu->space(AS_PROGRAM).install_read_handler(0xc000, 0xffff, read8_delegate(FUNC(generic_slot_device::read_rom),(generic_slot_device*)m_cart));
344	349	}
345	350
346	351	void pv2000_state::machine_reset()
r32144	r32145
355	360
356	361	DEVICE_IMAGE_LOAD_MEMBER( pv2000_state, pv2000_cart )
357	362	{
358		UINT8 *cart = memregion("maincpu")->base() + 0xC000;
	363	UINT8 *cart;
359	364	UINT32 size;
360
	365
361	366	if (image.software_entry() == NULL)
362	367	size = image.length();
363	368	else
364	369	size = image.get_software_region_length("rom");
365
	370
366	371	if (size != 0x2000 && size != 0x4000)
367	372	{
368	373	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
369	374	return IMAGE_INIT_FAIL;
370	375	}
371
	376
	377	m_cart->rom_alloc(size, 1);
	378	cart = m_cart->get_rom_base();
	379
372	380	if (image.software_entry() == NULL)
373		{
374		if (image.fread( cart, size) != size)
375		{
376		image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unable to fully read from file");
377		return IMAGE_INIT_FAIL;
378		}
379		}
	381	image.fread(cart, size);
380	382	else
381	383	memcpy(cart, image.get_software_region("rom"), size);
382
	384
383	385	return IMAGE_INIT_PASS;
384	386	}
385	387
r32144	r32145
391	393	MCFG_CPU_PROGRAM_MAP(pv2000_map)
392	394	MCFG_CPU_IO_MAP(pv2000_io_map)
393	395
394
395	396	// video hardware
396	397	MCFG_DEVICE_ADD( "tms9928a", TMS9928A, XTAL_10_738635MHz / 2 )
397	398	MCFG_TMS9928A_VRAM_SIZE(0x4000)
r32144	r32145
413	414	MCFG_CASSETTE_DEFAULT_STATE(CASSETTE_STOPPED | CASSETTE_MOTOR_DISABLED)
414	415
415	416	/* cartridge */
416		MCFG_CARTSLOT_ADD("cart")
417		MCFG_CARTSLOT_EXTENSION_LIST("rom,col,bin")
418		MCFG_CARTSLOT_NOT_MANDATORY
419		MCFG_CARTSLOT_LOAD(pv2000_state,pv2000_cart)
420		MCFG_CARTSLOT_INTERFACE("pv2000_cart")
	417	MCFG_GENERIC_CARTSLOT_ADD("cartslot", GENERIC_ROM8_WIDTH, generic_plain_slot, "pv2000_cart")
	418	MCFG_GENERIC_EXTENSIONS("bin,rom,col")
	419	MCFG_GENERIC_LOAD(pv2000_state, pv2000_cart)
421	420
422	421	/* Software lists */
423	422	MCFG_SOFTWARE_LIST_ADD("cart_list","pv2000")
r32144	r32145
429	428	ROM_START (pv2000)
430	429	ROM_REGION( 0x10000, "maincpu", 0 )
431	430	ROM_LOAD( "hn613128pc64.bin", 0x0000, 0x4000, CRC(8f31f297) SHA1(94b5f54dd7bce321e377fdaaf592acd3870cf621) )
432		ROM_CART_LOAD("cart", 0xC000, 0x4000, ROM_OPTIONAL)
433	431	ROM_END
434	432
435	433

trunk/src/mess/drivers/aim65.c

r32144	r32145
144	144	MACHINE DRIVERS
145	145	***************************************************************************/
146	146
147		struct aim_cart_range
	147	int aim65_state::load_cart(device_image_interface &image, generic_slot_device *slot, const char *slot_tag)
148	148	{
149		const char *tag;
150		int offset;
151		};
152
153		static const struct aim_cart_range aim_cart_table[] =
154		{
155		{ ":z24",   0xd000 },
156		{ ":z25",   0xc000 },
157		{ ":z26",   0xb000 },
158		{ 0 }
159		};
160
161		DEVICE_IMAGE_LOAD_MEMBER( aim65_state, aim65_cart )
162		{
	149	UINT8 *cart;
163	150	UINT32 size;
164		const struct aim_cart_range *aim_cart = &aim_cart_table[0], *this_cart;
165	151
166		/* First, determine where this cart has to be loaded */
167		while (aim_cart->tag)
	152	if (image.software_entry() == NULL)
	153	size = image.length();
	154	else
	155	size = image.get_software_region_length("rom");
	156
	157	if (size > 0x1000)
168	158	{
169		if (strcmp(aim_cart->tag, image.device().tag()) == 0)
170		break;
171
172		aim_cart++;
173		}
174
175		this_cart = aim_cart;
176
177		if (!this_cart->tag)
178		{
179		astring errmsg;
180		errmsg.printf("Tag '%s' could not be found", image.device().tag());
181		image.seterror(IMAGE_ERROR_UNSPECIFIED, errmsg.cstr());
	159	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
182	160	return IMAGE_INIT_FAIL;
183	161	}
184	162
185		dynamic_buffer temp_copy;
186		if (image.software_entry() == NULL)
187		{
188		size = image.length();
	163	slot->rom_alloc(size, 1);
	164	cart = slot->get_rom_base();
189	165
190		if (size > 0x1000)
191		{
192		image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
193		return IMAGE_INIT_FAIL;
194		}
195
196		temp_copy.resize(size);
197		if (image.fread(temp_copy, size) != size)
198		{
199		image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unable to fully read from file");
200		return IMAGE_INIT_FAIL;
201		}
202		}
	166	if (image.software_entry() == NULL)
	167	image.fread(cart, size);
203	168	else
204	169	{
205		if (image.get_software_region(this_cart->tag + 1) == NULL)
	170	if (image.get_software_region(slot_tag) == NULL)
206	171	{
207	172	astring errmsg;
208		errmsg.printf("Attempted to load file with wrong extension\nCartslot '%s' only accepts files with '.%s' extension",
209		this_cart->tag, this_cart->tag + 1);
	173	errmsg.printf("Attempted to load file with wrong extension\nSocket '%s' only accepts files with '.%s' extension",
	174	slot_tag, slot_tag);
210	175	image.seterror(IMAGE_ERROR_UNSPECIFIED, errmsg.cstr());
211	176	return IMAGE_INIT_FAIL;
212	177	}
213
214		size = image.get_software_region_length(this_cart->tag + 1);
215		temp_copy.resize(size);
216		memcpy(temp_copy, image.get_software_region(this_cart->tag + 1), size);
	178	memcpy(cart, image.get_software_region(slot_tag), size);
217	179	}
218	180
219		memcpy(memregion("maincpu")->base() + this_cart->offset, temp_copy, size);
220
221	181	return IMAGE_INIT_PASS;
222	182	}
223	183
	184
224	185	static MACHINE_CONFIG_START( aim65, aim65_state )
225	186	/* basic machine hardware */
226	187	MCFG_CPU_ADD("maincpu", M6502, AIM65_CLOCK) /* 1 MHz */
r32144	r32145
276	237	MCFG_CASSETTE_ADD( "cassette2" )
277	238	MCFG_CASSETTE_DEFAULT_STATE(CASSETTE_RECORD | CASSETTE_MOTOR_DISABLED | CASSETTE_SPEAKER_MUTED)
278	239
279		MCFG_CARTSLOT_ADD("z26")
280		MCFG_CARTSLOT_EXTENSION_LIST("z26")
281		MCFG_CARTSLOT_INTERFACE("aim65_cart")
282		MCFG_CARTSLOT_LOAD(aim65_state, aim65_cart)
283		MCFG_CARTSLOT_NOT_MANDATORY
	240	MCFG_GENERIC_SOCKET_ADD("z26", GENERIC_ROM8_WIDTH, generic_plain_slot, "aim65_cart")
	241	MCFG_GENERIC_EXTENSIONS("z26")
	242	MCFG_GENERIC_LOAD(aim65_state, z26_load)
284	243
285		MCFG_CARTSLOT_ADD("z25")
286		MCFG_CARTSLOT_EXTENSION_LIST("z25")
287		MCFG_CARTSLOT_INTERFACE("aim65_cart")
288		MCFG_CARTSLOT_LOAD(aim65_state, aim65_cart)
289		MCFG_CARTSLOT_NOT_MANDATORY
	244	MCFG_GENERIC_SOCKET_ADD("z25", GENERIC_ROM8_WIDTH, generic_plain_slot, "aim65_cart")
	245	MCFG_GENERIC_EXTENSIONS("z25")
	246	MCFG_GENERIC_LOAD(aim65_state, z25_load)
290	247
291		MCFG_CARTSLOT_ADD("z24")
292		MCFG_CARTSLOT_EXTENSION_LIST("z24")
293		MCFG_CARTSLOT_INTERFACE("aim65_cart")
294		MCFG_CARTSLOT_NOT_MANDATORY
295		MCFG_CARTSLOT_LOAD(aim65_state, aim65_cart)
	248	MCFG_GENERIC_SOCKET_ADD("z24", GENERIC_ROM8_WIDTH, generic_plain_slot, "aim65_cart")
	249	MCFG_GENERIC_EXTENSIONS("z24")
	250	MCFG_GENERIC_LOAD(aim65_state, z24_load)
296	251
297	252	/* internal ram */
298	253	MCFG_RAM_ADD(RAM_TAG)

trunk/src/mess/drivers/supracan.c

r32144	r32145
78	78	#include "emu.h"
79	79	#include "cpu/m68000/m68000.h"
80	80	#include "cpu/m6502/m6502.h"
81		#include "imagedev/cartslot.h"
82		//#include "debugger.h"
	81	#include "bus/generic/slot.h"
	82	#include "bus/generic/carts.h"
83	83
84	84	#define SOUNDCPU_BOOT_HACK      (1)
85	85
r32144	r32145
119	119	: driver_device(mconfig, type, tag),
120	120	m_maincpu(*this, "maincpu"),
121	121	m_soundcpu(*this, "soundcpu"),
	122	m_cart(*this, "cartslot"),
122	123	m_soundram(*this, "soundram"),
123	124	m_gfxdecode(*this, "gfxdecode"),
124	125	m_palette(*this, "palette")
r32144	r32145
128	129
129	130	required_device<cpu_device> m_maincpu;
130	131	required_device<cpu_device> m_soundcpu;
131		DECLARE_READ16_MEMBER(supracan_68k_soundram_r);
132		DECLARE_WRITE16_MEMBER(supracan_68k_soundram_w);
133		DECLARE_READ8_MEMBER(supracan_6502_soundmem_r);
134		DECLARE_WRITE8_MEMBER(supracan_6502_soundmem_w);
	132	required_device<generic_slot_device> m_cart;
	133	DECLARE_READ16_MEMBER(_68k_soundram_r);
	134	DECLARE_WRITE16_MEMBER(_68k_soundram_w);
	135	DECLARE_READ8_MEMBER(_6502_soundmem_r);
	136	DECLARE_WRITE8_MEMBER(_6502_soundmem_w);
135	137
136		void supracan_dma_w(address_space &space, int offset, UINT16 data, UINT16 mem_mask, int ch);
137		WRITE16_MEMBER( supracan_dma_channel0_w );
138		WRITE16_MEMBER( supracan_dma_channel1_w );
	138	void dma_w(address_space &space, int offset, UINT16 data, UINT16 mem_mask, int ch);
	139	DECLARE_WRITE16_MEMBER(dma_channel0_w);
	140	DECLARE_WRITE16_MEMBER(dma_channel1_w);
139	141
140		DECLARE_WRITE16_MEMBER(supracan_dma_w);
141		DECLARE_READ16_MEMBER(supracan_sound_r);
142		DECLARE_WRITE16_MEMBER(supracan_sound_w);
143		DECLARE_READ16_MEMBER(supracan_video_r);
144		DECLARE_WRITE16_MEMBER(supracan_video_w);
145		DECLARE_READ16_MEMBER(supracan_vram_r);
146		DECLARE_WRITE16_MEMBER(supracan_vram_w);
	142	DECLARE_READ16_MEMBER(sound_r);
	143	DECLARE_WRITE16_MEMBER(sound_w);
	144	DECLARE_READ16_MEMBER(video_r);
	145	DECLARE_WRITE16_MEMBER(video_w);
	146	DECLARE_READ16_MEMBER(vram_r);
	147	DECLARE_WRITE16_MEMBER(vram_w);
147	148	DECLARE_WRITE16_MEMBER(paletteram_w);
148	149	acan_dma_regs_t m_acan_dma_regs;
149	150	acan_sprdma_regs_t m_acan_sprdma_regs;
r32144	r32145
997	998	}
998	999
999	1000
1000		void supracan_state::supracan_dma_w(address_space &space, int offset, UINT16 data, UINT16 mem_mask, int ch)
	1001	void supracan_state::dma_w(address_space &space, int offset, UINT16 data, UINT16 mem_mask, int ch)
1001	1002	{
1002	1003	acan_dma_regs_t *acan_dma_regs = &m_acan_dma_regs;
1003	1004	address_space &mem = m_maincpu->space(AS_PROGRAM);
r32144	r32145
1005	1006	switch(offset)
1006	1007	{
1007	1008	case 0x00/2: // Source address MSW
1008		verboselog("maincpu", 0, "supracan_dma_w: source msw %d: %04x\n", ch, data);
	1009	verboselog("maincpu", 0, "dma_w: source msw %d: %04x\n", ch, data);
1009	1010	acan_dma_regs->source[ch] &= 0x0000ffff;
1010	1011	acan_dma_regs->source[ch] |= data << 16;
1011	1012	break;
1012	1013	case 0x02/2: // Source address LSW
1013		verboselog("maincpu", 0, "supracan_dma_w: source lsw %d: %04x\n", ch, data);
	1014	verboselog("maincpu", 0, "dma_w: source lsw %d: %04x\n", ch, data);
1014	1015	acan_dma_regs->source[ch] &= 0xffff0000;
1015	1016	acan_dma_regs->source[ch] |= data;
1016	1017	break;
1017	1018	case 0x04/2: // Destination address MSW
1018		verboselog("maincpu", 0, "supracan_dma_w: dest msw %d: %04x\n", ch, data);
	1019	verboselog("maincpu", 0, "dma_w: dest msw %d: %04x\n", ch, data);
1019	1020	acan_dma_regs->dest[ch] &= 0x0000ffff;
1020	1021	acan_dma_regs->dest[ch] |= data << 16;
1021	1022	break;
1022	1023	case 0x06/2: // Destination address LSW
1023		verboselog("maincpu", 0, "supracan_dma_w: dest lsw %d: %04x\n", ch, data);
	1024	verboselog("maincpu", 0, "dma_w: dest lsw %d: %04x\n", ch, data);
1024	1025	acan_dma_regs->dest[ch] &= 0xffff0000;
1025	1026	acan_dma_regs->dest[ch] |= data;
1026	1027	break;
1027	1028	case 0x08/2: // Byte count
1028		verboselog("maincpu", 0, "supracan_dma_w: count %d: %04x\n", ch, data);
	1029	verboselog("maincpu", 0, "dma_w: count %d: %04x\n", ch, data);
1029	1030	acan_dma_regs->count[ch] = data;
1030	1031	break;
1031	1032	case 0x0a/2: // Control
1032		verboselog("maincpu", 0, "supracan_dma_w: control %d: %04x\n", ch, data);
	1033	verboselog("maincpu", 0, "dma_w: control %d: %04x\n", ch, data);
1033	1034	if(data & 0x8800)
1034	1035	{
1035	1036	//            if(data & 0x2000)
1036	1037	//                acan_dma_regs->source-=2;
1037		logerror("supracan_dma_w: Kicking off a DMA from %08x to %08x, %d bytes (%04x)\n", acan_dma_regs->source[ch], acan_dma_regs->dest[ch], acan_dma_regs->count[ch] + 1, data);
	1038	logerror("dma_w: Kicking off a DMA from %08x to %08x, %d bytes (%04x)\n", acan_dma_regs->source[ch], acan_dma_regs->dest[ch], acan_dma_regs->count[ch] + 1, data);
1038	1039
1039	1040	for(int i = 0; i <= acan_dma_regs->count[ch]; i++)
1040	1041	{
r32144	r32145
1057	1058	}
1058	1059	else if(data != 0x0000) // fake DMA, used by C.U.G.
1059	1060	{
1060		verboselog("maincpu", 0, "supracan_dma_w: Unknown DMA kickoff value of %04x (other regs %08x, %08x, %d)\n", data, acan_dma_regs->source[ch], acan_dma_regs->dest[ch], acan_dma_regs->count[ch] + 1);
1061		fatalerror("supracan_dma_w: Unknown DMA kickoff value of %04x (other regs %08x, %08x, %d)\n",data, acan_dma_regs->source[ch], acan_dma_regs->dest[ch], acan_dma_regs->count[ch] + 1);
	1061	verboselog("maincpu", 0, "dma_w: Unknown DMA kickoff value of %04x (other regs %08x, %08x, %d)\n", data, acan_dma_regs->source[ch], acan_dma_regs->dest[ch], acan_dma_regs->count[ch] + 1);
	1062	fatalerror("dma_w: Unknown DMA kickoff value of %04x (other regs %08x, %08x, %d)\n",data, acan_dma_regs->source[ch], acan_dma_regs->dest[ch], acan_dma_regs->count[ch] + 1);
1062	1063	}
1063	1064	break;
1064	1065	default:
1065		verboselog("maincpu", 0, "supracan_dma_w: Unknown register: %08x = %04x & %04x\n", 0xe90020 + (offset << 1), data, mem_mask);
	1066	verboselog("maincpu", 0, "dma_w: Unknown register: %08x = %04x & %04x\n", 0xe90020 + (offset << 1), data, mem_mask);
1066	1067	break;
1067	1068	}
1068	1069	}
1069	1070
1070		WRITE16_MEMBER( supracan_state::supracan_dma_channel0_w )
	1071	WRITE16_MEMBER( supracan_state::dma_channel0_w )
1071	1072	{
1072		supracan_dma_w(space,offset,data,mem_mask,0);
	1073	dma_w(space, offset, data, mem_mask, 0);
1073	1074	}
1074	1075
1075		WRITE16_MEMBER( supracan_state::supracan_dma_channel1_w )
	1076	WRITE16_MEMBER( supracan_state::dma_channel1_w )
1076	1077	{
1077		supracan_dma_w(space,offset,data,mem_mask,1);
	1078	dma_w(space, offset, data, mem_mask, 1);
1078	1079	}
1079	1080
1080	1081
r32144	r32145
1095	1096	}
1096	1097
1097	1098
1098		READ16_MEMBER( supracan_state::supracan_vram_r )
	1099	READ16_MEMBER( supracan_state::vram_r )
1099	1100	{
1100	1101	return m_vram[offset];
1101	1102	}
1102	1103
1103	1104
1104		WRITE16_MEMBER( supracan_state::supracan_vram_w )
	1105	WRITE16_MEMBER( supracan_state::vram_w )
1105	1106	{
1106	1107	COMBINE_DATA(&m_vram[offset]);
1107	1108
r32144	r32145
1124	1125	}
1125	1126
1126	1127	static ADDRESS_MAP_START( supracan_mem, AS_PROGRAM, 16, supracan_state )
1127		AM_RANGE( 0x000000, 0x3fffff ) AM_ROM AM_REGION( "cart", 0 )
	1128	//AM_RANGE( 0x000000, 0x3fffff )      // mapped by the cartslot
1128	1129	AM_RANGE( 0xe80200, 0xe80201 ) AM_READ_PORT("P1")
1129	1130	AM_RANGE( 0xe80202, 0xe80203 ) AM_READ_PORT("P2")
1130	1131	AM_RANGE( 0xe80208, 0xe80209 ) AM_READ_PORT("P3")
1131	1132	AM_RANGE( 0xe8020c, 0xe8020d ) AM_READ_PORT("P4")
1132		AM_RANGE( 0xe80000, 0xe8ffff ) AM_READWRITE( supracan_68k_soundram_r, supracan_68k_soundram_w )
1133		AM_RANGE( 0xe90000, 0xe9001f ) AM_READWRITE( supracan_sound_r, supracan_sound_w )
1134		AM_RANGE( 0xe90020, 0xe9002f ) AM_WRITE( supracan_dma_channel0_w )
1135		AM_RANGE( 0xe90030, 0xe9003f ) AM_WRITE( supracan_dma_channel1_w )
	1133	AM_RANGE( 0xe80000, 0xe8ffff ) AM_READWRITE(_68k_soundram_r, _68k_soundram_w)
	1134	AM_RANGE( 0xe90000, 0xe9001f ) AM_READWRITE(sound_r, sound_w)
	1135	AM_RANGE( 0xe90020, 0xe9002f ) AM_WRITE(dma_channel0_w)
	1136	AM_RANGE( 0xe90030, 0xe9003f ) AM_WRITE(dma_channel1_w)
1136	1137
1137		AM_RANGE( 0xf00000, 0xf001ff ) AM_READWRITE( supracan_video_r, supracan_video_w )
	1138	AM_RANGE( 0xf00000, 0xf001ff ) AM_READWRITE(video_r, video_w)
1138	1139	AM_RANGE( 0xf00200, 0xf003ff ) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
1139		AM_RANGE( 0xf40000, 0xf5ffff ) AM_READWRITE(supracan_vram_r, supracan_vram_w)
	1140	AM_RANGE( 0xf40000, 0xf5ffff ) AM_READWRITE(vram_r, vram_w)
1140	1141	AM_RANGE( 0xfc0000, 0xfdffff ) AM_MIRROR(0x30000) AM_RAM /* System work ram */
1141	1142	ADDRESS_MAP_END
1142	1143
1143		READ8_MEMBER( supracan_state::supracan_6502_soundmem_r )
	1144	READ8_MEMBER( supracan_state::_6502_soundmem_r )
1144	1145	{
1145	1146	address_space &mem = m_maincpu->space(AS_PROGRAM);
1146	1147	UINT8 data = m_soundram[offset];
r32144	r32145
1199	1200	return data;
1200	1201	}
1201	1202
1202		WRITE8_MEMBER( supracan_state::supracan_6502_soundmem_w )
	1203	WRITE8_MEMBER( supracan_state::_6502_soundmem_w )
1203	1204	{
1204	1205	switch(offset)
1205	1206	{
r32144	r32145
1236	1237	}
1237	1238
1238	1239	static ADDRESS_MAP_START( supracan_sound_mem, AS_PROGRAM, 8, supracan_state )
1239		AM_RANGE( 0x0000, 0xffff ) AM_READWRITE(supracan_6502_soundmem_r, supracan_6502_soundmem_w) AM_SHARE("soundram")
	1240	AM_RANGE(0x0000, 0xffff) AM_READWRITE(_6502_soundmem_r, _6502_soundmem_w) AM_SHARE("soundram")
1240	1241	ADDRESS_MAP_END
1241	1242
1242	1243	static INPUT_PORTS_START( supracan )
r32144	r32145
1369	1370	//#endif
1370	1371	}
1371	1372
1372		WRITE16_MEMBER( supracan_state::supracan_68k_soundram_w )
	1373	WRITE16_MEMBER( supracan_state::_68k_soundram_w )
1373	1374	{
1374	1375	address_space &mem = m_maincpu->space(AS_PROGRAM);
1375	1376	m_soundram[offset*2 + 1] = data & 0xff;
r32144	r32145
1380	1381	if(mem_mask & 0xff00)
1381	1382	{
1382	1383	m_hack_68k_to_6502_access = true;
1383		supracan_6502_soundmem_w(mem, offset*2, data >> 8);
	1384	_6502_soundmem_w(mem, offset*2, data >> 8);
1384	1385	m_hack_68k_to_6502_access = false;
1385	1386	}
1386	1387	if(mem_mask & 0x00ff)
1387	1388	{
1388	1389	m_hack_68k_to_6502_access = true;
1389		supracan_6502_soundmem_w(mem, offset*2 + 1, data & 0xff);
	1390	_6502_soundmem_w(mem, offset*2 + 1, data & 0xff);
1390	1391	m_hack_68k_to_6502_access = false;
1391	1392	}
1392	1393	}
1393	1394	}
1394	1395
1395		READ16_MEMBER( supracan_state::supracan_68k_soundram_r )
	1396	READ16_MEMBER( supracan_state::_68k_soundram_r )
1396	1397	{
1397	1398	address_space &mem = m_maincpu->space(AS_PROGRAM);
1398	1399	UINT16 val = m_soundram[offset*2 + 0] << 8;
r32144	r32145
1404	1405	if(mem_mask & 0xff00)
1405	1406	{
1406	1407	m_hack_68k_to_6502_access = true;
1407		val |= supracan_6502_soundmem_r(mem, offset*2) << 8;
	1408	val |= _6502_soundmem_r(mem, offset*2) << 8;
1408	1409	m_hack_68k_to_6502_access = false;
1409	1410	}
1410	1411	if(mem_mask & 0x00ff)
1411	1412	{
1412	1413	m_hack_68k_to_6502_access = true;
1413		val |= supracan_6502_soundmem_r(mem, offset*2 + 1);
	1414	val |= _6502_soundmem_r(mem, offset*2 + 1);
1414	1415	m_hack_68k_to_6502_access = false;
1415	1416	}
1416	1417	}
r32144	r32145
1418	1419	return val;
1419	1420	}
1420	1421
1421		READ16_MEMBER( supracan_state::supracan_sound_r )
	1422	READ16_MEMBER( supracan_state::sound_r )
1422	1423	{
1423	1424	UINT16 data = 0;
1424	1425
1425	1426	switch( offset )
1426	1427	{
1427	1428	default:
1428		verboselog("maincpu", 0, "supracan_sound_r: Unknown register: (%08x) & %04x\n", 0xe90000 + (offset << 1), mem_mask);
	1429	verboselog("maincpu", 0, "sound_r: Unknown register: (%08x) & %04x\n", 0xe90000 + (offset << 1), mem_mask);
1429	1430	break;
1430	1431	}
1431	1432
1432	1433	return data;
1433	1434	}
1434	1435
1435		WRITE16_MEMBER( supracan_state::supracan_sound_w )
	1436	WRITE16_MEMBER( supracan_state::sound_w )
1436	1437	{
1437	1438	switch ( offset )
1438	1439	{
r32144	r32145
1460	1461	verboselog("maincpu", 0, "sound cpu ctrl: %04x\n", data);
1461	1462	break;
1462	1463	default:
1463		verboselog("maincpu", 0, "supracan_sound_w: Unknown register: %08x = %04x & %04x\n", 0xe90000 + (offset << 1), data, mem_mask);
	1464	verboselog("maincpu", 0, "sound_w: Unknown register: %08x = %04x & %04x\n", 0xe90000 + (offset << 1), data, mem_mask);
1464	1465	break;
1465	1466	}
1466	1467	}
1467	1468
1468	1469
1469		READ16_MEMBER( supracan_state::supracan_video_r )
	1470	READ16_MEMBER( supracan_state::video_r )
1470	1471	{
1471	1472	address_space &mem = m_maincpu->space(AS_PROGRAM);
1472	1473	UINT16 data = m_video_regs[offset];
r32144	r32145
1495	1496	if(!mem.debugger_access()) verboselog("maincpu", 0, "read tilemap_flags[1] (%04x)\n", data);
1496	1497	break;
1497	1498	default:
1498		if(!mem.debugger_access()) verboselog("maincpu", 0, "supracan_video_r: Unknown register: %08x (%04x & %04x)\n", 0xf00000 + (offset << 1), data, mem_mask);
	1499	if(!mem.debugger_access()) verboselog("maincpu", 0, "video_r: Unknown register: %08x (%04x & %04x)\n", 0xf00000 + (offset << 1), data, mem_mask);
1499	1500	break;
1500	1501	}
1501	1502
r32144	r32145
1562	1563	m_video_timer->adjust( machine().first_screen()->time_until_pos( ( vpos + 1 ) % 256, 0 ) );
1563	1564	}
1564	1565
1565		WRITE16_MEMBER( supracan_state::supracan_video_w )
	1566	WRITE16_MEMBER( supracan_state::video_w )
1566	1567	{
1567	1568	address_space &mem = m_maincpu->space(AS_PROGRAM);
1568	1569	acan_sprdma_regs_t *acan_sprdma_regs = &m_acan_sprdma_regs;
r32144	r32145
1609	1610	acan_sprdma_regs->src_inc = data;
1610	1611	break;
1611	1612	case 0x1e/2:
1612		logerror( "supracan_video_w: Kicking off a DMA from %08x to %08x, %d bytes (%04x)\n", acan_sprdma_regs->src, acan_sprdma_regs->dst, acan_sprdma_regs->count, data);
	1613	logerror( "video_w: Kicking off a DMA from %08x to %08x, %d bytes (%04x)\n", acan_sprdma_regs->src, acan_sprdma_regs->dst, acan_sprdma_regs->count, data);
1613	1614
1614	1615	/* TODO: what's 0x2000 and 0x4000 for? */
1615	1616	if(data & 0x8000)
r32144	r32145
1642	1643	}
1643	1644	else
1644	1645	{
1645		verboselog("maincpu", 0, "supracan_dma_w: Attempting to kick off a DMA without bit 15 set! (%04x)\n", data);
	1646	verboselog("maincpu", 0, "dma_w: Attempting to kick off a DMA without bit 15 set! (%04x)\n", data);
1646	1647	}
1647	1648	break;
1648	1649	case 0x08/2:
r32144	r32145
1743	1744	verboselog("maincpu", 3, "irq_mask = %04x\n", data);
1744	1745	break;
1745	1746	default:
1746		verboselog("maincpu", 0, "supracan_video_w: Unknown register: %08x = %04x & %04x\n", 0xf00000 + (offset << 1), data, mem_mask);
	1747	verboselog("maincpu", 0, "video_w: Unknown register: %08x = %04x & %04x\n", 0xf00000 + (offset << 1), data, mem_mask);
1747	1748	break;
1748	1749	}
1749	1750	//  m_video_regs[offset] = data;
r32144	r32145
1752	1753
1753	1754	DEVICE_IMAGE_LOAD_MEMBER( supracan_state, supracan_cart )
1754	1755	{
1755		UINT8 *cart = memregion("cart")->base();
1756		UINT32 size = 0;
1757
	1756	UINT8 *cart;
	1757	UINT32 size;
	1758
1758	1759	if (image.software_entry() == NULL)
1759		{
1760	1760	size = image.length();
1761
1762		if (size > 0x400000)
1763		{
1764		image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
1765		return IMAGE_INIT_FAIL;
1766		}
1767
1768		if (image.fread(cart, size) != size)
1769		{
1770		image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unable to fully read from file");
1771		return IMAGE_INIT_FAIL;
1772		}
1773		}
1774	1761	else
1775		{
1776	1762	size = image.get_software_region_length("rom");
1777		memcpy(cart, image.get_software_region("rom"), size);
	1763
	1764	if (size > 0x400000)
	1765	{
	1766	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unsupported cartridge size");
	1767	return IMAGE_INIT_FAIL;
1778	1768	}
1779
	1769
	1770	m_cart->rom_alloc(size, 1);
	1771	cart = m_cart->get_rom_base();
	1772
	1773	if (image.software_entry() == NULL)
	1774	image.fread(cart, size);
	1775	else
	1776	memcpy(cart, image.get_software_region("rom"), size);
	1777
1780	1778	return IMAGE_INIT_PASS;
1781	1779	}
1782	1780
r32144	r32145
1787	1785	m_hbl_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(supracan_state::supracan_hbl_callback),this));
1788	1786	m_line_on_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(supracan_state::supracan_line_on_callback),this));
1789	1787	m_line_off_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(supracan_state::supracan_line_off_callback),this));
	1788
	1789	if (m_cart->cart_mounted())
	1790	m_maincpu->space(AS_PROGRAM).install_read_handler(0x000000, 0x3fffff, read16_delegate(FUNC(generic_slot_device::read16_rom),(generic_slot_device*)m_cart));
1790	1791	}
1791	1792
1792	1793
r32144	r32145
1920	1921	MCFG_QUANTUM_PERFECT_CPU("soundcpu")
1921	1922	#endif
1922	1923
1923
1924	1924	MCFG_SCREEN_ADD( "screen", RASTER )
1925	1925	MCFG_SCREEN_RAW_PARAMS(XTAL_10_738635MHz/2, 348, 0, 256, 256, 0, 240 )  /* No idea if this is correct */
1926	1926	MCFG_SCREEN_UPDATE_DRIVER(supracan_state, screen_update_supracan)
r32144	r32145
1932	1932
1933	1933	MCFG_GFXDECODE_ADD("gfxdecode", "palette", supracan)
1934	1934
1935		MCFG_CARTSLOT_ADD("cart")
1936		MCFG_CARTSLOT_EXTENSION_LIST("bin")
1937		MCFG_CARTSLOT_INTERFACE("supracan_cart")
1938		MCFG_CARTSLOT_LOAD(supracan_state,supracan_cart)
	1935	MCFG_GENERIC_CARTSLOT_ADD("cartslot", GENERIC_ROM16_WIDTH, generic_plain_slot, "supracan_cart")
	1936	MCFG_GENERIC_LOAD(supracan_state, supracan_cart)
1939	1937
1940	1938	MCFG_SOFTWARE_LIST_ADD("cart_list","supracan")
1941	1939	MACHINE_CONFIG_END
1942	1940
1943	1941
1944	1942	ROM_START( supracan )
1945		ROM_REGION( 0x400000, "cart", ROMREGION_ERASEFF )
1946	1943	ROM_REGION( 0x20000, "ram_gfx", ROMREGION_ERASEFF )
1947	1944	ROM_REGION( 0x20000, "ram_gfx2", ROMREGION_ERASEFF )
1948	1945	ROM_REGION( 0x20000, "ram_gfx3", ROMREGION_ERASEFF )

trunk/src/mess/mess.mak

r32144	r32145
586	586	BUSES += EPSON_SIO
587	587	BUSES += GAMEBOY
588	588	BUSES += GBA
	589	BUSES += GENERIC
589	590	BUSES += IEEE488
590	591	BUSES += IMI7000
591	592	BUSES += IQ151

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