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r32124 Tuesday 16th September, 2014 at 04:05:33 UTC by Barry Rodewald
trident: some WIP, added CRTC offset bit 8 and start address bits 16-18.
[src/emu/bus/isa]svga_trident.c trident.c trident.h

trunk/src/emu/bus/isa/trident.c
r32123r32124
88
99#include "emu.h"
1010#include "trident.h"
11#include "debugger.h"
1112
1213const device_type TRIDENT_VGA = &device_creator<trident_vga_device>;
1314
r32123r32124
2021
2122void trident_vga_device::device_start()
2223{
23   svga_device::device_start();
24   memset(&vga, 0, sizeof(vga));
25   memset(&svga, 0, sizeof(svga));
26
27   int i;
28   for (i = 0; i < 0x100; i++)
29      m_palette->set_pen_color(i, 0, 0, 0);
30
31   // Avoid an infinite loop when displaying.  0 is not possible anyway.
32   vga.crtc.maximum_scan_line = 1;
33
34
35   // copy over interfaces
36   vga.read_dipswitch = read8_delegate(); //read_dipswitch;
37   vga.svga_intf.vram_size = 0x200000;
38
39   vga.memory.resize_and_clear(vga.svga_intf.vram_size);
40   save_item(NAME(vga.memory));
41   save_pointer(vga.crtc.data,"CRTC Registers",0x100);
42   save_pointer(vga.sequencer.data,"Sequencer Registers",0x100);
43   save_pointer(vga.attribute.data,"Attribute Registers", 0x15);
44
45   m_vblank_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(vga_device::vblank_timer_cb),this));
2446   vga.svga_intf.seq_regcount = 0x0f;
2547   vga.svga_intf.crtc_regcount = 0x50;
2648   memset(&tri, 0, sizeof(tri));
r32123r32124
3052{
3153   svga_device::device_reset();
3254   svga.id = 0xd3;  // identifies at TGUI9660XGi
33   tri.revision = 0x01;  // revision identifies as TGUI9680
55   tri.revision = 0x05;  // revision identifies as TGUI9680
3456   tri.new_mode = false;  // start up in old mode
3557   tri.dac_active = false;
58   tri.linear_active = false;
59   tri.mmio_active = false;
3660}
3761
3862UINT16 trident_vga_device::offset()
r32123r32124
111135         case 0x0b:
112136            res = svga.id;
113137            tri.new_mode = true;
138            //debugger_break(machine());
114139            break;
115140         case 0x0c:  // Power Up Mode register 1
116141            res = tri.sr0c & 0xef;
r32123r32124
134159            break;
135160      }
136161   }
137
162   logerror("Trident SR%02X: read %02x\n",index,res);
138163   return res;
139164}
140165
r32123r32124
176201            if(tri.new_mode)
177202            {
178203               tri.sr0e_new = data ^ 0x02;
179               svga.bank_w = (data & 0x0f) ^ 0x02;  // bit 1 is inverted, used for card detection, it is not XORed on reading
204               svga.bank_w = (data & 0x1f) ^ 0x02;  // bit 1 is inverted, used for card detection, it is not XORed on reading
180205               if(!(tri.gc0f & 0x01))
181                  svga.bank_r = (data & 0x0f) ^ 0x02;
206                  svga.bank_r = (data & 0x1f) ^ 0x02;
182207               // TODO: handle planar modes, where bits 0 and 2 only are used
183208            }
184209            else
185210            {
186211               tri.sr0e_old = data;
187               svga.bank_w = data & 0x06;
212               svga.bank_w = data & 0x0e;
188213               if(!(tri.gc0f & 0x01))
189                  svga.bank_r = data & 0x06;
214                  svga.bank_r = data & 0x0e;
190215            }
191216            break;
192217         case 0x0f:  // Power Up Mode 2
r32123r32124
206231   {
207232      switch(index)
208233      {
234      case 0x1e:
235         res = tri.cr1e;
236         break;
209237      case 0x1f:
210238         res = tri.cr1f;
211239         break;
240      case 0x21:
241         res = tri.cr21;
242         break;
243      case 0x27:
244         res = (vga.crtc.start_addr & 0x60000) >> 17;
245         break;
246      case 0x29:
247         res = tri.cr29;
248         break;
212249      case 0x38:
213250         res = tri.pixel_depth;
214251         break;
252      case 0x39:
253         res = tri.cr39;
254         break;
255      case 0x50:
256         res = tri.cr50;
257         break;
215258      default:
216259         res = vga.crtc.data[index];
217260         break;
218261      }
219262   }
263   logerror("Trident CR%02X: read %02x\n",index,res);
220264   return res;
221265}
222266void trident_vga_device::trident_crtc_reg_write(UINT8 index, UINT8 data)
r32123r32124
231275      logerror("Trident CR%02X: write %02x\n",index,data);
232276      switch(index)
233277      {
278      case 0x1e:  // Module Testing Register
279         tri.cr1e = data;
280         vga.crtc.start_addr = (vga.crtc.start_addr & 0xfffeffff) | ((data & 0x20)<<11);
281         break;
234282      case 0x1f:
235283         tri.cr1f = data;  // "Software Programming Register"  written to by software (BIOS?)
236284         break;
285      case 0x21:  // Linear aperture
286         tri.cr21 = data;
287         tri.linear_address = ((data & 0xc0)<<18) | ((data & 0x0f)<<20);
288         tri.linear_active = data & 0x20;
289         if(tri.linear_active)
290            popmessage("Trident: Linear Aperture active - %08x, %s",tri.linear_address,(tri.cr21 & 0x10) ? "2MB" : "1MB" );
291         break;
292      case 0x27:
293         vga.crtc.start_addr = (vga.crtc.start_addr & 0xfff9ffff) | ((data & 0x03)<<17);
294         break;
295      case 0x29:
296         tri.cr29 = data;
297         vga.crtc.offset = (vga.crtc.offset & 0xfeff) | ((data & 0x10)<<4);
298         break;
237299      case 0x38:
238300         tri.pixel_depth = data;
239301         trident_define_video_mode();
240302         break;
303      case 0x39:
304         tri.cr39 = data;
305         tri.mmio_active = data & 0x01;
306         if(tri.mmio_active)
307            popmessage("Trident: MMIO activated");
308         break;
309      case 0x50:
310         tri.cr50 = data;
311         break;
241312      default:
242         logerror("Trident: 3D4 index %02x write %02x\n",index,data);
313         //logerror("Trident: 3D4 index %02x write %02x\n",index,data);
243314         break;
244315      }
245316   }
r32123r32124
261332      case 0x0f:
262333         res = tri.gc0f;
263334         break;
335      case 0x2f:
336         res = tri.gc2f;
337         break;
264338      default:
265339         res = 0xff;
266340         break;
267341      }
268342   }
343   logerror("Trident GC%02X: read %02x\n",index,res);
269344   return res;
270345}
271346
r32123r32124
289364      case 0x0f:
290365         tri.gc0f = data;
291366         break;
367      case 0x2f:  // XFree86 refers to this register as "MiscIntContReg", setting bit 2, but gives no indication as to what it does
368         tri.gc2f = data;
369         break;
292370      default:
293         logerror("Trident: Unimplemented GC register %02x write %02x\n",index,data);
371         //logerror("Trident: Unimplemented GC register %02x write %02x\n",index,data);
294372         break;
295373      }
296374   }
r32123r32124
434512   }
435513}
436514
515READ8_MEMBER(trident_vga_device::port_83c6_r)
516{
517   UINT8 res = 0xff;
518   switch(offset)
519   {
520   case 2:
521      res = port_03c0_r(space,5,mem_mask);
522      logerror("Trident: 83c6 read %02x\n",res);
523      break;
524   case 4:
525      res = vga.sequencer.index;
526      logerror("Trident: 83c8 seq read %02x\n",res);
527      break;
528   }
529   return res;
530}
531
532WRITE8_MEMBER(trident_vga_device::port_83c6_w)
533{
534   switch(offset)
535   {
536   case 2:
537      logerror("Trident: 83c6 seq write %02x\n",data);
538      port_03c0_w(space,5,data,mem_mask);
539      break;
540   case 4:
541      logerror("Trident: 83c8 seq index write %02x\n",data);
542      vga.sequencer.index = data;
543      break;
544   }
545}
546
437547READ8_MEMBER(trident_vga_device::mem_r )
438548{
439549   if (svga.rgb8_en || svga.rgb15_en || svga.rgb16_en || svga.rgb32_en)
trunk/src/emu/bus/isa/trident.h
r32123r32124
2020   virtual WRITE8_MEMBER(port_03c0_w);
2121   virtual READ8_MEMBER(port_03d0_r);
2222   virtual WRITE8_MEMBER(port_03d0_w);
23   DECLARE_READ8_MEMBER(port_83c6_r);
24   DECLARE_WRITE8_MEMBER(port_83c6_w);
2325   virtual READ8_MEMBER(mem_r);
2426   virtual WRITE8_MEMBER(mem_w);
2527   virtual UINT16 offset();
r32123r32124
3638      UINT8 sr0f;
3739      UINT8 gc0e;
3840      UINT8 gc0f;
41      UINT8 gc2f;
42      UINT8 cr1e;
3943      UINT8 cr1f;
44      UINT8 cr21;
45      UINT8 cr29;
46      UINT8 cr39;
47      UINT8 cr50;
4048      UINT8 dac;
4149      bool new_mode;
4250      bool port_3c3;
r32123r32124
4553      UINT8 revision;
4654      bool dac_active;
4755      UINT8 dac_count;
56      UINT32 linear_address;
57      bool linear_active;
58      bool mmio_active;
4859   } tri;
4960private:
5061   UINT8 trident_seq_reg_read(UINT8 index);
trunk/src/emu/bus/isa/svga_trident.c
r32123r32124
8181   m_isa->install_device(0x3b0, 0x3bf, 0, 0, read8_delegate(FUNC(trident_vga_device::port_03b0_r),m_vga), write8_delegate(FUNC(trident_vga_device::port_03b0_w),m_vga));
8282   m_isa->install_device(0x3c0, 0x3cf, 0, 0, read8_delegate(FUNC(trident_vga_device::port_03c0_r),m_vga), write8_delegate(FUNC(trident_vga_device::port_03c0_w),m_vga));
8383   m_isa->install_device(0x3d0, 0x3df, 0, 0, read8_delegate(FUNC(trident_vga_device::port_03d0_r),m_vga), write8_delegate(FUNC(trident_vga_device::port_03d0_w),m_vga));
84   m_isa->install_device(0x83c4, 0x83cb, 0, 0, read8_delegate(FUNC(trident_vga_device::port_83c6_r),m_vga), write8_delegate(FUNC(trident_vga_device::port_83c6_w),m_vga));
8485
8586   m_isa->install_memory(0xa0000, 0xbffff, 0, 0, read8_delegate(FUNC(trident_vga_device::mem_r),m_vga), write8_delegate(FUNC(trident_vga_device::mem_w),m_vga));
8687}

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