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r32118 Sunday 14th September, 2014 at 22:28:33 UTC by Michael Zapf
(MESS) ti99: Avoid debugger messing up the setaddress/memory access pairs. (nw)
[src/emu/bus/ti99_peb]bwg.c bwg.h hfdc.c hfdc.h

trunk/src/emu/bus/ti99_peb/hfdc.h
r32117r32118
5959   machine_config_constructor device_mconfig_additions() const;
6060   ioport_constructor device_input_ports() const;
6161
62   // Debug accessors
63   void debug_read(offs_t offset, UINT8* value);
64   void debug_write(offs_t offset, UINT8 data);
65
6266   // Callback for the index hole
6367   void floppy_index_callback(floppy_image_device *floppy, int state);
6468
trunk/src/emu/bus/ti99_peb/bwg.c
r32117r32118
136136
137137SETADDRESS_DBIN_MEMBER( snug_bwg_device::setaddress_dbin )
138138{
139   // Do not allow setaddress for debugger
140   if (space.debugger_access()) return;
141
139142   // Selection login in the PAL and some circuits on the board
140143
141144   // Is the card being selected?
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181184}
182185
183186/*
187    Access for debugger. This is a stripped-down version of the
188    main methods below. We only allow ROM and RAM access.
189*/
190void snug_bwg_device::debug_read(offs_t offset, UINT8* value)
191{
192   if (((offset & m_select_mask)==m_select_value) && m_selected)
193   {
194      if ((offset & 0x1c00)==0x1c00)
195      {
196         if ((offset & 0x1fe0)!=0x1fe0)
197            *value = m_buffer_ram[(m_ram_page<<10) | (offset & 0x03ff)];
198      }
199      else
200         *value = m_dsrrom[(m_rom_page<<13) | (offset & 0x1fff)];
201   }
202}
203
204void snug_bwg_device::debug_write(offs_t offset, UINT8 data)
205{
206   if (((offset & m_select_mask)==m_select_value) && m_selected)
207   {
208      if (((offset & 0x1c00)==0x1c00) && ((offset & 0x1fe0)!=0x1fe0))
209            m_buffer_ram[(m_ram_page<<10) | (m_address & 0x03ff)] = data;
210   }
211}
212
213/*
184214    Read a byte from ROM, RAM, FDC, or RTC. See setaddress_dbin for selection
185215    logic.
186216*/
187217READ8Z_MEMBER(snug_bwg_device::readz)
188218{
219   if (space.debugger_access())
220   {
221      debug_read(offset, value);
222      return;
223   }
224
189225   if (m_inDsrArea && m_selected)
190226   {
191227      // 010x xxxx xxxx xxxx
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197233            if (m_RTCsel)
198234            {
199235               // .... ..11 111x xxx0
200               if (!space.debugger_access()) *value = m_clock->read(space, (m_address & 0x001e) >> 1);
236               *value = m_clock->read(space, (m_address & 0x001e) >> 1);
201237               if (TRACE_RW) logerror("bwg: read RTC: %04x -> %02x\n", m_address & 0xffff, *value);
202238            }
203239            else
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213249               // .... ..11 1111 0xx0
214250               // Note that the value is inverted again on the board,
215251               // so we can drop the inversion
216               if (!space.debugger_access()) *value = m_wd1773->gen_r((m_address >> 1)&0x03);
252               *value = m_wd1773->gen_r((m_address >> 1)&0x03);
217253               if (TRACE_RW) logerror("bwg: read FDC: %04x -> %02x\n", m_address & 0xffff, *value);
218254               if (TRACE_DATA)
219255               {
r32117r32118
250286*/
251287WRITE8_MEMBER(snug_bwg_device::write)
252288{
289   if (space.debugger_access())
290   {
291      debug_write(offset, data);
292      return;
293   }
294
253295   if (m_inDsrArea && m_selected)
254296   {
255297      if (m_lastK)
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260302            {
261303               // .... ..11 111x xxx0
262304               if (TRACE_RW) logerror("bwg: write RTC: %04x <- %02x\n", m_address & 0xffff, data);
263               if (!space.debugger_access()) m_clock->write(space, (m_address & 0x001e) >> 1, data);
305               m_clock->write(space, (m_address & 0x001e) >> 1, data);
264306            }
265307            else
266308            {
r32117r32118
276318               // Note that the value is inverted again on the board,
277319               // so we can drop the inversion
278320               if (TRACE_RW) logerror("bwg: write FDC: %04x <- %02x\n", m_address & 0xffff, data);
279               if (!space.debugger_access()) m_wd1773->gen_w((m_address >> 1)&0x03, data);
321               m_wd1773->gen_w((m_address >> 1)&0x03, data);
280322            }
281323            else
282324            {
trunk/src/emu/bus/ti99_peb/bwg.h
r32117r32118
5454private:
5555   void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
5656
57   // Debugger accessors
58   void debug_read(offs_t offset, UINT8* value);
59   void debug_write(offs_t offset, UINT8 data);
60
5761   // Wait state logic
5862   void operate_ready_line();
5963
trunk/src/emu/bus/ti99_peb/hfdc.c
r32117r32118
9696
9797SETADDRESS_DBIN_MEMBER( myarc_hfdc_device::setaddress_dbin )
9898{
99   // Debugger does not run safely with HFDC
100   // TODO: Check why debugger messes up the access (likely to happen at other locations, too)
99   // Do not allow setaddress for the debugger. It will mess up the
100   // setaddress/memory access pairs when the CPU enters wait states.
101101   if (space.debugger_access()) return;
102102
103103   // Selection login in the PAL and some circuits on the board
r32117r32118
139139}
140140
141141/*
142    Access for debugger. This is a stripped-down version of the
143    main methods below. We only allow ROM and RAM access.
144*/
145void myarc_hfdc_device::debug_read(offs_t offset, UINT8* value)
146{
147   if (((offset & m_select_mask)==m_select_value) && m_selected)
148   {
149      if ((offset & 0x1000)==RAM_ADDR)
150      {
151         int bank = (offset & 0x0c00) >> 10;
152         *value = m_buffer_ram[(m_ram_page[bank]<<10) | (offset & 0x03ff)];
153      }
154      else
155      {
156         if ((offset & 0x0fc0)!=0x0fc0)
157         {
158            *value = m_dsrrom[(m_rom_page << 12) | (offset & 0x0fff)];
159         }
160      }
161   }
162}
163
164void myarc_hfdc_device::debug_write(offs_t offset, UINT8 data)
165{
166   if (((offset & m_select_mask)==m_select_value) && m_selected)
167   {
168      if ((offset & 0x1000)==RAM_ADDR)
169      {
170         int bank = (offset & 0x0c00) >> 10;
171         m_buffer_ram[(m_ram_page[bank]<<10) | (m_address & 0x03ff)] = data;
172      }
173   }
174}
175
176/*
142177    Read a byte from the memory address space of the HFDC
143178
144179    0x4000 - 0x4fbf one of four possible ROM pages
r32117r32118
155190*/
156191READ8Z_MEMBER(myarc_hfdc_device::readz)
157192{
158   // Debugger does not run safely with HFDC
159   if (space.debugger_access()) return;
193   if (space.debugger_access())
194   {
195      debug_read(offset, value);
196      return;
197   }
160198
161199   if (m_inDsrArea && m_selected)
162200   {
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229267*/
230268WRITE8_MEMBER( myarc_hfdc_device::write )
231269{
232   // Debugger does not run safely with HFDC
233   if (space.debugger_access()) return;
270   if (space.debugger_access())
271   {
272      debug_write(offset, data);
273      return;
274   }
234275
235276   if (m_inDsrArea && m_selected)
236277   {

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