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r32087 Friday 12th September, 2014 at 19:30:27 UTC by Wilbert Pol
dsp56k.c: Modernised cpu core (nw)

[src/emu/cpu/dsp56k]	dsp56k.c dsp56k.h dsp56mem.c
[src/mame/drivers]	plygonet.c
[src/mame/includes]	plygonet.h

trunk/src/mame/drivers/plygonet.c

r32086	r32087
198	198	if (mem_mask == 0x0000ff00) { hi_addr++; }  /* Low byte */
199	199	if (mem_mask == 0xff000000) {}              /* High byte */
200	200
201		value = dsp56k_host_interface_read(m_dsp, hi_addr);
	201	value = m_dsp->host_interface_read(hi_addr);
202	202
203	203	if (mem_mask == 0x0000ff00) { value <<= 8;  }
204	204	if (mem_mask == 0xff000000) { value <<= 24; }
r32086	r32087
278	278	if (mem_mask == 0xff000000) { hi_data = (data & 0xff000000) >> 24; }
279	279
280	280	logerror("write (host-side) %08x %08x %08x (HI %04x)\n", offset, mem_mask, data, hi_addr);
281		dsp56k_host_interface_write(m_dsp, hi_addr, hi_data);
	281	m_dsp->host_interface_write(hi_addr, hi_data);
282	282	}
283	283
284	284
r32086	r32087
353	353
354	354	static UINT8 dsp56k_bank_group(device_t* cpu)
355	355	{
356		UINT16 portC = dsp56k_get_peripheral_memory(cpu, 0xffe3);
	356	UINT16 portC = ((dsp56k_device *)cpu)->get_peripheral_memory(0xffe3);
357	357
358	358	/* If bank group B is on, it overrides bank group A */
359	359	if (portC & 0x0002)
r32086	r32087
366	366
367	367	static UINT8 dsp56k_bank_num(device_t* cpu, UINT8 bank_group)
368	368	{
369		UINT16 portC = dsp56k_get_peripheral_memory(cpu, 0xffe3);
	369	UINT16 portC = ((dsp56k_device *)cpu)->get_peripheral_memory(0xffe3);
370	370
371	371	if (bank_group == BANK_GROUP_A)
372	372	{

trunk/src/mame/includes/plygonet.h

r32086	r32087
1	1	#include "machine/eepromser.h"
2	2	#include "video/k053936.h"
	3	#include "cpu/dsp56k/dsp56k.h"
3	4
4	5
5	6	static const UINT16 dsp56k_bank00_size = 0x1000;
r32086	r32087
28	29
29	30	required_device<cpu_device> m_maincpu;
30	31	required_device<cpu_device> m_audiocpu;
31		required_device<cpu_device> m_dsp;
	32	required_device<dsp56k_device> m_dsp;
32	33	required_device<eeprom_serial_er5911_device> m_eeprom;
33	34	required_device<k053936_device> m_k053936;
34	35

trunk/src/emu/cpu/dsp56k/dsp56mem.c

r32086	r32087
488	488
489	489	READ16_MEMBER( dsp56k_device::program_r )
490	490	{
491		dsp56k_core* cpustate = get_safe_token(this);
492		return cpustate->program_ram[offset];
	491	return m_dsp56k_core.program_ram[offset];
493	492	}
494	493
495	494	WRITE16_MEMBER( dsp56k_device::program_w )
496	495	{
497		dsp56k_core* cpustate = get_safe_token(this);
498		cpustate->program_ram[offset] = data;
	496	m_dsp56k_core.program_ram[offset] = data;
499	497	}
500	498
501	499	/* Work */
502	500	READ16_MEMBER( dsp56k_device::peripheral_register_r )
503	501	{
504		dsp56k_core* cpustate = get_safe_token(this);
	502	dsp56k_core* cpustate = &m_dsp56k_core;
505	503	// (printf) logerror("Peripheral read 0x%04x\n", O2A(offset));
506	504
507	505	switch (O2A(offset))
r32086	r32087
635	633
636	634	WRITE16_MEMBER( dsp56k_device::peripheral_register_w )
637	635	{
638		dsp56k_core* cpustate = get_safe_token(this);
	636	dsp56k_core* cpustate = &m_dsp56k_core;
639	637
640	638	// Its primary behavior is RAM
641	639	// COMBINE_DATA(&cpustate->peripheral_ram[offset]);
r32086	r32087
790	788
791	789	/* These two functions are exposed to the outside world */
792	790	/* They represent the host side of the dsp56k's host interface */
793		void dsp56k_host_interface_write(device_t* device, UINT8 offset, UINT8 data)
	791	void dsp56k_device::host_interface_write(UINT8 offset, UINT8 data)
794	792	{
795		dsp56k_core* cpustate = get_safe_token(device);
	793	dsp56k_core* cpustate = &m_dsp56k_core;
796	794
797	795	/* Not exactly correct since the bootstrap hack doesn't need this to be true */
798	796	/*
r32086	r32087
886	884	}
887	885	}
888	886
889		UINT8 dsp56k_host_interface_read(device_t* device, UINT8 offset)
	887	UINT8 dsp56k_device::host_interface_read(UINT8 offset)
890	888	{
891		dsp56k_core* cpustate = get_safe_token(device);
	889	dsp56k_core* cpustate = &m_dsp56k_core;
892	890
893	891	/* Not exactly correct since the bootstrap hack doesn't need this to be true */
894	892	/*
r32086	r32087
951	949	}
952	950
953	951	/* MISC*/
954		UINT16 dsp56k_get_peripheral_memory(device_t* device, UINT16 addr)
	952	UINT16 dsp56k_device::get_peripheral_memory(UINT16 addr)
955	953	{
956		dsp56k_core* cpustate = get_safe_token(device);
	954	dsp56k_core* cpustate = &m_dsp56k_core;
957	955	return cpustate->peripheral_ram[A2O(addr)];
958	956	}

trunk/src/emu/cpu/dsp56k/dsp56k.c

r32086	r32087
40	40	using namespace DSP56K;
41	41
42	42	/***************************************************************************
43		FUNCTION PROTOTYPES
44		***************************************************************************/
45		static CPU_RESET( dsp56k );
46
47
48		/***************************************************************************
49	43	COMPONENT FUNCTIONALITY
50	44	***************************************************************************/
51	45	/* 1-9 ALU */
r32086	r32087
64	58	#include "dsp56mem.h"
65	59
66	60
	61	enum
	62	{
	63	// PCU
	64	DSP56K_PC=1,
	65	DSP56K_SR,
	66	DSP56K_LC,
	67	DSP56K_LA,
	68	DSP56K_SP,
	69	DSP56K_OMR,
	70
	71	// ALU
	72	DSP56K_X, DSP56K_Y,
	73	DSP56K_A, DSP56K_B,
	74
	75	// AGU
	76	DSP56K_R0,DSP56K_R1,DSP56K_R2,DSP56K_R3,
	77	DSP56K_N0,DSP56K_N1,DSP56K_N2,DSP56K_N3,
	78	DSP56K_M0,DSP56K_M1,DSP56K_M2,DSP56K_M3,
	79	DSP56K_TEMP,
	80	DSP56K_STATUS,
	81
	82	// CPU STACK
	83	DSP56K_ST0,
	84	DSP56K_ST1,
	85	DSP56K_ST2,
	86	DSP56K_ST3,
	87	DSP56K_ST4,
	88	DSP56K_ST5,
	89	DSP56K_ST6,
	90	DSP56K_ST7,
	91	DSP56K_ST8,
	92	DSP56K_ST9,
	93	DSP56K_ST10,
	94	DSP56K_ST11,
	95	DSP56K_ST12,
	96	DSP56K_ST13,
	97	DSP56K_ST14,
	98	DSP56K_ST15
	99	};
	100
	101
	102	const device_type DSP56156 = &device_creator<dsp56k_device>;
	103
	104
	105	/****************************************************************************
	106	*  Internal Memory Maps
	107	****************************************************************************/
	108	static ADDRESS_MAP_START( dsp56156_program_map, AS_PROGRAM, 16, dsp56k_device )
	109	AM_RANGE(0x0000,0x07ff) AM_READWRITE(program_r, program_w)   /* 1-5 */
	110	//  AM_RANGE(0x2f00,0x2fff) AM_ROM                              /* 1-5 PROM reserved memory.  Is this the right spot for it? */
	111	ADDRESS_MAP_END
	112
	113	static ADDRESS_MAP_START( dsp56156_x_data_map, AS_DATA, 16, dsp56k_device )
	114	AM_RANGE(0x0000,0x07ff) AM_RAM                              /* 1-5 */
	115	AM_RANGE(0xffc0,0xffff) AM_READWRITE(peripheral_register_r, peripheral_register_w)   /* 1-5 On-chip peripheral registers memory mapped in data space */
	116	ADDRESS_MAP_END
	117
	118
	119	dsp56k_device::dsp56k_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	120	: cpu_device(mconfig, DSP56156, "DSP56156", tag, owner, clock, "dsp56156", __FILE__)
	121	, m_program_config("program", ENDIANNESS_LITTLE, 16, 16, -1, ADDRESS_MAP_NAME(dsp56156_program_map))
	122	, m_data_config("data", ENDIANNESS_LITTLE, 16, 16, -1, ADDRESS_MAP_NAME(dsp56156_x_data_map))
	123	{
	124	}
	125
	126
67	127	/***************************************************************************
68	128	Direct Update Handler
69	129	***************************************************************************/
r32086	r32087
71	131	{
72	132	if (address <= (0x07ff<<1))
73	133	{
74		dsp56k_core* cpustate = get_safe_token(&direct.space().device());
75		direct.explicit_configure(0x0000<<1, 0x07ff<<1, (0x07ff<<1) | 1, cpustate->program_ram);
	134	direct.explicit_configure(0x0000<<1, 0x07ff<<1, (0x07ff<<1) | 1, m_dsp56k_core.program_ram);
76	135	return ~0;
77	136	}
78	137
r32086	r32087
89	148	/***************************************************************************
90	149	IRQ HANDLING
91	150	***************************************************************************/
92		static void set_irq_line(dsp56k_core* cpustate, int irqline, int state)
	151	void dsp56k_device::execute_set_input(int irqline, int state)
93	152	{
94	153	//logerror("DSP56k set irq line %d %d\n", irqline, state);
95	154
r32086	r32087
97	156	{
98	157	case DSP56K_IRQ_MODA:
99	158	// TODO: 1-12 Get this triggering right
100		if (irqa_trigger(cpustate))
	159	if (irqa_trigger(&m_dsp56k_core))
101	160	logerror("DSP56k IRQA is set to fire on the \"Negative Edge\".\n");
102	161
103	162	if (state != CLEAR_LINE)
104		cpustate->modA_state = TRUE;
	163	m_dsp56k_core.modA_state = TRUE;
105	164	else
106		cpustate->modA_state = FALSE;
	165	m_dsp56k_core.modA_state = FALSE;
107	166
108		if (cpustate->reset_state != TRUE)
109		dsp56k_add_pending_interrupt(cpustate, "IRQA");
	167	if (m_dsp56k_core.reset_state != TRUE)
	168	dsp56k_add_pending_interrupt(&m_dsp56k_core, "IRQA");
110	169	break;
111	170
112	171	case DSP56K_IRQ_MODB:
113	172	// TODO: 1-12 Get this triggering right
114		if (irqb_trigger(cpustate))
	173	if (irqb_trigger(&m_dsp56k_core))
115	174	logerror("DSP56k IRQB is set to fire on the \"Negative Edge\".\n");
116	175
117	176	if (state != CLEAR_LINE)
118		cpustate->modB_state = TRUE;
	177	m_dsp56k_core.modB_state = TRUE;
119	178	else
120		cpustate->modB_state = FALSE;
	179	m_dsp56k_core.modB_state = FALSE;
121	180
122		if (cpustate->reset_state != TRUE)
123		dsp56k_add_pending_interrupt(cpustate, "IRQB");
	181	if (m_dsp56k_core.reset_state != TRUE)
	182	dsp56k_add_pending_interrupt(&m_dsp56k_core, "IRQB");
124	183	break;
125	184
126	185	case DSP56K_IRQ_MODC:
127	186	if (state != CLEAR_LINE)
128		cpustate->modC_state = TRUE;
	187	m_dsp56k_core.modC_state = TRUE;
129	188	else
130		cpustate->modC_state = FALSE;
	189	m_dsp56k_core.modC_state = FALSE;
131	190
132	191	// TODO : Set bus mode or whatever
133	192	break;
134	193
135	194	case DSP56K_IRQ_RESET:
136	195	if (state != CLEAR_LINE)
137		cpustate->reset_state = TRUE;
	196	m_dsp56k_core.reset_state = TRUE;
138	197	else
139	198	{
140	199	/* If it changes state from asserted to cleared.  Call the reset function. */
141		if (cpustate->reset_state == TRUE)
142		CPU_RESET_NAME(dsp56k)(cpustate->device);
	200	if (m_dsp56k_core.reset_state == TRUE)
	201	device_reset();
143	202
144		cpustate->reset_state = FALSE;
	203	m_dsp56k_core.reset_state = FALSE;
145	204	}
146	205
147	206	// dsp56k_add_pending_interrupt("Hardware RESET");
r32086	r32087
162	221	/***************************************************************************
163	222	INITIALIZATION AND SHUTDOWN
164	223	***************************************************************************/
165		static void agu_init(dsp56k_core* cpustate, device_t *device)
	224	void dsp56k_device::agu_init()
166	225	{
167	226	/* save states - dsp56k_agu members */
168		device->save_item(NAME(cpustate->AGU.r0));
169		device->save_item(NAME(cpustate->AGU.r1));
170		device->save_item(NAME(cpustate->AGU.r2));
171		device->save_item(NAME(cpustate->AGU.r3));
172		device->save_item(NAME(cpustate->AGU.n0));
173		device->save_item(NAME(cpustate->AGU.n1));
174		device->save_item(NAME(cpustate->AGU.n2));
175		device->save_item(NAME(cpustate->AGU.n3));
176		device->save_item(NAME(cpustate->AGU.m0));
177		device->save_item(NAME(cpustate->AGU.m1));
178		device->save_item(NAME(cpustate->AGU.m2));
179		device->save_item(NAME(cpustate->AGU.m3));
180		device->save_item(NAME(cpustate->AGU.temp));
	227	save_item(NAME(m_dsp56k_core.AGU.r0));
	228	save_item(NAME(m_dsp56k_core.AGU.r1));
	229	save_item(NAME(m_dsp56k_core.AGU.r2));
	230	save_item(NAME(m_dsp56k_core.AGU.r3));
	231	save_item(NAME(m_dsp56k_core.AGU.n0));
	232	save_item(NAME(m_dsp56k_core.AGU.n1));
	233	save_item(NAME(m_dsp56k_core.AGU.n2));
	234	save_item(NAME(m_dsp56k_core.AGU.n3));
	235	save_item(NAME(m_dsp56k_core.AGU.m0));
	236	save_item(NAME(m_dsp56k_core.AGU.m1));
	237	save_item(NAME(m_dsp56k_core.AGU.m2));
	238	save_item(NAME(m_dsp56k_core.AGU.m3));
	239	save_item(NAME(m_dsp56k_core.AGU.temp));
181	240	}
182	241
183		static void alu_init(dsp56k_core* cpustate, device_t *device)
	242	void dsp56k_device::alu_init()
184	243	{
185	244	/* save states - dsp56k_alu members */
186		device->save_item(NAME(cpustate->ALU.x));
187		device->save_item(NAME(cpustate->ALU.y));
188		device->save_item(NAME(cpustate->ALU.a));
189		device->save_item(NAME(cpustate->ALU.b));
	245	save_item(NAME(m_dsp56k_core.ALU.x));
	246	save_item(NAME(m_dsp56k_core.ALU.y));
	247	save_item(NAME(m_dsp56k_core.ALU.a));
	248	save_item(NAME(m_dsp56k_core.ALU.b));
190	249	}
191	250
192		static CPU_INIT( dsp56k )
	251	void dsp56k_device::device_start()
193	252	{
194		dsp56k_core* cpustate = get_safe_token(device);
	253	memset(&m_dsp56k_core, 0, sizeof(m_dsp56k_core));
195	254
	255	m_dsp56k_core.device = this;
	256
196	257	/* Call specific module inits */
197		pcu_init(cpustate, device);
198		agu_init(cpustate, device);
199		alu_init(cpustate, device);
	258	pcu_init(&m_dsp56k_core, this);
	259	agu_init();
	260	alu_init();
200	261
201	262	/* HACK - You're not in bootstrap mode upon bootup */
202		cpustate->bootstrap_mode = BOOTSTRAP_OFF;
	263	m_dsp56k_core.bootstrap_mode = BOOTSTRAP_OFF;
203	264
204	265	/* Clear the irq states */
205		cpustate->modA_state = FALSE;
206		cpustate->modB_state = FALSE;
207		cpustate->modC_state = FALSE;
208		cpustate->reset_state = FALSE;
	266	m_dsp56k_core.modA_state = FALSE;
	267	m_dsp56k_core.modB_state = FALSE;
	268	m_dsp56k_core.modC_state = FALSE;
	269	m_dsp56k_core.reset_state = FALSE;
209	270
210	271	/* save states - dsp56k_core members */
211		device->save_item(NAME(cpustate->modA_state));
212		device->save_item(NAME(cpustate->modB_state));
213		device->save_item(NAME(cpustate->modC_state));
214		device->save_item(NAME(cpustate->reset_state));
215		device->save_item(NAME(cpustate->bootstrap_mode));
216		device->save_item(NAME(cpustate->repFlag));
217		device->save_item(NAME(cpustate->repAddr));
218		device->save_item(NAME(cpustate->ppc));
219		device->save_item(NAME(cpustate->op));
220		device->save_item(NAME(cpustate->interrupt_cycles));
	272	save_item(NAME(m_dsp56k_core.modA_state));
	273	save_item(NAME(m_dsp56k_core.modB_state));
	274	save_item(NAME(m_dsp56k_core.modC_state));
	275	save_item(NAME(m_dsp56k_core.reset_state));
	276	save_item(NAME(m_dsp56k_core.bootstrap_mode));
	277	save_item(NAME(m_dsp56k_core.repFlag));
	278	save_item(NAME(m_dsp56k_core.repAddr));
	279	save_item(NAME(m_dsp56k_core.ppc));
	280	save_item(NAME(m_dsp56k_core.op));
	281	save_item(NAME(m_dsp56k_core.interrupt_cycles));
221	282
222	283	/* save states - dsp56k_host_interface members */
223		device->save_item(NAME(cpustate->HI.icr));
224		device->save_item(NAME(cpustate->HI.cvr));
225		device->save_item(NAME(cpustate->HI.isr));
226		device->save_item(NAME(cpustate->HI.ivr));
227		device->save_item(NAME(cpustate->HI.trxh));
228		device->save_item(NAME(cpustate->HI.trxl));
229		device->save_item(NAME(cpustate->HI.bootstrap_offset));
	284	save_item(NAME(m_dsp56k_core.HI.icr));
	285	save_item(NAME(m_dsp56k_core.HI.cvr));
	286	save_item(NAME(m_dsp56k_core.HI.isr));
	287	save_item(NAME(m_dsp56k_core.HI.ivr));
	288	save_item(NAME(m_dsp56k_core.HI.trxh));
	289	save_item(NAME(m_dsp56k_core.HI.trxl));
	290	save_item(NAME(m_dsp56k_core.HI.bootstrap_offset));
230	291
231		device->save_item(NAME(cpustate->peripheral_ram));
232		device->save_item(NAME(cpustate->program_ram));
	292	save_item(NAME(m_dsp56k_core.peripheral_ram));
	293	save_item(NAME(m_dsp56k_core.program_ram));
233	294
234		//cpustate->config = device->static_config();
235		//cpustate->irq_callback = irqcallback;
236		cpustate->device = device;
237		cpustate->program = &device->space(AS_PROGRAM);
238		cpustate->direct = &cpustate->program->direct();
239		cpustate->data = &device->space(AS_DATA);
	295	m_dsp56k_core.program = &space(AS_PROGRAM);
	296	m_dsp56k_core.direct = &m_dsp56k_core.program->direct();
	297	m_dsp56k_core.data = &space(AS_DATA);
240	298
241	299	/* Setup the direct memory handler for this CPU */
242	300	/* NOTE: Be sure to grab this guy and call him if you ever install another direct_update_hander in a driver! */
243		cpustate->program->set_direct_update_handler(direct_update_delegate(FUNC(dsp56k_device::dsp56k_direct_handler), (dsp56k_device*)device));
	301	m_dsp56k_core.program->set_direct_update_handler(direct_update_delegate(FUNC(dsp56k_device::dsp56k_direct_handler), this));
	302
	303	state_add(DSP56K_PC,     "PC", m_dsp56k_core.PCU.pc).formatstr("%04X");
	304	state_add(DSP56K_SR,     "SR", m_dsp56k_core.PCU.sr).formatstr("%04X");
	305	state_add(DSP56K_LC,     "LC", m_dsp56k_core.PCU.lc).formatstr("%04X");
	306	state_add(DSP56K_LA,     "LA", m_dsp56k_core.PCU.la).formatstr("%04X");
	307	state_add(DSP56K_SP,     "SP", m_dsp56k_core.PCU.sp).formatstr("%02X");
	308	state_add(DSP56K_OMR,    "OMR", m_dsp56k_core.PCU.omr).formatstr("%02X");
	309
	310	state_add(DSP56K_X,      "X", m_dsp56k_core.ALU.x.d).mask(0xffffffff).formatstr("%9s");
	311	state_add(DSP56K_Y,      "Y", m_dsp56k_core.ALU.y.d).mask(0xffffffff).formatstr("%9s");
	312
	313	state_add(DSP56K_A,      "A", m_dsp56k_core.ALU.a.q).mask((UINT64)U64(0xffffffffffffffff)).formatstr("%12s"); /* could benefit from a better mask? */
	314	state_add(DSP56K_B,      "B", m_dsp56k_core.ALU.b.q).mask((UINT64)U64(0xffffffffffffffff)).formatstr("%12s"); /* could benefit from a better mask? */
	315
	316	state_add(DSP56K_R0,     "R0", m_dsp56k_core.AGU.r0).formatstr("%04X");
	317	state_add(DSP56K_R1,     "R1", m_dsp56k_core.AGU.r1).formatstr("%04X");
	318	state_add(DSP56K_R2,     "R2", m_dsp56k_core.AGU.r2).formatstr("%04X");
	319	state_add(DSP56K_R3,     "R3", m_dsp56k_core.AGU.r3).formatstr("%04X");
	320
	321	state_add(DSP56K_N0,     "N0", m_dsp56k_core.AGU.n0).formatstr("%04X");
	322	state_add(DSP56K_N1,     "N1", m_dsp56k_core.AGU.n1).formatstr("%04X");
	323	state_add(DSP56K_N2,     "N2", m_dsp56k_core.AGU.n2).formatstr("%04X");
	324	state_add(DSP56K_N3,     "N3", m_dsp56k_core.AGU.n3).formatstr("%04X");
	325
	326	state_add(DSP56K_M0,     "M0", m_dsp56k_core.AGU.m0).formatstr("%04X");
	327	state_add(DSP56K_M1,     "M1", m_dsp56k_core.AGU.m1).formatstr("%04X");
	328	state_add(DSP56K_M2,     "M2", m_dsp56k_core.AGU.m2).formatstr("%04X");
	329	state_add(DSP56K_M3,     "M3", m_dsp56k_core.AGU.m3).formatstr("%04X");
	330
	331	state_add(DSP56K_TEMP,   "TMP", m_dsp56k_core.AGU.temp).formatstr("%04X").noshow();
	332	//state_add(DSP56K_STATUS, "STS", STATUS).formatstr("%02X");
	333
	334	state_add(DSP56K_ST0,    "ST0", m_dsp56k_core.PCU.ss[0].d).formatstr("%08X");
	335	state_add(DSP56K_ST1,    "ST1", m_dsp56k_core.PCU.ss[1].d).formatstr("%08X");
	336	state_add(DSP56K_ST2,    "ST2", m_dsp56k_core.PCU.ss[2].d).formatstr("%08X");
	337	state_add(DSP56K_ST3,    "ST3", m_dsp56k_core.PCU.ss[3].d).formatstr("%08X");
	338	state_add(DSP56K_ST4,    "ST4", m_dsp56k_core.PCU.ss[4].d).formatstr("%08X");
	339	state_add(DSP56K_ST5,    "ST5", m_dsp56k_core.PCU.ss[5].d).formatstr("%08X");
	340	state_add(DSP56K_ST6,    "ST6", m_dsp56k_core.PCU.ss[6].d).formatstr("%08X");
	341	state_add(DSP56K_ST7,    "ST7", m_dsp56k_core.PCU.ss[7].d).formatstr("%08X");
	342	state_add(DSP56K_ST8,    "ST8", m_dsp56k_core.PCU.ss[8].d).formatstr("%08X");
	343	state_add(DSP56K_ST9,    "ST9", m_dsp56k_core.PCU.ss[9].d).formatstr("%08X");
	344	state_add(DSP56K_ST10,   "ST10", m_dsp56k_core.PCU.ss[10].d).formatstr("%08X");
	345	state_add(DSP56K_ST11,   "ST11", m_dsp56k_core.PCU.ss[11].d).formatstr("%08X");
	346	state_add(DSP56K_ST12,   "ST12", m_dsp56k_core.PCU.ss[12].d).formatstr("%08X");
	347	state_add(DSP56K_ST13,   "ST13", m_dsp56k_core.PCU.ss[13].d).formatstr("%08X");
	348	state_add(DSP56K_ST14,   "ST14", m_dsp56k_core.PCU.ss[14].d).formatstr("%08X");
	349	state_add(DSP56K_ST15,   "ST15", m_dsp56k_core.PCU.ss[15].d).formatstr("%08X");
	350
	351	state_add(STATE_GENPC, "GENPC", m_dsp56k_core.PCU.pc).noshow();
	352	state_add(STATE_GENSP, "GENSP", m_dsp56k_core.PCU.sp).noshow();
	353	state_add(STATE_GENPCBASE, "GENPCBASE", m_dsp56k_core.ppc).noshow();
	354	state_add(STATE_GENFLAGS, "GENFLAGS", m_dsp56k_core.PCU.sr).formatstr("%14s").noshow();
	355
	356	m_icountptr = &m_dsp56k_core.icount;
244	357	}
245	358
246	359
	360	void dsp56k_device::state_string_export(const device_state_entry &entry, astring &string)
	361	{
	362	dsp56k_core *cpustate = &m_dsp56k_core;
	363
	364	switch (entry.index())
	365	{
	366	case STATE_GENFLAGS:
	367	string.printf("%s%s %s%s%s%s%s%s%s%s %s%s",
	368	/* Status Register */
	369	LF_bit(cpustate) ? "L" : ".",
	370	FV_bit(cpustate) ? "F" : ".",
	371
	372	S_bit(cpustate) ? "S" : ".",
	373	L_bit(cpustate) ? "L" : ".",
	374	E_bit(cpustate) ? "E" : ".",
	375	U_bit(cpustate) ? "U" : ".",
	376	N_bit(cpustate) ? "N" : ".",
	377	Z_bit(cpustate) ? "Z" : ".",
	378	V_bit(cpustate) ? "V" : ".",
	379	C_bit(cpustate) ? "C" : ".",
	380
	381	/* Stack Pointer */
	382	UF_bit(cpustate) ? "U" : ".",
	383	SE_bit(cpustate) ? "S" : ".");
	384	break;
	385
	386	case DSP56K_X:
	387	string.printf("%04x %04x", X1, X0);
	388	break;
	389
	390	case DSP56K_Y:
	391	string.printf("%04x %04x", Y1, Y0);
	392	break;
	393
	394	case DSP56K_A:
	395	string.printf("%02x %04x %04x", A2,A1,A0);
	396	break;
	397
	398	case DSP56K_B:
	399	string.printf("%02x %04x %04x", B2,B1,B0);
	400	break;
	401	}
	402	}
	403
247	404	/***************************************************************************
248	405	RESET BEHAVIOR
249	406	***************************************************************************/
r32086	r32087
276	433	B = 0x0000000000;
277	434	}
278	435
279		static CPU_RESET( dsp56k )
	436	void dsp56k_device::device_reset()
280	437	{
281		dsp56k_core* cpustate = get_safe_token(device);
282	438	logerror("Dsp56k reset\n");
283	439
284		cpustate->interrupt_cycles = 0;
285		cpustate->ppc = 0x0000;
	440	m_dsp56k_core.interrupt_cycles = 0;
	441	m_dsp56k_core.ppc = 0x0000;
286	442
287		cpustate->repFlag = 0;
288		cpustate->repAddr = 0x0000;
	443	m_dsp56k_core.repFlag = 0;
	444	m_dsp56k_core.repAddr = 0x0000;
289	445
290		pcu_reset(cpustate);
291		mem_reset(cpustate);
292		agu_reset(cpustate);
293		alu_reset(cpustate);
	446	pcu_reset(&m_dsp56k_core);
	447	mem_reset(&m_dsp56k_core);
	448	agu_reset(&m_dsp56k_core);
	449	alu_reset(&m_dsp56k_core);
294	450
295	451	/* HACK - Put a jump to 0x0000 at 0x0000 - this keeps the CPU locked to the instruction at address 0x0000 */
296		cpustate->program->write_word(0x0000, 0x0124);
	452	m_dsp56k_core.program->write_word(0x0000, 0x0124);
297	453	}
298	454
299	455
300		static CPU_EXIT( dsp56k )
301		{
302		}
303	456
304
305
306	457	/***************************************************************************
307	458	CORE INCLUDE
308	459	***************************************************************************/
r32086	r32087
330	481	return 4;
331	482	}
332	483
333		static CPU_EXECUTE( dsp56k )
	484	void dsp56k_device::execute_run()
334	485	{
335		dsp56k_core* cpustate = get_safe_token(device);
336
337	486	/* If reset line is asserted, do nothing */
338		if (cpustate->reset_state)
	487	if (m_dsp56k_core.reset_state)
339	488	{
340		cpustate->icount = 0;
	489	m_dsp56k_core.icount = 0;
341	490	return;
342	491	}
343	492
344	493	/* HACK - if you're in bootstrap mode, simply pretend you ate up all your cycles waiting for data. */
345		if (cpustate->bootstrap_mode != BOOTSTRAP_OFF)
	494	if (m_dsp56k_core.bootstrap_mode != BOOTSTRAP_OFF)
346	495	{
347		cpustate->icount = 0;
	496	m_dsp56k_core.icount = 0;
348	497	return;
349	498	}
350	499
351		//cpustate->icount -= cpustate->interrupt_cycles;
352		//cpustate->interrupt_cycles = 0;
	500	//m_dsp56k_core.icount -= m_dsp56k_core.interrupt_cycles;
	501	//m_dsp56k_core.interrupt_cycles = 0;
353	502
354		while(cpustate->icount > 0)
	503	while(m_dsp56k_core.icount > 0)
355	504	{
356		execute_one(cpustate);
357		if (0) cpustate->icount -= execute_one_new(cpustate);
358		pcu_service_interrupts(cpustate);   // TODO: Is it incorrect to service after each instruction?
	505	execute_one(&m_dsp56k_core);
	506	if (0) m_dsp56k_core.icount -= execute_one_new(&m_dsp56k_core);
	507	pcu_service_interrupts(&m_dsp56k_core);   // TODO: Is it incorrect to service after each instruction?
359	508	}
360	509	}
361	510
362	511
363
364		/***************************************************************************
365		DISASSEMBLY HOOK
366		***************************************************************************/
367		extern CPU_DISASSEMBLE( dsp56k );
368
369
370		/****************************************************************************
371		*  Internal Memory Maps
372		****************************************************************************/
373		static ADDRESS_MAP_START( dsp56156_program_map, AS_PROGRAM, 16, dsp56k_device )
374		AM_RANGE(0x0000,0x07ff) AM_READWRITE(program_r, program_w)   /* 1-5 */
375		//  AM_RANGE(0x2f00,0x2fff) AM_ROM                              /* 1-5 PROM reserved memory.  Is this the right spot for it? */
376		ADDRESS_MAP_END
377
378		static ADDRESS_MAP_START( dsp56156_x_data_map, AS_DATA, 16, dsp56k_device )
379		AM_RANGE(0x0000,0x07ff) AM_RAM                              /* 1-5 */
380		AM_RANGE(0xffc0,0xffff) AM_READWRITE(peripheral_register_r, peripheral_register_w)   /* 1-5 On-chip peripheral registers memory mapped in data space */
381		ADDRESS_MAP_END
382
383
384		/**************************************************************************
385		* Generic set_info/get_info
386		**************************************************************************/
387		enum
	512	offs_t dsp56k_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
388	513	{
389		// PCU
390		DSP56K_PC=1,
391		DSP56K_SR,
392		DSP56K_LC,
393		DSP56K_LA,
394		DSP56K_SP,
395		DSP56K_OMR,
396
397		// ALU
398		DSP56K_X, DSP56K_Y,
399		DSP56K_A, DSP56K_B,
400
401		// AGU
402		DSP56K_R0,DSP56K_R1,DSP56K_R2,DSP56K_R3,
403		DSP56K_N0,DSP56K_N1,DSP56K_N2,DSP56K_N3,
404		DSP56K_M0,DSP56K_M1,DSP56K_M2,DSP56K_M3,
405		DSP56K_TEMP,
406		DSP56K_STATUS,
407
408		// CPU STACK
409		DSP56K_ST0,
410		DSP56K_ST1,
411		DSP56K_ST2,
412		DSP56K_ST3,
413		DSP56K_ST4,
414		DSP56K_ST5,
415		DSP56K_ST6,
416		DSP56K_ST7,
417		DSP56K_ST8,
418		DSP56K_ST9,
419		DSP56K_ST10,
420		DSP56K_ST11,
421		DSP56K_ST12,
422		DSP56K_ST13,
423		DSP56K_ST14,
424		DSP56K_ST15
425		};
426
427		static CPU_SET_INFO( dsp56k )
428		{
429		dsp56k_core* cpustate = get_safe_token(device);
430
431		switch (state)
432		{
433		case CPUINFO_INT_INPUT_STATE + DSP56K_IRQ_MODA:   set_irq_line(cpustate, DSP56K_IRQ_MODA, info->i);  break;
434		case CPUINFO_INT_INPUT_STATE + DSP56K_IRQ_MODB:   set_irq_line(cpustate, DSP56K_IRQ_MODB, info->i);  break;
435		case CPUINFO_INT_INPUT_STATE + DSP56K_IRQ_MODC:   set_irq_line(cpustate, DSP56K_IRQ_MODC, info->i);  break;
436		case CPUINFO_INT_INPUT_STATE + DSP56K_IRQ_RESET:  set_irq_line(cpustate, DSP56K_IRQ_RESET, info->i); break;
437
438		case CPUINFO_INT_PC:
439		case CPUINFO_INT_REGISTER + DSP56K_PC:          PC  = info->i & 0xffff;                 break;
440
441		case CPUINFO_INT_REGISTER + DSP56K_SR:          SR  = info->i & 0xffff;                 break;
442		case CPUINFO_INT_REGISTER + DSP56K_LC:          LC  = info->i & 0xffff;                 break;
443		case CPUINFO_INT_REGISTER + DSP56K_LA:          LA  = info->i & 0xffff;                 break;
444
445		case CPUINFO_INT_SP:
446		case CPUINFO_INT_REGISTER + DSP56K_SP:          SP  = info->i & 0xff;                   break;
447
448		case CPUINFO_INT_REGISTER + DSP56K_OMR:         OMR = info->i & 0xff;                   break;
449
450		case CPUINFO_INT_REGISTER + DSP56K_X:           X   = info->i & 0xffffffff;             break;
451		case CPUINFO_INT_REGISTER + DSP56K_Y:           Y   = info->i & 0xffffffff;             break;
452
453		case CPUINFO_INT_REGISTER + DSP56K_A:           A   = info->i & (UINT64)U64(0xffffffffffffffff); break; /* could benefit from a better mask? */
454		case CPUINFO_INT_REGISTER + DSP56K_B:           B   = info->i & (UINT64)U64(0xffffffffffffffff); break; /* could benefit from a better mask? */
455
456		case CPUINFO_INT_REGISTER + DSP56K_R0:          R0  = info->i & 0xffff;                 break;
457		case CPUINFO_INT_REGISTER + DSP56K_R1:          R1  = info->i & 0xffff;                 break;
458		case CPUINFO_INT_REGISTER + DSP56K_R2:          R2  = info->i & 0xffff;                 break;
459		case CPUINFO_INT_REGISTER + DSP56K_R3:          R3  = info->i & 0xffff;                 break;
460
461		case CPUINFO_INT_REGISTER + DSP56K_N0:          N0  = info->i & 0xffff;                 break;
462		case CPUINFO_INT_REGISTER + DSP56K_N1:          N1  = info->i & 0xffff;                 break;
463		case CPUINFO_INT_REGISTER + DSP56K_N2:          N2  = info->i & 0xffff;                 break;
464		case CPUINFO_INT_REGISTER + DSP56K_N3:          N3  = info->i & 0xffff;                 break;
465
466		case CPUINFO_INT_REGISTER + DSP56K_M0:          M0  = info->i & 0xffff;                 break;
467		case CPUINFO_INT_REGISTER + DSP56K_M1:          M1  = info->i & 0xffff;                 break;
468		case CPUINFO_INT_REGISTER + DSP56K_M2:          M2  = info->i & 0xffff;                 break;
469		case CPUINFO_INT_REGISTER + DSP56K_M3:          M3  = info->i & 0xffff;                 break;
470
471		/*  case CPUINFO_INT_REGISTER + DSP56K_TEMP:        TEMP   = info->i & 0xffff;          break;  */
472		/*  case CPUINFO_INT_REGISTER + DSP56K_STATUS:      STATUS = info->i & 0xff;            break;  */
473
474		/* The CPU stack */
475		case CPUINFO_INT_REGISTER + DSP56K_ST0:         ST0 = info->i  & 0xffffffff;            break;
476		case CPUINFO_INT_REGISTER + DSP56K_ST1:         ST1 = info->i  & 0xffffffff;            break;
477		case CPUINFO_INT_REGISTER + DSP56K_ST2:         ST2 = info->i  & 0xffffffff;            break;
478		case CPUINFO_INT_REGISTER + DSP56K_ST3:         ST3 = info->i  & 0xffffffff;            break;
479		case CPUINFO_INT_REGISTER + DSP56K_ST4:         ST4 = info->i  & 0xffffffff;            break;
480		case CPUINFO_INT_REGISTER + DSP56K_ST5:         ST5 = info->i  & 0xffffffff;            break;
481		case CPUINFO_INT_REGISTER + DSP56K_ST6:         ST6 = info->i  & 0xffffffff;            break;
482		case CPUINFO_INT_REGISTER + DSP56K_ST7:         ST7 = info->i  & 0xffffffff;            break;
483		case CPUINFO_INT_REGISTER + DSP56K_ST8:         ST8 = info->i  & 0xffffffff;            break;
484		case CPUINFO_INT_REGISTER + DSP56K_ST9:         ST9 = info->i  & 0xffffffff;            break;
485		case CPUINFO_INT_REGISTER + DSP56K_ST10:        ST10 = info->i & 0xffffffff;            break;
486		case CPUINFO_INT_REGISTER + DSP56K_ST11:        ST11 = info->i & 0xffffffff;            break;
487		case CPUINFO_INT_REGISTER + DSP56K_ST12:        ST12 = info->i & 0xffffffff;            break;
488		case CPUINFO_INT_REGISTER + DSP56K_ST13:        ST13 = info->i & 0xffffffff;            break;
489		case CPUINFO_INT_REGISTER + DSP56K_ST14:        ST14 = info->i & 0xffffffff;            break;
490		case CPUINFO_INT_REGISTER + DSP56K_ST15:        ST15 = info->i & 0xffffffff;            break;
491		}
	514	extern CPU_DISASSEMBLE( dsp56k );
	515	return CPU_DISASSEMBLE_NAME(dsp56k)(this, buffer, pc, oprom, opram, options);
492	516	}
493	517
494
495		CPU_GET_INFO( dsp56k )
496		{
497		dsp56k_core* cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
498
499		switch (state)
500		{
501		/* --- the following bits of info are returned as 64-bit signed integers --- */
502		case CPUINFO_INT_CONTEXT_SIZE:                  info->i = sizeof(dsp56k_core);          break;
503		case CPUINFO_INT_INPUT_LINES:                   info->i = 4;                            break;
504		case CPUINFO_INT_DEFAULT_IRQ_VECTOR:            info->i = 0x0000;                       break;
505		case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_LITTLE;            break;
506		case CPUINFO_INT_CLOCK_MULTIPLIER:              info->i = 1;                            break;
507		case CPUINFO_INT_CLOCK_DIVIDER:                 info->i = 2;                            break;
508		case CPUINFO_INT_MIN_INSTRUCTION_BYTES:         info->i = 2;                            break;
509		case CPUINFO_INT_MAX_INSTRUCTION_BYTES:         info->i = 4;                            break;
510		case CPUINFO_INT_MIN_CYCLES:                    info->i = 1;    // ?                    break;
511		case CPUINFO_INT_MAX_CYCLES:                    info->i = 8;    // ?                    break;
512
513		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:    info->i = 16;                   break;
514		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16;                  break;
515		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = -1;                  break;
516		case CPUINFO_INT_DATABUS_WIDTH + AS_DATA:   info->i = 16;                   break;
517		case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA:   info->i = 16;                   break;
518		case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA:   info->i = -1;                   break;
519		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:     info->i = 0;                    break;
520		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO:     info->i = 0;                    break;
521		case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO:     info->i = 0;                    break;
522
523		case CPUINFO_INT_INPUT_STATE + DSP56K_IRQ_MODA: info->i = DSP56K_IRQ_MODA;              break;
524		case CPUINFO_INT_INPUT_STATE + DSP56K_IRQ_MODB: info->i = DSP56K_IRQ_MODB;              break;
525		case CPUINFO_INT_INPUT_STATE + DSP56K_IRQ_MODC: info->i = DSP56K_IRQ_MODC;              break;
526
527		case CPUINFO_INT_PC:
528		case CPUINFO_INT_REGISTER + DSP56K_PC:          info->i = PC;                           break;
529		case CPUINFO_INT_PREVIOUSPC:                    info->i = cpustate->ppc;                break;
530
531		case CPUINFO_INT_REGISTER + DSP56K_SR:          info->i = SR;                           break;
532		case CPUINFO_INT_REGISTER + DSP56K_LC:          info->i = LC;                           break;
533		case CPUINFO_INT_REGISTER + DSP56K_LA:          info->i = LA;                           break;
534
535		case CPUINFO_INT_SP:
536		case CPUINFO_INT_REGISTER + DSP56K_SP:          info->i = SP;                           break;
537
538		case CPUINFO_INT_REGISTER + DSP56K_OMR:         info->i = OMR;                          break;
539
540		case CPUINFO_INT_REGISTER + DSP56K_X:           info->i = X;                            break;
541		case CPUINFO_INT_REGISTER + DSP56K_Y:           info->i = Y;                            break;
542
543		case CPUINFO_INT_REGISTER + DSP56K_A:           info->i = A;                            break;
544		case CPUINFO_INT_REGISTER + DSP56K_B:           info->i = B;                            break;
545
546		case CPUINFO_INT_REGISTER + DSP56K_R0:          info->i = R0;                           break;
547		case CPUINFO_INT_REGISTER + DSP56K_R1:          info->i = R1;                           break;
548		case CPUINFO_INT_REGISTER + DSP56K_R2:          info->i = R2;                           break;
549		case CPUINFO_INT_REGISTER + DSP56K_R3:          info->i = R3;                           break;
550
551		case CPUINFO_INT_REGISTER + DSP56K_N0:          info->i = N0;                           break;
552		case CPUINFO_INT_REGISTER + DSP56K_N1:          info->i = N1;                           break;
553		case CPUINFO_INT_REGISTER + DSP56K_N2:          info->i = N2;                           break;
554		case CPUINFO_INT_REGISTER + DSP56K_N3:          info->i = N3;                           break;
555
556		case CPUINFO_INT_REGISTER + DSP56K_M0:          info->i = M0;                           break;
557		case CPUINFO_INT_REGISTER + DSP56K_M1:          info->i = M1;                           break;
558		case CPUINFO_INT_REGISTER + DSP56K_M2:          info->i = M2;                           break;
559		case CPUINFO_INT_REGISTER + DSP56K_M3:          info->i = M3;                           break;
560
561		/* case CPUINFO_INT_REGISTER + DSP56K_TEMP:    info->i = TEMP;                         break;  */
562		/* case CPUINFO_INT_REGISTER + DSP56K_STATUS:  info->i = STATUS;                       break;  */
563
564		/* The CPU stack */
565		case CPUINFO_INT_REGISTER + DSP56K_ST0:         info->i = ST0;                          break;
566		case CPUINFO_INT_REGISTER + DSP56K_ST1:         info->i = ST1;                          break;
567		case CPUINFO_INT_REGISTER + DSP56K_ST2:         info->i = ST2;                          break;
568		case CPUINFO_INT_REGISTER + DSP56K_ST3:         info->i = ST3;                          break;
569		case CPUINFO_INT_REGISTER + DSP56K_ST4:         info->i = ST4;                          break;
570		case CPUINFO_INT_REGISTER + DSP56K_ST5:         info->i = ST5;                          break;
571		case CPUINFO_INT_REGISTER + DSP56K_ST6:         info->i = ST6;                          break;
572		case CPUINFO_INT_REGISTER + DSP56K_ST7:         info->i = ST7;                          break;
573		case CPUINFO_INT_REGISTER + DSP56K_ST8:         info->i = ST8;                          break;
574		case CPUINFO_INT_REGISTER + DSP56K_ST9:         info->i = ST9;                          break;
575		case CPUINFO_INT_REGISTER + DSP56K_ST10:        info->i = ST10;                         break;
576		case CPUINFO_INT_REGISTER + DSP56K_ST11:        info->i = ST11;                         break;
577		case CPUINFO_INT_REGISTER + DSP56K_ST12:        info->i = ST12;                         break;
578		case CPUINFO_INT_REGISTER + DSP56K_ST13:        info->i = ST13;                         break;
579		case CPUINFO_INT_REGISTER + DSP56K_ST14:        info->i = ST14;                         break;
580		case CPUINFO_INT_REGISTER + DSP56K_ST15:        info->i = ST15;                         break;
581
582		/* --- the following bits of info are returned as pointers to data or functions --- */
583		case CPUINFO_FCT_SET_INFO:                      info->setinfo = CPU_SET_INFO_NAME(dsp56k); break;
584		case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(dsp56k);     break;
585		case CPUINFO_FCT_RESET:                         info->reset = CPU_RESET_NAME(dsp56k);   break;
586		case CPUINFO_FCT_EXIT:                          info->exit = CPU_EXIT_NAME(dsp56k);     break;
587		case CPUINFO_FCT_EXECUTE:                       info->execute = CPU_EXECUTE_NAME(dsp56k); break;
588		case CPUINFO_FCT_BURN:                          info->burn = NULL;                      break;
589		case CPUINFO_FCT_DISASSEMBLE:                   info->disassemble = CPU_DISASSEMBLE_NAME(dsp56k); break;
590		case CPUINFO_FCT_DEBUG_INIT:                    info->debug_init = NULL;                break;
591		case CPUINFO_FCT_TRANSLATE:                     info->translate = NULL;                 break;
592		case CPUINFO_FCT_READ:                          info->read = NULL;                      break;
593		case CPUINFO_FCT_WRITE:                         info->write = NULL;                     break;
594		case CPUINFO_FCT_READOP:                        info->readop = NULL;                    break;
595		case CPUINFO_PTR_INSTRUCTION_COUNTER:           info->icount = &cpustate->icount;       break;
596		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA:
597		info->internal_map16 = ADDRESS_MAP_NAME(dsp56156_x_data_map);                       break;
598		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM:
599		info->internal_map16 = ADDRESS_MAP_NAME(dsp56156_program_map);                      break;
600
601		/* --- the following bits of info are returned as NULL-terminated strings --- */
602		case CPUINFO_STR_NAME:                          strcpy(info->s, "DSP56156");            break;
603		case CPUINFO_STR_SHORTNAME:                          strcpy(info->s, "dsp56156");            break;
604		case CPUINFO_STR_FAMILY:                        strcpy(info->s, "Motorola DSP56156");   break;
605		case CPUINFO_STR_VERSION:                       strcpy(info->s, "0.1");                 break;
606		case CPUINFO_STR_SOURCE_FILE:                   strcpy(info->s, __FILE__);              break;
607		case CPUINFO_STR_CREDITS:                       strcpy(info->s, "Andrew Gardner");      break;
608
609		case CPUINFO_STR_FLAGS:
610		sprintf(info->s, "%s%s %s%s%s%s%s%s%s%s %s%s",
611		/* Status Register */
612		LF_bit(cpustate) ? "L" : ".",
613		FV_bit(cpustate) ? "F" : ".",
614
615		S_bit(cpustate) ? "S" : ".",
616		L_bit(cpustate) ? "L" : ".",
617		E_bit(cpustate) ? "E" : ".",
618		U_bit(cpustate) ? "U" : ".",
619		N_bit(cpustate) ? "N" : ".",
620		Z_bit(cpustate) ? "Z" : ".",
621		V_bit(cpustate) ? "V" : ".",
622		C_bit(cpustate) ? "C" : ".",
623
624		/* Stack Pointer */
625		UF_bit(cpustate) ? "U" : ".",
626		SE_bit(cpustate) ? "S" : ".");
627		break;
628
629		case CPUINFO_STR_REGISTER + DSP56K_PC:          sprintf(info->s, "PC : %04x", PC);      break;
630		case CPUINFO_STR_REGISTER + DSP56K_SR:          sprintf(info->s, "SR : %04x", SR);      break;
631		case CPUINFO_STR_REGISTER + DSP56K_LC:          sprintf(info->s, "LC : %04x", LC);      break;
632		case CPUINFO_STR_REGISTER + DSP56K_LA:          sprintf(info->s, "LA : %04x", LA);      break;
633		case CPUINFO_STR_REGISTER + DSP56K_SP:          sprintf(info->s, "SP : %02x", SP);      break;
634		case CPUINFO_STR_REGISTER + DSP56K_OMR:         sprintf(info->s, "OMR: %02x", OMR);     break;
635
636		case CPUINFO_STR_REGISTER + DSP56K_X:           sprintf(info->s, "X  : %04x %04x", X1, X0); break;
637		case CPUINFO_STR_REGISTER + DSP56K_Y:           sprintf(info->s, "Y  : %04x %04x", Y1, Y0); break;
638
639		case CPUINFO_STR_REGISTER + DSP56K_A:           sprintf(info->s, "A  : %02x %04x %04x", A2,A1,A0); break;
640		case CPUINFO_STR_REGISTER + DSP56K_B:           sprintf(info->s, "B  : %02x %04x %04x", B2,B1,B0); break;
641
642		case CPUINFO_STR_REGISTER + DSP56K_R0:          sprintf(info->s, "R0 : %04x", R0);      break;
643		case CPUINFO_STR_REGISTER + DSP56K_R1:          sprintf(info->s, "R1 : %04x", R1);      break;
644		case CPUINFO_STR_REGISTER + DSP56K_R2:          sprintf(info->s, "R2 : %04x", R2);      break;
645		case CPUINFO_STR_REGISTER + DSP56K_R3:          sprintf(info->s, "R3 : %04x", R3);      break;
646
647		case CPUINFO_STR_REGISTER + DSP56K_N0:          sprintf(info->s, "N0 : %04x", N0);      break;
648		case CPUINFO_STR_REGISTER + DSP56K_N1:          sprintf(info->s, "N1 : %04x", N1);      break;
649		case CPUINFO_STR_REGISTER + DSP56K_N2:          sprintf(info->s, "N2 : %04x", N2);      break;
650		case CPUINFO_STR_REGISTER + DSP56K_N3:          sprintf(info->s, "N3 : %04x", N3);      break;
651
652		case CPUINFO_STR_REGISTER + DSP56K_M0:          sprintf(info->s, "M0 : %04x", M0);      break;
653		case CPUINFO_STR_REGISTER + DSP56K_M1:          sprintf(info->s, "M1 : %04x", M1);      break;
654		case CPUINFO_STR_REGISTER + DSP56K_M2:          sprintf(info->s, "M2 : %04x", M2);      break;
655		case CPUINFO_STR_REGISTER + DSP56K_M3:          sprintf(info->s, "M3 : %04x", M3);      break;
656
657		/*  case CPUINFO_STR_REGISTER + DSP56K_TEMP:    sprintf(info->s, "TMP: %04x", TEMP);    break;  */
658		/*  case CPUINFO_STR_REGISTER + DSP56K_STATUS:  sprintf(info->s, "STS: %02x", STATUS);  break;  */
659
660		/* The CPU stack */
661		case CPUINFO_STR_REGISTER + DSP56K_ST0:         sprintf(info->s, "ST0 : %08x", ST0);    break;
662		case CPUINFO_STR_REGISTER + DSP56K_ST1:         sprintf(info->s, "ST1 : %08x", ST1);    break;
663		case CPUINFO_STR_REGISTER + DSP56K_ST2:         sprintf(info->s, "ST2 : %08x", ST2);    break;
664		case CPUINFO_STR_REGISTER + DSP56K_ST3:         sprintf(info->s, "ST3 : %08x", ST3);    break;
665		case CPUINFO_STR_REGISTER + DSP56K_ST4:         sprintf(info->s, "ST4 : %08x", ST4);    break;
666		case CPUINFO_STR_REGISTER + DSP56K_ST5:         sprintf(info->s, "ST5 : %08x", ST5);    break;
667		case CPUINFO_STR_REGISTER + DSP56K_ST6:         sprintf(info->s, "ST6 : %08x", ST6);    break;
668		case CPUINFO_STR_REGISTER + DSP56K_ST7:         sprintf(info->s, "ST7 : %08x", ST7);    break;
669		case CPUINFO_STR_REGISTER + DSP56K_ST8:         sprintf(info->s, "ST8 : %08x", ST8);    break;
670		case CPUINFO_STR_REGISTER + DSP56K_ST9:         sprintf(info->s, "ST9 : %08x", ST9);    break;
671		case CPUINFO_STR_REGISTER + DSP56K_ST10:        sprintf(info->s, "ST10: %08x", ST10);   break;
672		case CPUINFO_STR_REGISTER + DSP56K_ST11:        sprintf(info->s, "ST11: %08x", ST11);   break;
673		case CPUINFO_STR_REGISTER + DSP56K_ST12:        sprintf(info->s, "ST12: %08x", ST12);   break;
674		case CPUINFO_STR_REGISTER + DSP56K_ST13:        sprintf(info->s, "ST13: %08x", ST13);   break;
675		case CPUINFO_STR_REGISTER + DSP56K_ST14:        sprintf(info->s, "ST14: %08x", ST14);   break;
676		case CPUINFO_STR_REGISTER + DSP56K_ST15:        sprintf(info->s, "ST15: %08x", ST15);   break;
677		}
678		}
679
680		DEFINE_LEGACY_CPU_DEVICE(DSP56156, dsp56k);

trunk/src/emu/cpu/dsp56k/dsp56k.h

r32086	r32087
22	22	#define DSP56K_IRQ_MODC  2
23	23	#define DSP56K_IRQ_RESET 3  /* Is this needed? */
24	24
25		// Needed for MAME
26		CPU_GET_INFO( dsp56k );
27	25
28		class dsp56k_device : public legacy_cpu_device
29		{
30		public:
31		dsp56k_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock);
32
33		DECLARE_DIRECT_UPDATE_MEMBER(dsp56k_direct_handler);
34		DECLARE_READ16_MEMBER( program_r );
35		DECLARE_WRITE16_MEMBER( program_w );
36		DECLARE_READ16_MEMBER( peripheral_register_r );
37		DECLARE_WRITE16_MEMBER( peripheral_register_w );
38		};
39
40		extern const device_type DSP56156;
41
42
43	26	/***************************************************************************
44	27	STRUCTURES & TYPEDEFS
45	28	***************************************************************************/
r32086	r32087
204	187	UINT32          op;
205	188	int             interrupt_cycles;
206	189	void            (*output_pins_changed)(UINT32 pins);
207		legacy_cpu_device *device;
	190	cpu_device *device;
208	191	address_space *program;
209	192	direct_read_data *direct;
210	193	address_space *data;
r32086	r32087
214	197	};
215	198
216	199
217		INLINE dsp56k_core *get_safe_token(device_t *device)
	200	class dsp56k_device : public cpu_device
218	201	{
219		assert(device != NULL);
220		assert(device->type() == DSP56156);
221		return (dsp56k_core *)downcast<legacy_cpu_device *>(device)->token();
222		}
	202	public:
	203	dsp56k_device(const machine_config &mconfig, const char *_tag, device_t *_owner, UINT32 _clock);
223	204
	205	DECLARE_DIRECT_UPDATE_MEMBER(dsp56k_direct_handler);
	206	DECLARE_READ16_MEMBER( program_r );
	207	DECLARE_WRITE16_MEMBER( program_w );
	208	DECLARE_READ16_MEMBER( peripheral_register_r );
	209	DECLARE_WRITE16_MEMBER( peripheral_register_w );
224	210
225		/***************************************************************************
226		PUBLIC FUNCTIONS - ACCESSIBLE TO DRIVERS
227		***************************************************************************/
228		void  dsp56k_host_interface_write(device_t* device, UINT8 offset, UINT8 data);
229		UINT8 dsp56k_host_interface_read(device_t* device, UINT8 offset);
	211	void  host_interface_write(UINT8 offset, UINT8 data);
	212	UINT8 host_interface_read(UINT8 offset);
230	213
231		UINT16 dsp56k_get_peripheral_memory(device_t* device, UINT16 addr);
	214	UINT16 get_peripheral_memory(UINT16 addr);
232	215
	216	protected:
	217	// device-level overrides
	218	virtual void device_start();
	219	virtual void device_reset();
	220
	221	// device_execute_interface overrides
	222	virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 2 - 1) / 2; }
	223	virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 2); }
	224	virtual UINT32 execute_min_cycles() const { return 1; }
	225	virtual UINT32 execute_max_cycles() const { return 8; }
	226	virtual UINT32 execute_input_lines() const { return 4; }
	227	virtual UINT32 execute_default_irq_vector() const { return 0; }
	228	virtual void execute_run();
	229	virtual void execute_set_input(int inputnum, int state);
	230
	231	// device_memory_interface overrides
	232	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ((spacenum == AS_DATA) ? &m_data_config : NULL ); }
	233
	234	// device_state_interface overrides
	235	void state_string_export(const device_state_entry &entry, astring &string);
	236
	237	// device_disasm_interface overrides
	238	virtual UINT32 disasm_min_opcode_bytes() const { return 2; }
	239	virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
	240	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
	241
	242	private:
	243	address_space_config m_program_config;
	244	address_space_config m_data_config;
	245
	246	dsp56k_core m_dsp56k_core;
	247
	248	void agu_init();
	249	void alu_init();
	250
	251	};
	252
	253
	254	extern const device_type DSP56156;
	255
	256
233	257	#endif /* __DSP56K_H__ */

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