trunk/src/emu/bus/isa/trident.c
| r32061 | r32062 | |
|---|
| 29 | 29 | void trident_vga_device::device_reset() |
| 30 | 30 | { |
| 31 | 31 | svga_device::device_reset(); |
| 32 | | svga.id = 0xd3; // identifies at TGUI9660XGi (closest known to the 9680) |
| 32 | svga.id = 0xd3; // identifies at TGUI9660XGi |
| 33 | tri.revision = 0x01; // revision identifies as TGUI9680 |
| 33 | 34 | tri.new_mode = false; // start up in old mode |
| 35 | tri.dac_active = false; |
| 34 | 36 | } |
| 35 | 37 | |
| 38 | UINT16 trident_vga_device::offset() |
| 39 | { |
| 40 | UINT16 off = svga_device::offset(); |
| 41 | return off; |
| 42 | } |
| 43 | |
| 36 | 44 | void trident_vga_device::trident_define_video_mode() |
| 37 | 45 | { |
| 38 | 46 | int divisor = 1; |
| r32061 | r32062 | |
|---|
| 74 | 82 | { |
| 75 | 83 | case 0: |
| 76 | 84 | default: if(!(tri.pixel_depth & 0x10)) svga.rgb8_en = 1; break; |
| 77 | | case 1: svga.rgb16_en = 1; break; // for 15 or 16 bit modes, can we tell the difference? |
| 85 | case 1: if((tri.dac & 0xf0) == 0x30) svga.rgb16_en = 1; else svga.rgb15_en = 1; break; |
| 78 | 86 | case 2: svga.rgb32_en = 1; break; |
| 79 | 87 | } |
| 80 | 88 | |
| r32061 | r32062 | |
|---|
| 93 | 101 | { |
| 94 | 102 | switch(index) |
| 95 | 103 | { |
| 104 | case 0x09: |
| 105 | res = tri.revision; |
| 106 | break; |
| 96 | 107 | case 0x0b: |
| 97 | 108 | res = svga.id; |
| 98 | 109 | tri.new_mode = true; |
| r32061 | r32062 | |
|---|
| 125 | 136 | |
| 126 | 137 | void trident_vga_device::trident_seq_reg_write(UINT8 index, UINT8 data) |
| 127 | 138 | { |
| 139 | //logerror("Trident SR%02X: %s mode write %02x\n",index,tri.new_mode ? "new" : "old",data); |
| 128 | 140 | if(index <= 0x04) |
| 129 | 141 | { |
| 130 | 142 | vga.sequencer.data[vga.sequencer.index] = data; |
| r32061 | r32062 | |
|---|
| 205 | 217 | } |
| 206 | 218 | void trident_vga_device::trident_crtc_reg_write(UINT8 index, UINT8 data) |
| 207 | 219 | { |
| 220 | //logerror("Trident CR%02X: write %02x\n",index,data); |
| 208 | 221 | if(index <= 0x18) |
| 209 | 222 | { |
| 210 | 223 | crtc_reg_write(index,data); |
| r32061 | r32062 | |
|---|
| 254 | 267 | |
| 255 | 268 | void trident_vga_device::trident_gc_reg_write(UINT8 index, UINT8 data) |
| 256 | 269 | { |
| 270 | //logerror("Trident GC%02X: write %02x\n",index,data); |
| 257 | 271 | if(index <= 0x0d) |
| 258 | 272 | gc_reg_write(index,data); |
| 259 | 273 | else |
| r32061 | r32062 | |
|---|
| 287 | 301 | case 0x05: |
| 288 | 302 | res = trident_seq_reg_read(vga.sequencer.index); |
| 289 | 303 | break; |
| 304 | case 0x06: |
| 305 | tri.dac_count++; |
| 306 | if(tri.dac_count > 3) |
| 307 | tri.dac_active = true; |
| 308 | if(tri.dac_active) |
| 309 | res = tri.dac; |
| 310 | else |
| 311 | res = vga_device::port_03c0_r(space,offset,mem_mask); |
| 312 | break; |
| 313 | case 0x07: |
| 314 | case 0x08: |
| 315 | case 0x09: |
| 316 | tri.dac_active = false; |
| 317 | tri.dac_count = 0; |
| 318 | res = vga_device::port_03c0_r(space,offset,mem_mask); |
| 319 | break; |
| 290 | 320 | case 0x0f: |
| 291 | 321 | res = trident_gc_reg_read(vga.gc.index); |
| 292 | 322 | break; |
| r32061 | r32062 | |
|---|
| 305 | 335 | case 0x05: |
| 306 | 336 | trident_seq_reg_write(vga.sequencer.index,data); |
| 307 | 337 | break; |
| 338 | case 0x06: |
| 339 | if(tri.dac_active) |
| 340 | { |
| 341 | tri.dac = data; // DAC command register |
| 342 | tri.dac_active = false; |
| 343 | tri.dac_count = 0; |
| 344 | trident_define_video_mode(); |
| 345 | } |
| 346 | else |
| 347 | vga_device::port_03c0_w(space,offset,data,mem_mask); |
| 348 | break; |
| 349 | case 0x07: |
| 350 | case 0x08: |
| 351 | case 0x09: |
| 352 | tri.dac_active = false; |
| 353 | tri.dac_count = 0; |
| 354 | vga_device::port_03c0_w(space,offset,data,mem_mask); |
| 355 | break; |
| 308 | 356 | case 0x0f: |
| 309 | 357 | trident_gc_reg_write(vga.gc.index,data); |
| 310 | 358 | break; |