trunk/src/emu/video/pc_vga.c
| r31980 | r31981 | |
| 46 | 46 | |
| 47 | 47 | #include "emu.h" |
| 48 | 48 | #include "pc_vga.h" |
| 49 | #include "bus/isa/trident.h" |
| 49 | 50 | #include "machine/eepromser.h" |
| 50 | 51 | #include "debugger.h" |
| 51 | 52 | |
| r31980 | r31981 | |
| 118 | 119 | // device type definition |
| 119 | 120 | const device_type VGA = &device_creator<vga_device>; |
| 120 | 121 | const device_type TSENG_VGA = &device_creator<tseng_vga_device>; |
| 121 | | const device_type TRIDENT_VGA = &device_creator<trident_vga_device>; |
| 122 | 122 | const device_type S3_VGA = &device_creator<s3_vga_device>; |
| 123 | 123 | const device_type GAMTOR_VGA = &device_creator<gamtor_vga_device>; |
| 124 | 124 | const device_type ATI_VGA = &device_creator<ati_vga_device>; |
| r31980 | r31981 | |
| 148 | 148 | { |
| 149 | 149 | } |
| 150 | 150 | |
| 151 | | trident_vga_device::trident_vga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) |
| 152 | | : svga_device(mconfig, TRIDENT_VGA, "Trident VGA", tag, owner, clock, "trident_vga", __FILE__) |
| 153 | | { |
| 154 | | } |
| 155 | | |
| 156 | 151 | s3_vga_device::s3_vga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) |
| 157 | 152 | : ati_vga_device(mconfig, S3_VGA, "S3 Graphics VGA", tag, owner, clock, "s3_vga", __FILE__) |
| 158 | 153 | { |
| r31980 | r31981 | |
| 2584 | 2579 | |
| 2585 | 2580 | /****************************************** |
| 2586 | 2581 | |
| 2587 | | Trident implementation |
| 2588 | | |
| 2589 | | ******************************************/ |
| 2590 | | UINT8 trident_vga_device::trident_seq_reg_read(UINT8 index) |
| 2591 | | { |
| 2592 | | UINT8 res; |
| 2593 | | |
| 2594 | | res = 0xff; |
| 2595 | | |
| 2596 | | if(index <= 0x04) |
| 2597 | | res = vga.sequencer.data[index]; |
| 2598 | | else |
| 2599 | | { |
| 2600 | | switch(index) |
| 2601 | | { |
| 2602 | | case 0x0b: |
| 2603 | | res = svga.id; |
| 2604 | | // TODO: new mode registers selected |
| 2605 | | break; |
| 2606 | | case 0x0d: |
| 2607 | | res = svga.rgb15_en; |
| 2608 | | break; |
| 2609 | | } |
| 2610 | | } |
| 2611 | | |
| 2612 | | return res; |
| 2613 | | } |
| 2614 | | |
| 2615 | | void trident_vga_device::trident_seq_reg_write(UINT8 index, UINT8 data) |
| 2616 | | { |
| 2617 | | if(index <= 0x04) |
| 2618 | | { |
| 2619 | | vga.sequencer.data[vga.sequencer.index] = data; |
| 2620 | | seq_reg_write(vga.sequencer.index,data); |
| 2621 | | recompute_params(); |
| 2622 | | } |
| 2623 | | else |
| 2624 | | { |
| 2625 | | switch(index) |
| 2626 | | { |
| 2627 | | case 0x0b: |
| 2628 | | // TODO: old mode registers selected |
| 2629 | | break; |
| 2630 | | case 0x0d: |
| 2631 | | svga.rgb15_en = data & 0x30; // TODO: doesn't match documentation |
| 2632 | | break; |
| 2633 | | } |
| 2634 | | } |
| 2635 | | } |
| 2636 | | |
| 2637 | | |
| 2638 | | READ8_MEMBER(trident_vga_device::port_03c0_r) |
| 2639 | | { |
| 2640 | | UINT8 res; |
| 2641 | | |
| 2642 | | switch(offset) |
| 2643 | | { |
| 2644 | | case 0x05: |
| 2645 | | res = trident_seq_reg_read(vga.sequencer.index); |
| 2646 | | break; |
| 2647 | | default: |
| 2648 | | res = vga_device::port_03c0_r(space,offset,mem_mask); |
| 2649 | | break; |
| 2650 | | } |
| 2651 | | |
| 2652 | | return res; |
| 2653 | | } |
| 2654 | | |
| 2655 | | WRITE8_MEMBER(trident_vga_device::port_03c0_w) |
| 2656 | | { |
| 2657 | | switch(offset) |
| 2658 | | { |
| 2659 | | case 0x05: |
| 2660 | | trident_seq_reg_write(vga.sequencer.index,data); |
| 2661 | | break; |
| 2662 | | default: |
| 2663 | | vga_device::port_03c0_w(space,offset,data,mem_mask); |
| 2664 | | break; |
| 2665 | | } |
| 2666 | | } |
| 2667 | | |
| 2668 | | |
| 2669 | | READ8_MEMBER(trident_vga_device::port_03d0_r) |
| 2670 | | { |
| 2671 | | UINT8 res = 0xff; |
| 2672 | | |
| 2673 | | if (CRTC_PORT_ADDR == 0x3d0) |
| 2674 | | { |
| 2675 | | switch(offset) |
| 2676 | | { |
| 2677 | | case 8: |
| 2678 | | res = svga.bank_w & 0x1f; // TODO: a lot more complex than this |
| 2679 | | break; |
| 2680 | | default: |
| 2681 | | res = vga_device::port_03d0_r(space,offset,mem_mask); |
| 2682 | | break; |
| 2683 | | } |
| 2684 | | } |
| 2685 | | |
| 2686 | | return res; |
| 2687 | | } |
| 2688 | | |
| 2689 | | WRITE8_MEMBER(trident_vga_device::port_03d0_w) |
| 2690 | | { |
| 2691 | | if (CRTC_PORT_ADDR == 0x3d0) |
| 2692 | | { |
| 2693 | | switch(offset) |
| 2694 | | { |
| 2695 | | case 8: |
| 2696 | | svga.bank_w = data & 0x1f; // TODO: a lot more complex than this |
| 2697 | | break; |
| 2698 | | default: |
| 2699 | | vga_device::port_03d0_w(space,offset,data,mem_mask); |
| 2700 | | break; |
| 2701 | | } |
| 2702 | | } |
| 2703 | | } |
| 2704 | | |
| 2705 | | READ8_MEMBER(trident_vga_device::mem_r ) |
| 2706 | | { |
| 2707 | | if (svga.rgb15_en & 0x30) |
| 2708 | | { |
| 2709 | | int data; |
| 2710 | | if(offset & 0x10000) // TODO: old reg mode actually CAN read to the upper bank |
| 2711 | | return 0; |
| 2712 | | data=vga.memory[offset + (svga.bank_w*0x10000)]; |
| 2713 | | return data; |
| 2714 | | } |
| 2715 | | |
| 2716 | | return vga_device::mem_r(space,offset,mem_mask); |
| 2717 | | } |
| 2718 | | |
| 2719 | | WRITE8_MEMBER(trident_vga_device::mem_w) |
| 2720 | | { |
| 2721 | | if (svga.rgb15_en & 0x30) |
| 2722 | | { |
| 2723 | | if(offset & 0x10000) // TODO: old reg mode actually CAN write to the upper bank |
| 2724 | | return; |
| 2725 | | vga.memory[offset + (svga.bank_w*0x10000)]= data; |
| 2726 | | return; |
| 2727 | | } |
| 2728 | | |
| 2729 | | vga_device::mem_w(space,offset,data,mem_mask); |
| 2730 | | } |
| 2731 | | |
| 2732 | | /****************************************** |
| 2733 | | |
| 2734 | 2582 | S3 implementation |
| 2735 | 2583 | |
| 2736 | 2584 | ******************************************/ |
trunk/src/emu/video/pc_vga.h
| r31980 | r31981 | |
| 468 | 468 | // device type definition |
| 469 | 469 | extern const device_type TSENG_VGA; |
| 470 | 470 | |
| 471 | | // ======================> trident_vga_device |
| 472 | 471 | |
| 473 | | class trident_vga_device : public svga_device |
| 474 | | { |
| 475 | | public: |
| 476 | | // construction/destruction |
| 477 | | trident_vga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); |
| 478 | | |
| 479 | | virtual READ8_MEMBER(port_03c0_r); |
| 480 | | virtual WRITE8_MEMBER(port_03c0_w); |
| 481 | | virtual READ8_MEMBER(port_03d0_r); |
| 482 | | virtual WRITE8_MEMBER(port_03d0_w); |
| 483 | | virtual READ8_MEMBER(mem_r); |
| 484 | | virtual WRITE8_MEMBER(mem_w); |
| 485 | | |
| 486 | | protected: |
| 487 | | |
| 488 | | private: |
| 489 | | UINT8 trident_seq_reg_read(UINT8 index); |
| 490 | | void trident_seq_reg_write(UINT8 index, UINT8 data); |
| 491 | | |
| 492 | | }; |
| 493 | | |
| 494 | | |
| 495 | | // device type definition |
| 496 | | extern const device_type TRIDENT_VGA; |
| 497 | | |
| 498 | | |
| 499 | 472 | // ======================> ati_vga_device |
| 500 | 473 | |
| 501 | 474 | class ati_vga_device : public svga_device |
trunk/src/emu/bus/isa/trident.h
| r0 | r31981 | |
| 1 | /* |
| 2 | * trident.h |
| 3 | * |
| 4 | */ |
| 5 | |
| 6 | #ifndef TRIDENT_H_ |
| 7 | #define TRIDENT_H_ |
| 8 | |
| 9 | #include "video/pc_vga.h" |
| 10 | |
| 11 | // ======================> trident_vga_device |
| 12 | |
| 13 | class trident_vga_device : public svga_device |
| 14 | { |
| 15 | public: |
| 16 | // construction/destruction |
| 17 | trident_vga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); |
| 18 | |
| 19 | virtual READ8_MEMBER(port_03c0_r); |
| 20 | virtual WRITE8_MEMBER(port_03c0_w); |
| 21 | virtual READ8_MEMBER(port_03d0_r); |
| 22 | virtual WRITE8_MEMBER(port_03d0_w); |
| 23 | virtual READ8_MEMBER(mem_r); |
| 24 | virtual WRITE8_MEMBER(mem_w); |
| 25 | |
| 26 | protected: |
| 27 | |
| 28 | private: |
| 29 | UINT8 trident_seq_reg_read(UINT8 index); |
| 30 | void trident_seq_reg_write(UINT8 index, UINT8 data); |
| 31 | |
| 32 | }; |
| 33 | |
| 34 | |
| 35 | // device type definition |
| 36 | extern const device_type TRIDENT_VGA; |
| 37 | |
| 38 | #endif /* TRIDENT_H_ */ |
trunk/src/emu/bus/isa/trident.c
| r0 | r31981 | |
| 1 | /* |
| 2 | * trident.c |
| 3 | * |
| 4 | * Implementation of Trident VGA GUI accelerators |
| 5 | * |
| 6 | * |
| 7 | */ |
| 8 | |
| 9 | #include "emu.h" |
| 10 | #include "trident.h" |
| 11 | |
| 12 | const device_type TRIDENT_VGA = &device_creator<trident_vga_device>; |
| 13 | |
| 14 | #define CRTC_PORT_ADDR ((vga.miscellaneous_output&1)?0x3d0:0x3b0) |
| 15 | |
| 16 | trident_vga_device::trident_vga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) |
| 17 | : svga_device(mconfig, TRIDENT_VGA, "Trident TGUI9680", tag, owner, clock, "trident_vga", __FILE__) |
| 18 | { |
| 19 | } |
| 20 | |
| 21 | UINT8 trident_vga_device::trident_seq_reg_read(UINT8 index) |
| 22 | { |
| 23 | UINT8 res; |
| 24 | |
| 25 | res = 0xff; |
| 26 | |
| 27 | if(index <= 0x04) |
| 28 | res = vga.sequencer.data[index]; |
| 29 | else |
| 30 | { |
| 31 | switch(index) |
| 32 | { |
| 33 | case 0x0b: |
| 34 | res = svga.id; |
| 35 | // TODO: new mode registers selected |
| 36 | break; |
| 37 | case 0x0d: |
| 38 | res = svga.rgb15_en; |
| 39 | break; |
| 40 | } |
| 41 | } |
| 42 | |
| 43 | return res; |
| 44 | } |
| 45 | |
| 46 | void trident_vga_device::trident_seq_reg_write(UINT8 index, UINT8 data) |
| 47 | { |
| 48 | if(index <= 0x04) |
| 49 | { |
| 50 | vga.sequencer.data[vga.sequencer.index] = data; |
| 51 | seq_reg_write(vga.sequencer.index,data); |
| 52 | recompute_params(); |
| 53 | } |
| 54 | else |
| 55 | { |
| 56 | switch(index) |
| 57 | { |
| 58 | case 0x0b: |
| 59 | // TODO: old mode registers selected |
| 60 | break; |
| 61 | case 0x0d: |
| 62 | svga.rgb15_en = data & 0x30; // TODO: doesn't match documentation |
| 63 | break; |
| 64 | } |
| 65 | } |
| 66 | } |
| 67 | |
| 68 | |
| 69 | READ8_MEMBER(trident_vga_device::port_03c0_r) |
| 70 | { |
| 71 | UINT8 res; |
| 72 | |
| 73 | switch(offset) |
| 74 | { |
| 75 | case 0x05: |
| 76 | res = trident_seq_reg_read(vga.sequencer.index); |
| 77 | break; |
| 78 | default: |
| 79 | res = vga_device::port_03c0_r(space,offset,mem_mask); |
| 80 | break; |
| 81 | } |
| 82 | |
| 83 | return res; |
| 84 | } |
| 85 | |
| 86 | WRITE8_MEMBER(trident_vga_device::port_03c0_w) |
| 87 | { |
| 88 | switch(offset) |
| 89 | { |
| 90 | case 0x05: |
| 91 | trident_seq_reg_write(vga.sequencer.index,data); |
| 92 | break; |
| 93 | default: |
| 94 | vga_device::port_03c0_w(space,offset,data,mem_mask); |
| 95 | break; |
| 96 | } |
| 97 | } |
| 98 | |
| 99 | |
| 100 | READ8_MEMBER(trident_vga_device::port_03d0_r) |
| 101 | { |
| 102 | UINT8 res = 0xff; |
| 103 | |
| 104 | if (CRTC_PORT_ADDR == 0x3d0) |
| 105 | { |
| 106 | switch(offset) |
| 107 | { |
| 108 | case 8: |
| 109 | res = svga.bank_w & 0x1f; // TODO: a lot more complex than this |
| 110 | break; |
| 111 | default: |
| 112 | res = vga_device::port_03d0_r(space,offset,mem_mask); |
| 113 | break; |
| 114 | } |
| 115 | } |
| 116 | |
| 117 | return res; |
| 118 | } |
| 119 | |
| 120 | WRITE8_MEMBER(trident_vga_device::port_03d0_w) |
| 121 | { |
| 122 | if (CRTC_PORT_ADDR == 0x3d0) |
| 123 | { |
| 124 | switch(offset) |
| 125 | { |
| 126 | case 8: |
| 127 | svga.bank_w = data & 0x1f; // TODO: a lot more complex than this |
| 128 | break; |
| 129 | default: |
| 130 | vga_device::port_03d0_w(space,offset,data,mem_mask); |
| 131 | break; |
| 132 | } |
| 133 | } |
| 134 | } |
| 135 | |
| 136 | READ8_MEMBER(trident_vga_device::mem_r ) |
| 137 | { |
| 138 | if (svga.rgb15_en & 0x30) |
| 139 | { |
| 140 | int data; |
| 141 | if(offset & 0x10000) // TODO: old reg mode actually CAN read to the upper bank |
| 142 | return 0; |
| 143 | data=vga.memory[offset + (svga.bank_w*0x10000)]; |
| 144 | return data; |
| 145 | } |
| 146 | |
| 147 | return vga_device::mem_r(space,offset,mem_mask); |
| 148 | } |
| 149 | |
| 150 | WRITE8_MEMBER(trident_vga_device::mem_w) |
| 151 | { |
| 152 | if (svga.rgb15_en & 0x30) |
| 153 | { |
| 154 | if(offset & 0x10000) // TODO: old reg mode actually CAN write to the upper bank |
| 155 | return; |
| 156 | vga.memory[offset + (svga.bank_w*0x10000)]= data; |
| 157 | return; |
| 158 | } |
| 159 | |
| 160 | vga_device::mem_w(space,offset,data,mem_mask); |
| 161 | } |
| 162 | |