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r31973 Sunday 7th September, 2014 at 19:41:41 UTC by Michael Zapf
(MESS) hfdc/hdc9234: WIP; restore/seek/read sector FM/MFM working (nw)

[src/emu/bus/ti99_peb]	hfdc.c hfdc.h
[src/emu/machine]	hdc9234.c hdc9234.h

trunk/src/emu/machine/hdc9234.c

r31972	r31973
21	21	#include "emu.h"
22	22	#include "hdc9234.h"
23	23
24		#define TRACE_REG 1
25		#define TRACE_ACT 1
	24	#define TRACE_REG 0
	25	#define TRACE_ACT 0
	26	#define TRACE_SHIFT 0
	27	#define TRACE_LIVE 0
	28	#define TRACE_SYNC 0
26	29
	30	#define UNRELIABLE_MEDIA 0
	31
	32	// Seek complete?
	33
	34	// Untested:
	35	// Multi-sector read
	36	// Seek complete
	37	// read sectors physical
	38	//
	39
27	40	/*
28	41	Register names of the HDC. The left part is the set of write registers,
29	42	while the right part are the read registers.
r31972	r31973
34	47	|   0  |  Desired cylinder  |   Desired head  (OUTPUT2) |  SMC mode
35	48	+------+------+------+------+------+------+------+------+
36	49	+------+------+------+------+------+------+------+------+
37		RETRY:  |      Retry count          |   Progr. output (OUTPUT1) |
	50	RETRY:  |  Retry count (ones comp!) |   Progr. output (OUTPUT1) |
38	51	+------+------+------+------+------+------+------+------+
39	52	+------+------+------+------+------+------+------+------+
40	53	MODE:   | HD   | use CRC/ECC |  FM  |  0   |      step rate     |
r31972	r31973
49	62	+------+------+------+------+------+------+------+------+
50	63	|          Head load timer count                        | drselect
51	64	+------+------+------+------+------+------+------+------+
	65
	66	Read registers
	67	+------+------+------+------+------+------+------+------+
	68	CHIP_ST:| Retry|  ECC |  CRC | DelD | Sync | Comp | Current Drv |
	69	+------+------+------+------+------+------+------+------+
	70	+------+------+------+------+------+------+------+------+
	71	INT_ST: | Pend | DMARQ| Done |  Termcode   | RdyCh| Ovrun| BdSec|
	72	+------+------+------+------+------+------+------+------+
	73	+------+------+------+------+------+------+------+------+
	74	DRV_ST: | ECC  | Index| SeekC| Trk00| User | WrPrt| Ready|Wfault|
	75	+------+------+------+------+------+------+------+------+
	76
52	77	*/
53	78	enum
54	79	{
r31972	r31973
57	82	DMA7_0=0,
58	83	DMA15_8=1,
59	84	DMA23_16=2,
60		DESIRED_SECTOR=3,
	85	DESIRED_SECTOR=3,       CURRENT_SECTOR=3,
61	86	DESIRED_HEAD=4,         CURRENT_HEAD=4,
62	87	DESIRED_CYLINDER=5,     CURRENT_CYLINDER=5,
63	88	SECTOR_COUNT=6,         CURRENT_IDENT=6,
r31972	r31973
65	90	MODE=8,                 CHIP_STATUS=8,
66	91	INT_COMM_TERM=9,        DRIVE_STATUS=9,
67	92	DATA_DELAY=10,          DATA=10,
68		COMMAND=11,             INT_STATUS=11
	93	COMMAND=11,             INT_STATUS=11,
	94
	95	//======================
	96	// Internal registers
	97	CURRENT_SIZE=12,
	98	CURRENT_CRC1=13,
	99	CURRENT_CRC2=14
69	100	};
70	101
71	102	/*
r31972	r31973
79	110	ST_TERMCOD = 0x18,       // termination code (see below)
80	111	TC_SUCCESS = 0x00,   // Successful completion
81	112	TC_RDIDERR = 0x08,   // Error in READ-ID sequence
82		TC_SEEKERR = 0x10,   // Error in SEEK sequence
	113	TC_VRFYERR = 0x10,   // Error in VERIFY sequence
83	114	TC_DATAERR = 0x18,   // Error in DATA-TRANSFER seq.
84	115	ST_RDYCHNG = 0x04,       // ready change
85	116	ST_OVRUN   = 0x02,       // overrun/underrun
r31972	r31973
102	133	};
103	134
104	135	/*
	136	Definition of bits in the chip status register.
	137	*/
	138	enum
	139	{
	140	CS_RETREQ  = 0x80,        // retry required
	141	CS_ECCATT  = 0x40,        // ECC correction attempted
	142	CS_CRCERR  = 0x20,        // ECC/CRC error
	143	CS_DELDATA = 0x10,        // deleted data mark
	144	CS_SYNCERR = 0x08,        // synchronization error
	145	CS_COMPERR = 0x04,        // compare error
	146	CS_PRESDRV = 0x03         // present drive selected
	147	};
	148
	149	/*
105	150	Bits in the internal output registers. The registers are output via the
106	151	auxiliary bus (AB)
107	152
r31972	r31973
118	163	OUTPUT2
119	164	AB7     drive select 3* (active low, used for tape operations)
120	165	AB6     reduce write current
121		AB5     step direction
122		AB4     step pulse
	166	AB5     step direction       (0=towards TRK00)
	167	AB4     step pulse           (1=active)
123	168	AB3     desired head 3
124	169	AB2     desired head 2
125	170	AB1     desired head 1
r31972	r31973
149	194	TYPE_FLOPPY5 = 0x03
150	195	};
151	196
	197	#define DRIVE_TYPE  0x03
	198
	199	/*
	200	Timers
	201	*/
	202	enum
	203	{
	204	GEN_TIMER = 1,
	205	COM_TIMER,
	206	LIVE_TIMER
	207	};
	208
	209	/*
	210	Definition of bits in the Mode register
	211	*/
	212	enum {
	213	MO_TYPE     = 0x80,        // Hard disk (1) or floppy (0)
	214	MO_CRCECC   = 0x60,        // Values for CRC/ECC handling
	215	MO_DENSITY  = 0x10,        // FM = 1; MFM = 0
	216	MO_UNUSED   = 0x08,        // Unused, 0
	217	MO_STEPRATE = 0x07         // Step rates
	218	};
	219
	220	/*
	221	Step rates in microseconds for MFM. This is set in the mode register,
	222	bits 0-2. FM mode doubles all values.
	223	*/
	224	static const int step_hd[]      = { 22, 50, 100, 200, 400, 800, 1600, 3200 };
	225	static const int step_flop8[]   = { 218, 500, 1000, 2000, 4000, 8000, 16000, 32000 };
	226	static const int step_flop5[]   = { 436, 1000, 2000, 4000, 8000, 16000, 32000, 64000 };
	227
	228	/*
	229	ID fields association to registers
	230	*/
	231	static const int id_field[] = { CURRENT_CYLINDER, CURRENT_HEAD, CURRENT_SECTOR, CURRENT_SIZE, CURRENT_CRC1, CURRENT_CRC2 };
	232
	233	/*
	234	Pulse widths for stepping in ??s
	235	*/
	236	enum
	237	{
	238	pulse_hd = 11,
	239	pulse_flop8 = 112,
	240	pulse_flop5 = 224
	241	};
	242
	243	/*
	244	Times for UDC's acceptance of command and register write accesses (ns).
	245	*/
	246	enum
	247	{
	248	REGISTER_COMMIT = 1000,
	249	COMMAND_COMMIT = 1000
	250	};
	251
	252	enum
	253	{
	254	UNDEF,
	255	IDLE,
	256	DONE,
	257	STEP_ON,
	258	STEP_OFF,
	259	RESTORE_CHECK1,
	260	RESTORE_CHECK2,
	261	SEEK_COMPLETE,
	262
	263	READ_ID,
	264	READ_ID1,
	265
	266	VERIFY,
	267	VERIFY1,
	268	VERIFY2,
	269	VERIFY3,
	270
	271	DATA_TRANSFER,
	272	DATA_TRANSFER1,
	273
	274	// Live states
	275	SEARCH_IDAM,
	276	SEARCH_IDAM_FAILED,
	277	READ_TWO_MORE_A1_IDAM,
	278	READ_ID_FIELDS_INTO_REGS,
	279	SEARCH_DAM,
	280	READ_TWO_MORE_A1_DAM,
	281	SEARCH_DAM_FAILED,
	282	READ_SECTOR_DATA,
	283	READ_SECTOR_DATA1
	284	};
	285
	286	enum
	287	{
	288	NOCMD,
	289	RESET,
	290	DESELECT,
	291	RESTORE,
	292	STEP,
	293	SELECT,
	294	SETREG,
	295	READSECL,
	296	READSECP
	297	};
	298
	299	const hdc9234_device::cmddef hdc9234_device::s_command[] =
	300	{
	301	{ 0x00, 0xff, RESET, &hdc9234_device::device_reset },
	302	{ 0x01, 0xff, DESELECT, &hdc9234_device::drive_deselect },
	303	{ 0x02, 0xfe, RESTORE, &hdc9234_device::restore_drive },
	304	{ 0x04, 0xfc, STEP, &hdc9234_device::step_drive },
	305	{ 0x20, 0xe0, SELECT, &hdc9234_device::drive_select },
	306	{ 0x40, 0xf0, SETREG, &hdc9234_device::set_register_pointer },
	307	{ 0x58, 0xfe, READSECP, &hdc9234_device::read_sector_physical },
	308	{ 0x5c, 0xfc, READSECL, &hdc9234_device::read_sector_logical },
	309	{ 0, 0, 0, 0 }
	310	};
	311
	312	/*
	313	Standard constructor.
	314	*/
152	315	hdc9234_device::hdc9234_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
153	316	: device_t(mconfig, HDC9234, "SMC HDC9234 Universal Disk Controller", tag, owner, clock, "hdc9234", __FILE__),
154	317	m_out_intrq(*this),
	318	m_out_dmarq(*this),
155	319	m_out_dip(*this),
156	320	m_out_auxbus(*this),
157	321	m_in_dma(*this),
158		m_out_dma(*this)
	322	m_out_dma(*this),
	323	m_initialized(false)
159	324	{
160	325	}
161	326
r31972	r31973
169	334	}
170	335
171	336	/*
	337	Tell whether the controller is in FM mode.
	338	*/
	339	bool hdc9234_device::fm_mode()
	340	{
	341	return ((m_register_w[MODE]&MO_DENSITY)!=0);
	342	}
	343
	344	/*
172	345	Set/clear INT
173	346
174	347	Interupts are generated in the following occasions:
r31972	r31973
196	369	}
197	370
198	371	/*
199		Process a command
200		*/
201		void hdc9234_device::process_command(UINT8 opcode)
202		{
203		// Reset DONE and BAD_SECTOR [1], p.7
204		set_bits(m_register_r[INT_STATUS], ST_DONE | ST_BADSECT, false);
205
206		/*
207		// Reset interrupt line (not explicitly mentioned in spec, but seems reasonable
208		set_interrupt(CLEAR_LINE);
209
210		// Clear Interrupt Pending and Ready Change
211		set_bits(m_register_r[INT_STATUS], ST_INTPEND | ST_RDYCHNG, false);
212		*/
213		m_command = opcode;
214
215		if (opcode == 0x00)
216		{
217		// RESET
218		// same effect as the RST* pin being active
219		if (TRACE_ACT) logerror("%s: Reset command\n", tag());
220		device_reset();
221		}
222		else if (opcode == 0x01)
223		{
224		// DESELECT DRIVE
225		// done when no drive is in use
226		if (TRACE_ACT) logerror("%s: drdeselect command\n", tag());
227		set_bits(m_output1, OUT1_DRVSEL3|OUT1_DRVSEL2|OUT1_DRVSEL1|OUT1_DRVSEL0, false);
228		sync_latches_out();
229		}
230		else if (opcode >= 0x20 && opcode <= 0x3f)
231		{
232		// DRIVE SELECT
233		drive_select(opcode&0x1f);
234		}
235		else if (opcode >= 0x40 && opcode <= 0x4f)
236		{
237		// SETREGPTR
238		m_register_pointer = opcode & 0xf;
239		if (TRACE_ACT) logerror("%s: setregptr command; start reg=%d\n", tag(), m_register_pointer);
240		// Spec does not say anything about the effect of setting an
241		// invalid value (only "care should be taken")
242		if (m_register_pointer > 10)
243		{
244		logerror("%s: set register pointer: Invalid register number: %d. Setting to 10.\n", tag(), m_register_pointer);
245		m_register_pointer = 10;
246		}
247		}
248
249		set_command_done();
250		}
251
252		/*
253	372	Assert Command Done status bit, triggering interrupts as needed
254	373	*/
255	374	void hdc9234_device::set_command_done(int flags)
r31972	r31973
268	387	}
269	388
270	389	// [1], p. 6
271		if (m_register_w[INT_COMM_TERM] & TC_INTDONE)
272		set_interrupt(ASSERT_LINE);
	390	if (TRACE_ACT) logerror("%s: Raise interrupt DONE\n", tag());
	391	set_interrupt(ASSERT_LINE);
	392
	393	m_substate = IDLE;
	394	m_main_state = IDLE;
	395	m_command = NOCMD;
273	396	}
274	397
275	398	/*
r31972	r31973
280	403	set_command_done(-1);
281	404	}
282	405
283		void hdc9234_device::drive_select(int driveparm)
	406	void hdc9234_device::wait_time(emu_timer *tm, int microsec, int next_substate)
284	407	{
	408	if (TRACE_ACT) logerror("%s: Delay by %d microsec\n", tag(), microsec);
	409	tm->adjust(attotime::from_usec(microsec));
	410	m_substate = next_substate;
	411	}
	412
	413	void hdc9234_device::wait_time(emu_timer *tm, attotime delay, int param)
	414	{
	415	if (TRACE_ACT) logerror("%s: [%s] Delaying by %4.2f microsecs\n", tag(), ttsn().cstr(), delay.as_double()*1000000);
	416	tm->adjust(delay);
	417	m_substate = param;
	418	}
	419
	420	// ===========================================================================
	421	//     States
	422	// ===========================================================================
	423
	424	/*
	425	DESELECT DRIVE
	426	done when no drive is in use
	427	*/
	428	void hdc9234_device::drive_deselect()
	429	{
	430	if (TRACE_ACT) logerror("%s: deselect command\n", tag());
	431	set_bits(m_output1, OUT1_DRVSEL3|OUT1_DRVSEL2|OUT1_DRVSEL1|OUT1_DRVSEL0, false);
	432	sync_latches_out();
	433	set_command_done(TC_SUCCESS);
	434	}
	435
	436	/*
	437	"Restore" command
	438	// RESTORE DRIVE
	439	// bit 0:
	440	// 0 -> command ends after last seek pulse,
	441	// 1 -> command ends when the drive asserts the seek complete pin
	442	*/
	443	void hdc9234_device::restore_drive()
	444	{
	445	if (TRACE_ACT) logerror("%s: restore command %02x\n", tag(), m_command);
	446
	447	m_seek_count = 0;
	448	m_substate = RESTORE_CHECK1;
	449	step_drive_continue();
	450	}
	451
	452	/*
	453	STEP IN / OUT 1 CYLINDER
	454	*/
	455	void hdc9234_device::step_drive()
	456	{
	457	if (TRACE_ACT) logerror("%s: step in/out command %02x\n", tag(), m_command);
	458	m_substate = STEP_ON;
	459	step_drive_continue();
	460	}
	461
	462	void hdc9234_device::step_drive_continue()
	463	{
	464	while (true)
	465	{
	466	switch (m_substate)
	467	{
	468	case DONE:
	469	set_command_done(TC_SUCCESS);
	470	return;
	471
	472	case STEP_ON:
	473	if (TRACE_ACT) logerror("%s: substate STEP_ON\n", tag());
	474	// STEPDIR = 0 -> towards TRK00
	475	set_bits(m_output2, OUT2_STEPDIR, (m_command & 0x02)==0);
	476	// Raising edge (note that all signals must be inverted before leading them to the drive)
	477	set_bits(m_output2, OUT2_STEPPULSE, true);
	478	sync_latches_out();
	479	wait_time(m_timer, pulse_width(), STEP_OFF);
	480	return;
	481
	482	case STEP_OFF:
	483	if (TRACE_ACT) logerror("%s: substate STEP_OFF\n", tag());
	484	set_bits(m_output2, OUT2_STEPPULSE, false);
	485	sync_latches_out();
	486	if (m_main_state==RESTORE)
	487	{
	488	wait_time(m_timer, get_step_time(), RESTORE_CHECK1);
	489	}
	490	else
	491	{
	492	wait_time(m_timer, get_step_time(), DONE);
	493	}
	494	return;
	495
	496	case RESTORE_CHECK1:
	497	if (TRACE_ACT) logerror("%s: substate RESTORE_CHECK; seek count = %d\n", tag(), m_seek_count);
	498	// If the drive is on track 0 or not ready (no drive), terminate the command
	499	if (on_track00())
	500	{
	501	if (TRACE_ACT) logerror("%s: restore command TRK00 reached\n", tag());
	502	if (m_command & 1)
	503	{
	504	// Buffered seek; wait for SEEK_COMPLETE
	505	wait_line(SEEK_COMPLETE);
	506	return;
	507	}
	508	else
	509	{
	510	m_substate = DONE;
	511	break;
	512	}
	513	}
	514	m_substate = RESTORE_CHECK2;
	515	break;
	516
	517	case RESTORE_CHECK2:
	518	// Track 0 has not been reached yet
	519	if ((m_register_r[DRIVE_STATUS] & HDC_DS_READY)==0)
	520	{
	521	if (TRACE_ACT) logerror("%s: restore command: drive not ready\n", tag());
	522	m_substate = DONE;
	523	break;
	524	}
	525
	526	// Increase step count
	527	m_seek_count++;
	528	if (m_seek_count>=4096)
	529	{
	530	if (TRACE_ACT) logerror("%s: restore command: giving up\n", tag());
	531	set_command_done(TC_VRFYERR);
	532	return;
	533	}
	534
	535	m_substate = STEP_ON;
	536	break;
	537
	538	case SEEK_COMPLETE:
	539	m_substate = RESTORE_CHECK2;
	540	break;
	541	}
	542	}
	543	}
	544
	545	void hdc9234_device::drive_select()
	546	{
	547	int driveparm = m_command & 0x1f;
	548
285	549	// Command word
286	550	//
287	551	//        7     6     5     4     3     2     1     0
r31972	r31973
299	563	m_selected_drive_type = (driveparm>>2) & 0x03;
300	564	m_head_load_delay_enable = (driveparm>>4)&0x01;
301	565
302		if (TRACE_ACT) logerror("%s: drive select command: head load delay=%d, type=%d, drive=%d\n", tag(), m_head_load_delay_enable, m_selected_drive_type, driveparm&3);
	566	if (TRACE_ACT) logerror("%s: drive select command (%02x): head load delay=%d, type=%d, drive=%d\n", tag(), m_command, m_head_load_delay_enable, m_selected_drive_type, driveparm&3);
303	567
304		/*
305		// We need to store the type of the drive for the poll_drives command
306		// to be able to correctly select the device (floppy or hard disk).
307		m_types[driveparm&0x03] = m_selected_drive_type;
308		*/
	568	// We need to store the type of the drive for the poll_drives command
	569	// to be able to correctly select the device (floppy or hard disk).
	570	// m_types[driveparm&0x03] = m_selected_drive_type;
	571
309	572	// Copy the DMA registers to registers CURRENT_HEAD, CURRENT_CYLINDER,
310	573	// and CURRENT_IDENT. This is required during formatting ([1], p. 14)
311	574	// as the format command reuses the registers for formatting parameters.
r31972	r31973
313	576	m_register_r[CURRENT_CYLINDER] = m_register_r[DMA15_8];
314	577	m_register_r[CURRENT_IDENT] = m_register_r[DMA23_16];
315	578
	579	// Copy the selected drive number to the chip status register
316	580	m_register_r[CHIP_STATUS] = (m_register_r[CHIP_STATUS] & 0xfc) | (driveparm & 0x03);
317	581
318	582	sync_latches_out();
	583	set_command_done(TC_SUCCESS);
319	584	}
320	585
	586	void hdc9234_device::set_register_pointer()
	587	{
	588	m_register_pointer = m_command & 0xf;
	589	if (TRACE_ACT) logerror("%s: setregptr command; start reg=%d\n", tag(), m_register_pointer);
	590	// Spec does not say anything about the effect of setting an
	591	// invalid value (only "care should be taken")
	592	if (m_register_pointer > 10)
	593	{
	594	logerror("%s: set register pointer: Invalid register number: %d. Setting to 10.\n", tag(), m_register_pointer);
	595	m_register_pointer = 10;
	596	}
	597	set_command_done(TC_SUCCESS);
	598	}
	599
321	600	/*
	601	Read the desired sector. For multiple sectors, read the sectors in
	602	the order as they appear on the track. The command terminates with the
	603	next index pulse or when all sectors have been read before.
	604	Opcodes:
	605	58 = transfer disabled
	606	59 = transfer enabled
	607	*/
	608	void hdc9234_device::read_sector_physical()
	609	{
	610	if (TRACE_ACT) logerror("%s: read sectors physical command %02x\n", tag(), m_command);
	611	if (TRACE_ACT) logerror("%s: sector: C=%d H=%d S=%d\n", tag(), m_register_w[DESIRED_CYLINDER], m_register_w[DESIRED_HEAD],m_register_w[DESIRED_SECTOR]);
	612
	613	m_retry_save = m_register_w[RETRY_COUNT];
	614	m_multi_sector = (m_register_w[SECTOR_COUNT] != 1);
	615
	616	m_substate = READ_ID;
	617	read_sector_continue();
	618	}
	619
	620	/*
	621	Read the desired sector. For multiple sectors, read the sectors in
	622	ascending order (sector n, n+1, n+2 ...).
	623	Opcodes:
	624	5c = implied seek / transfer disabled
	625	5d = implied seek / transfer enabled
	626	5e = no implied seek / transfer disabled
	627	5f = no implied seek / transfer enabled
	628	*/
	629	void hdc9234_device::read_sector_logical()
	630	{
	631	if (TRACE_ACT) logerror("%s: read sectors logical command %02x\n", tag(), m_command);
	632	if (TRACE_ACT) logerror("%s: sector: C=%d H=%d S=%d\n", tag(), m_register_w[DESIRED_CYLINDER], m_register_w[DESIRED_HEAD],m_register_w[DESIRED_SECTOR]);
	633
	634	m_retry_save = m_register_w[RETRY_COUNT];
	635	m_multi_sector = (m_register_w[SECTOR_COUNT] != 1);
	636
	637	m_substate = READ_ID;
	638	read_sector_continue();
	639	}
	640
	641	void hdc9234_device::read_sector_continue()
	642	{
	643	while (true)
	644	{
	645	switch (m_substate)
	646	{
	647	/*
	648	READ ID FIELD ([1] p. 9)
	649	The controller
	650	- scans for the next IDAM
	651	- reads the ID field values into the CURRENT_HEAD/CYLINDER/SECTOR registers
	652	- checks the CRC
	653	- calculates the number of steps and the direction towards DESIRED_CYLINDER
	654	(must have saved that value before!)
	655	- steps to that location during OUTPUT2 times
	656
	657	When an error occurs, the COMMAND_TERMINATION bits are set to 01
	658	*/
	659	case READ_ID:
	660	// Implied seek: Enter the READ_ID subprogram.
	661	if (TRACE_ACT) logerror("%s: substate READ_ID\n", tag());
	662
	663	// Bit 1 = 0: enable implied seek (i.e. the controller will seek the desired track)
	664	// Bit 1 = 1: disable implied seek (controller will stay on the current track)
	665	// Also, do implied seek for read physical
	666	if ((m_command & 0x0e)==0x0e)
	667	m_substate = VERIFY;
	668	else
	669	m_substate = READ_ID1;
	670
	671	// First step: Search the next IDAM, and if found, read the
	672	// ID values into the registers
	673	m_live_state.bit_count_total = 0;
	674	live_start(SEARCH_IDAM);
	675	return;
	676
	677	case READ_ID1:
	678	// If an error occured (no IDAM found), terminate the command
	679	if ((m_register_r[CHIP_STATUS] & CS_SYNCERR) != 0)
	680	{
	681	if (TRACE_ACT) logerror("%s: READ_ID: No IDAM found\n", tag());
	682	set_command_done(TC_RDIDERR);
	683	return;
	684	}
	685
	686	if (TRACE_ACT)
	687	{
	688	logerror("%s: substate READ_ID1\n", tag());
	689	logerror("%s: DESIRED_CYL = %d; CURRENT_CYL = %d\n", tag(), m_register_w[DESIRED_CYLINDER], m_register_r[CURRENT_CYLINDER]);
	690	}
	691
	692	// The CRC has been updated automatically with each read_one_bit during the live_run.
	693	// We just need to check whether it ended in 0000
	694	if (m_live_state.crc != 0)
	695	{
	696	logerror("%s: CRC error in sector header\n", tag());
	697	set_bits(m_register_r[CHIP_STATUS], CS_CRCERR, true);
	698	set_command_done(TC_RDIDERR);
	699	return;
	700	}
	701
	702	// Calculate the direction and number of step pulses
	703	// positive -> towards inner cylinders
	704	// negative -> towards outer cylinders
	705	// zero -> we're already there
	706	m_track_delta = m_register_w[DESIRED_CYLINDER] - m_register_r[CURRENT_CYLINDER];
	707	m_substate = STEP_ON;
	708	break;
	709
	710	case STEP_ON:
	711	// Any more steps left?
	712	if (m_track_delta == 0)
	713	{
	714	m_substate = VERIFY;
	715	break;
	716	}
	717
	718	if (TRACE_ACT) logerror("%s: substate STEP_ON\n", tag());
	719	// STEPDIR = 0 -> towards TRK00
	720	set_bits(m_output2, OUT2_STEPDIR, (m_track_delta>0));
	721	set_bits(m_output2, OUT2_STEPPULSE, true);
	722	sync_latches_out();
	723	wait_time(m_timer, pulse_width(), STEP_OFF);
	724	return;
	725
	726	case STEP_OFF:
	727	if (TRACE_ACT) logerror("%s: substate STEP_OFF\n", tag());
	728	set_bits(m_output2, OUT2_STEPPULSE, false);
	729	sync_latches_out();
	730	m_track_delta += (m_track_delta<0)? 1 : -1;
	731	// Return to STEP_ON, check whether there are more steps
	732	wait_time(m_timer, get_step_time(), STEP_ON);
	733	return;
	734
	735	case VERIFY:
	736	/*
	737	VERIFY ([1] p. 10)
	738	The controller
	739	- continues to read the next ID field until the current values match the
	740	contents of the DESIRED_HEAD/CYLINDER/SECTOR registers
	741	- checks the CRC
	742
	743	When an error occurs, the COMMAND_TERMINATION bits are set to 10
	744	*/
	745	// After seeking (or immediately when implied seek has been disabled),
	746	// find the desired sector.
	747
	748	if (TRACE_ACT) logerror("%s: substate VERIFY\n", tag());
	749
	750	// If an error occured (no IDAM found), terminate the command
	751	// (This test is only relevant when we did not have a seek phase before)
	752	if ((m_register_r[CHIP_STATUS] & CS_SYNCERR) != 0)
	753	{
	754	if (TRACE_ACT) logerror("%s: READ_ID: No IDAM found\n", tag());
	755	set_command_done(TC_VRFYERR);
	756	return;
	757	}
	758
	759	// Count from 0 again
	760	m_live_state.bit_count_total = 0;
	761	m_substate = VERIFY1;
	762	break;
	763
	764	case VERIFY1:
	765	// Check whether we are already there
	766	if ((m_register_w[DESIRED_CYLINDER] == m_register_r[CURRENT_CYLINDER])
	767	&& (m_register_w[DESIRED_HEAD] == m_register_r[CURRENT_HEAD])
	768	&& (m_register_w[DESIRED_SECTOR] == m_register_r[CURRENT_SECTOR]))
	769	{
	770	if (TRACE_ACT) logerror("%s: Found the desired sector\n", tag());
	771	m_substate = DATA_TRANSFER;
	772	}
	773	else
	774	{
	775	if (TRACE_ACT) logerror("%s: Current CHS=(%d,%d,%d), desired CHS=(%d,%d,%d).\n", tag(),
	776	m_register_r[CURRENT_CYLINDER] & 0xff,
	777	m_register_r[CURRENT_HEAD] & 0xff,
	778	m_register_r[CURRENT_SECTOR] & 0xff,
	779	m_register_w[DESIRED_CYLINDER] & 0xff,
	780	m_register_w[DESIRED_HEAD] & 0xff,
	781	m_register_w[DESIRED_SECTOR] & 0xff);
	782	m_substate = VERIFY2;
	783	}
	784	break;
	785
	786	case VERIFY2:
	787	// Search the next ID
	788	m_substate = VERIFY3;
	789	live_start(SEARCH_IDAM);
	790	return;
	791
	792	case VERIFY3:
	793	if ((m_register_r[CHIP_STATUS] & CS_SYNCERR) != 0)
	794	{
	795	if (TRACE_ACT) logerror("%s: VERIFY: Desired sector not found\n", tag());
	796	// live_run has set the sync error; clear it
	797	set_bits(m_register_r[CHIP_STATUS], CS_SYNCERR, false);
	798	// and set the compare error bit instead
	799	set_bits(m_register_r[CHIP_STATUS], CS_COMPERR, true);
	800	set_command_done(TC_VRFYERR);
	801	return;
	802	}
	803
	804	// Continue with the loop
	805	if ((m_command & 0x0c)==0x0c)
	806	{
	807	// this is for the logical sector reading
	808	m_substate = VERIFY1;
	809	}
	810	else
	811	{
	812	// this is for the physical sector reading
	813	// do not verify the next ID field
	814	m_substate = DATA_TRANSFER;
	815	m_wait_for_index = true;
	816	}
	817	break;
	818
	819	case DATA_TRANSFER:
	820	/*
	821	DATA TRANSFER ([1], p. 10)
	822	only during READ PHYSICAL/LOGICAL
	823	The controller
	824	- scans for the next DAM
	825	- initiates a DMA request and waits for ACK from the system processor
	826	- transfers the contents of the current sector into memory via DMA
	827
	828	When an error occurs, the COMMAND_TERMINATION bits are set to 11
	829	*/
	830	if (TRACE_ACT) logerror("%s: substate DATA_TRANSFER\n", tag());
	831
	832	// Search the DAM and transfer the contents via DMA
	833	m_substate = DATA_TRANSFER1;
	834
	835	// Count from 0 again
	836	m_live_state.bit_count_total = 0;
	837
	838	dma_address_out();
	839	live_start(SEARCH_DAM);
	840	return;
	841
	842	case DATA_TRANSFER1:
	843	// OK, sector has been read.
	844	// Check CRC
	845	if (m_live_state.crc != 0)
	846	{
	847	if (TRACE_ACT) logerror("%s: CRC error in sector data\n", tag());
	848	// Set Retry Required flag
	849	set_bits(m_register_r[CHIP_STATUS], CS_RETREQ, true);
	850
	851	// Decrement the retry register (one's complemented value; 0000 = 15)
	852	int retry = 15-((m_register_w[RETRY_COUNT] >> 4)&0x0f);
	853	if (TRACE_ACT) logerror("%s: CRC error; retries = %d\n", tag(), retry);
	854	m_register_w[RETRY_COUNT] = (m_register_w[RETRY_COUNT] & 0x0f) | ((15-(retry-1))<<4);
	855
	856	if (retry == 0)
	857	{
	858	if (TRACE_ACT) logerror("%s: CRC error; no retries left\n", tag());
	859	set_bits(m_register_r[CHIP_STATUS], CS_CRCERR, true);
	860	set_command_done(TC_DATAERR);
	861	return;
	862	}
	863	else
	864	{
	865	// Go back to VERIFY and try again
	866	// Note that the specs recommend to set the retry to 0 (1111)
	867	// for physical reading; failing to do so will result in
	868	// unpredictable behavior.
	869	// We'll rely on the properly written software as well.
	870	m_live_state.bit_count_total = 0;
	871	m_substate = VERIFY2;
	872	}
	873	}
	874	else
	875	{
	876	if (TRACE_ACT) logerror("%s: Sector successfully read\n", tag());
	877
	878	// Update the DMA registers for multi-sector operations
	879	if (m_multi_sector)
	880	{
	881	int dma_address = (m_register_w[DMA23_16] & 0xff) << 16 |
	882	(m_register_w[DMA15_8] & 0xff) << 8 |
	883	(m_register_w[DMA7_0] & 0xff);
	884
	885	dma_address = (dma_address + get_sector_size()) & 0xffffff;
	886
	887	m_register_w[DMA23_16] = m_register_r[DMA23_16] = (dma_address & 0xff0000) >> 16;
	888	m_register_w[DMA15_8] = m_register_r[DMA15_8] = (dma_address & 0x00ff00) >> 16;
	889	m_register_w[DMA7_0] = m_register_r[DMA7_0] = (dma_address & 0x0000ff) >> 16;
	890	}
	891
	892	// Decrement the count
	893	m_register_w[SECTOR_COUNT] = (m_register_w[SECTOR_COUNT]-1) & 0xff;
	894
	895	// Do we have more sectors to read?
	896	// Surprisingly, the manual does not say what happens when
	897	// the sector count is zero for the first access.
	898	// It explicitly states that the check is done after the access.
	899	// If we take it (and especially the state charts) seriously, zero means 256.
	900	// m_stop_after_index is important for physical reading
	901	if (m_register_w[SECTOR_COUNT] != 0 && !m_stop_after_index)
	902	{
	903	// Increment the sector number
	904	// What happens when we exceed the highest sector number
	905	// in the track? We have to assume that this is possible
	906	// and that in this case the VERIFY routine fails.
	907	m_register_w[DESIRED_SECTOR] = (m_register_w[DESIRED_SECTOR] + 1) & 0xff;
	908	m_substate = VERIFY1;
	909	m_live_state.bit_count_total = 0;
	910	}
	911	else
	912	{
	913	set_command_done(TC_SUCCESS);
	914	return;
	915	}
	916	}
	917	break;
	918
	919	default:
	920	if (TRACE_ACT) logerror("%s: unknown substate %d in read_sector\n", tag(), m_substate);
	921	}
	922	}
	923	}
	924
	925	void hdc9234_device::general_continue()
	926	{
	927	// Do we have a live run on the track?
	928	if (m_live_state.state != IDLE)
	929	{
	930	// Continue with it
	931	live_run();
	932	if (m_live_state.state != IDLE)  return;
	933	}
	934
	935	// We're here when there is no live_run anymore
	936	// Where were we last time?
	937	switch (m_main_state)
	938	{
	939	case IDLE:
	940	break;
	941	case RESTORE:
	942	case STEP:
	943	step_drive_continue();
	944	break;
	945	case SELECT:
	946	// During drive_select there is no need to continue
	947	break;
	948	case READSECL:
	949	read_sector_continue();
	950	break;
	951	default:
	952	logerror("%s: [%s] general_continue on unknown main_state %d\n", tag(), ttsn().cstr(), m_main_state);
	953	break;
	954	}
	955	}
	956
	957	// ===========================================================================
	958
	959	/*
	960	Delivers the step time (in microseconds) minus the pulse width
	961	*/
	962	int hdc9234_device::get_step_time()
	963	{
	964	int time = 0;
	965	int index = m_register_w[MODE] & MO_STEPRATE;
	966	// Get seek time.
	967	if ((m_selected_drive_type & DRIVE_TYPE) == TYPE_FLOPPY8)
	968	time = step_flop8[index] - pulse_flop8;
	969
	970	else if ((m_selected_drive_type & DRIVE_TYPE) == TYPE_FLOPPY5)
	971	time = step_flop5[index] - pulse_flop5;
	972	else
	973	time = step_hd[index] - pulse_hd;
	974
	975	if (fm_mode()) time = time * 2;
	976	return time;
	977	}
	978
	979	/*
	980	Delivers the pulse width time (in microseconds)
	981	*/
	982	int hdc9234_device::pulse_width()
	983	{
	984	int time = 0;
	985	// Get seek time.
	986	if ((m_selected_drive_type & DRIVE_TYPE) == TYPE_FLOPPY8)
	987	time = pulse_flop8;
	988
	989	else if ((m_selected_drive_type & DRIVE_TYPE) == TYPE_FLOPPY5)
	990	time = pulse_flop5;
	991	else
	992	time = pulse_hd;
	993
	994	if (fm_mode()) time = time * 2;
	995	return time;
	996	}
	997
	998	/*
	999	Delivers the sector size
	1000	*/
	1001	int hdc9234_device::get_sector_size()
	1002	{
	1003	return 128 << (m_register_r[CURRENT_SIZE] & 3);
	1004	}
	1005
	1006	/*
	1007	===========================================================================
	1008
	1009	Live state machine
	1010
	1011	We follow a very similar approach to track access like in wd_fdc. The live
	1012	state machine attempts to find marks on the track, starting from the current
	1013	position. When found, it waits for the machine to catch up. When an event
	1014	happens in the meantime, the state machine is rolled back, and the actions
	1015	are replayed until the position where the event occured.
	1016
	1017	Lots of code is taken from wd_fdc, with some minor restructuring and renaming.
	1018	Same ideas, though. More comments.
	1019
	1020	===========================================================================
	1021	*/
	1022
	1023	astring hdc9234_device::tts(const attotime &t)
	1024	{
	1025	char buf[256];
	1026	int nsec = t.attoseconds / ATTOSECONDS_PER_NANOSECOND;
	1027	sprintf(buf, "%4d.%03d,%03d,%03d", int(t.seconds), nsec/1000000, (nsec/1000)%1000, nsec % 1000);
	1028	return buf;
	1029	}
	1030
	1031	astring hdc9234_device::ttsn()
	1032	{
	1033	return tts(machine().time());
	1034	}
	1035
	1036	/*
	1037	The controller starts to read bits from the disk. This method takes an
	1038	argument for the state machine called at the end.
	1039	*/
	1040	void hdc9234_device::live_start(int state)
	1041	{
	1042	if (TRACE_LIVE) logerror("%s: [%s] Live start substate=%d\n", tag(), ttsn().cstr(), state);
	1043	m_live_state.time = machine().time();
	1044	m_live_state.state = state;
	1045	m_live_state.next_state = -1;
	1046
	1047	m_live_state.shift_reg = 0;
	1048	m_live_state.crc = 0xffff;
	1049	m_live_state.bit_counter = 0;
	1050	m_live_state.data_separator_phase = false;
	1051	m_live_state.data_reg = 0;
	1052
	1053	pll_reset(m_live_state.time);
	1054	m_checkpoint_state = m_live_state;
	1055
	1056	// Save checkpoint
	1057	m_checkpoint_pll = m_pll;
	1058
	1059	live_run();
	1060	m_last_live_state = UNDEF;
	1061	}
	1062
	1063	void hdc9234_device::live_run()
	1064	{
	1065	live_run_until(attotime::never);
	1066	}
	1067
	1068	/*
	1069	The main method of the live state machine. We stay in this method until
	1070	the requested data are read.
	1071	limit: if unlimited (attotime::never), run up to the end of the track and wait there
	1072	otherwise, used to replay the read/write operation up to the point where the event happened
	1073	*/
	1074	void hdc9234_device::live_run_until(attotime limit)
	1075	{
	1076	int slot = 0;
	1077
	1078	if (TRACE_LIVE) logerror("%s: [%s] live_run, live_state=%d, fm_mode=%d\n", tag(), tts(m_live_state.time).cstr(), m_live_state.state, fm_mode()? 1:0);
	1079
	1080	if (m_live_state.state == IDLE || m_live_state.next_state != -1)
	1081	{
	1082	if (TRACE_LIVE) logerror("%s: [%s] live_run, state=%d, next_state=%d\n", tag(), tts(m_live_state.time).cstr(), m_live_state.state,m_live_state.next_state);
	1083	return;
	1084	}
	1085
	1086	if (limit == attotime::never)
	1087	{
	1088	// We did not specify an upper time bound, so we take the next index pulse
	1089	if (m_floppy != NULL) limit = m_floppy->time_next_index();
	1090
	1091	if (limit == attotime::never)
	1092	{
	1093	// We don't have an index pulse? (no disk?)
	1094	// See wd_fdc: Force a sync from time to time in that case
	1095	// so that the main cpu timeout isn't too painful.  Avoids
	1096	// looping into infinity looking for data too.
	1097	limit = machine().time() + attotime::from_msec(1);
	1098	m_timer->adjust(attotime::from_msec(1));
	1099	}
	1100	}
	1101
	1102	while (true)
	1103	{
	1104	switch (m_live_state.state)
	1105	{
	1106	case SEARCH_IDAM:
	1107
	1108	// We're doing this complicated logerror check to avoid
	1109	// repeated logging in the same state. This can be found for the
	1110	// other live states as well. m_last_live_state is only used to
	1111	// control this loggind.
	1112
	1113	if (TRACE_LIVE && m_last_live_state != SEARCH_IDAM)
	1114	logerror("%s: [%s] SEARCH_IDAM [limit %s]\n", tag(),tts(m_live_state.time).cstr(), tts(limit).cstr());
	1115	m_last_live_state = m_live_state.state;
	1116
	1117	// This bit will be set when the IDAM cannot be found
	1118	set_bits(m_register_r[CHIP_STATUS], CS_SYNCERR, false);
	1119
	1120	if (read_one_bit(limit))
	1121	{
	1122	if (TRACE_LIVE) logerror("%s: [%s] SEARCH_IDAM limit reached\n", tag(), tts(m_live_state.time).cstr());
	1123	return;
	1124	}
	1125	// logerror("%s: SEARCH_IDAM\n", tts(m_live_state.time).cstr());
	1126	if (TRACE_SHIFT) logerror("%s: shift = %04x data=%02x c=%d\n", tts(m_live_state.time).cstr(), m_live_state.shift_reg,
	1127	(m_live_state.shift_reg & 0x4000 ? 0x80 : 0x00) |
	1128	(m_live_state.shift_reg & 0x1000 ? 0x40 : 0x00) |
	1129	(m_live_state.shift_reg & 0x0400 ? 0x20 : 0x00) |
	1130	(m_live_state.shift_reg & 0x0100 ? 0x10 : 0x00) |
	1131	(m_live_state.shift_reg & 0x0040 ? 0x08 : 0x00) |
	1132	(m_live_state.shift_reg & 0x0010 ? 0x04 : 0x00) |
	1133	(m_live_state.shift_reg & 0x0004 ? 0x02 : 0x00) |
	1134	(m_live_state.shift_reg & 0x0001 ? 0x01 : 0x00),
	1135	m_live_state.bit_counter);
	1136
	1137	// [1] p. 9: The ID field sync mark must be found within 33,792 byte times
	1138	if (m_live_state.bit_count_total > 33792*16)
	1139	{
	1140	wait_for_realtime(SEARCH_IDAM_FAILED);
	1141	return;
	1142	}
	1143
	1144	if (!fm_mode())
	1145	{
	1146	// MFM case
	1147	if (m_live_state.shift_reg == 0x4489)
	1148	{
	1149	if (TRACE_LIVE) logerror("%s: [%s] Found an A1 mark\n", tag(),tts(m_live_state.time).cstr());
	1150	m_live_state.crc = 0x443b;
	1151	m_live_state.data_separator_phase = false;
	1152	m_live_state.bit_counter = 0;
	1153	// Next task: find the next two A1 marks
	1154	m_live_state.state = READ_TWO_MORE_A1_IDAM;
	1155	}
	1156	}
	1157	else
	1158	{
	1159	// FM case
	1160	if (m_live_state.shift_reg == 0xf57e)
	1161	{
	1162	if (TRACE_LIVE) logerror("%s: SEARCH_IDAM: IDAM found\n", tag());
	1163	m_live_state.crc = 0xef21;
	1164	m_live_state.data_separator_phase = false;
	1165	m_live_state.bit_counter = 0;
	1166	m_live_state.state = READ_ID_FIELDS_INTO_REGS;
	1167	}
	1168	}
	1169	break;
	1170
	1171	case SEARCH_IDAM_FAILED:
	1172	set_bits(m_register_r[CHIP_STATUS], CS_SYNCERR, true);
	1173	m_live_state.state = IDLE;
	1174	return;
	1175
	1176	case READ_TWO_MORE_A1_IDAM:     // This state only applies for MFM mode.
	1177
	1178	if (TRACE_LIVE && m_last_live_state != READ_TWO_MORE_A1_IDAM)
	1179	logerror("%s: [%s] READ_TWO_MORE_A1\n", tag(),tts(m_live_state.time).cstr());
	1180	m_last_live_state = m_live_state.state;
	1181
	1182	// Beyond time limit?
	1183	if (read_one_bit(limit)) return;
	1184
	1185	if (TRACE_SHIFT) logerror("%s: shift = %04x data=%02x c=%d\n", tts(m_live_state.time).cstr(), m_live_state.shift_reg,
	1186	(m_live_state.shift_reg & 0x4000 ? 0x80 : 0x00) |
	1187	(m_live_state.shift_reg & 0x1000 ? 0x40 : 0x00) |
	1188	(m_live_state.shift_reg & 0x0400 ? 0x20 : 0x00) |
	1189	(m_live_state.shift_reg & 0x0100 ? 0x10 : 0x00) |
	1190	(m_live_state.shift_reg & 0x0040 ? 0x08 : 0x00) |
	1191	(m_live_state.shift_reg & 0x0010 ? 0x04 : 0x00) |
	1192	(m_live_state.shift_reg & 0x0004 ? 0x02 : 0x00) |
	1193	(m_live_state.shift_reg & 0x0001 ? 0x01 : 0x00),
	1194	m_live_state.bit_counter);
	1195
	1196	if (m_live_state.bit_count_total > 33792*16)
	1197	{
	1198	wait_for_realtime(SEARCH_IDAM_FAILED);
	1199	return;
	1200	}
	1201
	1202	// Repeat until we have collected 16 bits
	1203	if(m_live_state.bit_counter & 15) break;
	1204
	1205	// So we now got 16 bits. Fill this value into the next slot. We expect two more A1 values.
	1206	slot = m_live_state.bit_counter >> 4;
	1207	if (slot < 3)
	1208	{
	1209	if (m_live_state.shift_reg != 0x4489)
	1210	{
	1211	// This ain't A1. Step back into the previous state (look for the next IDAM).
	1212	m_live_state.state = SEARCH_IDAM;
	1213	}
	1214	else
	1215	if (TRACE_LIVE) logerror("%s: [%s] Found an A1 mark\n", tag(),tts(m_live_state.time).cstr());
	1216	// Continue
	1217	break;
	1218	}
	1219
	1220	if (TRACE_LIVE) logerror("%s: [%s] Found data value %02X\n", tag(),tts(m_live_state.time).cstr(), m_live_state.data_reg);
	1221	if (m_live_state.data_reg != 0xfe)
	1222	{
	1223	// This may happen when we accidentally locked onto the DAM. Look for the next IDAM.
	1224	if (TRACE_LIVE) logerror("%s: Missing FE data after A1A1A1\n", tag());
	1225	m_live_state.state = SEARCH_IDAM;
	1226	break;
	1227	}
	1228
	1229	// We're here after we got the three A1 and FE
	1230	m_live_state.bit_counter = 0;
	1231	m_live_state.state = READ_ID_FIELDS_INTO_REGS;
	1232	break;
	1233
	1234	case READ_ID_FIELDS_INTO_REGS:
	1235	if (TRACE_LIVE && m_last_live_state != READ_ID_FIELDS_INTO_REGS)
	1236	logerror("%s: [%s] READ_ID_FIELDS_INTO_REGS\n", tag(),tts(m_live_state.time).cstr());
	1237	m_last_live_state = m_live_state.state;
	1238
	1239	if (read_one_bit(limit))
	1240	{
	1241	return;
	1242	}
	1243	// Already got 16 bits?
	1244	if (m_live_state.bit_counter & 15) break;
	1245
	1246	slot = (m_live_state.bit_counter >> 4)-1;
	1247
	1248	if (TRACE_LIVE) logerror("%s: slot %d = %02x, crc=%04x\n", tag(), slot, m_live_state.data_reg, m_live_state.crc);
	1249
	1250	// The id_field is an array of indexes into the chip registers.
	1251	// Thus we get the values properly assigned to the registers.
	1252	m_register_r[id_field[slot]] = m_live_state.data_reg;
	1253
	1254	if(slot > 4)
	1255	{
	1256	// We successfully read the ID fields; let's wait for the machine time to catch up.
	1257	// Live run is done here; it is the main state machine's turn again.
	1258	m_live_state.bit_count_total = 0;
	1259	wait_for_realtime(IDLE);
	1260	return;
	1261	}
	1262	break;
	1263
	1264	case SEARCH_DAM:
	1265	if (TRACE_LIVE && m_last_live_state != SEARCH_DAM)
	1266	logerror("%s: [%s] SEARCH_DAM\n", tag(),tts(m_live_state.time).cstr());
	1267	m_last_live_state = m_live_state.state;
	1268
	1269	set_bits(m_register_r[CHIP_STATUS], CS_DELDATA, false);
	1270
	1271	if(read_one_bit(limit))
	1272	return;
	1273
	1274	if (TRACE_SHIFT) logerror("%s: shift = %04x data=%02x c=%d\n", tts(m_live_state.time).cstr(), m_live_state.shift_reg,
	1275	(m_live_state.shift_reg & 0x4000 ? 0x80 : 0x00) |
	1276	(m_live_state.shift_reg & 0x1000 ? 0x40 : 0x00) |
	1277	(m_live_state.shift_reg & 0x0400 ? 0x20 : 0x00) |
	1278	(m_live_state.shift_reg & 0x0100 ? 0x10 : 0x00) |
	1279	(m_live_state.shift_reg & 0x0040 ? 0x08 : 0x00) |
	1280	(m_live_state.shift_reg & 0x0010 ? 0x04 : 0x00) |
	1281	(m_live_state.shift_reg & 0x0004 ? 0x02 : 0x00) |
	1282	(m_live_state.shift_reg & 0x0001 ? 0x01 : 0x00),
	1283	m_live_state.bit_counter);
	1284
	1285	if (!fm_mode())
	1286	{   // MFM
	1287	if(m_live_state.bit_counter > 43*16)
	1288	{
	1289	logerror("%s: SEARCH_DAM failed\n", tag());
	1290	wait_for_realtime(SEARCH_DAM_FAILED);
	1291	return;
	1292	}
	1293
	1294	if (m_live_state.bit_counter >= 28*16 && m_live_state.shift_reg == 0x4489)
	1295	{
	1296	if (TRACE_LIVE) logerror("%s: [%s] Found an A1 mark\n", tag(),tts(m_live_state.time).cstr());
	1297	m_live_state.crc = 0x443b;
	1298	m_live_state.data_separator_phase = false;
	1299	m_live_state.bit_counter = 0;
	1300	m_live_state.state = READ_TWO_MORE_A1_DAM;
	1301	}
	1302	}
	1303	else
	1304	{   // FM
	1305	if (m_live_state.bit_counter > 23*16)
	1306	{
	1307	logerror("%s: SEARCH_DAM failed\n", tag());
	1308	wait_for_realtime(SEARCH_DAM_FAILED);
	1309	return;
	1310	}
	1311
	1312	if (m_live_state.bit_counter >= 11*16 && (m_live_state.shift_reg == 0xf56a || m_live_state.shift_reg == 0xf56b ||
	1313	m_live_state.shift_reg == 0xf56e || m_live_state.shift_reg == 0xf56f)) {
	1314	if (TRACE_LIVE) logerror("%s: SEARCH_DAM: found DAM = %04x\n", tag(), m_live_state.shift_reg);
	1315	m_live_state.crc =
	1316	m_live_state.shift_reg == 0xf56a ? 0x8fe7 :
	1317	m_live_state.shift_reg == 0xf56b ? 0x9fc6 :
	1318	m_live_state.shift_reg == 0xf56e ? 0xafa5 :
	1319	0xbf84;
	1320	m_live_state.data_separator_phase = false;
	1321	m_live_state.bit_counter = 0;
	1322	m_live_state.state = READ_SECTOR_DATA;
	1323	}
	1324	}
	1325	break;
	1326
	1327	case READ_TWO_MORE_A1_DAM: {
	1328	if (TRACE_LIVE && m_last_live_state != READ_TWO_MORE_A1_DAM)
	1329	logerror("%s: [%s] READ_TWO_MORE_A1_DAM\n", tag(),tts(m_live_state.time).cstr());
	1330	m_last_live_state = m_live_state.state;
	1331
	1332	if(read_one_bit(limit))
	1333	return;
	1334
	1335	if (TRACE_SHIFT) logerror("%s: shift = %04x data=%02x c=%d\n", tts(m_live_state.time).cstr(), m_live_state.shift_reg,
	1336	(m_live_state.shift_reg & 0x4000 ? 0x80 : 0x00) |
	1337	(m_live_state.shift_reg & 0x1000 ? 0x40 : 0x00) |
	1338	(m_live_state.shift_reg & 0x0400 ? 0x20 : 0x00) |
	1339	(m_live_state.shift_reg & 0x0100 ? 0x10 : 0x00) |
	1340	(m_live_state.shift_reg & 0x0040 ? 0x08 : 0x00) |
	1341	(m_live_state.shift_reg & 0x0010 ? 0x04 : 0x00) |
	1342	(m_live_state.shift_reg & 0x0004 ? 0x02 : 0x00) |
	1343	(m_live_state.shift_reg & 0x0001 ? 0x01 : 0x00),
	1344	m_live_state.bit_counter);
	1345
	1346	// Repeat until we have collected 16 bits
	1347	if (m_live_state.bit_counter & 15) break;
	1348
	1349	// Fill this value into the next slot. We expect three A1 values.
	1350	int slot = m_live_state.bit_counter >> 4;
	1351
	1352	if (slot < 3)
	1353	{
	1354	if (m_live_state.shift_reg != 0x4489)
	1355	{
	1356	wait_for_realtime(SEARCH_DAM_FAILED);
	1357	return;
	1358	}
	1359	else
	1360	if (TRACE_LIVE) logerror("%s: [%s] Found an A1 mark\n", tag(),tts(m_live_state.time).cstr());
	1361	// Continue
	1362	break;
	1363	}
	1364
	1365	if (TRACE_LIVE) logerror("%s: [%s] Found data value %02X\n", tag(),tts(m_live_state.time).cstr(), m_live_state.data_reg);
	1366
	1367	if ((m_live_state.data_reg & 0xff) == 0xf8)
	1368	{
	1369	if (TRACE_LIVE) logerror("%s: Found deleted data mark F8 after DAM sync\n", tag());
	1370	set_bits(m_register_r[CHIP_STATUS], CS_DELDATA, true);
	1371	}
	1372	else
	1373	{
	1374	if ((m_live_state.data_reg & 0xff) != 0xfb)
	1375	{
	1376	if (TRACE_LIVE) logerror("%s: Missing FB/F8 data mark after DAM sync\n", tag());
	1377	wait_for_realtime(SEARCH_DAM_FAILED);
	1378	return;
	1379	}
	1380	}
	1381
	1382	m_live_state.bit_counter = 0;
	1383	m_live_state.state = READ_SECTOR_DATA;
	1384	break;
	1385	}
	1386	case SEARCH_DAM_FAILED:
	1387	if (TRACE_LIVE) logerror("%s: SEARCH_DAM failed\n", tag());
	1388	m_live_state.state = IDLE;
	1389	return;
	1390
	1391	case READ_SECTOR_DATA:
	1392	{
	1393	if (TRACE_LIVE && m_last_live_state != READ_SECTOR_DATA)
	1394	logerror("%s: [%s] READ_SECTOR_DATA\n", tag(),tts(m_live_state.time).cstr());
	1395	m_last_live_state = m_live_state.state;
	1396
	1397	if(read_one_bit(limit))
	1398	return;
	1399
	1400	// Request bus release at the first bit of each byte (floppy; [1], fig 5 and 6)
	1401	if ((m_command & 0x01)!=0) // transfer enabled
	1402	{
	1403	if ((m_live_state.bit_counter & 15)== 1)
	1404	{
	1405	set_bits(m_register_r[INT_STATUS], ST_OVRUN, true);
	1406	m_out_dmarq(ASSERT_LINE);
	1407	}
	1408	}
	1409
	1410	// Repeat until we have collected 16 bits
	1411	if (m_live_state.bit_counter & 15) break;
	1412
	1413	if (TRACE_LIVE) logerror("%s: [%s] Found data value %02X, CRC=%04x\n", tag(),tts(m_live_state.time).cstr(), m_live_state.data_reg, m_live_state.crc);
	1414	int slot = (m_live_state.bit_counter >> 4)-1;
	1415
	1416	if (slot < get_sector_size())
	1417	{
	1418	// Sector data
	1419	wait_for_realtime(READ_SECTOR_DATA1);
	1420	return;
	1421	}
	1422	else if (slot < get_sector_size()+2)
	1423	{
	1424	// CRC
	1425	if (slot == get_sector_size()+1)
	1426	{
	1427	if (TRACE_LIVE) logerror("%s: [%s] Sector read completed\n", tag(),tts(m_live_state.time).cstr());
	1428	wait_for_realtime(IDLE);
	1429	return;
	1430	}
	1431	}
	1432	break;
	1433	}
	1434
	1435	case READ_SECTOR_DATA1:
	1436	if (TRACE_LIVE && m_last_live_state != READ_SECTOR_DATA1)
	1437	logerror("%s: [%s] READ_SECTOR_DATA1\n", tag(),tts(m_live_state.time).cstr());
	1438	m_last_live_state = m_live_state.state;
	1439
	1440	// Did the system CPU send the DMA ACK in the meantime?
	1441	if ((m_register_r[INT_STATUS] & ST_OVRUN)!=0)
	1442	{
	1443	if (TRACE_LIVE) logerror("%s: No DMA ACK - buffer overrun\n", tag());
	1444	set_bits(m_register_r[INT_STATUS], TC_DATAERR, true);
	1445	m_live_state.state = IDLE;
	1446	return;
	1447	}
	1448
	1449	if ((m_command & 0x01)!=0)  // transfer enabled
	1450	{
	1451	m_out_dip(ASSERT_LINE);
	1452	m_out_dma(0, m_live_state.data_reg, 0xff);
	1453	m_out_dip(CLEAR_LINE);
	1454
	1455	m_out_dmarq(CLEAR_LINE);
	1456	}
	1457
	1458	m_live_state.state = READ_SECTOR_DATA;
	1459	checkpoint();
	1460	break;
	1461
	1462	default:
	1463	logerror("%s: Unknown live state: %02x\n", tag(), m_live_state.state);
	1464	m_last_live_state = m_live_state.state;
	1465	return;
	1466	}
	1467	}
	1468	m_last_live_state = UNDEF;
	1469	}
	1470
	1471	/*
	1472	Synchronize the live position on the track with the real time.
	1473	Results in a new checkpoint and a live position at machine time or behind.
	1474	As a side effect, portions of the track may be re-read
	1475	*/
	1476	void hdc9234_device::live_sync()
	1477	{
	1478	// Do we have some time set?
	1479	if (!m_live_state.time.is_never())
	1480	{
	1481	// Are we ahead of the machine time?
	1482	if(m_live_state.time > machine().time())
	1483	{
	1484	// If so, we must roll back to the last checkpoint
	1485	if (TRACE_SYNC) logerror("%s: [%s] Rolling back and replaying (%s)\n", tag(), ttsn().cstr(), tts(m_live_state.time).cstr());
	1486	rollback();
	1487	// and replay until we reach the machine time
	1488	live_run_until(machine().time());
	1489	// Caught up, commit that
	1490	m_pll.commit(m_floppy, m_live_state.time);
	1491	}
	1492	else
	1493	{
	1494	// We are behind machine time, so we will never get back to that
	1495	// time, thus we can commit that position
	1496	if (TRACE_SYNC) logerror("%s: [%s] Committing (%s)\n", tag(), ttsn().cstr(), tts(m_live_state.time).cstr());
	1497	m_pll.commit(m_floppy, m_live_state.time);
	1498
	1499	if (m_live_state.next_state != -1)
	1500	{
	1501	m_live_state.state = m_live_state.next_state;
	1502	}
	1503
	1504	if (m_live_state.state == IDLE)
	1505	{
	1506	m_pll.stop_writing(m_floppy, m_live_state.time);
	1507	m_live_state.time = attotime::never;
	1508	}
	1509	}
	1510
	1511	m_live_state.next_state = -1;
	1512	checkpoint();
	1513	}
	1514	}
	1515
	1516	void hdc9234_device::rollback()
	1517	{
	1518	m_live_state = m_checkpoint_state;
	1519	m_pll = m_checkpoint_pll;
	1520	}
	1521
	1522	/*
	1523	Wait for real time to catch up. This way we pretend that the last
	1524	operation actually needed the real time.
	1525	*/
	1526	void hdc9234_device::wait_for_realtime(int state)
	1527	{
	1528	m_live_state.next_state = state;
	1529	m_timer->adjust(m_live_state.time - machine().time());
	1530	if (TRACE_LIVE) logerror("%s: [%s] Waiting for real time [%s] to catch up\n", tag(), tts(m_live_state.time).cstr(), tts(machine().time()).cstr());
	1531	}
	1532
	1533	/*
	1534	Read the next bit from the disk.
	1535	Return true: the time limit has been reached
	1536	Return false: The next bit is read into the shift register as the
	1537	rightmost bit; the shift register is a member of m_live_state. Also,
	1538	the CRC is updated.
	1539	*/
	1540	bool hdc9234_device::read_one_bit(const attotime &limit)
	1541	{
	1542	// Get the next bit from the phase-locked loop.
	1543	int bit = m_pll.get_next_bit(m_live_state.time, m_floppy, limit);
	1544
	1545	// We have reached the time limit
	1546	if (bit < 0) return true;
	1547
	1548	// For test purposes: Drop a bit at some occasions
	1549	// value > 1000: rare occasions
	1550	// value = 500: can cope with
	1551	// value < 100: big trouble for controller, will fail
	1552	if (UNRELIABLE_MEDIA)
	1553	{
	1554	if ((machine().time().attoseconds % 1009)==0) bit = 0;
	1555	}
	1556
	1557	// Push into shift register
	1558	m_live_state.shift_reg = (m_live_state.shift_reg << 1) | bit;
	1559	m_live_state.bit_counter++;
	1560
	1561	// Used for timeout handling
	1562	m_live_state.bit_count_total++;
	1563
	1564	// Clock bit (false) or data bit (true)?
	1565	if (m_live_state.data_separator_phase==true)
	1566	{
	1567	m_live_state.data_reg = (m_live_state.data_reg << 1) | bit;
	1568	// Update CRC
	1569	if ((m_live_state.crc ^ (bit ? 0x8000 : 0x0000)) & 0x8000)
	1570	m_live_state.crc = (m_live_state.crc << 1) ^ 0x1021;
	1571	else
	1572	m_live_state.crc = m_live_state.crc << 1;
	1573	}
	1574
	1575	m_live_state.data_separator_phase = !m_live_state.data_separator_phase;
	1576	return false;
	1577	}
	1578
	1579	void hdc9234_device::pll_reset(const attotime &when)
	1580	{
	1581	m_pll.reset(when);
	1582	// In FM mode, cells are 4 ??s long; in MFM they are 2 ??s long.
	1583	m_pll.set_clock(attotime::from_usec(fm_mode()? 4 : 2));
	1584	}
	1585
	1586	void hdc9234_device::checkpoint()
	1587	{
	1588	m_pll.commit(m_floppy, m_live_state.time);
	1589	m_checkpoint_state = m_live_state;
	1590	m_checkpoint_pll = m_pll;
	1591	}
	1592
	1593	// ===========================================================================
	1594
	1595	/*
322	1596	This is pretty simple here, compared to wd17xx, because index and ready
323	1597	callbacks have to be tied to the controller board outside the chip.
324	1598	*/
r31972	r31973
339	1613	{
340	1614	// Data register
341	1615	reply = m_register_r[m_register_pointer];
342		if (TRACE_REG) logerror("%s: register[%d] -> %02x\n", tag(), m_register_pointer, reply);
	1616	if (TRACE_REG) logerror("%s: read register[%d] -> %02x\n", tag(), m_register_pointer, reply);
343	1617
344	1618	// Autoincrement until DATA is reached.
345	1619	if (m_register_pointer < DATA)  m_register_pointer++;
r31972	r31973
351	1625
352	1626	// "The interrupt pin is reset to its inactive state
353	1627	// when the UDC interrupt status register is read." [1] (p.3)
354		if (TRACE_REG) logerror("%s: interrupt status register -> %02x\n", tag(), reply);
	1628	if (TRACE_REG) logerror("%s: read interrupt status register -> %02x\n", tag(), reply);
355	1629	set_interrupt(CLEAR_LINE);
356	1630
357	1631	// Clear the bits due to interrupt status register read.
r31972	r31973
362	1636
363	1637	/*
364	1638	Write a byte to the controller
365		The address (offset) encodes the C/D* line (command and /data)
	1639	The address (offset) encodes the C/D* line (command and /data), so there
	1640	are only two addresses: 0 (register) and 1 (command).
	1641	The operation terminates immediately, and the controller picks up the
	1642	values stored in this phase at a later time.
366	1643	*/
367	1644	WRITE8_MEMBER( hdc9234_device::write )
368	1645	{
369		//  logerror("%s: Write access to %04x: %d\n", tag(), offset & 0xffff, data);
	1646	m_data = data & 0xff;
370	1647
371		data &= 0xff;
372		if ((offset & 1)==0)
	1648	if ((offset & 1) == 0)
373	1649	{
374		// Writing data to registers
	1650	wait_time(m_cmd_timer, attotime::from_nsec(REGISTER_COMMIT), 0);
	1651	}
	1652	else
	1653	{
	1654	if (m_command != NOCMD)
	1655	{
	1656	logerror("%s: [%s] Error - previous command %02x not completed; new command %02x ignored\n", tag(), ttsn().cstr(), m_command, m_data);
	1657	}
	1658	else
	1659	{
	1660	wait_time(m_cmd_timer, attotime::from_nsec(COMMAND_COMMIT), 1);
	1661	}
	1662	}
	1663	}
375	1664
376		// Data register
377		if (TRACE_REG) logerror("%s: register[%d] <- %02x\n", tag(), m_register_pointer, data);
378		m_register_w[m_register_pointer] = data;
	1665	/*
	1666	When the commit period has passed, process the command.
	1667	*/
	1668	void hdc9234_device::command_continue()
	1669	{
	1670	// Reset DONE and BAD_SECTOR [1], p.7
	1671	set_bits(m_register_r[INT_STATUS], ST_DONE | ST_BADSECT, false);
379	1672
380		// The DMA registers and the sector register for read and
381		// write are identical, so in that case we copy the contents
382		if (m_register_pointer < DESIRED_HEAD)  m_register_r[m_register_pointer] = data;
	1673	// Reset interrupt line (not explicitly mentioned in spec, but seems reasonable
	1674	set_interrupt(CLEAR_LINE);
383	1675
384		// Autoincrement until DATA is reached.
385		if (m_register_pointer < DATA)  m_register_pointer++;
	1676	// Clear Interrupt Pending and Ready Change
	1677	set_bits(m_register_r[INT_STATUS], ST_INTPEND | ST_RDYCHNG, false);
	1678
	1679	m_command = m_data;
	1680	m_stop_after_index = false;
	1681	m_wait_for_index = false;
	1682
	1683	int index = 0;
	1684	m_main_state = UNDEF;
	1685	while (s_command[index].mask!=0 && m_main_state == UNDEF)
	1686	{
	1687	if ((m_command & s_command[index].mask) == s_command[index].baseval)
	1688	{
	1689	// Invoke command
	1690	m_main_state = s_command[index].state;
	1691	(this->*s_command[index].command)();
	1692	}
	1693	index++;
386	1694	}
387		else
	1695	if (m_main_state==UNDEF)
388	1696	{
389		process_command(data);
	1697	logerror("%s: Command %02x not defined\n", tag(), m_command);
390	1698	}
391	1699	}
392	1700
393	1701	/*
	1702	When the commit period has passed, process the register write operation.
	1703	*/
	1704	void hdc9234_device::register_write_continue()
	1705	{
	1706	// Writing data to registers
	1707	// Data register
	1708	if (TRACE_REG)
	1709	{
	1710	if (m_register_pointer == INT_COMM_TERM)
	1711	logerror("%s: Setting interrupt trigger DONE=%d READY=%d\n", tag(), (m_data & TC_INTDONE)? 1:0, (m_data & TC_INTRDCH)? 1:0);
	1712	else
	1713	logerror("%s: register[%d] <- %02x\n", tag(), m_register_pointer, m_data);
	1714	}
	1715	m_register_w[m_register_pointer] = m_data;
	1716
	1717	// The DMA registers and the sector register for read and
	1718	// write are identical, so in that case we copy the contents
	1719	if (m_register_pointer < DESIRED_HEAD) m_register_r[m_register_pointer] = m_data;
	1720
	1721	// Autoincrement until DATA is reached.
	1722	if (m_register_pointer < DATA)  m_register_pointer++;
	1723	}
	1724
	1725	/*
394	1726	Auxiliary bus operation.
395	1727
396	1728	The auxbus of the HDC9234 is used to poll the drive status of the cur-
r31972	r31973
461	1793	*/
462	1794	void hdc9234_device::auxbus_in(UINT8 data)
463	1795	{
464		if (TRACE_ACT) logerror("%s: Got value %02x via auxbus\n", tag(), data);
	1796	// Kill unwanted input via auxbus until we are initialized.
	1797	if (!m_initialized)
	1798	return;
	1799
	1800	if (TRACE_ACT) logerror("%s: Got value %02x via auxbus: ecc=%d index=%d seek_comp=%d tr00=%d user=%d writeprot=%d ready=%d fault=%d\n",
	1801	tag(), data,
	1802	(data&HDC_DS_ECCERR)? 1:0, (data&HDC_DS_INDEX)? 1:0,
	1803	(data&HDC_DS_SKCOM)? 1:0, (data&HDC_DS_TRK00)? 1:0,
	1804	(data&HDC_DS_UDEF)? 1:0, (data&HDC_DS_WRPROT)? 1:0,
	1805	(data&HDC_DS_READY)? 1:0, (data&HDC_DS_WRFAULT)? 1:0);
465	1806	UINT8 prev = m_register_r[DRIVE_STATUS];
466	1807	m_register_r[DRIVE_STATUS] = data;
467	1808
468		// Raise interrupt if ready changes.
469		if (((m_register_r[DRIVE_STATUS] & HDC_DS_READY) != (prev & HDC_DS_READY))
470		& (m_register_r[INT_STATUS] & ST_RDYCHNG))
	1809	if ((prev & HDC_DS_INDEX) != (data &  HDC_DS_INDEX))
471	1810	{
	1811	// Check whether index value changed
	1812	index_callback((data & HDC_DS_INDEX)? ASSERT_LINE : CLEAR_LINE);
	1813	}
	1814
	1815	if ((prev & HDC_DS_READY) != (data & HDC_DS_READY))
	1816	{
	1817	// Check whether ready value changed
	1818	ready_callback((data & HDC_DS_READY)? ASSERT_LINE : CLEAR_LINE);
	1819	}
	1820
	1821	if ((prev & HDC_DS_SKCOM) != (data & HDC_DS_SKCOM))
	1822	{
	1823	// Check whether seek complete value changed
	1824	seek_complete_callback((data & HDC_DS_SKCOM)? ASSERT_LINE : CLEAR_LINE);
	1825	}
	1826	}
	1827
	1828	void hdc9234_device::index_callback(int level)
	1829	{
	1830	if (TRACE_ACT) logerror("%s: [%s] Index callback level=%d\n", tag(), ttsn().cstr(), level);
	1831
	1832	// Synchronize our position on the track
	1833	live_sync();
	1834
	1835	if (level==CLEAR_LINE) {
	1836	general_continue();
	1837	return;
	1838	}
	1839	else
	1840	{
	1841	// ...
	1842	if (m_wait_for_index) m_stop_after_index = true;
	1843	general_continue();
	1844	}
	1845	}
	1846
	1847	void hdc9234_device::ready_callback(int level)
	1848	{
	1849	if (TRACE_ACT) logerror("%s: [%s] Ready callback level=%d\n", tag(), ttsn().cstr(), level);
	1850
	1851	// Set the interrupt status flag
	1852	set_bits(m_register_r[INT_STATUS], ST_RDYCHNG, true);
	1853
	1854	// Synchronize our position on the track
	1855	live_sync();
	1856
	1857	// Raise an interrupt if desired
	1858	if (m_register_w[INT_COMM_TERM] & TC_INTRDCH)
	1859	{
	1860	if (TRACE_ACT) logerror("%s: Raise interrupt READY change\n", tag());
472	1861	set_interrupt(ASSERT_LINE);
473	1862	}
474	1863	}
475	1864
	1865	void hdc9234_device::seek_complete_callback(int level)
	1866	{
	1867	if (TRACE_ACT) logerror("%s: [%s] Seek complete callback level=%d\n", tag(), ttsn().cstr(), level);
	1868
	1869	// Synchronize our position on the track
	1870	live_sync();
	1871
	1872	if (level==ASSERT_LINE && m_next_state != UNDEF)
	1873	{
	1874	m_substate = m_next_state;
	1875	general_continue();
	1876	}
	1877	}
	1878
	1879	void hdc9234_device::wait_line(int substate)
	1880	{
	1881	m_next_state = substate;
	1882	}
	1883
	1884	bool hdc9234_device::on_track00()
	1885	{
	1886	return (m_register_r[DRIVE_STATUS] & HDC_DS_TRK00)!=0;
	1887	}
	1888
476	1889	/*
477	1890	Push the output registers over the auxiliary bus. It is expected that
478	1891	the PCB contains latches to store the values.
479	1892	*/
480	1893	void hdc9234_device::sync_latches_out()
481	1894	{
	1895	if (TRACE_ACT) logerror("%s: Setting OUTPUT1 to %02x\n", tag(), m_output1);
482	1896	m_out_auxbus((offs_t)HDC_OUTPUT_1, m_output1);
483	1897	set_bits(m_output2, OUT2_DRVSEL3I, (m_output1 & 0x80)==0);
	1898	if (TRACE_ACT) logerror("%s: Setting OUTPUT2 to %02x\n", tag(), m_output2);
484	1899	m_out_auxbus((offs_t)HDC_OUTPUT_2, m_output2);
485	1900	}
486	1901
	1902	void hdc9234_device::dma_address_out()
	1903	{
	1904	if (TRACE_ACT) logerror("%s: Setting DMA address %06x\n", tag(), (m_register_w[DMA23_16]<<16 | m_register_w[DMA15_8]<<8 | m_register_w[DMA7_0])&0xffffff);
	1905	m_out_auxbus((offs_t)HDC_OUTPUT_DMA_ADDR, m_register_w[DMA23_16]);
	1906	m_out_auxbus((offs_t)HDC_OUTPUT_DMA_ADDR, m_register_w[DMA15_8]);
	1907	m_out_auxbus((offs_t)HDC_OUTPUT_DMA_ADDR, m_register_w[DMA7_0]);
	1908	}
	1909
487	1910	/*
	1911	This is reached when a timer has expired
	1912	*/
	1913	void hdc9234_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
	1914	{
	1915	if (TRACE_ACT) logerror("%s: [%s] Timer id=%d expired\n", tag(), ttsn().cstr(), id);
	1916	live_sync();
	1917
	1918	switch (id)
	1919	{
	1920	case GEN_TIMER:
	1921	general_continue();
	1922	break;
	1923	case COM_TIMER:
	1924	if (m_substate==1) command_continue();
	1925	else register_write_continue();
	1926	break;
	1927	case LIVE_TIMER:
	1928	live_run();
	1929	break;
	1930	}
	1931	}
	1932
	1933	/*
	1934	DMA acknowledge line.
	1935	*/
	1936	WRITE_LINE_MEMBER( hdc9234_device::dmaack )
	1937	{
	1938	if (state==ASSERT_LINE)
	1939	{
	1940	if (TRACE_ACT) logerror("%s: [%s] DMA acknowledged\n", tag(), ttsn().cstr());
	1941	set_bits(m_register_r[INT_STATUS], ST_OVRUN, false);
	1942	}
	1943	}
	1944
	1945	/*
488	1946	Reset the controller. Negative logic, but we use ASSERT_LINE.
489	1947	*/
490	1948	WRITE_LINE_MEMBER( hdc9234_device::reset )
491	1949	{
492	1950	if (state == ASSERT_LINE)
493	1951	{
494		logerror("%s: Reset via RST line\n", tag());
	1952	if (TRACE_ACT) logerror("%s: Reset via RST line\n", tag());
495	1953	device_reset();
496	1954	}
497	1955	}
498	1956
499	1957	void hdc9234_device::device_start()
500	1958	{
501		logerror("%s: start\n", tag());
	1959	logerror("%s: Start\n", tag());
502	1960	m_out_intrq.resolve_safe();
503	1961	m_out_dip.resolve_safe();
504	1962	m_out_auxbus.resolve_safe();
	1963	m_out_dmarq.resolve_safe();
505	1964	m_out_dma.resolve_safe();
506	1965	m_in_dma.resolve_safe(0);
507	1966
508	1967	// allocate timers
	1968	m_timer = timer_alloc(GEN_TIMER);
	1969	m_cmd_timer = timer_alloc(COM_TIMER);
	1970	m_live_timer = timer_alloc(LIVE_TIMER);
	1971
	1972	m_live_state.state = IDLE;
509	1973	}
510	1974
511	1975	void hdc9234_device::device_reset()
512	1976	{
513		m_command = 0;
	1977	logerror("%s: Reset\n", tag());
	1978
514	1979	m_selected_drive_type = 0;
515	1980	m_head_load_delay_enable = false;
516	1981	m_register_pointer = 0;
r31972	r31973
519	1984
520	1985	set_interrupt(CLEAR_LINE);
521	1986	m_out_dip(CLEAR_LINE);
	1987	m_out_dmarq(CLEAR_LINE);
522	1988
523	1989	for (int i=0; i<=11; i++)
524	1990	m_register_r[i] = m_register_w[i] = 0;
	1991
	1992	m_step_direction = 0;
	1993
	1994	m_next_state = IDLE;
	1995	m_seek_count = 0;
	1996
	1997	m_live_state.time = attotime::never;
	1998	m_live_state.state = IDLE;
	1999	m_initialized = true;
	2000
	2001	m_track_delta = 0;
	2002
	2003	m_multi_sector = false;
	2004	m_retry_save = 0;
	2005
	2006	m_substate = IDLE;
	2007	m_main_state = IDLE;
	2008	m_command = NOCMD;
	2009
	2010	m_stop_after_index = false;
	2011	m_wait_for_index = false;
	2012
	2013	m_data = 0;
525	2014	}
526	2015
527	2016	const device_type HDC9234 = &device_creator<hdc9234_device>;

trunk/src/emu/machine/hdc9234.h

r31972	r31973
9	9
10	10	#include "emu.h"
11	11	#include "imagedev/floppy.h"
	12	#include "fdc_pll.h"
12	13
13	14	extern const device_type HDC9234;
14	15
r31972	r31973
45	46	#define MCFG_HDC9234_INTRQ_CALLBACK(_write) \
46	47	devcb = &hdc9234_device::set_intrq_wr_callback(*device, DEVCB_##_write);
47	48
	49	/* DMA request line. To be connected with the controller PCB. */
	50	#define MCFG_HDC9234_DMARQ_CALLBACK(_write) \
	51	devcb = &hdc9234_device::set_dmarq_wr_callback(*device, DEVCB_##_write);
	52
48	53	/* DMA in progress line. To be connected with the controller PCB. */
49	54	#define MCFG_HDC9234_DIP_CALLBACK(_write) \
50	55	devcb = &hdc9234_device::set_dip_wr_callback(*device, DEVCB_##_write);
r31972	r31973
78	83	DECLARE_READ8_MEMBER( read );
79	84	DECLARE_WRITE8_MEMBER( write );
80	85	DECLARE_WRITE_LINE_MEMBER( reset );
	86	DECLARE_WRITE_LINE_MEMBER( dmaack );
81	87
82	88	// Callbacks
83	89	template<class _Object> static devcb_base &set_intrq_wr_callback(device_t &device, _Object object) { return downcast<hdc9234_device &>(device).m_out_intrq.set_callback(object); }
	90	template<class _Object> static devcb_base &set_dmarq_wr_callback(device_t &device, _Object object) { return downcast<hdc9234_device &>(device).m_out_dmarq.set_callback(object); }
84	91	template<class _Object> static devcb_base &set_dip_wr_callback(device_t &device, _Object object) { return downcast<hdc9234_device &>(device).m_out_dip.set_callback(object); }
85	92	template<class _Object> static devcb_base &set_auxbus_wr_callback(device_t &device, _Object object) { return downcast<hdc9234_device &>(device).m_out_auxbus.set_callback(object); }
86	93	template<class _Object> static devcb_base &set_dma_rd_callback(device_t &device, _Object object) { return downcast<hdc9234_device &>(device).m_in_dma.set_callback(object); }
r31972	r31973
102	109
103	110	private:
104	111	devcb_write_line   m_out_intrq;    // INT line
	112	devcb_write_line   m_out_dmarq;    // DMA request line
105	113	devcb_write_line   m_out_dip;      // DMA in progress line
106	114	devcb_write8       m_out_auxbus;   // AB0-7 lines (using S0,S1 as address)
107	115	devcb_read8        m_in_dma;       // DMA read access to the cache buffer
r31972	r31973
111	119	int m_register_pointer;
112	120
113	121	// Read and write registers
114		UINT8 m_register_r[12];
115	122	UINT8 m_register_w[12];
	123	UINT8 m_register_r[15];
116	124
117	125	// Command processing
118	126	void  process_command(UINT8 opcode);
r31972	r31973
121	129	void set_command_done(int flags);
122	130	void set_command_done();
123	131
	132	// Are we in FM mode?
	133	bool fm_mode();
	134
124	135	// Recent command.
125	136	UINT8 m_command;
126	137
r31972	r31973
136	147	// internal register OUTPUT2
137	148	UINT8 m_output2;
138	149
	150	// Direction for track seek; +1 = towards center, -1 = towards rim
	151	int m_step_direction;
	152
139	153	// Write the output registers to the latches
140	154	void sync_latches_out();
141	155
	156	// Write the DMA address to the external latches
	157	void dma_address_out();
	158
142	159	// Utility routine to set or reset bits
143	160	void set_bits(UINT8& byte, int mask, bool set);
144	161
r31972	r31973
148	165	// Enable head load delays
149	166	bool m_head_load_delay_enable;
150	167
	168	// Timers to delay execution/completion of commands */
	169	emu_timer *m_timer;
	170	emu_timer *m_cmd_timer;
	171	emu_timer *m_live_timer;
	172
	173	// Timer callback
	174	void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
	175
	176	// Phase-locked loops
	177	fdc_pll_t m_pll, m_checkpoint_pll;
	178
	179	void ready_callback(int level);
	180	void index_callback(int level);
	181	void seek_complete_callback(int level);
	182
	183	void wait_time(emu_timer *tm, int microsec, int next_substate);
	184	void wait_time(emu_timer *tm, attotime delay, int param);
	185
	186	bool on_track00();
	187	void wait_line(int substate);
151	188	// ===================================================
	189	//   Utility functions
	190	// ===================================================
	191
	192	astring tts(const attotime &t);
	193	astring ttsn();
	194
	195	// ===================================================
	196	//   Live state machine
	197	// ===================================================
	198
	199	struct live_info
	200	{
	201	attotime time;
	202	UINT16 shift_reg;
	203	UINT16 crc;
	204	int bit_counter;
	205	int bit_count_total;    // used for timeout handling
	206	bool data_separator_phase;
	207	UINT8 data_reg;
	208	int state;
	209	int next_state;
	210	};
	211
	212	void live_start(int state);
	213	void live_run();
	214	void live_run_until(attotime limit);
	215	void wait_for_realtime(int state);
	216	void live_sync();
	217	void rollback();
	218
	219	void checkpoint();
	220
	221	live_info m_live_state, m_checkpoint_state;
	222
	223	// ===================================================
	224	//   PLL functions and interface to floppy
	225	// ===================================================
	226
	227	void pll_reset(const attotime &when);
	228	bool read_one_bit(const attotime &limit);
	229
	230	int get_sector_size();
	231
	232	// ===================================================
152	233	//   Commands
153	234	// ===================================================
154		void drive_select(int driveparm);
	235
	236	void process_states();
	237	void general_continue();
	238
	239	int m_main_state;
	240	int m_substate;
	241	int m_next_state;
	242	int m_last_live_state;
	243	int m_track_delta;
	244	int m_retry_save;
	245	bool m_multi_sector;
	246	bool m_wait_for_index;
	247	bool m_stop_after_index;
	248	bool m_initialized;
	249
	250	// Intermediate storage
	251	UINT8 m_data;
	252
	253	typedef void (hdc9234_device::*cmdfunc)(void);
	254
	255	typedef struct
	256	{
	257	UINT8 baseval;
	258	UINT8 mask;
	259	int state;
	260	cmdfunc command;
	261	} cmddef;
	262
	263	static const cmddef s_command[];
	264
	265	int get_step_time();
	266	int pulse_width();
	267
	268	int m_seek_count;
	269
	270	void command_continue();
	271	void register_write_continue();
	272
	273	// Commands
	274	void drive_select();
	275	void drive_deselect();
	276	void restore_drive();
	277	void step_drive();
	278	void step_drive_continue();
	279	void set_register_pointer();
	280	void read_sector_physical();
	281	void read_sector_logical();
	282	void read_sector_continue();
155	283	};
156	284
157	285	#endif

trunk/src/emu/bus/ti99_peb/hfdc.c

r31972	r31973
72	72	#define CLK_ADDR    0x0fe0
73	73	#define RAM_ADDR    0x1000
74	74
75		#define TRACE_EMU 1
76		#define TRACE_CRU 1
77		#define TRACE_COMP 1
	75	#define TRACE_EMU 0
	76	#define TRACE_CRU 0
	77	#define TRACE_COMP 0
78	78	#define TRACE_RAM 0
79	79	#define TRACE_ROM 0
80		#define TRACE_LINES 1
81		#define TRACE_MOTOR 1
	80	#define TRACE_LINES 0
	81	#define TRACE_MOTOR 0
	82	#define TRACE_DMA 0
82	83
83	84	// =========================================================================
84	85
r31972	r31973
179	180	// 0101 11xx xxxx xxxx  bank 3
180	181	int bank = (m_address & 0x0c00) >> 10;
181	182	*value = m_buffer_ram[(m_ram_page[bank]<<10) | (m_address & 0x03ff)];
182		if (TRACE_RAM) logerror("%s: %04x[%02x] -> %02x\n", tag(), m_address & 0xffff, m_ram_page[bank], *value);
	183	if (TRACE_RAM)
	184	{
	185	if ((m_address & 1)==0)  // only show even addresses with words
	186	{
	187	int valword = (((*value) << 8) | m_buffer_ram[(m_ram_page[bank]<<10) | ((m_address+1) & 0x03ff)])&0xffff;
	188	logerror("%s: %04x[%02x] -> %04x\n", tag(), m_address & 0xffff, m_ram_page[bank], valword);
	189	}
	190	}
183	191	return;
184	192	}
185	193
186	194	if (m_ROMsel)
187	195	{
188	196	*value = m_dsrrom[(m_rom_page << 12) | (m_address & 0x0fff)];
189		if (TRACE_ROM) logerror("%s: %04x[%02x] -> %02x\n", tag(), m_address & 0xffff, m_rom_page, *value);
	197	if (TRACE_ROM)
	198	{
	199	if ((m_address & 1)==0)  // only show even addresses with words
	200	{
	201	int valword = (((*value) << 8) | m_dsrrom[(m_rom_page << 12) | ((m_address + 1) & 0x0fff)])&0xffff;
	202	logerror("%s: %04x[%02x] -> %04x\n", tag(), m_address & 0xffff, m_rom_page, valword);
	203	}
	204	}
190	205	return;
191	206	}
192	207	}
r31972	r31973
381	396	m_CD = (data != 0)? (m_CD | 1) : (m_CD & 0xfe);
382	397
383	398	// Activate motor
384		if (data==0 && m_lastval==1)
385		{   // on falling edge, set motor_running for 4.23s
386		if (TRACE_CRU) logerror("%s: trigger motor (falling edge)\n", tag());
	399	// When 1, let motor run continuously. When 0, a simple monoflop circuit keeps the line active for another 4 sec
	400	// We keep triggering the monoflop for data==1
	401	if (data==1)
	402	{
	403	if (TRACE_CRU) logerror("%s: trigger motor\n", tag());
387	404	set_floppy_motors_running(true);
388	405	}
389	406	m_lastval = data;
r31972	r31973
420	437	*/
421	438	void myarc_hfdc_device::floppy_index_callback(floppy_image_device *floppy, int state)
422	439	{
423		logerror("%s: Index callback level=%d\n", tag(), state);
	440	if (TRACE_LINES) if (state==1) logerror("%s: Index pulse\n", tag());
424	441	// m_status_latch = (state==ASSERT_LINE)? (m_status_latch | HDC_DS_INDEX) :  (m_status_latch & ~HDC_DS_INDEX);
425	442	set_bits(m_status_latch, HDC_DS_INDEX, (state==ASSERT_LINE));
426	443	signal_drive_status();
r31972	r31973
453	470	void myarc_hfdc_device::signal_drive_status()
454	471	{
455	472	UINT8 reply = 0;
456		//int index = 0;
457
458	473	// Status byte as defined by HDC9234
459	474	// +------+------+------+------+------+------+------+------+
460	475	// | ECC  |Index | SeekC| Tr00 | User | WrPrt| Ready|Fault |
r31972	r31973
467	482	// |  0   | Index| SeekC| Tr00 |   0  | WrPrt| Ready|Fault |
468	483	// +------+------+------+------+------+------+------+------+
469	484	//
470		//  Ready = WDS.ready | DSK
471		//  SeekComplete = WDS.seekComplete | DSK
	485	//  Ready = /WDS.ready* | DSK
	486	//  SeekComplete = /WDS.seekComplete* | DSK
472	487
473	488	// If DSK is selected, set Ready and SeekComplete to 1
474		// If WDS is selected but not connected, Ready and SeekComplete are 1
475		if ((m_output1_latch & 0x10)!=0) reply |= 0x22;
	489	if ((m_output1_latch & 0x10)!=0)
	490	{
	491	reply |= 0x22;
476	492
	493	// Check for TRK00*
	494	if ((m_current_floppy != NULL) && (!m_current_floppy->trk00_r()))
	495	reply |= 0x10;
	496	}
	497
	498	// If WDS is selected but not connected, WDS.ready* and WDS.seekComplete* are 1, so Ready=SeekComplete=0
477	499	reply |= m_status_latch;
478	500
479	501	m_hdc9234->auxbus_in(reply);
r31972	r31973
500	522	// Value is dma address byte. Shift previous contents to the left.
501	523	// The value is latched inside the Gate Array.
502	524	m_dma_address = ((m_dma_address << 8) + (data&0xff))&0xffffff;
	525	if (TRACE_DMA) logerror("%s: Setting DMA address; current value = %06x\n", tag(), m_dma_address);
503	526	break;
504	527
505	528	case HDC_OUTPUT_1:
r31972	r31973
511	534	// +------+------+------+------+------+------+------+------+
512	535	// Accordingly, drive 0 is always the floppy; selected by the low nibble
513	536
514		logerror("%s: Setting OUTPUT1 latch to %02x\n", tag(), data);
515	537	m_output1_latch = data;
516	538
517	539	if ((data & 0x10) != 0)
r31972	r31973
525	547	index = slog2((data>>4) & 0x0f);
526	548	if (index == -1)
527	549	{
528		logerror("%s: Unselect all drives\n", tag());
	550	if (TRACE_LINES) logerror("%s: Unselect all drives\n", tag());
529	551	}
530	552	else
531	553	{
532		logerror("%s: Select hard disk WDS%d\n", tag(), index);
	554	if (TRACE_LINES) logerror("%s: Select hard disk WDS%d\n", tag(), index);
533	555	//          if (index>=0) m_hdc9234->connect_hard_drive(m_harddisk_unit[index-1]);
534	556	}
535	557	if (m_current_harddisk==NULL)
536	558	{
537		set_bits(m_status_latch, HDC_DS_READY | HDC_DS_SKCOM, true);
	559	set_bits(m_status_latch, HDC_DS_READY | HDC_DS_SKCOM, false);
538	560	}
539	561	}
540	562	break;
r31972	r31973
549	571	// +------+------+------+------+------+------+------+------+
550	572	// | DS3* | WCur | Dir  | Step |           Head            |
551	573	// +------+------+------+------+------+------+------+------+
552		logerror("%s: Setting OUTPUT2 latch to %02x\n", tag(), data);
553	574	m_output2_latch = data;
554	575
555	576	// Output the step pulse to the selected floppy drive
556	577	if (m_current_floppy != NULL)
557	578	{
558	579	m_current_floppy->dir_w((data & 0x20)==0);
559		m_current_floppy->stp_w(0);
560		m_current_floppy->stp_w(1);
	580	m_current_floppy->stp_w((data & 0x10)==0);
561	581	}
562	582
	583	// We are pushing the drive status after OUTPUT2
	584	signal_drive_status();
563	585	break;
564	586	}
565
566		// We are pushing the drive status after every output
567		signal_drive_status();
568	587	}
569	588
570	589	enum
r31972	r31973
580	599	{
581	600	if (m_floppy_unit[index] != m_current_floppy)
582	601	{
583		logerror("%s: Select floppy drive DSK%d\n", tag(), index);
	602	if (TRACE_LINES) logerror("%s: Select floppy drive DSK%d\n", tag(), index+1);
584	603	if (m_current_floppy != NULL)
585	604	{
586	605	// Disconnect old drive from index line
	606	if (TRACE_LINES) logerror("%s: Disconnect previous index callback DSK%d\n", tag(), index+1);
587	607	m_current_floppy->setup_index_pulse_cb(floppy_image_device::index_pulse_cb());
	608	}
	609	// Connect new drive
	610	m_current_floppy = m_floppy_unit[index];
588	611
589		// Connect new drive
590		m_current_floppy = m_floppy_unit[index];
591
592		// We don't use the READY line of floppy drives.
593		// READY is asserted when DSKx = 1
594		// The controller fetches the state with the auxbus access
595		m_current_floppy->setup_index_pulse_cb(floppy_image_device::index_pulse_cb(FUNC(myarc_hfdc_device::floppy_index_callback), this));
596		}
	612	// We don't use the READY line of floppy drives.
	613	// READY is asserted when DSKx = 1
	614	// The controller fetches the state with the auxbus access
	615	if (TRACE_LINES) logerror("%s: Connect index callback DSK%d\n", tag(), index+1);
	616	m_current_floppy->setup_index_pulse_cb(floppy_image_device::index_pulse_cb(FUNC(myarc_hfdc_device::floppy_index_callback), this));
597	617	m_hdc9234->connect_floppy_drive(m_floppy_unit[index]);
598	618	}
599	619	}
600	620	else
601	621	{
602		logerror("%s: Unselect all floppy drives\n", tag());
	622	if (TRACE_LINES) logerror("%s: Unselect all floppy drives\n", tag());
603	623	// Disconnect current floppy
604	624	if (m_current_floppy != NULL)
605	625	{
r31972	r31973
607	627	m_current_floppy = NULL;
608	628	}
609	629	}
610		signal_drive_status();
	630	// The drive status is supposed to be sampled after OUTPUT2
	631	// signal_drive_status();
611	632	}
612	633
613	634	void myarc_hfdc_device::connect_harddisk_unit(int index)
r31972	r31973
616	637	//  {
617	638	m_current_harddisk = NULL;
618	639	//  }
619		signal_drive_status();
	640	// signal_drive_status();
620	641	}
621	642
622	643	/*
r31972	r31973
658	679	}
659	680
660	681	/*
	682	Called whenever the HDC9234 desires bus access to the buffer RAM. The
	683	controller expects a call to dmarq in 1 byte time.
	684	*/
	685	WRITE_LINE_MEMBER( myarc_hfdc_device::dmarq_w )
	686	{
	687	if (TRACE_LINES) logerror("%s: DMARQ pin from controller = %d\n", tag(), state);
	688	if (state == ASSERT_LINE)
	689	{
	690	m_hdc9234->dmaack(ASSERT_LINE);
	691	}
	692	}
	693
	694	/*
661	695	Called whenever the state of the HDC9234 DMA in progress changes.
662	696	*/
663	697	WRITE_LINE_MEMBER( myarc_hfdc_device::dip_w )
r31972	r31973
670	704	*/
671	705	READ8_MEMBER( myarc_hfdc_device::read_buffer )
672	706	{
673		logerror("%s: Read access to onboard SRAM at %04x\n", tag(), offset & 0xffff);
674		return 0;
	707	logerror("%s: Read access to onboard SRAM at %04x\n", tag(), m_dma_address);
	708	UINT8 value = m_buffer_ram[m_dma_address & 0x7fff];
	709	m_dma_address = (m_dma_address+1) & 0x7fff;
	710	return value;
675	711	}
676	712
677	713	/*
r31972	r31973
679	715	*/
680	716	WRITE8_MEMBER( myarc_hfdc_device::write_buffer )
681	717	{
682		logerror("%s: Write access to onboard SRAM at %04x: %02x\n", tag(), offset & 0xffff, data);
	718	if (TRACE_DMA) logerror("%s: Write access to onboard SRAM at %04x: %02x\n", tag(), m_dma_address, data);
	719	m_buffer_ram[m_dma_address & 0x7fff] = data;
	720	m_dma_address = (m_dma_address+1) & 0x7fff;
683	721	}
684	722
685	723	void myarc_hfdc_device::device_start()
r31972	r31973
774	812	PORT_DIPSETTING( 0x1f00, "1F00" )
775	813
776	814	PORT_START( "HFDCDIP" )
777		PORT_DIPNAME( 0xff, 0x55, "HFDC drive config" )
	815	PORT_DIPNAME( 0xff, 0x00, "HFDC drive config" )
778	816	PORT_DIPSETTING( 0x00, "40 track, 16 ms")
779	817	PORT_DIPSETTING( 0xaa, "40 track, 8 ms")
780	818	PORT_DIPSETTING( 0x55, "80 track, 2 ms")
r31972	r31973
797	835	MCFG_HDC9234_INTRQ_CALLBACK(WRITELINE(myarc_hfdc_device, intrq_w))
798	836	MCFG_HDC9234_DIP_CALLBACK(WRITELINE(myarc_hfdc_device, dip_w))
799	837	MCFG_HDC9234_AUXBUS_OUT_CALLBACK(WRITE8(myarc_hfdc_device, auxbus_out))
	838	MCFG_HDC9234_DMARQ_CALLBACK(WRITELINE(myarc_hfdc_device, dmarq_w))
800	839	MCFG_HDC9234_DMA_IN_CALLBACK(READ8(myarc_hfdc_device, read_buffer))
801	840	MCFG_HDC9234_DMA_OUT_CALLBACK(WRITE8(myarc_hfdc_device, write_buffer))
802	841

trunk/src/emu/bus/ti99_peb/hfdc.h

r31972	r31973
40	40	DECLARE_READ8Z_MEMBER(crureadz);
41	41	DECLARE_WRITE8_MEMBER(cruwrite);
42	42
	43	DECLARE_WRITE_LINE_MEMBER( dmarq_w );
43	44	DECLARE_WRITE_LINE_MEMBER( intrq_w );
44	45	DECLARE_WRITE_LINE_MEMBER( dip_w );
45	46	DECLARE_WRITE8_MEMBER( auxbus_out );

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