| Previous | 199869 Revisions | Next |
| r31965 Sunday 7th September, 2014 at 10:18:41 UTC by Barry Rodewald |
|---|
| svga_s3: added CLKSYN test register (SR17), gets stock Trio64V2/DX BIOS to boot. (no whatsnew) |
| [src/emu/bus/isa] | svga_s3.c |
| [src/emu/video] | pc_vga.c pc_vga.h |
| r31964 | r31965 | |
|---|---|---|
| 2005 | 2005 | // Power-on strapping bits. Sampled at reset, but can be modified later. |
| 2006 | 2006 | // These are just assumed defaults. |
| 2007 | 2007 | s3.strapping = 0x000f0b1e; |
| 2008 | s3.sr10 = 0x42; | |
| 2009 | s3.sr11 = 0x41; | |
| 2008 | 2010 | } |
| 2009 | 2011 | |
| 2010 | 2012 | READ8_MEMBER(vga_device::mem_r) |
| r31964 | r31965 | |
| 3241 | 3243 | case 0x15: |
| 3242 | 3244 | res = s3.sr15; |
| 3243 | 3245 | break; |
| 3246 | case 0x17: | |
| 3247 | res = s3.sr17; // CLKSYN test register | |
| 3248 | s3.sr17--; // who knows what it should return, docs only say it defaults to 0, and is reserved for testing of the clock synthesiser | |
| 3249 | break; | |
| 3244 | 3250 | } |
| 3245 | 3251 | } |
| 3246 | 3252 |
| r31964 | r31965 | |
|---|---|---|
| 584 | 584 | UINT8 sr12; // DCLK PLL |
| 585 | 585 | UINT8 sr13; // DCLK PLL |
| 586 | 586 | UINT8 sr15; // CLKSYN control 2 |
| 587 | UINT8 sr17; // CLKSYN test | |
| 587 | 588 | UINT8 clk_pll_r; // individual DCLK PLL values |
| 588 | 589 | UINT8 clk_pll_m; |
| 589 | 590 | UINT8 clk_pll_n; |
| r31964 | r31965 | |
|---|---|---|
| 16 | 16 | ROM_IGNORE( 0x8000 ) |
| 17 | 17 | |
| 18 | 18 | // The following are from Trio64V2/DX based cards |
| 19 | ROM_SYSTEM_BIOS( 1, " | |
| 19 | ROM_SYSTEM_BIOS( 1, "trio64v2", "PCI S3 86C765 v1.03-08N (S3 Trio64V2/DX)" ) | |
| 20 | 20 | ROMX_LOAD("pci_9503-62_s3.bin", 0x00000, 0x8000, CRC(0e9d79d8) SHA1(274b5b98cc998f2783567000cdb12b14308bc290), ROM_BIOS(2) ) |
| 21 | 21 | |
| 22 | 22 | ROM_SYSTEM_BIOS( 2, "winner1k", "PCI Elsa Winner 1000/T2D 6.01.00 (S3 Trio64V2/DX)" ) |
| Previous | 199869 Revisions | Next |