trunk/src/mame/drivers/raiden2.c
| r31914 | r31915 | |
|---|
| 744 | 744 | |
| 745 | 745 | // raidendx only |
| 746 | 746 | case 0x7e05: |
| 747 | | space.write_dword(0x470, (space.read_dword(cop_regs[4]) & 0x30) << 6); |
| 748 | | // Actually, wherever the bank selection actually is |
| 749 | | // And probably 8 bytes too, but they zero all the rest |
| 747 | space.write_byte(0x470, space.read_byte(cop_regs[4])); |
| 750 | 748 | break; |
| 751 | 749 | |
| 752 | 750 | case 0xa100: |
| r31914 | r31915 | |
|---|
| 1010 | 1008 | { |
| 1011 | 1009 | COMBINE_DATA(&cop_bank); |
| 1012 | 1010 | |
| 1013 | | if(ACCESSING_BITS_8_15) { |
| 1014 | | int new_bank = 4 | ((cop_bank >> 10) & 3); |
| 1015 | | if(new_bank != fg_bank) { |
| 1016 | | fg_bank = new_bank; |
| 1017 | | foreground_layer->mark_all_dirty(); |
| 1018 | | } |
| 1011 | int new_bank = 4 | ((cop_bank >> 4) & 3); |
| 1012 | if(new_bank != fg_bank) { |
| 1013 | fg_bank = new_bank; |
| 1014 | foreground_layer->mark_all_dirty(); |
| 1015 | } |
| 1019 | 1016 | |
| 1020 | | /* probably bit 3 is from 6c9 */ |
| 1021 | | /* TODO: this doesn't work! */ |
| 1022 | | membank("mainbank")->set_entry(8 | (cop_bank & 0x7000) >> 12); |
| 1023 | | } |
| 1017 | /* mainbank2 coming from 6c9 ? */ |
| 1018 | int bb = cop_bank >> 12; |
| 1019 | membank("mainbank1")->set_entry(bb + 16); |
| 1020 | membank("mainbank2")->set_entry(3); |
| 1024 | 1021 | } |
| 1025 | 1022 | |
| 1026 | 1023 | |
| r31914 | r31915 | |
|---|
| 1257 | 1254 | common_reset(); |
| 1258 | 1255 | sprcpt_init(); |
| 1259 | 1256 | |
| 1260 | | membank("mainbank")->set_entry(1); |
| 1257 | membank("mainbank1")->set_entry(2); |
| 1258 | membank("mainbank2")->set_entry(3); |
| 1261 | 1259 | |
| 1262 | 1260 | prg_bank = 0; |
| 1263 | 1261 | //cop_init(); |
| r31914 | r31915 | |
|---|
| 1268 | 1266 | common_reset(); |
| 1269 | 1267 | sprcpt_init(); |
| 1270 | 1268 | |
| 1271 | | membank("mainbank")->set_entry(8); |
| 1269 | membank("mainbank1")->set_entry(16); |
| 1270 | membank("mainbank2")->set_entry(3); |
| 1272 | 1271 | |
| 1273 | 1272 | prg_bank = 0x08; |
| 1274 | 1273 | |
| r31914 | r31915 | |
|---|
| 1282 | 1281 | mid_bank = 1; |
| 1283 | 1282 | sprcpt_init(); |
| 1284 | 1283 | |
| 1285 | | membank("mainbank")->set_entry(1); |
| 1284 | membank("mainbank1")->set_entry(2); |
| 1285 | membank("mainbank2")->set_entry(3); |
| 1286 | 1286 | |
| 1287 | 1287 | prg_bank = 0; |
| 1288 | 1288 | //cop_init(); |
| r31914 | r31915 | |
|---|
| 1294 | 1294 | fg_bank = 2; |
| 1295 | 1295 | mid_bank = 1; |
| 1296 | 1296 | sprcpt_init(); |
| 1297 | | |
| 1298 | | //membank("mainbank")->set_entry(1); |
| 1299 | | |
| 1300 | | //cop_init(); |
| 1301 | 1297 | } |
| 1302 | 1298 | |
| 1303 | 1299 | READ16_MEMBER(raiden2_state::raiden2_sound_comms_r) |
| r31914 | r31915 | |
|---|
| 1313 | 1309 | WRITE16_MEMBER(raiden2_state::raiden2_bank_w) |
| 1314 | 1310 | { |
| 1315 | 1311 | if(ACCESSING_BITS_8_15) { |
| 1312 | int bb = (~data >> 15) & 1; |
| 1316 | 1313 | logerror("select bank %d %04x\n", (data >> 15) & 1, data); |
| 1317 | | membank("mainbank")->set_entry(!((data >> 15) & 1)); |
| 1314 | membank("mainbank1")->set_entry(bb*2); |
| 1315 | membank("mainbank2")->set_entry(bb*2+1); |
| 1318 | 1316 | prg_bank = ((data >> 15) & 1); |
| 1319 | 1317 | } |
| 1320 | 1318 | } |
| r31914 | r31915 | |
|---|
| 1598 | 1596 | AM_RANGE(0x10000, 0x1efff) AM_RAM |
| 1599 | 1597 | AM_RANGE(0x1f000, 0x1ffff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette") |
| 1600 | 1598 | |
| 1601 | | AM_RANGE(0x20000, 0x3ffff) AM_ROMBANK("mainbank") |
| 1599 | AM_RANGE(0x20000, 0x2ffff) AM_ROMBANK("mainbank1") |
| 1600 | AM_RANGE(0x30000, 0x3ffff) AM_ROMBANK("mainbank2") |
| 1602 | 1601 | AM_RANGE(0x40000, 0xfffff) AM_ROM AM_REGION("mainprg", 0x40000) |
| 1603 | 1602 | ADDRESS_MAP_END |
| 1604 | 1603 | |
| r31914 | r31915 | |
|---|
| 1636 | 1635 | AM_RANGE(0x0f000, 0x0ffff) AM_RAM AM_SHARE("sprites") |
| 1637 | 1636 | AM_RANGE(0x10000, 0x1ffff) AM_RAM |
| 1638 | 1637 | |
| 1639 | | AM_RANGE(0x20000, 0x3ffff) AM_ROMBANK("mainbank") |
| 1638 | AM_RANGE(0x20000, 0x2ffff) AM_ROMBANK("mainbank1") |
| 1639 | AM_RANGE(0x30000, 0x3ffff) AM_ROMBANK("mainbank2") |
| 1640 | 1640 | AM_RANGE(0x40000, 0xfffff) AM_ROM AM_REGION("mainprg", 0x40000) |
| 1641 | 1641 | ADDRESS_MAP_END |
| 1642 | 1642 | |
| r31914 | r31915 | |
|---|
| 3306 | 3306 | |
| 3307 | 3307 | DRIVER_INIT_MEMBER(raiden2_state,raiden2) |
| 3308 | 3308 | { |
| 3309 | | membank("mainbank")->configure_entries(0, 2, memregion("mainprg")->base(), 0x20000); |
| 3309 | membank("mainbank1")->configure_entries(0, 4, memregion("mainprg")->base(), 0x10000); |
| 3310 | membank("mainbank2")->configure_entries(0, 4, memregion("mainprg")->base(), 0x10000); |
| 3310 | 3311 | raiden2_decrypt_sprites(machine()); |
| 3311 | 3312 | } |
| 3312 | 3313 | |
| 3313 | 3314 | DRIVER_INIT_MEMBER(raiden2_state,raidendx) |
| 3314 | 3315 | { |
| 3315 | | membank("mainbank")->configure_entries(0, 0x10, memregion("mainprg")->base(), 0x20000); |
| 3316 | membank("mainbank1")->configure_entries(0, 0x20, memregion("mainprg")->base(), 0x10000); |
| 3317 | membank("mainbank2")->configure_entries(0, 0x20, memregion("mainprg")->base(), 0x10000); |
| 3316 | 3318 | raiden2_decrypt_sprites(machine()); |
| 3317 | 3319 | } |
| 3318 | 3320 | |
| 3319 | 3321 | DRIVER_INIT_MEMBER(raiden2_state,xsedae) |
| 3320 | 3322 | { |
| 3321 | 3323 | /* doesn't have banking */ |
| 3322 | | //membank("mainbank")->configure_entries(0, 2, memregion("mainprg")->base(), 0x20000); |
| 3323 | 3324 | } |
| 3324 | 3325 | |
| 3325 | 3326 | DRIVER_INIT_MEMBER(raiden2_state,zeroteam) |
| 3326 | 3327 | { |
| 3327 | | membank("mainbank")->configure_entries(0, 2, memregion("mainprg")->base(), 0x20000); |
| 3328 | membank("mainbank1")->configure_entries(0, 4, memregion("mainprg")->base(), 0x10000); |
| 3329 | membank("mainbank2")->configure_entries(0, 4, memregion("mainprg")->base(), 0x10000); |
| 3328 | 3330 | zeroteam_decrypt_sprites(machine()); |
| 3329 | 3331 | } |
| 3330 | 3332 | |