Previous

199869 Revisions

Next

r31834 Friday 29th August, 2014 at 20:01:29 UTC by Wilbert Pol
rsp.c: Modernised cpu core (nw)

[src/emu/cpu/rsp]	rsp.c rsp.h rspdrc.c rspfe.c rspfe.h
[src/mame/machine]	n64.c

trunk/src/mame/machine/n64.c

r31833	r31834
2417	2417	/* configure fast RAM regions for DRC */
2418	2418	dynamic_cast<mips3_device *>(machine().device("maincpu"))->mips3drc_add_fastram(0x00000000, 0x007fffff, FALSE, rdram);
2419	2419
2420		rspdrc_set_options(machine().device("rsp"), RSPDRC_STRICT_VERIFY);
2421		rspdrc_flush_drc_cache(machine().device("rsp"));
2422		rspdrc_add_dmem(machine().device("rsp"), rsp_dmem);
2423		rspdrc_add_imem(machine().device("rsp"), rsp_imem);
	2420	rsp_device *rsp = machine().device<rsp_device>("rsp");
	2421	rsp->rspdrc_set_options(RSPDRC_STRICT_VERIFY);
	2422	rsp->rspdrc_flush_drc_cache();
	2423	rsp->rspdrc_add_dmem(rsp_dmem);
	2424	rsp->rspdrc_add_imem(rsp_imem);
2424	2425
2425	2426	/* add a hook for battery save */
2426	2427	machine().add_notifier(MACHINE_NOTIFY_EXIT, machine_notify_delegate(FUNC(n64_state::n64_machine_stop),this));

trunk/src/emu/cpu/rsp/rspdrc.c

r31833	r31834
36	36	extern offs_t rsp_dasm_one(char *buffer, offs_t pc, UINT32 op);
37	37
38	38	/***************************************************************************
39		DEBUGGING
40		***************************************************************************/
41
42		#define LOG_UML                         (0)
43		#define LOG_NATIVE                      (0)
44
45		#define SINGLE_INSTRUCTION_MODE         (0)
46
47
48		/***************************************************************************
49	39	CONSTANTS
50	40	***************************************************************************/
51	41
r31833	r31834
53	43	#define MAPVAR_PC                       M0
54	44	#define MAPVAR_CYCLES                   M1
55	45
56		/* size of the execution code cache */
57		#define CACHE_SIZE                      (32 * 1024 * 1024)
58
59		/* compilation boundaries -- how far back/forward does the analysis extend? */
60		#define COMPILE_BACKWARDS_BYTES         128
61		#define COMPILE_FORWARDS_BYTES          512
62		#define COMPILE_MAX_INSTRUCTIONS        ((COMPILE_BACKWARDS_BYTES/4) + (COMPILE_FORWARDS_BYTES/4))
63		#define COMPILE_MAX_SEQUENCE            64
64
65	46	/* exit codes */
66	47	#define EXECUTE_OUT_OF_CYCLES           0
67	48	#define EXECUTE_MISSING_CODE            1
r31833	r31834
74	55	MACROS
75	56	***************************************************************************/
76	57
77		#define R32(reg)                rsp->impstate->regmap[reg]
	58	#define R32(reg)                m_regmap[reg]
78	59
79	60	/***************************************************************************
80		STRUCTURES & TYPEDEFS
81		***************************************************************************/
82
83		/* fast RAM info */
84		struct fast_ram_info
85		{
86		offs_t              start;                      /* start of the RAM block */
87		offs_t              end;                        /* end of the RAM block */
88		UINT8               readonly;                   /* TRUE if read-only */
89		void *              base;                       /* base in memory where the RAM lives */
90		};
91
92
93		/* internal compiler state */
94		struct compiler_state
95		{
96		UINT32              cycles;                     /* accumulated cycles */
97		UINT8               checkints;                  /* need to check interrupts before next instruction */
98		UINT8               checksoftints;              /* need to check software interrupts before next instruction */
99		code_label  labelnum;                   /* index for local labels */
100		};
101
102		struct rspimp_state
103		{
104		/* core state */
105		drc_cache *         cache;                      /* pointer to the DRC code cache */
106		drcuml_state *      drcuml;                     /* DRC UML generator state */
107		rsp_frontend *      drcfe;                      /* pointer to the DRC front-end state */
108		UINT32              drcoptions;                 /* configurable DRC options */
109
110		/* internal stuff */
111		UINT8               cache_dirty;                /* true if we need to flush the cache */
112		UINT32              jmpdest;                    /* destination jump target */
113
114		/* parameters for subroutines */
115		UINT64              numcycles;                  /* return value from gettotalcycles */
116		const char *        format;                     /* format string for print_debug */
117		UINT32              arg0;                       /* print_debug argument 1 */
118		UINT32              arg1;                       /* print_debug argument 2 */
119		UINT32              arg2;                       /* print_debug argument 3 */
120		UINT32              arg3;                       /* print_debug argument 4 */
121		UINT32              vres[8];                    /* used for temporary vector results */
122
123		/* register mappings */
124		parameter   regmap[34];                 /* parameter to register mappings for all 32 integer registers */
125
126		/* subroutines */
127		code_handle *   entry;                      /* entry point */
128		code_handle *   nocode;                     /* nocode exception handler */
129		code_handle *   out_of_cycles;              /* out of cycles exception handler */
130		code_handle *   read8;                      /* read byte */
131		code_handle *   write8;                     /* write byte */
132		code_handle *   read16;                     /* read half */
133		code_handle *   write16;                    /* write half */
134		code_handle *   read32;                     /* read word */
135		code_handle *   write32;                    /* write word */
136		};
137
138		/***************************************************************************
139		FUNCTION PROTOTYPES
140		***************************************************************************/
141
142		static void code_flush_cache(rsp_state *rsp);
143		static void code_compile_block(rsp_state *rsp, offs_t pc);
144
145		static void cfunc_unimplemented(void *param);
146		static void cfunc_set_cop0_reg(void *param);
147		static void cfunc_get_cop0_reg(void *param);
148		#if USE_SIMD
149		static void cfunc_mfc2_simd(void *param);
150		static void cfunc_cfc2_simd(void *param);
151		static void cfunc_mtc2_simd(void *param);
152		static void cfunc_ctc2_simd(void *param);
153		#endif
154
155		#if (!USE_SIMD || SIMUL_SIMD)
156		static void cfunc_mfc2_scalar(void *param);
157		static void cfunc_cfc2_scalar(void *param);
158		static void cfunc_mtc2_scalar(void *param);
159		static void cfunc_ctc2_scalar(void *param);
160		#endif
161		//static void cfunc_swc2(void *param);
162		//static void cfunc_lwc2(void *param);
163		static void cfunc_sp_set_status_cb(void *param);
164
165		#if USE_SIMD
166		static void cfunc_rsp_lbv_simd(void *param);
167		static void cfunc_rsp_lsv_simd(void *param);
168		static void cfunc_rsp_llv_simd(void *param);
169		static void cfunc_rsp_ldv_simd(void *param);
170		static void cfunc_rsp_lqv_simd(void *param);
171		static void cfunc_rsp_lrv_simd(void *param);
172		static void cfunc_rsp_lpv_simd(void *param);
173		static void cfunc_rsp_luv_simd(void *param);
174		static void cfunc_rsp_lhv_simd(void *param);
175		static void cfunc_rsp_lfv_simd(void *param);
176		static void cfunc_rsp_lwv_simd(void *param);
177		static void cfunc_rsp_ltv_simd(void *param);
178
179		static void cfunc_rsp_sbv_simd(void *param);
180		static void cfunc_rsp_ssv_simd(void *param);
181		static void cfunc_rsp_slv_simd(void *param);
182		static void cfunc_rsp_sdv_simd(void *param);
183		static void cfunc_rsp_sqv_simd(void *param);
184		static void cfunc_rsp_srv_simd(void *param);
185		static void cfunc_rsp_spv_simd(void *param);
186		static void cfunc_rsp_suv_simd(void *param);
187		static void cfunc_rsp_shv_simd(void *param);
188		static void cfunc_rsp_sfv_simd(void *param);
189		static void cfunc_rsp_swv_simd(void *param);
190		static void cfunc_rsp_stv_simd(void *param);
191		#endif
192
193		#if (!USE_SIMD || SIMUL_SIMD)
194		static void cfunc_rsp_lbv_scalar(void *param);
195		static void cfunc_rsp_lsv_scalar(void *param);
196		static void cfunc_rsp_llv_scalar(void *param);
197		static void cfunc_rsp_ldv_scalar(void *param);
198		static void cfunc_rsp_lqv_scalar(void *param);
199		static void cfunc_rsp_lrv_scalar(void *param);
200		static void cfunc_rsp_lpv_scalar(void *param);
201		static void cfunc_rsp_luv_scalar(void *param);
202		static void cfunc_rsp_lhv_scalar(void *param);
203		static void cfunc_rsp_lfv_scalar(void *param);
204		static void cfunc_rsp_lwv_scalar(void *param);
205		static void cfunc_rsp_ltv_scalar(void *param);
206
207		static void cfunc_rsp_sbv_scalar(void *param);
208		static void cfunc_rsp_ssv_scalar(void *param);
209		static void cfunc_rsp_slv_scalar(void *param);
210		static void cfunc_rsp_sdv_scalar(void *param);
211		static void cfunc_rsp_sqv_scalar(void *param);
212		static void cfunc_rsp_srv_scalar(void *param);
213		static void cfunc_rsp_spv_scalar(void *param);
214		static void cfunc_rsp_suv_scalar(void *param);
215		static void cfunc_rsp_shv_scalar(void *param);
216		static void cfunc_rsp_sfv_scalar(void *param);
217		static void cfunc_rsp_swv_scalar(void *param);
218		static void cfunc_rsp_stv_scalar(void *param);
219		#endif
220
221		static void static_generate_entry_point(rsp_state *rsp);
222		static void static_generate_nocode_handler(rsp_state *rsp);
223		static void static_generate_out_of_cycles(rsp_state *rsp);
224		static void static_generate_memory_accessor(rsp_state *rsp, int size, int iswrite, const char *name, code_handle *&handleptr);
225
226		static int generate_lwc2(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
227		static int generate_swc2(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
228		static void generate_update_cycles(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, parameter param, int allow_exception);
229		static void generate_checksum_block(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast);
230		static void generate_sequence_instruction(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
231		static void generate_delay_slot_and_branch(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 linkreg);
232		static int generate_opcode(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
233		static int generate_special(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
234		static int generate_regimm(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
235		static int generate_cop0(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
236		static int generate_cop2(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
237
238		static void log_add_disasm_comment(rsp_state *rsp, drcuml_block *block, UINT32 pc, UINT32 op);
239
240		/***************************************************************************
241	61	HELPFUL DEFINES
242	62	***************************************************************************/
243	63
r31833	r31834
277	97	#define SIMD_EXTRACT16C(reg, value, element) value = _mm_extract_epi16(reg, element);
278	98	#define SIMD_INSERT16C(reg, value, element) reg = _mm_insert_epi16(reg, value, element);
279	99
280		#define VREG_B(reg, offset)         rsp->v[(reg)].b[(offset)^1]
281		#define W_VREG_S(reg, offset)       rsp->v[(reg)].s[(offset)]
282		#define VREG_S(reg, offset)         (INT16)rsp->v[(reg)].s[(offset)]
	100	#define VREG_B(reg, offset)         m_v[(reg)].b[(offset)^1]
	101	#define W_VREG_S(reg, offset)       m_v[(reg)].s[(offset)]
	102	#define VREG_S(reg, offset)         (INT16)m_v[(reg)].s[(offset)]
283	103
284	104	#define VEC_EL_2(x,z)               (vector_elements_2[(x)][(z)])
285	105
286		#define ACCUM(x)        rsp->accum[x].q
	106	#define ACCUM(x)        m_accum[x].q
287	107
288	108	#define CARRY       0
289	109	#define COMPARE     1
r31833	r31834
291	111	#define ZERO        3
292	112	#define CLIP2       4
293	113
	114
294	115	#if USE_SIMD
295		INLINE UINT16 VEC_ACCUM_H(const rsp_state *rsp, int x)
	116	static void cfunc_mfc2_simd(void *param);
	117	static void cfunc_cfc2_simd(void *param);
	118	static void cfunc_mtc2_simd(void *param);
	119	static void cfunc_ctc2_simd(void *param);
	120	#endif
	121
	122	#if (!USE_SIMD || SIMUL_SIMD)
	123	static void cfunc_mfc2_scalar(void *param);
	124	static void cfunc_cfc2_scalar(void *param);
	125	static void cfunc_mtc2_scalar(void *param);
	126	static void cfunc_ctc2_scalar(void *param);
	127	#endif
	128
	129
	130	#if USE_SIMD
	131	inline UINT16 rsp_device::VEC_ACCUM_H(int x)
296	132	{
297	133	UINT16 out;
298		SIMD_EXTRACT16(rsp->accum_h, out, x);
	134	SIMD_EXTRACT16(m_accum_h, out, x);
299	135	return out;
300	136	}
301	137
302		INLINE UINT16 VEC_ACCUM_M(const rsp_state *rsp, int x)
	138	inline UINT16 rsp_device::VEC_ACCUM_M(int x)
303	139	{
304	140	UINT16 out;
305		SIMD_EXTRACT16(rsp->accum_m, out, x);
	141	SIMD_EXTRACT16(m_accum_m, out, x);
306	142	return out;
307	143	}
308	144
309		INLINE UINT16 VEC_ACCUM_L(const rsp_state *rsp, int x)
	145	inline UINT16 rsp_device::VEC_ACCUM_L(int x)
310	146	{
311	147	UINT16 out;
312		SIMD_EXTRACT16(rsp->accum_l, out, x);
	148	SIMD_EXTRACT16(m_accum_l, out, x);
313	149	return out;
314	150	}
315	151
316		INLINE UINT16 VEC_ACCUM_LL(const rsp_state *rsp, int x)
	152	inline UINT16 rsp_device::VEC_ACCUM_LL(int x)
317	153	{
318	154	UINT16 out;
319		SIMD_EXTRACT16(rsp->accum_ll, out, x);
	155	SIMD_EXTRACT16(m_accum_ll, out, x);
320	156	return out;
321	157	}
322	158
323		#define VEC_SET_ACCUM_H(v, x) SIMD_INSERT16(rsp->accum_h, v, x);
324		#define VEC_SET_ACCUM_M(v, x) SIMD_INSERT16(rsp->accum_m, v, x);
325		#define VEC_SET_ACCUM_L(v, x) SIMD_INSERT16(rsp->accum_l, v, x);
326		#define VEC_SET_ACCUM_LL(v, x) SIMD_INSERT16(rsp->accum_ll, v, x);
	159	#define VEC_SET_ACCUM_H(v, x) SIMD_INSERT16(m_accum_h, v, x);
	160	#define VEC_SET_ACCUM_M(v, x) SIMD_INSERT16(m_>accum_m, v, x);
	161	#define VEC_SET_ACCUM_L(v, x) SIMD_INSERT16(m_accum_l, v, x);
	162	#define VEC_SET_ACCUM_LL(v, x) SIMD_INSERT16(m_accum_ll, v, x);
327	163
328		#define VEC_GET_SCALAR_VS1(out, i) SIMD_EXTRACT16(rsp->xv[VS1REG], out, i);
329		#define VEC_GET_SCALAR_VS2(out, i) SIMD_EXTRACT16(rsp->xv[VS2REG], out, VEC_EL_2(EL, i));
	164	#define VEC_GET_SCALAR_VS1(out, i) SIMD_EXTRACT16(m_xv[VS1REG], out, i);
	165	#define VEC_GET_SCALAR_VS2(out, i) SIMD_EXTRACT16(m_xv[VS2REG], out, VEC_EL_2(EL, i));
330	166
331		INLINE UINT16 VEC_CARRY_FLAG(rsp_state *rsp, const int x)
	167	inline UINT16 rsp_device::VEC_CARRY_FLAG(const int x)
332	168	{
333	169	UINT16 out;
334		SIMD_EXTRACT16(rsp->xvflag[CARRY], out, x);
	170	SIMD_EXTRACT16(m_xvflag[CARRY], out, x);
335	171	return out;
336	172	}
337	173
338		INLINE UINT16 VEC_COMPARE_FLAG(rsp_state *rsp, const int x)
	174	inline UINT16 rsp_device::VEC_COMPARE_FLAG(const int x)
339	175	{
340	176	UINT16 out;
341		SIMD_EXTRACT16(rsp->xvflag[COMPARE], out, x);
	177	SIMD_EXTRACT16(m_xvflag[COMPARE], out, x);
342	178	return out;
343	179	}
344	180
345		INLINE UINT16 VEC_CLIP1_FLAG(rsp_state *rsp, const int x)
	181	inline UINT16 rsp_device::VEC_CLIP1_FLAG(const int x)
346	182	{
347	183	UINT16 out;
348		SIMD_EXTRACT16(rsp->xvflag[CLIP1], out, x);
	184	SIMD_EXTRACT16(m_xvflag[CLIP1], out, x);
349	185	return out;
350	186	}
351	187
352		INLINE UINT16 VEC_ZERO_FLAG(rsp_state *rsp, const int x)
	188	inline UINT16 rsp_device::VEC_ZERO_FLAG(const int x)
353	189	{
354	190	UINT16 out;
355		SIMD_EXTRACT16(rsp->xvflag[ZERO], out, x);
	191	SIMD_EXTRACT16(m_xvflag[ZERO], out, x);
356	192	return out;
357	193	}
358	194
359		INLINE UINT16 VEC_CLIP2_FLAG(rsp_state *rsp, const int x)
	195	inline UINT16 rsp_device::VEC_CLIP2_FLAG(const int x)
360	196	{
361	197	UINT16 out;
362		SIMD_EXTRACT16(rsp->xvflag[CLIP2], out, x);
	198	SIMD_EXTRACT16(m_xvflag[CLIP2], out, x);
363	199	return out;
364	200	}
365	201
366		#define VEC_CLEAR_CARRY_FLAGS()     { rsp->xvflag[CARRY] = _mm_setzero_si128(); }
367		#define VEC_CLEAR_COMPARE_FLAGS()   { rsp->xvflag[COMPARE] = _mm_setzero_si128(); }
368		#define VEC_CLEAR_CLIP1_FLAGS()     { rsp->xvflag[CLIP1] = _mm_setzero_si128(); }
369		#define VEC_CLEAR_ZERO_FLAGS()      { rsp->xvflag[ZERO] = _mm_setzero_si128(); }
370		#define VEC_CLEAR_CLIP2_FLAGS()     { rsp->xvflag[CLIP2] = _mm_setzero_si128(); }
	202	#define VEC_CLEAR_CARRY_FLAGS()     { m_xvflag[CARRY] = _mm_setzero_si128(); }
	203	#define VEC_CLEAR_COMPARE_FLAGS()   { m_xvflag[COMPARE] = _mm_setzero_si128(); }
	204	#define VEC_CLEAR_CLIP1_FLAGS()     { m_xvflag[CLIP1] = _mm_setzero_si128(); }
	205	#define VEC_CLEAR_ZERO_FLAGS()      { m_xvflag[ZERO] = _mm_setzero_si128(); }
	206	#define VEC_CLEAR_CLIP2_FLAGS()     { m_xvflag[CLIP2] = _mm_setzero_si128(); }
371	207
372		#define VEC_SET_CARRY_FLAG(x)       { SIMD_INSERT16(rsp->xvflag[CARRY], 0xffff, x); }
373		#define VEC_SET_COMPARE_FLAG(x)     { SIMD_INSERT16(rsp->xvflag[COMPARE], 0xffff, x); }
374		#define VEC_SET_CLIP1_FLAG(x)       { SIMD_INSERT16(rsp->xvflag[CLIP1], 0xffff, x); }
375		#define VEC_SET_ZERO_FLAG(x)        { SIMD_INSERT16(rsp->xvflag[ZERO], 0xffff, x); }
376		#define VEC_SET_CLIP2_FLAG(x)       { SIMD_INSERT16(rsp->xvflag[CLIP2], 0xffff, x); }
	208	#define VEC_SET_CARRY_FLAG(x)       { SIMD_INSERT16(m_xvflag[CARRY], 0xffff, x); }
	209	#define VEC_SET_COMPARE_FLAG(x)     { SIMD_INSERT16(m_xvflag[COMPARE], 0xffff, x); }
	210	#define VEC_SET_CLIP1_FLAG(x)       { SIMD_INSERT16(m_xvflag[CLIP1], 0xffff, x); }
	211	#define VEC_SET_ZERO_FLAG(x)        { SIMD_INSERT16(m_xvflag[ZERO], 0xffff, x); }
	212	#define VEC_SET_CLIP2_FLAG(x)       { SIMD_INSERT16(m_xvflag[CLIP2], 0xffff, x); }
377	213
378		#define VEC_CLEAR_CARRY_FLAG(x)     { SIMD_INSERT16(rsp->xvflag[CARRY], 0, x); }
379		#define VEC_CLEAR_COMPARE_FLAG(x)   { SIMD_INSERT16(rsp->xvflag[COMPARE], 0, x); }
380		#define VEC_CLEAR_CLIP1_FLAG(x)     { SIMD_INSERT16(rsp->xvflag[CLIP1], 0, x); }
381		#define VEC_CLEAR_ZERO_FLAG(x)      { SIMD_INSERT16(rsp->xvflag[ZERO], 0, x); }
382		#define VEC_CLEAR_CLIP2_FLAG(x)     { SIMD_INSERT16(rsp->xvflag[CLIP2], 0, x); }
	214	#define VEC_CLEAR_CARRY_FLAG(x)     { SIMD_INSERT16(m_xvflag[CARRY], 0, x); }
	215	#define VEC_CLEAR_COMPARE_FLAG(x)   { SIMD_INSERT16(m_xvflag[COMPARE], 0, x); }
	216	#define VEC_CLEAR_CLIP1_FLAG(x)     { SIMD_INSERT16(m_xvflag[CLIP1], 0, x); }
	217	#define VEC_CLEAR_ZERO_FLAG(x)      { SIMD_INSERT16(m_xvflag[ZERO], 0, x); }
	218	#define VEC_CLEAR_CLIP2_FLAG(x)     { SIMD_INSERT16(m_xvflag[CLIP2], 0, x); }
383	219
384	220	#endif
385	221
386		#define ACCUM_H(v, x)           (UINT16)rsp->accum[x].w[3]
387		#define ACCUM_M(v, x)           (UINT16)rsp->accum[x].w[2]
388		#define ACCUM_L(v, x)           (UINT16)rsp->accum[x].w[1]
389		#define ACCUM_LL(v, x)          (UINT16)rsp->accum[x].w[0]
	222	#define ACCUM_H(x)           (UINT16)m_accum[x].w[3]
	223	#define ACCUM_M(x)           (UINT16)m_accum[x].w[2]
	224	#define ACCUM_L(x)           (UINT16)m_accum[x].w[1]
	225	#define ACCUM_LL(x)          (UINT16)m_accum[x].w[0]
390	226
391		#define SET_ACCUM_H(v, x)       rsp->accum[x].w[3] = v;
392		#define SET_ACCUM_M(v, x)       rsp->accum[x].w[2] = v;
393		#define SET_ACCUM_L(v, x)       rsp->accum[x].w[1] = v;
394		#define SET_ACCUM_LL(v, x)      rsp->accum[x].w[0] = v;
	227	#define SET_ACCUM_H(v, x)       m_accum[x].w[3] = v;
	228	#define SET_ACCUM_M(v, x)       m_accum[x].w[2] = v;
	229	#define SET_ACCUM_L(v, x)       m_accum[x].w[1] = v;
	230	#define SET_ACCUM_LL(v, x)      m_accum[x].w[0] = v;
395	231
396	232	#define SCALAR_GET_VS1(out, i)  out = VREG_S(VS1REG, i)
397	233	#define SCALAR_GET_VS2(out, i)  out = VREG_S(VS2REG, VEC_EL_2(EL, i))
398	234
399		#define CARRY_FLAG(rsp, x)          (rsp->vflag[CARRY][x & 7] != 0 ? 0xffff : 0)
400		#define COMPARE_FLAG(rsp, x)        (rsp->vflag[COMPARE][x & 7] != 0 ? 0xffff : 0)
401		#define CLIP1_FLAG(rsp, x)          (rsp->vflag[CLIP1][x & 7] != 0 ? 0xffff : 0)
402		#define ZERO_FLAG(rsp, x)           (rsp->vflag[ZERO][x & 7] != 0 ? 0xffff : 0)
403		#define CLIP2_FLAG(rsp, x)          (rsp->vflag[CLIP2][x & 7] != 0 ? 0xffff : 0)
	235	#define CARRY_FLAG(x)          (m_vflag[CARRY][x & 7] != 0 ? 0xffff : 0)
	236	#define COMPARE_FLAG(x)        (m_vflag[COMPARE][x & 7] != 0 ? 0xffff : 0)
	237	#define CLIP1_FLAG(x)          (m_vflag[CLIP1][x & 7] != 0 ? 0xffff : 0)
	238	#define ZERO_FLAG(x)           (m_vflag[ZERO][x & 7] != 0 ? 0xffff : 0)
	239	#define CLIP2_FLAG(x)          (m_vflag[CLIP2][x & 7] != 0 ? 0xffff : 0)
404	240
405		#define CLEAR_CARRY_FLAGS()         { memset(rsp->vflag[CARRY], 0, 16); }
406		#define CLEAR_COMPARE_FLAGS()       { memset(rsp->vflag[COMPARE], 0, 16); }
407		#define CLEAR_CLIP1_FLAGS()         { memset(rsp->vflag[CLIP1], 0, 16); }
408		#define CLEAR_ZERO_FLAGS()          { memset(rsp->vflag[ZERO], 0, 16); }
409		#define CLEAR_CLIP2_FLAGS()         { memset(rsp->vflag[CLIP2], 0, 16); }
	241	#define CLEAR_CARRY_FLAGS()         { memset(m_vflag[CARRY], 0, 16); }
	242	#define CLEAR_COMPARE_FLAGS()       { memset(m_vflag[COMPARE], 0, 16); }
	243	#define CLEAR_CLIP1_FLAGS()         { memset(m_vflag[CLIP1], 0, 16); }
	244	#define CLEAR_ZERO_FLAGS()          { memset(m_vflag[ZERO], 0, 16); }
	245	#define CLEAR_CLIP2_FLAGS()         { memset(m_vflag[CLIP2], 0, 16); }
410	246
411		#define SET_CARRY_FLAG(x)           { rsp->vflag[CARRY][x & 7] = 0xffff; }
412		#define SET_COMPARE_FLAG(x)         { rsp->vflag[COMPARE][x & 7] = 0xffff; }
413		#define SET_CLIP1_FLAG(x)           { rsp->vflag[CLIP1][x & 7] = 0xffff; }
414		#define SET_ZERO_FLAG(x)            { rsp->vflag[ZERO][x & 7] = 0xffff; }
415		#define SET_CLIP2_FLAG(x)           { rsp->vflag[CLIP2][x & 7] = 0xffff; }
	247	#define SET_CARRY_FLAG(x)           { m_vflag[CARRY][x & 7] = 0xffff; }
	248	#define SET_COMPARE_FLAG(x)         { m_vflag[COMPARE][x & 7] = 0xffff; }
	249	#define SET_CLIP1_FLAG(x)           { m_vflag[CLIP1][x & 7] = 0xffff; }
	250	#define SET_ZERO_FLAG(x)            { m_vflag[ZERO][x & 7] = 0xffff; }
	251	#define SET_CLIP2_FLAG(x)           { m_vflag[CLIP2][x & 7] = 0xffff; }
416	252
417		#define CLEAR_CARRY_FLAG(x)         { rsp->vflag[CARRY][x & 7] = 0; }
418		#define CLEAR_COMPARE_FLAG(x)       { rsp->vflag[COMPARE][x & 7] = 0; }
419		#define CLEAR_CLIP1_FLAG(x)         { rsp->vflag[CLIP1][x & 7] = 0; }
420		#define CLEAR_ZERO_FLAG(x)          { rsp->vflag[ZERO][x & 7] = 0; }
421		#define CLEAR_CLIP2_FLAG(x)         { rsp->vflag[CLIP2][x & 7] = 0; }
	253	#define CLEAR_CARRY_FLAG(x)         { m_vflag[CARRY][x & 7] = 0; }
	254	#define CLEAR_COMPARE_FLAG(x)       { m_vflag[COMPARE][x & 7] = 0; }
	255	#define CLEAR_CLIP1_FLAG(x)         { m_vflag[CLIP1][x & 7] = 0; }
	256	#define CLEAR_ZERO_FLAG(x)          { m_vflag[ZERO][x & 7] = 0; }
	257	#define CLEAR_CLIP2_FLAG(x)         { m_vflag[CLIP2][x & 7] = 0; }
422	258
423		INLINE rsp_state *get_safe_token(device_t *device)
424		{
425		assert(device != NULL);
426		assert(device->type() == RSP_DRC);
427		return *(rsp_state **)downcast<legacy_cpu_device *>(device)->token();
428		}
429	259
430	260	/***************************************************************************
431	261	INLINE FUNCTIONS
r31833	r31834
459	289	registers
460	290	-------------------------------------------------*/
461	291
462		INLINE void load_fast_iregs(rsp_state *rsp, drcuml_block *block)
	292	inline void rsp_device::load_fast_iregs(drcuml_block *block)
463	293	{
464	294	int regnum;
465	295
466		for (regnum = 0; regnum < ARRAY_LENGTH(rsp->impstate->regmap); regnum++)
467		if (rsp->impstate->regmap[regnum].is_int_register())
468		UML_MOV(block, ireg(rsp->impstate->regmap[regnum].ireg() - REG_I0), mem(&rsp->r[regnum]));
	296	for (regnum = 0; regnum < ARRAY_LENGTH(m_regmap); regnum++)
	297	if (m_regmap[regnum].is_int_register())
	298	UML_MOV(block, ireg(m_regmap[regnum].ireg() - REG_I0), mem(&m_rsp_state->r[regnum]));
469	299	}
470	300
471	301
r31833	r31834
474	304	registers
475	305	-------------------------------------------------*/
476	306
477		INLINE void save_fast_iregs(rsp_state *rsp, drcuml_block *block)
	307	inline void rsp_device::save_fast_iregs(drcuml_block *block)
478	308	{
479	309	int regnum;
480	310
481		for (regnum = 0; regnum < ARRAY_LENGTH(rsp->impstate->regmap); regnum++)
482		if (rsp->impstate->regmap[regnum].is_int_register())
483		UML_MOV(block, mem(&rsp->r[regnum]), ireg(rsp->impstate->regmap[regnum].ireg() - REG_I0));
	311	for (regnum = 0; regnum < ARRAY_LENGTH(m_regmap); regnum++)
	312	if (m_regmap[regnum].is_int_register())
	313	UML_MOV(block, mem(&m_rsp_state->r[regnum]), ireg(m_regmap[regnum].ireg() - REG_I0));
484	314	}
485	315
486	316	/***************************************************************************
487	317	CORE CALLBACKS
488	318	***************************************************************************/
489	319
490		void rspdrc_add_imem(device_t *device, UINT32 *base)
	320	void rsp_device::rspdrc_add_imem(UINT32 *base)
491	321	{
492		if (!device->machine().options().drc()) return;
493		rsp_state *rsp = get_safe_token(device);
494		rsp->imem32 = base;
495		rsp->imem16 = (UINT16*)base;
496		rsp->imem8 = (UINT8*)base;
	322	m_imem32 = base;
	323	m_imem16 = (UINT16*)base;
	324	m_imem8 = (UINT8*)base;
497	325	}
498	326
499		void rspdrc_add_dmem(device_t *device, UINT32 *base)
	327	void rsp_device::rspdrc_add_dmem(UINT32 *base)
500	328	{
501		if (!device->machine().options().drc()) return;
502		rsp_state *rsp = get_safe_token(device);
503		rsp->dmem32 = base;
504		rsp->dmem16 = (UINT16*)base;
505		rsp->dmem8 = (UINT8*)base;
	329	m_dmem32 = base;
	330	m_dmem16 = (UINT16*)base;
	331	m_dmem8 = (UINT8*)base;
506	332	}
507	333
508		INLINE UINT8 READ8(rsp_state *rsp, UINT32 address)
	334	inline UINT8 rsp_device::DM_READ8(UINT32 address)
509	335	{
510		UINT8 ret = rsp->dmem8[BYTE4_XOR_BE(address & 0xfff)];
	336	UINT8 ret = m_dmem8[BYTE4_XOR_BE(address & 0xfff)];
511	337	return ret;
512	338	}
513	339
	340	inline void rsp_device::ccfunc_read8()
	341	{
	342	m_rsp_state->arg0 = DM_READ8(m_rsp_state->arg0);
	343	}
	344
514	345	static void cfunc_read8(void *param)
515	346	{
516		rsp_state *rsp = (rsp_state *)param;
517		rsp->impstate->arg0 = READ8(rsp, rsp->impstate->arg0);
	347	((rsp_device *)param)->ccfunc_read8();
518	348	}
519	349
520		INLINE UINT16 READ16(rsp_state *rsp, UINT32 address)
	350	inline UINT16 rsp_device::DM_READ16(UINT32 address)
521	351	{
522	352	UINT16 ret;
523	353	address &= 0xfff;
524		ret = rsp->dmem8[BYTE4_XOR_BE(address)] << 8;
525		ret |= rsp->dmem8[BYTE4_XOR_BE(address + 1)];
	354	ret = m_dmem8[BYTE4_XOR_BE(address)] << 8;
	355	ret |= m_dmem8[BYTE4_XOR_BE(address + 1)];
526	356	return ret;
527	357	}
528	358
	359	inline void rsp_device::ccfunc_read16()
	360	{
	361	m_rsp_state->arg0 = DM_READ16(m_rsp_state->arg0);
	362	}
	363
529	364	static void cfunc_read16(void *param)
530	365	{
531		rsp_state *rsp = (rsp_state *)param;
532		rsp->impstate->arg0 = READ16(rsp, rsp->impstate->arg0);
	366	((rsp_device *)param)->ccfunc_read16();
533	367	}
534	368
535		INLINE UINT32 READ32(rsp_state *rsp, UINT32 address)
	369	inline UINT32 rsp_device::DM_READ32(UINT32 address)
536	370	{
537	371	UINT32 ret;
538	372	address &= 0xfff;
539		ret = rsp->dmem8[BYTE4_XOR_BE(address)] << 24;
540		ret |= rsp->dmem8[BYTE4_XOR_BE(address + 1)] << 16;
541		ret |= rsp->dmem8[BYTE4_XOR_BE(address + 2)] << 8;
542		ret |= rsp->dmem8[BYTE4_XOR_BE(address + 3)];
	373	ret = m_dmem8[BYTE4_XOR_BE(address)] << 24;
	374	ret |= m_dmem8[BYTE4_XOR_BE(address + 1)] << 16;
	375	ret |= m_dmem8[BYTE4_XOR_BE(address + 2)] << 8;
	376	ret |= m_dmem8[BYTE4_XOR_BE(address + 3)];
543	377	return ret;
544	378	}
545	379
	380	inline void rsp_device::ccfunc_read32()
	381	{
	382	m_rsp_state->arg0 = DM_READ32(m_rsp_state->arg0);
	383	}
	384
546	385	static void cfunc_read32(void *param)
547	386	{
548		rsp_state *rsp = (rsp_state *)param;
549		rsp->impstate->arg0 = READ32(rsp, rsp->impstate->arg0);
	387	((rsp_device *)param)->ccfunc_read32();;
550	388	}
551	389
552		INLINE void WRITE8(rsp_state *rsp, UINT32 address, UINT8 data)
	390	inline void rsp_device::DM_WRITE8(UINT32 address, UINT8 data)
553	391	{
554	392	address &= 0xfff;
555		rsp->dmem8[BYTE4_XOR_BE(address)] = data;
	393	m_dmem8[BYTE4_XOR_BE(address)] = data;
556	394	}
557	395
	396	inline void rsp_device::ccfunc_write8()
	397	{
	398	DM_WRITE8(m_rsp_state->arg0, m_rsp_state->arg1);
	399	}
	400
558	401	static void cfunc_write8(void *param)
559	402	{
560		rsp_state *rsp = (rsp_state *)param;
561		WRITE8(rsp, rsp->impstate->arg0, (UINT8)rsp->impstate->arg1);
	403	((rsp_device *)param)->ccfunc_write8();;
562	404	}
563	405
564		INLINE void WRITE16(rsp_state *rsp, UINT32 address, UINT16 data)
	406	inline void rsp_device::DM_WRITE16(UINT32 address, UINT16 data)
565	407	{
566	408	address &= 0xfff;
567		rsp->dmem8[BYTE4_XOR_BE(address)] = data >> 8;
568		rsp->dmem8[BYTE4_XOR_BE(address + 1)] = data & 0xff;
	409	m_dmem8[BYTE4_XOR_BE(address)] = data >> 8;
	410	m_dmem8[BYTE4_XOR_BE(address + 1)] = data & 0xff;
569	411	}
570	412
	413	inline void rsp_device::ccfunc_write16()
	414	{
	415	DM_WRITE16(m_rsp_state->arg0, m_rsp_state->arg1);
	416	}
	417
571	418	static void cfunc_write16(void *param)
572	419	{
573		rsp_state *rsp = (rsp_state *)param;
574		WRITE16(rsp, rsp->impstate->arg0, (UINT16)rsp->impstate->arg1);
	420	((rsp_device *)param)->ccfunc_write16();;
575	421	}
576	422
577		INLINE void WRITE32(rsp_state *rsp, UINT32 address, UINT32 data)
	423	inline void rsp_device::DM_WRITE32(UINT32 address, UINT32 data)
578	424	{
579	425	address &= 0xfff;
580		rsp->dmem8[BYTE4_XOR_BE(address)] = data >> 24;
581		rsp->dmem8[BYTE4_XOR_BE(address + 1)] = (data >> 16) & 0xff;
582		rsp->dmem8[BYTE4_XOR_BE(address + 2)] = (data >> 8) & 0xff;
583		rsp->dmem8[BYTE4_XOR_BE(address + 3)] = data & 0xff;
	426	m_dmem8[BYTE4_XOR_BE(address)] = data >> 24;
	427	m_dmem8[BYTE4_XOR_BE(address + 1)] = (data >> 16) & 0xff;
	428	m_dmem8[BYTE4_XOR_BE(address + 2)] = (data >> 8) & 0xff;
	429	m_dmem8[BYTE4_XOR_BE(address + 3)] = data & 0xff;
584	430	}
585	431
	432	inline void rsp_device::ccfunc_write32()
	433	{
	434	DM_WRITE32(m_rsp_state->arg0, m_rsp_state->arg1);
	435	}
	436
586	437	static void cfunc_write32(void *param)
587	438	{
588		rsp_state *rsp = (rsp_state *)param;
589		WRITE32(rsp, rsp->impstate->arg0, rsp->impstate->arg1);
	439	((rsp_device *)param)->ccfunc_write32();;
590	440	}
591	441
592	442	/*****************************************************************************/
r31833	r31834
595	445	rspdrc_set_options - configure DRC options
596	446	-------------------------------------------------*/
597	447
598		void rspdrc_set_options(device_t *device, UINT32 options)
	448	void rsp_device::rspdrc_set_options(UINT32 options)
599	449	{
600		if (!device->machine().options().drc()) return;
601		rsp_state *rsp = get_safe_token(device);
602		rsp->impstate->drcoptions = options;
	450	if (!machine().options().drc()) return;
	451	m_drcoptions = options;
603	452	}
604	453
605	454
r31833	r31834
609	458	-------------------------------------------------*/
610	459
611	460	#ifdef UNUSED_CODE
612		static void cfunc_printf_debug(void *param)
	461	inline void rs_device::cfunc_printf_debug()
613	462	{
614		rsp_state *rsp = (rsp_state *)param;
615		switch(rsp->impstate->arg2)
	463	switch(m_arg2)
616	464	{
617	465	case 0: // WRITE8
618		printf("%04x:%02x\n", rsp->impstate->arg0 & 0xffff, (UINT8)rsp->impstate->arg1);
	466	printf("%04x:%02x\n", m_rsp_state->arg0 & 0xffff, (UINT8)m_rsp_state->arg1);
619	467	break;
620	468	case 1: // WRITE16
621		printf("%04x:%04x\n", rsp->impstate->arg0 & 0xffff, (UINT16)rsp->impstate->arg1);
	469	printf("%04x:%04x\n", m_rsp_state->arg0 & 0xffff, (UINT16)m_rsp_state->arg1);
622	470	break;
623	471	case 2: // WRITE32
624		printf("%04x:%08x\n", rsp->impstate->arg0 & 0xffff, rsp->impstate->arg1);
	472	printf("%04x:%08x\n", m_rsp_state->arg0 & 0xffff, m_rsp_state->arg1);
625	473	break;
626	474	case 3: // READ8
627		printf("%04xr%02x\n", rsp->impstate->arg0 & 0xffff, (UINT8)rsp->impstate->arg1);
	475	printf("%04xr%02x\n", m_rsp_state->arg0 & 0xffff, (UINT8)m_rsp_state->arg1);
628	476	break;
629	477	case 4: // READ16
630		printf("%04xr%04x\n", rsp->impstate->arg0 & 0xffff, (UINT16)rsp->impstate->arg1);
	478	printf("%04xr%04x\n", m_rsp_state->arg0 & 0xffff, (UINT16)m_rsp_state->arg1);
631	479	break;
632	480	case 5: // READ32
633		printf("%04xr%08x\n", rsp->impstate->arg0 & 0xffff, rsp->impstate->arg1);
	481	printf("%04xr%08x\n", m_rsp_state->arg0 & 0xffff, m_rsp_state->arg1);
634	482	break;
635	483	case 6: // Checksum
636		printf("Sum: %08x\n", rsp->impstate->arg0);
	484	printf("Sum: %08x\n", m_rsp_state->arg0);
637	485	break;
638	486	case 7: // Checksum
639		printf("Correct Sum: %08x\n", rsp->impstate->arg0);
	487	printf("Correct Sum: %08x\n", m_rsp_state->arg0);
640	488	break;
641	489	default: // ???
642		printf("%08x %08x\n", rsp->impstate->arg0 & 0xffff, rsp->impstate->arg1);
	490	printf("%08x %08x\n", m_rsp_state->arg0 & 0xffff, m_rsp_state->arg1);
643	491	break;
644	492	}
645	493	}
	494
	495	static void cfunc_printf_debug(void *param)
	496	{
	497	((rsp_device *)param)->ccfunc_printf_debug();
	498	}
646	499	#endif
647	500
648		static void cfunc_get_cop0_reg(void *param)
	501	inline void rsp_device::ccfunc_get_cop0_reg()
649	502	{
650		rsp_state *rsp = (rsp_state*)param;
651		int reg = rsp->impstate->arg0;
652		int dest = rsp->impstate->arg1;
	503	int reg = m_rsp_state->arg0;
	504	int dest = m_rsp_state->arg1;
653	505
654	506	if (reg >= 0 && reg < 8)
655	507	{
656	508	if(dest)
657	509	{
658		rsp->r[dest] = (rsp->device->sp_reg_r_func)(reg, 0xffffffff);
	510	m_rsp_state->r[dest] = m_sp_reg_r_func(reg, 0xffffffff);
659	511	}
660	512	}
661	513	else if (reg >= 8 && reg < 16)
662	514	{
663	515	if(dest)
664	516	{
665		rsp->r[dest] = (rsp->device->dp_reg_r_func)(reg - 8, 0xffffffff);
	517	m_rsp_state->r[dest] = m_dp_reg_r_func(reg - 8, 0xffffffff);
666	518	}
667	519	}
668	520	else
r31833	r31834
671	523	}
672	524	}
673	525
674		static void cfunc_set_cop0_reg(void *param)
	526	static void cfunc_get_cop0_reg(void *param)
675	527	{
676		rsp_state *rsp = (rsp_state*)param;
677		int reg = rsp->impstate->arg0;
678		UINT32 data = rsp->impstate->arg1;
	528	((rsp_device *)param)->ccfunc_get_cop0_reg();
	529	}
679	530
	531	inline void rsp_device::ccfunc_set_cop0_reg()
	532	{
	533	int reg = m_rsp_state->arg0;
	534	UINT32 data = m_rsp_state->arg1;
	535
680	536	if (reg >= 0 && reg < 8)
681	537	{
682		(rsp->device->sp_reg_w_func)(reg, data, 0xffffffff);
	538	m_sp_reg_w_func(reg, data, 0xffffffff);
683	539	}
684	540	else if (reg >= 8 && reg < 16)
685	541	{
686		(rsp->device->dp_reg_w_func)(reg - 8, data, 0xffffffff);
	542	m_dp_reg_w_func(reg - 8, data, 0xffffffff);
687	543	}
688	544	else
689	545	{
r31833	r31834
691	547	}
692	548	}
693	549
694		static void cfunc_unimplemented_opcode(void *param)
	550	static void cfunc_set_cop0_reg(void *param)
695	551	{
696		rsp_state *rsp = (rsp_state*)param;
697		int op = rsp->impstate->arg0;
698		if ((rsp->device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
699		{
700		char string[200];
701		rsp_dasm_one(string, rsp->ppc, op);
702		osd_printf_debug("%08X: %s\n", rsp->ppc, string);
703		}
704
705		fatalerror("RSP: unknown opcode %02X (%08X) at %08X\n", op >> 26, op, rsp->ppc);
	552	((rsp_device *)param)->ccfunc_set_cop0_reg();
706	553	}
707	554
708		static void unimplemented_opcode(rsp_state *rsp, UINT32 op)
	555	inline void rsp_device::ccfunc_unimplemented_opcode()
709	556	{
710		if ((rsp->device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
	557	int op = m_rsp_state->arg0;
	558	if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
711	559	{
712	560	char string[200];
713		rsp_dasm_one(string, rsp->ppc, op);
714		osd_printf_debug("%08X: %s\n", rsp->ppc, string);
	561	rsp_dasm_one(string, m_ppc, op);
	562	osd_printf_debug("%08X: %s\n", m_ppc, string);
715	563	}
716	564
717		fatalerror("RSP: unknown opcode %02X (%08X) at %08X\n", op >> 26, op, rsp->ppc);
	565	fatalerror("RSP: unknown opcode %02X (%08X) at %08X\n", op >> 26, op, m_ppc);
718	566	}
719	567
	568	static void cfunc_unimplemented_opcode(void *param)
	569	{
	570	((rsp_device *)param)->ccfunc_unimplemented_opcode();
	571	}
	572
720	573	/*****************************************************************************/
721	574
722	575	/* Legacy.  Going forward, this will be transitioned into unrolled opcode decodes. */
r31833	r31834
757	610	static __m128i vec_shuf_inverse[16];
758	611	#endif
759	612
760		static void rspcom_init(rsp_state *rsp, legacy_cpu_device *device, device_irq_acknowledge_delegate irqcallback)
	613	void rsp_device::rspcom_init()
761	614	{
762		int regIdx = 0;
763		int accumIdx;
764
765		memset(rsp, 0, sizeof(*rsp));
766
767		rsp->irq_callback = irqcallback;
768		rsp->device = downcast<rsp_cpu_device *>(device);
769		rsp->program = &device->space(AS_PROGRAM);
770		rsp->direct = &rsp->program->direct();
771		rsp->device->resolve_cb();
772
773		// Inaccurate.  RSP registers power on to a random state...
774		for(regIdx = 0; regIdx < 32; regIdx++ )
775		{
776		rsp->r[regIdx] = 0;
777		rsp->v[regIdx].d[0] = 0;
778		rsp->v[regIdx].d[1] = 0;
779		}
780
781	615	#if USE_SIMD
782	616	VEC_CLEAR_CARRY_FLAGS();
783	617	VEC_CLEAR_COMPARE_FLAGS();
r31833	r31834
793	627	CLEAR_ZERO_FLAGS();
794	628	CLEAR_CLIP2_FLAGS();
795	629	#endif
796		rsp->reciprocal_res = 0;
797		rsp->reciprocal_high = 0;
798	630
799		// ...except for the accumulators.
800		for(accumIdx = 0; accumIdx < 8; accumIdx++ )
801		{
802		rsp->accum[accumIdx].q = 0;
803		}
804
805		rsp->sr = RSP_STATUS_HALT;
806		rsp->step_count = 0;
807
808	631	#if USE_SIMD
809	632	vec_shuf_inverse[ 0] = _mm_set_epi16(0x0f0e, 0x0d0c, 0x0b0a, 0x0908, 0x0706, 0x0504, 0x0302, 0x0100); // none
810	633	vec_shuf_inverse[ 1] = _mm_set_epi16(0x0f0e, 0x0d0c, 0x0b0a, 0x0908, 0x0706, 0x0504, 0x0302, 0x0100); // ???
r31833	r31834
839	662	vec_shuf[13] = _mm_set_epi16(0x0504, 0x0504, 0x0504, 0x0504, 0x0504, 0x0504, 0x0504, 0x0504); // 5
840	663	vec_shuf[14] = _mm_set_epi16(0x0302, 0x0302, 0x0302, 0x0302, 0x0302, 0x0302, 0x0302, 0x0302); // 6
841	664	vec_shuf[15] = _mm_set_epi16(0x0100, 0x0100, 0x0100, 0x0100, 0x0100, 0x0100, 0x0100, 0x0100); // 7
842		rsp->accum_h = _mm_setzero_si128();
843		rsp->accum_m = _mm_setzero_si128();
844		rsp->accum_l = _mm_setzero_si128();
845		rsp->accum_ll = _mm_setzero_si128();
	665	m_accum_h = _mm_setzero_si128();
	666	m_accum_m = _mm_setzero_si128();
	667	m_accum_l = _mm_setzero_si128();
	668	m_accum_ll = _mm_setzero_si128();
846	669	vec_neg1 = _mm_set_epi64x(0xffffffffffffffffL, 0xffffffffffffffffL);
847	670	vec_zero = _mm_setzero_si128();
848	671	vec_himask = _mm_set_epi64x(0xffff0000ffff0000L, 0xffff0000ffff0000L);
r31833	r31834
858	681	#endif
859	682	}
860	683
861		static CPU_INIT( rsp )
862		{
863		rsp_state *rsp;
864		drc_cache *cache;
865		UINT32 flags = 0;
866		int regnum;
867		//int elnum;
868	684
869		/* allocate enough space for the cache and the core */
870		cache = auto_alloc(device->machine(), drc_cache(CACHE_SIZE + sizeof(*rsp)));
871
872		/* allocate the core memory */
873		*(rsp_state **)device->token() = rsp = (rsp_state *)cache->alloc_near(sizeof(*rsp));
874		memset(rsp, 0, sizeof(*rsp));
875
876		rspcom_init(rsp, device, irqcallback);
877
878		/* allocate the implementation-specific state from the full cache */
879		rsp->impstate = (rspimp_state *)cache->alloc_near(sizeof(*rsp->impstate));
880		memset(rsp->impstate, 0, sizeof(*rsp->impstate));
881		rsp->impstate->cache = cache;
882
883		/* initialize the UML generator */
884		if (LOG_UML)
885		{
886		flags |= DRCUML_OPTION_LOG_UML;
887		}
888		if (LOG_NATIVE)
889		{
890		flags |= DRCUML_OPTION_LOG_NATIVE;
891		}
892		rsp->impstate->drcuml = auto_alloc(device->machine(), drcuml_state(*device, *cache, flags, 8, 32, 2));
893
894		/* add symbols for our stuff */
895		rsp->impstate->drcuml->symbol_add(&rsp->pc, sizeof(rsp->pc), "pc");
896		rsp->impstate->drcuml->symbol_add(&rsp->icount, sizeof(rsp->icount), "icount");
897		for (regnum = 0; regnum < 32; regnum++)
898		{
899		char buf[10];
900		sprintf(buf, "r%d", regnum);
901		rsp->impstate->drcuml->symbol_add(&rsp->r[regnum], sizeof(rsp->r[regnum]), buf);
902		}
903		rsp->impstate->drcuml->symbol_add(&rsp->impstate->arg0, sizeof(rsp->impstate->arg0), "arg0");
904		rsp->impstate->drcuml->symbol_add(&rsp->impstate->arg1, sizeof(rsp->impstate->arg1), "arg1");
905		rsp->impstate->drcuml->symbol_add(&rsp->impstate->arg2, sizeof(rsp->impstate->arg2), "arg2");
906		rsp->impstate->drcuml->symbol_add(&rsp->impstate->arg3, sizeof(rsp->impstate->arg3), "arg3");
907		rsp->impstate->drcuml->symbol_add(&rsp->impstate->numcycles, sizeof(rsp->impstate->numcycles), "numcycles");
908
909		/* initialize the front-end helper */
910		rsp->impstate->drcfe = auto_alloc(device->machine(), rsp_frontend(*rsp, COMPILE_BACKWARDS_BYTES, COMPILE_FORWARDS_BYTES, SINGLE_INSTRUCTION_MODE ? 1 : COMPILE_MAX_SEQUENCE));
911
912		/* compute the register parameters */
913		for (regnum = 0; regnum < 32; regnum++)
914		rsp->impstate->regmap[regnum] = (regnum == 0) ? parameter(0) : parameter::make_memory(&rsp->r[regnum]);
915
916		/*
917		drcbe_info beinfo;
918		rsp->impstate->drcuml->get_backend_info(beinfo);
919		if (beinfo.direct_iregs > 2)
920		{
921		rsp->impstate->regmap[30] = I2;
922		}
923		if (beinfo.direct_iregs > 3)
924		{
925		rsp->impstate->regmap[31] = I3;
926		}
927		if (beinfo.direct_iregs > 4)
928		{
929		rsp->impstate->regmap[2] = I4;
930		}
931		if (beinfo.direct_iregs > 5)
932		{
933		rsp->impstate->regmap[3] = I5;
934		}
935		if (beinfo.direct_iregs > 6)
936		{
937		rsp->impstate->regmap[4] = I6;
938		}
939		*/
940
941		/* mark the cache dirty so it is updated on next execute */
942		rsp->impstate->cache_dirty = TRUE;
943		}
944
945		static CPU_EXIT( rsp )
946		{
947		rsp_state *rsp = get_safe_token(device);
948
949		/* clean up the DRC */
950		auto_free(device->machine(), rsp->impstate->drcfe);
951		auto_free(device->machine(), rsp->impstate->drcuml);
952		auto_free(device->machine(), rsp->impstate->cache);
953		}
954
955
956		static CPU_RESET( rsp )
957		{
958		rsp_state *rsp = get_safe_token(device);
959		rsp->nextpc = ~0;
960		}
961
962	685	#if USE_SIMD
963	686	// LBV
964	687	//
r31833	r31834
969	692	//
970	693	// Load 1 byte to vector byte index
971	694
972		static void cfunc_rsp_lbv_simd(void *param)
	695	inline void rsp_device::ccfunc_rsp_lbv_simd()
973	696	{
974		rsp_state *rsp = (rsp_state*)param;
975		UINT32 op = rsp->impstate->arg0;
	697	UINT32 op = m_rsp_state->arg0;
976	698
977	699	UINT32 ea = 0;
978	700	int dest = (op >> 16) & 0x1f;
r31833	r31834
984	706	offset |= 0xffffffc0;
985	707	}
986	708
987		ea = (base) ? rsp->r[base] + offset : offset;
	709	ea = (base) ? m_rsp_state->r[base] + offset : offset;
988	710
989	711	UINT16 element;
990		SIMD_EXTRACT16(rsp->xv[dest], element, (index >> 1));
	712	SIMD_EXTRACT16(m_xv[dest], element, (index >> 1));
991	713	element &= 0xff00 >> ((1-(index & 1)) * 8);
992		element |= READ8(rsp, ea) << ((1-(index & 1)) * 8);
993		SIMD_INSERT16(rsp->xv[dest], element, (index >> 1));
	714	element |= DM_READ8(ea) << ((1-(index & 1)) * 8);
	715	SIMD_INSERT16(m_xv[dest], element, (index >> 1));
994	716	}
	717
	718	static void cfunc_rsp_lbv_simd(void *param)
	719	{
	720	((rsp_device *)param)->ccfunc_rsp_lbv_simd();
	721	}
995	722	#endif
996	723
997	724	#if (!USE_SIMD || SIMUL_SIMD)
998		static void cfunc_rsp_lbv_scalar(void *param)
	725	inline void rsp_device::ccfunc_rsp_lbv_scalar()
999	726	{
1000		rsp_state *rsp = (rsp_state*)param;
1001		UINT32 op = rsp->impstate->arg0;
	727	UINT32 op = m_rsp_state->arg0;
1002	728
1003	729	UINT32 ea = 0;
1004	730	int dest = (op >> 16) & 0x1f;
r31833	r31834
1010	736	offset |= 0xffffffc0;
1011	737	}
1012	738
1013		ea = (base) ? rsp->r[base] + offset : offset;
1014		VREG_B(dest, index) = READ8(rsp, ea);
	739	ea = (base) ? m_rsp_state->r[base] + offset : offset;
	740	VREG_B(dest, index) = DM_READ8(ea);
1015	741	}
	742
	743	static void cfunc_rsp_lbv_scalar(void *param)
	744	{
	745	((rsp_device *)param)->ccfunc_rsp_lbv_scalar();
	746	}
1016	747	#endif
1017	748
1018	749	#if USE_SIMD
r31833	r31834
1025	756	//
1026	757	// Loads 2 bytes starting from vector byte index
1027	758
1028		static void cfunc_rsp_lsv_simd(void *param)
	759	inline void rsp_device::ccfunc_rsp_lsv_simd()
1029	760	{
1030		rsp_state *rsp = (rsp_state*)param;
1031		UINT32 op = rsp->impstate->arg0;
	761	UINT32 op = m_rsp_state->arg0;
1032	762	int dest = (op >> 16) & 0x1f;
1033	763	int base = (op >> 21) & 0x1f;
1034	764	int index = (op >> 7) & 0xe;
r31833	r31834
1038	768	offset |= 0xffffffc0;
1039	769	}
1040	770
1041		UINT32 ea = (base) ? rsp->r[base] + (offset * 2) : (offset * 2);
	771	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 2) : (offset * 2);
1042	772	int end = index + 2;
1043	773	for (int i = index; i < end; i++)
1044	774	{
1045	775	UINT16 element;
1046		SIMD_EXTRACT16(rsp->xv[dest], element, (i >> 1));
	776	SIMD_EXTRACT16(m_xv[dest], element, (i >> 1));
1047	777	element &= 0xff00 >> ((1 - (i & 1)) * 8);
1048		element |= READ8(rsp, ea) << ((1 - (i & 1)) * 8);
1049		SIMD_INSERT16(rsp->xv[dest], element, (i >> 1));
	778	element |= DM_READ8(ea) << ((1 - (i & 1)) * 8);
	779	SIMD_INSERT16(m_xv[dest], element, (i >> 1));
1050	780	ea++;
1051	781	}
1052	782	}
	783
	784	static void cfunc_rsp_lsv_simd(void *param)
	785	{
	786	((rsp_device *)param)->ccfunc_rsp_lsv_simd();
	787	}
1053	788	#endif
1054	789
1055	790	#if (!USE_SIMD || SIMUL_SIMD)
1056		static void cfunc_rsp_lsv_scalar(void *param)
	791	inline void rsp_device::ccfunc_rsp_lsv_scalar()
1057	792	{
1058		rsp_state *rsp = (rsp_state*)param;
1059		UINT32 op = rsp->impstate->arg0;
	793	UINT32 op = m_rsp_state->arg0;
1060	794	int dest = (op >> 16) & 0x1f;
1061	795	int base = (op >> 21) & 0x1f;
1062	796	int index = (op >> 7) & 0xe;
r31833	r31834
1066	800	offset |= 0xffffffc0;
1067	801	}
1068	802
1069		UINT32 ea = (base) ? rsp->r[base] + (offset * 2) : (offset * 2);
	803	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 2) : (offset * 2);
1070	804	int end = index + 2;
1071	805	for (int i = index; i < end; i++)
1072	806	{
1073		VREG_B(dest, i) = READ8(rsp, ea);
	807	VREG_B(dest, i) = DM_READ8(ea);
1074	808	ea++;
1075	809	}
1076	810	}
	811
	812	static void cfunc_rsp_lsv_scalar(void *param)
	813	{
	814	((rsp_device *)param)->ccfunc_rsp_lsv_scalar();
	815	}
1077	816	#endif
1078	817
1079	818	#if USE_SIMD
r31833	r31834
1086	825	//
1087	826	// Loads 4 bytes starting from vector byte index
1088	827
1089		static void cfunc_rsp_llv_simd(void *param)
	828	inline void rsp_device::ccfunc_rsp_llv_simd()
1090	829	{
1091		rsp_state *rsp = (rsp_state*)param;
1092		UINT32 op = rsp->impstate->arg0;
	830	UINT32 op = m_rsp_state->arg0;
1093	831	UINT32 ea = 0;
1094	832	int dest = (op >> 16) & 0x1f;
1095	833	int base = (op >> 21) & 0x1f;
r31833	r31834
1100	838	offset |= 0xffffffc0;
1101	839	}
1102	840
1103		ea = (base) ? rsp->r[base] + (offset * 4) : (offset * 4);
	841	ea = (base) ? m_rsp_state->r[base] + (offset * 4) : (offset * 4);
1104	842
1105	843	int end = index + 4;
1106	844
1107	845	for (int i = index; i < end; i++)
1108	846	{
1109	847	UINT16 element;
1110		SIMD_EXTRACT16(rsp->xv[dest], element, (i >> 1));
	848	SIMD_EXTRACT16(m_xv[dest], element, (i >> 1));
1111	849	element &= 0xff00 >> ((1 - (i & 1)) * 8);
1112		element |= READ8(rsp, ea) << ((1 - (i & 1)) * 8);
1113		SIMD_INSERT16(rsp->xv[dest], element, (i >> 1));
	850	element |= DM_READ8(ea) << ((1 - (i & 1)) * 8);
	851	SIMD_INSERT16(m_xv[dest], element, (i >> 1));
1114	852	ea++;
1115	853	}
1116	854	}
1117	855
	856	static void cfunc_rsp_llv_simd(void *param)
	857	{
	858	((rsp_device *)param)->ccfunc_rsp_llv_simd();
	859	}
1118	860	#endif
1119	861
1120	862	#if (!USE_SIMD || SIMUL_SIMD)
1121	863
1122		static void cfunc_rsp_llv_scalar(void *param)
	864	inline void rsp_device::ccfunc_rsp_llv_scalar()
1123	865	{
1124		rsp_state *rsp = (rsp_state*)param;
1125		UINT32 op = rsp->impstate->arg0;
	866	UINT32 op = m_rsp_state->arg0;
1126	867	UINT32 ea = 0;
1127	868	int dest = (op >> 16) & 0x1f;
1128	869	int base = (op >> 21) & 0x1f;
r31833	r31834
1133	874	offset |= 0xffffffc0;
1134	875	}
1135	876
1136		ea = (base) ? rsp->r[base] + (offset * 4) : (offset * 4);
	877	ea = (base) ? m_rsp_state->r[base] + (offset * 4) : (offset * 4);
1137	878
1138	879	int end = index + 4;
1139	880
1140	881	for (int i = index; i < end; i++)
1141	882	{
1142		VREG_B(dest, i) = READ8(rsp, ea);
	883	VREG_B(dest, i) = DM_READ8(ea);
1143	884	ea++;
1144	885	}
1145	886	}
	887
	888	static void cfunc_rsp_llv_scalar(void *param)
	889	{
	890	((rsp_device *)param)->ccfunc_rsp_llv_scalar();
	891	}
1146	892	#endif
1147	893
1148	894	#if USE_SIMD
r31833	r31834
1155	901	//
1156	902	// Loads 8 bytes starting from vector byte index
1157	903
1158		static void cfunc_rsp_ldv_simd(void *param)
	904	inline void rsp_device::ccfunc_rsp_ldv_simd()
1159	905	{
1160		rsp_state *rsp = (rsp_state*)param;
1161		UINT32 op = rsp->impstate->arg0;
	906	UINT32 op = m_rsp_state->arg0;
1162	907	UINT32 ea = 0;
1163	908	int dest = (op >> 16) & 0x1f;
1164	909	int base = (op >> 21) & 0x1f;
r31833	r31834
1169	914	offset |= 0xffffffc0;
1170	915	}
1171	916
1172		ea = (base) ? rsp->r[base] + (offset * 8) : (offset * 8);
	917	ea = (base) ? m_rsp_state->r[base] + (offset * 8) : (offset * 8);
1173	918
1174	919	int end = index + 8;
1175	920
1176	921	for (int i = index; i < end; i++)
1177	922	{
1178	923	UINT16 element;
1179		SIMD_EXTRACT16(rsp->xv[dest], element, (i >> 1));
	924	SIMD_EXTRACT16(m_xv[dest], element, (i >> 1));
1180	925	element &= 0xff00 >> ((1 - (i & 1)) * 8);
1181		element |= READ8(rsp, ea) << ((1 - (i & 1)) * 8);
1182		SIMD_INSERT16(rsp->xv[dest], element, (i >> 1));
	926	element |= DM_READ8(ea) << ((1 - (i & 1)) * 8);
	927	SIMD_INSERT16(m_xv[dest], element, (i >> 1));
1183	928	ea++;
1184	929	}
1185	930	}
1186	931
	932	static void cfunc_rsp_ldv_simd(void *param)
	933	{
	934	((rsp_device *)param)->ccfunc_rsp_ldv_simd();
	935	}
1187	936	#endif
1188	937
1189	938	#if (!USE_SIMD || SIMUL_SIMD)
1190	939
1191		static void cfunc_rsp_ldv_scalar(void *param)
	940	inline void rsp_device::ccfunc_rsp_ldv_scalar()
1192	941	{
1193		rsp_state *rsp = (rsp_state*)param;
1194		UINT32 op = rsp->impstate->arg0;
	942	UINT32 op = m_rsp_state->arg0;
1195	943	UINT32 ea = 0;
1196	944	int dest = (op >> 16) & 0x1f;
1197	945	int base = (op >> 21) & 0x1f;
r31833	r31834
1202	950	offset |= 0xffffffc0;
1203	951	}
1204	952
1205		ea = (base) ? rsp->r[base] + (offset * 8) : (offset * 8);
	953	ea = (base) ? m_rsp_state->r[base] + (offset * 8) : (offset * 8);
1206	954
1207	955	int end = index + 8;
1208	956
1209	957	for (int i = index; i < end; i++)
1210	958	{
1211		VREG_B(dest, i) = READ8(rsp, ea);
	959	VREG_B(dest, i) = DM_READ8(ea);
1212	960	ea++;
1213	961	}
1214	962	}
	963
	964	static void cfunc_rsp_ldv_scalar(void *param)
	965	{
	966	((rsp_device *)param)->ccfunc_rsp_ldv_scalar();
	967	}
1215	968	#endif
1216	969
1217	970	#if USE_SIMD
r31833	r31834
1224	977	//
1225	978	// Loads up to 16 bytes starting from vector byte index
1226	979
1227		static void cfunc_rsp_lqv_simd(void *param)
	980	inline void rsp_device::ccfunc_rsp_lqv_simd()
1228	981	{
1229		rsp_state *rsp = (rsp_state*)param;
1230		UINT32 op = rsp->impstate->arg0;
	982	UINT32 op = m_rsp_state->arg0;
1231	983	int dest = (op >> 16) & 0x1f;
1232	984	int base = (op >> 21) & 0x1f;
1233	985	int offset = (op & 0x7f);
r31833	r31834
1236	988	offset |= 0xffffffc0;
1237	989	}
1238	990
1239		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	991	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
1240	992
1241	993	int end = 16 - (ea & 0xf);
1242	994	if (end > 16) end = 16;
r31833	r31834
1244	996	for (int i = 0; i < end; i++)
1245	997	{
1246	998	UINT16 element;
1247		SIMD_EXTRACT16(rsp->xv[dest], element, (i >> 1));
	999	SIMD_EXTRACT16(m_xv[dest], element, (i >> 1));
1248	1000	element &= 0xff00 >> ((1 - (i & 1)) * 8);
1249		element |= READ8(rsp, ea) << ((1 - (i & 1)) * 8);
1250		SIMD_INSERT16(rsp->xv[dest], element, (i >> 1));
	1001	element |= DM_READ8(ea) << ((1 - (i & 1)) * 8);
	1002	SIMD_INSERT16(m_xv[dest], element, (i >> 1));
1251	1003	ea++;
1252	1004	}
1253	1005	}
1254	1006
	1007	static void cfunc_rsp_lqv_simd(void *param)
	1008	{
	1009	((rsp_device *)param)->ccfunc_rsp_lqv_simd();
	1010	}
1255	1011	#endif
1256	1012
1257	1013	#if (!USE_SIMD || SIMUL_SIMD)
1258	1014
1259		static void cfunc_rsp_lqv_scalar(void *param)
	1015	inline void rsp_device::ccfunc_rsp_lqv_scalar()
1260	1016	{
1261		rsp_state *rsp = (rsp_state*)param;
1262		UINT32 op = rsp->impstate->arg0;
	1017	UINT32 op = m_rsp_state->arg0;
1263	1018	int dest = (op >> 16) & 0x1f;
1264	1019	int base = (op >> 21) & 0x1f;
1265	1020	int offset = (op & 0x7f);
r31833	r31834
1268	1023	offset |= 0xffffffc0;
1269	1024	}
1270	1025
1271		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	1026	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
1272	1027
1273	1028	int end = 16 - (ea & 0xf);
1274	1029	if (end > 16) end = 16;
1275	1030
1276	1031	for (int i = 0; i < end; i++)
1277	1032	{
1278		VREG_B(dest, i) = READ8(rsp, ea);
	1033	VREG_B(dest, i) = DM_READ8(ea);
1279	1034	ea++;
1280	1035	}
1281	1036	}
	1037
	1038	static void cfunc_rsp_lqv_scalar(void *param)
	1039	{
	1040	((rsp_device *)param)->ccfunc_rsp_lqv_scalar();
	1041	}
1282	1042	#endif
1283	1043
1284	1044	#if USE_SIMD
r31833	r31834
1291	1051	//
1292	1052	// Stores up to 16 bytes starting from right side until 16-byte boundary
1293	1053
1294		static void cfunc_rsp_lrv_simd(void *param)
	1054	inline void rsp_device::ccfunc_rsp_lrv_simd()
1295	1055	{
1296		rsp_state *rsp = (rsp_state*)param;
1297		UINT32 op = rsp->impstate->arg0;
	1056	UINT32 op = m_rsp_state->arg0;
1298	1057	int dest = (op >> 16) & 0x1f;
1299	1058	int base = (op >> 21) & 0x1f;
1300	1059	int index = (op >> 7) & 0xf;
r31833	r31834
1304	1063	offset |= 0xffffffc0;
1305	1064	}
1306	1065
1307		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	1066	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
1308	1067
1309	1068	index = 16 - ((ea & 0xf) - index);
1310	1069	ea &= ~0xf;
r31833	r31834
1312	1071	for (int i = index; i < 16; i++)
1313	1072	{
1314	1073	UINT16 element;
1315		SIMD_EXTRACT16(rsp->xv[dest], element, (i >> 1));
	1074	SIMD_EXTRACT16(m_xv[dest], element, (i >> 1));
1316	1075	element &= 0xff00 >> ((1-(i & 1)) * 8);
1317		element |= READ8(rsp, ea) << ((1-(i & 1)) * 8);
1318		SIMD_INSERT16(rsp->xv[dest], element, (i >> 1));
	1076	element |= DM_READ8(ea) << ((1-(i & 1)) * 8);
	1077	SIMD_INSERT16(m_xv[dest], element, (i >> 1));
1319	1078	ea++;
1320	1079	}
1321	1080	}
1322	1081
	1082	static void cfunc_rsp_lrv_simd(void *param)
	1083	{
	1084	((rsp_device *)param)->ccfunc_rsp_lrv_simd();
	1085	}
1323	1086	#endif
1324	1087
1325	1088	#if (!USE_SIMD || SIMUL_SIMD)
1326	1089
1327		static void cfunc_rsp_lrv_scalar(void *param)
	1090	inline void rsp_device::ccfunc_rsp_lrv_scalar()
1328	1091	{
1329		rsp_state *rsp = (rsp_state*)param;
1330		UINT32 op = rsp->impstate->arg0;
	1092	UINT32 op = m_rsp_state->arg0;
1331	1093	int dest = (op >> 16) & 0x1f;
1332	1094	int base = (op >> 21) & 0x1f;
1333	1095	int index = (op >> 7) & 0xf;
r31833	r31834
1337	1099	offset |= 0xffffffc0;
1338	1100	}
1339	1101
1340		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	1102	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
1341	1103
1342	1104	index = 16 - ((ea & 0xf) - index);
1343	1105	ea &= ~0xf;
1344	1106
1345	1107	for (int i = index; i < 16; i++)
1346	1108	{
1347		VREG_B(dest, i) = READ8(rsp, ea);
	1109	VREG_B(dest, i) = DM_READ8(ea);
1348	1110	ea++;
1349	1111	}
1350	1112	}
	1113
	1114	static void cfunc_rsp_lrv_scalar(void *param)
	1115	{
	1116	((rsp_device *)param)->ccfunc_rsp_lrv_scalar();
	1117	}
1351	1118	#endif
1352	1119
1353	1120	#if USE_SIMD
r31833	r31834
1360	1127	//
1361	1128	// Loads a byte as the upper 8 bits of each element
1362	1129
1363		static void cfunc_rsp_lpv_simd(void *param)
	1130	inline void rsp_device::ccfunc_rsp_lpv_simd()
1364	1131	{
1365		rsp_state *rsp = (rsp_state*)param;
1366		UINT32 op = rsp->impstate->arg0;
	1132	UINT32 op = m_rsp_state->arg0;
1367	1133	int dest = (op >> 16) & 0x1f;
1368	1134	int base = (op >> 21) & 0x1f;
1369	1135	int index = (op >> 7) & 0xf;
r31833	r31834
1373	1139	offset |= 0xffffffc0;
1374	1140	}
1375	1141
1376		UINT32 ea = (base) ? rsp->r[base] + (offset * 8) : (offset * 8);
	1142	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 8) : (offset * 8);
1377	1143
1378	1144	for (int i = 0; i < 8; i++)
1379	1145	{
1380		SIMD_INSERT16(rsp->xv[dest], READ8(rsp, ea + (((16-index) + i) & 0xf)) << 8, i);
	1146	SIMD_INSERT16(m_xv[dest], DM_READ8(ea + (((16-index) + i) & 0xf)) << 8, i);
1381	1147	}
1382	1148	}
1383	1149
	1150	static void cfunc_rsp_lpv_simd(void *param)
	1151	{
	1152	((rsp_device *)param)->ccfunc_rsp_lpv_simd();
	1153	}
1384	1154	#endif
1385	1155
1386	1156	#if (!USE_SIMD || SIMUL_SIMD)
1387	1157
1388		static void cfunc_rsp_lpv_scalar(void *param)
	1158	inline void rsp_device::ccfunc_rsp_lpv_scalar()
1389	1159	{
1390		rsp_state *rsp = (rsp_state*)param;
1391		UINT32 op = rsp->impstate->arg0;
	1160	UINT32 op = m_rsp_state->arg0;
1392	1161	int dest = (op >> 16) & 0x1f;
1393	1162	int base = (op >> 21) & 0x1f;
1394	1163	int index = (op >> 7) & 0xf;
r31833	r31834
1398	1167	offset |= 0xffffffc0;
1399	1168	}
1400	1169
1401		UINT32 ea = (base) ? rsp->r[base] + (offset * 8) : (offset * 8);
	1170	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 8) : (offset * 8);
1402	1171
1403	1172	for (int i = 0; i < 8; i++)
1404	1173	{
1405		W_VREG_S(dest, i) = READ8(rsp, ea + (((16-index) + i) & 0xf)) << 8;
	1174	W_VREG_S(dest, i) = DM_READ8(ea + (((16-index) + i) & 0xf)) << 8;
1406	1175	}
1407	1176	}
	1177
	1178	static void cfunc_rsp_lpv_scalar(void *param)
	1179	{
	1180	((rsp_device *)param)->ccfunc_rsp_lpv_scalar();
	1181	}
1408	1182	#endif
1409	1183
1410	1184	#if USE_SIMD
r31833	r31834
1417	1191	//
1418	1192	// Loads a byte as the bits 14-7 of each element
1419	1193
1420		static void cfunc_rsp_luv_simd(void *param)
	1194	inline void rsp_device::ccfunc_rsp_luv_simd()
1421	1195	{
1422		rsp_state *rsp = (rsp_state*)param;
1423		UINT32 op = rsp->impstate->arg0;
	1196	UINT32 op = m_rsp_state->arg0;
1424	1197	int dest = (op >> 16) & 0x1f;
1425	1198	int base = (op >> 21) & 0x1f;
1426	1199	int index = (op >> 7) & 0xf;
r31833	r31834
1430	1203	offset |= 0xffffffc0;
1431	1204	}
1432	1205
1433		UINT32 ea = (base) ? rsp->r[base] + (offset * 8) : (offset * 8);
	1206	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 8) : (offset * 8);
1434	1207
1435	1208	for (int i = 0; i < 8; i++)
1436	1209	{
1437		SIMD_INSERT16(rsp->xv[dest], READ8(rsp, ea + (((16-index) + i) & 0xf)) << 7, i);
	1210	SIMD_INSERT16(m_xv[dest], DM_READ8(ea + (((16-index) + i) & 0xf)) << 7, i);
1438	1211	}
1439	1212	}
1440	1213
	1214	static void cfunc_rsp_luv_simd(void *param)
	1215	{
	1216	((rsp_device *)param)->ccfunc_rsp_luv_simd();
	1217	}
1441	1218	#endif
1442	1219
1443	1220	#if (!USE_SIMD || SIMUL_SIMD)
1444	1221
1445		static void cfunc_rsp_luv_scalar(void *param)
	1222	inline void rsp_device::ccfunc_rsp_luv_scalar()
1446	1223	{
1447		rsp_state *rsp = (rsp_state*)param;
1448		UINT32 op = rsp->impstate->arg0;
	1224	UINT32 op = m_rsp_state->arg0;
1449	1225	int dest = (op >> 16) & 0x1f;
1450	1226	int base = (op >> 21) & 0x1f;
1451	1227	int index = (op >> 7) & 0xf;
r31833	r31834
1455	1231	offset |= 0xffffffc0;
1456	1232	}
1457	1233
1458		UINT32 ea = (base) ? rsp->r[base] + (offset * 8) : (offset * 8);
	1234	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 8) : (offset * 8);
1459	1235
1460	1236	for (int i = 0; i < 8; i++)
1461	1237	{
1462		W_VREG_S(dest, i) = READ8(rsp, ea + (((16-index) + i) & 0xf)) << 7;
	1238	W_VREG_S(dest, i) = DM_READ8(ea + (((16-index) + i) & 0xf)) << 7;
1463	1239	}
1464	1240	}
	1241
	1242	static void cfunc_rsp_luv_scalar(void *param)
	1243	{
	1244	((rsp_device *)param)->ccfunc_rsp_luv_scalar();
	1245	}
1465	1246	#endif
1466	1247
1467	1248	#if USE_SIMD
r31833	r31834
1474	1255	//
1475	1256	// Loads a byte as the bits 14-7 of each element, with 2-byte stride
1476	1257
1477		static void cfunc_rsp_lhv_simd(void *param)
	1258	inline void rsp_device::ccfunc_rsp_lhv_simd()
1478	1259	{
1479		rsp_state *rsp = (rsp_state*)param;
1480		UINT32 op = rsp->impstate->arg0;
	1260	UINT32 op = m_rsp_state->arg0;
1481	1261	int dest = (op >> 16) & 0x1f;
1482	1262	int base = (op >> 21) & 0x1f;
1483	1263	int index = (op >> 7) & 0xf;
r31833	r31834
1487	1267	offset |= 0xffffffc0;
1488	1268	}
1489	1269
1490		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	1270	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
1491	1271
1492	1272	for (int i = 0; i < 8; i++)
1493	1273	{
1494		SIMD_INSERT16(rsp->xv[dest], READ8(rsp, ea + (((16-index) + (i<<1)) & 0xf)) << 7, i);
	1274	SIMD_INSERT16(m_xv[dest], DM_READ8(ea + (((16-index) + (i<<1)) & 0xf)) << 7, i);
1495	1275	}
1496	1276	}
1497	1277
	1278	static void cfunc_rsp_lhv_simd(void *param)
	1279	{
	1280	((rsp_device *)param)->ccfunc_rsp_lhv_simd();
	1281	}
1498	1282	#endif
1499	1283
1500	1284	#if (!USE_SIMD || SIMUL_SIMD)
1501	1285
1502		static void cfunc_rsp_lhv_scalar(void *param)
	1286	inline void rsp_device::ccfunc_rsp_lhv_scalar()
1503	1287	{
1504		rsp_state *rsp = (rsp_state*)param;
1505		UINT32 op = rsp->impstate->arg0;
	1288	UINT32 op = m_rsp_state->arg0;
1506	1289	int dest = (op >> 16) & 0x1f;
1507	1290	int base = (op >> 21) & 0x1f;
1508	1291	int index = (op >> 7) & 0xf;
r31833	r31834
1512	1295	offset |= 0xffffffc0;
1513	1296	}
1514	1297
1515		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	1298	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
1516	1299
1517	1300	for (int i = 0; i < 8; i++)
1518	1301	{
1519		W_VREG_S(dest, i) = READ8(rsp, ea + (((16-index) + (i<<1)) & 0xf)) << 7;
	1302	W_VREG_S(dest, i) = DM_READ8(ea + (((16-index) + (i<<1)) & 0xf)) << 7;
1520	1303	}
1521	1304	}
	1305
	1306	static void cfunc_rsp_lhv_scalar(void *param)
	1307	{
	1308	((rsp_device *)param)->ccfunc_rsp_lhv_scalar();
	1309	}
1522	1310	#endif
1523	1311
1524	1312	#if USE_SIMD
r31833	r31834
1530	1318	//
1531	1319	// Loads a byte as the bits 14-7 of upper or lower quad, with 4-byte stride
1532	1320
1533		static void cfunc_rsp_lfv_simd(void *param)
	1321	inline void rsp_device::ccfunc_rsp_lfv_simd()
1534	1322	{
1535		rsp_state *rsp = (rsp_state*)param;
1536		UINT32 op = rsp->impstate->arg0;
	1323	UINT32 op = m_rsp_state->arg0;
1537	1324	int dest = (op >> 16) & 0x1f;
1538	1325	int base = (op >> 21) & 0x1f;
1539	1326	int index = (op >> 7) & 0xf;
r31833	r31834
1543	1330	offset |= 0xffffffc0;
1544	1331	}
1545	1332
1546		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	1333	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
1547	1334
1548	1335	// not sure what happens if 16-byte boundary is crossed...
1549	1336
r31833	r31834
1551	1338
1552	1339	for (int i = index >> 1; i < end; i++)
1553	1340	{
1554		SIMD_INSERT16(rsp->xv[dest], READ8(rsp, ea) << 7, i);
	1341	SIMD_INSERT16(m_xv[dest], DM_READ8(ea) << 7, i);
1555	1342	ea += 4;
1556	1343	}
1557	1344	}
1558	1345
	1346	static void cfunc_rsp_lfv_simd(void *param)
	1347	{
	1348	((rsp_device *)param)->ccfunc_rsp_lfv_simd();
	1349	}
1559	1350	#endif
1560	1351
1561	1352	#if (!USE_SIMD || SIMUL_SIMD)
1562	1353
1563		static void cfunc_rsp_lfv_scalar(void *param)
	1354	inline void rsp_device::ccfunc_rsp_lfv_scalar()
1564	1355	{
1565		rsp_state *rsp = (rsp_state*)param;
1566		UINT32 op = rsp->impstate->arg0;
	1356	UINT32 op = m_rsp_state->arg0;
1567	1357	int dest = (op >> 16) & 0x1f;
1568	1358	int base = (op >> 21) & 0x1f;
1569	1359	int index = (op >> 7) & 0xf;
r31833	r31834
1573	1363	offset |= 0xffffffc0;
1574	1364	}
1575	1365
1576		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	1366	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
1577	1367
1578	1368	// not sure what happens if 16-byte boundary is crossed...
1579	1369
r31833	r31834
1581	1371
1582	1372	for (int i = index >> 1; i < end; i++)
1583	1373	{
1584		W_VREG_S(dest, i) = READ8(rsp, ea) << 7;
	1374	W_VREG_S(dest, i) = DM_READ8(ea) << 7;
1585	1375	ea += 4;
1586	1376	}
1587	1377	}
	1378
	1379	static void cfunc_rsp_lfv_scalar(void *param)
	1380	{
	1381	((rsp_device *)param)->ccfunc_rsp_lfv_scalar();
	1382	}
1588	1383	#endif
1589	1384
1590	1385	#if USE_SIMD
r31833	r31834
1598	1393	// Loads the full 128-bit vector starting from vector byte index and wrapping to index 0
1599	1394	// after byte index 15
1600	1395
1601		static void cfunc_rsp_lwv_simd(void *param)
	1396	inline void rsp_device::ccfunc_rsp_lwv_simd()
1602	1397	{
1603		rsp_state *rsp = (rsp_state*)param;
1604		UINT32 op = rsp->impstate->arg0;
	1398	UINT32 op = m_rsp_state->arg0;
1605	1399	int dest = (op >> 16) & 0x1f;
1606	1400	int base = (op >> 21) & 0x1f;
1607	1401	int index = (op >> 7) & 0xf;
r31833	r31834
1611	1405	offset |= 0xffffffc0;
1612	1406	}
1613	1407
1614		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	1408	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
1615	1409	int end = (16 - index) + 16;
1616	1410
1617	1411	UINT8 val[16];
1618	1412	for (int i = (16 - index); i < end; i++)
1619	1413	{
1620		val[i & 0xf] = READ8(rsp, ea);
	1414	val[i & 0xf] = DM_READ8(ea);
1621	1415	ea += 4;
1622	1416	}
1623	1417
1624		rsp->xv[dest] = _mm_set_epi8(val[15], val[14], val[13], val[12], val[11], val[10], val[ 9], val[ 8],
	1418	m_xv[dest] = _mm_set_epi8(val[15], val[14], val[13], val[12], val[11], val[10], val[ 9], val[ 8],
1625	1419	val[ 7], val[ 6], val[ 5], val[ 4], val[ 3], val[ 2], val[ 1], val[ 0]);
1626	1420	}
1627	1421
	1422	static void cfunc_rsp_lwv_simd(void *param)
	1423	{
	1424	((rsp_device *)param)->ccfunc_rsp_lwv_simd();
	1425	}
1628	1426	#endif
1629	1427
1630	1428	#if (!USE_SIMD || SIMUL_SIMD)
1631	1429
1632		static void cfunc_rsp_lwv_scalar(void *param)
	1430	inline void rsp_device::ccfunc_rsp_lwv_scalar()
1633	1431	{
1634		rsp_state *rsp = (rsp_state*)param;
1635		UINT32 op = rsp->impstate->arg0;
	1432	UINT32 op = m_rsp_state->arg0;
1636	1433	int dest = (op >> 16) & 0x1f;
1637	1434	int base = (op >> 21) & 0x1f;
1638	1435	int index = (op >> 7) & 0xf;
r31833	r31834
1642	1439	offset |= 0xffffffc0;
1643	1440	}
1644	1441
1645		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	1442	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
1646	1443	int end = (16 - index) + 16;
1647	1444
1648	1445	for (int i = (16 - index); i < end; i++)
1649	1446	{
1650		VREG_B(dest, i & 0xf) = READ8(rsp, ea);
	1447	VREG_B(dest, i & 0xf) = DM_READ8(ea);
1651	1448	ea += 4;
1652	1449	}
1653	1450	}
	1451
	1452	static void cfunc_rsp_lwv_scalar(void *param)
	1453	{
	1454	((rsp_device *)param)->ccfunc_rsp_lwv_scalar();
	1455	}
1654	1456	#endif
1655	1457
1656	1458	#if USE_SIMD
r31833	r31834
1663	1465	//
1664	1466	// Loads one element to maximum of 8 vectors, while incrementing element index
1665	1467
1666		static void cfunc_rsp_ltv_simd(void *param)
	1468	inline void rsp_device::ccfunc_rsp_ltv_simd()
1667	1469	{
1668		rsp_state *rsp = (rsp_state*)param;
1669		UINT32 op = rsp->impstate->arg0;
	1470	UINT32 op = m_rsp_state->arg0;
1670	1471	int dest = (op >> 16) & 0x1f;
1671	1472	int base = (op >> 21) & 0x1f;
1672	1473	int index = (op >> 7) & 0xf;
r31833	r31834
1683	1484
1684	1485	int element = 7 - (index >> 1);
1685	1486
1686		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	1487	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
1687	1488
1688	1489	ea = ((ea + 8) & ~0xf) + (index & 1);
1689	1490	for (int i = vs; i < ve; i++)
1690	1491	{
1691	1492	element = (8 - (index >> 1) + (i - vs)) << 1;
1692		UINT16 value = (READ8(rsp, ea) << 8) | READ8(rsp, ea + 1);
1693		SIMD_INSERT16(rsp->xv[i], value, (element >> 1));
	1493	UINT16 value = (DM_READ8(ea) << 8) | DM_READ8(ea + 1);
	1494	SIMD_INSERT16(m_xv[i], value, (element >> 1));
1694	1495	ea += 2;
1695	1496	}
1696	1497	}
1697	1498
	1499	static void cfunc_rsp_ltv_simd(void *param)
	1500	{
	1501	((rsp_device *)param)->ccfunc_rsp_ltv_simd();
	1502	}
1698	1503	#endif
1699	1504
1700	1505	#if (!USE_SIMD || SIMUL_SIMD)
1701	1506
1702		static void cfunc_rsp_ltv_scalar(void *param)
	1507	inline void rsp_device::ccfunc_rsp_ltv_scalar()
1703	1508	{
1704		rsp_state *rsp = (rsp_state*)param;
1705		UINT32 op = rsp->impstate->arg0;
	1509	UINT32 op = m_rsp_state->arg0;
1706	1510	int dest = (op >> 16) & 0x1f;
1707	1511	int base = (op >> 21) & 0x1f;
1708	1512	int index = (op >> 7) & 0xf;
r31833	r31834
1719	1523
1720	1524	int element = 7 - (index >> 1);
1721	1525
1722		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	1526	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
1723	1527
1724	1528	ea = ((ea + 8) & ~0xf) + (index & 1);
1725	1529	for (int i = vs; i < ve; i++)
1726	1530	{
1727	1531	element = (8 - (index >> 1) + (i - vs)) << 1;
1728		VREG_B(i, (element & 0xf)) = READ8(rsp, ea);
1729		VREG_B(i, ((element + 1) & 0xf)) = READ8(rsp, ea + 1);
	1532	VREG_B(i, (element & 0xf)) = DM_READ8(ea);
	1533	VREG_B(i, ((element + 1) & 0xf)) = DM_READ8(ea + 1);
1730	1534	ea += 2;
1731	1535	}
1732	1536	}
	1537
	1538	static void cfunc_rsp_ltv_scalar(void *param)
	1539	{
	1540	((rsp_device *)param)->ccfunc_rsp_ltv_scalar();
	1541	}
1733	1542	#endif
1734	1543
1735	1544	#if USE_SIMD && SIMUL_SIMD
1736		INLINE void cfunc_backup_regs(void *param)
	1545	inline void rsp_device::ccfunc_backup_regs()
1737	1546	{
1738		rsp_state *rsp = (rsp_state*)param;
1739		memcpy(rsp->old_dmem, rsp->dmem8, sizeof(rsp->old_dmem));
1740		memcpy(rsp->old_r, rsp->r, sizeof(rsp->r));
	1547	memcpy(m_old_dmem, m_dmem8, sizeof(m_old_dmem));
	1548	memcpy(m_old_r, m_r, sizeof(m_r));
1741	1549
1742		rsp->simd_reciprocal_res = rsp->reciprocal_res;
1743		rsp->simd_reciprocal_high = rsp->reciprocal_high;
1744		rsp->simd_dp_allowed = rsp->dp_allowed;
	1550	m_simd_reciprocal_res = m_reciprocal_res;
	1551	m_simd_reciprocal_high = m_reciprocal_high;
	1552	m_simd_dp_allowed = m_dp_allowed;
1745	1553
1746		rsp->reciprocal_res = rsp->old_reciprocal_res;
1747		rsp->reciprocal_high = rsp->old_reciprocal_high;
1748		rsp->dp_allowed = rsp->old_dp_allowed;
	1554	m_reciprocal_res = m_old_reciprocal_res;
	1555	m_reciprocal_high = m_old_reciprocal_high;
	1556	m_dp_allowed = m_old_dp_allowed;
1749	1557	}
1750	1558
1751		INLINE void cfunc_restore_regs(void *param)
	1559	static void cfunc_backup_regs(void *param)
1752	1560	{
1753		rsp_state *rsp = (rsp_state*)param;
1754		memcpy(rsp->scalar_r, rsp->r, sizeof(rsp->r));
1755		memcpy(rsp->r, rsp->old_r, sizeof(rsp->r));
1756		memcpy(rsp->scalar_dmem, rsp->dmem8, sizeof(rsp->scalar_dmem));
1757		memcpy(rsp->dmem8, rsp->old_dmem, sizeof(rsp->old_dmem));
	1561	((rsp_device *)param)->ccfunc_backup_regs();
	1562	}
1758	1563
1759		rsp->scalar_reciprocal_res = rsp->reciprocal_res;
1760		rsp->scalar_reciprocal_high = rsp->reciprocal_high;
1761		rsp->scalar_dp_allowed = rsp->dp_allowed;
	1564	inline void rsp_device::ccfunc_restore_regs()
	1565	{
	1566	memcpy(m_scalar_r, m_r, sizeof(m_r));
	1567	memcpy(m_r, m_old_r, sizeof(m_r));
	1568	memcpy(m_scalar_dmem, m_dmem8, sizeof(m_scalar_dmem));
	1569	memcpy(m_dmem8, m_old_dmem, sizeof(m_old_dmem));
1762	1570
1763		rsp->reciprocal_res = rsp->simd_reciprocal_res;
1764		rsp->reciprocal_high = rsp->simd_reciprocal_high;
1765		rsp->dp_allowed = rsp->simd_dp_allowed;
	1571	m_scalar_reciprocal_res = m_reciprocal_res;
	1572	m_scalar_reciprocal_high = m_reciprocal_high;
	1573	m_scalar_dp_allowed = m_dp_allowed;
	1574
	1575	m_reciprocal_res = m_simd_reciprocal_res;
	1576	m_reciprocal_high = m_simd_reciprocal_high;
	1577	m_dp_allowed = m_simd_dp_allowed;
1766	1578	}
1767	1579
1768		INLINE void cfunc_verify_regs(void *param)
	1580	static void cfunc_restore_regs(void *param)
1769	1581	{
1770		rsp_state *rsp = (rsp_state*)param;
1771		int op = rsp->impstate->arg0;
1772		if (VEC_ACCUM_H(rsp, 0) != ACCUM_H(rsp, 0)) fatalerror("ACCUM_H element 0 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_H(rsp, 0), ACCUM_H(rsp, 0), op);
1773		if (VEC_ACCUM_H(rsp, 1) != ACCUM_H(rsp, 1)) fatalerror("ACCUM_H element 1 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_H(rsp, 1), ACCUM_H(rsp, 1), op);
1774		if (VEC_ACCUM_H(rsp, 2) != ACCUM_H(rsp, 2)) fatalerror("ACCUM_H element 2 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_H(rsp, 2), ACCUM_H(rsp, 2), op);
1775		if (VEC_ACCUM_H(rsp, 3) != ACCUM_H(rsp, 3)) fatalerror("ACCUM_H element 3 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_H(rsp, 3), ACCUM_H(rsp, 3), op);
1776		if (VEC_ACCUM_H(rsp, 4) != ACCUM_H(rsp, 4)) fatalerror("ACCUM_H element 4 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_H(rsp, 4), ACCUM_H(rsp, 4), op);
1777		if (VEC_ACCUM_H(rsp, 5) != ACCUM_H(rsp, 5)) fatalerror("ACCUM_H element 5 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_H(rsp, 5), ACCUM_H(rsp, 5), op);
1778		if (VEC_ACCUM_H(rsp, 6) != ACCUM_H(rsp, 6)) fatalerror("ACCUM_H element 6 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_H(rsp, 6), ACCUM_H(rsp, 6), op);
1779		if (VEC_ACCUM_H(rsp, 7) != ACCUM_H(rsp, 7)) fatalerror("ACCUM_H element 7 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_H(rsp, 7), ACCUM_H(rsp, 7), op);
1780		if (VEC_ACCUM_M(rsp, 0) != ACCUM_M(rsp, 0)) fatalerror("ACCUM_M element 0 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_M(rsp, 0), ACCUM_M(rsp, 0), op);
1781		if (VEC_ACCUM_M(rsp, 1) != ACCUM_M(rsp, 1)) fatalerror("ACCUM_M element 1 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_M(rsp, 1), ACCUM_M(rsp, 1), op);
1782		if (VEC_ACCUM_M(rsp, 2) != ACCUM_M(rsp, 2)) fatalerror("ACCUM_M element 2 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_M(rsp, 2), ACCUM_M(rsp, 2), op);
1783		if (VEC_ACCUM_M(rsp, 3) != ACCUM_M(rsp, 3)) fatalerror("ACCUM_M element 3 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_M(rsp, 3), ACCUM_M(rsp, 3), op);
1784		if (VEC_ACCUM_M(rsp, 4) != ACCUM_M(rsp, 4)) fatalerror("ACCUM_M element 4 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_M(rsp, 4), ACCUM_M(rsp, 4), op);
1785		if (VEC_ACCUM_M(rsp, 5) != ACCUM_M(rsp, 5)) fatalerror("ACCUM_M element 5 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_M(rsp, 5), ACCUM_M(rsp, 5), op);
1786		if (VEC_ACCUM_M(rsp, 6) != ACCUM_M(rsp, 6)) fatalerror("ACCUM_M element 6 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_M(rsp, 6), ACCUM_M(rsp, 6), op);
1787		if (VEC_ACCUM_M(rsp, 7) != ACCUM_M(rsp, 7)) fatalerror("ACCUM_M element 7 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_M(rsp, 7), ACCUM_M(rsp, 7), op);
1788		if (VEC_ACCUM_L(rsp, 0) != ACCUM_L(rsp, 0)) fatalerror("ACCUM_L element 0 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_L(rsp, 0), ACCUM_L(rsp, 0), op);
1789		if (VEC_ACCUM_L(rsp, 1) != ACCUM_L(rsp, 1)) fatalerror("ACCUM_L element 1 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_L(rsp, 1), ACCUM_L(rsp, 1), op);
1790		if (VEC_ACCUM_L(rsp, 2) != ACCUM_L(rsp, 2)) fatalerror("ACCUM_L element 2 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_L(rsp, 2), ACCUM_L(rsp, 2), op);
1791		if (VEC_ACCUM_L(rsp, 3) != ACCUM_L(rsp, 3)) fatalerror("ACCUM_L element 3 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_L(rsp, 3), ACCUM_L(rsp, 3), op);
1792		if (VEC_ACCUM_L(rsp, 4) != ACCUM_L(rsp, 4)) fatalerror("ACCUM_L element 4 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_L(rsp, 4), ACCUM_L(rsp, 4), op);
1793		if (VEC_ACCUM_L(rsp, 5) != ACCUM_L(rsp, 5)) fatalerror("ACCUM_L element 5 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_L(rsp, 5), ACCUM_L(rsp, 5), op);
1794		if (VEC_ACCUM_L(rsp, 6) != ACCUM_L(rsp, 6)) fatalerror("ACCUM_L element 6 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_L(rsp, 6), ACCUM_L(rsp, 6), op);
1795		if (VEC_ACCUM_L(rsp, 7) != ACCUM_L(rsp, 7)) fatalerror("ACCUM_L element 7 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_L(rsp, 7), ACCUM_L(rsp, 7), op);
	1582	((rsp_device *)param)->ccfunc_restore_regs();
	1583	}
	1584
	1585	inline void rsp_device::ccfunc_verify_regs()
	1586	{
	1587	int op = m_rsp_state->arg0;
	1588	if (VEC_ACCUM_H(0) != ACCUM_H(0)) fatalerror("ACCUM_H element 0 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_H(0), ACCUM_H(0), op);
	1589	if (VEC_ACCUM_H(1) != ACCUM_H(1)) fatalerror("ACCUM_H element 1 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_H(1), ACCUM_H(1), op);
	1590	if (VEC_ACCUM_H(2) != ACCUM_H(2)) fatalerror("ACCUM_H element 2 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_H(2), ACCUM_H(2), op);
	1591	if (VEC_ACCUM_H(3) != ACCUM_H(3)) fatalerror("ACCUM_H element 3 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_H(3), ACCUM_H(3), op);
	1592	if (VEC_ACCUM_H(4) != ACCUM_H(4)) fatalerror("ACCUM_H element 4 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_H(4), ACCUM_H(4), op);
	1593	if (VEC_ACCUM_H(5) != ACCUM_H(5)) fatalerror("ACCUM_H element 5 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_H(5), ACCUM_H(5), op);
	1594	if (VEC_ACCUM_H(6) != ACCUM_H(6)) fatalerror("ACCUM_H element 6 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_H(6), ACCUM_H(6), op);
	1595	if (VEC_ACCUM_H(7) != ACCUM_H(7)) fatalerror("ACCUM_H element 7 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_H(7), ACCUM_H(7), op);
	1596	if (VEC_ACCUM_M(0) != ACCUM_M(0)) fatalerror("ACCUM_M element 0 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_M(0), ACCUM_M(0), op);
	1597	if (VEC_ACCUM_M(1) != ACCUM_M(1)) fatalerror("ACCUM_M element 1 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_M(1), ACCUM_M(1), op);
	1598	if (VEC_ACCUM_M(2) != ACCUM_M(2)) fatalerror("ACCUM_M element 2 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_M(2), ACCUM_M(2), op);
	1599	if (VEC_ACCUM_M(3) != ACCUM_M(3)) fatalerror("ACCUM_M element 3 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_M(3), ACCUM_M(3), op);
	1600	if (VEC_ACCUM_M(4) != ACCUM_M(4)) fatalerror("ACCUM_M element 4 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_M(4), ACCUM_M(4), op);
	1601	if (VEC_ACCUM_M(5) != ACCUM_M(5)) fatalerror("ACCUM_M element 5 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_M(5), ACCUM_M(5), op);
	1602	if (VEC_ACCUM_M(6) != ACCUM_M(6)) fatalerror("ACCUM_M element 6 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_M(6), ACCUM_M(6), op);
	1603	if (VEC_ACCUM_M(7) != ACCUM_M(7)) fatalerror("ACCUM_M element 7 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_M(7), ACCUM_M(7), op);
	1604	if (VEC_ACCUM_L(0) != ACCUM_L(0)) fatalerror("ACCUM_L element 0 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_L(0), ACCUM_L(0), op);
	1605	if (VEC_ACCUM_L(1) != ACCUM_L(1)) fatalerror("ACCUM_L element 1 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_L(1), ACCUM_L(1), op);
	1606	if (VEC_ACCUM_L(2) != ACCUM_L(2)) fatalerror("ACCUM_L element 2 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_L(2), ACCUM_L(2), op);
	1607	if (VEC_ACCUM_L(3) != ACCUM_L(3)) fatalerror("ACCUM_L element 3 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_L(3), ACCUM_L(3), op);
	1608	if (VEC_ACCUM_L(4) != ACCUM_L(4)) fatalerror("ACCUM_L element 4 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_L(4), ACCUM_L(4), op);
	1609	if (VEC_ACCUM_L(5) != ACCUM_L(5)) fatalerror("ACCUM_L element 5 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_L(5), ACCUM_L(5), op);
	1610	if (VEC_ACCUM_L(6) != ACCUM_L(6)) fatalerror("ACCUM_L element 6 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_L(6), ACCUM_L(6), op);
	1611	if (VEC_ACCUM_L(7) != ACCUM_L(7)) fatalerror("ACCUM_L element 7 mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", VEC_ACCUM_L(7), ACCUM_L(7), op);
1796	1612	for (int i = 0; i < 32; i++)
1797	1613	{
1798		if (rsp->r[i] != rsp->scalar_r[i]) fatalerror("r[%d] mismatch (SIMD %08x vs. Scalar %08x) after op: %08x\n", i, rsp->r[i], rsp->scalar_r[i], op);
	1614	if (m_rsp_state->r[i] != m_scalar_r[i]) fatalerror("r[%d] mismatch (SIMD %08x vs. Scalar %08x) after op: %08x\n", i, m_rsp_state->r[i], m_scalar_r[i], op);
1799	1615	for (int el = 0; el < 8; el++)
1800	1616	{
1801	1617	UINT16 out;
1802		SIMD_EXTRACT16(rsp->xv[i], out, el);
	1618	SIMD_EXTRACT16(m_xv[i], out, el);
1803	1619	if ((UINT16)VREG_S(i, el) != out) fatalerror("Vector %d element %d mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", i, el, out, (UINT16)VREG_S(i, el), op);
1804	1620	}
1805	1621	}
1806	1622	for (int i = 0; i < 4096; i++)
1807	1623	{
1808		if (rsp->dmem8[i] != rsp->scalar_dmem[i]) fatalerror("dmem[%d] mismatch (SIMD %02x vs. Scalar %02x) after op: %08x\n", i, rsp->dmem8[i], rsp->scalar_dmem[i], op);
	1624	if (m_dmem8[i] != m_scalar_dmem[i]) fatalerror("dmem[%d] mismatch (SIMD %02x vs. Scalar %02x) after op: %08x\n", i, m_dmem8[i], m_scalar_dmem[i], op);
1809	1625	}
1810	1626	for (int i = 0; i < 5; i++)
1811	1627	{
1812	1628	for (int el = 0; el < 8; el++)
1813	1629	{
1814	1630	UINT16 out;
1815		SIMD_EXTRACT16(rsp->xvflag[i], out, el);
1816		if (rsp->vflag[i][el] != out) fatalerror("flag[%d][%d] mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", i, el, out, rsp->vflag[i][el], op);
	1631	SIMD_EXTRACT16(m_xvflag[i], out, el);
	1632	if (m_vflag[i][el] != out) fatalerror("flag[%d][%d] mismatch (SIMD %04x vs. Scalar %04x) after op: %08x\n", i, el, out, m_vflag[i][el], op);
1817	1633	}
1818	1634	}
1819	1635	}
	1636
	1637	static void cfunc_verify_regs(void *param)
	1638	{
	1639	((rsp_device *)param)->ccfunc_verify_regs();
	1640	}
1820	1641	#endif
1821	1642
1822	1643	#if USE_SIMD
1823		static int generate_lwc2(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
	1644	int rsp_device::generate_lwc2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
1824	1645	{
1825	1646	//int loopdest;
1826	1647	UINT32 op = desc->opptr.l[0];
r31833	r31834
1838	1659	{
1839	1660	case 0x00:      /* LBV */
1840	1661	//UML_ADD(block, I0, R32(RSREG), offset);
1841		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
1842		UML_CALLC(block, cfunc_rsp_lbv_simd, rsp);
	1662	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1663	UML_CALLC(block, cfunc_rsp_lbv_simd, this);
1843	1664	#if SIMUL_SIMD
1844		UML_CALLC(block, cfunc_backup_regs, rsp);
1845		UML_CALLC(block, cfunc_rsp_lbv_scalar, rsp);
1846		UML_CALLC(block, cfunc_restore_regs, rsp);
1847		UML_CALLC(block, cfunc_verify_regs, rsp);
	1665	UML_CALLC(block, cfunc_backup_regs, this);
	1666	UML_CALLC(block, cfunc_rsp_lbv_scalar, this);
	1667	UML_CALLC(block, cfunc_restore_regs, this);
	1668	UML_CALLC(block, cfunc_verify_regs, this);
1848	1669	#endif
1849	1670	return TRUE;
1850	1671	case 0x01:      /* LSV */
1851		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
1852		UML_CALLC(block, cfunc_rsp_lsv_simd, rsp);
	1672	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1673	UML_CALLC(block, cfunc_rsp_lsv_simd, this);
1853	1674	#if SIMUL_SIMD
1854		UML_CALLC(block, cfunc_backup_regs, rsp);
1855		UML_CALLC(block, cfunc_rsp_lsv_scalar, rsp);
1856		UML_CALLC(block, cfunc_restore_regs, rsp);
1857		UML_CALLC(block, cfunc_verify_regs, rsp);
	1675	UML_CALLC(block, cfunc_backup_regs, this);
	1676	UML_CALLC(block, cfunc_rsp_lsv_scalar, this);
	1677	UML_CALLC(block, cfunc_restore_regs, this);
	1678	UML_CALLC(block, cfunc_verify_regs, this);
1858	1679	#endif
1859	1680	return TRUE;
1860	1681	case 0x02:      /* LLV */
1861		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
1862		UML_CALLC(block, cfunc_rsp_llv_simd, rsp);
	1682	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1683	UML_CALLC(block, cfunc_rsp_llv_simd, this);
1863	1684	#if SIMUL_SIMD
1864		UML_CALLC(block, cfunc_backup_regs, rsp);
1865		UML_CALLC(block, cfunc_rsp_llv_scalar, rsp);
1866		UML_CALLC(block, cfunc_restore_regs, rsp);
1867		UML_CALLC(block, cfunc_verify_regs, rsp);
	1685	UML_CALLC(block, cfunc_backup_regs, this);
	1686	UML_CALLC(block, cfunc_rsp_llv_scalar, this);
	1687	UML_CALLC(block, cfunc_restore_regs, this);
	1688	UML_CALLC(block, cfunc_verify_regs, this);
1868	1689	#endif
1869	1690	return TRUE;
1870	1691	case 0x03:      /* LDV */
1871		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
1872		UML_CALLC(block, cfunc_rsp_ldv_simd, rsp);
	1692	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1693	UML_CALLC(block, cfunc_rsp_ldv_simd, this);
1873	1694	#if SIMUL_SIMD
1874		UML_CALLC(block, cfunc_backup_regs, rsp);
1875		UML_CALLC(block, cfunc_rsp_ldv_scalar, rsp);
1876		UML_CALLC(block, cfunc_restore_regs, rsp);
1877		UML_CALLC(block, cfunc_verify_regs, rsp);
	1695	UML_CALLC(block, cfunc_backup_regs, this);
	1696	UML_CALLC(block, cfunc_rsp_ldv_scalar, this);
	1697	UML_CALLC(block, cfunc_restore_regs, this);
	1698	UML_CALLC(block, cfunc_verify_regs, this);
1878	1699	#endif
1879	1700	return TRUE;
1880	1701	case 0x04:      /* LQV */
1881		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
1882		UML_CALLC(block, cfunc_rsp_lqv_simd, rsp);
	1702	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1703	UML_CALLC(block, cfunc_rsp_lqv_simd, this);
1883	1704	#if SIMUL_SIMD
1884		UML_CALLC(block, cfunc_backup_regs, rsp);
1885		UML_CALLC(block, cfunc_rsp_lqv_scalar, rsp);
1886		UML_CALLC(block, cfunc_restore_regs, rsp);
1887		UML_CALLC(block, cfunc_verify_regs, rsp);
	1705	UML_CALLC(block, cfunc_backup_regs, this);
	1706	UML_CALLC(block, cfunc_rsp_lqv_scalar, this);
	1707	UML_CALLC(block, cfunc_restore_regs, this);
	1708	UML_CALLC(block, cfunc_verify_regs, this);
1888	1709	#endif
1889	1710	return TRUE;
1890	1711	case 0x05:      /* LRV */
1891		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
1892		UML_CALLC(block, cfunc_rsp_lrv_simd, rsp);
	1712	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1713	UML_CALLC(block, cfunc_rsp_lrv_simd, this);
1893	1714	#if SIMUL_SIMD
1894		UML_CALLC(block, cfunc_backup_regs, rsp);
1895		UML_CALLC(block, cfunc_rsp_lrv_scalar, rsp);
1896		UML_CALLC(block, cfunc_restore_regs, rsp);
1897		UML_CALLC(block, cfunc_verify_regs, rsp);
	1715	UML_CALLC(block, cfunc_backup_regs, this);
	1716	UML_CALLC(block, cfunc_rsp_lrv_scalar, this);
	1717	UML_CALLC(block, cfunc_restore_regs, this);
	1718	UML_CALLC(block, cfunc_verify_regs, this);
1898	1719	#endif
1899	1720	return TRUE;
1900	1721	case 0x06:      /* LPV */
1901		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
1902		UML_CALLC(block, cfunc_rsp_lpv_simd, rsp);
	1722	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1723	UML_CALLC(block, cfunc_rsp_lpv_simd, this);
1903	1724	#if SIMUL_SIMD
1904		UML_CALLC(block, cfunc_backup_regs, rsp);
1905		UML_CALLC(block, cfunc_rsp_lpv_scalar, rsp);
1906		UML_CALLC(block, cfunc_restore_regs, rsp);
1907		UML_CALLC(block, cfunc_verify_regs, rsp);
	1725	UML_CALLC(block, cfunc_backup_regs, this);
	1726	UML_CALLC(block, cfunc_rsp_lpv_scalar, this);
	1727	UML_CALLC(block, cfunc_restore_regs, this);
	1728	UML_CALLC(block, cfunc_verify_regs, this);
1908	1729	#endif
1909	1730	return TRUE;
1910	1731	case 0x07:      /* LUV */
1911		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
1912		UML_CALLC(block, cfunc_rsp_luv_simd, rsp);
	1732	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1733	UML_CALLC(block, cfunc_rsp_luv_simd, this);
1913	1734	#if SIMUL_SIMD
1914		UML_CALLC(block, cfunc_backup_regs, rsp);
1915		UML_CALLC(block, cfunc_rsp_luv_scalar, rsp);
1916		UML_CALLC(block, cfunc_restore_regs, rsp);
1917		UML_CALLC(block, cfunc_verify_regs, rsp);
	1735	UML_CALLC(block, cfunc_backup_regs, this);
	1736	UML_CALLC(block, cfunc_rsp_luv_scalar, this);
	1737	UML_CALLC(block, cfunc_restore_regs, this);
	1738	UML_CALLC(block, cfunc_verify_regs, this);
1918	1739	#endif
1919	1740	return TRUE;
1920	1741	case 0x08:      /* LHV */
1921		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
1922		UML_CALLC(block, cfunc_rsp_lhv_simd, rsp);
	1742	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1743	UML_CALLC(block, cfunc_rsp_lhv_simd, this);
1923	1744	#if SIMUL_SIMD
1924		UML_CALLC(block, cfunc_backup_regs, rsp);
1925		UML_CALLC(block, cfunc_rsp_lhv_scalar, rsp);
1926		UML_CALLC(block, cfunc_restore_regs, rsp);
1927		UML_CALLC(block, cfunc_verify_regs, rsp);
	1745	UML_CALLC(block, cfunc_backup_regs, this);
	1746	UML_CALLC(block, cfunc_rsp_lhv_scalar, this);
	1747	UML_CALLC(block, cfunc_restore_regs, this);
	1748	UML_CALLC(block, cfunc_verify_regs, this);
1928	1749	#endif
1929	1750	return TRUE;
1930	1751	case 0x09:      /* LFV */
1931		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
1932		UML_CALLC(block, cfunc_rsp_lfv_simd, rsp);
	1752	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1753	UML_CALLC(block, cfunc_rsp_lfv_simd, this);
1933	1754	#if SIMUL_SIMD
1934		UML_CALLC(block, cfunc_backup_regs, rsp);
1935		UML_CALLC(block, cfunc_rsp_lfv_scalar, rsp);
1936		UML_CALLC(block, cfunc_restore_regs, rsp);
1937		UML_CALLC(block, cfunc_verify_regs, rsp);
	1755	UML_CALLC(block, cfunc_backup_regs, this);
	1756	UML_CALLC(block, cfunc_rsp_lfv_scalar, this);
	1757	UML_CALLC(block, cfunc_restore_regs, this);
	1758	UML_CALLC(block, cfunc_verify_regs, this);
1938	1759	#endif
1939	1760	return TRUE;
1940	1761	case 0x0a:      /* LWV */
1941		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
1942		UML_CALLC(block, cfunc_rsp_lwv_simd, rsp);
	1762	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1763	UML_CALLC(block, cfunc_rsp_lwv_simd, this);
1943	1764	#if SIMUL_SIMD
1944		UML_CALLC(block, cfunc_backup_regs, rsp);
1945		UML_CALLC(block, cfunc_rsp_lwv_scalar, rsp);
1946		UML_CALLC(block, cfunc_restore_regs, rsp);
1947		UML_CALLC(block, cfunc_verify_regs, rsp);
	1765	UML_CALLC(block, cfunc_backup_regs, this);
	1766	UML_CALLC(block, cfunc_rsp_lwv_scalar, this);
	1767	UML_CALLC(block, cfunc_restore_regs, this);
	1768	UML_CALLC(block, cfunc_verify_regs, this);
1948	1769	#endif
1949	1770	return TRUE;
1950	1771	case 0x0b:      /* LTV */
1951		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
1952		UML_CALLC(block, cfunc_rsp_ltv_simd, rsp);
	1772	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1773	UML_CALLC(block, cfunc_rsp_ltv_simd, this);
1953	1774	#if SIMUL_SIMD
1954		UML_CALLC(block, cfunc_backup_regs, rsp);
1955		UML_CALLC(block, cfunc_rsp_ltv_scalar, rsp);
1956		UML_CALLC(block, cfunc_restore_regs, rsp);
1957		UML_CALLC(block, cfunc_verify_regs, rsp);
	1775	UML_CALLC(block, cfunc_backup_regs, this);
	1776	UML_CALLC(block, cfunc_rsp_ltv_scalar, this);
	1777	UML_CALLC(block, cfunc_restore_regs, this);
	1778	UML_CALLC(block, cfunc_verify_regs, this);
1958	1779	#endif
1959	1780	return TRUE;
1960	1781
r31833	r31834
1965	1786
1966	1787	#else
1967	1788
1968		static int generate_lwc2(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
	1789	int rsp_device::generate_lwc2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
1969	1790	{
1970	1791	//int loopdest;
1971	1792	UINT32 op = desc->opptr.l[0];
r31833	r31834
1983	1804	{
1984	1805	case 0x00:      /* LBV */
1985	1806	//UML_ADD(block, I0, R32(RSREG), offset);
1986		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
1987		UML_CALLC(block, cfunc_rsp_lbv_scalar, rsp);
	1807	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1808	UML_CALLC(block, cfunc_rsp_lbv_scalar, this);
1988	1809	return TRUE;
1989	1810	case 0x01:      /* LSV */
1990		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
1991		UML_CALLC(block, cfunc_rsp_lsv_scalar, rsp);
	1811	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1812	UML_CALLC(block, cfunc_rsp_lsv_scalar, this);
1992	1813	return TRUE;
1993	1814	case 0x02:      /* LLV */
1994		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
1995		UML_CALLC(block, cfunc_rsp_llv_scalar, rsp);
	1815	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1816	UML_CALLC(block, cfunc_rsp_llv_scalar, this);
1996	1817	return TRUE;
1997	1818	case 0x03:      /* LDV */
1998		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
1999		UML_CALLC(block, cfunc_rsp_ldv_scalar, rsp);
	1819	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1820	UML_CALLC(block, cfunc_rsp_ldv_scalar, this);
2000	1821	return TRUE;
2001	1822	case 0x04:      /* LQV */
2002		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
2003		UML_CALLC(block, cfunc_rsp_lqv_scalar, rsp);
	1823	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1824	UML_CALLC(block, cfunc_rsp_lqv_scalar, this);
2004	1825	return TRUE;
2005	1826	case 0x05:      /* LRV */
2006		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
2007		UML_CALLC(block, cfunc_rsp_lrv_scalar, rsp);
	1827	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1828	UML_CALLC(block, cfunc_rsp_lrv_scalar, this);
2008	1829	return TRUE;
2009	1830	case 0x06:      /* LPV */
2010		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
2011		UML_CALLC(block, cfunc_rsp_lpv_scalar, rsp);
	1831	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1832	UML_CALLC(block, cfunc_rsp_lpv_scalar, this);
2012	1833	return TRUE;
2013	1834	case 0x07:      /* LUV */
2014		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
2015		UML_CALLC(block, cfunc_rsp_luv_scalar, rsp);
	1835	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1836	UML_CALLC(block, cfunc_rsp_luv_scalar, this);
2016	1837	return TRUE;
2017	1838	case 0x08:      /* LHV */
2018		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
2019		UML_CALLC(block, cfunc_rsp_lhv_scalar, rsp);
	1839	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1840	UML_CALLC(block, cfunc_rsp_lhv_scalar, this);
2020	1841	return TRUE;
2021	1842	case 0x09:      /* LFV */
2022		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
2023		UML_CALLC(block, cfunc_rsp_lfv_scalar, rsp);
	1843	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1844	UML_CALLC(block, cfunc_rsp_lfv_scalar, this);
2024	1845	return TRUE;
2025	1846	case 0x0a:      /* LWV */
2026		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
2027		UML_CALLC(block, cfunc_rsp_lwv_scalar, rsp);
	1847	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1848	UML_CALLC(block, cfunc_rsp_lwv_scalar, this);
2028	1849	return TRUE;
2029	1850	case 0x0b:      /* LTV */
2030		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
2031		UML_CALLC(block, cfunc_rsp_ltv_scalar, rsp);
	1851	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	1852	UML_CALLC(block, cfunc_rsp_ltv_scalar, this);
2032	1853	return TRUE;
2033	1854
2034	1855	default:
r31833	r31834
2047	1868	//
2048	1869	// Stores 1 byte from vector byte index
2049	1870
2050		static void cfunc_rsp_sbv_simd(void *param)
	1871	inline void rsp_device::ccfunc_rsp_sbv_simd()
2051	1872	{
2052		rsp_state *rsp = (rsp_state*)param;
2053		UINT32 op = rsp->impstate->arg0;
	1873	UINT32 op = m_rsp_state->arg0;
2054	1874	int dest = (op >> 16) & 0x1f;
2055	1875	int base = (op >> 21) & 0x1f;
2056	1876	int index = (op >> 7) & 0xf;
r31833	r31834
2060	1880	offset |= 0xffffffc0;
2061	1881	}
2062	1882
2063		UINT32 ea = (base) ? rsp->r[base] + offset : offset;
	1883	UINT32 ea = (base) ? m_rsp_state->r[base] + offset : offset;
2064	1884	UINT16 value;
2065		SIMD_EXTRACT16(rsp->xv[dest], value, (index >> 1));
	1885	SIMD_EXTRACT16(m_xv[dest], value, (index >> 1));
2066	1886	value >>= (1-(index & 1)) * 8;
2067		WRITE8(rsp, ea, (UINT8)value);
	1887	DM_WRITE8(ea, (UINT8)value);
2068	1888	}
2069	1889
	1890	static void cfunc_rsp_sbv_simd(void *param)
	1891	{
	1892	((rsp_device *)param)->ccfunc_rsp_sbv_simd();
	1893	}
2070	1894	#endif
2071	1895
2072	1896	#if (!USE_SIMD || SIMUL_SIMD)
2073	1897
2074		static void cfunc_rsp_sbv_scalar(void *param)
	1898	inline void rsp_device::ccfunc_rsp_sbv_scalar()
2075	1899	{
2076		rsp_state *rsp = (rsp_state*)param;
2077		UINT32 op = rsp->impstate->arg0;
	1900	UINT32 op = m_rsp_state->arg0;
2078	1901	int dest = (op >> 16) & 0x1f;
2079	1902	int base = (op >> 21) & 0x1f;
2080	1903	int index = (op >> 7) & 0xf;
r31833	r31834
2084	1907	offset |= 0xffffffc0;
2085	1908	}
2086	1909
2087		UINT32 ea = (base) ? rsp->r[base] + offset : offset;
2088		WRITE8(rsp, ea, VREG_B(dest, index));
	1910	UINT32 ea = (base) ? m_rsp_state->r[base] + offset : offset;
	1911	DM_WRITE8(ea, VREG_B(dest, index));
2089	1912	}
	1913
	1914	static void cfunc_rsp_sbv_scalar(void *param)
	1915	{
	1916	((rsp_device *)param)->ccfunc_rsp_sbv_scalar();
	1917	}
2090	1918	#endif
2091	1919
2092	1920	#if USE_SIMD
r31833	r31834
2099	1927	//
2100	1928	// Stores 2 bytes starting from vector byte index
2101	1929
2102		static void cfunc_rsp_ssv_simd(void *param)
	1930	inline void rsp_device::ccfunc_rsp_ssv_simd()
2103	1931	{
2104		rsp_state *rsp = (rsp_state*)param;
2105		UINT32 op = rsp->impstate->arg0;
	1932	UINT32 op = m_rsp_state->arg0;
2106	1933	int dest = (op >> 16) & 0x1f;
2107	1934	int base = (op >> 21) & 0x1f;
2108	1935	int index = (op >> 7) & 0xf;
r31833	r31834
2112	1939	offset |= 0xffffffc0;
2113	1940	}
2114	1941
2115		UINT32 ea = (base) ? rsp->r[base] + (offset * 2) : (offset * 2);
	1942	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 2) : (offset * 2);
2116	1943
2117	1944	int end = index + 2;
2118	1945	for (int i = index; i < end; i++)
2119	1946	{
2120	1947	UINT16 value;
2121		SIMD_EXTRACT16(rsp->xv[dest], value, (i >> 1));
	1948	SIMD_EXTRACT16(m_xv[dest], value, (i >> 1));
2122	1949	value >>= (1 - (i & 1)) * 8;
2123		WRITE8(rsp, ea, (UINT8)value);
	1950	DM_WRITE8(ea, (UINT8)value);
2124	1951	ea++;
2125	1952	}
2126	1953	}
2127	1954
	1955	static void cfunc_rsp_ssv_simd(void *param)
	1956	{
	1957	((rsp_device *)param)->ccfunc_rsp_ssv_simd();
	1958	}
2128	1959	#endif
2129	1960
2130	1961	#if (!USE_SIMD || SIMUL_SIMD)
2131	1962
2132		static void cfunc_rsp_ssv_scalar(void *param)
	1963	inline void rsp_device::ccfunc_rsp_ssv_scalar()
2133	1964	{
2134		rsp_state *rsp = (rsp_state*)param;
2135		UINT32 op = rsp->impstate->arg0;
	1965	UINT32 op = m_rsp_state->arg0;
2136	1966	int dest = (op >> 16) & 0x1f;
2137	1967	int base = (op >> 21) & 0x1f;
2138	1968	int index = (op >> 7) & 0xf;
r31833	r31834
2142	1972	offset |= 0xffffffc0;
2143	1973	}
2144	1974
2145		UINT32 ea = (base) ? rsp->r[base] + (offset * 2) : (offset * 2);
	1975	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 2) : (offset * 2);
2146	1976
2147	1977	int end = index + 2;
2148	1978	for (int i = index; i < end; i++)
2149	1979	{
2150		WRITE8(rsp, ea, VREG_B(dest, i));
	1980	DM_WRITE8(ea, VREG_B(dest, i));
2151	1981	ea++;
2152	1982	}
2153	1983	}
	1984
	1985	static void cfunc_rsp_ssv_scalar(void *param)
	1986	{
	1987	((rsp_device *)param)->ccfunc_rsp_ssv_scalar();
	1988	}
2154	1989	#endif
2155	1990
2156	1991	#if USE_SIMD
r31833	r31834
2163	1998	//
2164	1999	// Stores 4 bytes starting from vector byte index
2165	2000
2166		static void cfunc_rsp_slv_simd(void *param)
	2001	inline void rsp_device::ccfunc_rsp_slv_simd()
2167	2002	{
2168		rsp_state *rsp = (rsp_state*)param;
2169		UINT32 op = rsp->impstate->arg0;
	2003	UINT32 op = m_rsp_state->arg0;
2170	2004	int dest = (op >> 16) & 0x1f;
2171	2005	int base = (op >> 21) & 0x1f;
2172	2006	int index = (op >> 7) & 0xf;
r31833	r31834
2176	2010	offset |= 0xffffffc0;
2177	2011	}
2178	2012
2179		UINT32 ea = (base) ? rsp->r[base] + (offset * 4) : (offset * 4);
	2013	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 4) : (offset * 4);
2180	2014
2181	2015	int end = index + 4;
2182	2016	for (int i = index; i < end; i++)
2183	2017	{
2184	2018	UINT16 value;
2185		SIMD_EXTRACT16(rsp->xv[dest], value, (i >> 1));
	2019	SIMD_EXTRACT16(m_xv[dest], value, (i >> 1));
2186	2020	value >>= (1 - (i & 1)) * 8;
2187		WRITE8(rsp, ea, (UINT8)value);
	2021	DM_WRITE8(ea, (UINT8)value);
2188	2022	ea++;
2189	2023	}
2190	2024	}
2191	2025
	2026	static void cfunc_rsp_slv_simd(void *param)
	2027	{
	2028	((rsp_device *)param)->ccfunc_rsp_slv_simd();
	2029	}
2192	2030	#endif
2193	2031
2194	2032	#if (!USE_SIMD || SIMUL_SIMD)
2195	2033
2196		static void cfunc_rsp_slv_scalar(void *param)
	2034	inline void rsp_device::ccfunc_rsp_slv_scalar()
2197	2035	{
2198		rsp_state *rsp = (rsp_state*)param;
2199		UINT32 op = rsp->impstate->arg0;
	2036	UINT32 op = m_rsp_state->arg0;
2200	2037	int dest = (op >> 16) & 0x1f;
2201	2038	int base = (op >> 21) & 0x1f;
2202	2039	int index = (op >> 7) & 0xf;
r31833	r31834
2206	2043	offset |= 0xffffffc0;
2207	2044	}
2208	2045
2209		UINT32 ea = (base) ? rsp->r[base] + (offset * 4) : (offset * 4);
	2046	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 4) : (offset * 4);
2210	2047
2211	2048	int end = index + 4;
2212	2049	for (int i = index; i < end; i++)
2213	2050	{
2214		WRITE8(rsp, ea, VREG_B(dest, i));
	2051	DM_WRITE8(ea, VREG_B(dest, i));
2215	2052	ea++;
2216	2053	}
2217	2054	}
	2055
	2056	static void cfunc_rsp_slv_scalar(void *param)
	2057	{
	2058	((rsp_device *)param)->ccfunc_rsp_slv_scalar();
	2059	}
2218	2060	#endif
2219	2061
2220	2062	#if USE_SIMD
r31833	r31834
2227	2069	//
2228	2070	// Stores 8 bytes starting from vector byte index
2229	2071
2230		static void cfunc_rsp_sdv_simd(void *param)
	2072	inline void rsp_device::ccfunc_rsp_sdv_simd()
2231	2073	{
2232		rsp_state *rsp = (rsp_state*)param;
2233		UINT32 op = rsp->impstate->arg0;
	2074	UINT32 op = m_rsp_state->arg0;
2234	2075	int dest = (op >> 16) & 0x1f;
2235	2076	int base = (op >> 21) & 0x1f;
2236	2077	int index = (op >> 7) & 0x8;
r31833	r31834
2239	2080	{
2240	2081	offset |= 0xffffffc0;
2241	2082	}
2242		UINT32 ea = (base) ? rsp->r[base] + (offset * 8) : (offset * 8);
	2083	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 8) : (offset * 8);
2243	2084
2244	2085	int end = index + 8;
2245	2086	for (int i = index; i < end; i++)
2246	2087	{
2247	2088	UINT16 value;
2248		SIMD_EXTRACT16(rsp->xv[dest], value, (i >> 1));
	2089	SIMD_EXTRACT16(m_xv[dest], value, (i >> 1));
2249	2090	value >>= (1 - (i & 1)) * 8;
2250		WRITE8(rsp, ea, (UINT8)value);
	2091	DM_WRITE8(ea, (UINT8)value);
2251	2092	ea++;
2252	2093	}
2253	2094	}
2254	2095
	2096	static void cfunc_rsp_sdv_simd(void *param)
	2097	{
	2098	((rsp_device *)param)->ccfunc_rsp_sdv_simd();
	2099	}
2255	2100	#endif
2256	2101
2257	2102	#if (!USE_SIMD || SIMUL_SIMD)
2258	2103
2259		static void cfunc_rsp_sdv_scalar(void *param)
	2104	inline void rsp_device::ccfunc_rsp_sdv_scalar()
2260	2105	{
2261		rsp_state *rsp = (rsp_state*)param;
2262		UINT32 op = rsp->impstate->arg0;
	2106	UINT32 op = m_rsp_state->arg0;
2263	2107	int dest = (op >> 16) & 0x1f;
2264	2108	int base = (op >> 21) & 0x1f;
2265	2109	int index = (op >> 7) & 0x8;
r31833	r31834
2268	2112	{
2269	2113	offset |= 0xffffffc0;
2270	2114	}
2271		UINT32 ea = (base) ? rsp->r[base] + (offset * 8) : (offset * 8);
	2115	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 8) : (offset * 8);
2272	2116
2273	2117	int end = index + 8;
2274	2118	for (int i = index; i < end; i++)
2275	2119	{
2276		WRITE8(rsp, ea, VREG_B(dest, i));
	2120	DM_WRITE8(ea, VREG_B(dest, i));
2277	2121	ea++;
2278	2122	}
2279	2123	}
	2124
	2125	static void cfunc_rsp_sdv_scalar(void *param)
	2126	{
	2127	((rsp_device *)param)->ccfunc_rsp_sdv_scalar();
	2128	}
2280	2129	#endif
2281	2130
2282	2131	#if USE_SIMD
r31833	r31834
2289	2138	//
2290	2139	// Stores up to 16 bytes starting from vector byte index until 16-byte boundary
2291	2140
2292		static void cfunc_rsp_sqv_simd(void *param)
	2141	inline void rsp_device::ccfunc_rsp_sqv_simd()
2293	2142	{
2294		rsp_state *rsp = (rsp_state*)param;
2295		UINT32 op = rsp->impstate->arg0;
	2143	UINT32 op = m_rsp_state->arg0;
2296	2144	int dest = (op >> 16) & 0x1f;
2297	2145	int base = (op >> 21) & 0x1f;
2298	2146	int index = (op >> 7) & 0xf;
r31833	r31834
2302	2150	offset |= 0xffffffc0;
2303	2151	}
2304	2152
2305		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	2153	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
2306	2154	int end = index + (16 - (ea & 0xf));
2307	2155	for (int i=index; i < end; i++)
2308	2156	{
2309	2157	UINT16 value;
2310		SIMD_EXTRACT16(rsp->xv[dest], value, (i >> 1));
	2158	SIMD_EXTRACT16(m_xv[dest], value, (i >> 1));
2311	2159	value >>= (1-(i & 1)) * 8;
2312		WRITE8(rsp, ea, (UINT8)value);
	2160	DM_WRITE8(ea, (UINT8)value);
2313	2161	ea++;
2314	2162	}
2315	2163	}
2316	2164
	2165	static void cfunc_rsp_sqv_simd(void *param)
	2166	{
	2167	((rsp_device *)param)->ccfunc_rsp_sqv_simd();
	2168	}
2317	2169	#endif
2318	2170
2319	2171	#if (!USE_SIMD || SIMUL_SIMD)
2320	2172
2321		static void cfunc_rsp_sqv_scalar(void *param)
	2173	inline void rsp_device::ccfunc_rsp_sqv_scalar()
2322	2174	{
2323		rsp_state *rsp = (rsp_state*)param;
2324		UINT32 op = rsp->impstate->arg0;
	2175	UINT32 op = m_rsp_state->arg0;
2325	2176	int dest = (op >> 16) & 0x1f;
2326	2177	int base = (op >> 21) & 0x1f;
2327	2178	int index = (op >> 7) & 0xf;
r31833	r31834
2331	2182	offset |= 0xffffffc0;
2332	2183	}
2333	2184
2334		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	2185	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
2335	2186	int end = index + (16 - (ea & 0xf));
2336	2187	for (int i=index; i < end; i++)
2337	2188	{
2338		WRITE8(rsp, ea, VREG_B(dest, i & 0xf));
	2189	DM_WRITE8(ea, VREG_B(dest, i & 0xf));
2339	2190	ea++;
2340	2191	}
2341	2192	}
	2193
	2194	static void cfunc_rsp_sqv_scalar(void *param)
	2195	{
	2196	((rsp_device *)param)->ccfunc_rsp_sqv_scalar();
	2197	}
2342	2198	#endif
2343	2199
2344	2200	#if USE_SIMD
r31833	r31834
2351	2207	//
2352	2208	// Stores up to 16 bytes starting from right side until 16-byte boundary
2353	2209
2354		static void cfunc_rsp_srv_simd(void *param)
	2210	inline void rsp_device::ccfunc_rsp_srv_simd()
2355	2211	{
2356		rsp_state *rsp = (rsp_state*)param;
2357		UINT32 op = rsp->impstate->arg0;
	2212	UINT32 op = m_rsp_state->arg0;
2358	2213	int dest = (op >> 16) & 0x1f;
2359	2214	int base = (op >> 21) & 0x1f;
2360	2215	int index = (op >> 7) & 0xf;
r31833	r31834
2364	2219	offset |= 0xffffffc0;
2365	2220	}
2366	2221
2367		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	2222	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
2368	2223
2369	2224	int end = index + (ea & 0xf);
2370	2225	int o = (16 - (ea & 0xf)) & 0xf;
r31833	r31834
2374	2229	{
2375	2230	UINT32 bi = (i + o) & 0xf;
2376	2231	UINT16 value;
2377		SIMD_EXTRACT16(rsp->xv[dest], value, (bi >> 1));
	2232	SIMD_EXTRACT16(m_xv[dest], value, (bi >> 1));
2378	2233	value >>= (1-(bi & 1)) * 8;
2379		WRITE8(rsp, ea, (UINT8)value);
	2234	DM_WRITE8(ea, (UINT8)value);
2380	2235	ea++;
2381	2236	}
2382	2237	}
2383	2238
	2239	static void cfunc_rsp_srv_simd(void *param)
	2240	{
	2241	((rsp_device *)param)->ccfunc_rsp_srv_simd();
	2242	}
2384	2243	#endif
2385	2244
2386	2245	#if (!USE_SIMD || SIMUL_SIMD)
2387	2246
2388		static void cfunc_rsp_srv_scalar(void *param)
	2247	inline void rsp_device::ccfunc_rsp_srv_scalar()
2389	2248	{
2390		rsp_state *rsp = (rsp_state*)param;
2391		UINT32 op = rsp->impstate->arg0;
	2249	UINT32 op = m_rsp_state->arg0;
2392	2250	int dest = (op >> 16) & 0x1f;
2393	2251	int base = (op >> 21) & 0x1f;
2394	2252	int index = (op >> 7) & 0xf;
r31833	r31834
2398	2256	offset |= 0xffffffc0;
2399	2257	}
2400	2258
2401		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	2259	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
2402	2260
2403	2261	int end = index + (ea & 0xf);
2404	2262	int o = (16 - (ea & 0xf)) & 0xf;
r31833	r31834
2406	2264
2407	2265	for (int i = index; i < end; i++)
2408	2266	{
2409		WRITE8(rsp, ea, VREG_B(dest, ((i + o) & 0xf)));
	2267	DM_WRITE8(ea, VREG_B(dest, ((i + o) & 0xf)));
2410	2268	ea++;
2411	2269	}
2412	2270	}
	2271
	2272	static void cfunc_rsp_srv_scalar(void *param)
	2273	{
	2274	((rsp_device *)param)->ccfunc_rsp_srv_scalar();
	2275	}
2413	2276	#endif
2414	2277
2415	2278	#if USE_SIMD
r31833	r31834
2422	2285	//
2423	2286	// Stores upper 8 bits of each element
2424	2287
2425		static void cfunc_rsp_spv_simd(void *param)
	2288	inline void rsp_device::ccfunc_rsp_spv_simd()
2426	2289	{
2427		rsp_state *rsp = (rsp_state*)param;
2428		UINT32 op = rsp->impstate->arg0;
	2290	UINT32 op = m_rsp_state->arg0;
2429	2291	int dest = (op >> 16) & 0x1f;
2430	2292	int base = (op >> 21) & 0x1f;
2431	2293	int index = (op >> 7) & 0xf;
r31833	r31834
2435	2297	offset |= 0xffffffc0;
2436	2298	}
2437	2299
2438		UINT32 ea = (base) ? rsp->r[base] + (offset * 8) : (offset * 8);
	2300	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 8) : (offset * 8);
2439	2301	int end = index + 8;
2440	2302	for (int i=index; i < end; i++)
2441	2303	{
2442	2304	if ((i & 0xf) < 8)
2443	2305	{
2444	2306	UINT16 value;
2445		SIMD_EXTRACT16(rsp->xv[dest], value, i);
2446		WRITE8(rsp, ea, (UINT8)(value >> 8));
	2307	SIMD_EXTRACT16(m_xv[dest], value, i);
	2308	DM_WRITE8(ea, (UINT8)(value >> 8));
2447	2309	}
2448	2310	else
2449	2311	{
2450	2312	UINT16 value;
2451		SIMD_EXTRACT16(rsp->xv[dest], value, i);
2452		WRITE8(rsp, ea, (UINT8)(value >> 7));
	2313	SIMD_EXTRACT16(m_xv[dest], value, i);
	2314	DM_WRITE8(ea, (UINT8)(value >> 7));
2453	2315	}
2454	2316	ea++;
2455	2317	}
2456	2318	}
2457	2319
	2320	static void cfunc_rsp_spv_simd(void *param)
	2321	{
	2322	((rsp_device *)param)->ccfunc_rsp_spv_simd();
	2323	}
2458	2324	#endif
2459	2325
2460	2326	#if (!USE_SIMD || SIMUL_SIMD)
2461	2327
2462		static void cfunc_rsp_spv_scalar(void *param)
	2328	inline void rsp_device::ccfunc_rsp_spv_scalar()
2463	2329	{
2464		rsp_state *rsp = (rsp_state*)param;
2465		UINT32 op = rsp->impstate->arg0;
	2330	UINT32 op = m_rsp_state->arg0;
2466	2331	int dest = (op >> 16) & 0x1f;
2467	2332	int base = (op >> 21) & 0x1f;
2468	2333	int index = (op >> 7) & 0xf;
r31833	r31834
2472	2337	offset |= 0xffffffc0;
2473	2338	}
2474	2339
2475		UINT32 ea = (base) ? rsp->r[base] + (offset * 8) : (offset * 8);
	2340	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 8) : (offset * 8);
2476	2341	int end = index + 8;
2477	2342	for (int i=index; i < end; i++)
2478	2343	{
2479	2344	if ((i & 0xf) < 8)
2480	2345	{
2481		WRITE8(rsp, ea, VREG_B(dest, (i & 0xf) << 1));
	2346	DM_WRITE8(ea, VREG_B(dest, (i & 0xf) << 1));
2482	2347	}
2483	2348	else
2484	2349	{
2485		WRITE8(rsp, ea, VREG_S(dest, (i & 0x7)) >> 7);
	2350	DM_WRITE8(ea, VREG_S(dest, (i & 0x7)) >> 7);
2486	2351	}
2487	2352	ea++;
2488	2353	}
2489	2354	}
	2355
	2356	static void cfunc_rsp_spv_scalar(void *param)
	2357	{
	2358	((rsp_device *)param)->ccfunc_rsp_spv_scalar();
	2359	}
2490	2360	#endif
2491	2361
2492	2362	#if USE_SIMD
r31833	r31834
2499	2369	//
2500	2370	// Stores bits 14-7 of each element
2501	2371
2502		static void cfunc_rsp_suv_simd(void *param)
	2372	inline void rsp_device::ccfunc_rsp_suv_simd()
2503	2373	{
2504		rsp_state *rsp = (rsp_state*)param;
2505		UINT32 op = rsp->impstate->arg0;
	2374	UINT32 op = m_rsp_state->arg0;
2506	2375	int dest = (op >> 16) & 0x1f;
2507	2376	int base = (op >> 21) & 0x1f;
2508	2377	int index = (op >> 7) & 0xf;
r31833	r31834
2512	2381	offset |= 0xffffffc0;
2513	2382	}
2514	2383
2515		UINT32 ea = (base) ? rsp->r[base] + (offset * 8) : (offset * 8);
	2384	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 8) : (offset * 8);
2516	2385	int end = index + 8;
2517	2386	for (int i=index; i < end; i++)
2518	2387	{
2519	2388	if ((i & 0xf) < 8)
2520	2389	{
2521	2390	UINT16 value;
2522		SIMD_EXTRACT16(rsp->xv[dest], value, i);
2523		WRITE8(rsp, ea, (UINT8)(value >> 7));
	2391	SIMD_EXTRACT16(m_xv[dest], value, i);
	2392	DM_WRITE8(ea, (UINT8)(value >> 7));
2524	2393	}
2525	2394	else
2526	2395	{
2527	2396	UINT16 value;
2528		SIMD_EXTRACT16(rsp->xv[dest], value, i);
2529		WRITE8(rsp, ea, (UINT8)(value >> 8));
	2397	SIMD_EXTRACT16(m_xv[dest], value, i);
	2398	DM_WRITE8(ea, (UINT8)(value >> 8));
2530	2399	}
2531	2400	ea++;
2532	2401	}
2533	2402	}
2534	2403
	2404	static void cfunc_rsp_suv_simd(void *param)
	2405	{
	2406	((rsp_device *)param)->ccfunc_rsp_suv_simd();
	2407	}
2535	2408	#endif
2536	2409
2537	2410	#if (!USE_SIMD || SIMUL_SIMD)
2538	2411
2539		static void cfunc_rsp_suv_scalar(void *param)
	2412	inline void rsp_device::ccfunc_rsp_suv_scalar()
2540	2413	{
2541		rsp_state *rsp = (rsp_state*)param;
2542		UINT32 op = rsp->impstate->arg0;
	2414	UINT32 op = m_rsp_state->arg0;
2543	2415	int dest = (op >> 16) & 0x1f;
2544	2416	int base = (op >> 21) & 0x1f;
2545	2417	int index = (op >> 7) & 0xf;
r31833	r31834
2549	2421	offset |= 0xffffffc0;
2550	2422	}
2551	2423
2552		UINT32 ea = (base) ? rsp->r[base] + (offset * 8) : (offset * 8);
	2424	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 8) : (offset * 8);
2553	2425	int end = index + 8;
2554	2426	for (int i=index; i < end; i++)
2555	2427	{
2556	2428	if ((i & 0xf) < 8)
2557	2429	{
2558		WRITE8(rsp, ea, VREG_S(dest, (i & 0x7)) >> 7);
	2430	DM_WRITE8(ea, VREG_S(dest, (i & 0x7)) >> 7);
2559	2431	}
2560	2432	else
2561	2433	{
2562		WRITE8(rsp, ea, VREG_B(dest, ((i & 0x7) << 1)));
	2434	DM_WRITE8(ea, VREG_B(dest, ((i & 0x7) << 1)));
2563	2435	}
2564	2436	ea++;
2565	2437	}
2566	2438	}
	2439
	2440	static void cfunc_rsp_suv_scalar(void *param)
	2441	{
	2442	((rsp_device *)param)->ccfunc_rsp_suv_scalar();
	2443	}
2567	2444	#endif
2568	2445
2569	2446	#if USE_SIMD
r31833	r31834
2576	2453	//
2577	2454	// Stores bits 14-7 of each element, with 2-byte stride
2578	2455
2579		static void cfunc_rsp_shv_simd(void *param)
	2456	inline void rsp_device::ccfunc_rsp_shv_simd()
2580	2457	{
2581		rsp_state *rsp = (rsp_state*)param;
2582		UINT32 op = rsp->impstate->arg0;
	2458	UINT32 op = m_rsp_state->arg0;
2583	2459	int dest = (op >> 16) & 0x1f;
2584	2460	int base = (op >> 21) & 0x1f;
2585	2461	int index = (op >> 7) & 0xf;
r31833	r31834
2589	2465	offset |= 0xffffffc0;
2590	2466	}
2591	2467
2592		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	2468	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
2593	2469	for (int i=0; i < 8; i++)
2594	2470	{
2595	2471	int element = index + (i << 1);
2596	2472	UINT16 value;
2597		SIMD_EXTRACT16(rsp->xv[dest], value, element >> 1);
2598		WRITE8(rsp, ea, (value >> 7) & 0x00ff);
	2473	SIMD_EXTRACT16(m_xv[dest], value, element >> 1);
	2474	DM_WRITE8(ea, (value >> 7) & 0x00ff);
2599	2475	ea += 2;
2600	2476	}
2601	2477	}
2602	2478
	2479	static void cfunc_rsp_shv_simd(void *param)
	2480	{
	2481	((rsp_device *)param)->ccfunc_rsp_shv_simd();
	2482	}
2603	2483	#endif
2604	2484
2605	2485	#if (!USE_SIMD || SIMUL_SIMD)
2606	2486
2607		static void cfunc_rsp_shv_scalar(void *param)
	2487	inline void rsp_device::ccfunc_rsp_shv_scalar()
2608	2488	{
2609		rsp_state *rsp = (rsp_state*)param;
2610		UINT32 op = rsp->impstate->arg0;
	2489	UINT32 op = m_rsp_state->arg0;
2611	2490	int dest = (op >> 16) & 0x1f;
2612	2491	int base = (op >> 21) & 0x1f;
2613	2492	int index = (op >> 7) & 0xf;
r31833	r31834
2617	2496	offset |= 0xffffffc0;
2618	2497	}
2619	2498
2620		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	2499	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
2621	2500	for (int i=0; i < 8; i++)
2622	2501	{
2623	2502	int element = index + (i << 1);
2624	2503	UINT8 d = (VREG_B(dest, (element & 0xf)) << 1) |
2625	2504	(VREG_B(dest, ((element + 1) & 0xf)) >> 7);
2626		WRITE8(rsp, ea, d);
	2505	DM_WRITE8(ea, d);
2627	2506	ea += 2;
2628	2507	}
2629	2508	}
	2509
	2510	static void cfunc_rsp_shv_scalar(void *param)
	2511	{
	2512	((rsp_device *)param)->ccfunc_rsp_shv_scalar();
	2513	}
2630	2514	#endif
2631	2515
2632	2516	#if USE_SIMD
r31833	r31834
2639	2523	//
2640	2524	// Stores bits 14-7 of upper or lower quad, with 4-byte stride
2641	2525
2642		static void cfunc_rsp_sfv_simd(void *param)
	2526	inline void rsp_device::ccfunc_rsp_sfv_simd()
2643	2527	{
2644		rsp_state *rsp = (rsp_state*)param;
2645		UINT32 op = rsp->impstate->arg0;
	2528	UINT32 op = m_rsp_state->arg0;
2646	2529	int dest = (op >> 16) & 0x1f;
2647	2530	int base = (op >> 21) & 0x1f;
2648	2531	int index = (op >> 7) & 0xf;
r31833	r31834
2652	2535	offset |= 0xffffffc0;
2653	2536	}
2654	2537
2655		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	2538	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
2656	2539	int eaoffset = ea & 0xf;
2657	2540	ea &= ~0xf;
2658	2541
r31833	r31834
2661	2544	for (int i = index>>1; i < end; i++)
2662	2545	{
2663	2546	UINT16 value;
2664		SIMD_EXTRACT16(rsp->xv[dest], value, i);
2665		WRITE8(rsp, ea + (eaoffset & 0xf), (value >> 7) & 0x00ff);
	2547	SIMD_EXTRACT16(m_xv[dest], value, i);
	2548	DM_WRITE8(ea + (eaoffset & 0xf), (value >> 7) & 0x00ff);
2666	2549	eaoffset += 4;
2667	2550	}
2668	2551	}
2669	2552
	2553	static void cfunc_rsp_sfv_simd(void *param)
	2554	{
	2555	((rsp_device *)param)->ccfunc_rsp_sfv_simd();
	2556	}
2670	2557	#endif
2671	2558
2672	2559	#if (!USE_SIMD || SIMUL_SIMD)
2673	2560
2674		static void cfunc_rsp_sfv_scalar(void *param)
	2561	inline void rsp_device::ccfunc_rsp_sfv_scalar()
2675	2562	{
2676		rsp_state *rsp = (rsp_state*)param;
2677		UINT32 op = rsp->impstate->arg0;
	2563	UINT32 op = m_rsp_state->arg0;
2678	2564	int dest = (op >> 16) & 0x1f;
2679	2565	int base = (op >> 21) & 0x1f;
2680	2566	int index = (op >> 7) & 0xf;
r31833	r31834
2684	2570	offset |= 0xffffffc0;
2685	2571	}
2686	2572
2687		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	2573	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
2688	2574	int eaoffset = ea & 0xf;
2689	2575	ea &= ~0xf;
2690	2576
r31833	r31834
2692	2578
2693	2579	for (int i = index>>1; i < end; i++)
2694	2580	{
2695		WRITE8(rsp, ea + (eaoffset & 0xf), VREG_S(dest, i) >> 7);
	2581	DM_WRITE8(ea + (eaoffset & 0xf), VREG_S(dest, i) >> 7);
2696	2582	eaoffset += 4;
2697	2583	}
2698	2584	}
	2585
	2586	static void cfunc_rsp_sfv_scalar(void *param)
	2587	{
	2588	((rsp_device *)param)->ccfunc_rsp_sfv_scalar();
	2589	}
2699	2590	#endif
2700	2591
2701	2592	#if USE_SIMD
r31833	r31834
2709	2600	// Stores the full 128-bit vector starting from vector byte index and wrapping to index 0
2710	2601	// after byte index 15
2711	2602
2712		static void cfunc_rsp_swv_simd(void *param)
	2603	inline void rsp_device::ccfunc_rsp_swv_simd()
2713	2604	{
2714		rsp_state *rsp = (rsp_state*)param;
2715		UINT32 op = rsp->impstate->arg0;
	2605	UINT32 op = m_rsp_state->arg0;
2716	2606	int dest = (op >> 16) & 0x1f;
2717	2607	int base = (op >> 21) & 0x1f;
2718	2608	int index = (op >> 7) & 0xf;
r31833	r31834
2722	2612	offset |= 0xffffffc0;
2723	2613	}
2724	2614
2725		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	2615	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
2726	2616	int eaoffset = ea & 0xf;
2727	2617	ea &= ~0xf;
2728	2618
r31833	r31834
2730	2620	for (int i = index; i < end; i++)
2731	2621	{
2732	2622	UINT16 value;
2733		SIMD_EXTRACT16(rsp->xv[dest], value, i >> 1);
2734		WRITE8(rsp, ea + (eaoffset & 0xf), (value >> ((1-(i & 1)) * 8)) & 0xff);
	2623	SIMD_EXTRACT16(m_xv[dest], value, i >> 1);
	2624	DM_WRITE8(ea + (eaoffset & 0xf), (value >> ((1-(i & 1)) * 8)) & 0xff);
2735	2625	eaoffset++;
2736	2626	}
2737	2627	}
2738	2628
	2629	static void cfunc_rsp_swv_simd(void *param)
	2630	{
	2631	((rsp_device *)param)->ccfunc_rsp_swv_simd();
	2632	}
2739	2633	#endif
2740	2634
2741	2635	#if (!USE_SIMD || SIMUL_SIMD)
2742	2636
2743		static void cfunc_rsp_swv_scalar(void *param)
	2637	inline void rsp_device::ccfunc_rsp_swv_scalar()
2744	2638	{
2745		rsp_state *rsp = (rsp_state*)param;
2746		UINT32 op = rsp->impstate->arg0;
	2639	UINT32 op = m_rsp_state->arg0;
2747	2640	int dest = (op >> 16) & 0x1f;
2748	2641	int base = (op >> 21) & 0x1f;
2749	2642	int index = (op >> 7) & 0xf;
r31833	r31834
2753	2646	offset |= 0xffffffc0;
2754	2647	}
2755	2648
2756		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	2649	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
2757	2650	int eaoffset = ea & 0xf;
2758	2651	ea &= ~0xf;
2759	2652
2760	2653	int end = index + 16;
2761	2654	for (int i = index; i < end; i++)
2762	2655	{
2763		WRITE8(rsp, ea + (eaoffset & 0xf), VREG_B(dest, i & 0xf));
	2656	DM_WRITE8(ea + (eaoffset & 0xf), VREG_B(dest, i & 0xf));
2764	2657	eaoffset++;
2765	2658	}
2766	2659	}
	2660
	2661	static void cfunc_rsp_swv_scalar(void *param)
	2662	{
	2663	((rsp_device *)param)->ccfunc_rsp_swv_scalar();
	2664	}
2767	2665	#endif
2768	2666
2769	2667	#if USE_SIMD
r31833	r31834
2776	2674	//
2777	2675	// Stores one element from maximum of 8 vectors, while incrementing element index
2778	2676
2779		static void cfunc_rsp_stv_simd(void *param)
	2677	inline void rsp_device::ccfunc_rsp_stv_simd()
2780	2678	{
2781		rsp_state *rsp = (rsp_state*)param;
2782		UINT32 op = rsp->impstate->arg0;
	2679	UINT32 op = m_rsp_state->arg0;
2783	2680	int dest = (op >> 16) & 0x1f;
2784	2681	int base = (op >> 21) & 0x1f;
2785	2682	int index = (op >> 7) & 0xf;
r31833	r31834
2799	2696
2800	2697	int element = 8 - (index >> 1);
2801	2698
2802		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	2699	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
2803	2700	int eaoffset = (ea & 0xf) + (element * 2);
2804	2701	ea &= ~0xf;
2805	2702
2806	2703	for (int i = vs; i < ve; i++)
2807	2704	{
2808	2705	UINT16 value;
2809		SIMD_EXTRACT16(rsp->xv[i], value, element);
2810		WRITE16(rsp, ea + (eaoffset & 0xf), value);
	2706	SIMD_EXTRACT16(m_xv[i], value, element);
	2707	DM_WRITE16(ea + (eaoffset & 0xf), value);
2811	2708	eaoffset += 2;
2812	2709	element++;
2813	2710	}
2814	2711	}
2815	2712
	2713	static void cfunc_rsp_stv_simd(void *param)
	2714	{
	2715	((rsp_device *)param)->ccfunc_rsp_stv_simd();
	2716	}
2816	2717	#endif
2817	2718
2818	2719	#if (!USE_SIMD || SIMUL_SIMD)
2819	2720
2820		static void cfunc_rsp_stv_scalar(void *param)
	2721	inline void rsp_device::ccfunc_rsp_stv_scalar()
2821	2722	{
2822		rsp_state *rsp = (rsp_state*)param;
2823		UINT32 op = rsp->impstate->arg0;
	2723	UINT32 op = m_rsp_state->arg0;
2824	2724	int dest = (op >> 16) & 0x1f;
2825	2725	int base = (op >> 21) & 0x1f;
2826	2726	int index = (op >> 7) & 0xf;
r31833	r31834
2840	2740
2841	2741	int element = 8 - (index >> 1);
2842	2742
2843		UINT32 ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	2743	UINT32 ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
2844	2744	int eaoffset = (ea & 0xf) + (element * 2);
2845	2745	ea &= ~0xf;
2846	2746
2847	2747	for (int i = vs; i < ve; i++)
2848	2748	{
2849		WRITE16(rsp, ea + (eaoffset & 0xf), VREG_S(i, element & 0x7));
	2749	DM_WRITE16(ea + (eaoffset & 0xf), VREG_S(i, element & 0x7));
2850	2750	eaoffset += 2;
2851	2751	element++;
2852	2752	}
2853	2753	}
2854	2754
	2755	static void cfunc_rsp_stv_scalar(void *param)
	2756	{
	2757	((rsp_device *)param)->ccfunc_rsp_stv_scalar();
	2758	}
2855	2759	#endif
2856	2760
2857	2761	#if USE_SIMD
2858		static int generate_swc2(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
	2762	int rsp_device::generate_swc2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
2859	2763	{
2860	2764	//  int loopdest;
2861	2765	UINT32 op = desc->opptr.l[0];
r31833	r31834
2872	2776	switch ((op >> 11) & 0x1f)
2873	2777	{
2874	2778	case 0x00:      /* SBV */
2875		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
2876		UML_CALLC(block, cfunc_rsp_sbv_simd, rsp);
	2779	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2780	UML_CALLC(block, cfunc_rsp_sbv_simd, this);
2877	2781	#if SIMUL_SIMD
2878		UML_CALLC(block, cfunc_backup_regs, rsp);
2879		UML_CALLC(block, cfunc_rsp_sbv_scalar, rsp);
2880		UML_CALLC(block, cfunc_restore_regs, rsp);
2881		UML_CALLC(block, cfunc_verify_regs, rsp);
	2782	UML_CALLC(block, cfunc_backup_regs, this);
	2783	UML_CALLC(block, cfunc_rsp_sbv_scalar, this);
	2784	UML_CALLC(block, cfunc_restore_regs, this);
	2785	UML_CALLC(block, cfunc_verify_regs, this);
2882	2786	#endif
2883	2787	return TRUE;
2884	2788	case 0x01:      /* SSV */
2885		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
2886		UML_CALLC(block, cfunc_rsp_ssv_simd, rsp);
	2789	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2790	UML_CALLC(block, cfunc_rsp_ssv_simd, this);
2887	2791	#if SIMUL_SIMD
2888		UML_CALLC(block, cfunc_backup_regs, rsp);
2889		UML_CALLC(block, cfunc_rsp_ssv_scalar, rsp);
2890		UML_CALLC(block, cfunc_restore_regs, rsp);
2891		UML_CALLC(block, cfunc_verify_regs, rsp);
	2792	UML_CALLC(block, cfunc_backup_regs, this);
	2793	UML_CALLC(block, cfunc_rsp_ssv_scalar, this);
	2794	UML_CALLC(block, cfunc_restore_regs, this);
	2795	UML_CALLC(block, cfunc_verify_regs, this);
2892	2796	#endif
2893	2797	return TRUE;
2894	2798	case 0x02:      /* SLV */
2895		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
2896		UML_CALLC(block, cfunc_rsp_slv_simd, rsp);
	2799	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2800	UML_CALLC(block, cfunc_rsp_slv_simd, this);
2897	2801	#if SIMUL_SIMD
2898		UML_CALLC(block, cfunc_backup_regs, rsp);
2899		UML_CALLC(block, cfunc_rsp_slv_scalar, rsp);
2900		UML_CALLC(block, cfunc_restore_regs, rsp);
2901		UML_CALLC(block, cfunc_verify_regs, rsp);
	2802	UML_CALLC(block, cfunc_backup_regs, this);
	2803	UML_CALLC(block, cfunc_rsp_slv_scalar, this);
	2804	UML_CALLC(block, cfunc_restore_regs, this);
	2805	UML_CALLC(block, cfunc_verify_regs, this);
2902	2806	#endif
2903	2807	return TRUE;
2904	2808	case 0x03:      /* SDV */
2905		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
2906		UML_CALLC(block, cfunc_rsp_sdv_simd, rsp);
	2809	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2810	UML_CALLC(block, cfunc_rsp_sdv_simd, this);
2907	2811	#if SIMUL_SIMD
2908		UML_CALLC(block, cfunc_backup_regs, rsp);
2909		UML_CALLC(block, cfunc_rsp_sdv_scalar, rsp);
2910		UML_CALLC(block, cfunc_restore_regs, rsp);
2911		UML_CALLC(block, cfunc_verify_regs, rsp);
	2812	UML_CALLC(block, cfunc_backup_regs, this);
	2813	UML_CALLC(block, cfunc_rsp_sdv_scalar, this);
	2814	UML_CALLC(block, cfunc_restore_regs, this);
	2815	UML_CALLC(block, cfunc_verify_regs, this);
2912	2816	#endif
2913	2817	return TRUE;
2914	2818	case 0x04:      /* SQV */
2915		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
2916		UML_CALLC(block, cfunc_rsp_sqv_simd, rsp);
	2819	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2820	UML_CALLC(block, cfunc_rsp_sqv_simd, this);
2917	2821	#if SIMUL_SIMD
2918		UML_CALLC(block, cfunc_backup_regs, rsp);
2919		UML_CALLC(block, cfunc_rsp_sqv_scalar, rsp);
2920		UML_CALLC(block, cfunc_restore_regs, rsp);
2921		UML_CALLC(block, cfunc_verify_regs, rsp);
	2822	UML_CALLC(block, cfunc_backup_regs, this);
	2823	UML_CALLC(block, cfunc_rsp_sqv_scalar, this);
	2824	UML_CALLC(block, cfunc_restore_regs, this);
	2825	UML_CALLC(block, cfunc_verify_regs, this);
2922	2826	#endif
2923	2827	return TRUE;
2924	2828	case 0x05:      /* SRV */
2925		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
2926		UML_CALLC(block, cfunc_rsp_srv_simd, rsp);
	2829	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2830	UML_CALLC(block, cfunc_rsp_srv_simd, this);
2927	2831	#if SIMUL_SIMD
2928		UML_CALLC(block, cfunc_backup_regs, rsp);
2929		UML_CALLC(block, cfunc_rsp_srv_scalar, rsp);
2930		UML_CALLC(block, cfunc_restore_regs, rsp);
2931		UML_CALLC(block, cfunc_verify_regs, rsp);
	2832	UML_CALLC(block, cfunc_backup_regs, this);
	2833	UML_CALLC(block, cfunc_rsp_srv_scalar, this);
	2834	UML_CALLC(block, cfunc_restore_regs, this);
	2835	UML_CALLC(block, cfunc_verify_regs, this);
2932	2836	#endif
2933	2837	return TRUE;
2934	2838	case 0x06:      /* SPV */
2935		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
2936		UML_CALLC(block, cfunc_rsp_spv_simd, rsp);
	2839	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2840	UML_CALLC(block, cfunc_rsp_spv_simd, this);
2937	2841	#if SIMUL_SIMD
2938		UML_CALLC(block, cfunc_backup_regs, rsp);
2939		UML_CALLC(block, cfunc_rsp_spv_scalar, rsp);
2940		UML_CALLC(block, cfunc_restore_regs, rsp);
2941		UML_CALLC(block, cfunc_verify_regs, rsp);
	2842	UML_CALLC(block, cfunc_backup_regs, this);
	2843	UML_CALLC(block, cfunc_rsp_spv_scalar, this);
	2844	UML_CALLC(block, cfunc_restore_regs, this);
	2845	UML_CALLC(block, cfunc_verify_regs, this);
2942	2846	#endif
2943	2847	return TRUE;
2944	2848	case 0x07:      /* SUV */
2945		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
2946		UML_CALLC(block, cfunc_rsp_suv_simd, rsp);
	2849	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2850	UML_CALLC(block, cfunc_rsp_suv_simd, this);
2947	2851	#if SIMUL_SIMD
2948		UML_CALLC(block, cfunc_backup_regs, rsp);
2949		UML_CALLC(block, cfunc_rsp_suv_scalar, rsp);
2950		UML_CALLC(block, cfunc_restore_regs, rsp);
2951		UML_CALLC(block, cfunc_verify_regs, rsp);
	2852	UML_CALLC(block, cfunc_backup_regs, this);
	2853	UML_CALLC(block, cfunc_rsp_suv_scalar, this);
	2854	UML_CALLC(block, cfunc_restore_regs, this);
	2855	UML_CALLC(block, cfunc_verify_regs, this);
2952	2856	#endif
2953	2857	return TRUE;
2954	2858	case 0x08:      /* SHV */
2955		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
2956		UML_CALLC(block, cfunc_rsp_shv_simd, rsp);
	2859	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2860	UML_CALLC(block, cfunc_rsp_shv_simd, this);
2957	2861	#if SIMUL_SIMD
2958		UML_CALLC(block, cfunc_backup_regs, rsp);
2959		UML_CALLC(block, cfunc_rsp_shv_scalar, rsp);
2960		UML_CALLC(block, cfunc_restore_regs, rsp);
2961		UML_CALLC(block, cfunc_verify_regs, rsp);
	2862	UML_CALLC(block, cfunc_backup_regs, this);
	2863	UML_CALLC(block, cfunc_rsp_shv_scalar, this);
	2864	UML_CALLC(block, cfunc_restore_regs, this);
	2865	UML_CALLC(block, cfunc_verify_regs, this);
2962	2866	#endif
2963	2867	return TRUE;
2964	2868	case 0x09:      /* SFV */
2965		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
2966		UML_CALLC(block, cfunc_rsp_sfv_simd, rsp);
	2869	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2870	UML_CALLC(block, cfunc_rsp_sfv_simd, this);
2967	2871	#if SIMUL_SIMD
2968		UML_CALLC(block, cfunc_backup_regs, rsp);
2969		UML_CALLC(block, cfunc_rsp_sfv_scalar, rsp);
2970		UML_CALLC(block, cfunc_restore_regs, rsp);
2971		UML_CALLC(block, cfunc_verify_regs, rsp);
	2872	UML_CALLC(block, cfunc_backup_regs, this);
	2873	UML_CALLC(block, cfunc_rsp_sfv_scalar, this);
	2874	UML_CALLC(block, cfunc_restore_regs, this);
	2875	UML_CALLC(block, cfunc_verify_regs, this);
2972	2876	#endif
2973	2877	return TRUE;
2974	2878	case 0x0a:      /* SWV */
2975		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
2976		UML_CALLC(block, cfunc_rsp_swv_simd, rsp);
	2879	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2880	UML_CALLC(block, cfunc_rsp_swv_simd, this);
2977	2881	#if SIMUL_SIMD
2978		UML_CALLC(block, cfunc_backup_regs, rsp);
2979		UML_CALLC(block, cfunc_rsp_swv_scalar, rsp);
2980		UML_CALLC(block, cfunc_restore_regs, rsp);
2981		UML_CALLC(block, cfunc_verify_regs, rsp);
	2882	UML_CALLC(block, cfunc_backup_regs, this);
	2883	UML_CALLC(block, cfunc_rsp_swv_scalar, this);
	2884	UML_CALLC(block, cfunc_restore_regs, this);
	2885	UML_CALLC(block, cfunc_verify_regs, this);
2982	2886	#endif
2983	2887	return TRUE;
2984	2888	case 0x0b:      /* STV */
2985		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
2986		UML_CALLC(block, cfunc_rsp_stv_simd, rsp);
	2889	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2890	UML_CALLC(block, cfunc_rsp_stv_simd, this);
2987	2891	#if SIMUL_SIMD
2988		UML_CALLC(block, cfunc_backup_regs, rsp);
2989		UML_CALLC(block, cfunc_rsp_stv_scalar, rsp);
2990		UML_CALLC(block, cfunc_restore_regs, rsp);
2991		UML_CALLC(block, cfunc_verify_regs, rsp);
	2892	UML_CALLC(block, cfunc_backup_regs, this);
	2893	UML_CALLC(block, cfunc_rsp_stv_scalar, this);
	2894	UML_CALLC(block, cfunc_restore_regs, this);
	2895	UML_CALLC(block, cfunc_verify_regs, this);
2992	2896	#endif
2993	2897	return TRUE;
2994	2898
2995	2899	default:
2996		unimplemented_opcode(rsp, op);
	2900	unimplemented_opcode(op);
2997	2901	return FALSE;
2998	2902	}
2999	2903
r31833	r31834
3002	2906
3003	2907	#else
3004	2908
3005		static int generate_swc2(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
	2909	int rsp_device::generate_swc2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
3006	2910	{
3007	2911	//  int loopdest;
3008	2912	UINT32 op = desc->opptr.l[0];
r31833	r31834
3019	2923	switch ((op >> 11) & 0x1f)
3020	2924	{
3021	2925	case 0x00:      /* SBV */
3022		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
3023		UML_CALLC(block, cfunc_rsp_sbv_scalar, rsp);
	2926	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2927	UML_CALLC(block, cfunc_rsp_sbv_scalar, this);
3024	2928	return TRUE;
3025	2929	case 0x01:      /* SSV */
3026		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
3027		UML_CALLC(block, cfunc_rsp_ssv_scalar, rsp);
	2930	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2931	UML_CALLC(block, cfunc_rsp_ssv_scalar, this);
3028	2932	return TRUE;
3029	2933	case 0x02:      /* SLV */
3030		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
3031		UML_CALLC(block, cfunc_rsp_slv_scalar, rsp);
	2934	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2935	UML_CALLC(block, cfunc_rsp_slv_scalar, this);
3032	2936	return TRUE;
3033	2937	case 0x03:      /* SDV */
3034		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
3035		UML_CALLC(block, cfunc_rsp_sdv_scalar, rsp);
	2938	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2939	UML_CALLC(block, cfunc_rsp_sdv_scalar, this);
3036	2940	return TRUE;
3037	2941	case 0x04:      /* SQV */
3038		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
3039		UML_CALLC(block, cfunc_rsp_sqv_scalar, rsp);
	2942	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2943	UML_CALLC(block, cfunc_rsp_sqv_scalar, this);
3040	2944	return TRUE;
3041	2945	case 0x05:      /* SRV */
3042		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
3043		UML_CALLC(block, cfunc_rsp_srv_scalar, rsp);
	2946	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2947	UML_CALLC(block, cfunc_rsp_srv_scalar, this);
3044	2948	return TRUE;
3045	2949	case 0x06:      /* SPV */
3046		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
3047		UML_CALLC(block, cfunc_rsp_spv_scalar, rsp);
	2950	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2951	UML_CALLC(block, cfunc_rsp_spv_scalar, this);
3048	2952	return TRUE;
3049	2953	case 0x07:      /* SUV */
3050		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
3051		UML_CALLC(block, cfunc_rsp_suv_scalar, rsp);
	2954	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2955	UML_CALLC(block, cfunc_rsp_suv_scalar, this);
3052	2956	return TRUE;
3053	2957	case 0x08:      /* SHV */
3054		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
3055		UML_CALLC(block, cfunc_rsp_shv_scalar, rsp);
	2958	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2959	UML_CALLC(block, cfunc_rsp_shv_scalar, this);
3056	2960	return TRUE;
3057	2961	case 0x09:      /* SFV */
3058		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
3059		UML_CALLC(block, cfunc_rsp_sfv_scalar, rsp);
	2962	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2963	UML_CALLC(block, cfunc_rsp_sfv_scalar, this);
3060	2964	return TRUE;
3061	2965	case 0x0a:      /* SWV */
3062		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
3063		UML_CALLC(block, cfunc_rsp_swv_scalar, rsp);
	2966	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2967	UML_CALLC(block, cfunc_rsp_swv_scalar, this);
3064	2968	return TRUE;
3065	2969	case 0x0b:      /* STV */
3066		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
3067		UML_CALLC(block, cfunc_rsp_stv_scalar, rsp);
	2970	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	2971	UML_CALLC(block, cfunc_rsp_stv_scalar, this);
3068	2972	return TRUE;
3069	2973
3070	2974	default:
3071		unimplemented_opcode(rsp, op);
	2975	unimplemented_opcode(op);
3072	2976	return FALSE;
3073	2977	}
3074	2978
r31833	r31834
3077	2981	#endif
3078	2982
3079	2983	#if USE_SIMD
3080		INLINE UINT16 VEC_SATURATE_ACCUM(rsp_state *rsp, int accum, int slice, UINT16 negative, UINT16 positive)
	2984	inline UINT16 rsp_device::VEC_SATURATE_ACCUM(int accum, int slice, UINT16 negative, UINT16 positive)
3081	2985	{
3082		if ((INT16)VEC_ACCUM_H(rsp, accum) < 0)
	2986	if ((INT16)VEC_ACCUM_H(accum) < 0)
3083	2987	{
3084		if ((UINT16)(VEC_ACCUM_H(rsp, accum)) != 0xffff)
	2988	if ((UINT16)(VEC_ACCUM_H(accum)) != 0xffff)
3085	2989	{
3086	2990	return negative;
3087	2991	}
3088	2992	else
3089	2993	{
3090		if ((INT16)VEC_ACCUM_M(rsp, accum) >= 0)
	2994	if ((INT16)VEC_ACCUM_M(accum) >= 0)
3091	2995	{
3092	2996	return negative;
3093	2997	}
r31833	r31834
3095	2999	{
3096	3000	if (slice == 0)
3097	3001	{
3098		return VEC_ACCUM_L(rsp, accum);
	3002	return VEC_ACCUM_L(accum);
3099	3003	}
3100	3004	else if (slice == 1)
3101	3005	{
3102		return VEC_ACCUM_M(rsp, accum);
	3006	return VEC_ACCUM_M(accum);
3103	3007	}
3104	3008	}
3105	3009	}
3106	3010	}
3107	3011	else
3108	3012	{
3109		if ((UINT16)(VEC_ACCUM_H(rsp, accum)) != 0)
	3013	if ((UINT16)(VEC_ACCUM_H(accum)) != 0)
3110	3014	{
3111	3015	return positive;
3112	3016	}
3113	3017	else
3114	3018	{
3115		if ((INT16)VEC_ACCUM_M(rsp, accum) < 0)
	3019	if ((INT16)VEC_ACCUM_M(accum) < 0)
3116	3020	{
3117	3021	return positive;
3118	3022	}
r31833	r31834
3120	3024	{
3121	3025	if (slice == 0)
3122	3026	{
3123		return VEC_ACCUM_L(rsp, accum);
	3027	return VEC_ACCUM_L(accum);
3124	3028	}
3125	3029	else
3126	3030	{
3127		return VEC_ACCUM_M(rsp, accum);
	3031	return VEC_ACCUM_M(accum);
3128	3032	}
3129	3033	}
3130	3034	}
r31833	r31834
3134	3038	#endif
3135	3039
3136	3040	#if (!USE_SIMD || SIMUL_SIMD)
3137		INLINE UINT16 SATURATE_ACCUM(rsp_state *rsp, int accum, int slice, UINT16 negative, UINT16 positive)
	3041	inline UINT16 rsp_device::SATURATE_ACCUM(int accum, int slice, UINT16 negative, UINT16 positive)
3138	3042	{
3139		if ((INT16)ACCUM_H(rsp, accum) < 0)
	3043	if ((INT16)ACCUM_H(accum) < 0)
3140	3044	{
3141		if ((UINT16)(ACCUM_H(rsp, accum)) != 0xffff)
	3045	if ((UINT16)(ACCUM_H(accum)) != 0xffff)
3142	3046	{
3143	3047	return negative;
3144	3048	}
3145	3049	else
3146	3050	{
3147		if ((INT16)ACCUM_M(rsp, accum) >= 0)
	3051	if ((INT16)ACCUM_M(accum) >= 0)
3148	3052	{
3149	3053	return negative;
3150	3054	}
r31833	r31834
3152	3056	{
3153	3057	if (slice == 0)
3154	3058	{
3155		return ACCUM_L(rsp, accum);
	3059	return ACCUM_L(accum);
3156	3060	}
3157	3061	else if (slice == 1)
3158	3062	{
3159		return ACCUM_M(rsp, accum);
	3063	return ACCUM_M(accum);
3160	3064	}
3161	3065	}
3162	3066	}
3163	3067	}
3164	3068	else
3165	3069	{
3166		if ((UINT16)(ACCUM_H(rsp, accum)) != 0)
	3070	if ((UINT16)(ACCUM_H(accum)) != 0)
3167	3071	{
3168	3072	return positive;
3169	3073	}
3170	3074	else
3171	3075	{
3172		if ((INT16)ACCUM_M(rsp, accum) < 0)
	3076	if ((INT16)ACCUM_M(accum) < 0)
3173	3077	{
3174	3078	return positive;
3175	3079	}
r31833	r31834
3177	3081	{
3178	3082	if (slice == 0)
3179	3083	{
3180		return ACCUM_L(rsp, accum);
	3084	return ACCUM_L(accum);
3181	3085	}
3182	3086	else
3183	3087	{
3184		return ACCUM_M(rsp, accum);
	3088	return ACCUM_M(accum);
3185	3089	}
3186	3090	}
3187	3091	}
r31833	r31834
3190	3094	}
3191	3095	#endif
3192	3096
3193		INLINE UINT16 SATURATE_ACCUM1(rsp_state *rsp, int accum, UINT16 negative, UINT16 positive)
	3097	inline UINT16 rsp_device::SATURATE_ACCUM1(int accum, UINT16 negative, UINT16 positive)
3194	3098	{
3195	3099	// Return negative if H<0 && (H!=0xffff || M >= 0)
3196	3100	// Return positive if H>0 || (H==0 && M<0)
3197	3101	// Return medium slice if H==0xffff && M<0
3198	3102	// Return medium slice if H==0 && M>=0
3199		if ((INT16)ACCUM_H(rsp, accum) < 0)
	3103	if ((INT16)ACCUM_H(accum) < 0)
3200	3104	{
3201		if ((UINT16)(ACCUM_H(rsp, accum)) != 0xffff)
	3105	if ((UINT16)(ACCUM_H(accum)) != 0xffff)
3202	3106	{
3203	3107	return negative;
3204	3108	}
3205	3109	else
3206	3110	{
3207		if ((INT16)ACCUM_M(rsp, accum) >= 0)
	3111	if ((INT16)ACCUM_M(accum) >= 0)
3208	3112	{
3209	3113	return negative;
3210	3114	}
3211	3115	else
3212	3116	{
3213		return ACCUM_M(rsp, accum);
	3117	return ACCUM_M(accum);
3214	3118	}
3215	3119	}
3216	3120	}
3217	3121	else
3218	3122	{
3219		if ((UINT16)(ACCUM_H(rsp, accum)) != 0)
	3123	if ((UINT16)(ACCUM_H(accum)) != 0)
3220	3124	{
3221	3125	return positive;
3222	3126	}
3223	3127	else
3224	3128	{
3225		if ((INT16)ACCUM_M(rsp, accum) < 0)
	3129	if ((INT16)ACCUM_M(accum) < 0)
3226	3130	{
3227	3131	return positive;
3228	3132	}
3229	3133	else
3230	3134	{
3231		return ACCUM_M(rsp, accum);
	3135	return ACCUM_M(accum);
3232	3136	}
3233	3137	}
3234	3138	}
r31833	r31834
3237	3141
3238	3142	#if USE_SIMD
3239	3143	#define VEC_WRITEBACK_RESULT() { \
3240		SIMD_INSERT16(rsp->xv[VDREG], vres[0], 0); \
3241		SIMD_INSERT16(rsp->xv[VDREG], vres[1], 1); \
3242		SIMD_INSERT16(rsp->xv[VDREG], vres[2], 2); \
3243		SIMD_INSERT16(rsp->xv[VDREG], vres[3], 3); \
3244		SIMD_INSERT16(rsp->xv[VDREG], vres[4], 4); \
3245		SIMD_INSERT16(rsp->xv[VDREG], vres[5], 5); \
3246		SIMD_INSERT16(rsp->xv[VDREG], vres[6], 6); \
3247		SIMD_INSERT16(rsp->xv[VDREG], vres[7], 7); \
	3144	SIMD_INSERT16(m_xv[VDREG], vres[0], 0); \
	3145	SIMD_INSERT16(m_xv[VDREG], vres[1], 1); \
	3146	SIMD_INSERT16(m_xv[VDREG], vres[2], 2); \
	3147	SIMD_INSERT16(m_xv[VDREG], vres[3], 3); \
	3148	SIMD_INSERT16(m_xv[VDREG], vres[4], 4); \
	3149	SIMD_INSERT16(m_xv[VDREG], vres[5], 5); \
	3150	SIMD_INSERT16(m_xv[VDREG], vres[6], 6); \
	3151	SIMD_INSERT16(m_xv[VDREG], vres[7], 7); \
3248	3152	}
3249	3153	#endif
3250	3154
r31833	r31834
3358	3262	//
3359	3263	// Multiplies signed integer by signed integer * 2
3360	3264
3361		INLINE void cfunc_rsp_vmulf_simd(void *param)
	3265	inline void rsp_device::ccfunc_rsp_vmulf_simd()
3362	3266	{
3363		rsp_state *rsp = (rsp_state*)param;
3364		int op = rsp->impstate->arg0;
	3267	int op = m_rsp_state->arg0;
3365	3268
3366	3269	INT16 vres[8];
3367	3270	for (int i = 0; i < 8; i++)
r31833	r31834
3387	3290	VEC_SET_ACCUM_H((r < 0) ? 0xffff : 0, i);
3388	3291	VEC_SET_ACCUM_M((INT16)(r >> 16), i);
3389	3292	VEC_SET_ACCUM_L((UINT16)(r), i);
3390		vres[i] = VEC_ACCUM_M(rsp, i);
	3293	vres[i] = VEC_ACCUM_M(i);
3391	3294	}
3392	3295	}
3393	3296	VEC_WRITEBACK_RESULT();
3394	3297	}
3395	3298
	3299	static void cfunc_rsp_vmulf_simd(void *param)
	3300	{
	3301	((rsp_device *)param)->ccfunc_rsp_vmulf_simd();
	3302	}
3396	3303	#endif
3397	3304
3398	3305	#if (!USE_SIMD || SIMUL_SIMD)
3399	3306
3400		INLINE void cfunc_rsp_vmulf_scalar(void *param)
	3307	inline void rsp_device::ccfunc_rsp_vmulf_scalar()
3401	3308	{
3402		rsp_state *rsp = (rsp_state*)param;
3403		int op = rsp->impstate->arg0;
	3309	int op = m_rsp_state->arg0;
3404	3310
3405	3311	INT16 vres[8];
3406	3312	for (int i = 0; i < 8; i++)
r31833	r31834
3426	3332	SET_ACCUM_H((r < 0) ? 0xffff : 0, i);
3427	3333	SET_ACCUM_M((INT16)(r >> 16), i);
3428	3334	SET_ACCUM_L((UINT16)(r), i);
3429		vres[i] = ACCUM_M(rsp, i);
	3335	vres[i] = ACCUM_M(i);
3430	3336	}
3431	3337	}
3432	3338	WRITEBACK_RESULT();
3433	3339	}
	3340
	3341	static void cfunc_rsp_vmulf_scalar(void *param)
	3342	{
	3343	((rsp_device *)param)->ccfunc_rsp_vmulf_scalar();
	3344	}
3434	3345	#endif
3435	3346
3436	3347	#if USE_SIMD
r31833	r31834
3442	3353	// ------------------------------------------------------
3443	3354	//
3444	3355
3445		INLINE void cfunc_rsp_vmulu_simd(void *param)
	3356	inline void rsp_device::ccfunc_rsp_vmulu_simd()
3446	3357	{
3447		rsp_state *rsp = (rsp_state*)param;
3448		int op = rsp->impstate->arg0;
	3358	int op = m_rsp_state->arg0;
3449	3359
3450	3360	INT16 vres[8];
3451	3361	for (int i = 0; i < 8; i++)
r31833	r31834
3467	3377	{
3468	3378	vres[i] = 0;
3469	3379	}
3470		else if (((INT16)(VEC_ACCUM_H(rsp, i)) ^ (INT16)(VEC_ACCUM_M(rsp, i))) < 0)
	3380	else if (((INT16)(VEC_ACCUM_H(i)) ^ (INT16)(VEC_ACCUM_M(i))) < 0)
3471	3381	{
3472	3382	vres[i] = -1;
3473	3383	}
3474	3384	else
3475	3385	{
3476		vres[i] = VEC_ACCUM_M(rsp, i);
	3386	vres[i] = VEC_ACCUM_M(i);
3477	3387	}
3478	3388	}
3479	3389	VEC_WRITEBACK_RESULT();
3480	3390	}
3481	3391
	3392	static void cfunc_rsp_vmulu_simd(void *param)
	3393	{
	3394	((rsp_device *)param)->ccfunc_rsp_vmulu_simd();
	3395	}
3482	3396	#endif
3483	3397
3484	3398	#if (!USE_SIMD || SIMUL_SIMD)
3485	3399
3486		INLINE void cfunc_rsp_vmulu_scalar(void *param)
	3400	inline void rsp_device::ccfunc_rsp_vmulu_scalar()
3487	3401	{
3488		rsp_state *rsp = (rsp_state*)param;
3489		int op = rsp->impstate->arg0;
	3402	int op = m_rsp_state->arg0;
3490	3403
3491	3404	INT16 vres[8];
3492	3405	for (int i = 0; i < 8; i++)
r31833	r31834
3508	3421	{
3509	3422	vres[i] = 0;
3510	3423	}
3511		else if (((INT16)(ACCUM_H(rsp, i)) ^ (INT16)(ACCUM_M(rsp, i))) < 0)
	3424	else if (((INT16)(ACCUM_H(i)) ^ (INT16)(ACCUM_M(i))) < 0)
3512	3425	{
3513	3426	vres[i] = -1;
3514	3427	}
3515	3428	else
3516	3429	{
3517		vres[i] = ACCUM_M(rsp, i);
	3430	vres[i] = ACCUM_M(i);
3518	3431	}
3519	3432	}
3520	3433	WRITEBACK_RESULT();
3521	3434	}
	3435
	3436	static void cfunc_rsp_vmulu_scalar(void *param)
	3437	{
	3438	((rsp_device *)param)->ccfunc_rsp_vmulu_scalar();
	3439	}
3522	3440	#endif
3523	3441
3524	3442	#if USE_SIMD
r31833	r31834
3533	3451	// The result is added into accumulator
3534	3452	// The middle slice of accumulator is stored into destination element
3535	3453
3536		INLINE void cfunc_rsp_vmudl_simd(void *param)
	3454	inline void rsp_device::ccfunc_rsp_vmudl_simd()
3537	3455	{
3538		rsp_state *rsp = (rsp_state*)param;
3539		int op = rsp->impstate->arg0;
	3456	int op = m_rsp_state->arg0;
3540	3457
3541		__m128i vsReg = rsp->xv[VS1REG];
3542		__m128i vtReg = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
	3458	__m128i vsReg = m_xv[VS1REG];
	3459	__m128i vtReg = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
3543	3460
3544	3461	/* Unpack to obtain for 32-bit precision. */
3545	3462	__m128i unpackLo = _mm_mullo_epi16(vsReg, vtReg);
r31833	r31834
3547	3464	__m128i loProduct = _mm_unpacklo_epi16(unpackLo, unpackHi);
3548	3465	__m128i hiProduct = _mm_unpackhi_epi16(unpackLo, unpackHi);
3549	3466
3550		rsp->xv[VDREG] = rsp->accum_l = RSPPackHi32to16(loProduct, hiProduct);
	3467	m_xv[VDREG] = m_accum_l = RSPPackHi32to16(loProduct, hiProduct);
3551	3468
3552		rsp->accum_m = _mm_setzero_si128();
3553		rsp->accum_h = _mm_setzero_si128();
	3469	m_accum_m = _mm_setzero_si128();
	3470	m_accum_h = _mm_setzero_si128();
3554	3471	}
3555	3472
	3473	static void cfunc_rsp_vmudl_simd(void *param)
	3474	{
	3475	((rsp_device *)param)->ccfunc_rsp_vmudl_simd();
	3476	}
3556	3477	#endif
3557	3478
3558	3479	#if (!USE_SIMD || SIMUL_SIMD)
3559	3480
3560		INLINE void cfunc_rsp_vmudl_scalar(void *param)
	3481	inline void rsp_device::ccfunc_rsp_vmudl_scalar()
3561	3482	{
3562		rsp_state *rsp = (rsp_state*)param;
3563		int op = rsp->impstate->arg0;
	3483	int op = m_rsp_state->arg0;
3564	3484
3565	3485	INT16 vres[8];
3566	3486	for (int i = 0; i < 8; i++)
r31833	r31834
3577	3497	SET_ACCUM_M(0, i);
3578	3498	SET_ACCUM_L((UINT16)(r >> 16), i);
3579	3499
3580		vres[i] = ACCUM_L(rsp, i);
	3500	vres[i] = ACCUM_L(i);
3581	3501	}
3582	3502	WRITEBACK_RESULT();
3583	3503	}
	3504
	3505	static void cfunc_rsp_vmudl_scalar(void *param)
	3506	{
	3507	((rsp_device *)param)->ccfunc_rsp_vmudl_scalar();
	3508	}
3584	3509	#endif
3585	3510
3586	3511	#if USE_SIMD
r31833	r31834
3595	3520	// The result is stored into accumulator
3596	3521	// The middle slice of accumulator is stored into destination element
3597	3522
3598		INLINE void cfunc_rsp_vmudm_simd(void *param)
	3523	inline void rsp_device::ccfunc_rsp_vmudm_simd()
3599	3524	{
3600		rsp_state *rsp = (rsp_state*)param;
3601		int op = rsp->impstate->arg0;
	3525	int op = m_rsp_state->arg0;
3602	3526
3603	3527	__m128i vsRegLo, vsRegHi, vtRegLo, vtRegHi;
3604	3528
3605		__m128i vsReg = rsp->xv[VS1REG];
3606		__m128i vtReg = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
	3529	__m128i vsReg = m_xv[VS1REG];
	3530	__m128i vtReg = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
3607	3531
3608	3532	/* Unpack to obtain for 32-bit precision. */
3609	3533	RSPSignExtend16to32(vsReg, &vsRegLo, &vsRegHi);
r31833	r31834
3612	3536	/* Begin accumulating the products. */
3613	3537	__m128i loProduct = _mm_mullo_epi32(vsRegLo, vtRegLo);
3614	3538	__m128i hiProduct = _mm_mullo_epi32(vsRegHi, vtRegHi);
3615		rsp->accum_l = RSPPackLo32to16(loProduct, hiProduct);
3616		rsp->accum_m = rsp->xv[VDREG] = RSPPackHi32to16(loProduct, hiProduct);
	3539	m_accum_l = RSPPackLo32to16(loProduct, hiProduct);
	3540	m_accum_m = m_xv[VDREG] = RSPPackHi32to16(loProduct, hiProduct);
3617	3541
3618	3542	loProduct = _mm_cmplt_epi32(loProduct, _mm_setzero_si128());
3619	3543	hiProduct = _mm_cmplt_epi32(hiProduct, _mm_setzero_si128());
3620		rsp->accum_h = _mm_packs_epi32(loProduct, hiProduct);
	3544	m_accum_h = _mm_packs_epi32(loProduct, hiProduct);
3621	3545	}
3622	3546
	3547	static void cfunc_rsp_vmudm_simd(void *param)
	3548	{
	3549	((rsp_device *)param)->ccfunc_rsp_vmudm_simd();
	3550	}
3623	3551	#endif
3624	3552
3625	3553	#if (!USE_SIMD || SIMUL_SIMD)
3626	3554
3627		INLINE void cfunc_rsp_vmudm_scalar(void *param)
	3555	inline void rsp_device::ccfunc_rsp_vmudm_scalar()
3628	3556	{
3629		rsp_state *rsp = (rsp_state*)param;
3630		int op = rsp->impstate->arg0;
	3557	int op = m_rsp_state->arg0;
3631	3558
3632	3559	INT16 vres[8];
3633	3560	for (int i = 0; i < 8; i++)
r31833	r31834
3644	3571	SET_ACCUM_M((INT16)(r >> 16), i);
3645	3572	SET_ACCUM_L((UINT16)r, i);
3646	3573
3647		vres[i] = ACCUM_M(rsp, i);
	3574	vres[i] = ACCUM_M(i);
3648	3575	}
3649	3576	WRITEBACK_RESULT();
3650	3577	}
	3578
	3579	static void cfunc_rsp_vmudm_scalar(void *param)
	3580	{
	3581	((rsp_device *)param)->ccfunc_rsp_vmudm_scalar();
	3582	}
3651	3583	#endif
3652	3584
3653	3585	#if USE_SIMD
r31833	r31834
3662	3594	// The result is stored into accumulator
3663	3595	// The low slice of accumulator is stored into destination element
3664	3596
3665		INLINE void cfunc_rsp_vmudn_simd(void *param)
	3597	inline void rsp_device::ccfunc_rsp_vmudn_simd()
3666	3598	{
3667		rsp_state *rsp = (rsp_state*)param;
3668		int op = rsp->impstate->arg0;
	3599	int op = m_rsp_state->arg0;
3669	3600
3670	3601	__m128i vsRegLo, vsRegHi, vtRegLo, vtRegHi;
3671	3602
3672		__m128i vsReg = rsp->xv[VS1REG];
3673		__m128i vtReg = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
	3603	__m128i vsReg = m_xv[VS1REG];
	3604	__m128i vtReg = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
3674	3605
3675	3606	/* Unpack to obtain for 32-bit precision. */
3676	3607	RSPZeroExtend16to32(vsReg, &vsRegLo, &vsRegHi);
r31833	r31834
3679	3610	/* Begin accumulating the products. */
3680	3611	__m128i loProduct = _mm_mullo_epi32(vsRegLo, vtRegLo);
3681	3612	__m128i hiProduct = _mm_mullo_epi32(vsRegHi, vtRegHi);
3682		rsp->xv[VDREG] = rsp->accum_l = RSPPackLo32to16(loProduct, hiProduct);
3683		rsp->accum_m = RSPPackHi32to16(loProduct, hiProduct);
3684		rsp->accum_h = _mm_cmplt_epi16(rsp->accum_m, _mm_setzero_si128());
	3613	m_xv[VDREG] = m_accum_l = RSPPackLo32to16(loProduct, hiProduct);
	3614	m_accum_m = RSPPackHi32to16(loProduct, hiProduct);
	3615	m_accum_h = _mm_cmplt_epi16(m_accum_m, _mm_setzero_si128());
3685	3616	}
3686	3617
	3618	static void cfunc_rsp_vmudn_simd(void *param)
	3619	{
	3620	((rsp_device *)param)->ccfunc_rsp_vmudn_simd();
	3621	}
3687	3622	#endif
3688	3623
3689	3624	#if (!USE_SIMD || SIMUL_SIMD)
3690	3625
3691		INLINE void cfunc_rsp_vmudn_scalar(void *param)
	3626	inline void rsp_device::ccfunc_rsp_vmudn_scalar()
3692	3627	{
3693		rsp_state *rsp = (rsp_state*)param;
3694		int op = rsp->impstate->arg0;
	3628	int op = m_rsp_state->arg0;
3695	3629
3696	3630	INT16 vres[8] = { 0 };
3697	3631	for (int i = 0; i < 8; i++)
r31833	r31834
3712	3646	}
3713	3647	WRITEBACK_RESULT();
3714	3648	}
	3649
	3650	static void cfunc_rsp_vmudn_scalar(void *param)
	3651	{
	3652	((rsp_device *)param)->ccfunc_rsp_vmudn_scalar();
	3653	}
3715	3654	#endif
3716	3655
3717	3656	#if USE_SIMD
r31833	r31834
3726	3665	// The result is stored into highest 32 bits of accumulator, the low slice is zero
3727	3666	// The highest 32 bits of accumulator is saturated into destination element
3728	3667
3729		INLINE void cfunc_rsp_vmudh_simd(void *param)
	3668	inline void rsp_device::ccfunc_rsp_vmudh_simd()
3730	3669	{
3731		rsp_state *rsp = (rsp_state*)param;
3732		int op = rsp->impstate->arg0;
	3670	int op = m_rsp_state->arg0;
3733	3671
3734	3672	__m128i vaccLow, vaccHigh;
3735	3673	__m128i unpackLo, unpackHi;
3736	3674
3737		__m128i vsReg = rsp->xv[VS1REG];
3738		__m128i vtReg = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
	3675	__m128i vsReg = m_xv[VS1REG];
	3676	__m128i vtReg = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
3739	3677
3740	3678	/* Multiply the sources, accumulate the product. */
3741	3679	unpackLo = _mm_mullo_epi16(vsReg, vtReg);
r31833	r31834
3744	3682	vaccLow = _mm_unpacklo_epi16(unpackLo, unpackHi);
3745	3683
3746	3684	/* Pack the accumulator and result back up. */
3747		rsp->xv[VDREG] = _mm_packs_epi32(vaccLow, vaccHigh);
3748		rsp->accum_l = _mm_setzero_si128();
3749		rsp->accum_m = RSPPackLo32to16(vaccLow, vaccHigh);
3750		rsp->accum_h = RSPPackHi32to16(vaccLow, vaccHigh);
	3685	m_xv[VDREG] = _mm_packs_epi32(vaccLow, vaccHigh);
	3686	m_accum_l = _mm_setzero_si128();
	3687	m_accum_m = RSPPackLo32to16(vaccLow, vaccHigh);
	3688	m_accum_h = RSPPackHi32to16(vaccLow, vaccHigh);
3751	3689	}
3752	3690
	3691	static void cfunc_rsp_vmudh_simd(void *param)
	3692	{
	3693	((rsp_device *)param)->ccfunc_rsp_vmudh_simd();
	3694	}
3753	3695	#endif
3754	3696
3755	3697	#if (!USE_SIMD || SIMUL_SIMD)
3756	3698
3757		INLINE void cfunc_rsp_vmudh_scalar(void *param)
	3699	inline void rsp_device::ccfunc_rsp_vmudh_scalar()
3758	3700	{
3759		rsp_state *rsp = (rsp_state*)param;
3760		int op = rsp->impstate->arg0;
	3701	int op = m_rsp_state->arg0;
3761	3702
3762	3703	INT16 vres[8];
3763	3704	for (int i = 0; i < 8; i++)
r31833	r31834
3780	3721	}
3781	3722	WRITEBACK_RESULT();
3782	3723	}
	3724
	3725	static void cfunc_rsp_vmudh_scalar(void *param)
	3726	{
	3727	((rsp_device *)param)->ccfunc_rsp_vmudh_scalar();
	3728	}
3783	3729	#endif
3784	3730
3785	3731	#if USE_SIMD
r31833	r31834
3791	3737	// ------------------------------------------------------
3792	3738	//
3793	3739
3794		INLINE void cfunc_rsp_vmacf_simd(void *param)
	3740	inline void rsp_device::ccfunc_rsp_vmacf_simd()
3795	3741	{
3796		rsp_state *rsp = (rsp_state*)param;
3797		int op = rsp->impstate->arg0;
	3742	int op = m_rsp_state->arg0;
3798	3743
3799	3744	INT16 vres[8];
3800	3745	for (int i = 0; i < 8; i++)
r31833	r31834
3807	3752
3808	3753	INT32 r = s1 * s2;
3809	3754
3810		UINT64 q = (UINT64)(UINT16)VEC_ACCUM_LL(rsp, i);
3811		q |= (((UINT64)(UINT16)VEC_ACCUM_L(rsp, i)) << 16);
3812		q |= (((UINT64)(UINT16)VEC_ACCUM_M(rsp, i)) << 32);
3813		q |= (((UINT64)(UINT16)VEC_ACCUM_H(rsp, i)) << 48);
	3755	UINT64 q = (UINT64)(UINT16)VEC_ACCUM_LL(i);
	3756	q |= (((UINT64)(UINT16)VEC_ACCUM_L(i)) << 16);
	3757	q |= (((UINT64)(UINT16)VEC_ACCUM_M(i)) << 32);
	3758	q |= (((UINT64)(UINT16)VEC_ACCUM_H(i)) << 48);
3814	3759
3815	3760	q += (INT64)(r) << 17;
3816	3761	VEC_SET_ACCUM_LL((UINT16)q, i);
r31833	r31834
3818	3763	VEC_SET_ACCUM_M((UINT16)(q >> 32), i);
3819	3764	VEC_SET_ACCUM_H((UINT16)(q >> 48), i);
3820	3765
3821		vres[i] = VEC_SATURATE_ACCUM(rsp, i, 1, 0x8000, 0x7fff);
	3766	vres[i] = VEC_SATURATE_ACCUM(i, 1, 0x8000, 0x7fff);
3822	3767	}
3823	3768	VEC_WRITEBACK_RESULT();
3824	3769	/*
r31833	r31834
3826	3771	__m128i vaccHigh;
3827	3772	__m128i vdReg, vdRegLo, vdRegHi;
3828	3773
3829		__m128i vsReg = rsp->xv[VS1REG];
3830		__m128i vtReg = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
	3774	__m128i vsReg = m_xv[VS1REG];
	3775	__m128i vtReg = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
3831	3776
3832		__m128i vaccLow = rsp->accum_l;
	3777	__m128i vaccLow = m_accum_l;
3833	3778
3834	3779	// Unpack to obtain for 32-bit precision.
3835	3780	RSPZeroExtend16to32(vaccLow, &vaccLow, &vaccHigh);
r31833	r31834
3852	3797	vaccLow = _mm_add_epi32(vaccLow, vdRegLo);
3853	3798	vaccHigh = _mm_add_epi32(vaccHigh, vdRegHi);
3854	3799
3855		rsp->accum_l = vdReg = RSPPackLo32to16(vaccLow, vaccHigh);
	3800	m_accum_l = vdReg = RSPPackLo32to16(vaccLow, vaccHigh);
3856	3801
3857	3802	// Multiply the MSB of sources, accumulate the product.
3858		vdRegLo = _mm_unpacklo_epi16(rsp->accum_m, rsp->accum_h);
3859		vdRegHi = _mm_unpackhi_epi16(rsp->accum_m, rsp->accum_h);
	3803	vdRegLo = _mm_unpacklo_epi16(m_accum_m, m_accum_h);
	3804	vdRegHi = _mm_unpackhi_epi16(m_accum_m, m_accum_h);
3860	3805
3861	3806	loProduct = _mm_srai_epi32(loProduct, 16);
3862	3807	hiProduct = _mm_srai_epi32(hiProduct, 16);
r31833	r31834
3869	3814	vaccHigh = _mm_add_epi32(vdRegHi, vaccHigh);
3870	3815
3871	3816	// Clamp the accumulator and write it all out.
3872		rsp->xv[VDREG] = _mm_packs_epi32(vaccLow, vaccHigh);
3873		rsp->accum_m = RSPPackLo32to16(vaccLow, vaccHigh);
3874		rsp->accum_h = RSPPackHi32to16(vaccLow, vaccHigh);
	3817	m_xv[VDREG] = _mm_packs_epi32(vaccLow, vaccHigh);
	3818	m_accum_m = RSPPackLo32to16(vaccLow, vaccHigh);
	3819	m_accum_h = RSPPackHi32to16(vaccLow, vaccHigh);
3875	3820	*/
3876	3821	}
3877	3822
	3823	static void cfunc_rsp_vmacf_simd(void *param)
	3824	{
	3825	((rsp_device *)param)->ccfunc_rsp_vmacf_simd();
	3826	}
3878	3827	#endif
3879	3828
3880	3829	#if (!USE_SIMD || SIMUL_SIMD)
3881	3830
3882		INLINE void cfunc_rsp_vmacf_scalar(void *param)
	3831	inline void rsp_device::ccfunc_rsp_vmacf_scalar()
3883	3832	{
3884		rsp_state *rsp = (rsp_state*)param;
3885		int op = rsp->impstate->arg0;
	3833	int op = m_rsp_state->arg0;
3886	3834
3887	3835	INT16 vres[8];
3888	3836	for (int i = 0; i < 8; i++)
r31833	r31834
3895	3843
3896	3844	INT32 r = s1 * s2;
3897	3845
3898		UINT64 q = (UINT64)(UINT16)ACCUM_LL(rsp, i);
3899		q |= (((UINT64)(UINT16)ACCUM_L(rsp, i)) << 16);
3900		q |= (((UINT64)(UINT16)ACCUM_M(rsp, i)) << 32);
3901		q |= (((UINT64)(UINT16)ACCUM_H(rsp, i)) << 48);
	3846	UINT64 q = (UINT64)(UINT16)ACCUM_LL(i);
	3847	q |= (((UINT64)(UINT16)ACCUM_L(i)) << 16);
	3848	q |= (((UINT64)(UINT16)ACCUM_M(i)) << 32);
	3849	q |= (((UINT64)(UINT16)ACCUM_H(i)) << 48);
3902	3850
3903	3851	q += (INT64)(r) << 17;
3904	3852	SET_ACCUM_LL((UINT16)q, i);
r31833	r31834
3906	3854	SET_ACCUM_M((UINT16)(q >> 32), i);
3907	3855	SET_ACCUM_H((UINT16)(q >> 48), i);
3908	3856
3909		vres[i] = SATURATE_ACCUM(rsp, i, 1, 0x8000, 0x7fff);
	3857	vres[i] = SATURATE_ACCUM(i, 1, 0x8000, 0x7fff);
3910	3858	}
3911	3859	WRITEBACK_RESULT();
3912	3860	}
	3861
	3862	static void cfunc_rsp_vmacf_scalar(void *param)
	3863	{
	3864	((rsp_device *)param)->ccfunc_rsp_vmacf_scalar();
	3865	}
3913	3866	#endif
3914	3867
3915	3868	#if USE_SIMD
r31833	r31834
3921	3874	// ------------------------------------------------------
3922	3875	//
3923	3876
3924		INLINE void cfunc_rsp_vmacu_simd(void *param)
	3877	inline void rsp_device::ccfunc_rsp_vmacu_simd()
3925	3878	{
3926		rsp_state *rsp = (rsp_state*)param;
3927		int op = rsp->impstate->arg0;
	3879	int op = m_rsp_state->arg0;
3928	3880
3929	3881	__m128i loProduct, hiProduct, unpackLo, unpackHi;
3930	3882	__m128i vaccHigh;
3931	3883	__m128i vdReg, vdRegLo, vdRegHi;
3932	3884
3933		__m128i vsReg = rsp->xv[VS1REG];
3934		__m128i vtReg = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
	3885	__m128i vsReg = m_xv[VS1REG];
	3886	__m128i vtReg = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
3935	3887
3936		__m128i vaccLow = rsp->accum_l;
	3888	__m128i vaccLow = m_accum_l;
3937	3889
3938	3890	/* Unpack to obtain for 32-bit precision. */
3939	3891	RSPZeroExtend16to32(vaccLow, &vaccLow, &vaccHigh);
r31833	r31834
3956	3908	vaccLow = _mm_add_epi32(vaccLow, vdRegLo);
3957	3909	vaccHigh = _mm_add_epi32(vaccHigh, vdRegHi);
3958	3910
3959		rsp->accum_l = vdReg = RSPPackLo32to16(vaccLow, vaccHigh);
	3911	m_accum_l = vdReg = RSPPackLo32to16(vaccLow, vaccHigh);
3960	3912
3961	3913	/* Multiply the MSB of sources, accumulate the product. */
3962		vdRegLo = _mm_unpacklo_epi16(rsp->accum_m, rsp->accum_h);
3963		vdRegHi = _mm_unpackhi_epi16(rsp->accum_m, rsp->accum_h);
	3914	vdRegLo = _mm_unpacklo_epi16(m_accum_m, m_accum_h);
	3915	vdRegHi = _mm_unpackhi_epi16(m_accum_m, m_accum_h);
3964	3916
3965	3917	loProduct = _mm_srai_epi32(loProduct, 16);
3966	3918	hiProduct = _mm_srai_epi32(hiProduct, 16);
r31833	r31834
3973	3925	vaccHigh = _mm_add_epi32(vdRegHi, vaccHigh);
3974	3926
3975	3927	/* Clamp the accumulator and write it all out. */
3976		rsp->accum_m = RSPPackLo32to16(vaccLow, vaccHigh);
3977		rsp->accum_h = RSPPackHi32to16(vaccLow, vaccHigh);
	3928	m_accum_m = RSPPackLo32to16(vaccLow, vaccHigh);
	3929	m_accum_h = RSPPackHi32to16(vaccLow, vaccHigh);
3978	3930	}
3979	3931
	3932	static void cfunc_rsp_vmacu_simd(void *param)
	3933	{
	3934	((rsp_device *)param)->ccfunc_rsp_vmacu_simd();
	3935	}
3980	3936	#endif
3981	3937
3982	3938	#if (!USE_SIMD || SIMUL_SIMD)
3983	3939
3984		INLINE void cfunc_rsp_vmacu_scalar(void *param)
	3940	inline void rsp_device::ccfunc_rsp_vmacu_scalar()
3985	3941	{
3986		rsp_state *rsp = (rsp_state*)param;
3987		int op = rsp->impstate->arg0;
	3942	int op = m_rsp_state->arg0;
3988	3943
3989	3944	INT16 vres[8];
3990	3945	for (int i = 0; i < 8; i++)
r31833	r31834
3996	3951	INT32 s2 = (INT32)(INT16)w2;
3997	3952
3998	3953	INT32 r1 = s1 * s2;
3999		UINT32 r2 = (UINT16)ACCUM_L(rsp, i) + ((UINT16)(r1) * 2);
4000		UINT32 r3 = (UINT16)ACCUM_M(rsp, i) + (UINT16)((r1 >> 16) * 2) + (UINT16)(r2 >> 16);
	3954	UINT32 r2 = (UINT16)ACCUM_L(i) + ((UINT16)(r1) * 2);
	3955	UINT32 r3 = (UINT16)ACCUM_M(i) + (UINT16)((r1 >> 16) * 2) + (UINT16)(r2 >> 16);
4001	3956
4002	3957	SET_ACCUM_L((UINT16)(r2), i);
4003	3958	SET_ACCUM_M((UINT16)(r3), i);
4004		SET_ACCUM_H(ACCUM_H(rsp, i) + (UINT16)(r3 >> 16) + (UINT16)(r1 >> 31), i);
	3959	SET_ACCUM_H(ACCUM_H(i) + (UINT16)(r3 >> 16) + (UINT16)(r1 >> 31), i);
4005	3960
4006		if ((INT16)ACCUM_H(rsp, i) < 0)
	3961	if ((INT16)ACCUM_H(i) < 0)
4007	3962	{
4008	3963	vres[i] = 0;
4009	3964	}
4010	3965	else
4011	3966	{
4012		if (ACCUM_H(rsp, i) != 0)
	3967	if (ACCUM_H(i) != 0)
4013	3968	{
4014	3969	vres[i] = (INT16)0xffff;
4015	3970	}
4016	3971	else
4017	3972	{
4018		if ((INT16)ACCUM_M(rsp, i) < 0)
	3973	if ((INT16)ACCUM_M(i) < 0)
4019	3974	{
4020	3975	vres[i] = (INT16)0xffff;
4021	3976	}
4022	3977	else
4023	3978	{
4024		vres[i] = ACCUM_M(rsp, i);
	3979	vres[i] = ACCUM_M(i);
4025	3980	}
4026	3981	}
4027	3982	}
4028	3983	}
4029	3984	WRITEBACK_RESULT();
4030	3985	}
	3986
	3987	static void cfunc_rsp_vmacu_scalar(void *param)
	3988	{
	3989	((rsp_device *)param)->ccfunc_rsp_vmacu_scalar();
	3990	}
4031	3991	#endif
4032	3992
4033	3993	#if USE_SIMD
r31833	r31834
4042	4002	// Adds the higher 16 bits of the 32-bit result to accumulator
4043	4003	// The low slice of accumulator is stored into destination element
4044	4004
4045		INLINE void cfunc_rsp_vmadl_simd(void *param)
	4005	inline void rsp_device::ccfunc_rsp_vmadl_simd()
4046	4006	{
4047		rsp_state *rsp = (rsp_state*)param;
4048		int op = rsp->impstate->arg0;
	4007	int op = m_rsp_state->arg0;
4049	4008
4050	4009	INT16 vres[8];
4051	4010	for (int i = 0; i < 8; i++)
r31833	r31834
4057	4016	UINT32 s2 = w2;
4058	4017
4059	4018	UINT32 r1 = s1 * s2;
4060		UINT32 r2 = (UINT16)VEC_ACCUM_L(rsp, i) + (r1 >> 16);
4061		UINT32 r3 = (UINT16)VEC_ACCUM_M(rsp, i) + (r2 >> 16);
	4019	UINT32 r2 = (UINT16)VEC_ACCUM_L(i) + (r1 >> 16);
	4020	UINT32 r3 = (UINT16)VEC_ACCUM_M(i) + (r2 >> 16);
4062	4021
4063	4022	VEC_SET_ACCUM_L((UINT16)r2, i);
4064	4023	VEC_SET_ACCUM_M((UINT16)r3, i);
4065		VEC_SET_ACCUM_H(VEC_ACCUM_H(rsp, i) + (INT16)(r3 >> 16), i);
	4024	VEC_SET_ACCUM_H(VEC_ACCUM_H(i) + (INT16)(r3 >> 16), i);
4066	4025
4067		vres[i] = VEC_SATURATE_ACCUM(rsp, i, 0, 0x0000, 0xffff);
	4026	vres[i] = VEC_SATURATE_ACCUM(i, 0, 0x0000, 0xffff);
4068	4027	}
4069	4028	VEC_WRITEBACK_RESULT();
4070	4029
r31833	r31834
4072	4031	__m128i unpackHi, loProduct, hiProduct;
4073	4032	__m128i vdReg, vdRegLo, vdRegHi;
4074	4033
4075		__m128i vsReg = rsp->xv[VS1REG];
4076		__m128i vtReg = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
	4034	__m128i vsReg = m_xv[VS1REG];
	4035	__m128i vtReg = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
4077	4036
4078		__m128i vaccLow = rsp->accum_l;
	4037	__m128i vaccLow = m_accum_l;
4079	4038
4080	4039	// Unpack to obtain for 32-bit precision.
4081	4040	RSPZeroExtend16to32(vaccLow, &vaccLow, &vaccHigh);
r31833	r31834
4087	4046
4088	4047	vaccLow = _mm_add_epi32(vaccLow, loProduct);
4089	4048	vaccHigh = _mm_add_epi32(vaccHigh, hiProduct);
4090		rsp->accum_l = vdReg = RSPPackLo32to16(vaccLow, vaccHigh);
	4049	m_accum_l = vdReg = RSPPackLo32to16(vaccLow, vaccHigh);
4091	4050
4092	4051	// Finish accumulating whatever is left.
4093		vdRegLo = _mm_unpacklo_epi16(rsp->accum_m, rsp->accum_h);
4094		vdRegHi = _mm_unpackhi_epi16(rsp->accum_m, rsp->accum_h);
	4052	vdRegLo = _mm_unpacklo_epi16(m_accum_m, m_accum_h);
	4053	vdRegHi = _mm_unpackhi_epi16(m_accum_m, m_accum_h);
4095	4054
4096	4055	vaccLow = _mm_srai_epi32(vaccLow, 16);
4097	4056	vaccHigh = _mm_srai_epi32(vaccHigh, 16);
r31833	r31834
4099	4058	vaccHigh = _mm_add_epi32(vdRegHi, vaccHigh);
4100	4059
4101	4060	// Clamp the accumulator and write it all out.
4102		rsp->accum_m = RSPPackLo32to16(vaccLow, vaccHigh);
4103		rsp->accum_h = RSPPackHi32to16(vaccLow, vaccHigh);
4104		rsp->xv[VDREG] = RSPClampLowToVal(vdReg, rsp->accum_m, rsp->accum_h);*/
	4061	m_accum_m = RSPPackLo32to16(vaccLow, vaccHigh);
	4062	m_accum_h = RSPPackHi32to16(vaccLow, vaccHigh);
	4063	m_xv[VDREG] = RSPClampLowToVal(vdReg, m_accum_m, m_accum_h);*/
4105	4064	}
4106	4065
	4066	static void cfunc_rsp_vmadl_simd(void *param)
	4067	{
	4068	((rsp_device *)param)->ccfunc_rsp_vmadl_simd();
	4069	}
4107	4070	#endif
4108	4071
4109	4072	#if (!USE_SIMD || SIMUL_SIMD)
4110	4073
4111		INLINE void cfunc_rsp_vmadl_scalar(void *param)
	4074	inline void rsp_device::ccfunc_rsp_vmadl_scalar()
4112	4075	{
4113		rsp_state *rsp = (rsp_state*)param;
4114		int op = rsp->impstate->arg0;
	4076	int op = m_rsp_state->arg0;
4115	4077
4116	4078	INT16 vres[8];
4117	4079	for (int i = 0; i < 8; i++)
r31833	r31834
4123	4085	UINT32 s2 = w2;
4124	4086
4125	4087	UINT32 r1 = s1 * s2;
4126		UINT32 r2 = (UINT16)ACCUM_L(rsp, i) + (r1 >> 16);
4127		UINT32 r3 = (UINT16)ACCUM_M(rsp, i) + (r2 >> 16);
	4088	UINT32 r2 = (UINT16)ACCUM_L(i) + (r1 >> 16);
	4089	UINT32 r3 = (UINT16)ACCUM_M(i) + (r2 >> 16);
4128	4090
4129	4091	SET_ACCUM_L((UINT16)r2, i);
4130	4092	SET_ACCUM_M((UINT16)r3, i);
4131		SET_ACCUM_H(ACCUM_H(rsp, i) + (INT16)(r3 >> 16), i);
	4093	SET_ACCUM_H(ACCUM_H(i) + (INT16)(r3 >> 16), i);
4132	4094
4133		vres[i] = SATURATE_ACCUM(rsp, i, 0, 0x0000, 0xffff);
	4095	vres[i] = SATURATE_ACCUM(i, 0, 0x0000, 0xffff);
4134	4096	}
4135	4097	WRITEBACK_RESULT();
4136	4098	}
	4099
	4100	static void cfunc_rsp_vmadl_scalar(void *param)
	4101	{
	4102	((rsp_device *)param)->ccfunc_rsp_vmadl_scalar();
	4103	}
4137	4104	#endif
4138	4105
4139	4106	#if USE_SIMD
4140	4107	// VMADM
4141	4108	//
4142	4109
4143		INLINE void cfunc_rsp_vmadm_simd(void *param)
	4110	inline void rsp_device::ccfunc_rsp_vmadm_simd()
4144	4111	{
4145		rsp_state *rsp = (rsp_state*)param;
4146		int op = rsp->impstate->arg0;
	4112	int op = m_rsp_state->arg0;
4147	4113
4148	4114	__m128i vaccLow, vaccHigh, loProduct, hiProduct;
4149	4115	__m128i vsRegLo, vsRegHi, vtRegLo, vtRegHi, vdRegLo, vdRegHi;
4150	4116
4151		__m128i vsReg = rsp->xv[VS1REG];
4152		__m128i vtReg = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
	4117	__m128i vsReg = m_xv[VS1REG];
	4118	__m128i vtReg = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
4153	4119
4154	4120	/* Unpack to obtain for 32-bit precision. */
4155	4121	RSPSignExtend16to32(vsReg, &vsRegLo, &vsRegHi);
4156	4122	RSPZeroExtend16to32(vtReg, &vtRegLo, &vtRegHi);
4157		RSPZeroExtend16to32(rsp->accum_l, &vaccLow, &vaccHigh);
	4123	RSPZeroExtend16to32(m_accum_l, &vaccLow, &vaccHigh);
4158	4124
4159	4125	/* Begin accumulating the products. */
4160	4126	loProduct = _mm_mullo_epi32(vsRegLo, vtRegLo);
r31833	r31834
4169	4135	vaccLow = _mm_add_epi32(vaccLow, vdRegLo);
4170	4136	vaccHigh = _mm_add_epi32(vaccHigh, vdRegHi);
4171	4137
4172		rsp->accum_l = rsp->xv[VDREG] = RSPPackLo32to16(vaccLow, vaccHigh);
	4138	m_accum_l = m_xv[VDREG] = RSPPackLo32to16(vaccLow, vaccHigh);
4173	4139
4174	4140	/* Multiply the MSB of sources, accumulate the product. */
4175		vdRegLo = _mm_unpacklo_epi16(rsp->accum_m, rsp->accum_h);
4176		vdRegHi = _mm_unpackhi_epi16(rsp->accum_m, rsp->accum_h);
	4141	vdRegLo = _mm_unpacklo_epi16(m_accum_m, m_accum_h);
	4142	vdRegHi = _mm_unpackhi_epi16(m_accum_m, m_accum_h);
4177	4143
4178	4144	loProduct = _mm_srai_epi32(loProduct, 16);
4179	4145	hiProduct = _mm_srai_epi32(hiProduct, 16);
r31833	r31834
4186	4152	vaccHigh = _mm_add_epi32(vdRegHi, vaccHigh);
4187	4153
4188	4154	/* Clamp the accumulator and write it all out. */
4189		rsp->xv[VDREG] = _mm_packs_epi32(vaccLow, vaccHigh);
4190		rsp->accum_m = RSPPackLo32to16(vaccLow, vaccHigh);
4191		rsp->accum_h = RSPPackHi32to16(vaccLow, vaccHigh);
	4155	m_xv[VDREG] = _mm_packs_epi32(vaccLow, vaccHigh);
	4156	m_accum_m = RSPPackLo32to16(vaccLow, vaccHigh);
	4157	m_accum_h = RSPPackHi32to16(vaccLow, vaccHigh);
4192	4158	}
4193	4159
	4160	static void cfunc_rsp_vmadm_simd(void *param)
	4161	{
	4162	((rsp_device *)param)->ccfunc_rsp_vmadm_simd();
	4163	}
4194	4164	#endif
4195	4165
4196	4166	#if (!USE_SIMD || SIMUL_SIMD)
4197	4167
4198		INLINE void cfunc_rsp_vmadm_scalar(void *param)
	4168	inline void rsp_device::ccfunc_rsp_vmadm_scalar()
4199	4169	{
4200		rsp_state *rsp = (rsp_state*)param;
4201		int op = rsp->impstate->arg0;
	4170	int op = m_rsp_state->arg0;
4202	4171
4203	4172	INT16 vres[8];
4204	4173	for (int i = 0; i < 8; i++)
r31833	r31834
4210	4179	UINT32 s2 = (UINT16)w2;
4211	4180
4212	4181	UINT32 r1 = s1 * s2;
4213		UINT32 r2 = (UINT16)ACCUM_L(rsp, i) + (UINT16)(r1);
4214		UINT32 r3 = (UINT16)ACCUM_M(rsp, i) + (r1 >> 16) + (r2 >> 16);
	4182	UINT32 r2 = (UINT16)ACCUM_L(i) + (UINT16)(r1);
	4183	UINT32 r3 = (UINT16)ACCUM_M(i) + (r1 >> 16) + (r2 >> 16);
4215	4184
4216	4185	SET_ACCUM_L((UINT16)r2, i);
4217	4186	SET_ACCUM_M((UINT16)r3, i);
4218		SET_ACCUM_H((UINT16)ACCUM_H(rsp, i) + (UINT16)(r3 >> 16), i);
	4187	SET_ACCUM_H((UINT16)ACCUM_H(i) + (UINT16)(r3 >> 16), i);
4219	4188	if ((INT32)(r1) < 0)
4220	4189	{
4221		SET_ACCUM_H((UINT16)ACCUM_H(rsp, i) - 1, i);
	4190	SET_ACCUM_H((UINT16)ACCUM_H(i) - 1, i);
4222	4191	}
4223	4192
4224		vres[i] = SATURATE_ACCUM(rsp, i, 1, 0x8000, 0x7fff);
	4193	vres[i] = SATURATE_ACCUM(i, 1, 0x8000, 0x7fff);
4225	4194	}
4226	4195	WRITEBACK_RESULT();
4227	4196	}
	4197
	4198	static void cfunc_rsp_vmadm_scalar(void *param)
	4199	{
	4200	((rsp_device *)param)->ccfunc_rsp_vmadm_scalar();
	4201	}
4228	4202	#endif
4229	4203
4230	4204	#if USE_SIMD
4231	4205	// VMADN
4232	4206	//
4233	4207
4234		INLINE void cfunc_rsp_vmadn_simd(void *param)
	4208	inline void rsp_device::ccfunc_rsp_vmadn_simd()
4235	4209	{
4236		rsp_state *rsp = (rsp_state*)param;
4237		int op = rsp->impstate->arg0;
	4210	int op = m_rsp_state->arg0;
4238	4211
4239	4212	INT16 vres[8];
4240	4213	for (int i = 0; i < 8; i++)
r31833	r31834
4245	4218	INT32 s1 = (UINT16)w1;
4246	4219	INT32 s2 = (INT32)(INT16)w2;
4247	4220
4248		UINT64 q = (UINT64)VEC_ACCUM_LL(rsp, i);
4249		q |= (((UINT64)VEC_ACCUM_L(rsp, i)) << 16);
4250		q |= (((UINT64)VEC_ACCUM_M(rsp, i)) << 32);
4251		q |= (((UINT64)VEC_ACCUM_H(rsp, i)) << 48);
	4221	UINT64 q = (UINT64)VEC_ACCUM_LL(i);
	4222	q |= (((UINT64)VEC_ACCUM_L(i)) << 16);
	4223	q |= (((UINT64)VEC_ACCUM_M(i)) << 32);
	4224	q |= (((UINT64)VEC_ACCUM_H(i)) << 48);
4252	4225	q += (INT64)(s1*s2) << 16;
4253	4226
4254	4227	VEC_SET_ACCUM_LL((UINT16)q, i);
r31833	r31834
4256	4229	VEC_SET_ACCUM_M((UINT16)(q >> 32), i);
4257	4230	VEC_SET_ACCUM_H((UINT16)(q >> 48), i);
4258	4231
4259		vres[i] = VEC_SATURATE_ACCUM(rsp, i, 0, 0x0000, 0xffff);
	4232	vres[i] = VEC_SATURATE_ACCUM(i, 0, 0x0000, 0xffff);
4260	4233	}
4261	4234	VEC_WRITEBACK_RESULT();
4262	4235	}
4263	4236	/*INLINE void cfunc_rsp_vmadn_simd(void *param)
4264	4237	{
4265	4238	rsp_state *rsp = (rsp_state*)param;
4266		int op = rsp->impstate->arg0;
	4239	int op = m_rsp_state->arg0;
4267	4240
4268	4241	__m128i vaccLow, vaccHigh, loProduct, hiProduct;
4269	4242	__m128i vsRegLo, vsRegHi, vtRegLo, vtRegHi, vdRegLo, vdRegHi;
4270	4243
4271		__m128i vsReg = rsp->xv[VS1REG];
4272		__m128i vtReg = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
	4244	__m128i vsReg = m_xv[VS1REG];
	4245	__m128i vtReg = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
4273	4246
4274		vaccLow = rsp->accum_l;
	4247	vaccLow = m_accum_l;
4275	4248
4276	4249	RSPZeroExtend16to32(vsReg, &vsRegLo, &vsRegHi);
4277	4250	RSPSignExtend16to32(vtReg, &vtRegLo, &vtRegHi);
r31833	r31834
4291	4264	vaccLow = _mm_add_epi32(vaccLow, vdRegLo);
4292	4265	vaccHigh = _mm_add_epi32(vaccHigh, vdRegHi);
4293	4266
4294		rsp->accum_l = RSPPackLo32to16(vaccLow, vaccHigh);
	4267	m_accum_l = RSPPackLo32to16(vaccLow, vaccHigh);
4295	4268
4296	4269	// Multiply the MSB of sources, accumulate the product.
4297		vdRegLo = _mm_unpacklo_epi16(rsp->accum_m, rsp->accum_h);
4298		vdRegHi = _mm_unpackhi_epi16(rsp->accum_m, rsp->accum_h);
	4270	vdRegLo = _mm_unpacklo_epi16(m_accum_m, m_accum_h);
	4271	vdRegHi = _mm_unpackhi_epi16(m_accum_m, m_accum_h);
4299	4272
4300	4273	loProduct = _mm_srai_epi32(loProduct, 16);
4301	4274	hiProduct = _mm_srai_epi32(hiProduct, 16);
r31833	r31834
4308	4281	vaccHigh = _mm_add_epi32(vdRegHi, vaccHigh);
4309	4282
4310	4283	// Clamp the accumulator and write it all out.
4311		rsp->accum_m = RSPPackLo32to16(vaccLow, vaccHigh);
4312		rsp->accum_h = RSPPackHi32to16(vaccLow, vaccHigh);
4313		rsp->xv[VDREG] = RSPClampLowToVal(rsp->accum_l, rsp->accum_m, rsp->accum_h);
	4284	m_accum_m = RSPPackLo32to16(vaccLow, vaccHigh);
	4285	m_accum_h = RSPPackHi32to16(vaccLow, vaccHigh);
	4286	m_xv[VDREG] = RSPClampLowToVal(m_accum_l, m_accum_m, m_accum_h);
4314	4287	}*/
4315	4288
	4289	static void cfunc_rsp_vmadn_simd(void *param)
	4290	{
	4291	((rsp_device *)param)->ccfunc_rsp_vmadn_simd();
	4292	}
4316	4293	#endif
4317	4294
4318	4295	#if (!USE_SIMD || SIMUL_SIMD)
4319	4296
4320		INLINE void cfunc_rsp_vmadn_scalar(void *param)
	4297	inline void rsp_device::ccfunc_rsp_vmadn_scalar()
4321	4298	{
4322		rsp_state *rsp = (rsp_state*)param;
4323		int op = rsp->impstate->arg0;
	4299	int op = m_rsp_state->arg0;
4324	4300
4325	4301	INT16 vres[8];
4326	4302	for (int i = 0; i < 8; i++)
r31833	r31834
4331	4307	INT32 s1 = (UINT16)w1;
4332	4308	INT32 s2 = (INT32)(INT16)w2;
4333	4309
4334		UINT64 q = (UINT64)ACCUM_LL(rsp, i);
4335		q |= (((UINT64)ACCUM_L(rsp, i)) << 16);
4336		q |= (((UINT64)ACCUM_M(rsp, i)) << 32);
4337		q |= (((UINT64)ACCUM_H(rsp, i)) << 48);
	4310	UINT64 q = (UINT64)ACCUM_LL(i);
	4311	q |= (((UINT64)ACCUM_L(i)) << 16);
	4312	q |= (((UINT64)ACCUM_M(i)) << 32);
	4313	q |= (((UINT64)ACCUM_H(i)) << 48);
4338	4314	q += (INT64)(s1*s2) << 16;
4339	4315
4340	4316	SET_ACCUM_LL((UINT16)q, i);
r31833	r31834
4342	4318	SET_ACCUM_M((UINT16)(q >> 32), i);
4343	4319	SET_ACCUM_H((UINT16)(q >> 48), i);
4344	4320
4345		vres[i] = SATURATE_ACCUM(rsp, i, 0, 0x0000, 0xffff);
	4321	vres[i] = SATURATE_ACCUM(i, 0, 0x0000, 0xffff);
4346	4322	}
4347	4323	WRITEBACK_RESULT();
4348	4324	}
	4325
	4326	static void cfunc_rsp_vmadn_scalar(void *param)
	4327	{
	4328	((rsp_device *)param)->ccfunc_rsp_vmadn_scalar();
	4329	}
4349	4330	#endif
4350	4331
4351	4332	#if USE_SIMD
r31833	r31834
4360	4341	// The result is added into highest 32 bits of accumulator, the low slice is zero
4361	4342	// The highest 32 bits of accumulator is saturated into destination element
4362	4343
4363		INLINE void cfunc_rsp_vmadh_simd(void *param)
	4344	inline void rsp_device::ccfunc_rsp_vmadh_simd()
4364	4345	{
4365		rsp_state *rsp = (rsp_state*)param;
4366		int op = rsp->impstate->arg0;
	4346	int op = m_rsp_state->arg0;
4367	4347
4368		__m128i vsReg = rsp->xv[VS1REG];
4369		__m128i vtReg = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
	4348	__m128i vsReg = m_xv[VS1REG];
	4349	__m128i vtReg = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
4370	4350
4371	4351	/* Unpack to obtain for 32-bit precision. */
4372		__m128i vaccLow = _mm_unpacklo_epi16(rsp->accum_m, rsp->accum_h);
4373		__m128i vaccHigh = _mm_unpackhi_epi16(rsp->accum_m, rsp->accum_h);
	4352	__m128i vaccLow = _mm_unpacklo_epi16(m_accum_m, m_accum_h);
	4353	__m128i vaccHigh = _mm_unpackhi_epi16(m_accum_m, m_accum_h);
4374	4354
4375	4355	/* Multiply the sources, accumulate the product. */
4376	4356	__m128i unpackLo = _mm_mullo_epi16(vsReg, vtReg);
r31833	r31834
4381	4361	vaccHigh = _mm_add_epi32(vaccHigh, hiProduct);
4382	4362
4383	4363	/* Pack the accumulator and result back up. */
4384		rsp->xv[VDREG] = _mm_packs_epi32(vaccLow, vaccHigh);
4385		rsp->accum_m = RSPPackLo32to16(vaccLow, vaccHigh);
4386		rsp->accum_h = RSPPackHi32to16(vaccLow, vaccHigh);
	4364	m_xv[VDREG] = _mm_packs_epi32(vaccLow, vaccHigh);
	4365	m_accum_m = RSPPackLo32to16(vaccLow, vaccHigh);
	4366	m_accum_h = RSPPackHi32to16(vaccLow, vaccHigh);
4387	4367	}
4388	4368
	4369	static void cfunc_rsp_vmadh_simd(void *param)
	4370	{
	4371	((rsp_device *)param)->ccfunc_rsp_vmadh_simd();
	4372	}
4389	4373	#endif
4390	4374
4391	4375	#if (!USE_SIMD || SIMUL_SIMD)
4392	4376
4393		INLINE void cfunc_rsp_vmadh_scalar(void *param)
	4377	inline void rsp_device::ccfunc_rsp_vmadh_scalar()
4394	4378	{
4395		rsp_state *rsp = (rsp_state*)param;
4396		int op = rsp->impstate->arg0;
	4379	int op = m_rsp_state->arg0;
4397	4380
4398	4381	INT16 vres[8];
4399	4382	for (int i = 0; i < 8; i++)
r31833	r31834
4404	4387	INT32 s1 = (INT32)(INT16)w1;
4405	4388	INT32 s2 = (INT32)(INT16)w2;
4406	4389
4407		INT32 accum = (UINT32)(UINT16)ACCUM_M(rsp, i);
4408		accum |= ((UINT32)((UINT16)ACCUM_H(rsp, i))) << 16;
	4390	INT32 accum = (UINT32)(UINT16)ACCUM_M(i);
	4391	accum |= ((UINT32)((UINT16)ACCUM_H(i))) << 16;
4409	4392	accum += s1*s2;
4410	4393
4411	4394	SET_ACCUM_H((UINT16)(accum >> 16), i);
4412	4395	SET_ACCUM_M((UINT16)accum, i);
4413	4396
4414		vres[i] = SATURATE_ACCUM1(rsp, i, 0x8000, 0x7fff);
	4397	vres[i] = SATURATE_ACCUM1(i, 0x8000, 0x7fff);
4415	4398	}
4416	4399	WRITEBACK_RESULT();
4417	4400	}
	4401
	4402	static void cfunc_rsp_vmadh_scalar(void *param)
	4403	{
	4404	((rsp_device *)param)->ccfunc_rsp_vmadh_scalar();
	4405	}
4418	4406	#endif
4419	4407
4420	4408	#if USE_SIMD
r31833	r31834
4426	4414	//
4427	4415	// Adds two vector registers and carry flag, the result is saturated to 32767
4428	4416
4429		INLINE void cfunc_rsp_vadd_simd(void *param)
	4417	inline void rsp_device::ccfunc_rsp_vadd_simd()
4430	4418	{
4431		rsp_state *rsp = (rsp_state*)param;
4432		int op = rsp->impstate->arg0;
	4419	int op = m_rsp_state->arg0;
4433	4420
4434		__m128i shuffled = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
4435		__m128i carry = _mm_and_si128(rsp->xvflag[CARRY], vec_flagmask);
4436		rsp->accum_l = _mm_add_epi16(_mm_add_epi16(rsp->xv[VS1REG], shuffled), carry);
	4421	__m128i shuffled = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
	4422	__m128i carry = _mm_and_si128(m_xvflag[CARRY], vec_flagmask);
	4423	m_accum_l = _mm_add_epi16(_mm_add_epi16(m_xv[VS1REG], shuffled), carry);
4437	4424
4438		__m128i addvec = _mm_adds_epi16(rsp->xv[VS1REG], shuffled);
	4425	__m128i addvec = _mm_adds_epi16(m_xv[VS1REG], shuffled);
4439	4426
4440	4427	carry = _mm_and_si128(carry, _mm_xor_si128(_mm_cmpeq_epi16(addvec, vec_32767), vec_neg1));
4441	4428	carry = _mm_and_si128(carry, _mm_xor_si128(_mm_cmpeq_epi16(addvec, vec_n32768), vec_neg1));
4442	4429
4443		rsp->xv[VDREG] = _mm_add_epi16(addvec, carry);
	4430	m_xv[VDREG] = _mm_add_epi16(addvec, carry);
4444	4431
4445		rsp->xvflag[ZERO] = vec_zero;
4446		rsp->xvflag[CARRY] = vec_zero;
	4432	m_xvflag[ZERO] = vec_zero;
	4433	m_xvflag[CARRY] = vec_zero;
4447	4434	}
4448	4435
	4436	static void cfunc_rsp_vadd_simd(void *param)
	4437	{
	4438	((rsp_Device *)param)->ccfunc_rsp_vadd_simd();
	4439	}
4449	4440	#endif
4450	4441
4451	4442	#if (!USE_SIMD || SIMUL_SIMD)
4452	4443
4453		INLINE void cfunc_rsp_vadd_scalar(void *param)
	4444	inline void rsp_device::ccfunc_rsp_vadd_scalar()
4454	4445	{
4455		rsp_state *rsp = (rsp_state*)param;
4456		int op = rsp->impstate->arg0;
	4446	int op = m_rsp_state->arg0;
4457	4447
4458	4448	INT16 vres[8] = { 0 };
4459	4449	for (int i = 0; i < 8; i++)
r31833	r31834
4463	4453	SCALAR_GET_VS2(w2, i);
4464	4454	INT32 s1 = (INT32)(INT16)w1;
4465	4455	INT32 s2 = (INT32)(INT16)w2;
4466		INT32 r = s1 + s2 + (((CARRY_FLAG(rsp, i)) != 0) ? 1 : 0);
	4456	INT32 r = s1 + s2 + (((CARRY_FLAG(i)) != 0) ? 1 : 0);
4467	4457
4468	4458	SET_ACCUM_L((INT16)(r), i);
4469	4459
r31833	r31834
4475	4465	CLEAR_CARRY_FLAGS();
4476	4466	WRITEBACK_RESULT();
4477	4467	}
	4468
	4469	static void cfunc_rsp_vadd_scalar(void *param)
	4470	{
	4471	((rsp_device *)param)->ccfunc_rsp_vadd_scalar();
	4472	}
4478	4473	#endif
4479	4474
4480	4475	#if USE_SIMD
r31833	r31834
4488	4483	// Subtracts two vector registers and carry flag, the result is saturated to -32768
4489	4484	// TODO: check VS2REG == VDREG
4490	4485
4491		INLINE void cfunc_rsp_vsub_simd(void *param)
	4486	inline void rsp_device::ccfunc_rsp_vsub_simd()
4492	4487	{
4493		rsp_state *rsp = (rsp_state*)param;
4494		int op = rsp->impstate->arg0;
	4488	int op = m_rsp_state->arg0;
4495	4489
4496		__m128i shuffled = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
4497		__m128i carry = _mm_and_si128(rsp->xvflag[CARRY], vec_flagmask);
4498		__m128i unsat = _mm_sub_epi16(rsp->xv[VS1REG], shuffled);
	4490	__m128i shuffled = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
	4491	__m128i carry = _mm_and_si128(m_xvflag[CARRY], vec_flagmask);
	4492	__m128i unsat = _mm_sub_epi16(m_xv[VS1REG], shuffled);
4499	4493
4500	4494	__m128i vs2neg = _mm_cmplt_epi16(shuffled, vec_zero);
4501	4495	__m128i vs2pos = _mm_cmpeq_epi16(vs2neg, vec_zero);
4502	4496
4503		__m128i saturated = _mm_subs_epi16(rsp->xv[VS1REG], shuffled);
	4497	__m128i saturated = _mm_subs_epi16(m_xv[VS1REG], shuffled);
4504	4498	__m128i carry_mask = _mm_cmpeq_epi16(unsat, saturated);
4505	4499	carry_mask = _mm_and_si128(vs2neg, carry_mask);
4506	4500
4507	4501	vs2neg = _mm_and_si128(carry_mask, carry);
4508	4502	vs2pos = _mm_and_si128(vs2pos, carry);
4509	4503	__m128i dest_carry = _mm_or_si128(vs2neg, vs2pos);
4510		rsp->xv[VDREG] = _mm_subs_epi16(saturated, dest_carry);
	4504	m_xv[VDREG] = _mm_subs_epi16(saturated, dest_carry);
4511	4505
4512		rsp->accum_l = _mm_sub_epi16(unsat, carry);
	4506	m_accum_l = _mm_sub_epi16(unsat, carry);
4513	4507
4514		rsp->xvflag[ZERO] = _mm_setzero_si128();
4515		rsp->xvflag[CARRY] = _mm_setzero_si128();
	4508	m_xvflag[ZERO] = _mm_setzero_si128();
	4509	m_xvflag[CARRY] = _mm_setzero_si128();
4516	4510	}
4517	4511
	4512	static void cfunc_rsp_vsub_simd(void *param)
	4513	{
	4514	((rsp_device *)param)->ccfunc_rsp_vsub_simd();
	4515	}
4518	4516	#endif
4519	4517
4520	4518	#if (!USE_SIMD || SIMUL_SIMD)
4521	4519
4522		INLINE void cfunc_rsp_vsub_scalar(void *param)
	4520	inline void rsp_device::ccfunc_rsp_vsub_scalar()
4523	4521	{
4524		rsp_state *rsp = (rsp_state*)param;
4525		int op = rsp->impstate->arg0;
	4522	int op = m_rsp_state->arg0;
4526	4523
4527	4524	INT16 vres[8];
4528	4525	for (int i = 0; i < 8; i++)
r31833	r31834
4532	4529	SCALAR_GET_VS2(w2, i);
4533	4530	INT32 s1 = (INT32)(INT16)w1;
4534	4531	INT32 s2 = (INT32)(INT16)w2;
4535		INT32 r = s1 - s2 - (((CARRY_FLAG(rsp, i)) != 0) ? 1 : 0);
	4532	INT32 r = s1 - s2 - (((CARRY_FLAG(i)) != 0) ? 1 : 0);
4536	4533
4537	4534	SET_ACCUM_L((INT16)(r), i);
4538	4535
r31833	r31834
4545	4542	CLEAR_CARRY_FLAGS();
4546	4543	WRITEBACK_RESULT();
4547	4544	}
	4545
	4546	static void cfunc_rsp_vsub_scalar(void *param)
	4547	{
	4548	((rsp_device *)param)->ccfunc_rsp_vsub_scalar();
	4549	}
4548	4550	#endif
4549	4551
4550	4552	#if USE_SIMD
r31833	r31834
4557	4559	//
4558	4560	// Changes the sign of source register 2 if source register 1 is negative and stores the result to destination register
4559	4561
4560		INLINE void cfunc_rsp_vabs_simd(void *param)
	4562	inline void rsp_device::ccfunc_rsp_vabs_simd()
4561	4563	{
4562		rsp_state *rsp = (rsp_state*)param;
4563		int op = rsp->impstate->arg0;
	4564	int op = m_rsp_state->arg0;
4564	4565
4565		__m128i shuf2 = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
	4566	__m128i shuf2 = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
4566	4567	__m128i negs2 = _mm_sub_epi16(_mm_setzero_si128(), shuf2);
4567	4568	__m128i s2_n32768 = _mm_cmpeq_epi16(shuf2, vec_n32768);
4568		__m128i s1_lz = _mm_cmplt_epi16(rsp->xv[VS1REG], _mm_setzero_si128());
	4569	__m128i s1_lz = _mm_cmplt_epi16(m_xv[VS1REG], _mm_setzero_si128());
4569	4570
4570		__m128i result_gz = _mm_and_si128(shuf2, _mm_cmpgt_epi16(rsp->xv[VS1REG], _mm_setzero_si128()));
	4571	__m128i result_gz = _mm_and_si128(shuf2, _mm_cmpgt_epi16(m_xv[VS1REG], _mm_setzero_si128()));
4571	4572	__m128i result_n32768 = _mm_and_si128(s1_lz, _mm_and_si128(vec_32767, s2_n32768));
4572	4573	__m128i result_negs2 = _mm_and_si128(s1_lz, _mm_and_si128(negs2, _mm_xor_si128(s2_n32768, vec_neg1)));
4573		rsp->xv[VDREG] = rsp->accum_l = _mm_or_si128(result_gz, _mm_or_si128(result_n32768, result_negs2));
	4574	m_xv[VDREG] = m_accum_l = _mm_or_si128(result_gz, _mm_or_si128(result_n32768, result_negs2));
4574	4575	}
4575	4576
	4577	static void cfunc_rsp_vabs_simd(void *param)
	4578	{
	4579	((rsp_device *)param)->ccfunc_rsp_vabs_simd();
	4580	}
4576	4581	#endif
4577	4582
4578	4583	#if (!USE_SIMD || SIMUL_SIMD)
4579	4584
4580		INLINE void cfunc_rsp_vabs_scalar(void *param)
	4585	inline void rsp_device::ccfunc_rsp_vabs_scalar()
4581	4586	{
4582		rsp_state *rsp = (rsp_state*)param;
4583		int op = rsp->impstate->arg0;
	4587	int op = m_rsp_state->arg0;
4584	4588
4585	4589	INT16 vres[8];
4586	4590	for (int i = 0; i < 8; i++)
r31833	r31834
4613	4617	}
4614	4618	WRITEBACK_RESULT();
4615	4619	}
	4620
	4621	static void cfunc_rsp_vabs_scalar(void *param)
	4622	{
	4623	((rsp_device *)param)->ccfunc_rsp_vabs_scalar();
	4624	}
4616	4625	#endif
4617	4626
4618	4627	#if USE_SIMD
r31833	r31834
4626	4635	// Adds two vector registers, the carry out is stored into carry register
4627	4636	// TODO: check VS2REG = VDREG
4628	4637
4629		INLINE void cfunc_rsp_vaddc_simd(void *param)
	4638	inline void rsp_device::ccfunc_rsp_vaddc_simd()
4630	4639	{
4631		rsp_state *rsp = (rsp_state*)param;
4632		int op = rsp->impstate->arg0;
	4640	int op = m_rsp_state->arg0;
4633	4641
4634	4642	VEC_CLEAR_ZERO_FLAGS();
4635	4643	VEC_CLEAR_CARRY_FLAGS();
4636	4644
4637		__m128i shuf2 = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
4638		__m128i vec7531 = _mm_and_si128(rsp->xv[VS1REG], vec_lomask);
4639		__m128i vec6420 = _mm_srli_epi32(rsp->xv[VS1REG], 16);
	4645	__m128i shuf2 = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
	4646	__m128i vec7531 = _mm_and_si128(m_xv[VS1REG], vec_lomask);
	4647	__m128i vec6420 = _mm_srli_epi32(m_xv[VS1REG], 16);
4640	4648	__m128i shuf7531 = _mm_and_si128(shuf2, vec_lomask);
4641	4649	__m128i shuf6420 = _mm_srli_epi32(shuf2, 16);
4642	4650	__m128i sum7531 = _mm_add_epi32(vec7531, shuf7531);
r31833	r31834
4648	4656	sum7531 = _mm_and_si128(sum7531, vec_lomask);
4649	4657	sum6420 = _mm_and_si128(sum6420, vec_lomask);
4650	4658
4651		rsp->xvflag[CARRY] = _mm_or_si128(over6420, _mm_srli_epi32(over7531, 16));
4652		rsp->accum_l = rsp->xv[VDREG] = _mm_or_si128(_mm_slli_epi32(sum6420, 16), sum7531);
	4659	m_xvflag[CARRY] = _mm_or_si128(over6420, _mm_srli_epi32(over7531, 16));
	4660	m_accum_l = m_xv[VDREG] = _mm_or_si128(_mm_slli_epi32(sum6420, 16), sum7531);
4653	4661	}
4654	4662
	4663	static void cfunc_rsp_vaddc_simd(void *param)
	4664	{
	4665	((rsp_device *)param)->ccfunc_rsp_vaddc_simd();
	4666	}
4655	4667	#endif
4656	4668
4657	4669	#if (!USE_SIMD || SIMUL_SIMD)
4658	4670
4659		INLINE void cfunc_rsp_vaddc_scalar(void *param)
	4671	inline void rsp_device::ccfunc_rsp_vaddc_scalar()
4660	4672	{
4661		rsp_state *rsp = (rsp_state*)param;
4662		int op = rsp->impstate->arg0;
	4673	int op = m_rsp_state->arg0;
4663	4674
4664	4675	CLEAR_ZERO_FLAGS();
4665	4676	CLEAR_CARRY_FLAGS();
r31833	r31834
4684	4695	}
4685	4696	WRITEBACK_RESULT();
4686	4697	}
	4698
	4699	static void cfunc_rsp_vaddc_scalar(void *param)
	4700	{
	4701	((rsp_device *)param)->ccfunc_rsp_vaddc_scalar();
	4702	}
4687	4703	#endif
4688	4704
4689	4705	#if USE_SIMD
r31833	r31834
4697	4713	// Subtracts two vector registers, the carry out is stored into carry register
4698	4714	// TODO: check VS2REG = VDREG
4699	4715
4700		INLINE void cfunc_rsp_vsubc_simd(void *param)
	4716	inline void rsp_device::ccfunc_rsp_vsubc_simd()
4701	4717	{
4702		rsp_state *rsp = (rsp_state*)param;
4703		int op = rsp->impstate->arg0;
	4718	int op = m_rsp_state->arg0;
4704	4719
4705	4720	VEC_CLEAR_ZERO_FLAGS();
4706	4721	VEC_CLEAR_CARRY_FLAGS();
4707	4722
4708		__m128i shuf2 = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
4709		__m128i vec7531 = _mm_and_si128(rsp->xv[VS1REG], vec_lomask);
4710		__m128i vec6420 = _mm_srli_epi32(rsp->xv[VS1REG], 16);
	4723	__m128i shuf2 = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
	4724	__m128i vec7531 = _mm_and_si128(m_xv[VS1REG], vec_lomask);
	4725	__m128i vec6420 = _mm_srli_epi32(m_xv[VS1REG], 16);
4711	4726	__m128i shuf7531 = _mm_and_si128(shuf2, vec_lomask);
4712	4727	__m128i shuf6420 = _mm_srli_epi32(shuf2, 16);
4713	4728	__m128i sum7531 = _mm_sub_epi32(vec7531, shuf7531);
r31833	r31834
4720	4735	__m128i zero7531 = _mm_and_si128(_mm_xor_si128(_mm_cmpeq_epi16(sum7531, _mm_setzero_si128()), vec_neg1), vec_lomask);
4721	4736	__m128i zero6420 = _mm_and_si128(_mm_xor_si128(_mm_cmpeq_epi16(sum6420, _mm_setzero_si128()), vec_neg1), vec_lomask);
4722	4737
4723		rsp->xvflag[CARRY] = _mm_or_si128(over6420, _mm_srli_epi32(over7531, 16));
4724		rsp->xvflag[ZERO] = _mm_or_si128(_mm_slli_epi32(zero6420, 16), zero7531);
	4738	m_xvflag[CARRY] = _mm_or_si128(over6420, _mm_srli_epi32(over7531, 16));
	4739	m_xvflag[ZERO] = _mm_or_si128(_mm_slli_epi32(zero6420, 16), zero7531);
4725	4740
4726		rsp->accum_l = rsp->xv[VDREG] = _mm_or_si128(_mm_slli_epi32(sum6420, 16), sum7531);
	4741	m_accum_l = m_xv[VDREG] = _mm_or_si128(_mm_slli_epi32(sum6420, 16), sum7531);
4727	4742	}
4728	4743
	4744	static void cfunc_rsp_vsubc_simd(void *param)
	4745	{
	4746	((rsp_device *)param)->ccfunc_rsp_vsubc_simd();
	4747	}
4729	4748	#endif
4730	4749
4731	4750	#if (!USE_SIMD || SIMUL_SIMD)
4732	4751
4733		INLINE void cfunc_rsp_vsubc_scalar(void *param)
	4752	inline void rsp_device::ccfunc_rsp_vsubc_scalar()
4734	4753	{
4735		rsp_state *rsp = (rsp_state*)param;
4736		int op = rsp->impstate->arg0;
	4754	int op = m_rsp_state->arg0;
4737	4755
4738	4756
4739	4757	CLEAR_ZERO_FLAGS();
r31833	r31834
4763	4781	}
4764	4782	WRITEBACK_RESULT();
4765	4783	}
	4784
	4785	static void cfunc_rsp_vsubc_scalar(void *param)
	4786	{
	4787	((rsp_device *)param)->ccfunc_rsp_vsubc_scalar();
	4788	}
4766	4789	#endif
4767	4790
4768	4791	#if USE_SIMD
r31833	r31834
4775	4798	//
4776	4799	// Stores high, middle or low slice of accumulator to destination vector
4777	4800
4778		INLINE void cfunc_rsp_vsaw_simd(void *param)
	4801	inline void rsp_device::ccfunc_rsp_vsaw_simd()
4779	4802	{
4780		rsp_state *rsp = (rsp_state*)param;
4781		int op = rsp->impstate->arg0;
	4803	int op = m_rsp_state->arg0;
4782	4804
4783	4805	switch (EL)
4784	4806	{
4785	4807	case 0x08:      // VSAWH
4786	4808	{
4787		rsp->xv[VDREG] = rsp->accum_h;
	4809	m_xv[VDREG] = m_accum_h;
4788	4810	break;
4789	4811	}
4790	4812	case 0x09:      // VSAWM
4791	4813	{
4792		rsp->xv[VDREG] = rsp->accum_m;
	4814	m_xv[VDREG] = m_accum_m;
4793	4815	break;
4794	4816	}
4795	4817	case 0x0a:      // VSAWL
4796	4818	{
4797		rsp->xv[VDREG] = rsp->accum_l;
	4819	m_xv[VDREG] = m_accum_l;
4798	4820	break;
4799	4821	}
4800	4822	default:    fatalerror("RSP: VSAW: el = %d\n", EL);
4801	4823	}
4802	4824	}
4803	4825
	4826	static void cfunc_rsp_vsaw_simd(void *param)
	4827	{
	4828	((rsp_device *)param)->ccfunc_rsp_vsaw_simd();
	4829	}
4804	4830	#endif
4805	4831
4806	4832	#if (!USE_SIMD || SIMUL_SIMD)
4807	4833
4808		INLINE void cfunc_rsp_vsaw_scalar(void *param)
	4834	inline void rsp_device::ccfunc_rsp_vsaw_scalar()
4809	4835	{
4810		rsp_state *rsp = (rsp_state*)param;
4811		int op = rsp->impstate->arg0;
	4836	int op = m_rsp_state->arg0;
4812	4837
4813	4838	switch (EL)
4814	4839	{
r31833	r31834
4816	4841	{
4817	4842	for (int i = 0; i < 8; i++)
4818	4843	{
4819		W_VREG_S(VDREG, i) = ACCUM_H(rsp, i);
	4844	W_VREG_S(VDREG, i) = ACCUM_H(i);
4820	4845	}
4821	4846	break;
4822	4847	}
r31833	r31834
4824	4849	{
4825	4850	for (int i = 0; i < 8; i++)
4826	4851	{
4827		W_VREG_S(VDREG, i) = ACCUM_M(rsp, i);
	4852	W_VREG_S(VDREG, i) = ACCUM_M(i);
4828	4853	}
4829	4854	break;
4830	4855	}
r31833	r31834
4832	4857	{
4833	4858	for (int i = 0; i < 8; i++)
4834	4859	{
4835		W_VREG_S(VDREG, i) = ACCUM_L(rsp, i);
	4860	W_VREG_S(VDREG, i) = ACCUM_L(i);
4836	4861	}
4837	4862	break;
4838	4863	}
4839	4864	default:    fatalerror("RSP: VSAW: el = %d\n", EL);
4840	4865	}
4841	4866	}
	4867
	4868	static void cfunc_rsp_vsaw_scalar(void *param)
	4869	{
	4870	((rsp_device *)param)->ccfunc_rsp_vsaw_scalar();
	4871	}
4842	4872	#endif
4843	4873
4844	4874	#if USE_SIMD
r31833	r31834
4852	4882	// Sets compare flags if elements in VS1 are less than VS2
4853	4883	// Moves the element in VS2 to destination vector
4854	4884
4855		INLINE void cfunc_rsp_vlt_simd(void *param)
	4885	inline void rsp_device::ccfunc_rsp_vlt_simd()
4856	4886	{
4857		rsp_state *rsp = (rsp_state*)param;
4858		int op = rsp->impstate->arg0;
	4887	int op = m_rsp_state->arg0;
4859	4888
4860		rsp->xvflag[COMPARE] = rsp->xvflag[CLIP2] = _mm_setzero_si128();
	4889	m_xvflag[COMPARE] = m_xvflag[CLIP2] = _mm_setzero_si128();
4861	4890
4862		__m128i shuf = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
4863		__m128i zc_mask = _mm_and_si128(rsp->xvflag[ZERO], rsp->xvflag[CARRY]);
4864		__m128i lt_mask = _mm_cmplt_epi16(rsp->xv[VS1REG], shuf);
4865		__m128i eq_mask = _mm_and_si128(_mm_cmpeq_epi16(rsp->xv[VS1REG], shuf), zc_mask);
	4891	__m128i shuf = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
	4892	__m128i zc_mask = _mm_and_si128(m_xvflag[ZERO], m_xvflag[CARRY]);
	4893	__m128i lt_mask = _mm_cmplt_epi16(m_xv[VS1REG], shuf);
	4894	__m128i eq_mask = _mm_and_si128(_mm_cmpeq_epi16(m_xv[VS1REG], shuf), zc_mask);
4866	4895
4867		rsp->xvflag[COMPARE] = _mm_or_si128(lt_mask, eq_mask);
	4896	m_xvflag[COMPARE] = _mm_or_si128(lt_mask, eq_mask);
4868	4897
4869		__m128i result = _mm_and_si128(rsp->xv[VS1REG], rsp->xvflag[COMPARE]);
4870		rsp->accum_l = rsp->xv[VDREG] = _mm_or_si128(result, _mm_and_si128(shuf, _mm_xor_si128(rsp->xvflag[COMPARE], vec_neg1)));
	4898	__m128i result = _mm_and_si128(m_xv[VS1REG], m_xvflag[COMPARE]);
	4899	m_accum_l = m_xv[VDREG] = _mm_or_si128(result, _mm_and_si128(shuf, _mm_xor_si128(m_xvflag[COMPARE], vec_neg1)));
4871	4900
4872		rsp->xvflag[ZERO] = rsp->xvflag[CARRY] = _mm_setzero_si128();
	4901	m_xvflag[ZERO] = m_xvflag[CARRY] = _mm_setzero_si128();
4873	4902	}
4874	4903
	4904	static void void cfunc_rsp_vlt_simd(void *param)
	4905	{
	4906	((rsp_device *)param)->ccfunc_rsp_vlt_simd();
	4907	}
4875	4908	#endif
4876	4909
4877	4910	#if (!USE_SIMD || SIMUL_SIMD)
4878	4911
4879		INLINE void cfunc_rsp_vlt_scalar(void *param)
	4912	inline void rsp_device::ccfunc_rsp_vlt_scalar()
4880	4913	{
4881		rsp_state *rsp = (rsp_state*)param;
4882		int op = rsp->impstate->arg0;
	4914	int op = m_rsp_state->arg0;
4883	4915
4884	4916	CLEAR_COMPARE_FLAGS();
4885	4917	CLEAR_CLIP2_FLAGS();
r31833	r31834
4897	4929	}
4898	4930	else if (s1 == s2)
4899	4931	{
4900		if (ZERO_FLAG(rsp, i) != 0 && CARRY_FLAG(rsp, i) != 0)
	4932	if (ZERO_FLAG(i) != 0 && CARRY_FLAG(i) != 0)
4901	4933	{
4902	4934	SET_COMPARE_FLAG(i);
4903	4935	}
4904	4936	}
4905	4937
4906		if (COMPARE_FLAG(rsp, i) != 0)
	4938	if (COMPARE_FLAG(i) != 0)
4907	4939	{
4908	4940	vres[i] = s1;
4909	4941	}
r31833	r31834
4919	4951	CLEAR_CARRY_FLAGS();
4920	4952	WRITEBACK_RESULT();
4921	4953	}
	4954
	4955	static void cfunc_rsp_vlt_scalar(void *param)
	4956	{
	4957	((rsp_device *)param)->ccfunc_rsp_vlt_scalar();
	4958	}
4922	4959	#endif
4923	4960
4924	4961	#if USE_SIMD
r31833	r31834
4932	4969	// Sets compare flags if elements in VS1 are equal with VS2
4933	4970	// Moves the element in VS2 to destination vector
4934	4971
4935		INLINE void cfunc_rsp_veq_simd(void *param)
	4972	inline void rsp_device::ccfunc_rsp_veq_simd()
4936	4973	{
4937		rsp_state *rsp = (rsp_state*)param;
4938		int op = rsp->impstate->arg0;
	4974	int op = m_rsp_state->arg0;
4939	4975
4940		rsp->xvflag[COMPARE] = rsp->xvflag[CLIP2] = _mm_setzero_si128();
	4976	m_xvflag[COMPARE] = m_xvflag[CLIP2] = _mm_setzero_si128();
4941	4977
4942		__m128i shuf = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
4943		__m128i zero_mask = _mm_cmpeq_epi16(rsp->xvflag[ZERO], _mm_setzero_si128());
4944		__m128i eq_mask = _mm_cmpeq_epi16(rsp->xv[VS1REG], shuf);
	4978	__m128i shuf = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
	4979	__m128i zero_mask = _mm_cmpeq_epi16(m_xvflag[ZERO], _mm_setzero_si128());
	4980	__m128i eq_mask = _mm_cmpeq_epi16(m_xv[VS1REG], shuf);
4945	4981
4946		rsp->xvflag[COMPARE] = _mm_and_si128(zero_mask, eq_mask);
	4982	m_xvflag[COMPARE] = _mm_and_si128(zero_mask, eq_mask);
4947	4983
4948		__m128i result = _mm_and_si128(rsp->xv[VS1REG], rsp->xvflag[COMPARE]);
4949		rsp->accum_l = rsp->xv[VDREG] = _mm_or_si128(result, _mm_and_si128(shuf, _mm_xor_si128(rsp->xvflag[COMPARE], vec_neg1)));
	4984	__m128i result = _mm_and_si128(m_xv[VS1REG], m_xvflag[COMPARE]);
	4985	m_accum_l = m_xv[VDREG] = _mm_or_si128(result, _mm_and_si128(shuf, _mm_xor_si128(m_xvflag[COMPARE], vec_neg1)));
4950	4986
4951		rsp->xvflag[ZERO] = rsp->xvflag[CARRY] = _mm_setzero_si128();
	4987	m_xvflag[ZERO] = m_xvflag[CARRY] = _mm_setzero_si128();
4952	4988	}
4953	4989
	4990	static void cfunc_rsp_veq_simd(void *param)
	4991	{
	4992	((rsp_device *)param)->ccfunc_rsp_veq_simd();
	4993	}
4954	4994	#endif
4955	4995
4956	4996	#if (!USE_SIMD || SIMUL_SIMD)
4957	4997
4958		INLINE void cfunc_rsp_veq_scalar(void *param)
	4998	inline void rsp_device::ccfunc_rsp_veq_scalar()
4959	4999	{
4960		rsp_state *rsp = (rsp_state*)param;
4961		int op = rsp->impstate->arg0;
	5000	int op = m_rsp_state->arg0;
4962	5001
4963	5002	CLEAR_COMPARE_FLAGS();
4964	5003	CLEAR_CLIP2_FLAGS();
r31833	r31834
4970	5009	SCALAR_GET_VS1(s1, i);
4971	5010	SCALAR_GET_VS2(s2, i);
4972	5011
4973		if ((s1 == s2) && ZERO_FLAG(rsp, i) == 0)
	5012	if ((s1 == s2) && ZERO_FLAG(i) == 0)
4974	5013	{
4975	5014	SET_COMPARE_FLAG(i);
4976	5015	vres[i] = s1;
r31833	r31834
4987	5026	CLEAR_CARRY_FLAGS();
4988	5027	WRITEBACK_RESULT();
4989	5028	}
	5029
	5030	static void cfunc_rsp_veq_scalar(void *param)
	5031	{
	5032	((rsp_device *)param)->ccfunc_rsp_veq_scalar();
	5033	}
4990	5034	#endif
4991	5035
4992	5036	#if USE_SIMD
r31833	r31834
5000	5044	// Sets compare flags if elements in VS1 are not equal with VS2
5001	5045	// Moves the element in VS2 to destination vector
5002	5046
5003		INLINE void cfunc_rsp_vne_simd(void *param)
	5047	inline void rsp_device::ccfunc_rsp_vne_simd()
5004	5048	{
5005		rsp_state *rsp = (rsp_state*)param;
5006		int op = rsp->impstate->arg0;
	5049	int op = m_rsp_state->arg0;
5007	5050
5008		rsp->xvflag[COMPARE] = rsp->xvflag[CLIP2] = _mm_setzero_si128();
	5051	m_xvflag[COMPARE] = m_xvflag[CLIP2] = _mm_setzero_si128();
5009	5052
5010		__m128i shuf = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
5011		__m128i neq_mask = _mm_xor_si128(_mm_cmpeq_epi16(rsp->xv[VS1REG], shuf), vec_neg1);
	5053	__m128i shuf = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
	5054	__m128i neq_mask = _mm_xor_si128(_mm_cmpeq_epi16(m_xv[VS1REG], shuf), vec_neg1);
5012	5055
5013		rsp->xvflag[COMPARE] = _mm_or_si128(rsp->xvflag[ZERO], neq_mask);
	5056	m_xvflag[COMPARE] = _mm_or_si128(m_xvflag[ZERO], neq_mask);
5014	5057
5015		__m128i result = _mm_and_si128(rsp->xv[VS1REG], rsp->xvflag[COMPARE]);
5016		rsp->accum_l = rsp->xv[VDREG] = _mm_or_si128(result, _mm_and_si128(shuf, _mm_xor_si128(rsp->xvflag[COMPARE], vec_neg1)));
	5058	__m128i result = _mm_and_si128(m_xv[VS1REG], m_xvflag[COMPARE]);
	5059	m_accum_l = m_xv[VDREG] = _mm_or_si128(result, _mm_and_si128(shuf, _mm_xor_si128(m_xvflag[COMPARE], vec_neg1)));
5017	5060
5018		rsp->xvflag[ZERO] = rsp->xvflag[CARRY] = _mm_setzero_si128();
	5061	m_xvflag[ZERO] = m_xvflag[CARRY] = _mm_setzero_si128();
5019	5062	}
5020	5063
	5064	static void cfunc_rsp_vne_simd(void *param)
	5065	{
	5066	((rsp_device *)param)->ccfunc_rsp_vne_simd();
	5067	}
5021	5068	#endif
5022	5069
5023	5070	#if (!USE_SIMD || SIMUL_SIMD)
5024	5071
5025		INLINE void cfunc_rsp_vne_scalar(void *param)
	5072	inline void rsp_device::ccfunc_rsp_vne_scalar()
5026	5073	{
5027		rsp_state *rsp = (rsp_state*)param;
5028		int op = rsp->impstate->arg0;
	5074	int op = m_rsp_state->arg0;
5029	5075
5030	5076	CLEAR_COMPARE_FLAGS();
5031	5077	CLEAR_CLIP2_FLAGS();
r31833	r31834
5037	5083	SCALAR_GET_VS1(s1, i);
5038	5084	SCALAR_GET_VS2(s2, i);
5039	5085
5040		if (s1 != s2 || ZERO_FLAG(rsp, i) != 0)
	5086	if (s1 != s2 || ZERO_FLAG(i) != 0)
5041	5087	{
5042	5088	SET_COMPARE_FLAG(i);
5043	5089	vres[i] = s1;
r31833	r31834
5054	5100	CLEAR_CARRY_FLAGS();
5055	5101	WRITEBACK_RESULT();
5056	5102	}
	5103
	5104	static void cfunc_rsp_vne_scalar(void *param)
	5105	{
	5106	((rsp_device *)param)->ccfunc_rsp_vne_scalar();
	5107	}
5057	5108	#endif
5058	5109
5059	5110	#if USE_SIMD
r31833	r31834
5067	5118	// Sets compare flags if elements in VS1 are greater or equal with VS2
5068	5119	// Moves the element in VS2 to destination vector
5069	5120
5070		INLINE void cfunc_rsp_vge_simd(void *param)
	5121	inline void rsp_device::ccfunc_rsp_vge_simd()
5071	5122	{
5072		rsp_state *rsp = (rsp_state*)param;
5073		int op = rsp->impstate->arg0;
	5123	int op = m_rsp_state->arg0;
5074	5124
5075		rsp->xvflag[COMPARE] = rsp->xvflag[CLIP2] = _mm_setzero_si128();
	5125	m_xvflag[COMPARE] = m_xvflag[CLIP2] = _mm_setzero_si128();
5076	5126
5077		__m128i shuf = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
5078		__m128i zero_mask = _mm_cmpeq_epi16(rsp->xvflag[ZERO], _mm_setzero_si128());
5079		__m128i carry_mask = _mm_cmpeq_epi16(rsp->xvflag[CARRY], _mm_setzero_si128());
	5127	__m128i shuf = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
	5128	__m128i zero_mask = _mm_cmpeq_epi16(m_xvflag[ZERO], _mm_setzero_si128());
	5129	__m128i carry_mask = _mm_cmpeq_epi16(m_xvflag[CARRY], _mm_setzero_si128());
5080	5130	__m128i flag_mask = _mm_or_si128(zero_mask, carry_mask);
5081		__m128i eq_mask = _mm_and_si128(_mm_cmpeq_epi16(rsp->xv[VS1REG], shuf), flag_mask);
5082		__m128i gt_mask = _mm_cmpgt_epi16(rsp->xv[VS1REG], shuf);
5083		rsp->xvflag[COMPARE] = _mm_or_si128(eq_mask, gt_mask);
	5131	__m128i eq_mask = _mm_and_si128(_mm_cmpeq_epi16(m_xv[VS1REG], shuf), flag_mask);
	5132	__m128i gt_mask = _mm_cmpgt_epi16(m_xv[VS1REG], shuf);
	5133	m_xvflag[COMPARE] = _mm_or_si128(eq_mask, gt_mask);
5084	5134
5085		__m128i result = _mm_and_si128(rsp->xv[VS1REG], rsp->xvflag[COMPARE]);
5086		rsp->accum_l = rsp->xv[VDREG] = _mm_or_si128(result, _mm_and_si128(shuf, _mm_xor_si128(rsp->xvflag[COMPARE], vec_neg1)));
	5135	__m128i result = _mm_and_si128(m_xv[VS1REG], m_xvflag[COMPARE]);
	5136	m_accum_l = m_xv[VDREG] = _mm_or_si128(result, _mm_and_si128(shuf, _mm_xor_si128(m_xvflag[COMPARE], vec_neg1)));
5087	5137
5088		rsp->xvflag[ZERO] = rsp->xvflag[CARRY] = _mm_setzero_si128();
	5138	m_xvflag[ZERO] = m_xvflag[CARRY] = _mm_setzero_si128();
5089	5139	}
5090	5140
	5141	static void cfunc_rsp_vge_simd(void *param)
	5142	{
	5143	((rsp_device *)param)->ccfunc_rsp_vge_simd();
	5144	}
5091	5145	#endif
5092	5146
5093	5147	#if (!USE_SIMD || SIMUL_SIMD)
5094	5148
5095		INLINE void cfunc_rsp_vge_scalar(void *param)
	5149	inline void rsp_device::ccfunc_rsp_vge_scalar()
5096	5150	{
5097		rsp_state *rsp = (rsp_state*)param;
5098		int op = rsp->impstate->arg0;
	5151	int op = m_rsp_state->arg0;
5099	5152
5100	5153	CLEAR_COMPARE_FLAGS();
5101	5154	CLEAR_CLIP2_FLAGS();
r31833	r31834
5106	5159	INT16 s1, s2;
5107	5160	SCALAR_GET_VS1(s1, i);
5108	5161	SCALAR_GET_VS2(s2, i);
5109		if ((s1 == s2 && (ZERO_FLAG(rsp, i) == 0 || CARRY_FLAG(rsp, i) == 0)) || s1 > s2)
	5162	if ((s1 == s2 && (ZERO_FLAG(i) == 0 || CARRY_FLAG(i) == 0)) || s1 > s2)
5110	5163	{
5111	5164	SET_COMPARE_FLAG(i);
5112	5165	vres[i] = s1;
r31833	r31834
5123	5176	CLEAR_CARRY_FLAGS();
5124	5177	WRITEBACK_RESULT();
5125	5178	}
	5179
	5180	static void cfunc_rsp_vge_scalar(void *param)
	5181	{
	5182	((rsp_device *)param)->ccfunc_rsp_vge_scalar();
	5183	}
5126	5184	#endif
5127	5185
5128	5186	#if USE_SIMD
r31833	r31834
5135	5193	//
5136	5194	// Vector clip low
5137	5195
5138		INLINE void cfunc_rsp_vcl_simd(void *param)
	5196	inline void rsp_device::ccfunc_rsp_vcl_simd()
5139	5197	{
5140		rsp_state *rsp = (rsp_state*)param;
5141		int op = rsp->impstate->arg0;
	5198	int op = m_rsp_state->arg0;
5142	5199	INT16 vres[8];
5143	5200
5144	5201	for (int i = 0; i < 8; i++)
r31833	r31834
5147	5204	VEC_GET_SCALAR_VS1(s1, i);
5148	5205	VEC_GET_SCALAR_VS2(s2, i);
5149	5206
5150		if (VEC_CARRY_FLAG(rsp, i) != 0)
	5207	if (VEC_CARRY_FLAG(i) != 0)
5151	5208	{
5152		if (VEC_ZERO_FLAG(rsp, i) != 0)
	5209	if (VEC_ZERO_FLAG(i) != 0)
5153	5210	{
5154		if (VEC_COMPARE_FLAG(rsp, i) != 0)
	5211	if (VEC_COMPARE_FLAG(i) != 0)
5155	5212	{
5156	5213	VEC_SET_ACCUM_L(-(UINT16)s2, i);
5157	5214	}
r31833	r31834
5160	5217	VEC_SET_ACCUM_L(s1, i);
5161	5218	}
5162	5219	}
5163		else//VEC_ZERO_FLAG(rsp, i)==0
	5220	else//VEC_ZERO_FLAG(i)==0
5164	5221	{
5165		if (VEC_CLIP1_FLAG(rsp, i) != 0)
	5222	if (VEC_CLIP1_FLAG(i) != 0)
5166	5223	{
5167	5224	if (((UINT32)(UINT16)(s1) + (UINT32)(UINT16)(s2)) > 0x10000)
5168	5225	{//proper fix for Harvest Moon 64, r4
r31833	r31834
5190	5247	}
5191	5248	}
5192	5249	}
5193		else//VEC_CARRY_FLAG(rsp, i)==0
	5250	else//VEC_CARRY_FLAG(i)==0
5194	5251	{
5195		if (VEC_ZERO_FLAG(rsp, i) != 0)
	5252	if (VEC_ZERO_FLAG(i) != 0)
5196	5253	{
5197		if (VEC_CLIP2_FLAG(rsp, i) != 0)
	5254	if (VEC_CLIP2_FLAG(i) != 0)
5198	5255	{
5199	5256	VEC_SET_ACCUM_L(s2, i);
5200	5257	}
r31833	r31834
5217	5274	}
5218	5275	}
5219	5276	}
5220		vres[i] = VEC_ACCUM_L(rsp, i);
	5277	vres[i] = VEC_ACCUM_L(i);
5221	5278	}
5222	5279	VEC_CLEAR_ZERO_FLAGS();
5223	5280	VEC_CLEAR_CARRY_FLAGS();
r31833	r31834
5225	5282	VEC_WRITEBACK_RESULT();
5226	5283	}
5227	5284
	5285	static void cfunc_rsp_vcl_simd(void *param)
	5286	{
	5287	((rsp_device *)param)->ccfunc_rsp_vcl_simd();
	5288	}
5228	5289	#endif
5229	5290
5230	5291	#if (!USE_SIMD || SIMUL_SIMD)
5231	5292
5232		INLINE void cfunc_rsp_vcl_scalar(void *param)
	5293	inline void rsp_device::ccfunc_rsp_vcl_scalar()
5233	5294	{
5234		rsp_state *rsp = (rsp_state*)param;
5235		int op = rsp->impstate->arg0;
	5295	int op = m_rsp_state->arg0;
5236	5296	INT16 vres[8];
5237	5297
5238	5298	for (int i = 0; i < 8; i++)
r31833	r31834
5241	5301	SCALAR_GET_VS1(s1, i);
5242	5302	SCALAR_GET_VS2(s2, i);
5243	5303
5244		if (CARRY_FLAG(rsp, i) != 0)
	5304	if (CARRY_FLAG(i) != 0)
5245	5305	{
5246		if (ZERO_FLAG(rsp, i) != 0)
	5306	if (ZERO_FLAG(i) != 0)
5247	5307	{
5248		if (COMPARE_FLAG(rsp, i) != 0)
	5308	if (COMPARE_FLAG(i) != 0)
5249	5309	{
5250	5310	SET_ACCUM_L(-(UINT16)s2, i);
5251	5311	}
r31833	r31834
5254	5314	SET_ACCUM_L(s1, i);
5255	5315	}
5256	5316	}
5257		else//ZERO_FLAG(rsp, i)==0
	5317	else//ZERO_FLAG(i)==0
5258	5318	{
5259		if (CLIP1_FLAG(rsp, i) != 0)
	5319	if (CLIP1_FLAG(i) != 0)
5260	5320	{
5261	5321	if (((UINT32)(UINT16)(s1) + (UINT32)(UINT16)(s2)) > 0x10000)
5262	5322	{//proper fix for Harvest Moon 64, r4
r31833	r31834
5284	5344	}
5285	5345	}
5286	5346	}
5287		else//CARRY_FLAG(rsp, i)==0
	5347	else//CARRY_FLAG(i)==0
5288	5348	{
5289		if (ZERO_FLAG(rsp, i) != 0)
	5349	if (ZERO_FLAG(i) != 0)
5290	5350	{
5291		if (CLIP2_FLAG(rsp, i) != 0)
	5351	if (CLIP2_FLAG(i) != 0)
5292	5352	{
5293	5353	SET_ACCUM_L(s2, i);
5294	5354	}
r31833	r31834
5311	5371	}
5312	5372	}
5313	5373	}
5314		vres[i] = ACCUM_L(rsp, i);
	5374	vres[i] = ACCUM_L(i);
5315	5375	}
5316	5376	CLEAR_ZERO_FLAGS();
5317	5377	CLEAR_CARRY_FLAGS();
5318	5378	CLEAR_CLIP1_FLAGS();
5319	5379	WRITEBACK_RESULT();
5320	5380	}
	5381
	5382	static void cfunc_rsp_vcl_scalar(void *param)
	5383	{
	5384	((rsp_device *)param)->ccfunc_rsp_vcl_scalar();
	5385	}
5321	5386	#endif
5322	5387
5323	5388	#if USE_SIMD
r31833	r31834
5330	5395	//
5331	5396	// Vector clip high
5332	5397
5333		INLINE void cfunc_rsp_vch_simd(void *param)
	5398	inline void rsp_device::ccfunc_rsp_vch_simd()
5334	5399	{
5335		rsp_state *rsp = (rsp_state*)param;
5336		int op = rsp->impstate->arg0;
	5400	int op = m_rsp_state->arg0;
5337	5401
5338	5402	VEC_CLEAR_CARRY_FLAGS();
5339	5403	VEC_CLEAR_COMPARE_FLAGS();
r31833	r31834
5364	5428	// accum set to s1 if (s1 ^ s2) < 0 && (s1 + s2) > 0)
5365	5429	// accum set to s1 if (s1 ^ s2) >= 0 && (s1 - s2) < 0
5366	5430
5367		__m128i shuf = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
5368		__m128i s1_xor_s2 = _mm_xor_si128(rsp->xv[VS1REG], shuf);
5369		__m128i s1_plus_s2 = _mm_add_epi16(rsp->xv[VS1REG], shuf);
5370		__m128i s1_sub_s2 = _mm_sub_epi16(rsp->xv[VS1REG], shuf);
	5431	__m128i shuf = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
	5432	__m128i s1_xor_s2 = _mm_xor_si128(m_xv[VS1REG], shuf);
	5433	__m128i s1_plus_s2 = _mm_add_epi16(m_xv[VS1REG], shuf);
	5434	__m128i s1_sub_s2 = _mm_sub_epi16(m_xv[VS1REG], shuf);
5371	5435	__m128i s2_neg = _mm_xor_si128(shuf, vec_neg1);
5372	5436
5373	5437	__m128i s2_lz = _mm_cmplt_epi16(shuf, _mm_setzero_si128());
r31833	r31834
5380	5444	__m128i s1s2_sub_nz = _mm_xor_si128(_mm_cmpeq_epi16(s1_sub_s2, _mm_setzero_si128()), vec_neg1);
5381	5445	__m128i s1s2_sub_lz = _mm_cmplt_epi16(s1_sub_s2, _mm_setzero_si128());
5382	5446	__m128i s1s2_sub_gez = _mm_xor_si128(s1s2_sub_lz, vec_neg1);
5383		__m128i s1_nens2 = _mm_xor_si128(_mm_cmpeq_epi16(rsp->xv[VS1REG], s2_neg), vec_neg1);
	5447	__m128i s1_nens2 = _mm_xor_si128(_mm_cmpeq_epi16(m_xv[VS1REG], s2_neg), vec_neg1);
5384	5448
5385	5449	__m128i ext_mask = _mm_and_si128(_mm_and_si128(s1s2_xor_lz, s1s2_plus_n1), vec_flagmask);
5386		rsp->flag[2] |= _mm_extract_epi16(ext_mask, 0) << 0;
5387		rsp->flag[2] |= _mm_extract_epi16(ext_mask, 1) << 1;
5388		rsp->flag[2] |= _mm_extract_epi16(ext_mask, 2) << 2;
5389		rsp->flag[2] |= _mm_extract_epi16(ext_mask, 3) << 3;
5390		rsp->flag[2] |= _mm_extract_epi16(ext_mask, 4) << 4;
5391		rsp->flag[2] |= _mm_extract_epi16(ext_mask, 5) << 5;
5392		rsp->flag[2] |= _mm_extract_epi16(ext_mask, 6) << 6;
5393		rsp->flag[2] |= _mm_extract_epi16(ext_mask, 7) << 7;
	5450	m_flag[2] |= _mm_extract_epi16(ext_mask, 0) << 0;
	5451	m_flag[2] |= _mm_extract_epi16(ext_mask, 1) << 1;
	5452	m_flag[2] |= _mm_extract_epi16(ext_mask, 2) << 2;
	5453	m_flag[2] |= _mm_extract_epi16(ext_mask, 3) << 3;
	5454	m_flag[2] |= _mm_extract_epi16(ext_mask, 4) << 4;
	5455	m_flag[2] |= _mm_extract_epi16(ext_mask, 5) << 5;
	5456	m_flag[2] |= _mm_extract_epi16(ext_mask, 6) << 6;
	5457	m_flag[2] |= _mm_extract_epi16(ext_mask, 7) << 7;
5394	5458
5395	5459	__m128i carry_mask = _mm_and_si128(s1s2_xor_lz, vec_flagmask);
5396		rsp->flag[0] |= _mm_extract_epi16(carry_mask, 0) << 0;
5397		rsp->flag[0] |= _mm_extract_epi16(carry_mask, 1) << 1;
5398		rsp->flag[0] |= _mm_extract_epi16(carry_mask, 2) << 2;
5399		rsp->flag[0] |= _mm_extract_epi16(carry_mask, 3) << 3;
5400		rsp->flag[0] |= _mm_extract_epi16(carry_mask, 4) << 4;
5401		rsp->flag[0] |= _mm_extract_epi16(carry_mask, 5) << 5;
5402		rsp->flag[0] |= _mm_extract_epi16(carry_mask, 6) << 6;
5403		rsp->flag[0] |= _mm_extract_epi16(carry_mask, 7) << 7;
	5460	m_flag[0] |= _mm_extract_epi16(carry_mask, 0) << 0;
	5461	m_flag[0] |= _mm_extract_epi16(carry_mask, 1) << 1;
	5462	m_flag[0] |= _mm_extract_epi16(carry_mask, 2) << 2;
	5463	m_flag[0] |= _mm_extract_epi16(carry_mask, 3) << 3;
	5464	m_flag[0] |= _mm_extract_epi16(carry_mask, 4) << 4;
	5465	m_flag[0] |= _mm_extract_epi16(carry_mask, 5) << 5;
	5466	m_flag[0] |= _mm_extract_epi16(carry_mask, 6) << 6;
	5467	m_flag[0] |= _mm_extract_epi16(carry_mask, 7) << 7;
5404	5468
5405	5469	__m128i z0_mask = _mm_and_si128(_mm_and_si128(s1s2_xor_gez, s1s2_sub_nz), s1_nens2);
5406	5470	__m128i z1_mask = _mm_and_si128(_mm_and_si128(s1s2_xor_lz, s1s2_plus_nz), s1_nens2);
r31833	r31834
5409	5473	z_mask = _mm_and_si128(_mm_or_si128(z_mask, _mm_srli_epi64(z_mask, 30)), vec_shiftmask4);
5410	5474	z_mask = _mm_or_si128(z_mask, _mm_srli_si128(z_mask, 7));
5411	5475	z_mask = _mm_or_si128(z_mask, _mm_srli_epi16(z_mask, 4));
5412		rsp->flag[0] |= (_mm_extract_epi16(z_mask, 0) << 8) & 0x00ff00;
	5476	m_flag[0] |= (_mm_extract_epi16(z_mask, 0) << 8) & 0x00ff00;
5413	5477
5414	5478	__m128i f0_mask = _mm_and_si128(_mm_or_si128(_mm_and_si128(s1s2_xor_gez, s2_lz),         _mm_and_si128(s1s2_xor_lz, s1s2_plus_lez)), vec_flagmask);
5415	5479	__m128i f8_mask = _mm_and_si128(_mm_or_si128(_mm_and_si128(s1s2_xor_gez, s1s2_sub_gez),  _mm_and_si128(s1s2_xor_lz, s2_lz)), vec_flagmask);
5416	5480	f0_mask = _mm_and_si128(f0_mask, vec_flagmask);
5417	5481	f8_mask = _mm_and_si128(f8_mask, vec_flagmask);
5418		rsp->flag[1] |= _mm_extract_epi16(f0_mask, 0) << 0;
5419		rsp->flag[1] |= _mm_extract_epi16(f0_mask, 1) << 1;
5420		rsp->flag[1] |= _mm_extract_epi16(f0_mask, 2) << 2;
5421		rsp->flag[1] |= _mm_extract_epi16(f0_mask, 3) << 3;
5422		rsp->flag[1] |= _mm_extract_epi16(f0_mask, 4) << 4;
5423		rsp->flag[1] |= _mm_extract_epi16(f0_mask, 5) << 5;
5424		rsp->flag[1] |= _mm_extract_epi16(f0_mask, 6) << 6;
5425		rsp->flag[1] |= _mm_extract_epi16(f0_mask, 7) << 7;
	5482	m_flag[1] |= _mm_extract_epi16(f0_mask, 0) << 0;
	5483	m_flag[1] |= _mm_extract_epi16(f0_mask, 1) << 1;
	5484	m_flag[1] |= _mm_extract_epi16(f0_mask, 2) << 2;
	5485	m_flag[1] |= _mm_extract_epi16(f0_mask, 3) << 3;
	5486	m_flag[1] |= _mm_extract_epi16(f0_mask, 4) << 4;
	5487	m_flag[1] |= _mm_extract_epi16(f0_mask, 5) << 5;
	5488	m_flag[1] |= _mm_extract_epi16(f0_mask, 6) << 6;
	5489	m_flag[1] |= _mm_extract_epi16(f0_mask, 7) << 7;
5426	5490
5427		rsp->flag[1] |= _mm_extract_epi16(f8_mask, 0) << 8;
5428		rsp->flag[1] |= _mm_extract_epi16(f8_mask, 1) << 9;
5429		rsp->flag[1] |= _mm_extract_epi16(f8_mask, 2) << 10;
5430		rsp->flag[1] |= _mm_extract_epi16(f8_mask, 3) << 11;
5431		rsp->flag[1] |= _mm_extract_epi16(f8_mask, 4) << 12;
5432		rsp->flag[1] |= _mm_extract_epi16(f8_mask, 5) << 13;
5433		rsp->flag[1] |= _mm_extract_epi16(f8_mask, 6) << 14;
5434		rsp->flag[1] |= _mm_extract_epi16(f8_mask, 7) << 15;
	5491	m_flag[1] |= _mm_extract_epi16(f8_mask, 0) << 8;
	5492	m_flag[1] |= _mm_extract_epi16(f8_mask, 1) << 9;
	5493	m_flag[1] |= _mm_extract_epi16(f8_mask, 2) << 10;
	5494	m_flag[1] |= _mm_extract_epi16(f8_mask, 3) << 11;
	5495	m_flag[1] |= _mm_extract_epi16(f8_mask, 4) << 12;
	5496	m_flag[1] |= _mm_extract_epi16(f8_mask, 5) << 13;
	5497	m_flag[1] |= _mm_extract_epi16(f8_mask, 6) << 14;
	5498	m_flag[1] |= _mm_extract_epi16(f8_mask, 7) << 15;
5435	5499	#endif
5436	5500	INT16 vres[8];
5437	5501	UINT32 vce = 0;
r31833	r31834
5496	5560	VEC_WRITEBACK_RESULT();
5497	5561	}
5498	5562
	5563	static void cfunc_rsp_vch_simd(void *param)
	5564	{
	5565	((rsp_device *)param)->ccfunc_rsp_vch_simd();
	5566	}
5499	5567	#endif
5500	5568
5501	5569	#if (!USE_SIMD || SIMUL_SIMD)
5502	5570
5503		INLINE void cfunc_rsp_vch_scalar(void *param)
	5571	inline void rsp_device::ccfunc_rsp_vch_scalar()
5504	5572	{
5505		rsp_state *rsp = (rsp_state*)param;
5506		int op = rsp->impstate->arg0;
	5573	int op = m_rsp_state->arg0;
5507	5574
5508	5575	CLEAR_CARRY_FLAGS();
5509	5576	CLEAR_COMPARE_FLAGS();
r31833	r31834
5573	5640	}
5574	5641	WRITEBACK_RESULT();
5575	5642	}
	5643
	5644	static void cfunc_rsp_vch_scalar(void *param)
	5645	{
	5646	((rsp_device *)param)->ccfunc_rsp_vch_scalar();
	5647	}
5576	5648	#endif
5577	5649
5578	5650	#if USE_SIMD
r31833	r31834
5585	5657	//
5586	5658	// Vector clip reverse
5587	5659
5588		INLINE void cfunc_rsp_vcr_simd(void *param)
	5660	inline void rsp_device::ccfunc_rsp_vcr_simd()
5589	5661	{
5590		rsp_state *rsp = (rsp_state*)param;
5591		int op = rsp->impstate->arg0;
	5662	int op = m_rsp_state->arg0;
5592	5663
5593	5664	VEC_CLEAR_CARRY_FLAGS();
5594	5665	VEC_CLEAR_COMPARE_FLAGS();
r31833	r31834
5608	5679
5609	5680	// accum set to s1 if (s1 ^ s2) < 0 && (s1 + s2) > 0)
5610	5681	// accum set to s1 if (s1 ^ s2) >= 0 && (s1 - s2) < 0
5611		__m128i shuf = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
5612		__m128i s1_xor_s2 = _mm_xor_si128(rsp->xv[VS1REG], shuf);
5613		__m128i s1_plus_s2 = _mm_add_epi16(rsp->xv[VS1REG], shuf);
5614		__m128i s1_sub_s2 = _mm_sub_epi16(rsp->xv[VS1REG], shuf);
	5682	__m128i shuf = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
	5683	__m128i s1_xor_s2 = _mm_xor_si128(m_xv[VS1REG], shuf);
	5684	__m128i s1_plus_s2 = _mm_add_epi16(m_xv[VS1REG], shuf);
	5685	__m128i s1_sub_s2 = _mm_sub_epi16(m_xv[VS1REG], shuf);
5615	5686	__m128i s2_neg = _mm_xor_si128(shuf, vec_neg1);
5616	5687
5617	5688	__m128i s2_lz = _mm_cmplt_epi16(shuf, _mm_setzero_si128());
r31833	r31834
5624	5695
5625	5696	__m128i s1_mask = _mm_or_si128(_mm_and_si128(s1s2_xor_gez, s1s2_sub_lz),   _mm_and_si128(s1s2_xor_lz, s1s2_plus_gz));
5626	5697	__m128i s2_mask = _mm_or_si128(_mm_and_si128(s1s2_xor_gez, s1s2_sub_gez),  _mm_and_si128(s1s2_xor_lz, s1s2_plus_lez));
5627		rsp->accum_l = _mm_or_si128(_mm_and_si128(rsp->xv[VS1REG], s1_mask), _mm_and_si128(s2_neg, s2_mask));
5628		rsp->xv[VDREG] = rsp->accum_l;
	5698	m_accum_l = _mm_or_si128(_mm_and_si128(m_xv[VS1REG], s1_mask), _mm_and_si128(s2_neg, s2_mask));
	5699	m_xv[VDREG] = m_accum_l;
5629	5700
5630		rsp->xvflag[COMPARE] = _mm_or_si128(_mm_and_si128(s1s2_xor_gez, s2_lz),         _mm_and_si128(s1s2_xor_lz, s1s2_plus_lez));
5631		rsp->xvflag[CLIP2] = _mm_or_si128(_mm_and_si128(s1s2_xor_gez, s1s2_sub_gez),  _mm_and_si128(s1s2_xor_lz, s2_lz));
	5701	m_xvflag[COMPARE] = _mm_or_si128(_mm_and_si128(s1s2_xor_gez, s2_lz),         _mm_and_si128(s1s2_xor_lz, s1s2_plus_lez));
	5702	m_xvflag[CLIP2] = _mm_or_si128(_mm_and_si128(s1s2_xor_gez, s1s2_sub_gez),  _mm_and_si128(s1s2_xor_lz, s2_lz));
5632	5703	#endif
5633	5704	INT16 vres[8];
5634	5705	for (int i = 0; i < 8; i++)
r31833	r31834
5670	5741	}
5671	5742	}
5672	5743
5673		vres[i] = VEC_ACCUM_L(rsp, i);
	5744	vres[i] = VEC_ACCUM_L(i);
5674	5745	}
5675	5746	VEC_WRITEBACK_RESULT();
5676	5747	}
5677	5748
	5749	static void cfunc_rsp_vcr_simd(void *param)
	5750	{
	5751	((rsp_device *)param)->ccfunc_rsp_vcr_simd();
	5752	}
5678	5753	#endif
5679	5754
5680	5755	#if (!USE_SIMD || SIMUL_SIMD)
5681	5756
5682		INLINE void cfunc_rsp_vcr_scalar(void *param)
	5757	inline void rsp_device::ccfunc_rsp_vcr_scalar()
5683	5758	{
5684		rsp_state *rsp = (rsp_state*)param;
5685		int op = rsp->impstate->arg0;
	5759	int op = m_rsp_state->arg0;
5686	5760
5687	5761	CLEAR_CARRY_FLAGS();
5688	5762	CLEAR_COMPARE_FLAGS();
r31833	r31834
5730	5804	}
5731	5805	}
5732	5806
5733		vres[i] = ACCUM_L(rsp, i);
	5807	vres[i] = ACCUM_L(i);
5734	5808	}
5735	5809	WRITEBACK_RESULT();
5736	5810	}
	5811
	5812	static void cfunc_rsp_vcr_scalar(void *param)
	5813	{
	5814	((rsp_device *)param)->ccfunc_rsp_vcr_scalar();
	5815	}
5737	5816	#endif
5738	5817
5739	5818	#if USE_SIMD
r31833	r31834
5746	5825	//
5747	5826	// Merges two vectors according to compare flags
5748	5827
5749		INLINE void cfunc_rsp_vmrg_simd(void *param)
	5828	inline void rsp_device::ccfunc_rsp_vmrg_simd()
5750	5829	{
5751		rsp_state *rsp = (rsp_state*)param;
5752		int op = rsp->impstate->arg0;
	5830	int op = m_rsp_state->arg0;
5753	5831
5754		__m128i shuf = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
5755		__m128i s2mask = _mm_cmpeq_epi16(rsp->xvflag[COMPARE], _mm_setzero_si128());
	5832	__m128i shuf = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
	5833	__m128i s2mask = _mm_cmpeq_epi16(m_xvflag[COMPARE], _mm_setzero_si128());
5756	5834	__m128i s1mask = _mm_xor_si128(s2mask, vec_neg1);
5757		__m128i result = _mm_and_si128(rsp->xv[VS1REG], s1mask);
5758		rsp->xv[VDREG] = _mm_or_si128(result, _mm_and_si128(shuf, s2mask));
5759		rsp->accum_l = rsp->xv[VDREG];
	5835	__m128i result = _mm_and_si128(m_xv[VS1REG], s1mask);
	5836	m_xv[VDREG] = _mm_or_si128(result, _mm_and_si128(shuf, s2mask));
	5837	m_accum_l = m_xv[VDREG];
5760	5838	}
5761	5839
	5840	static void cfunc_rsp_vmrg_simd(void *param)
	5841	{
	5842	((rsp_device *)param)->ccfunc_rsp_vmrg_simd();
	5843	}
5762	5844	#endif
5763	5845
5764	5846	#if (!USE_SIMD || SIMUL_SIMD)
5765	5847
5766		INLINE void cfunc_rsp_vmrg_scalar(void *param)
	5848	inline void rsp_device::ccfunc_rsp_vmrg_scalar()
5767	5849	{
5768		rsp_state *rsp = (rsp_state*)param;
5769		int op = rsp->impstate->arg0;
	5850	int op = m_rsp_state->arg0;
5770	5851
5771	5852	INT16 vres[8];
5772	5853	for (int i = 0; i < 8; i++)
r31833	r31834
5774	5855	INT16 s1, s2;
5775	5856	SCALAR_GET_VS1(s1, i);
5776	5857	SCALAR_GET_VS2(s2, i);
5777		if (COMPARE_FLAG(rsp, i) != 0)
	5858	if (COMPARE_FLAG(i) != 0)
5778	5859	{
5779	5860	vres[i] = s1;
5780	5861	}
r31833	r31834
5787	5868	}
5788	5869	WRITEBACK_RESULT();
5789	5870	}
	5871
	5872	static void cfunc_rsp_vmrg_scalar(void *param)
	5873	{
	5874	((rsp_device *)param)->ccfunc_rsp_vmrg_scalar();
	5875	}
5790	5876	#endif
5791	5877
5792	5878	#if USE_SIMD
r31833	r31834
5799	5885	//
5800	5886	// Bitwise AND of two vector registers
5801	5887
5802		INLINE void cfunc_rsp_vand_simd(void *param)
	5888	inline void rsp_device::ccfunc_rsp_vand_simd()
5803	5889	{
5804		rsp_state *rsp = (rsp_state*)param;
5805		int op = rsp->impstate->arg0;
	5890	int op = m_rsp_state->arg0;
5806	5891
5807		__m128i shuf = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
5808		rsp->xv[VDREG] = _mm_and_si128(rsp->xv[VS1REG], shuf);
5809		rsp->accum_l = rsp->xv[VDREG];
	5892	__m128i shuf = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
	5893	m_xv[VDREG] = _mm_and_si128(m_xv[VS1REG], shuf);
	5894	m_accum_l = m_xv[VDREG];
5810	5895	}
5811	5896
	5897	static void cfunc_rsp_vand_simd(void *param)
	5898	{
	5899	((rsp_device *)param)->ccfunc_rsp_vand_simd();
	5900	}
5812	5901	#endif
5813	5902
5814	5903	#if (!USE_SIMD || SIMUL_SIMD)
5815	5904
5816		INLINE void cfunc_rsp_vand_scalar(void *param)
	5905	inline void rsp_device::ccfunc_rsp_vand_scalar()
5817	5906	{
5818		rsp_state *rsp = (rsp_state*)param;
5819		int op = rsp->impstate->arg0;
	5907	int op = m_rsp_state->arg0;
5820	5908
5821	5909	INT16 vres[8];
5822	5910	for (int i = 0; i < 8; i++)
r31833	r31834
5829	5917	}
5830	5918	WRITEBACK_RESULT();
5831	5919	}
	5920
	5921	static void cfunc_rsp_vand_scalar(void *param)
	5922	{
	5923	((rsp_device *)param)->ccfunc_rsp_vand_scalar();
	5924	}
5832	5925	#endif
5833	5926
5834	5927	#if USE_SIMD
r31833	r31834
5841	5934	//
5842	5935	// Bitwise NOT AND of two vector registers
5843	5936
5844		INLINE void cfunc_rsp_vnand_simd(void *param)
	5937	inline void rsp_device::ccfunc_rsp_vnand_simd()
5845	5938	{
5846		rsp_state *rsp = (rsp_state*)param;
5847		int op = rsp->impstate->arg0;
	5939	int op = m_rsp_state->arg0;
5848	5940
5849		__m128i shuf = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
5850		rsp->xv[VDREG] = _mm_xor_si128(_mm_and_si128(rsp->xv[VS1REG], shuf), vec_neg1);
5851		rsp->accum_l = rsp->xv[VDREG];
	5941	__m128i shuf = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
	5942	m_xv[VDREG] = _mm_xor_si128(_mm_and_si128(m_xv[VS1REG], shuf), vec_neg1);
	5943	m_accum_l = m_xv[VDREG];
5852	5944	}
5853	5945
	5946	static void cfunc_rsp_vnand_simd(void *param)
	5947	{
	5948	((rsp_device *)param)->ccfunc_rsp_vnand_simd();
	5949	}
5854	5950	#endif
5855	5951
5856	5952	#if (!USE_SIMD || SIMUL_SIMD)
5857	5953
5858		INLINE void cfunc_rsp_vnand_scalar(void *param)
	5954	inline void rsp_device::ccfunc_rsp_vnand_scalar()
5859	5955	{
5860		rsp_state *rsp = (rsp_state*)param;
5861		int op = rsp->impstate->arg0;
	5956	int op = m_rsp_state->arg0;
5862	5957
5863	5958	INT16 vres[8];
5864	5959	for (int i = 0; i < 8; i++)
r31833	r31834
5871	5966	}
5872	5967	WRITEBACK_RESULT();
5873	5968	}
	5969
	5970	static void cfunc_rsp_vnand_scalar(void *param)
	5971	{
	5972	((rsp_device *)param)->ccfunc_rsp_vnand_scalar();
	5973	}
5874	5974	#endif
5875	5975
5876	5976	#if USE_SIMD
r31833	r31834
5883	5983	//
5884	5984	// Bitwise OR of two vector registers
5885	5985
5886		INLINE void cfunc_rsp_vor_simd(void *param)
	5986	inline void rsp_device::ccfunc_rsp_vor_simd()
5887	5987	{
5888		rsp_state *rsp = (rsp_state*)param;
5889		int op = rsp->impstate->arg0;
	5988	int op = m_rsp_state->arg0;
5890	5989
5891		__m128i shuf = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
5892		rsp->xv[VDREG] = _mm_or_si128(rsp->xv[VS1REG], shuf);
5893		rsp->accum_l = rsp->xv[VDREG];
	5990	__m128i shuf = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
	5991	m_xv[VDREG] = _mm_or_si128(m_xv[VS1REG], shuf);
	5992	m_accum_l = m_xv[VDREG];
5894	5993	}
5895	5994
	5995	static void cfunc_rsp_vor_simd(void *param)
	5996	{
	5997	((rsp_device *)param)->ccfunc_rsp_vor_simd();
	5998	}
5896	5999	#endif
5897	6000
5898	6001	#if (!USE_SIMD || SIMUL_SIMD)
5899	6002
5900		INLINE void cfunc_rsp_vor_scalar(void *param)
	6003	inline void rsp_device::ccfunc_rsp_vor_scalar()
5901	6004	{
5902		rsp_state *rsp = (rsp_state*)param;
5903		int op = rsp->impstate->arg0;
	6005	int op = m_rsp_state->arg0;
5904	6006
5905	6007	INT16 vres[8];
5906	6008	for (int i = 0; i < 8; i++)
r31833	r31834
5913	6015	}
5914	6016	WRITEBACK_RESULT();
5915	6017	}
	6018
	6019	static void cfunc_rsp_vor_scalar(void *param)
	6020	{
	6021	((rsp_device *)param)->ccfunc_rsp_vor_scalar();
	6022	}
5916	6023	#endif
5917	6024
5918	6025	#if USE_SIMD
r31833	r31834
5925	6032	//
5926	6033	// Bitwise NOT OR of two vector registers
5927	6034
5928		INLINE void cfunc_rsp_vnor_simd(void *param)
	6035	inline void rsp_device::ccfunc_rsp_vnor_simd()
5929	6036	{
5930		rsp_state *rsp = (rsp_state*)param;
5931		int op = rsp->impstate->arg0;
	6037	int op = m_rsp_state->arg0;
5932	6038
5933		__m128i shuf = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
5934		rsp->xv[VDREG] = _mm_xor_si128(_mm_or_si128(rsp->xv[VS1REG], shuf), vec_neg1);
5935		rsp->accum_l = rsp->xv[VDREG];
	6039	__m128i shuf = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
	6040	m_xv[VDREG] = _mm_xor_si128(_mm_or_si128(m_xv[VS1REG], shuf), vec_neg1);
	6041	m_accum_l = m_xv[VDREG];
5936	6042	}
5937	6043
	6044	static void cfunc_rsp_vnor_simd(void *param)
	6045	{
	6046	((rsp_device *)param)->ccfunc_rsp_vnor_simd();
	6047	}
5938	6048	#endif
5939	6049
5940	6050	#if (!USE_SIMD || SIMUL_SIMD)
5941	6051
5942		INLINE void cfunc_rsp_vnor_scalar(void *param)
	6052	inline void rsp_device::ccfunc_rsp_vnor_scalar()
5943	6053	{
5944		rsp_state *rsp = (rsp_state*)param;
5945		int op = rsp->impstate->arg0;
	6054	int op = m_rsp_state->arg0;
5946	6055
5947	6056	INT16 vres[8];
5948	6057	for (int i = 0; i < 8; i++)
r31833	r31834
5955	6064	}
5956	6065	WRITEBACK_RESULT();
5957	6066	}
	6067
	6068	static void cfunc_rsp_vnor_scalar(void *param)
	6069	{
	6070	((rsp_device *)param)->ccfunc_rsp_vnor_scalar();
	6071	}
5958	6072	#endif
5959	6073
5960	6074	#if USE_SIMD
r31833	r31834
5967	6081	//
5968	6082	// Bitwise XOR of two vector registers
5969	6083
5970		INLINE void cfunc_rsp_vxor_simd(void *param)
	6084	inline void rsp_device::ccfunc_rsp_vxor_simd()
5971	6085	{
5972		rsp_state *rsp = (rsp_state*)param;
5973		int op = rsp->impstate->arg0;
	6086	int op = m_rsp_state->arg0;
5974	6087
5975		__m128i shuf = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
5976		rsp->xv[VDREG] = _mm_xor_si128(rsp->xv[VS1REG], shuf);
5977		rsp->accum_l = rsp->xv[VDREG];
	6088	__m128i shuf = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
	6089	m_xv[VDREG] = _mm_xor_si128(m_xv[VS1REG], shuf);
	6090	m_accum_l = m_xv[VDREG];
5978	6091	}
5979	6092
	6093	static void cfunc_rsp_vxor_simd(void *param)
	6094	{
	6095	((rsp_device *)param)->ccfunc_rsp_vxor_simd();
	6096	}
5980	6097	#endif
5981	6098
5982	6099	#if (!USE_SIMD || SIMUL_SIMD)
5983	6100
5984		INLINE void cfunc_rsp_vxor_scalar(void *param)
	6101	inline void rsp_device::ccfunc_rsp_vxor_scalar()
5985	6102	{
5986		rsp_state *rsp = (rsp_state*)param;
5987		int op = rsp->impstate->arg0;
	6103	int op = m_rsp_state->arg0;
5988	6104
5989	6105	INT16 vres[8];
5990	6106	for (int i = 0; i < 8; i++)
r31833	r31834
5997	6113	}
5998	6114	WRITEBACK_RESULT();
5999	6115	}
	6116
	6117	static void cfunc_rsp_vxor_scalar(void *param)
	6118	{
	6119	((rsp_device *)param)->ccfunc_rsp_vxor_scalar();
	6120	}
6000	6121	#endif
6001	6122
6002	6123	#if USE_SIMD
r31833	r31834
6009	6130	//
6010	6131	// Bitwise NOT XOR of two vector registers
6011	6132
6012		INLINE void cfunc_rsp_vnxor_simd(void *param)
	6133	inline void rsp_device::ccfunc_rsp_vnxor_simd()
6013	6134	{
6014		rsp_state *rsp = (rsp_state*)param;
6015		int op = rsp->impstate->arg0;
	6135	int op = m_rsp_state->arg0;
6016	6136
6017		__m128i shuf = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
6018		rsp->xv[VDREG] = _mm_xor_si128(_mm_xor_si128(rsp->xv[VS1REG], shuf), vec_neg1);
6019		rsp->accum_l = rsp->xv[VDREG];
	6137	__m128i shuf = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
	6138	m_xv[VDREG] = _mm_xor_si128(_mm_xor_si128(m_xv[VS1REG], shuf), vec_neg1);
	6139	m_accum_l = m_xv[VDREG];
6020	6140	}
6021	6141
	6142	static void cfunc_rsp_vnxor_simd(void *param)
	6143	{
	6144	((rsp_device *)param)->ccfunc_rsp_vnxor_simd();
	6145	}
6022	6146	#endif
6023	6147
6024	6148	#if (!USE_SIMD || SIMUL_SIMD)
6025	6149
6026		INLINE void cfunc_rsp_vnxor_scalar(void *param)
	6150	inline void rsp_device::ccfunc_rsp_vnxor_scalar()
6027	6151	{
6028		rsp_state *rsp = (rsp_state*)param;
6029		int op = rsp->impstate->arg0;
	6152	int op = m_rsp_state->arg0;
6030	6153
6031	6154	INT16 vres[8];
6032	6155	for (int i = 0; i < 8; i++)
r31833	r31834
6039	6162	}
6040	6163	WRITEBACK_RESULT();
6041	6164	}
	6165
	6166	static void cfunc_rsp_vnxor_scalar(void *param)
	6167	{
	6168	((rsp_device *)param)->ccfunc_rsp_vnxor_scalar();
	6169	}
6042	6170	#endif
6043	6171
6044	6172	#if USE_SIMD
r31833	r31834
6051	6179	//
6052	6180	// Calculates reciprocal
6053	6181
6054		INLINE void cfunc_rsp_vrcp_simd(void *param)
	6182	inline void rsp_device::ccfunc_rsp_vrcp_simd()
6055	6183	{
6056		rsp_state *rsp = (rsp_state*)param;
6057		int op = rsp->impstate->arg0;
	6184	int op = m_rsp_state->arg0;
6058	6185
6059	6186	INT32 shifter = 0;
6060	6187	UINT16 urec;
6061	6188	INT32 rec;
6062		SIMD_EXTRACT16(rsp->xv[VS2REG], urec, EL);
	6189	SIMD_EXTRACT16(m_xv[VS2REG], urec, EL);
6063	6190	rec = (INT16)urec;
6064	6191	INT32 datainput = (rec < 0) ? (-rec) : rec;
6065	6192	if (datainput)
r31833	r31834
6095	6222	}
6096	6223	rec = temp;
6097	6224
6098		rsp->reciprocal_res = rec;
6099		rsp->dp_allowed = 0;
	6225	m_reciprocal_res = rec;
	6226	m_dp_allowed = 0;
6100	6227
6101		SIMD_INSERT16(rsp->xv[VDREG], (UINT16)rec, VS1REG);
6102		rsp->accum_l = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
	6228	SIMD_INSERT16(m_xv[VDREG], (UINT16)rec, VS1REG);
	6229	m_accum_l = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
6103	6230	}
6104	6231
	6232	static void cfunc_rsp_vrcp_simd(void *param)
	6233	{
	6234	((rsp_device *)param)->ccfunc_rsp_vrcp_simd();
	6235	}
6105	6236	#endif
6106	6237
6107	6238	#if (!USE_SIMD || SIMUL_SIMD)
6108	6239
6109		INLINE void cfunc_rsp_vrcp_scalar(void *param)
	6240	inline void rsp_device::ccfunc_rsp_vrcp_scalar()
6110	6241	{
6111		rsp_state *rsp = (rsp_state*)param;
6112		int op = rsp->impstate->arg0;
	6242	int op = m_rsp_state->arg0;
6113	6243
6114	6244	INT32 shifter = 0;
6115	6245	INT32 rec = (INT16)(VREG_S(VS2REG, EL & 7));
r31833	r31834
6147	6277	}
6148	6278	rec = temp;
6149	6279
6150		rsp->reciprocal_res = rec;
6151		rsp->dp_allowed = 0;
	6280	m_reciprocal_res = rec;
	6281	m_dp_allowed = 0;
6152	6282
6153	6283	W_VREG_S(VDREG, VS1REG & 7) = (UINT16)rec;
6154	6284	for (int i = 0; i < 8; i++)
r31833	r31834
6156	6286	SET_ACCUM_L(VREG_S(VS2REG, VEC_EL_2(EL, i)), i);
6157	6287	}
6158	6288	}
	6289
	6290	static void cfunc_rsp_vrcp_scalar(void *param)
	6291	{
	6292	((rsp_device *)param)->ccfunc_rsp_vrcp_scalar();
	6293	}
6159	6294	#endif
6160	6295
6161	6296	#if USE_SIMD
r31833	r31834
6168	6303	//
6169	6304	// Calculates reciprocal low part
6170	6305
6171		INLINE void cfunc_rsp_vrcpl_simd(void *param)
	6306	inline void rsp_device::ccfunc_rsp_vrcpl_simd()
6172	6307	{
6173		rsp_state *rsp = (rsp_state*)param;
6174		int op = rsp->impstate->arg0;
	6308	int op = m_rsp_state->arg0;
6175	6309
6176	6310	#if SIMUL_SIMD
6177		rsp->old_reciprocal_res = rsp->reciprocal_res;
6178		rsp->old_reciprocal_high = rsp->reciprocal_high;
6179		rsp->old_dp_allowed = rsp->dp_allowed;
	6311	m_old_reciprocal_res = m_reciprocal_res;
	6312	m_old_reciprocal_high = m_reciprocal_high;
	6313	m_old_dp_allowed = m_dp_allowed;
6180	6314	#endif
6181	6315
6182	6316	INT32 shifter = 0;
6183	6317
6184	6318	UINT16 urec;
6185		SIMD_EXTRACT16(rsp->xv[VS2REG], urec, EL);
6186		INT32 rec = (urec | rsp->reciprocal_high);
	6319	SIMD_EXTRACT16(m_xv[VS2REG], urec, EL);
	6320	INT32 rec = (urec | m_reciprocal_high);
6187	6321
6188	6322	INT32 datainput = rec;
6189	6323
6190	6324	if (rec < 0)
6191	6325	{
6192		if (rsp->dp_allowed)
	6326	if (m_dp_allowed)
6193	6327	{
6194	6328	if (rec < -32768)
6195	6329	{
r31833	r31834
6220	6354	}
6221	6355	else
6222	6356	{
6223		if (rsp->dp_allowed)
	6357	if (m_dp_allowed)
6224	6358	{
6225	6359	shifter = 0;
6226	6360	}
r31833	r31834
6247	6381	}
6248	6382	rec = temp;
6249	6383
6250		rsp->reciprocal_res = rec;
6251		rsp->dp_allowed = 0;
	6384	m_reciprocal_res = rec;
	6385	m_dp_allowed = 0;
6252	6386
6253		SIMD_INSERT16(rsp->xv[VDREG], (UINT16)rec, VS1REG);
	6387	SIMD_INSERT16(m_xv[VDREG], (UINT16)rec, VS1REG);
6254	6388
6255	6389	for (int i = 0; i < 8; i++)
6256	6390	{
6257	6391	INT16 val;
6258		SIMD_EXTRACT16(rsp->xv[VS2REG], val, VEC_EL_2(EL, i));
	6392	SIMD_EXTRACT16(m_xv[VS2REG], val, VEC_EL_2(EL, i));
6259	6393	VEC_SET_ACCUM_L(val, i);
6260	6394	}
6261	6395	}
6262	6396
	6397	static void cfunc_rsp_vrcpl_simd(void *param)
	6398	{
	6399	((rsp_device *)param)->ccfunc_rsp_vrcpl_simd();
	6400	}
6263	6401	#endif
6264	6402
6265	6403	#if (!USE_SIMD || SIMUL_SIMD)
6266	6404
6267		INLINE void cfunc_rsp_vrcpl_scalar(void *param)
	6405	inline void rsp_device::ccfunc_rsp_vrcpl_scalar()
6268	6406	{
6269		rsp_state *rsp = (rsp_state*)param;
6270		int op = rsp->impstate->arg0;
	6407	int op = m_rsp_state->arg0;
6271	6408
6272	6409	INT32 shifter = 0;
6273		INT32 rec = ((UINT16)(VREG_S(VS2REG, EL & 7)) | rsp->reciprocal_high);
	6410	INT32 rec = ((UINT16)(VREG_S(VS2REG, EL & 7)) | m_reciprocal_high);
6274	6411	INT32 datainput = rec;
6275	6412
6276	6413	if (rec < 0)
6277	6414	{
6278		if (rsp->dp_allowed)
	6415	if (m_dp_allowed)
6279	6416	{
6280	6417	if (rec < -32768)
6281	6418	{
r31833	r31834
6306	6443	}
6307	6444	else
6308	6445	{
6309		if (rsp->dp_allowed)
	6446	if (m_dp_allowed)
6310	6447	{
6311	6448	shifter = 0;
6312	6449	}
r31833	r31834
6333	6470	}
6334	6471	rec = temp;
6335	6472
6336		rsp->reciprocal_res = rec;
6337		rsp->dp_allowed = 0;
	6473	m_reciprocal_res = rec;
	6474	m_dp_allowed = 0;
6338	6475
6339	6476	W_VREG_S(VDREG, VS1REG & 7) = (UINT16)rec;
6340	6477
r31833	r31834
6343	6480	SET_ACCUM_L(VREG_S(VS2REG, VEC_EL_2(EL, i)), i);
6344	6481	}
6345	6482	}
	6483
	6484	static void cfunc_rsp_vrcpl_scalar(void *param)
	6485	{
	6486	((rsp_device *)param)->ccfunc_rsp_vrcpl_scalar();
	6487	}
6346	6488	#endif
6347	6489
6348	6490	#if USE_SIMD
r31833	r31834
6355	6497	//
6356	6498	// Calculates reciprocal high part
6357	6499
6358		INLINE void cfunc_rsp_vrcph_simd(void *param)
	6500	inline void rsp_device::ccfunc_rsp_vrcph_simd()
6359	6501	{
6360		rsp_state *rsp = (rsp_state*)param;
6361		int op = rsp->impstate->arg0;
	6502	int op = m_rsp_state->arg0;
6362	6503
6363	6504	#if SIMUL_SIMD
6364		rsp->old_reciprocal_res = rsp->reciprocal_res;
6365		rsp->old_reciprocal_high = rsp->reciprocal_high;
6366		rsp->old_dp_allowed = rsp->dp_allowed;
	6505	m_old_reciprocal_res = m_reciprocal_res;
	6506	m_old_reciprocal_high = m_reciprocal_high;
	6507	m_old_dp_allowed = m_dp_allowed;
6367	6508	#endif
6368	6509
6369	6510	UINT16 rcph;
6370		SIMD_EXTRACT16(rsp->xv[VS2REG], rcph, EL);
6371		rsp->reciprocal_high = rcph << 16;
6372		rsp->dp_allowed = 1;
	6511	SIMD_EXTRACT16(m_xv[VS2REG], rcph, EL);
	6512	m_reciprocal_high = rcph << 16;
	6513	m_dp_allowed = 1;
6373	6514
6374		rsp->accum_l = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
	6515	m_accum_l = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
6375	6516
6376		SIMD_INSERT16(rsp->xv[VDREG], (INT16)(rsp->reciprocal_res >> 16), VS1REG);
	6517	SIMD_INSERT16(m_xv[VDREG], (INT16)(m_reciprocal_res >> 16), VS1REG);
6377	6518	}
6378	6519
	6520	static void cfunc_rsp_vrcph_simd(void *param)
	6521	{
	6522	((rsp_device *)param)->ccfunc_rsp_vrcph_simd();
	6523	}
6379	6524	#endif
6380	6525
6381	6526	#if (!USE_SIMD || SIMUL_SIMD)
6382	6527
6383		INLINE void cfunc_rsp_vrcph_scalar(void *param)
	6528	inline void rsp_device::ccfunc_rsp_vrcph_scalar()
6384	6529	{
6385		rsp_state *rsp = (rsp_state*)param;
6386		int op = rsp->impstate->arg0;
	6530	int op = m_rsp_state->arg0;
6387	6531
6388		rsp->reciprocal_high = (VREG_S(VS2REG, EL & 7)) << 16;
6389		rsp->dp_allowed = 1;
	6532	m_reciprocal_high = (VREG_S(VS2REG, EL & 7)) << 16;
	6533	m_dp_allowed = 1;
6390	6534
6391	6535	for (int i = 0; i < 8; i++)
6392	6536	{
6393	6537	SET_ACCUM_L(VREG_S(VS2REG, VEC_EL_2(EL, i)), i);
6394	6538	}
6395	6539
6396		W_VREG_S(VDREG, VS1REG & 7) = (INT16)(rsp->reciprocal_res >> 16);
	6540	W_VREG_S(VDREG, VS1REG & 7) = (INT16)(m_reciprocal_res >> 16);
6397	6541	}
	6542
	6543	static void cfunc_rsp_vrcph_scalar(void *param)
	6544	{
	6545	((rsp_device *)param)->ccfunc_rsp_vrcph_scalar();
	6546	}
6398	6547	#endif
6399	6548
6400	6549	#if USE_SIMD
r31833	r31834
6407	6556	//
6408	6557	// Moves element from vector to destination vector
6409	6558
6410		INLINE void cfunc_rsp_vmov_simd(void *param)
	6559	inline void rsp_device::ccfunc_rsp_vmov_simd()
6411	6560	{
6412		rsp_state *rsp = (rsp_state*)param;
6413		int op = rsp->impstate->arg0;
	6561	int op = m_rsp_state->arg0;
6414	6562
6415	6563	INT16 val;
6416		SIMD_EXTRACT16(rsp->xv[VS2REG], val, EL);
6417		SIMD_INSERT16(rsp->xv[VDREG], val, VS1REG);
6418		rsp->accum_l = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
	6564	SIMD_EXTRACT16(m_xv[VS2REG], val, EL);
	6565	SIMD_INSERT16(m_xv[VDREG], val, VS1REG);
	6566	m_accum_l = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
6419	6567	}
6420	6568
	6569	static void cfunc_rsp_vmov_simd(void *param)
	6570	{
	6571	((rsp_device *)param)->ccfunc_rsp_vmov_simd();
	6572	}
6421	6573	#endif
6422	6574
6423	6575	#if (!USE_SIMD || SIMUL_SIMD)
6424	6576
6425		INLINE void cfunc_rsp_vmov_scalar(void *param)
	6577	inline void rsp_device::ccfunc_rsp_vmov_scalar()
6426	6578	{
6427		rsp_state *rsp = (rsp_state*)param;
6428		int op = rsp->impstate->arg0;
	6579	int op = m_rsp_state->arg0;
6429	6580
6430	6581	W_VREG_S(VDREG, VS1REG & 7) = VREG_S(VS2REG, EL & 7);
6431	6582	for (int i = 0; i < 8; i++)
r31833	r31834
6434	6585	}
6435	6586	}
6436	6587
	6588	static void cfunc_rsp_vmov_scalar(void *param)
	6589	{
	6590	((rsp_device *)param)->ccfunc_rsp_vmov_scalar();
	6591	}
6437	6592	#endif
6438	6593
6439	6594	#if USE_SIMD
r31833	r31834
6446	6601	//
6447	6602	// Calculates reciprocal square-root low part
6448	6603
6449		INLINE void cfunc_rsp_vrsql_simd(void *param)
	6604	inline void rsp_device::ccfunc_rsp_vrsql_simd()
6450	6605	{
6451		rsp_state *rsp = (rsp_state*)param;
6452		int op = rsp->impstate->arg0;
	6606	int op = m_rsp_state->arg0;
6453	6607
6454	6608	#if SIMUL_SIMD
6455		rsp->old_reciprocal_res = rsp->reciprocal_res;
6456		rsp->old_reciprocal_high = rsp->reciprocal_high;
6457		rsp->old_dp_allowed = rsp->dp_allowed;
	6609	m_old_reciprocal_res = m_reciprocal_res;
	6610	m_old_reciprocal_high = m_reciprocal_high;
	6611	m_old_dp_allowed = m_dp_allowed;
6458	6612	#endif
6459	6613
6460	6614	INT32 shifter = 0;
6461	6615	UINT16 val;
6462		SIMD_EXTRACT16(rsp->xv[VS2REG], val, EL);
6463		INT32 rec = rsp->reciprocal_high | val;
	6616	SIMD_EXTRACT16(m_xv[VS2REG], val, EL);
	6617	INT32 rec = m_reciprocal_high | val;
6464	6618	INT32 datainput = rec;
6465	6619
6466	6620	if (rec < 0)
6467	6621	{
6468		if (rsp->dp_allowed)
	6622	if (m_dp_allowed)
6469	6623	{
6470	6624	if (rec < -32768)
6471	6625	{
r31833	r31834
6495	6649	}
6496	6650	else
6497	6651	{
6498		if (rsp->dp_allowed)
	6652	if (m_dp_allowed)
6499	6653	{
6500	6654	shifter = 0;
6501	6655	}
r31833	r31834
6524	6678	}
6525	6679	rec = temp;
6526	6680
6527		rsp->reciprocal_res = rec;
6528		rsp->dp_allowed = 0;
	6681	m_reciprocal_res = rec;
	6682	m_dp_allowed = 0;
6529	6683
6530		SIMD_INSERT16(rsp->xv[VDREG], (UINT16)rec, VS1REG);
6531		rsp->accum_l = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
	6684	SIMD_INSERT16(m_xv[VDREG], (UINT16)rec, VS1REG);
	6685	m_accum_l = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
6532	6686	}
6533	6687
	6688	static void cfunc_rsp_vrsql_simd(void *param)
	6689	{
	6690	((rsp_device *)param)->ccfunc_rsp_vrsql_simd();
	6691	}
6534	6692	#endif
6535	6693
6536	6694	#if (!USE_SIMD || SIMUL_SIMD)
6537	6695
6538		INLINE void cfunc_rsp_vrsql_scalar(void *param)
	6696	inline void rsp_device::ccfunc_rsp_vrsql_scalar()
6539	6697	{
6540		rsp_state *rsp = (rsp_state*)param;
6541		int op = rsp->impstate->arg0;
	6698	int op = m_rsp_state->arg0;
6542	6699
6543	6700	INT32 shifter = 0;
6544		INT32 rec = rsp->reciprocal_high | (UINT16)VREG_S(VS2REG, EL & 7);
	6701	INT32 rec = m_reciprocal_high | (UINT16)VREG_S(VS2REG, EL & 7);
6545	6702	INT32 datainput = rec;
6546	6703
6547	6704	if (rec < 0)
6548	6705	{
6549		if (rsp->dp_allowed)
	6706	if (m_dp_allowed)
6550	6707	{
6551	6708	if (rec < -32768)
6552	6709	{
r31833	r31834
6576	6733	}
6577	6734	else
6578	6735	{
6579		if (rsp->dp_allowed)
	6736	if (m_dp_allowed)
6580	6737	{
6581	6738	shifter = 0;
6582	6739	}
r31833	r31834
6605	6762	}
6606	6763	rec = temp;
6607	6764
6608		rsp->reciprocal_res = rec;
6609		rsp->dp_allowed = 0;
	6765	m_reciprocal_res = rec;
	6766	m_dp_allowed = 0;
6610	6767
6611	6768	W_VREG_S(VDREG, VS1REG & 7) = (UINT16)(rec & 0xffff);
6612	6769	for (int i = 0; i < 8; i++)
r31833	r31834
6614	6771	SET_ACCUM_L(VREG_S(VS2REG, VEC_EL_2(EL, i)), i);
6615	6772	}
6616	6773	}
	6774
	6775	static void cfunc_rsp_vrsql_scalar(void *param)
	6776	{
	6777	((rsp_device *)param)->ccfunc_rsp_vrsql_scalar();
	6778	}
6617	6779	#endif
6618	6780
6619	6781	#if USE_SIMD
r31833	r31834
6626	6788	//
6627	6789	// Calculates reciprocal square-root high part
6628	6790
6629		INLINE void cfunc_rsp_vrsqh_simd(void *param)
	6791	inline void rsp_device::ccfunc_rsp_vrsqh_simd()
6630	6792	{
6631		rsp_state *rsp = (rsp_state*)param;
6632		int op = rsp->impstate->arg0;
	6793	int op = m_rsp_state->arg0;
6633	6794
6634	6795	#if SIMUL_SIMD
6635		rsp->old_reciprocal_res = rsp->reciprocal_res;
6636		rsp->old_reciprocal_high = rsp->reciprocal_high;
6637		rsp->old_dp_allowed = rsp->dp_allowed;
	6796	m_old_reciprocal_res = m_reciprocal_res;
	6797	m_old_reciprocal_high = m_reciprocal_high;
	6798	m_old_dp_allowed = m_dp_allowed;
6638	6799	#endif
6639	6800
6640	6801	UINT16 val;
6641		SIMD_EXTRACT16(rsp->xv[VS2REG], val, EL);
6642		rsp->reciprocal_high = val << 16;
6643		rsp->dp_allowed = 1;
	6802	SIMD_EXTRACT16(m_xv[VS2REG], val, EL);
	6803	m_reciprocal_high = val << 16;
	6804	m_dp_allowed = 1;
6644	6805
6645		rsp->accum_l = _mm_shuffle_epi8(rsp->xv[VS2REG], vec_shuf_inverse[EL]);
	6806	m_accum_l = _mm_shuffle_epi8(m_xv[VS2REG], vec_shuf_inverse[EL]);
6646	6807
6647		SIMD_INSERT16(rsp->xv[VDREG], (INT16)(rsp->reciprocal_res >> 16), VS1REG); // store high part
	6808	SIMD_INSERT16(m_xv[VDREG], (INT16)(m_reciprocal_res >> 16), VS1REG); // store high part
6648	6809	}
6649	6810
	6811	static void cfunc_rsp_vrsqh_simd(void *param)
	6812	{
	6813	((rsp_device *)param)->ccfunc_rsp_vrsqh_simd();
	6814	}
6650	6815	#endif
6651	6816
6652	6817	#if (!USE_SIMD || SIMUL_SIMD)
6653	6818
6654		INLINE void cfunc_rsp_vrsqh_scalar(void *param)
	6819	inline void rsp_device::ccfunc_rsp_vrsqh_scalar()
6655	6820	{
6656		rsp_state *rsp = (rsp_state*)param;
6657		int op = rsp->impstate->arg0;
	6821	int op = m_rsp_state->arg0;
6658	6822
6659		rsp->reciprocal_high = (VREG_S(VS2REG, EL & 7)) << 16;
6660		rsp->dp_allowed = 1;
	6823	m_reciprocal_high = (VREG_S(VS2REG, EL & 7)) << 16;
	6824	m_dp_allowed = 1;
6661	6825
6662	6826	for (int i = 0; i < 8; i++)
6663	6827	{
6664	6828	SET_ACCUM_L(VREG_S(VS2REG, VEC_EL_2(EL, i)), i);
6665	6829	}
6666	6830
6667		W_VREG_S(VDREG, VS1REG & 7) = (INT16)(rsp->reciprocal_res >> 16);  // store high part
	6831	W_VREG_S(VDREG, VS1REG & 7) = (INT16)(m_reciprocal_res >> 16);  // store high part
6668	6832	}
	6833
	6834	static void cfunc_rsp_vrsqh_scalar(void *param)
	6835	{
	6836	((rsp_device *)param)->ccfunc_rsp_vrsqh_scalar();
	6837	}
6669	6838	#endif
6670	6839
6671	6840
6672		static void cfunc_sp_set_status_cb(void *param)
	6841	inline void rsp_device::ccfunc_sp_set_status_cb()
6673	6842	{
6674		rsp_state *rsp = (rsp_state*)param;
6675		(rsp->device->sp_set_status_func)(0, rsp->impstate->arg0, 0xffffffff);
	6843	m_sp_set_status_func(0, m_rsp_state->arg0, 0xffffffff);
6676	6844	}
6677	6845
6678		static CPU_EXECUTE( rsp )
	6846	void cfunc_sp_set_status_cb(void *param)
6679	6847	{
6680		rsp_state *rsp = get_safe_token(device);
6681		drcuml_state *drcuml = rsp->impstate->drcuml;
	6848	((rsp_device *)param)->ccfunc_sp_set_status_cb();
	6849	}
	6850
	6851	void rsp_device::execute_run_drc()
	6852	{
	6853	drcuml_state *drcuml = m_drcuml;
6682	6854	int execute_result;
6683	6855
6684	6856	/* reset the cache if dirty */
6685		if (rsp->impstate->cache_dirty)
6686		code_flush_cache(rsp);
6687		rsp->impstate->cache_dirty = FALSE;
	6857	if (m_cache_dirty)
	6858	code_flush_cache();
	6859	m_cache_dirty = FALSE;
6688	6860
6689	6861	/* execute */
6690	6862	do
6691	6863	{
6692		if( rsp->sr & ( RSP_STATUS_HALT | RSP_STATUS_BROKE ) )
	6864	if( m_sr & ( RSP_STATUS_HALT | RSP_STATUS_BROKE ) )
6693	6865	{
6694		rsp->icount = MIN(rsp->icount, 0);
	6866	m_rsp_state->icount = MIN(m_rsp_state->icount, 0);
6695	6867	break;
6696	6868	}
6697	6869
6698	6870	/* run as much as we can */
6699		execute_result = drcuml->execute(*rsp->impstate->entry);
	6871	execute_result = drcuml->execute(*m_entry);
6700	6872
6701	6873	/* if we need to recompile, do it */
6702	6874	if (execute_result == EXECUTE_MISSING_CODE)
6703	6875	{
6704		code_compile_block(rsp, rsp->pc);
	6876	code_compile_block(m_rsp_state->pc);
6705	6877	}
6706	6878	else if (execute_result == EXECUTE_UNMAPPED_CODE)
6707	6879	{
6708		fatalerror("Attempted to execute unmapped code at PC=%08X\n", rsp->pc);
	6880	fatalerror("Attempted to execute unmapped code at PC=%08X\n", m_rsp_state->pc);
6709	6881	}
6710	6882	else if (execute_result == EXECUTE_RESET_CACHE)
6711	6883	{
6712		code_flush_cache(rsp);
	6884	code_flush_cache();
6713	6885	}
6714	6886	} while (execute_result != EXECUTE_OUT_OF_CYCLES);
6715	6887	}
r31833	r31834
6723	6895	accessor to code_flush_cache
6724	6896	-------------------------------------------------*/
6725	6897
6726		void rspdrc_flush_drc_cache(device_t *device)
	6898	void rsp_device::rspdrc_flush_drc_cache()
6727	6899	{
6728		if (!device->machine().options().drc()) return;
6729		rsp_state *rsp = get_safe_token(device);
6730		rsp->impstate->cache_dirty = TRUE;
	6900	if (!machine().options().drc()) return;
	6901	m_cache_dirty = TRUE;
6731	6902	}
6732	6903
6733	6904	/*-------------------------------------------------
r31833	r31834
6735	6906	regenerate static code
6736	6907	-------------------------------------------------*/
6737	6908
6738		static void code_flush_cache(rsp_state *rsp)
	6909	void rsp_device::code_flush_cache()
6739	6910	{
6740	6911	/* empty the transient cache contents */
6741		rsp->impstate->drcuml->reset();
	6912	m_drcuml->reset();
6742	6913
6743	6914	try
6744	6915	{
6745	6916	/* generate the entry point and out-of-cycles handlers */
6746		static_generate_entry_point(rsp);
6747		static_generate_nocode_handler(rsp);
6748		static_generate_out_of_cycles(rsp);
	6917	static_generate_entry_point();
	6918	static_generate_nocode_handler();
	6919	static_generate_out_of_cycles();
6749	6920
6750	6921	/* add subroutines for memory accesses */
6751		static_generate_memory_accessor(rsp, 1, FALSE, "read8",       rsp->impstate->read8);
6752		static_generate_memory_accessor(rsp, 1, TRUE,  "write8",      rsp->impstate->write8);
6753		static_generate_memory_accessor(rsp, 2, FALSE, "read16",      rsp->impstate->read16);
6754		static_generate_memory_accessor(rsp, 2, TRUE,  "write16",     rsp->impstate->write16);
6755		static_generate_memory_accessor(rsp, 4, FALSE, "read32",      rsp->impstate->read32);
6756		static_generate_memory_accessor(rsp, 4, TRUE,  "write32",     rsp->impstate->write32);
	6922	static_generate_memory_accessor(1, FALSE, "read8",       m_read8);
	6923	static_generate_memory_accessor(1, TRUE,  "write8",      m_write8);
	6924	static_generate_memory_accessor(2, FALSE, "read16",      m_read16);
	6925	static_generate_memory_accessor(2, TRUE,  "write16",     m_write16);
	6926	static_generate_memory_accessor(4, FALSE, "read32",      m_read32);
	6927	static_generate_memory_accessor(4, TRUE,  "write32",     m_write32);
6757	6928	}
6758	6929	catch (drcuml_block::abort_compilation &)
6759	6930	{
r31833	r31834
6767	6938	given mode at the specified pc
6768	6939	-------------------------------------------------*/
6769	6940
6770		static void code_compile_block(rsp_state *rsp, offs_t pc)
	6941	void rsp_device::code_compile_block(offs_t pc)
6771	6942	{
6772		drcuml_state *drcuml = rsp->impstate->drcuml;
	6943	drcuml_state *drcuml = m_drcuml;
6773	6944	compiler_state compiler = { 0 };
6774	6945	const opcode_desc *seqhead, *seqlast;
6775	6946	const opcode_desc *desclist;
r31833	r31834
6779	6950	g_profiler.start(PROFILER_DRC_COMPILE);
6780	6951
6781	6952	/* get a description of this sequence */
6782		desclist = rsp->impstate->drcfe->describe_code(pc);
	6953	desclist = m_drcfe->describe_code(pc);
6783	6954
6784	6955	bool succeeded = false;
6785	6956	while (!succeeded)
r31833	r31834
6796	6967	UINT32 nextpc;
6797	6968
6798	6969	/* add a code log entry */
6799		if (LOG_UML)
	6970	if (RSP_LOG_UML)
6800	6971	block->append_comment("-------------------------");                 // comment
6801	6972
6802	6973	/* determine the last instruction in this sequence */
r31833	r31834
6821	6992	else
6822	6993	{
6823	6994	UML_LABEL(block, seqhead->pc | 0x80000000);                             // label   seqhead->pc
6824		UML_HASHJMP(block, 0, seqhead->pc, *rsp->impstate->nocode);
	6995	UML_HASHJMP(block, 0, seqhead->pc, *m_nocode);
6825	6996	// hashjmp <0>,seqhead->pc,nocode
6826	6997	continue;
6827	6998	}
6828	6999
6829	7000	/* validate this code block if we're not pointing into ROM */
6830		if (rsp->program->get_write_ptr(seqhead->physpc) != NULL)
6831		generate_checksum_block(rsp, block, &compiler, seqhead, seqlast);
	7001	if (m_program->get_write_ptr(seqhead->physpc) != NULL)
	7002	generate_checksum_block(block, &compiler, seqhead, seqlast);
6832	7003
6833	7004	/* label this instruction, if it may be jumped to locally */
6834	7005	if (seqhead->flags & OPFLAG_IS_BRANCH_TARGET)
r31833	r31834
6836	7007
6837	7008	/* iterate over instructions in the sequence and compile them */
6838	7009	for (curdesc = seqhead; curdesc != seqlast->next(); curdesc = curdesc->next())
6839		generate_sequence_instruction(rsp, block, &compiler, curdesc);
	7010	generate_sequence_instruction(block, &compiler, curdesc);
6840	7011
6841	7012	/* if we need to return to the start, do it */
6842	7013	if (seqlast->flags & OPFLAG_RETURN_TO_START)
r31833	r31834
6847	7018	nextpc = seqlast->pc + (seqlast->skipslots + 1) * 4;
6848	7019
6849	7020	/* count off cycles and go there */
6850		generate_update_cycles(rsp, block, &compiler, nextpc, TRUE);            // <subtract cycles>
	7021	generate_update_cycles(block, &compiler, nextpc, TRUE);            // <subtract cycles>
6851	7022
6852	7023	/* if the last instruction can change modes, use a variable mode; otherwise, assume the same mode */
6853	7024	if (seqlast->next() == NULL || seqlast->next()->pc != nextpc)
6854		UML_HASHJMP(block, 0, nextpc, *rsp->impstate->nocode);          // hashjmp <mode>,nextpc,nocode
	7025	UML_HASHJMP(block, 0, nextpc, *m_nocode);          // hashjmp <mode>,nextpc,nocode
6855	7026	}
6856	7027
6857	7028	/* end the sequence */
r31833	r31834
6861	7032	}
6862	7033	catch (drcuml_block::abort_compilation &)
6863	7034	{
6864		code_flush_cache(rsp);
	7035	code_flush_cache();
6865	7036	}
6866	7037	}
6867	7038	}
r31833	r31834
6875	7046	unimplemented opcdes
6876	7047	-------------------------------------------------*/
6877	7048
	7049	inline void rsp_device::ccfunc_unimplemented()
	7050	{
	7051	UINT32 opcode = m_rsp_state->arg0;
	7052	fatalerror("PC=%08X: Unimplemented op %08X (%02X,%02X)\n", m_rsp_state->pc, opcode, opcode >> 26, opcode & 0x3f);
	7053	}
	7054
6878	7055	static void cfunc_unimplemented(void *param)
6879	7056	{
6880		rsp_state *rsp = (rsp_state *)param;
6881		UINT32 opcode = rsp->impstate->arg0;
6882		fatalerror("PC=%08X: Unimplemented op %08X (%02X,%02X)\n", rsp->pc, opcode, opcode >> 26, opcode & 0x3f);
	7057	((rsp_device *)param)->ccfunc_unimplemented();
6883	7058	}
6884	7059
6885
6886	7060	/*-------------------------------------------------
6887	7061	cfunc_fatalerror - a generic fatalerror call
6888	7062	-------------------------------------------------*/
r31833	r31834
6904	7078	static entry point
6905	7079	-------------------------------------------------*/
6906	7080
6907		static void static_generate_entry_point(rsp_state *rsp)
	7081	void rsp_device::static_generate_entry_point()
6908	7082	{
6909		drcuml_state *drcuml = rsp->impstate->drcuml;
	7083	drcuml_state *drcuml = m_drcuml;
6910	7084	drcuml_block *block;
6911	7085
6912	7086	/* begin generating */
6913	7087	block = drcuml->begin_block(20);
6914	7088
6915	7089	/* forward references */
6916		alloc_handle(drcuml, &rsp->impstate->nocode, "nocode");
	7090	alloc_handle(drcuml, &m_nocode, "nocode");
6917	7091
6918		alloc_handle(drcuml, &rsp->impstate->entry, "entry");
6919		UML_HANDLE(block, *rsp->impstate->entry);                                       // handle  entry
	7092	alloc_handle(drcuml, &m_entry, "entry");
	7093	UML_HANDLE(block, *m_entry);                                       // handle  entry
6920	7094
6921	7095	/* load fast integer registers */
6922		load_fast_iregs(rsp, block);
	7096	load_fast_iregs(block);
6923	7097
6924	7098	/* generate a hash jump via the current mode and PC */
6925		UML_HASHJMP(block, 0, mem(&rsp->pc), *rsp->impstate->nocode);                   // hashjmp <mode>,<pc>,nocode
	7099	UML_HASHJMP(block, 0, mem(&m_rsp_state->pc), *m_nocode);                   // hashjmp <mode>,<pc>,nocode
6926	7100	block->end();
6927	7101	}
6928	7102
r31833	r31834
6932	7106	exception handler for "out of code"
6933	7107	-------------------------------------------------*/
6934	7108
6935		static void static_generate_nocode_handler(rsp_state *rsp)
	7109	void rsp_device::static_generate_nocode_handler()
6936	7110	{
6937		drcuml_state *drcuml = rsp->impstate->drcuml;
	7111	drcuml_state *drcuml = m_drcuml;
6938	7112	drcuml_block *block;
6939	7113
6940	7114	/* begin generating */
6941	7115	block = drcuml->begin_block(10);
6942	7116
6943	7117	/* generate a hash jump via the current mode and PC */
6944		alloc_handle(drcuml, &rsp->impstate->nocode, "nocode");
6945		UML_HANDLE(block, *rsp->impstate->nocode);                                      // handle  nocode
	7118	alloc_handle(drcuml, &m_nocode, "nocode");
	7119	UML_HANDLE(block, *m_nocode);                                      // handle  nocode
6946	7120	UML_GETEXP(block, I0);                                                      // getexp  i0
6947		UML_MOV(block, mem(&rsp->pc), I0);                                          // mov     [pc],i0
6948		save_fast_iregs(rsp, block);
	7121	UML_MOV(block, mem(&m_rsp_state->pc), I0);                                          // mov     [pc],i0
	7122	save_fast_iregs(block);
6949	7123	UML_EXIT(block, EXECUTE_MISSING_CODE);                                      // exit    EXECUTE_MISSING_CODE
6950	7124
6951	7125	block->end();
r31833	r31834
6957	7131	out of cycles exception handler
6958	7132	-------------------------------------------------*/
6959	7133
6960		static void static_generate_out_of_cycles(rsp_state *rsp)
	7134	void rsp_device::static_generate_out_of_cycles()
6961	7135	{
6962		drcuml_state *drcuml = rsp->impstate->drcuml;
	7136	drcuml_state *drcuml = m_drcuml;
6963	7137	drcuml_block *block;
6964	7138
6965	7139	/* begin generating */
6966	7140	block = drcuml->begin_block(10);
6967	7141
6968	7142	/* generate a hash jump via the current mode and PC */
6969		alloc_handle(drcuml, &rsp->impstate->out_of_cycles, "out_of_cycles");
6970		UML_HANDLE(block, *rsp->impstate->out_of_cycles);                               // handle  out_of_cycles
	7143	alloc_handle(drcuml, &m_out_of_cycles, "out_of_cycles");
	7144	UML_HANDLE(block, *m_out_of_cycles);                               // handle  out_of_cycles
6971	7145	UML_GETEXP(block, I0);                                                      // getexp  i0
6972		UML_MOV(block, mem(&rsp->pc), I0);                                          // mov     <pc>,i0
6973		save_fast_iregs(rsp, block);
	7146	UML_MOV(block, mem(&m_rsp_state->pc), I0);                                          // mov     <pc>,i0
	7147	save_fast_iregs(block);
6974	7148	UML_EXIT(block, EXECUTE_OUT_OF_CYCLES);                                 // exit    EXECUTE_OUT_OF_CYCLES
6975	7149
6976	7150	block->end();
r31833	r31834
6980	7154	static_generate_memory_accessor
6981	7155	------------------------------------------------------------------*/
6982	7156
6983		static void static_generate_memory_accessor(rsp_state *rsp, int size, int iswrite, const char *name, code_handle *&handleptr)
	7157	void rsp_device::static_generate_memory_accessor(int size, int iswrite, const char *name, code_handle *&handleptr)
6984	7158	{
6985	7159	/* on entry, address is in I0; data for writes is in I1 */
6986	7160	/* on exit, read result is in I0 */
6987	7161	/* routine trashes I0-I1 */
6988		drcuml_state *drcuml = rsp->impstate->drcuml;
	7162	drcuml_state *drcuml = m_drcuml;
6989	7163	drcuml_block *block;
6990	7164
6991	7165	/* begin generating */
r31833	r31834
7000	7174	{
7001	7175	if (size == 1)
7002	7176	{
7003		UML_MOV(block, mem(&rsp->impstate->arg0), I0);              // mov     [arg0],i0 ; address
7004		UML_MOV(block, mem(&rsp->impstate->arg1), I1);              // mov     [arg1],i1 ; data
7005		UML_CALLC(block, cfunc_write8, rsp);                            // callc   cfunc_write8
	7177	UML_MOV(block, mem(&m_rsp_state->arg0), I0);              // mov     [arg0],i0 ; address
	7178	UML_MOV(block, mem(&m_rsp_state->arg1), I1);              // mov     [arg1],i1 ; data
	7179	UML_CALLC(block, cfunc_write8, this);                            // callc   cfunc_write8
7006	7180	}
7007	7181	else if (size == 2)
7008	7182	{
7009		UML_MOV(block, mem(&rsp->impstate->arg0), I0);              // mov     [arg0],i0 ; address
7010		UML_MOV(block, mem(&rsp->impstate->arg1), I1);              // mov     [arg1],i1 ; data
7011		UML_CALLC(block, cfunc_write16, rsp);                           // callc   cfunc_write16
	7183	UML_MOV(block, mem(&m_rsp_state->arg0), I0);              // mov     [arg0],i0 ; address
	7184	UML_MOV(block, mem(&m_rsp_state->arg1), I1);              // mov     [arg1],i1 ; data
	7185	UML_CALLC(block, cfunc_write16, this);                           // callc   cfunc_write16
7012	7186	}
7013	7187	else if (size == 4)
7014	7188	{
7015		UML_MOV(block, mem(&rsp->impstate->arg0), I0);              // mov     [arg0],i0 ; address
7016		UML_MOV(block, mem(&rsp->impstate->arg1), I1);              // mov     [arg1],i1 ; data
7017		UML_CALLC(block, cfunc_write32, rsp);                           // callc   cfunc_write32
	7189	UML_MOV(block, mem(&m_rsp_state->arg0), I0);              // mov     [arg0],i0 ; address
	7190	UML_MOV(block, mem(&m_rsp_state->arg1), I1);              // mov     [arg1],i1 ; data
	7191	UML_CALLC(block, cfunc_write32, this);                           // callc   cfunc_write32
7018	7192	}
7019	7193	}
7020	7194	else
7021	7195	{
7022	7196	if (size == 1)
7023	7197	{
7024		UML_MOV(block, mem(&rsp->impstate->arg0), I0);          // mov     [arg0],i0 ; address
7025		UML_CALLC(block, cfunc_read8, rsp);                         // callc   cfunc_printf_debug
7026		UML_MOV(block, I0, mem(&rsp->impstate->arg0));          // mov     i0,[arg0],i0 ; result
	7198	UML_MOV(block, mem(&m_rsp_state->arg0), I0);          // mov     [arg0],i0 ; address
	7199	UML_CALLC(block, cfunc_read8, this);                         // callc   cfunc_printf_debug
	7200	UML_MOV(block, I0, mem(&m_rsp_state->arg0));          // mov     i0,[arg0],i0 ; result
7027	7201	}
7028	7202	else if (size == 2)
7029	7203	{
7030		UML_MOV(block, mem(&rsp->impstate->arg0), I0);          // mov     [arg0],i0 ; address
7031		UML_CALLC(block, cfunc_read16, rsp);                        // callc   cfunc_read16
7032		UML_MOV(block, I0, mem(&rsp->impstate->arg0));          // mov     i0,[arg0],i0 ; result
	7204	UML_MOV(block, mem(&m_rsp_state->arg0), I0);          // mov     [arg0],i0 ; address
	7205	UML_CALLC(block, cfunc_read16, this);                        // callc   cfunc_read16
	7206	UML_MOV(block, I0, mem(&m_rsp_state->arg0));          // mov     i0,[arg0],i0 ; result
7033	7207	}
7034	7208	else if (size == 4)
7035	7209	{
7036		UML_MOV(block, mem(&rsp->impstate->arg0), I0);          // mov     [arg0],i0 ; address
7037		UML_CALLC(block, cfunc_read32, rsp);                        // callc   cfunc_read32
7038		UML_MOV(block, I0, mem(&rsp->impstate->arg0));          // mov     i0,[arg0],i0 ; result
	7210	UML_MOV(block, mem(&m_rsp_state->arg0), I0);          // mov     [arg0],i0 ; address
	7211	UML_CALLC(block, cfunc_read32, this);                        // callc   cfunc_read32
	7212	UML_MOV(block, I0, mem(&m_rsp_state->arg0));          // mov     i0,[arg0],i0 ; result
7039	7213	}
7040	7214	}
7041	7215	UML_RET(block);
r31833	r31834
7054	7228	subtract cycles from the icount and generate
7055	7229	an exception if out
7056	7230	-------------------------------------------------*/
7057		static void generate_update_cycles(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, parameter param, int allow_exception)
	7231	void rsp_device::generate_update_cycles(drcuml_block *block, compiler_state *compiler, parameter param, int allow_exception)
7058	7232	{
7059	7233	/* account for cycles */
7060	7234	if (compiler->cycles > 0)
7061	7235	{
7062		UML_SUB(block, mem(&rsp->icount), mem(&rsp->icount), MAPVAR_CYCLES);        // sub     icount,icount,cycles
	7236	UML_SUB(block, mem(&m_rsp_state->icount), mem(&m_rsp_state->icount), MAPVAR_CYCLES);        // sub     icount,icount,cycles
7063	7237	UML_MAPVAR(block, MAPVAR_CYCLES, 0);                                        // mapvar  cycles,0
7064		UML_EXHc(block, COND_S, *rsp->impstate->out_of_cycles, param);
	7238	UML_EXHc(block, COND_S, *m_out_of_cycles, param);
7065	7239	}
7066	7240	compiler->cycles = 0;
7067	7241	}
r31833	r31834
7071	7245	validate a sequence of opcodes
7072	7246	-------------------------------------------------*/
7073	7247
7074		static void generate_checksum_block(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast)
	7248	void rsp_device::generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast)
7075	7249	{
7076	7250	const opcode_desc *curdesc;
7077		if (LOG_UML)
	7251	if (RSP_LOG_UML)
7078	7252	{
7079	7253	block->append_comment("[Validation for %08X]", seqhead->pc | 0x1000);       // comment
7080	7254	}
7081	7255	/* loose verify or single instruction: just compare and fail */
7082		if (!(rsp->impstate->drcoptions & RSPDRC_STRICT_VERIFY) || seqhead->next() == NULL)
	7256	if (!(m_drcoptions & RSPDRC_STRICT_VERIFY) || seqhead->next() == NULL)
7083	7257	{
7084	7258	if (!(seqhead->flags & OPFLAG_VIRTUAL_NOOP))
7085	7259	{
7086	7260	UINT32 sum = seqhead->opptr.l[0];
7087		void *base = rsp->direct->read_decrypted_ptr(seqhead->physpc | 0x1000);
	7261	void *base = m_direct->read_decrypted_ptr(seqhead->physpc | 0x1000);
7088	7262	UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4);                         // load    i0,base,0,dword
7089	7263
7090	7264	if (seqhead->delay.first() != NULL && seqhead->physpc != seqhead->delay.first()->physpc)
7091	7265	{
7092		base = rsp->direct->read_decrypted_ptr(seqhead->delay.first()->physpc | 0x1000);
	7266	base = m_direct->read_decrypted_ptr(seqhead->delay.first()->physpc | 0x1000);
7093	7267	UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4);                 // load    i1,base,dword
7094	7268	UML_ADD(block, I0, I0, I1);                     // add     i0,i0,i1
7095	7269
r31833	r31834
7097	7271	}
7098	7272
7099	7273	UML_CMP(block, I0, sum);                                    // cmp     i0,opptr[0]
7100		UML_EXHc(block, COND_NE, *rsp->impstate->nocode, epc(seqhead));     // exne    nocode,seqhead->pc
	7274	UML_EXHc(block, COND_NE, *m_nocode, epc(seqhead));     // exne    nocode,seqhead->pc
7101	7275	}
7102	7276	}
7103	7277
r31833	r31834
7105	7279	else
7106	7280	{
7107	7281	UINT32 sum = 0;
7108		void *base = rsp->direct->read_decrypted_ptr(seqhead->physpc | 0x1000);
	7282	void *base = m_direct->read_decrypted_ptr(seqhead->physpc | 0x1000);
7109	7283	UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4);                             // load    i0,base,0,dword
7110	7284	sum += seqhead->opptr.l[0];
7111	7285	for (curdesc = seqhead->next(); curdesc != seqlast->next(); curdesc = curdesc->next())
7112	7286	if (!(curdesc->flags & OPFLAG_VIRTUAL_NOOP))
7113	7287	{
7114		base = rsp->direct->read_decrypted_ptr(curdesc->physpc | 0x1000);
	7288	base = m_direct->read_decrypted_ptr(curdesc->physpc | 0x1000);
7115	7289	UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4);                     // load    i1,base,dword
7116	7290	UML_ADD(block, I0, I0, I1);                         // add     i0,i0,i1
7117	7291	sum += curdesc->opptr.l[0];
7118	7292
7119	7293	if (curdesc->delay.first() != NULL && (curdesc == seqlast || (curdesc->next() != NULL && curdesc->next()->physpc != curdesc->delay.first()->physpc)))
7120	7294	{
7121		base = rsp->direct->read_decrypted_ptr(curdesc->delay.first()->physpc | 0x1000);
	7295	base = m_direct->read_decrypted_ptr(curdesc->delay.first()->physpc | 0x1000);
7122	7296	UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4);                 // load    i1,base,dword
7123	7297	UML_ADD(block, I0, I0, I1);                     // add     i0,i0,i1
7124	7298
r31833	r31834
7126	7300	}
7127	7301	}
7128	7302	UML_CMP(block, I0, sum);                                            // cmp     i0,sum
7129		UML_EXHc(block, COND_NE, *rsp->impstate->nocode, epc(seqhead));         // exne    nocode,seqhead->pc
	7303	UML_EXHc(block, COND_NE, *m_nocode, epc(seqhead));         // exne    nocode,seqhead->pc
7130	7304	}
7131	7305	}
7132	7306
r31833	r31834
7136	7310	for a single instruction in a sequence
7137	7311	-------------------------------------------------*/
7138	7312
7139		static void generate_sequence_instruction(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
	7313	void rsp_device::generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
7140	7314	{
7141	7315	offs_t expc;
7142	7316
7143	7317	/* add an entry for the log */
7144		if (LOG_UML && !(desc->flags & OPFLAG_VIRTUAL_NOOP))
7145		log_add_disasm_comment(rsp, block, desc->pc, desc->opptr.l[0]);
	7318	if (RSP_LOG_UML && !(desc->flags & OPFLAG_VIRTUAL_NOOP))
	7319	log_add_disasm_comment(block, desc->pc, desc->opptr.l[0]);
7146	7320
7147	7321	/* set the PC map variable */
7148	7322	expc = (desc->flags & OPFLAG_IN_DELAY_SLOT) ? desc->pc - 3 : desc->pc;
r31833	r31834
7155	7329	UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles);                             // mapvar  CYCLES,compiler->cycles
7156	7330
7157	7331	/* if we are debugging, call the debugger */
7158		if ((rsp->device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
	7332	if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
7159	7333	{
7160		UML_MOV(block, mem(&rsp->pc), desc->pc);                                // mov     [pc],desc->pc
7161		save_fast_iregs(rsp, block);
	7334	UML_MOV(block, mem(&m_rsp_state->pc), desc->pc);                                // mov     [pc],desc->pc
	7335	save_fast_iregs(block);
7162	7336	UML_DEBUG(block, desc->pc);                                         // debug   desc->pc
7163	7337	}
7164	7338
r31833	r31834
7166	7340	#if 0
7167	7341	if (desc->flags & OPFLAG_COMPILER_UNMAPPED)
7168	7342	{
7169		UML_MOV(block, mem(&rsp->pc), desc->pc);                               // mov     [pc],desc->pc
7170		save_fast_iregs(rsp, block);
	7343	UML_MOV(block, mem(&m_rsp_state->pc), desc->pc);                               // mov     [pc],desc->pc
	7344	save_fast_iregs(block);
7171	7345	UML_EXIT(block, EXECUTE_UNMAPPED_CODE);                             // exit EXECUTE_UNMAPPED_CODE
7172	7346	}
7173	7347	#endif
r31833	r31834
7176	7350	/*else*/ if (!(desc->flags & OPFLAG_VIRTUAL_NOOP))
7177	7351	{
7178	7352	/* compile the instruction */
7179		if (!generate_opcode(rsp, block, compiler, desc))
	7353	if (!generate_opcode(block, compiler, desc))
7180	7354	{
7181		UML_MOV(block, mem(&rsp->pc), desc->pc);                            // mov     [pc],desc->pc
7182		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7183		UML_CALLC(block, cfunc_unimplemented, rsp);                             // callc   cfunc_unimplemented
	7355	UML_MOV(block, mem(&m_rsp_state->pc), desc->pc);                            // mov     [pc],desc->pc
	7356	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7357	UML_CALLC(block, cfunc_unimplemented, this);                             // callc   cfunc_unimplemented
7184	7358	}
7185	7359	}
7186	7360	}
r31833	r31834
7189	7363	generate_delay_slot_and_branch
7190	7364	------------------------------------------------------------------*/
7191	7365
7192		static void generate_delay_slot_and_branch(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 linkreg)
	7366	void rsp_device::generate_delay_slot_and_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 linkreg)
7193	7367	{
7194	7368	compiler_state compiler_temp = *compiler;
7195	7369	UINT32 op = desc->opptr.l[0];
r31833	r31834
7197	7371	/* fetch the target register if dynamic, in case it is modified by the delay slot */
7198	7372	if (desc->targetpc == BRANCH_TARGET_DYNAMIC)
7199	7373	{
7200		UML_AND(block, mem(&rsp->impstate->jmpdest), R32(RSREG), 0x00000fff);
7201		UML_OR(block, mem(&rsp->impstate->jmpdest), mem(&rsp->impstate->jmpdest), 0x1000);
	7374	UML_AND(block, mem(&m_rsp_state->jmpdest), R32(RSREG), 0x00000fff);
	7375	UML_OR(block, mem(&m_rsp_state->jmpdest), mem(&m_rsp_state->jmpdest), 0x1000);
7202	7376	}
7203	7377
7204	7378	/* set the link if needed -- before the delay slot */
r31833	r31834
7209	7383
7210	7384	/* compile the delay slot using temporary compiler state */
7211	7385	assert(desc->delay.first() != NULL);
7212		generate_sequence_instruction(rsp, block, &compiler_temp, desc->delay.first());     // <next instruction>
	7386	generate_sequence_instruction(block, &compiler_temp, desc->delay.first());     // <next instruction>
7213	7387
7214	7388	/* update the cycles and jump through the hash table to the target */
7215	7389	if (desc->targetpc != BRANCH_TARGET_DYNAMIC)
7216	7390	{
7217		generate_update_cycles(rsp, block, &compiler_temp, desc->targetpc, TRUE);   // <subtract cycles>
	7391	generate_update_cycles(block, &compiler_temp, desc->targetpc, TRUE);   // <subtract cycles>
7218	7392	if (desc->flags & OPFLAG_INTRABLOCK_BRANCH)
7219	7393	UML_JMP(block, desc->targetpc | 0x80000000);                            // jmp     desc->targetpc
7220	7394	else
7221		UML_HASHJMP(block, 0, desc->targetpc, *rsp->impstate->nocode);
	7395	UML_HASHJMP(block, 0, desc->targetpc, *m_nocode);
7222	7396	// hashjmp <mode>,desc->targetpc,nocode
7223	7397	}
7224	7398	else
7225	7399	{
7226		generate_update_cycles(rsp, block, &compiler_temp, mem(&rsp->impstate->jmpdest), TRUE);
	7400	generate_update_cycles(block, &compiler_temp, mem(&m_rsp_state->jmpdest), TRUE);
7227	7401	// <subtract cycles>
7228		UML_HASHJMP(block, 0, mem(&rsp->impstate->jmpdest), *rsp->impstate->nocode);
	7402	UML_HASHJMP(block, 0, mem(&m_rsp_state->jmpdest), *m_nocode);
7229	7403	// hashjmp <mode>,<rsreg>,nocode
7230	7404	}
7231	7405
r31833	r31834
7245	7419
7246	7420	#if USE_SIMD
7247	7421
7248		static int generate_vector_opcode(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
	7422	int rsp_device::generate_vector_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
7249	7423	{
7250	7424	UINT32 op = desc->opptr.l[0];
7251	7425	// Opcode legend:
r31833	r31834
7257	7431	switch (op & 0x3f)
7258	7432	{
7259	7433	case 0x00:      /* VMULF */
7260		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7261		UML_CALLC(block, cfunc_rsp_vmulf_simd, rsp);
	7434	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7435	UML_CALLC(block, cfunc_rsp_vmulf_simd, this);
7262	7436	#if SIMUL_SIMD
7263		UML_CALLC(block, cfunc_backup_regs, rsp);
7264		UML_CALLC(block, cfunc_rsp_vmulf_scalar, rsp);
7265		UML_CALLC(block, cfunc_restore_regs, rsp);
7266		UML_CALLC(block, cfunc_verify_regs, rsp);
	7437	UML_CALLC(block, cfunc_backup_regs, this);
	7438	UML_CALLC(block, cfunc_rsp_vmulf_scalar, this);
	7439	UML_CALLC(block, cfunc_restore_regs, this);
	7440	UML_CALLC(block, cfunc_verify_regs, this);
7267	7441	#endif
7268	7442	return TRUE;
7269	7443
7270	7444	case 0x01:      /* VMULU */
7271		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7272		UML_CALLC(block, cfunc_rsp_vmulu_simd, rsp);
	7445	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7446	UML_CALLC(block, cfunc_rsp_vmulu_simd, this);
7273	7447	#if SIMUL_SIMD
7274		UML_CALLC(block, cfunc_backup_regs, rsp);
7275		UML_CALLC(block, cfunc_rsp_vmulu_scalar, rsp);
7276		UML_CALLC(block, cfunc_restore_regs, rsp);
7277		UML_CALLC(block, cfunc_verify_regs, rsp);
	7448	UML_CALLC(block, cfunc_backup_regs, this);
	7449	UML_CALLC(block, cfunc_rsp_vmulu_scalar, this);
	7450	UML_CALLC(block, cfunc_restore_regs, this);
	7451	UML_CALLC(block, cfunc_verify_regs, this);
7278	7452	#endif
7279	7453	return TRUE;
7280	7454
7281	7455	case 0x04:      /* VMUDL */
7282		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7283		UML_CALLC(block, cfunc_rsp_vmudl_simd, rsp);
	7456	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7457	UML_CALLC(block, cfunc_rsp_vmudl_simd, this);
7284	7458	#if SIMUL_SIMD
7285		UML_CALLC(block, cfunc_backup_regs, rsp);
7286		UML_CALLC(block, cfunc_rsp_vmudl_scalar, rsp);
7287		UML_CALLC(block, cfunc_restore_regs, rsp);
7288		UML_CALLC(block, cfunc_verify_regs, rsp);
	7459	UML_CALLC(block, cfunc_backup_regs, this);
	7460	UML_CALLC(block, cfunc_rsp_vmudl_scalar, this);
	7461	UML_CALLC(block, cfunc_restore_regs, this);
	7462	UML_CALLC(block, cfunc_verify_regs, this);
7289	7463	#endif
7290	7464	return TRUE;
7291	7465
7292	7466	case 0x05:      /* VMUDM */
7293		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7294		UML_CALLC(block, cfunc_rsp_vmudm_simd, rsp);
	7467	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7468	UML_CALLC(block, cfunc_rsp_vmudm_simd, this);
7295	7469	#if SIMUL_SIMD
7296		UML_CALLC(block, cfunc_backup_regs, rsp);
7297		UML_CALLC(block, cfunc_rsp_vmudm_scalar, rsp);
7298		UML_CALLC(block, cfunc_restore_regs, rsp);
7299		UML_CALLC(block, cfunc_verify_regs, rsp);
	7470	UML_CALLC(block, cfunc_backup_regs, this);
	7471	UML_CALLC(block, cfunc_rsp_vmudm_scalar, this);
	7472	UML_CALLC(block, cfunc_restore_regs, this);
	7473	UML_CALLC(block, cfunc_verify_regs, this);
7300	7474	#endif
7301	7475	return TRUE;
7302	7476
7303	7477	case 0x06:      /* VMUDN */
7304		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7305		UML_CALLC(block, cfunc_rsp_vmudn_simd, rsp);
	7478	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7479	UML_CALLC(block, cfunc_rsp_vmudn_simd, this);
7306	7480	#if SIMUL_SIMD
7307		UML_CALLC(block, cfunc_backup_regs, rsp);
7308		UML_CALLC(block, cfunc_rsp_vmudn_scalar, rsp);
7309		UML_CALLC(block, cfunc_restore_regs, rsp);
7310		UML_CALLC(block, cfunc_verify_regs, rsp);
	7481	UML_CALLC(block, cfunc_backup_regs, this);
	7482	UML_CALLC(block, cfunc_rsp_vmudn_scalar, this);
	7483	UML_CALLC(block, cfunc_restore_regs, this);
	7484	UML_CALLC(block, cfunc_verify_regs, this);
7311	7485	#endif
7312	7486	return TRUE;
7313	7487
7314	7488	case 0x07:      /* VMUDH */
7315		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7316		UML_CALLC(block, cfunc_rsp_vmudh_simd, rsp);
	7489	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7490	UML_CALLC(block, cfunc_rsp_vmudh_simd, this);
7317	7491	#if SIMUL_SIMD
7318		UML_CALLC(block, cfunc_backup_regs, rsp);
7319		UML_CALLC(block, cfunc_rsp_vmudh_scalar, rsp);
7320		UML_CALLC(block, cfunc_restore_regs, rsp);
7321		UML_CALLC(block, cfunc_verify_regs, rsp);
	7492	UML_CALLC(block, cfunc_backup_regs, this);
	7493	UML_CALLC(block, cfunc_rsp_vmudh_scalar, this);
	7494	UML_CALLC(block, cfunc_restore_regs, this);
	7495	UML_CALLC(block, cfunc_verify_regs, this);
7322	7496	#endif
7323	7497	return TRUE;
7324	7498
7325	7499	case 0x08:      /* VMACF */
7326		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7327		UML_CALLC(block, cfunc_rsp_vmacf_simd, rsp);
	7500	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7501	UML_CALLC(block, cfunc_rsp_vmacf_simd, this);
7328	7502	#if SIMUL_SIMD
7329		UML_CALLC(block, cfunc_backup_regs, rsp);
7330		UML_CALLC(block, cfunc_rsp_vmacf_scalar, rsp);
7331		UML_CALLC(block, cfunc_restore_regs, rsp);
7332		UML_CALLC(block, cfunc_verify_regs, rsp);
	7503	UML_CALLC(block, cfunc_backup_regs, this);
	7504	UML_CALLC(block, cfunc_rsp_vmacf_scalar, this);
	7505	UML_CALLC(block, cfunc_restore_regs, this);
	7506	UML_CALLC(block, cfunc_verify_regs, this);
7333	7507	#endif
7334	7508	return TRUE;
7335	7509
7336	7510	case 0x09:      /* VMACU */
7337		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7338		UML_CALLC(block, cfunc_rsp_vmacu_simd, rsp);
	7511	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7512	UML_CALLC(block, cfunc_rsp_vmacu_simd, this);
7339	7513	#if SIMUL_SIMD
7340		UML_CALLC(block, cfunc_backup_regs, rsp);
7341		UML_CALLC(block, cfunc_rsp_vmacu_scalar, rsp);
7342		UML_CALLC(block, cfunc_restore_regs, rsp);
7343		UML_CALLC(block, cfunc_verify_regs, rsp);
	7514	UML_CALLC(block, cfunc_backup_regs, this);
	7515	UML_CALLC(block, cfunc_rsp_vmacu_scalar, this);
	7516	UML_CALLC(block, cfunc_restore_regs, this);
	7517	UML_CALLC(block, cfunc_verify_regs, this);
7344	7518	#endif
7345	7519	return TRUE;
7346	7520
7347	7521	case 0x0c:      /* VMADL */
7348		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7349		UML_CALLC(block, cfunc_rsp_vmadl_simd, rsp);
	7522	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7523	UML_CALLC(block, cfunc_rsp_vmadl_simd, this);
7350	7524	#if SIMUL_SIMD
7351		UML_CALLC(block, cfunc_backup_regs, rsp);
7352		UML_CALLC(block, cfunc_rsp_vmadl_scalar, rsp);
7353		UML_CALLC(block, cfunc_restore_regs, rsp);
7354		UML_CALLC(block, cfunc_verify_regs, rsp);
	7525	UML_CALLC(block, cfunc_backup_regs, this);
	7526	UML_CALLC(block, cfunc_rsp_vmadl_scalar, this);
	7527	UML_CALLC(block, cfunc_restore_regs, this);
	7528	UML_CALLC(block, cfunc_verify_regs, this);
7355	7529	#endif
7356	7530	return TRUE;
7357	7531
7358	7532	case 0x0d:      /* VMADM */
7359		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7360		UML_CALLC(block, cfunc_rsp_vmadm_simd, rsp);
	7533	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7534	UML_CALLC(block, cfunc_rsp_vmadm_simd, this);
7361	7535	#if SIMUL_SIMD
7362		UML_CALLC(block, cfunc_backup_regs, rsp);
7363		UML_CALLC(block, cfunc_rsp_vmadm_scalar, rsp);
7364		UML_CALLC(block, cfunc_restore_regs, rsp);
7365		UML_CALLC(block, cfunc_verify_regs, rsp);
	7536	UML_CALLC(block, cfunc_backup_regs, this);
	7537	UML_CALLC(block, cfunc_rsp_vmadm_scalar, this);
	7538	UML_CALLC(block, cfunc_restore_regs, this);
	7539	UML_CALLC(block, cfunc_verify_regs, this);
7366	7540	#endif
7367	7541	return TRUE;
7368	7542
7369	7543	case 0x0e:      /* VMADN */
7370		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7371		UML_CALLC(block, cfunc_rsp_vmadn_simd, rsp);
	7544	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7545	UML_CALLC(block, cfunc_rsp_vmadn_simd, this);
7372	7546	#if SIMUL_SIMD
7373		UML_CALLC(block, cfunc_backup_regs, rsp);
7374		UML_CALLC(block, cfunc_rsp_vmadn_scalar, rsp);
7375		UML_CALLC(block, cfunc_restore_regs, rsp);
7376		UML_CALLC(block, cfunc_verify_regs, rsp);
	7547	UML_CALLC(block, cfunc_backup_regs, this);
	7548	UML_CALLC(block, cfunc_rsp_vmadn_scalar, this);
	7549	UML_CALLC(block, cfunc_restore_regs, this);
	7550	UML_CALLC(block, cfunc_verify_regs, this);
7377	7551	#endif
7378	7552	return TRUE;
7379	7553
7380	7554	case 0x0f:      /* VMADH */
7381		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7382		UML_CALLC(block, cfunc_rsp_vmadh_simd, rsp);
	7555	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7556	UML_CALLC(block, cfunc_rsp_vmadh_simd, this);
7383	7557	#if SIMUL_SIMD
7384		UML_CALLC(block, cfunc_backup_regs, rsp);
7385		UML_CALLC(block, cfunc_rsp_vmadh_scalar, rsp);
7386		UML_CALLC(block, cfunc_restore_regs, rsp);
7387		UML_CALLC(block, cfunc_verify_regs, rsp);
	7558	UML_CALLC(block, cfunc_backup_regs, this);
	7559	UML_CALLC(block, cfunc_rsp_vmadh_scalar, this);
	7560	UML_CALLC(block, cfunc_restore_regs, this);
	7561	UML_CALLC(block, cfunc_verify_regs, this);
7388	7562	#endif
7389	7563	return TRUE;
7390	7564
7391	7565	case 0x10:      /* VADD */
7392		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7393		UML_CALLC(block, cfunc_rsp_vadd_simd, rsp);
	7566	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7567	UML_CALLC(block, cfunc_rsp_vadd_simd, this);
7394	7568	#if SIMUL_SIMD
7395		UML_CALLC(block, cfunc_backup_regs, rsp);
7396		UML_CALLC(block, cfunc_rsp_vadd_scalar, rsp);
7397		UML_CALLC(block, cfunc_restore_regs, rsp);
7398		UML_CALLC(block, cfunc_verify_regs, rsp);
	7569	UML_CALLC(block, cfunc_backup_regs, this);
	7570	UML_CALLC(block, cfunc_rsp_vadd_scalar, this);
	7571	UML_CALLC(block, cfunc_restore_regs, this);
	7572	UML_CALLC(block, cfunc_verify_regs, this);
7399	7573	#endif
7400	7574	return TRUE;
7401	7575
7402	7576	case 0x11:      /* VSUB */
7403		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7404		UML_CALLC(block, cfunc_rsp_vsub_simd, rsp);
	7577	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7578	UML_CALLC(block, cfunc_rsp_vsub_simd, this);
7405	7579	#if SIMUL_SIMD
7406		UML_CALLC(block, cfunc_backup_regs, rsp);
7407		UML_CALLC(block, cfunc_rsp_vsub_scalar, rsp);
7408		UML_CALLC(block, cfunc_restore_regs, rsp);
7409		UML_CALLC(block, cfunc_verify_regs, rsp);
	7580	UML_CALLC(block, cfunc_backup_regs, this);
	7581	UML_CALLC(block, cfunc_rsp_vsub_scalar, this);
	7582	UML_CALLC(block, cfunc_restore_regs, this);
	7583	UML_CALLC(block, cfunc_verify_regs, this);
7410	7584	#endif
7411	7585	return TRUE;
7412	7586
7413	7587	case 0x13:      /* VABS */
7414		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7415		UML_CALLC(block, cfunc_rsp_vabs_simd, rsp);
	7588	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7589	UML_CALLC(block, cfunc_rsp_vabs_simd, this);
7416	7590	#if SIMUL_SIMD
7417		UML_CALLC(block, cfunc_backup_regs, rsp);
7418		UML_CALLC(block, cfunc_rsp_vabs_scalar, rsp);
7419		UML_CALLC(block, cfunc_restore_regs, rsp);
7420		UML_CALLC(block, cfunc_verify_regs, rsp);
	7591	UML_CALLC(block, cfunc_backup_regs, this);
	7592	UML_CALLC(block, cfunc_rsp_vabs_scalar, this);
	7593	UML_CALLC(block, cfunc_restore_regs, this);
	7594	UML_CALLC(block, cfunc_verify_regs, this);
7421	7595	#endif
7422	7596	return TRUE;
7423	7597
7424	7598	case 0x14:      /* VADDC */
7425		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7426		UML_CALLC(block, cfunc_rsp_vaddc_simd, rsp);
	7599	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7600	UML_CALLC(block, cfunc_rsp_vaddc_simd, this);
7427	7601	#if SIMUL_SIMD
7428		UML_CALLC(block, cfunc_backup_regs, rsp);
7429		UML_CALLC(block, cfunc_rsp_vaddc_scalar, rsp);
7430		UML_CALLC(block, cfunc_restore_regs, rsp);
7431		UML_CALLC(block, cfunc_verify_regs, rsp);
	7602	UML_CALLC(block, cfunc_backup_regs, this);
	7603	UML_CALLC(block, cfunc_rsp_vaddc_scalar, this);
	7604	UML_CALLC(block, cfunc_restore_regs, this);
	7605	UML_CALLC(block, cfunc_verify_regs, this);
7432	7606	#endif
7433	7607	return TRUE;
7434	7608
7435	7609	case 0x15:      /* VSUBC */
7436		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7437		UML_CALLC(block, cfunc_rsp_vsubc_simd, rsp);
	7610	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7611	UML_CALLC(block, cfunc_rsp_vsubc_simd, this);
7438	7612	#if SIMUL_SIMD
7439		UML_CALLC(block, cfunc_backup_regs, rsp);
7440		UML_CALLC(block, cfunc_rsp_vsubc_scalar, rsp);
7441		UML_CALLC(block, cfunc_restore_regs, rsp);
7442		UML_CALLC(block, cfunc_verify_regs, rsp);
	7613	UML_CALLC(block, cfunc_backup_regs, this);
	7614	UML_CALLC(block, cfunc_rsp_vsubc_scalar, this);
	7615	UML_CALLC(block, cfunc_restore_regs, this);
	7616	UML_CALLC(block, cfunc_verify_regs, this);
7443	7617	#endif
7444	7618	return TRUE;
7445	7619
7446	7620	case 0x1d:      /* VSAW */
7447		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7448		UML_CALLC(block, cfunc_rsp_vsaw_simd, rsp);
	7621	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7622	UML_CALLC(block, cfunc_rsp_vsaw_simd, this);
7449	7623	#if SIMUL_SIMD
7450		UML_CALLC(block, cfunc_backup_regs, rsp);
7451		UML_CALLC(block, cfunc_rsp_vsaw_scalar, rsp);
7452		UML_CALLC(block, cfunc_restore_regs, rsp);
7453		UML_CALLC(block, cfunc_verify_regs, rsp);
	7624	UML_CALLC(block, cfunc_backup_regs, this);
	7625	UML_CALLC(block, cfunc_rsp_vsaw_scalar, this);
	7626	UML_CALLC(block, cfunc_restore_regs, this);
	7627	UML_CALLC(block, cfunc_verify_regs, this);
7454	7628	#endif
7455	7629	return TRUE;
7456	7630
7457	7631	case 0x20:      /* VLT */
7458		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7459		UML_CALLC(block, cfunc_rsp_vlt_simd, rsp);
	7632	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7633	UML_CALLC(block, cfunc_rsp_vlt_simd, this);
7460	7634	#if SIMUL_SIMD
7461		UML_CALLC(block, cfunc_backup_regs, rsp);
7462		UML_CALLC(block, cfunc_rsp_vlt_scalar, rsp);
7463		UML_CALLC(block, cfunc_restore_regs, rsp);
7464		UML_CALLC(block, cfunc_verify_regs, rsp);
	7635	UML_CALLC(block, cfunc_backup_regs, this);
	7636	UML_CALLC(block, cfunc_rsp_vlt_scalar, this);
	7637	UML_CALLC(block, cfunc_restore_regs, this);
	7638	UML_CALLC(block, cfunc_verify_regs, this);
7465	7639	#endif
7466	7640	return TRUE;
7467	7641
7468	7642	case 0x21:      /* VEQ */
7469		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7470		UML_CALLC(block, cfunc_rsp_veq_simd, rsp);
	7643	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7644	UML_CALLC(block, cfunc_rsp_veq_simd, this);
7471	7645	#if SIMUL_SIMD
7472		UML_CALLC(block, cfunc_backup_regs, rsp);
7473		UML_CALLC(block, cfunc_rsp_veq_scalar, rsp);
7474		UML_CALLC(block, cfunc_restore_regs, rsp);
7475		UML_CALLC(block, cfunc_verify_regs, rsp);
	7646	UML_CALLC(block, cfunc_backup_regs, this);
	7647	UML_CALLC(block, cfunc_rsp_veq_scalar, this);
	7648	UML_CALLC(block, cfunc_restore_regs, this);
	7649	UML_CALLC(block, cfunc_verify_regs, this);
7476	7650	#endif
7477	7651	return TRUE;
7478	7652
7479	7653	case 0x22:      /* VNE */
7480		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7481		UML_CALLC(block, cfunc_rsp_vne_simd, rsp);
	7654	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7655	UML_CALLC(block, cfunc_rsp_vne_simd, this);
7482	7656	#if SIMUL_SIMD
7483		UML_CALLC(block, cfunc_backup_regs, rsp);
7484		UML_CALLC(block, cfunc_rsp_vne_scalar, rsp);
7485		UML_CALLC(block, cfunc_restore_regs, rsp);
7486		UML_CALLC(block, cfunc_verify_regs, rsp);
	7657	UML_CALLC(block, cfunc_backup_regs, this);
	7658	UML_CALLC(block, cfunc_rsp_vne_scalar, this);
	7659	UML_CALLC(block, cfunc_restore_regs, this);
	7660	UML_CALLC(block, cfunc_verify_regs, this);
7487	7661	#endif
7488	7662	return TRUE;
7489	7663
7490	7664	case 0x23:      /* VGE */
7491		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7492		UML_CALLC(block, cfunc_rsp_vge_simd, rsp);
	7665	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7666	UML_CALLC(block, cfunc_rsp_vge_simd, this);
7493	7667	#if SIMUL_SIMD
7494		UML_CALLC(block, cfunc_backup_regs, rsp);
7495		UML_CALLC(block, cfunc_rsp_vge_scalar, rsp);
7496		UML_CALLC(block, cfunc_restore_regs, rsp);
7497		UML_CALLC(block, cfunc_verify_regs, rsp);
	7668	UML_CALLC(block, cfunc_backup_regs, this);
	7669	UML_CALLC(block, cfunc_rsp_vge_scalar, this);
	7670	UML_CALLC(block, cfunc_restore_regs, this);
	7671	UML_CALLC(block, cfunc_verify_regs, this);
7498	7672	#endif
7499	7673	return TRUE;
7500	7674
7501	7675	case 0x24:      /* VCL */
7502		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7503		UML_CALLC(block, cfunc_rsp_vcl_simd, rsp);
	7676	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7677	UML_CALLC(block, cfunc_rsp_vcl_simd, this);
7504	7678	#if SIMUL_SIMD
7505		UML_CALLC(block, cfunc_backup_regs, rsp);
7506		UML_CALLC(block, cfunc_rsp_vcl_scalar, rsp);
7507		UML_CALLC(block, cfunc_restore_regs, rsp);
7508		UML_CALLC(block, cfunc_verify_regs, rsp);
	7679	UML_CALLC(block, cfunc_backup_regs, this);
	7680	UML_CALLC(block, cfunc_rsp_vcl_scalar, this);
	7681	UML_CALLC(block, cfunc_restore_regs, this);
	7682	UML_CALLC(block, cfunc_verify_regs, this);
7509	7683	#endif
7510	7684	return TRUE;
7511	7685
7512	7686	case 0x25:      /* VCH */
7513		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7514		UML_CALLC(block, cfunc_rsp_vch_simd, rsp);
	7687	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7688	UML_CALLC(block, cfunc_rsp_vch_simd, this);
7515	7689	#if SIMUL_SIMD
7516		UML_CALLC(block, cfunc_backup_regs, rsp);
7517		UML_CALLC(block, cfunc_rsp_vch_scalar, rsp);
7518		UML_CALLC(block, cfunc_restore_regs, rsp);
7519		UML_CALLC(block, cfunc_verify_regs, rsp);
	7690	UML_CALLC(block, cfunc_backup_regs, this);
	7691	UML_CALLC(block, cfunc_rsp_vch_scalar, this);
	7692	UML_CALLC(block, cfunc_restore_regs, this);
	7693	UML_CALLC(block, cfunc_verify_regs, this);
7520	7694	#endif
7521	7695	return TRUE;
7522	7696
7523	7697	case 0x26:      /* VCR */
7524		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7525		UML_CALLC(block, cfunc_rsp_vcr_simd, rsp);
	7698	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7699	UML_CALLC(block, cfunc_rsp_vcr_simd, this);
7526	7700	#if SIMUL_SIMD
7527		UML_CALLC(block, cfunc_backup_regs, rsp);
7528		UML_CALLC(block, cfunc_rsp_vcr_scalar, rsp);
7529		UML_CALLC(block, cfunc_restore_regs, rsp);
7530		UML_CALLC(block, cfunc_verify_regs, rsp);
	7701	UML_CALLC(block, cfunc_backup_regs, this);
	7702	UML_CALLC(block, cfunc_rsp_vcr_scalar, this);
	7703	UML_CALLC(block, cfunc_restore_regs, this);
	7704	UML_CALLC(block, cfunc_verify_regs, this);
7531	7705	#endif
7532	7706	return TRUE;
7533	7707
7534	7708	case 0x27:      /* VMRG */
7535		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7536		UML_CALLC(block, cfunc_rsp_vmrg_simd, rsp);
	7709	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7710	UML_CALLC(block, cfunc_rsp_vmrg_simd, this);
7537	7711	#if SIMUL_SIMD
7538		UML_CALLC(block, cfunc_backup_regs, rsp);
7539		UML_CALLC(block, cfunc_rsp_vmrg_scalar, rsp);
7540		UML_CALLC(block, cfunc_restore_regs, rsp);
7541		UML_CALLC(block, cfunc_verify_regs, rsp);
	7712	UML_CALLC(block, cfunc_backup_regs, this);
	7713	UML_CALLC(block, cfunc_rsp_vmrg_scalar, this);
	7714	UML_CALLC(block, cfunc_restore_regs, this);
	7715	UML_CALLC(block, cfunc_verify_regs, this);
7542	7716	#endif
7543	7717	return TRUE;
7544	7718
7545	7719	case 0x28:      /* VAND */
7546		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7547		UML_CALLC(block, cfunc_rsp_vand_simd, rsp);
	7720	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7721	UML_CALLC(block, cfunc_rsp_vand_simd, this);
7548	7722	#if SIMUL_SIMD
7549		UML_CALLC(block, cfunc_backup_regs, rsp);
7550		UML_CALLC(block, cfunc_rsp_vand_scalar, rsp);
7551		UML_CALLC(block, cfunc_restore_regs, rsp);
7552		UML_CALLC(block, cfunc_verify_regs, rsp);
	7723	UML_CALLC(block, cfunc_backup_regs, this);
	7724	UML_CALLC(block, cfunc_rsp_vand_scalar, this);
	7725	UML_CALLC(block, cfunc_restore_regs, this);
	7726	UML_CALLC(block, cfunc_verify_regs, this);
7553	7727	#endif
7554	7728	return TRUE;
7555	7729
7556	7730	case 0x29:      /* VNAND */
7557		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7558		UML_CALLC(block, cfunc_rsp_vnand_simd, rsp);
	7731	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7732	UML_CALLC(block, cfunc_rsp_vnand_simd, this);
7559	7733	#if SIMUL_SIMD
7560		UML_CALLC(block, cfunc_backup_regs, rsp);
7561		UML_CALLC(block, cfunc_rsp_vnand_scalar, rsp);
7562		UML_CALLC(block, cfunc_restore_regs, rsp);
7563		UML_CALLC(block, cfunc_verify_regs, rsp);
	7734	UML_CALLC(block, cfunc_backup_regs, this);
	7735	UML_CALLC(block, cfunc_rsp_vnand_scalar, this);
	7736	UML_CALLC(block, cfunc_restore_regs, this);
	7737	UML_CALLC(block, cfunc_verify_regs, this);
7564	7738	#endif
7565	7739	return TRUE;
7566	7740
7567	7741	case 0x2a:      /* VOR */
7568		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7569		UML_CALLC(block, cfunc_rsp_vor_simd, rsp);
	7742	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7743	UML_CALLC(block, cfunc_rsp_vor_simd, this);
7570	7744	#if SIMUL_SIMD
7571		UML_CALLC(block, cfunc_backup_regs, rsp);
7572		UML_CALLC(block, cfunc_rsp_vor_scalar, rsp);
7573		UML_CALLC(block, cfunc_restore_regs, rsp);
7574		UML_CALLC(block, cfunc_verify_regs, rsp);
	7745	UML_CALLC(block, cfunc_backup_regs, this);
	7746	UML_CALLC(block, cfunc_rsp_vor_scalar, this);
	7747	UML_CALLC(block, cfunc_restore_regs, this);
	7748	UML_CALLC(block, cfunc_verify_regs, this);
7575	7749	#endif
7576	7750	return TRUE;
7577	7751
7578	7752	case 0x2b:      /* VNOR */
7579		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7580		UML_CALLC(block, cfunc_rsp_vnor_simd, rsp);
	7753	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7754	UML_CALLC(block, cfunc_rsp_vnor_simd, this);
7581	7755	#if SIMUL_SIMD
7582		UML_CALLC(block, cfunc_backup_regs, rsp);
7583		UML_CALLC(block, cfunc_rsp_vnor_scalar, rsp);
7584		UML_CALLC(block, cfunc_restore_regs, rsp);
7585		UML_CALLC(block, cfunc_verify_regs, rsp);
	7756	UML_CALLC(block, cfunc_backup_regs, this);
	7757	UML_CALLC(block, cfunc_rsp_vnor_scalar, this);
	7758	UML_CALLC(block, cfunc_restore_regs, this);
	7759	UML_CALLC(block, cfunc_verify_regs, this);
7586	7760	#endif
7587	7761	return TRUE;
7588	7762
7589	7763	case 0x2c:      /* VXOR */
7590		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7591		UML_CALLC(block, cfunc_rsp_vxor_simd, rsp);
	7764	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7765	UML_CALLC(block, cfunc_rsp_vxor_simd, this);
7592	7766	#if SIMUL_SIMD
7593		UML_CALLC(block, cfunc_backup_regs, rsp);
7594		UML_CALLC(block, cfunc_rsp_vxor_scalar, rsp);
7595		UML_CALLC(block, cfunc_restore_regs, rsp);
7596		UML_CALLC(block, cfunc_verify_regs, rsp);
	7767	UML_CALLC(block, cfunc_backup_regs, this);
	7768	UML_CALLC(block, cfunc_rsp_vxor_scalar, this);
	7769	UML_CALLC(block, cfunc_restore_regs, this);
	7770	UML_CALLC(block, cfunc_verify_regs, this);
7597	7771	#endif
7598	7772	return TRUE;
7599	7773
7600	7774	case 0x2d:      /* VNXOR */
7601		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7602		UML_CALLC(block, cfunc_rsp_vnxor_simd, rsp);
	7775	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7776	UML_CALLC(block, cfunc_rsp_vnxor_simd, this);
7603	7777	#if SIMUL_SIMD
7604		UML_CALLC(block, cfunc_backup_regs, rsp);
7605		UML_CALLC(block, cfunc_rsp_vnxor_scalar, rsp);
7606		UML_CALLC(block, cfunc_restore_regs, rsp);
7607		UML_CALLC(block, cfunc_verify_regs, rsp);
	7778	UML_CALLC(block, cfunc_backup_regs, this);
	7779	UML_CALLC(block, cfunc_rsp_vnxor_scalar, this);
	7780	UML_CALLC(block, cfunc_restore_regs, this);
	7781	UML_CALLC(block, cfunc_verify_regs, this);
7608	7782	#endif
7609	7783	return TRUE;
7610	7784
7611	7785	case 0x30:      /* VRCP */
7612		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7613		UML_CALLC(block, cfunc_rsp_vrcp_simd, rsp);
	7786	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7787	UML_CALLC(block, cfunc_rsp_vrcp_simd, this);
7614	7788	#if SIMUL_SIMD
7615		UML_CALLC(block, cfunc_backup_regs, rsp);
7616		UML_CALLC(block, cfunc_rsp_vrcp_scalar, rsp);
7617		UML_CALLC(block, cfunc_restore_regs, rsp);
7618		UML_CALLC(block, cfunc_verify_regs, rsp);
	7789	UML_CALLC(block, cfunc_backup_regs, this);
	7790	UML_CALLC(block, cfunc_rsp_vrcp_scalar, this);
	7791	UML_CALLC(block, cfunc_restore_regs, this);
	7792	UML_CALLC(block, cfunc_verify_regs, this);
7619	7793	#endif
7620	7794	return TRUE;
7621	7795
7622	7796	case 0x31:      /* VRCPL */
7623		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7624		UML_CALLC(block, cfunc_rsp_vrcpl_simd, rsp);
	7797	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7798	UML_CALLC(block, cfunc_rsp_vrcpl_simd, this);
7625	7799	#if SIMUL_SIMD
7626		UML_CALLC(block, cfunc_backup_regs, rsp);
7627		UML_CALLC(block, cfunc_rsp_vrcpl_scalar, rsp);
7628		UML_CALLC(block, cfunc_restore_regs, rsp);
7629		UML_CALLC(block, cfunc_verify_regs, rsp);
	7800	UML_CALLC(block, cfunc_backup_regs, this);
	7801	UML_CALLC(block, cfunc_rsp_vrcpl_scalar, this);
	7802	UML_CALLC(block, cfunc_restore_regs, this);
	7803	UML_CALLC(block, cfunc_verify_regs, this);
7630	7804	#endif
7631	7805	return TRUE;
7632	7806
7633	7807	case 0x32:      /* VRCPH */
7634		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7635		UML_CALLC(block, cfunc_rsp_vrcph_simd, rsp);
	7808	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7809	UML_CALLC(block, cfunc_rsp_vrcph_simd, this);
7636	7810	#if SIMUL_SIMD
7637		UML_CALLC(block, cfunc_backup_regs, rsp);
7638		UML_CALLC(block, cfunc_rsp_vrcph_scalar, rsp);
7639		UML_CALLC(block, cfunc_restore_regs, rsp);
7640		UML_CALLC(block, cfunc_verify_regs, rsp);
	7811	UML_CALLC(block, cfunc_backup_regs, this);
	7812	UML_CALLC(block, cfunc_rsp_vrcph_scalar, this);
	7813	UML_CALLC(block, cfunc_restore_regs, this);
	7814	UML_CALLC(block, cfunc_verify_regs, this);
7641	7815	#endif
7642	7816	return TRUE;
7643	7817
7644	7818	case 0x33:      /* VMOV */
7645		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7646		UML_CALLC(block, cfunc_rsp_vmov_simd, rsp);
	7819	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7820	UML_CALLC(block, cfunc_rsp_vmov_simd, this);
7647	7821	#if SIMUL_SIMD
7648		UML_CALLC(block, cfunc_backup_regs, rsp);
7649		UML_CALLC(block, cfunc_rsp_vmov_scalar, rsp);
7650		UML_CALLC(block, cfunc_restore_regs, rsp);
7651		UML_CALLC(block, cfunc_verify_regs, rsp);
	7822	UML_CALLC(block, cfunc_backup_regs, this);
	7823	UML_CALLC(block, cfunc_rsp_vmov_scalar, this);
	7824	UML_CALLC(block, cfunc_restore_regs, this);
	7825	UML_CALLC(block, cfunc_verify_regs, this);
7652	7826	#endif
7653	7827	return TRUE;
7654	7828
7655	7829	case 0x35:      /* VRSQL */
7656		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7657		UML_CALLC(block, cfunc_rsp_vrsql_simd, rsp);
	7830	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7831	UML_CALLC(block, cfunc_rsp_vrsql_simd, this);
7658	7832	#if SIMUL_SIMD
7659		UML_CALLC(block, cfunc_backup_regs, rsp);
7660		UML_CALLC(block, cfunc_rsp_vrsql_scalar, rsp);
7661		UML_CALLC(block, cfunc_restore_regs, rsp);
7662		UML_CALLC(block, cfunc_verify_regs, rsp);
	7833	UML_CALLC(block, cfunc_backup_regs, this);
	7834	UML_CALLC(block, cfunc_rsp_vrsql_scalar, this);
	7835	UML_CALLC(block, cfunc_restore_regs, this);
	7836	UML_CALLC(block, cfunc_verify_regs, this);
7663	7837	#endif
7664	7838	return TRUE;
7665	7839
7666	7840	case 0x36:      /* VRSQH */
7667		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7668		UML_CALLC(block, cfunc_rsp_vrsqh_simd, rsp);
	7841	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7842	UML_CALLC(block, cfunc_rsp_vrsqh_simd, this);
7669	7843	#if SIMUL_SIMD
7670		UML_CALLC(block, cfunc_backup_regs, rsp);
7671		UML_CALLC(block, cfunc_rsp_vrsqh_scalar, rsp);
7672		UML_CALLC(block, cfunc_restore_regs, rsp);
7673		UML_CALLC(block, cfunc_verify_regs, rsp);
	7844	UML_CALLC(block, cfunc_backup_regs, this);
	7845	UML_CALLC(block, cfunc_rsp_vrsqh_scalar, this);
	7846	UML_CALLC(block, cfunc_restore_regs, this);
	7847	UML_CALLC(block, cfunc_verify_regs, this);
7674	7848	#endif
7675	7849	return TRUE;
7676	7850
7677	7851	default:
7678		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7679		UML_CALLC(block, cfunc_unimplemented_opcode, rsp);
	7852	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7853	UML_CALLC(block, cfunc_unimplemented_opcode, this);
7680	7854	return FALSE;
7681	7855	}
7682	7856	}
7683	7857
7684	7858	#else
7685	7859
7686		static int generate_vector_opcode(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
	7860	int rsp_device::generate_vector_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
7687	7861	{
7688	7862	UINT32 op = desc->opptr.l[0];
7689	7863	// Opcode legend:
r31833	r31834
7695	7869	switch (op & 0x3f)
7696	7870	{
7697	7871	case 0x00:      /* VMULF */
7698		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7699		UML_CALLC(block, cfunc_rsp_vmulf_scalar, rsp);
	7872	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7873	UML_CALLC(block, cfunc_rsp_vmulf_scalar, this);
7700	7874	return TRUE;
7701	7875
7702	7876	case 0x01:      /* VMULU */
7703		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7704		UML_CALLC(block, cfunc_rsp_vmulu_scalar, rsp);
	7877	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7878	UML_CALLC(block, cfunc_rsp_vmulu_scalar, this);
7705	7879	return TRUE;
7706	7880
7707	7881	case 0x04:      /* VMUDL */
7708		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7709		UML_CALLC(block, cfunc_rsp_vmudl_scalar, rsp);
	7882	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7883	UML_CALLC(block, cfunc_rsp_vmudl_scalar, this);
7710	7884	return TRUE;
7711	7885
7712	7886	case 0x05:      /* VMUDM */
7713		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7714		UML_CALLC(block, cfunc_rsp_vmudm_scalar, rsp);
	7887	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7888	UML_CALLC(block, cfunc_rsp_vmudm_scalar, this);
7715	7889	return TRUE;
7716	7890
7717	7891	case 0x06:      /* VMUDN */
7718		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7719		UML_CALLC(block, cfunc_rsp_vmudn_scalar, rsp);
	7892	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7893	UML_CALLC(block, cfunc_rsp_vmudn_scalar, this);
7720	7894	return TRUE;
7721	7895
7722	7896	case 0x07:      /* VMUDH */
7723		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7724		UML_CALLC(block, cfunc_rsp_vmudh_scalar, rsp);
	7897	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7898	UML_CALLC(block, cfunc_rsp_vmudh_scalar, this);
7725	7899	return TRUE;
7726	7900
7727	7901	case 0x08:      /* VMACF */
7728		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7729		UML_CALLC(block, cfunc_rsp_vmacf_scalar, rsp);
	7902	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7903	UML_CALLC(block, cfunc_rsp_vmacf_scalar, this);
7730	7904	return TRUE;
7731	7905
7732	7906	case 0x09:      /* VMACU */
7733		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7734		UML_CALLC(block, cfunc_rsp_vmacu_scalar, rsp);
	7907	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7908	UML_CALLC(block, cfunc_rsp_vmacu_scalar, this);
7735	7909	return TRUE;
7736	7910
7737	7911	case 0x0c:      /* VMADL */
7738		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7739		UML_CALLC(block, cfunc_rsp_vmadl_scalar, rsp);
	7912	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7913	UML_CALLC(block, cfunc_rsp_vmadl_scalar, this);
7740	7914	return TRUE;
7741	7915
7742	7916	case 0x0d:      /* VMADM */
7743		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7744		UML_CALLC(block, cfunc_rsp_vmadm_scalar, rsp);
	7917	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7918	UML_CALLC(block, cfunc_rsp_vmadm_scalar, this);
7745	7919	return TRUE;
7746	7920
7747	7921	case 0x0e:      /* VMADN */
7748		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7749		UML_CALLC(block, cfunc_rsp_vmadn_scalar, rsp);
	7922	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7923	UML_CALLC(block, cfunc_rsp_vmadn_scalar, this);
7750	7924	return TRUE;
7751	7925
7752	7926	case 0x0f:      /* VMADH */
7753		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7754		UML_CALLC(block, cfunc_rsp_vmadh_scalar, rsp);
	7927	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7928	UML_CALLC(block, cfunc_rsp_vmadh_scalar, this);
7755	7929	return TRUE;
7756	7930
7757	7931	case 0x10:      /* VADD */
7758		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7759		UML_CALLC(block, cfunc_rsp_vadd_scalar, rsp);
	7932	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7933	UML_CALLC(block, cfunc_rsp_vadd_scalar, this);
7760	7934	return TRUE;
7761	7935
7762	7936	case 0x11:      /* VSUB */
7763		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7764		UML_CALLC(block, cfunc_rsp_vsub_scalar, rsp);
	7937	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7938	UML_CALLC(block, cfunc_rsp_vsub_scalar, this);
7765	7939	return TRUE;
7766	7940
7767	7941	case 0x13:      /* VABS */
7768		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7769		UML_CALLC(block, cfunc_rsp_vabs_scalar, rsp);
	7942	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7943	UML_CALLC(block, cfunc_rsp_vabs_scalar, this);
7770	7944	return TRUE;
7771	7945
7772	7946	case 0x14:      /* VADDC */
7773		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7774		UML_CALLC(block, cfunc_rsp_vaddc_scalar, rsp);
	7947	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7948	UML_CALLC(block, cfunc_rsp_vaddc_scalar, this);
7775	7949	return TRUE;
7776	7950
7777	7951	case 0x15:      /* VSUBC */
7778		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7779		UML_CALLC(block, cfunc_rsp_vsubc_scalar, rsp);
	7952	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7953	UML_CALLC(block, cfunc_rsp_vsubc_scalar, this);
7780	7954	return TRUE;
7781	7955
7782	7956	case 0x1d:      /* VSAW */
7783		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7784		UML_CALLC(block, cfunc_rsp_vsaw_scalar, rsp);
	7957	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7958	UML_CALLC(block, cfunc_rsp_vsaw_scalar, this);
7785	7959	return TRUE;
7786	7960
7787	7961	case 0x20:      /* VLT */
7788		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7789		UML_CALLC(block, cfunc_rsp_vlt_scalar, rsp);
	7962	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7963	UML_CALLC(block, cfunc_rsp_vlt_scalar, this);
7790	7964	return TRUE;
7791	7965
7792	7966	case 0x21:      /* VEQ */
7793		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7794		UML_CALLC(block, cfunc_rsp_veq_scalar, rsp);
	7967	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7968	UML_CALLC(block, cfunc_rsp_veq_scalar, this);
7795	7969	return TRUE;
7796	7970
7797	7971	case 0x22:      /* VNE */
7798		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7799		UML_CALLC(block, cfunc_rsp_vne_scalar, rsp);
	7972	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7973	UML_CALLC(block, cfunc_rsp_vne_scalar, this);
7800	7974	return TRUE;
7801	7975
7802	7976	case 0x23:      /* VGE */
7803		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7804		UML_CALLC(block, cfunc_rsp_vge_scalar, rsp);
	7977	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7978	UML_CALLC(block, cfunc_rsp_vge_scalar, this);
7805	7979	return TRUE;
7806	7980
7807	7981	case 0x24:      /* VCL */
7808		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7809		UML_CALLC(block, cfunc_rsp_vcl_scalar, rsp);
	7982	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7983	UML_CALLC(block, cfunc_rsp_vcl_scalar, this);
7810	7984	return TRUE;
7811	7985
7812	7986	case 0x25:      /* VCH */
7813		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7814		UML_CALLC(block, cfunc_rsp_vch_scalar, rsp);
	7987	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7988	UML_CALLC(block, cfunc_rsp_vch_scalar, this);
7815	7989	return TRUE;
7816	7990
7817	7991	case 0x26:      /* VCR */
7818		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7819		UML_CALLC(block, cfunc_rsp_vcr_scalar, rsp);
	7992	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7993	UML_CALLC(block, cfunc_rsp_vcr_scalar, this);
7820	7994	return TRUE;
7821	7995
7822	7996	case 0x27:      /* VMRG */
7823		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7824		UML_CALLC(block, cfunc_rsp_vmrg_scalar, rsp);
	7997	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	7998	UML_CALLC(block, cfunc_rsp_vmrg_scalar, this);
7825	7999	return TRUE;
7826	8000
7827	8001	case 0x28:      /* VAND */
7828		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7829		UML_CALLC(block, cfunc_rsp_vand_scalar, rsp);
	8002	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	8003	UML_CALLC(block, cfunc_rsp_vand_scalar, this);
7830	8004	return TRUE;
7831	8005
7832	8006	case 0x29:      /* VNAND */
7833		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7834		UML_CALLC(block, cfunc_rsp_vnand_scalar, rsp);
	8007	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	8008	UML_CALLC(block, cfunc_rsp_vnand_scalar, this);
7835	8009	return TRUE;
7836	8010
7837	8011	case 0x2a:      /* VOR */
7838		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7839		UML_CALLC(block, cfunc_rsp_vor_scalar, rsp);
	8012	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	8013	UML_CALLC(block, cfunc_rsp_vor_scalar, this);
7840	8014	return TRUE;
7841	8015
7842	8016	case 0x2b:      /* VNOR */
7843		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7844		UML_CALLC(block, cfunc_rsp_vnor_scalar, rsp);
	8017	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	8018	UML_CALLC(block, cfunc_rsp_vnor_scalar, this);
7845	8019	return TRUE;
7846	8020
7847	8021	case 0x2c:      /* VXOR */
7848		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7849		UML_CALLC(block, cfunc_rsp_vxor_scalar, rsp);
	8022	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	8023	UML_CALLC(block, cfunc_rsp_vxor_scalar, this);
7850	8024	return TRUE;
7851	8025
7852	8026	case 0x2d:      /* VNXOR */
7853		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7854		UML_CALLC(block, cfunc_rsp_vnxor_scalar, rsp);
	8027	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	8028	UML_CALLC(block, cfunc_rsp_vnxor_scalar, this);
7855	8029	return TRUE;
7856	8030
7857	8031	case 0x30:      /* VRCP */
7858		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7859		UML_CALLC(block, cfunc_rsp_vrcp_scalar, rsp);
	8032	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	8033	UML_CALLC(block, cfunc_rsp_vrcp_scalar, this);
7860	8034	return TRUE;
7861	8035
7862	8036	case 0x31:      /* VRCPL */
7863		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7864		UML_CALLC(block, cfunc_rsp_vrcpl_scalar, rsp);
	8037	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	8038	UML_CALLC(block, cfunc_rsp_vrcpl_scalar, this);
7865	8039	return TRUE;
7866	8040
7867	8041	case 0x32:      /* VRCPH */
7868		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7869		UML_CALLC(block, cfunc_rsp_vrcph_scalar, rsp);
	8042	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	8043	UML_CALLC(block, cfunc_rsp_vrcph_scalar, this);
7870	8044	return TRUE;
7871	8045
7872	8046	case 0x33:      /* VMOV */
7873		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7874		UML_CALLC(block, cfunc_rsp_vmov_scalar, rsp);
	8047	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	8048	UML_CALLC(block, cfunc_rsp_vmov_scalar, this);
7875	8049	return TRUE;
7876	8050
7877	8051	case 0x35:      /* VRSQL */
7878		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7879		UML_CALLC(block, cfunc_rsp_vrsql_scalar, rsp);
	8052	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	8053	UML_CALLC(block, cfunc_rsp_vrsql_scalar, this);
7880	8054	return TRUE;
7881	8055
7882	8056	case 0x36:      /* VRSQH */
7883		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7884		UML_CALLC(block, cfunc_rsp_vrsqh_scalar, rsp);
	8057	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	8058	UML_CALLC(block, cfunc_rsp_vrsqh_scalar, this);
7885	8059	return TRUE;
7886	8060
7887	8061	default:
7888		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
7889		UML_CALLC(block, cfunc_unimplemented_opcode, rsp);
	8062	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	8063	UML_CALLC(block, cfunc_unimplemented_opcode, this);
7890	8064	return FALSE;
7891	8065	}
7892	8066	}
7893	8067	#endif
7894	8068
7895		static int generate_opcode(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
	8069	int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
7896	8070	{
7897	8071	int in_delay_slot = ((desc->flags & OPFLAG_IN_DELAY_SLOT) != 0);
7898	8072	UINT32 op = desc->opptr.l[0];
r31833	r31834
7904	8078	/* ----- sub-groups ----- */
7905	8079
7906	8080	case 0x00:  /* SPECIAL - MIPS I */
7907		return generate_special(rsp, block, compiler, desc);
	8081	return generate_special(block, compiler, desc);
7908	8082
7909	8083	case 0x01:  /* REGIMM - MIPS I */
7910		return generate_regimm(rsp, block, compiler, desc);
	8084	return generate_regimm(block, compiler, desc);
7911	8085
7912	8086	/* ----- jumps and branches ----- */
7913	8087
7914	8088	case 0x02:  /* J - MIPS I */
7915		generate_delay_slot_and_branch(rsp, block, compiler, desc, 0);      // <next instruction + hashjmp>
	8089	generate_delay_slot_and_branch(block, compiler, desc, 0);      // <next instruction + hashjmp>
7916	8090	return TRUE;
7917	8091
7918	8092	case 0x03:  /* JAL - MIPS I */
7919		generate_delay_slot_and_branch(rsp, block, compiler, desc, 31);     // <next instruction + hashjmp>
	8093	generate_delay_slot_and_branch(block, compiler, desc, 31);     // <next instruction + hashjmp>
7920	8094	return TRUE;
7921	8095
7922	8096	case 0x04:  /* BEQ - MIPS I */
7923	8097	UML_CMP(block, R32(RSREG), R32(RTREG));                             // cmp    <rsreg>,<rtreg>
7924	8098	UML_JMPc(block, COND_NE, skip = compiler->labelnum++);              // jmp    skip,NE
7925		generate_delay_slot_and_branch(rsp, block, compiler, desc, 0);      // <next instruction + hashjmp>
	8099	generate_delay_slot_and_branch(block, compiler, desc, 0);      // <next instruction + hashjmp>
7926	8100	UML_LABEL(block, skip);                                             // skip:
7927	8101	return TRUE;
7928	8102
7929	8103	case 0x05:  /* BNE - MIPS I */
7930	8104	UML_CMP(block, R32(RSREG), R32(RTREG));                             // dcmp    <rsreg>,<rtreg>
7931	8105	UML_JMPc(block, COND_E, skip = compiler->labelnum++);                       // jmp     skip,E
7932		generate_delay_slot_and_branch(rsp, block, compiler, desc, 0);      // <next instruction + hashjmp>
	8106	generate_delay_slot_and_branch(block, compiler, desc, 0);      // <next instruction + hashjmp>
7933	8107	UML_LABEL(block, skip);                                             // skip:
7934	8108	return TRUE;
7935	8109
r31833	r31834
7938	8112	{
7939	8113	UML_CMP(block, R32(RSREG), 0);                              // dcmp    <rsreg>,0
7940	8114	UML_JMPc(block, COND_G, skip = compiler->labelnum++);                   // jmp     skip,G
7941		generate_delay_slot_and_branch(rsp, block, compiler, desc, 0);  // <next instruction + hashjmp>
	8115	generate_delay_slot_and_branch(block, compiler, desc, 0);  // <next instruction + hashjmp>
7942	8116	UML_LABEL(block, skip);                                         // skip:
7943	8117	}
7944	8118	else
7945		generate_delay_slot_and_branch(rsp, block, compiler, desc, 0);  // <next instruction + hashjmp>
	8119	generate_delay_slot_and_branch(block, compiler, desc, 0);  // <next instruction + hashjmp>
7946	8120	return TRUE;
7947	8121
7948	8122	case 0x07:  /* BGTZ - MIPS I */
7949	8123	UML_CMP(block, R32(RSREG), 0);                                  // dcmp    <rsreg>,0
7950	8124	UML_JMPc(block, COND_LE, skip = compiler->labelnum++);                  // jmp     skip,LE
7951		generate_delay_slot_and_branch(rsp, block, compiler, desc, 0);      // <next instruction + hashjmp>
	8125	generate_delay_slot_and_branch(block, compiler, desc, 0);      // <next instruction + hashjmp>
7952	8126	UML_LABEL(block, skip);                                             // skip:
7953	8127	return TRUE;
7954	8128
r31833	r31834
8004	8178
8005	8179	case 0x20:  /* LB - MIPS I */
8006	8180	UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
8007		UML_CALLH(block, *rsp->impstate->read8);                                    // callh   read8
	8181	UML_CALLH(block, *m_read8);                                    // callh   read8
8008	8182	if (RTREG != 0)
8009	8183	UML_SEXT(block, R32(RTREG), I0, SIZE_BYTE);                     // dsext   <rtreg>,i0,byte
8010	8184	if (!in_delay_slot)
8011		generate_update_cycles(rsp, block, compiler, desc->pc + 4, TRUE);
	8185	generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
8012	8186	return TRUE;
8013	8187
8014	8188	case 0x21:  /* LH - MIPS I */
8015	8189	UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
8016		UML_CALLH(block, *rsp->impstate->read16);                               // callh   read16
	8190	UML_CALLH(block, *m_read16);                               // callh   read16
8017	8191	if (RTREG != 0)
8018	8192	UML_SEXT(block, R32(RTREG), I0, SIZE_WORD);                     // dsext   <rtreg>,i0,word
8019	8193	if (!in_delay_slot)
8020		generate_update_cycles(rsp, block, compiler, desc->pc + 4, TRUE);
	8194	generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
8021	8195	return TRUE;
8022	8196
8023	8197	case 0x23:  /* LW - MIPS I */
8024	8198	UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
8025		UML_CALLH(block, *rsp->impstate->read32);                               // callh   read32
	8199	UML_CALLH(block, *m_read32);                               // callh   read32
8026	8200	if (RTREG != 0)
8027	8201	UML_MOV(block, R32(RTREG), I0);
8028	8202	if (!in_delay_slot)
8029		generate_update_cycles(rsp, block, compiler, desc->pc + 4, TRUE);
	8203	generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
8030	8204	return TRUE;
8031	8205
8032	8206	case 0x24:  /* LBU - MIPS I */
8033	8207	UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
8034		UML_CALLH(block, *rsp->impstate->read8);                                    // callh   read8
	8208	UML_CALLH(block, *m_read8);                                    // callh   read8
8035	8209	if (RTREG != 0)
8036	8210	UML_AND(block, R32(RTREG), I0, 0xff);                   // dand    <rtreg>,i0,0xff
8037	8211	if (!in_delay_slot)
8038		generate_update_cycles(rsp, block, compiler, desc->pc + 4, TRUE);
	8212	generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
8039	8213	return TRUE;
8040	8214
8041	8215	case 0x25:  /* LHU - MIPS I */
8042	8216	UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
8043		UML_CALLH(block, *rsp->impstate->read16);                               // callh   read16
	8217	UML_CALLH(block, *m_read16);                               // callh   read16
8044	8218	if (RTREG != 0)
8045	8219	UML_AND(block, R32(RTREG), I0, 0xffff);                 // dand    <rtreg>,i0,0xffff
8046	8220	if (!in_delay_slot)
8047		generate_update_cycles(rsp, block, compiler, desc->pc + 4, TRUE);
	8221	generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
8048	8222	return TRUE;
8049	8223
8050	8224	case 0x32:  /* LWC2 - MIPS I */
8051		return generate_lwc2(rsp, block, compiler, desc);
	8225	return generate_lwc2(block, compiler, desc);
8052	8226
8053	8227
8054	8228	/* ----- memory store operations ----- */
r31833	r31834
8056	8230	case 0x28:  /* SB - MIPS I */
8057	8231	UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
8058	8232	UML_MOV(block, I1, R32(RTREG));                                 // mov     i1,<rtreg>
8059		UML_CALLH(block, *rsp->impstate->write8);                               // callh   write8
	8233	UML_CALLH(block, *m_write8);                               // callh   write8
8060	8234	if (!in_delay_slot)
8061		generate_update_cycles(rsp, block, compiler, desc->pc + 4, TRUE);
	8235	generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
8062	8236	return TRUE;
8063	8237
8064	8238	case 0x29:  /* SH - MIPS I */
8065	8239	UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
8066	8240	UML_MOV(block, I1, R32(RTREG));                                 // mov     i1,<rtreg>
8067		UML_CALLH(block, *rsp->impstate->write16);                              // callh   write16
	8241	UML_CALLH(block, *m_write16);                              // callh   write16
8068	8242	if (!in_delay_slot)
8069		generate_update_cycles(rsp, block, compiler, desc->pc + 4, TRUE);
	8243	generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
8070	8244	return TRUE;
8071	8245
8072	8246	case 0x2b:  /* SW - MIPS I */
8073	8247	UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
8074	8248	UML_MOV(block, I1, R32(RTREG));                                 // mov     i1,<rtreg>
8075		UML_CALLH(block, *rsp->impstate->write32);                              // callh   write32
	8249	UML_CALLH(block, *m_write32);                              // callh   write32
8076	8250	if (!in_delay_slot)
8077		generate_update_cycles(rsp, block, compiler, desc->pc + 4, TRUE);
	8251	generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
8078	8252	return TRUE;
8079	8253
8080	8254	case 0x3a:  /* SWC2 - MIPS I */
8081		return generate_swc2(rsp, block, compiler, desc);
8082		//UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);     // mov     [arg0],desc->opptr.l
8083		//UML_CALLC(block, cfunc_swc2, rsp);                                        // callc   cfunc_mfc2
	8255	return generate_swc2(block, compiler, desc);
	8256	//UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);     // mov     [arg0],desc->opptr.l
	8257	//UML_CALLC(block, cfunc_swc2, this);                                        // callc   cfunc_mfc2
8084	8258	//return TRUE;
8085	8259
8086	8260	/* ----- coprocessor instructions ----- */
8087	8261
8088	8262	case 0x10:  /* COP0 - MIPS I */
8089		return generate_cop0(rsp, block, compiler, desc);
	8263	return generate_cop0(block, compiler, desc);
8090	8264
8091	8265	case 0x12:  /* COP2 - MIPS I */
8092		return generate_cop2(rsp, block, compiler, desc);
8093		//UML_EXH(block, rsp->impstate->exception[EXCEPTION_INVALIDOP], 0);// exh     invalidop,0
	8266	return generate_cop2(block, compiler, desc);
	8267	//UML_EXH(block, m_exception[EXCEPTION_INVALIDOP], 0);// exh     invalidop,0
8094	8268	//return TRUE;
8095	8269
8096	8270
r31833	r31834
8108	8282	'SPECIAL' group
8109	8283	-------------------------------------------------*/
8110	8284
8111		static int generate_special(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
	8285	int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
8112	8286	{
8113	8287	UINT32 op = desc->opptr.l[0];
8114	8288	UINT8 opswitch = op & 63;
r31833	r31834
8232	8406	/* ----- jumps and branches ----- */
8233	8407
8234	8408	case 0x08:  /* JR - MIPS I */
8235		generate_delay_slot_and_branch(rsp, block, compiler, desc, 0);      // <next instruction + hashjmp>
	8409	generate_delay_slot_and_branch(block, compiler, desc, 0);      // <next instruction + hashjmp>
8236	8410	return TRUE;
8237	8411
8238	8412	case 0x09:  /* JALR - MIPS I */
8239		generate_delay_slot_and_branch(rsp, block, compiler, desc, RDREG);  // <next instruction + hashjmp>
	8413	generate_delay_slot_and_branch(block, compiler, desc, RDREG);  // <next instruction + hashjmp>
8240	8414	return TRUE;
8241	8415
8242	8416
8243	8417	/* ----- system calls ----- */
8244	8418
8245	8419	case 0x0d:  /* BREAK - MIPS I */
8246		UML_MOV(block, mem(&rsp->impstate->arg0), 3);                   // mov     [arg0],3
8247		UML_CALLC(block, cfunc_sp_set_status_cb, rsp);                      // callc   cfunc_sp_set_status_cb
8248		UML_MOV(block, mem(&rsp->icount), 0);                       // mov icount, #0
	8420	UML_MOV(block, mem(&m_rsp_state->arg0), 3);                   // mov     [arg0],3
	8421	UML_CALLC(block, cfunc_sp_set_status_cb, this);                      // callc   cfunc_sp_set_status_cb
	8422	UML_MOV(block, mem(&m_rsp_state->icount), 0);                       // mov icount, #0
8249	8423
8250	8424	UML_EXIT(block, EXECUTE_OUT_OF_CYCLES);
8251	8425	return TRUE;
r31833	r31834
8260	8434	'REGIMM' group
8261	8435	-------------------------------------------------*/
8262	8436
8263		static int generate_regimm(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
	8437	int rsp_device::generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
8264	8438	{
8265	8439	UINT32 op = desc->opptr.l[0];
8266	8440	UINT8 opswitch = RTREG;
r31833	r31834
8274	8448	{
8275	8449	UML_CMP(block, R32(RSREG), 0);                              // dcmp    <rsreg>,0
8276	8450	UML_JMPc(block, COND_GE, skip = compiler->labelnum++);              // jmp     skip,GE
8277		generate_delay_slot_and_branch(rsp, block, compiler, desc, (opswitch & 0x10) ? 31 : 0);
	8451	generate_delay_slot_and_branch(block, compiler, desc, (opswitch & 0x10) ? 31 : 0);
8278	8452	// <next instruction + hashjmp>
8279	8453	UML_LABEL(block, skip);                                         // skip:
8280	8454	}
r31833	r31834
8286	8460	{
8287	8461	UML_CMP(block, R32(RSREG), 0);                              // dcmp    <rsreg>,0
8288	8462	UML_JMPc(block, COND_L, skip = compiler->labelnum++);                   // jmp     skip,L
8289		generate_delay_slot_and_branch(rsp, block, compiler, desc, (opswitch & 0x10) ? 31 : 0);
	8463	generate_delay_slot_and_branch(block, compiler, desc, (opswitch & 0x10) ? 31 : 0);
8290	8464	// <next instruction + hashjmp>
8291	8465	UML_LABEL(block, skip);                                         // skip:
8292	8466	}
8293	8467	else
8294		generate_delay_slot_and_branch(rsp, block, compiler, desc, (opswitch & 0x10) ? 31 : 0);
	8468	generate_delay_slot_and_branch(block, compiler, desc, (opswitch & 0x10) ? 31 : 0);
8295	8469	// <next instruction + hashjmp>
8296	8470	return TRUE;
8297	8471	}
r31833	r31834
8303	8477	generate_cop2 - compile COP2 opcodes
8304	8478	-------------------------------------------------*/
8305	8479
8306		static int generate_cop2(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
	8480	int rsp_device::generate_cop2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
8307	8481	{
8308	8482	UINT32 op = desc->opptr.l[0];
8309	8483	UINT8 opswitch = RSREG;
r31833	r31834
8313	8487	case 0x00:  /* MFCz */
8314	8488	if (RTREG != 0)
8315	8489	{
8316		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);    // mov     [arg0],desc->opptr.l
	8490	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);    // mov     [arg0],desc->opptr.l
8317	8491	#if USE_SIMD
8318		UML_CALLC(block, cfunc_mfc2_simd, rsp);                                      // callc   cfunc_ctc2
	8492	UML_CALLC(block, cfunc_mfc2_simd, this);                                      // callc   cfunc_ctc2
8319	8493	#if SIMUL_SIMD
8320		UML_CALLC(block, cfunc_backup_regs, rsp);
8321		UML_CALLC(block, cfunc_mfc2_scalar, rsp);
8322		UML_CALLC(block, cfunc_restore_regs, rsp);
8323		UML_CALLC(block, cfunc_verify_regs, rsp);
	8494	UML_CALLC(block, cfunc_backup_regs, this);
	8495	UML_CALLC(block, cfunc_mfc2_scalar, this);
	8496	UML_CALLC(block, cfunc_restore_regs, this);
	8497	UML_CALLC(block, cfunc_verify_regs, this);
8324	8498	#endif
8325	8499	#else
8326		UML_CALLC(block, cfunc_mfc2_scalar, rsp);
	8500	UML_CALLC(block, cfunc_mfc2_scalar, this);
8327	8501	#endif
8328	8502	//UML_SEXT(block, R32(RTREG), I0, DWORD);                      // dsext   <rtreg>,i0,dword
8329	8503	}
r31833	r31834
8332	8506	case 0x02:  /* CFCz */
8333	8507	if (RTREG != 0)
8334	8508	{
8335		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);    // mov     [arg0],desc->opptr.l
	8509	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);    // mov     [arg0],desc->opptr.l
8336	8510	#if USE_SIMD
8337		UML_CALLC(block, cfunc_cfc2_simd, rsp);                                      // callc   cfunc_ctc2
	8511	UML_CALLC(block, cfunc_cfc2_simd, this);                                      // callc   cfunc_ctc2
8338	8512	#if SIMUL_SIMD
8339		UML_CALLC(block, cfunc_backup_regs, rsp);
8340		UML_CALLC(block, cfunc_cfc2_scalar, rsp);
8341		UML_CALLC(block, cfunc_restore_regs, rsp);
8342		UML_CALLC(block, cfunc_verify_regs, rsp);
	8513	UML_CALLC(block, cfunc_backup_regs, this);
	8514	UML_CALLC(block, cfunc_cfc2_scalar, this);
	8515	UML_CALLC(block, cfunc_restore_regs, this);
	8516	UML_CALLC(block, cfunc_verify_regs, this);
8343	8517	#endif
8344	8518	#else
8345		UML_CALLC(block, cfunc_cfc2_scalar, rsp);
	8519	UML_CALLC(block, cfunc_cfc2_scalar, this);
8346	8520	#endif
8347	8521	//UML_SEXT(block, R32(RTREG), I0, DWORD);                      // dsext   <rtreg>,i0,dword
8348	8522	}
8349	8523	return TRUE;
8350	8524
8351	8525	case 0x04:  /* MTCz */
8352		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	8526	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
8353	8527	#if USE_SIMD
8354		UML_CALLC(block, cfunc_mtc2_simd, rsp);                                      // callc   cfunc_ctc2
	8528	UML_CALLC(block, cfunc_mtc2_simd, this);                                      // callc   cfunc_ctc2
8355	8529	#if SIMUL_SIMD
8356		UML_CALLC(block, cfunc_backup_regs, rsp);
8357		UML_CALLC(block, cfunc_mtc2_scalar, rsp);
8358		UML_CALLC(block, cfunc_restore_regs, rsp);
8359		UML_CALLC(block, cfunc_verify_regs, rsp);
	8530	UML_CALLC(block, cfunc_backup_regs, this);
	8531	UML_CALLC(block, cfunc_mtc2_scalar, this);
	8532	UML_CALLC(block, cfunc_restore_regs, this);
	8533	UML_CALLC(block, cfunc_verify_regs, this);
8360	8534	#endif
8361	8535	#else
8362		UML_CALLC(block, cfunc_mtc2_scalar, rsp);
	8536	UML_CALLC(block, cfunc_mtc2_scalar, this);
8363	8537	#endif
8364	8538	return TRUE;
8365	8539
8366	8540	case 0x06:  /* CTCz */
8367		UML_MOV(block, mem(&rsp->impstate->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
	8541	UML_MOV(block, mem(&m_rsp_state->arg0), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
8368	8542	#if USE_SIMD
8369		UML_CALLC(block, cfunc_ctc2_simd, rsp);                                      // callc   cfunc_ctc2
	8543	UML_CALLC(block, cfunc_ctc2_simd, this);                                      // callc   cfunc_ctc2
8370	8544	#if SIMUL_SIMD
8371		UML_CALLC(block, cfunc_backup_regs, rsp);
8372		UML_CALLC(block, cfunc_ctc2_scalar, rsp);
8373		UML_CALLC(block, cfunc_restore_regs, rsp);
8374		UML_CALLC(block, cfunc_verify_regs, rsp);
	8545	UML_CALLC(block, cfunc_backup_regs, this);
	8546	UML_CALLC(block, cfunc_ctc2_scalar, this);
	8547	UML_CALLC(block, cfunc_restore_regs, this);
	8548	UML_CALLC(block, cfunc_verify_regs, this);
8375	8549	#endif
8376	8550	#else
8377		UML_CALLC(block, cfunc_ctc2_scalar, rsp);
	8551	UML_CALLC(block, cfunc_ctc2_scalar, this);
8378	8552	#endif
8379	8553	return TRUE;
8380	8554
8381	8555	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
8382	8556	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
8383		return generate_vector_opcode(rsp, block, compiler, desc);
	8557	return generate_vector_opcode(block, compiler, desc);
8384	8558	}
8385	8559	return FALSE;
8386	8560	}
r31833	r31834
8389	8563	generate_cop0 - compile COP0 opcodes
8390	8564	-------------------------------------------------*/
8391	8565
8392		static int generate_cop0(rsp_state *rsp, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
	8566	int rsp_device::generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
8393	8567	{
8394	8568	UINT32 op = desc->opptr.l[0];
8395	8569	UINT8 opswitch = RSREG;
r31833	r31834
8399	8573	case 0x00:  /* MFCz */
8400	8574	if (RTREG != 0)
8401	8575	{
8402		UML_MOV(block, mem(&rsp->impstate->arg0), RDREG);               // mov     [arg0],<rdreg>
8403		UML_MOV(block, mem(&rsp->impstate->arg1), RTREG);               // mov     [arg1],<rtreg>
8404		UML_CALLC(block, cfunc_get_cop0_reg, rsp);                          // callc   cfunc_get_cop0_reg
	8576	UML_MOV(block, mem(&m_rsp_state->arg0), RDREG);               // mov     [arg0],<rdreg>
	8577	UML_MOV(block, mem(&m_rsp_state->arg1), RTREG);               // mov     [arg1],<rtreg>
	8578	UML_CALLC(block, cfunc_get_cop0_reg, this);                          // callc   cfunc_get_cop0_reg
8405	8579	if(RDREG == 2)
8406	8580	{
8407		generate_update_cycles(rsp, block, compiler, mem(&rsp->pc), TRUE);
8408		UML_HASHJMP(block, 0, mem(&rsp->pc), *rsp->impstate->nocode);
	8581	generate_update_cycles(block, compiler, mem(&m_rsp_state->pc), TRUE);
	8582	UML_HASHJMP(block, 0, mem(&m_rsp_state->pc), *m_nocode);
8409	8583	}
8410	8584	}
8411	8585	return TRUE;
8412	8586
8413	8587	case 0x04:  /* MTCz */
8414		UML_MOV(block, mem(&rsp->impstate->arg0), RDREG);                   // mov     [arg0],<rdreg>
8415		UML_MOV(block, mem(&rsp->impstate->arg1), R32(RTREG));                  // mov     [arg1],rtreg
8416		UML_CALLC(block, cfunc_set_cop0_reg, rsp);                              // callc   cfunc_set_cop0_reg
	8588	UML_MOV(block, mem(&m_rsp_state->arg0), RDREG);                   // mov     [arg0],<rdreg>
	8589	UML_MOV(block, mem(&m_rsp_state->arg1), R32(RTREG));                  // mov     [arg1],rtreg
	8590	UML_CALLC(block, cfunc_set_cop0_reg, this);                              // callc   cfunc_set_cop0_reg
8417	8591	return TRUE;
8418	8592	}
8419	8593
r31833	r31834
8421	8595	}
8422	8596
8423	8597	#if USE_SIMD
8424		static void cfunc_mfc2_simd(void *param)
	8598	inline void rsp_device::ccfunc_mfc2_simd()
8425	8599	{
8426		rsp_state *rsp = (rsp_state*)param;
8427		UINT32 op = rsp->impstate->arg0;
	8600	UINT32 op = m_rsp_state->arg0;
8428	8601	int el = (op >> 7) & 0xf;
8429	8602
8430	8603	UINT16 out;
8431		SIMD_EXTRACT16(rsp->xv[VS1REG], out, (el >> 1));
	8604	SIMD_EXTRACT16(m_xv[VS1REG], out, (el >> 1));
8432	8605	out >>= (1 - (el & 1)) * 8;
8433	8606	out &= 0x00ff;
8434	8607
8435	8608	el++;
8436	8609
8437	8610	UINT16 temp;
8438		SIMD_EXTRACT16(rsp->xv[VS1REG], temp, (el >> 1));
	8611	SIMD_EXTRACT16(m_xv[VS1REG], temp, (el >> 1));
8439	8612	temp >>= (1 - (el & 1)) * 8;
8440	8613	temp &= 0x00ff;
8441	8614
8442		rsp->r[RTREG] = (INT32)(INT16)((out << 8) | temp);
	8615	m_rsp_state->r[RTREG] = (INT32)(INT16)((out << 8) | temp);
8443	8616	}
	8617
	8618	static void cfunc_mfc2_simd(void *param)
	8619	{
	8620	((rsp_device *)param)->ccfunc_mfc2_simd();
	8621	}
8444	8622	#endif
8445	8623
8446	8624	#if (!USE_SIMD || SIMUL_SIMD)
8447		static void cfunc_mfc2_scalar(void *param)
	8625	inline void rsp_device::ccfunc_mfc2_scalar()
8448	8626	{
8449		rsp_state *rsp = (rsp_state*)param;
8450		UINT32 op = rsp->impstate->arg0;
	8627	UINT32 op = m_rsp_state->arg0;
8451	8628	int el = (op >> 7) & 0xf;
8452	8629
8453	8630	UINT16 b1 = VREG_B(VS1REG, (el+0) & 0xf);
8454	8631	UINT16 b2 = VREG_B(VS1REG, (el+1) & 0xf);
8455	8632	if (RTREG) RTVAL = (INT32)(INT16)((b1 << 8) | (b2));
8456	8633	}
	8634
	8635	static void cfunc_mfc2_scalar(void *param)
	8636	{
	8637	((rsp_device *)param)->ccfunc_mfc2_scalar();
	8638	}
8457	8639	#endif
8458	8640
8459	8641	#if USE_SIMD
8460		static void cfunc_cfc2_simd(void *param)
	8642	inline void rsp_device::ccfunc_cfc2_simd()
8461	8643	{
8462		rsp_state *rsp = (rsp_state*)param;
8463		UINT32 op = rsp->impstate->arg0;
	8644	UINT32 op = m_rsp_state->arg0;
8464	8645	if (RTREG)
8465	8646	{
8466	8647	switch(RDREG)
8467	8648	{
8468	8649	case 0:
8469		RTVAL = ((VEC_CARRY_FLAG(rsp, 0) & 1) << 0) |
8470		((VEC_CARRY_FLAG(rsp, 1) & 1) << 1) |
8471		((VEC_CARRY_FLAG(rsp, 2) & 1) << 2) |
8472		((VEC_CARRY_FLAG(rsp, 3) & 1) << 3) |
8473		((VEC_CARRY_FLAG(rsp, 4) & 1) << 4) |
8474		((VEC_CARRY_FLAG(rsp, 5) & 1) << 5) |
8475		((VEC_CARRY_FLAG(rsp, 6) & 1) << 6) |
8476		((VEC_CARRY_FLAG(rsp, 7) & 1) << 7) |
8477		((VEC_ZERO_FLAG(rsp, 0) & 1) << 8) |
8478		((VEC_ZERO_FLAG(rsp, 1) & 1) << 9) |
8479		((VEC_ZERO_FLAG(rsp, 2) & 1) << 10) |
8480		((VEC_ZERO_FLAG(rsp, 3) & 1) << 11) |
8481		((VEC_ZERO_FLAG(rsp, 4) & 1) << 12) |
8482		((VEC_ZERO_FLAG(rsp, 5) & 1) << 13) |
8483		((VEC_ZERO_FLAG(rsp, 6) & 1) << 14) |
8484		((VEC_ZERO_FLAG(rsp, 7) & 1) << 15);
	8650	RTVAL = ((VEC_CARRY_FLAG(0) & 1) << 0) |
	8651	((VEC_CARRY_FLAG(1) & 1) << 1) |
	8652	((VEC_CARRY_FLAG(2) & 1) << 2) |
	8653	((VEC_CARRY_FLAG(3) & 1) << 3) |
	8654	((VEC_CARRY_FLAG(4) & 1) << 4) |
	8655	((VEC_CARRY_FLAG(5) & 1) << 5) |
	8656	((VEC_CARRY_FLAG(6) & 1) << 6) |
	8657	((VEC_CARRY_FLAG(7) & 1) << 7) |
	8658	((VEC_ZERO_FLAG(0) & 1) << 8) |
	8659	((VEC_ZERO_FLAG(1) & 1) << 9) |
	8660	((VEC_ZERO_FLAG(2) & 1) << 10) |
	8661	((VEC_ZERO_FLAG(3) & 1) << 11) |
	8662	((VEC_ZERO_FLAG(4) & 1) << 12) |
	8663	((VEC_ZERO_FLAG(5) & 1) << 13) |
	8664	((VEC_ZERO_FLAG(6) & 1) << 14) |
	8665	((VEC_ZERO_FLAG(7) & 1) << 15);
8485	8666	if (RTVAL & 0x8000) RTVAL |= 0xffff0000;
8486	8667	break;
8487	8668	case 1:
8488		RTVAL = ((VEC_COMPARE_FLAG(rsp, 0) & 1) << 0) |
8489		((VEC_COMPARE_FLAG(rsp, 1) & 1) << 1) |
8490		((VEC_COMPARE_FLAG(rsp, 2) & 1) << 2) |
8491		((VEC_COMPARE_FLAG(rsp, 3) & 1) << 3) |
8492		((VEC_COMPARE_FLAG(rsp, 4) & 1) << 4) |
8493		((VEC_COMPARE_FLAG(rsp, 5) & 1) << 5) |
8494		((VEC_COMPARE_FLAG(rsp, 6) & 1) << 6) |
8495		((VEC_COMPARE_FLAG(rsp, 7) & 1) << 7) |
8496		((VEC_CLIP2_FLAG(rsp, 0) & 1) << 8) |
8497		((VEC_CLIP2_FLAG(rsp, 1) & 1) << 9) |
8498		((VEC_CLIP2_FLAG(rsp, 2) & 1) << 10) |
8499		((VEC_CLIP2_FLAG(rsp, 3) & 1) << 11) |
8500		((VEC_CLIP2_FLAG(rsp, 4) & 1) << 12) |
8501		((VEC_CLIP2_FLAG(rsp, 5) & 1) << 13) |
8502		((VEC_CLIP2_FLAG(rsp, 6) & 1) << 14) |
8503		((VEC_CLIP2_FLAG(rsp, 7) & 1) << 15);
	8669	RTVAL = ((VEC_COMPARE_FLAG(0) & 1) << 0) |
	8670	((VEC_COMPARE_FLAG(1) & 1) << 1) |
	8671	((VEC_COMPARE_FLAG(2) & 1) << 2) |
	8672	((VEC_COMPARE_FLAG(3) & 1) << 3) |
	8673	((VEC_COMPARE_FLAG(4) & 1) << 4) |
	8674	((VEC_COMPARE_FLAG(5) & 1) << 5) |
	8675	((VEC_COMPARE_FLAG(6) & 1) << 6) |
	8676	((VEC_COMPARE_FLAG(7) & 1) << 7) |
	8677	((VEC_CLIP2_FLAG(0) & 1) << 8) |
	8678	((VEC_CLIP2_FLAG(1) & 1) << 9) |
	8679	((VEC_CLIP2_FLAG(2) & 1) << 10) |
	8680	((VEC_CLIP2_FLAG(3) & 1) << 11) |
	8681	((VEC_CLIP2_FLAG(4) & 1) << 12) |
	8682	((VEC_CLIP2_FLAG(5) & 1) << 13) |
	8683	((VEC_CLIP2_FLAG(6) & 1) << 14) |
	8684	((VEC_CLIP2_FLAG(7) & 1) << 15);
8504	8685	if (RTVAL & 0x8000) RTVAL |= 0xffff0000;
8505	8686	break;
8506	8687	case 2:
8507		RTVAL = ((VEC_CLIP1_FLAG(rsp, 0) & 1) << 0) |
8508		((VEC_CLIP1_FLAG(rsp, 1) & 1) << 1) |
8509		((VEC_CLIP1_FLAG(rsp, 2) & 1) << 2) |
8510		((VEC_CLIP1_FLAG(rsp, 3) & 1) << 3) |
8511		((VEC_CLIP1_FLAG(rsp, 4) & 1) << 4) |
8512		((VEC_CLIP1_FLAG(rsp, 5) & 1) << 5) |
8513		((VEC_CLIP1_FLAG(rsp, 6) & 1) << 6) |
8514		((VEC_CLIP1_FLAG(rsp, 7) & 1) << 7);
	8688	RTVAL = ((VEC_CLIP1_FLAG(0) & 1) << 0) |
	8689	((VEC_CLIP1_FLAG(1) & 1) << 1) |
	8690	((VEC_CLIP1_FLAG(2) & 1) << 2) |
	8691	((VEC_CLIP1_FLAG(3) & 1) << 3) |
	8692	((VEC_CLIP1_FLAG(4) & 1) << 4) |
	8693	((VEC_CLIP1_FLAG(5) & 1) << 5) |
	8694	((VEC_CLIP1_FLAG(6) & 1) << 6) |
	8695	((VEC_CLIP1_FLAG(7) & 1) << 7);
8515	8696	break;
8516	8697	}
8517	8698	}
8518	8699	}
	8700
	8701	static void cfunc_cfc2_simd(void *param)
	8702	{
	8703	((rsp_device *)param)->ccfunc_cfc2_simd();
	8704	}
8519	8705	#endif
8520	8706
8521	8707	#if (!USE_SIMD || SIMUL_SIMD)
8522		static void cfunc_cfc2_scalar(void *param)
	8708	inline void rsp_device::ccfunc_cfc2_scalar()
8523	8709	{
8524		rsp_state *rsp = (rsp_state*)param;
8525		UINT32 op = rsp->impstate->arg0;
	8710	UINT32 op = m_rsp_state->arg0;
8526	8711	if (RTREG)
8527	8712	{
8528	8713	switch(RDREG)
8529	8714	{
8530	8715	case 0:
8531		RTVAL = ((CARRY_FLAG(rsp, 0) & 1) << 0) |
8532		((CARRY_FLAG(rsp, 1) & 1) << 1) |
8533		((CARRY_FLAG(rsp, 2) & 1) << 2) |
8534		((CARRY_FLAG(rsp, 3) & 1) << 3) |
8535		((CARRY_FLAG(rsp, 4) & 1) << 4) |
8536		((CARRY_FLAG(rsp, 5) & 1) << 5) |
8537		((CARRY_FLAG(rsp, 6) & 1) << 6) |
8538		((CARRY_FLAG(rsp, 7) & 1) << 7) |
8539		((ZERO_FLAG(rsp, 0) & 1) << 8) |
8540		((ZERO_FLAG(rsp, 1) & 1) << 9) |
8541		((ZERO_FLAG(rsp, 2) & 1) << 10) |
8542		((ZERO_FLAG(rsp, 3) & 1) << 11) |
8543		((ZERO_FLAG(rsp, 4) & 1) << 12) |
8544		((ZERO_FLAG(rsp, 5) & 1) << 13) |
8545		((ZERO_FLAG(rsp, 6) & 1) << 14) |
8546		((ZERO_FLAG(rsp, 7) & 1) << 15);
	8716	RTVAL = ((CARRY_FLAG(0) & 1) << 0) |
	8717	((CARRY_FLAG(1) & 1) << 1) |
	8718	((CARRY_FLAG(2) & 1) << 2) |
	8719	((CARRY_FLAG(3) & 1) << 3) |
	8720	((CARRY_FLAG(4) & 1) << 4) |
	8721	((CARRY_FLAG(5) & 1) << 5) |
	8722	((CARRY_FLAG(6) & 1) << 6) |
	8723	((CARRY_FLAG(7) & 1) << 7) |
	8724	((ZERO_FLAG(0) & 1) << 8) |
	8725	((ZERO_FLAG(1) & 1) << 9) |
	8726	((ZERO_FLAG(2) & 1) << 10) |
	8727	((ZERO_FLAG(3) & 1) << 11) |
	8728	((ZERO_FLAG(4) & 1) << 12) |
	8729	((ZERO_FLAG(5) & 1) << 13) |
	8730	((ZERO_FLAG(6) & 1) << 14) |
	8731	((ZERO_FLAG(7) & 1) << 15);
8547	8732	if (RTVAL & 0x8000) RTVAL |= 0xffff0000;
8548	8733	break;
8549	8734	case 1:
8550		RTVAL = ((COMPARE_FLAG(rsp, 0) & 1) << 0) |
8551		((COMPARE_FLAG(rsp, 1) & 1) << 1) |
8552		((COMPARE_FLAG(rsp, 2) & 1) << 2) |
8553		((COMPARE_FLAG(rsp, 3) & 1) << 3) |
8554		((COMPARE_FLAG(rsp, 4) & 1) << 4) |
8555		((COMPARE_FLAG(rsp, 5) & 1) << 5) |
8556		((COMPARE_FLAG(rsp, 6) & 1) << 6) |
8557		((COMPARE_FLAG(rsp, 7) & 1) << 7) |
8558		((CLIP2_FLAG(rsp, 0) & 1) << 8) |
8559		((CLIP2_FLAG(rsp, 1) & 1) << 9) |
8560		((CLIP2_FLAG(rsp, 2) & 1) << 10) |
8561		((CLIP2_FLAG(rsp, 3) & 1) << 11) |
8562		((CLIP2_FLAG(rsp, 4) & 1) << 12) |
8563		((CLIP2_FLAG(rsp, 5) & 1) << 13) |
8564		((CLIP2_FLAG(rsp, 6) & 1) << 14) |
8565		((CLIP2_FLAG(rsp, 7) & 1) << 15);
	8735	RTVAL = ((COMPARE_FLAG(0) & 1) << 0) |
	8736	((COMPARE_FLAG(1) & 1) << 1) |
	8737	((COMPARE_FLAG(2) & 1) << 2) |
	8738	((COMPARE_FLAG(3) & 1) << 3) |
	8739	((COMPARE_FLAG(4) & 1) << 4) |
	8740	((COMPARE_FLAG(5) & 1) << 5) |
	8741	((COMPARE_FLAG(6) & 1) << 6) |
	8742	((COMPARE_FLAG(7) & 1) << 7) |
	8743	((CLIP2_FLAG(0) & 1) << 8) |
	8744	((CLIP2_FLAG(1) & 1) << 9) |
	8745	((CLIP2_FLAG(2) & 1) << 10) |
	8746	((CLIP2_FLAG(3) & 1) << 11) |
	8747	((CLIP2_FLAG(4) & 1) << 12) |
	8748	((CLIP2_FLAG(5) & 1) << 13) |
	8749	((CLIP2_FLAG(6) & 1) << 14) |
	8750	((CLIP2_FLAG(7) & 1) << 15);
8566	8751	if (RTVAL & 0x8000) RTVAL |= 0xffff0000;
8567	8752	break;
8568	8753	case 2:
8569		RTVAL = ((CLIP1_FLAG(rsp, 0) & 1) << 0) |
8570		((CLIP1_FLAG(rsp, 1) & 1) << 1) |
8571		((CLIP1_FLAG(rsp, 2) & 1) << 2) |
8572		((CLIP1_FLAG(rsp, 3) & 1) << 3) |
8573		((CLIP1_FLAG(rsp, 4) & 1) << 4) |
8574		((CLIP1_FLAG(rsp, 5) & 1) << 5) |
8575		((CLIP1_FLAG(rsp, 6) & 1) << 6) |
8576		((CLIP1_FLAG(rsp, 7) & 1) << 7);
	8754	RTVAL = ((CLIP1_FLAG(0) & 1) << 0) |
	8755	((CLIP1_FLAG(1) & 1) << 1) |
	8756	((CLIP1_FLAG(2) & 1) << 2) |
	8757	((CLIP1_FLAG(3) & 1) << 3) |
	8758	((CLIP1_FLAG(4) & 1) << 4) |
	8759	((CLIP1_FLAG(5) & 1) << 5) |
	8760	((CLIP1_FLAG(6) & 1) << 6) |
	8761	((CLIP1_FLAG(7) & 1) << 7);
8577	8762	break;
8578	8763	}
8579	8764	}
8580	8765	}
	8766
	8767	static void cfunc_cfc2_scalar(void *param)
	8768	{
	8769	((rsp_device *)param)->ccfunc_cfc2_scalar();
	8770	}
8581	8771	#endif
8582	8772
8583	8773	#if USE_SIMD
8584		static void cfunc_mtc2_simd(void *param)
	8774	inline void rsp_device::ccfunc_mtc2_simd()
8585	8775	{
8586		rsp_state *rsp = (rsp_state*)param;
8587		UINT32 op = rsp->impstate->arg0;
	8776	UINT32 op = m_rsp_state->arg0;
8588	8777	int el = (op >> 7) & 0xf;
8589		SIMD_INSERT16(rsp->xv[VS1REG], RTVAL, el >> 1);
	8778	SIMD_INSERT16(m_xv[VS1REG], RTVAL, el >> 1);
8590	8779	}
	8780
	8781	static void cfunc_mtc2_simd(void *param)
	8782	{
	8783	((rsp_device *)param)->ccfunc_mtc2_simd();
	8784	}
8591	8785	#endif
8592	8786
8593	8787	#if (!USE_SIMD || SIMUL_SIMD)
8594		static void cfunc_mtc2_scalar(void *param)
	8788	inline void rsp_device::ccfunc_mtc2_scalar()
8595	8789	{
8596		rsp_state *rsp = (rsp_state*)param;
8597		UINT32 op = rsp->impstate->arg0;
	8790	UINT32 op = m_rsp_state->arg0;
8598	8791	int el = (op >> 7) & 0xf;
8599	8792	VREG_B(VS1REG, (el+0) & 0xf) = (RTVAL >> 8) & 0xff;
8600	8793	VREG_B(VS1REG, (el+1) & 0xf) = (RTVAL >> 0) & 0xff;
8601	8794	}
	8795
	8796	static void cfunc_mtc2_scalar(void *param)
	8797	{
	8798	((rsp_device *)param)->ccfunc_mtc2_scalar();
	8799	}
8602	8800	#endif
8603	8801
8604	8802	#if USE_SIMD
8605		static void cfunc_ctc2_simd(void *param)
	8803	inline void rsp_device::ccfunc_ctc2_simd()
8606	8804	{
8607		rsp_state *rsp = (rsp_state*)param;
8608		UINT32 op = rsp->impstate->arg0;
	8805	UINT32 op = m_rsp_state->arg0;
8609	8806	switch(RDREG)
8610	8807	{
8611	8808	case 0:
8612	8809	VEC_CLEAR_CARRY_FLAGS();
8613	8810	VEC_CLEAR_ZERO_FLAGS();
8614		rsp->vflag[0][0] = ((RTVAL >> 0) & 1) ? 0xffff : 0;
8615		rsp->vflag[0][1] = ((RTVAL >> 1) & 1) ? 0xffff : 0;
8616		rsp->vflag[0][2] = ((RTVAL >> 2) & 1) ? 0xffff : 0;
8617		rsp->vflag[0][3] = ((RTVAL >> 3) & 1) ? 0xffff : 0;
8618		rsp->vflag[0][4] = ((RTVAL >> 4) & 1) ? 0xffff : 0;
8619		rsp->vflag[0][5] = ((RTVAL >> 5) & 1) ? 0xffff : 0;
8620		rsp->vflag[0][6] = ((RTVAL >> 6) & 1) ? 0xffff : 0;
8621		rsp->vflag[0][7] = ((RTVAL >> 7) & 1) ? 0xffff : 0;
	8811	m_vflag[0][0] = ((RTVAL >> 0) & 1) ? 0xffff : 0;
	8812	m_vflag[0][1] = ((RTVAL >> 1) & 1) ? 0xffff : 0;
	8813	m_vflag[0][2] = ((RTVAL >> 2) & 1) ? 0xffff : 0;
	8814	m_vflag[0][3] = ((RTVAL >> 3) & 1) ? 0xffff : 0;
	8815	m_vflag[0][4] = ((RTVAL >> 4) & 1) ? 0xffff : 0;
	8816	m_vflag[0][5] = ((RTVAL >> 5) & 1) ? 0xffff : 0;
	8817	m_vflag[0][6] = ((RTVAL >> 6) & 1) ? 0xffff : 0;
	8818	m_vflag[0][7] = ((RTVAL >> 7) & 1) ? 0xffff : 0;
8622	8819	if (RTVAL & (1 << 0))  { VEC_SET_CARRY_FLAG(0); }
8623	8820	if (RTVAL & (1 << 1))  { VEC_SET_CARRY_FLAG(1); }
8624	8821	if (RTVAL & (1 << 2))  { VEC_SET_CARRY_FLAG(2); }
r31833	r31834
8627	8824	if (RTVAL & (1 << 5))  { VEC_SET_CARRY_FLAG(5); }
8628	8825	if (RTVAL & (1 << 6))  { VEC_SET_CARRY_FLAG(6); }
8629	8826	if (RTVAL & (1 << 7))  { VEC_SET_CARRY_FLAG(7); }
8630		rsp->vflag[3][0] = ((RTVAL >> 8) & 1) ? 0xffff : 0;
8631		rsp->vflag[3][1] = ((RTVAL >> 9) & 1) ? 0xffff : 0;
8632		rsp->vflag[3][2] = ((RTVAL >> 10) & 1) ? 0xffff : 0;
8633		rsp->vflag[3][3] = ((RTVAL >> 11) & 1) ? 0xffff : 0;
8634		rsp->vflag[3][4] = ((RTVAL >> 12) & 1) ? 0xffff : 0;
8635		rsp->vflag[3][5] = ((RTVAL >> 13) & 1) ? 0xffff : 0;
8636		rsp->vflag[3][6] = ((RTVAL >> 14) & 1) ? 0xffff : 0;
8637		rsp->vflag[3][7] = ((RTVAL >> 15) & 1) ? 0xffff : 0;
	8827	m_vflag[3][0] = ((RTVAL >> 8) & 1) ? 0xffff : 0;
	8828	m_vflag[3][1] = ((RTVAL >> 9) & 1) ? 0xffff : 0;
	8829	m_vflag[3][2] = ((RTVAL >> 10) & 1) ? 0xffff : 0;
	8830	m_vflag[3][3] = ((RTVAL >> 11) & 1) ? 0xffff : 0;
	8831	m_vflag[3][4] = ((RTVAL >> 12) & 1) ? 0xffff : 0;
	8832	m_vflag[3][5] = ((RTVAL >> 13) & 1) ? 0xffff : 0;
	8833	m_vflag[3][6] = ((RTVAL >> 14) & 1) ? 0xffff : 0;
	8834	m_vflag[3][7] = ((RTVAL >> 15) & 1) ? 0xffff : 0;
8638	8835	if (RTVAL & (1 << 8))  { VEC_SET_ZERO_FLAG(0); }
8639	8836	if (RTVAL & (1 << 9))  { VEC_SET_ZERO_FLAG(1); }
8640	8837	if (RTVAL & (1 << 10)) { VEC_SET_ZERO_FLAG(2); }
r31833	r31834
8647	8844	case 1:
8648	8845	VEC_CLEAR_COMPARE_FLAGS();
8649	8846	VEC_CLEAR_CLIP2_FLAGS();
8650		rsp->vflag[1][0] = ((RTVAL >> 0) & 1) ? 0xffff : 0;
8651		rsp->vflag[1][1] = ((RTVAL >> 1) & 1) ? 0xffff : 0;
8652		rsp->vflag[1][2] = ((RTVAL >> 2) & 1) ? 0xffff : 0;
8653		rsp->vflag[1][3] = ((RTVAL >> 3) & 1) ? 0xffff : 0;
8654		rsp->vflag[1][4] = ((RTVAL >> 4) & 1) ? 0xffff : 0;
8655		rsp->vflag[1][5] = ((RTVAL >> 5) & 1) ? 0xffff : 0;
8656		rsp->vflag[1][6] = ((RTVAL >> 6) & 1) ? 0xffff : 0;
8657		rsp->vflag[1][7] = ((RTVAL >> 7) & 1) ? 0xffff : 0;
	8847	m_vflag[1][0] = ((RTVAL >> 0) & 1) ? 0xffff : 0;
	8848	m_vflag[1][1] = ((RTVAL >> 1) & 1) ? 0xffff : 0;
	8849	m_vflag[1][2] = ((RTVAL >> 2) & 1) ? 0xffff : 0;
	8850	m_vflag[1][3] = ((RTVAL >> 3) & 1) ? 0xffff : 0;
	8851	m_vflag[1][4] = ((RTVAL >> 4) & 1) ? 0xffff : 0;
	8852	m_vflag[1][5] = ((RTVAL >> 5) & 1) ? 0xffff : 0;
	8853	m_vflag[1][6] = ((RTVAL >> 6) & 1) ? 0xffff : 0;
	8854	m_vflag[1][7] = ((RTVAL >> 7) & 1) ? 0xffff : 0;
8658	8855	if (RTVAL & (1 << 0)) { VEC_SET_COMPARE_FLAG(0); }
8659	8856	if (RTVAL & (1 << 1)) { VEC_SET_COMPARE_FLAG(1); }
8660	8857	if (RTVAL & (1 << 2)) { VEC_SET_COMPARE_FLAG(2); }
r31833	r31834
8663	8860	if (RTVAL & (1 << 5)) { VEC_SET_COMPARE_FLAG(5); }
8664	8861	if (RTVAL & (1 << 6)) { VEC_SET_COMPARE_FLAG(6); }
8665	8862	if (RTVAL & (1 << 7)) { VEC_SET_COMPARE_FLAG(7); }
8666		rsp->vflag[4][0] = ((RTVAL >> 8) & 1) ? 0xffff : 0;
8667		rsp->vflag[4][1] = ((RTVAL >> 9) & 1) ? 0xffff : 0;
8668		rsp->vflag[4][2] = ((RTVAL >> 10) & 1) ? 0xffff : 0;
8669		rsp->vflag[4][3] = ((RTVAL >> 11) & 1) ? 0xffff : 0;
8670		rsp->vflag[4][4] = ((RTVAL >> 12) & 1) ? 0xffff : 0;
8671		rsp->vflag[4][5] = ((RTVAL >> 13) & 1) ? 0xffff : 0;
8672		rsp->vflag[4][6] = ((RTVAL >> 14) & 1) ? 0xffff : 0;
8673		rsp->vflag[4][7] = ((RTVAL >> 15) & 1) ? 0xffff : 0;
	8863	m_vflag[4][0] = ((RTVAL >> 8) & 1) ? 0xffff : 0;
	8864	m_vflag[4][1] = ((RTVAL >> 9) & 1) ? 0xffff : 0;
	8865	m_vflag[4][2] = ((RTVAL >> 10) & 1) ? 0xffff : 0;
	8866	m_vflag[4][3] = ((RTVAL >> 11) & 1) ? 0xffff : 0;
	8867	m_vflag[4][4] = ((RTVAL >> 12) & 1) ? 0xffff : 0;
	8868	m_vflag[4][5] = ((RTVAL >> 13) & 1) ? 0xffff : 0;
	8869	m_vflag[4][6] = ((RTVAL >> 14) & 1) ? 0xffff : 0;
	8870	m_vflag[4][7] = ((RTVAL >> 15) & 1) ? 0xffff : 0;
8674	8871	if (RTVAL & (1 << 8))  { VEC_SET_CLIP2_FLAG(0); }
8675	8872	if (RTVAL & (1 << 9))  { VEC_SET_CLIP2_FLAG(1); }
8676	8873	if (RTVAL & (1 << 10)) { VEC_SET_CLIP2_FLAG(2); }
r31833	r31834
8682	8879	break;
8683	8880	case 2:
8684	8881	VEC_CLEAR_CLIP1_FLAGS();
8685		rsp->vflag[2][0] = ((RTVAL >> 0) & 1) ? 0xffff : 0;
8686		rsp->vflag[2][1] = ((RTVAL >> 1) & 1) ? 0xffff : 0;
8687		rsp->vflag[2][2] = ((RTVAL >> 2) & 1) ? 0xffff : 0;
8688		rsp->vflag[2][3] = ((RTVAL >> 3) & 1) ? 0xffff : 0;
8689		rsp->vflag[2][4] = ((RTVAL >> 4) & 1) ? 0xffff : 0;
8690		rsp->vflag[2][5] = ((RTVAL >> 5) & 1) ? 0xffff : 0;
8691		rsp->vflag[2][6] = ((RTVAL >> 6) & 1) ? 0xffff : 0;
8692		rsp->vflag[2][7] = ((RTVAL >> 7) & 1) ? 0xffff : 0;
	8882	m_vflag[2][0] = ((RTVAL >> 0) & 1) ? 0xffff : 0;
	8883	m_vflag[2][1] = ((RTVAL >> 1) & 1) ? 0xffff : 0;
	8884	m_vflag[2][2] = ((RTVAL >> 2) & 1) ? 0xffff : 0;
	8885	m_vflag[2][3] = ((RTVAL >> 3) & 1) ? 0xffff : 0;
	8886	m_vflag[2][4] = ((RTVAL >> 4) & 1) ? 0xffff : 0;
	8887	m_vflag[2][5] = ((RTVAL >> 5) & 1) ? 0xffff : 0;
	8888	m_vflag[2][6] = ((RTVAL >> 6) & 1) ? 0xffff : 0;
	8889	m_vflag[2][7] = ((RTVAL >> 7) & 1) ? 0xffff : 0;
8693	8890	if (RTVAL & (1 << 0)) { VEC_SET_CLIP1_FLAG(0); }
8694	8891	if (RTVAL & (1 << 1)) { VEC_SET_CLIP1_FLAG(1); }
8695	8892	if (RTVAL & (1 << 2)) { VEC_SET_CLIP1_FLAG(2); }
r31833	r31834
8701	8898	break;
8702	8899	}
8703	8900	}
	8901
	8902	static void cfunc_ctc2_simd(void *param)
	8903	{
	8904	((rsp_device *)param)->ccfunc_ctc2_simd();
	8905	}
8704	8906	#endif
8705	8907
8706	8908	#if (!USE_SIMD || SIMUL_SIMD)
8707		static void cfunc_ctc2_scalar(void *param)
	8909	inline void rsp_device::ccfunc_ctc2_scalar()
8708	8910	{
8709		rsp_state *rsp = (rsp_state*)param;
8710		UINT32 op = rsp->impstate->arg0;
	8911	UINT32 op = m_rsp_state->arg0;
8711	8912	switch(RDREG)
8712	8913	{
8713	8914	case 0:
8714	8915	CLEAR_CARRY_FLAGS();
8715	8916	CLEAR_ZERO_FLAGS();
8716		rsp->vflag[0][0] = ((RTVAL >> 0) & 1) ? 0xffff : 0;
8717		rsp->vflag[0][1] = ((RTVAL >> 1) & 1) ? 0xffff : 0;
8718		rsp->vflag[0][2] = ((RTVAL >> 2) & 1) ? 0xffff : 0;
8719		rsp->vflag[0][3] = ((RTVAL >> 3) & 1) ? 0xffff : 0;
8720		rsp->vflag[0][4] = ((RTVAL >> 4) & 1) ? 0xffff : 0;
8721		rsp->vflag[0][5] = ((RTVAL >> 5) & 1) ? 0xffff : 0;
8722		rsp->vflag[0][6] = ((RTVAL >> 6) & 1) ? 0xffff : 0;
8723		rsp->vflag[0][7] = ((RTVAL >> 7) & 1) ? 0xffff : 0;
	8917	m_vflag[0][0] = ((RTVAL >> 0) & 1) ? 0xffff : 0;
	8918	m_vflag[0][1] = ((RTVAL >> 1) & 1) ? 0xffff : 0;
	8919	m_vflag[0][2] = ((RTVAL >> 2) & 1) ? 0xffff : 0;
	8920	m_vflag[0][3] = ((RTVAL >> 3) & 1) ? 0xffff : 0;
	8921	m_vflag[0][4] = ((RTVAL >> 4) & 1) ? 0xffff : 0;
	8922	m_vflag[0][5] = ((RTVAL >> 5) & 1) ? 0xffff : 0;
	8923	m_vflag[0][6] = ((RTVAL >> 6) & 1) ? 0xffff : 0;
	8924	m_vflag[0][7] = ((RTVAL >> 7) & 1) ? 0xffff : 0;
8724	8925	if (RTVAL & (1 << 0))  { SET_CARRY_FLAG(0); }
8725	8926	if (RTVAL & (1 << 1))  { SET_CARRY_FLAG(1); }
8726	8927	if (RTVAL & (1 << 2))  { SET_CARRY_FLAG(2); }
r31833	r31834
8729	8930	if (RTVAL & (1 << 5))  { SET_CARRY_FLAG(5); }
8730	8931	if (RTVAL & (1 << 6))  { SET_CARRY_FLAG(6); }
8731	8932	if (RTVAL & (1 << 7))  { SET_CARRY_FLAG(7); }
8732		rsp->vflag[3][0] = ((RTVAL >> 8) & 1) ? 0xffff : 0;
8733		rsp->vflag[3][1] = ((RTVAL >> 9) & 1) ? 0xffff : 0;
8734		rsp->vflag[3][2] = ((RTVAL >> 10) & 1) ? 0xffff : 0;
8735		rsp->vflag[3][3] = ((RTVAL >> 11) & 1) ? 0xffff : 0;
8736		rsp->vflag[3][4] = ((RTVAL >> 12) & 1) ? 0xffff : 0;
8737		rsp->vflag[3][5] = ((RTVAL >> 13) & 1) ? 0xffff : 0;
8738		rsp->vflag[3][6] = ((RTVAL >> 14) & 1) ? 0xffff : 0;
8739		rsp->vflag[3][7] = ((RTVAL >> 15) & 1) ? 0xffff : 0;
	8933	m_vflag[3][0] = ((RTVAL >> 8) & 1) ? 0xffff : 0;
	8934	m_vflag[3][1] = ((RTVAL >> 9) & 1) ? 0xffff : 0;
	8935	m_vflag[3][2] = ((RTVAL >> 10) & 1) ? 0xffff : 0;
	8936	m_vflag[3][3] = ((RTVAL >> 11) & 1) ? 0xffff : 0;
	8937	m_vflag[3][4] = ((RTVAL >> 12) & 1) ? 0xffff : 0;
	8938	m_vflag[3][5] = ((RTVAL >> 13) & 1) ? 0xffff : 0;
	8939	m_vflag[3][6] = ((RTVAL >> 14) & 1) ? 0xffff : 0;
	8940	m_vflag[3][7] = ((RTVAL >> 15) & 1) ? 0xffff : 0;
8740	8941	if (RTVAL & (1 << 8))  { SET_ZERO_FLAG(0); }
8741	8942	if (RTVAL & (1 << 9))  { SET_ZERO_FLAG(1); }
8742	8943	if (RTVAL & (1 << 10)) { SET_ZERO_FLAG(2); }
r31833	r31834
8749	8950	case 1:
8750	8951	CLEAR_COMPARE_FLAGS();
8751	8952	CLEAR_CLIP2_FLAGS();
8752		rsp->vflag[1][0] = ((RTVAL >> 0) & 1) ? 0xffff : 0;
8753		rsp->vflag[1][1] = ((RTVAL >> 1) & 1) ? 0xffff : 0;
8754		rsp->vflag[1][2] = ((RTVAL >> 2) & 1) ? 0xffff : 0;
8755		rsp->vflag[1][3] = ((RTVAL >> 3) & 1) ? 0xffff : 0;
8756		rsp->vflag[1][4] = ((RTVAL >> 4) & 1) ? 0xffff : 0;
8757		rsp->vflag[1][5] = ((RTVAL >> 5) & 1) ? 0xffff : 0;
8758		rsp->vflag[1][6] = ((RTVAL >> 6) & 1) ? 0xffff : 0;
8759		rsp->vflag[1][7] = ((RTVAL >> 7) & 1) ? 0xffff : 0;
	8953	m_vflag[1][0] = ((RTVAL >> 0) & 1) ? 0xffff : 0;
	8954	m_vflag[1][1] = ((RTVAL >> 1) & 1) ? 0xffff : 0;
	8955	m_vflag[1][2] = ((RTVAL >> 2) & 1) ? 0xffff : 0;
	8956	m_vflag[1][3] = ((RTVAL >> 3) & 1) ? 0xffff : 0;
	8957	m_vflag[1][4] = ((RTVAL >> 4) & 1) ? 0xffff : 0;
	8958	m_vflag[1][5] = ((RTVAL >> 5) & 1) ? 0xffff : 0;
	8959	m_vflag[1][6] = ((RTVAL >> 6) & 1) ? 0xffff : 0;
	8960	m_vflag[1][7] = ((RTVAL >> 7) & 1) ? 0xffff : 0;
8760	8961	if (RTVAL & (1 << 0)) { SET_COMPARE_FLAG(0); }
8761	8962	if (RTVAL & (1 << 1)) { SET_COMPARE_FLAG(1); }
8762	8963	if (RTVAL & (1 << 2)) { SET_COMPARE_FLAG(2); }
r31833	r31834
8765	8966	if (RTVAL & (1 << 5)) { SET_COMPARE_FLAG(5); }
8766	8967	if (RTVAL & (1 << 6)) { SET_COMPARE_FLAG(6); }
8767	8968	if (RTVAL & (1 << 7)) { SET_COMPARE_FLAG(7); }
8768		rsp->vflag[4][0] = ((RTVAL >> 8) & 1) ? 0xffff : 0;
8769		rsp->vflag[4][1] = ((RTVAL >> 9) & 1) ? 0xffff : 0;
8770		rsp->vflag[4][2] = ((RTVAL >> 10) & 1) ? 0xffff : 0;
8771		rsp->vflag[4][3] = ((RTVAL >> 11) & 1) ? 0xffff : 0;
8772		rsp->vflag[4][4] = ((RTVAL >> 12) & 1) ? 0xffff : 0;
8773		rsp->vflag[4][5] = ((RTVAL >> 13) & 1) ? 0xffff : 0;
8774		rsp->vflag[4][6] = ((RTVAL >> 14) & 1) ? 0xffff : 0;
8775		rsp->vflag[4][7] = ((RTVAL >> 15) & 1) ? 0xffff : 0;
	8969	m_vflag[4][0] = ((RTVAL >> 8) & 1) ? 0xffff : 0;
	8970	m_vflag[4][1] = ((RTVAL >> 9) & 1) ? 0xffff : 0;
	8971	m_vflag[4][2] = ((RTVAL >> 10) & 1) ? 0xffff : 0;
	8972	m_vflag[4][3] = ((RTVAL >> 11) & 1) ? 0xffff : 0;
	8973	m_vflag[4][4] = ((RTVAL >> 12) & 1) ? 0xffff : 0;
	8974	m_vflag[4][5] = ((RTVAL >> 13) & 1) ? 0xffff : 0;
	8975	m_vflag[4][6] = ((RTVAL >> 14) & 1) ? 0xffff : 0;
	8976	m_vflag[4][7] = ((RTVAL >> 15) & 1) ? 0xffff : 0;
8776	8977	if (RTVAL & (1 << 8))  { SET_CLIP2_FLAG(0); }
8777	8978	if (RTVAL & (1 << 9))  { SET_CLIP2_FLAG(1); }
8778	8979	if (RTVAL & (1 << 10)) { SET_CLIP2_FLAG(2); }
r31833	r31834
8784	8985	break;
8785	8986	case 2:
8786	8987	CLEAR_CLIP1_FLAGS();
8787		rsp->vflag[2][0] = ((RTVAL >> 0) & 1) ? 0xffff : 0;
8788		rsp->vflag[2][1] = ((RTVAL >> 1) & 1) ? 0xffff : 0;
8789		rsp->vflag[2][2] = ((RTVAL >> 2) & 1) ? 0xffff : 0;
8790		rsp->vflag[2][3] = ((RTVAL >> 3) & 1) ? 0xffff : 0;
8791		rsp->vflag[2][4] = ((RTVAL >> 4) & 1) ? 0xffff : 0;
8792		rsp->vflag[2][5] = ((RTVAL >> 5) & 1) ? 0xffff : 0;
8793		rsp->vflag[2][6] = ((RTVAL >> 6) & 1) ? 0xffff : 0;
8794		rsp->vflag[2][7] = ((RTVAL >> 7) & 1) ? 0xffff : 0;
	8988	m_vflag[2][0] = ((RTVAL >> 0) & 1) ? 0xffff : 0;
	8989	m_vflag[2][1] = ((RTVAL >> 1) & 1) ? 0xffff : 0;
	8990	m_vflag[2][2] = ((RTVAL >> 2) & 1) ? 0xffff : 0;
	8991	m_vflag[2][3] = ((RTVAL >> 3) & 1) ? 0xffff : 0;
	8992	m_vflag[2][4] = ((RTVAL >> 4) & 1) ? 0xffff : 0;
	8993	m_vflag[2][5] = ((RTVAL >> 5) & 1) ? 0xffff : 0;
	8994	m_vflag[2][6] = ((RTVAL >> 6) & 1) ? 0xffff : 0;
	8995	m_vflag[2][7] = ((RTVAL >> 7) & 1) ? 0xffff : 0;
8795	8996	if (RTVAL & (1 << 0)) { SET_CLIP1_FLAG(0); }
8796	8997	if (RTVAL & (1 << 1)) { SET_CLIP1_FLAG(1); }
8797	8998	if (RTVAL & (1 << 2)) { SET_CLIP1_FLAG(2); }
r31833	r31834
8803	9004	break;
8804	9005	}
8805	9006	}
	9007
	9008	static void cfunc_ctc2_scalar(void *param)
	9009	{
	9010	((rsp_device *)param)->ccfunc_ctc2_scalar();
	9011	}
8806	9012	#endif
8807	9013
8808	9014	/***************************************************************************
r31833	r31834
8814	9020	including disassembly of a RSP instruction
8815	9021	-------------------------------------------------*/
8816	9022
8817		static void log_add_disasm_comment(rsp_state *rsp, drcuml_block *block, UINT32 pc, UINT32 op)
	9023	void rsp_device::log_add_disasm_comment(drcuml_block *block, UINT32 pc, UINT32 op)
8818	9024	{
8819		#if (LOG_UML)
	9025	#if (RSP_LOG_UML)
8820	9026	char buffer[100];
8821	9027	rsp_dasm_one(buffer, pc, op);
8822	9028	block->append_comment("%08X: %s", pc, buffer);                                  // comment
8823	9029	#endif
8824	9030	}
8825	9031
8826
8827		static CPU_SET_INFO( rsp )
8828		{
8829		rsp_state *rsp = get_safe_token(device);
8830
8831		switch (state)
8832		{
8833		/* --- the following bits of info are set as 64-bit signed integers --- */
8834		case CPUINFO_INT_PC:
8835		case CPUINFO_INT_REGISTER + RSP_PC:             rsp->pc = info->i;        break;
8836		case CPUINFO_INT_REGISTER + RSP_R0:             rsp->r[0] = info->i;        break;
8837		case CPUINFO_INT_REGISTER + RSP_R1:             rsp->r[1] = info->i;        break;
8838		case CPUINFO_INT_REGISTER + RSP_R2:             rsp->r[2] = info->i;        break;
8839		case CPUINFO_INT_REGISTER + RSP_R3:             rsp->r[3] = info->i;        break;
8840		case CPUINFO_INT_REGISTER + RSP_R4:             rsp->r[4] = info->i;        break;
8841		case CPUINFO_INT_REGISTER + RSP_R5:             rsp->r[5] = info->i;        break;
8842		case CPUINFO_INT_REGISTER + RSP_R6:             rsp->r[6] = info->i;        break;
8843		case CPUINFO_INT_REGISTER + RSP_R7:             rsp->r[7] = info->i;        break;
8844		case CPUINFO_INT_REGISTER + RSP_R8:             rsp->r[8] = info->i;        break;
8845		case CPUINFO_INT_REGISTER + RSP_R9:             rsp->r[9] = info->i;        break;
8846		case CPUINFO_INT_REGISTER + RSP_R10:            rsp->r[10] = info->i;        break;
8847		case CPUINFO_INT_REGISTER + RSP_R11:            rsp->r[11] = info->i;        break;
8848		case CPUINFO_INT_REGISTER + RSP_R12:            rsp->r[12] = info->i;        break;
8849		case CPUINFO_INT_REGISTER + RSP_R13:            rsp->r[13] = info->i;        break;
8850		case CPUINFO_INT_REGISTER + RSP_R14:            rsp->r[14] = info->i;        break;
8851		case CPUINFO_INT_REGISTER + RSP_R15:            rsp->r[15] = info->i;        break;
8852		case CPUINFO_INT_REGISTER + RSP_R16:            rsp->r[16] = info->i;        break;
8853		case CPUINFO_INT_REGISTER + RSP_R17:            rsp->r[17] = info->i;        break;
8854		case CPUINFO_INT_REGISTER + RSP_R18:            rsp->r[18] = info->i;        break;
8855		case CPUINFO_INT_REGISTER + RSP_R19:            rsp->r[19] = info->i;        break;
8856		case CPUINFO_INT_REGISTER + RSP_R20:            rsp->r[20] = info->i;        break;
8857		case CPUINFO_INT_REGISTER + RSP_R21:            rsp->r[21] = info->i;        break;
8858		case CPUINFO_INT_REGISTER + RSP_R22:            rsp->r[22] = info->i;        break;
8859		case CPUINFO_INT_REGISTER + RSP_R23:            rsp->r[23] = info->i;        break;
8860		case CPUINFO_INT_REGISTER + RSP_R24:            rsp->r[24] = info->i;        break;
8861		case CPUINFO_INT_REGISTER + RSP_R25:            rsp->r[25] = info->i;        break;
8862		case CPUINFO_INT_REGISTER + RSP_R26:            rsp->r[26] = info->i;        break;
8863		case CPUINFO_INT_REGISTER + RSP_R27:            rsp->r[27] = info->i;        break;
8864		case CPUINFO_INT_REGISTER + RSP_R28:            rsp->r[28] = info->i;        break;
8865		case CPUINFO_INT_REGISTER + RSP_R29:            rsp->r[29] = info->i;        break;
8866		case CPUINFO_INT_REGISTER + RSP_R30:            rsp->r[30] = info->i;        break;
8867		case CPUINFO_INT_SP:
8868		case CPUINFO_INT_REGISTER + RSP_R31:            rsp->r[31] = info->i;        break;
8869		case CPUINFO_INT_REGISTER + RSP_SR:             rsp->sr = info->i;           break;
8870		case CPUINFO_INT_REGISTER + RSP_NEXTPC:         rsp->nextpc = info->i;       break;
8871		case CPUINFO_INT_REGISTER + RSP_STEPCNT:        rsp->step_count = info->i;   break;
8872		}
8873		}
8874
8875		CPU_GET_INFO( rsp_drc )
8876		{
8877		rsp_state *rsp = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
8878
8879		switch(state)
8880		{
8881		/* --- the following bits of info are returned as 64-bit signed integers --- */
8882		case CPUINFO_INT_CONTEXT_SIZE:                  info->i = sizeof(rsp_state);                    break;
8883		case CPUINFO_INT_INPUT_LINES:                   info->i = 1;                            break;
8884		case CPUINFO_INT_DEFAULT_IRQ_VECTOR:            info->i = 0;                            break;
8885		case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_BIG;               break;
8886		case CPUINFO_INT_CLOCK_MULTIPLIER:              info->i = 1;                            break;
8887		case CPUINFO_INT_CLOCK_DIVIDER:                 info->i = 1;                            break;
8888		case CPUINFO_INT_MIN_INSTRUCTION_BYTES:         info->i = 4;                            break;
8889		case CPUINFO_INT_MAX_INSTRUCTION_BYTES:         info->i = 4;                            break;
8890		case CPUINFO_INT_MIN_CYCLES:                    info->i = 1;                            break;
8891		case CPUINFO_INT_MAX_CYCLES:                    info->i = 1;                            break;
8892
8893		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:    info->i = 32;                   break;
8894		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32;                  break;
8895		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0;                   break;
8896		case CPUINFO_INT_DATABUS_WIDTH + AS_DATA:   info->i = 0;                    break;
8897		case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA:   info->i = 0;                    break;
8898		case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA:   info->i = 0;                    break;
8899		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:     info->i = 0;                    break;
8900		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO:     info->i = 0;                    break;
8901		case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO:     info->i = 0;                    break;
8902
8903		case CPUINFO_INT_INPUT_STATE:                   info->i = CLEAR_LINE;                   break;
8904
8905		case CPUINFO_INT_PREVIOUSPC:                    info->i = rsp->ppc | 0x04000000;                        break;
8906
8907		case CPUINFO_INT_PC:    /* intentional fallthrough */
8908		case CPUINFO_INT_REGISTER + RSP_PC:             info->i = rsp->pc | 0x04000000;                     break;
8909
8910		case CPUINFO_INT_REGISTER + RSP_R0:             info->i = rsp->r[0];                        break;
8911		case CPUINFO_INT_REGISTER + RSP_R1:             info->i = rsp->r[1];                        break;
8912		case CPUINFO_INT_REGISTER + RSP_R2:             info->i = rsp->r[2];                        break;
8913		case CPUINFO_INT_REGISTER + RSP_R3:             info->i = rsp->r[3];                        break;
8914		case CPUINFO_INT_REGISTER + RSP_R4:             info->i = rsp->r[4];                        break;
8915		case CPUINFO_INT_REGISTER + RSP_R5:             info->i = rsp->r[5];                        break;
8916		case CPUINFO_INT_REGISTER + RSP_R6:             info->i = rsp->r[6];                        break;
8917		case CPUINFO_INT_REGISTER + RSP_R7:             info->i = rsp->r[7];                        break;
8918		case CPUINFO_INT_REGISTER + RSP_R8:             info->i = rsp->r[8];                        break;
8919		case CPUINFO_INT_REGISTER + RSP_R9:             info->i = rsp->r[9];                        break;
8920		case CPUINFO_INT_REGISTER + RSP_R10:            info->i = rsp->r[10];                   break;
8921		case CPUINFO_INT_REGISTER + RSP_R11:            info->i = rsp->r[11];                   break;
8922		case CPUINFO_INT_REGISTER + RSP_R12:            info->i = rsp->r[12];                   break;
8923		case CPUINFO_INT_REGISTER + RSP_R13:            info->i = rsp->r[13];                   break;
8924		case CPUINFO_INT_REGISTER + RSP_R14:            info->i = rsp->r[14];                   break;
8925		case CPUINFO_INT_REGISTER + RSP_R15:            info->i = rsp->r[15];                   break;
8926		case CPUINFO_INT_REGISTER + RSP_R16:            info->i = rsp->r[16];                   break;
8927		case CPUINFO_INT_REGISTER + RSP_R17:            info->i = rsp->r[17];                   break;
8928		case CPUINFO_INT_REGISTER + RSP_R18:            info->i = rsp->r[18];                   break;
8929		case CPUINFO_INT_REGISTER + RSP_R19:            info->i = rsp->r[19];                   break;
8930		case CPUINFO_INT_REGISTER + RSP_R20:            info->i = rsp->r[20];                   break;
8931		case CPUINFO_INT_REGISTER + RSP_R21:            info->i = rsp->r[21];                   break;
8932		case CPUINFO_INT_REGISTER + RSP_R22:            info->i = rsp->r[22];                   break;
8933		case CPUINFO_INT_REGISTER + RSP_R23:            info->i = rsp->r[23];                   break;
8934		case CPUINFO_INT_REGISTER + RSP_R24:            info->i = rsp->r[24];                   break;
8935		case CPUINFO_INT_REGISTER + RSP_R25:            info->i = rsp->r[25];                   break;
8936		case CPUINFO_INT_REGISTER + RSP_R26:            info->i = rsp->r[26];                   break;
8937		case CPUINFO_INT_REGISTER + RSP_R27:            info->i = rsp->r[27];                   break;
8938		case CPUINFO_INT_REGISTER + RSP_R28:            info->i = rsp->r[28];                   break;
8939		case CPUINFO_INT_REGISTER + RSP_R29:            info->i = rsp->r[29];                   break;
8940		case CPUINFO_INT_REGISTER + RSP_R30:            info->i = rsp->r[30];                   break;
8941		case CPUINFO_INT_SP:
8942		case CPUINFO_INT_REGISTER + RSP_R31:            info->i = rsp->r[31];                    break;
8943		case CPUINFO_INT_REGISTER + RSP_SR:             info->i = rsp->sr;                       break;
8944		case CPUINFO_INT_REGISTER + RSP_NEXTPC:         info->i = rsp->nextpc | 0x04000000;      break;
8945		case CPUINFO_INT_REGISTER + RSP_STEPCNT:        info->i = rsp->step_count;               break;
8946
8947		/* --- the following bits of info are returned as pointers to data or functions --- */
8948		case CPUINFO_FCT_SET_INFO:                      info->setinfo = CPU_SET_INFO_NAME(rsp);         break;
8949		case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(rsp);                    break;
8950		case CPUINFO_FCT_RESET:                         info->reset = CPU_RESET_NAME(rsp);              break;
8951		case CPUINFO_FCT_EXIT:                          info->exit = CPU_EXIT_NAME(rsp);                    break;
8952		case CPUINFO_FCT_EXECUTE:                       info->execute = CPU_EXECUTE_NAME(rsp);          break;
8953		case CPUINFO_FCT_BURN:                          info->burn = NULL;                      break;
8954		case CPUINFO_FCT_DISASSEMBLE:                   info->disassemble = CPU_DISASSEMBLE_NAME(rsp);          break;
8955		case CPUINFO_PTR_INSTRUCTION_COUNTER:           info->icount = &rsp->icount;                break;
8956
8957		/* --- the following bits of info are returned as NULL-terminated strings --- */
8958		case CPUINFO_STR_NAME:                          strcpy(info->s, "RSP DRC");                 break;
8959		case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "rsp_drc");                 break;
8960		case CPUINFO_STR_FAMILY:                    strcpy(info->s, "RSP");                 break;
8961		case CPUINFO_STR_VERSION:                   strcpy(info->s, "1.0");                 break;
8962		case CPUINFO_STR_SOURCE_FILE:                       strcpy(info->s, __FILE__);              break;
8963		case CPUINFO_STR_CREDITS:                   strcpy(info->s, "Copyright Nicola Salmoria and the MAME Team"); break;
8964
8965		case CPUINFO_STR_FLAGS:                         strcpy(info->s, " ");                   break;
8966
8967		case CPUINFO_STR_REGISTER + RSP_PC:             sprintf(info->s, "PC: %08X", rsp->pc | 0x04000000); break;
8968
8969		case CPUINFO_STR_REGISTER + RSP_R0:             sprintf(info->s, "R0: %08X", rsp->r[0]); break;
8970		case CPUINFO_STR_REGISTER + RSP_R1:             sprintf(info->s, "R1: %08X", rsp->r[1]); break;
8971		case CPUINFO_STR_REGISTER + RSP_R2:             sprintf(info->s, "R2: %08X", rsp->r[2]); break;
8972		case CPUINFO_STR_REGISTER + RSP_R3:             sprintf(info->s, "R3: %08X", rsp->r[3]); break;
8973		case CPUINFO_STR_REGISTER + RSP_R4:             sprintf(info->s, "R4: %08X", rsp->r[4]); break;
8974		case CPUINFO_STR_REGISTER + RSP_R5:             sprintf(info->s, "R5: %08X", rsp->r[5]); break;
8975		case CPUINFO_STR_REGISTER + RSP_R6:             sprintf(info->s, "R6: %08X", rsp->r[6]); break;
8976		case CPUINFO_STR_REGISTER + RSP_R7:             sprintf(info->s, "R7: %08X", rsp->r[7]); break;
8977		case CPUINFO_STR_REGISTER + RSP_R8:             sprintf(info->s, "R8: %08X", rsp->r[8]); break;
8978		case CPUINFO_STR_REGISTER + RSP_R9:             sprintf(info->s, "R9: %08X", rsp->r[9]); break;
8979		case CPUINFO_STR_REGISTER + RSP_R10:            sprintf(info->s, "R10: %08X", rsp->r[10]); break;
8980		case CPUINFO_STR_REGISTER + RSP_R11:            sprintf(info->s, "R11: %08X", rsp->r[11]); break;
8981		case CPUINFO_STR_REGISTER + RSP_R12:            sprintf(info->s, "R12: %08X", rsp->r[12]); break;
8982		case CPUINFO_STR_REGISTER + RSP_R13:            sprintf(info->s, "R13: %08X", rsp->r[13]); break;
8983		case CPUINFO_STR_REGISTER + RSP_R14:            sprintf(info->s, "R14: %08X", rsp->r[14]); break;
8984		case CPUINFO_STR_REGISTER + RSP_R15:            sprintf(info->s, "R15: %08X", rsp->r[15]); break;
8985		case CPUINFO_STR_REGISTER + RSP_R16:            sprintf(info->s, "R16: %08X", rsp->r[16]); break;
8986		case CPUINFO_STR_REGISTER + RSP_R17:            sprintf(info->s, "R17: %08X", rsp->r[17]); break;
8987		case CPUINFO_STR_REGISTER + RSP_R18:            sprintf(info->s, "R18: %08X", rsp->r[18]); break;
8988		case CPUINFO_STR_REGISTER + RSP_R19:            sprintf(info->s, "R19: %08X", rsp->r[19]); break;
8989		case CPUINFO_STR_REGISTER + RSP_R20:            sprintf(info->s, "R20: %08X", rsp->r[20]); break;
8990		case CPUINFO_STR_REGISTER + RSP_R21:            sprintf(info->s, "R21: %08X", rsp->r[21]); break;
8991		case CPUINFO_STR_REGISTER + RSP_R22:            sprintf(info->s, "R22: %08X", rsp->r[22]); break;
8992		case CPUINFO_STR_REGISTER + RSP_R23:            sprintf(info->s, "R23: %08X", rsp->r[23]); break;
8993		case CPUINFO_STR_REGISTER + RSP_R24:            sprintf(info->s, "R24: %08X", rsp->r[24]); break;
8994		case CPUINFO_STR_REGISTER + RSP_R25:            sprintf(info->s, "R25: %08X", rsp->r[25]); break;
8995		case CPUINFO_STR_REGISTER + RSP_R26:            sprintf(info->s, "R26: %08X", rsp->r[26]); break;
8996		case CPUINFO_STR_REGISTER + RSP_R27:            sprintf(info->s, "R27: %08X", rsp->r[27]); break;
8997		case CPUINFO_STR_REGISTER + RSP_R28:            sprintf(info->s, "R28: %08X", rsp->r[28]); break;
8998		case CPUINFO_STR_REGISTER + RSP_R29:            sprintf(info->s, "R29: %08X", rsp->r[29]); break;
8999		case CPUINFO_STR_REGISTER + RSP_R30:            sprintf(info->s, "R30: %08X", rsp->r[30]); break;
9000		case CPUINFO_STR_REGISTER + RSP_R31:            sprintf(info->s, "R31: %08X", rsp->r[31]); break;
9001
9002		#if USE_SIMD
9003		case CPUINFO_STR_REGISTER + RSP_V0:             sprintf(info->s, "V0: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X",  (UINT16)_mm_extract_epi16(rsp->xv[ 0], 7), (UINT16)_mm_extract_epi16(rsp->xv[ 0], 6), (UINT16)_mm_extract_epi16(rsp->xv[ 0], 5), (UINT16)_mm_extract_epi16(rsp->xv[ 0], 4), (UINT16)_mm_extract_epi16(rsp->xv[ 0], 3), (UINT16)_mm_extract_epi16(rsp->xv[ 0], 2), (UINT16)_mm_extract_epi16(rsp->xv[ 0], 1), (UINT16)_mm_extract_epi16(rsp->xv[ 0], 0)); break;
9004		case CPUINFO_STR_REGISTER + RSP_V1:             sprintf(info->s, "V1: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X",  (UINT16)_mm_extract_epi16(rsp->xv[ 1], 7), (UINT16)_mm_extract_epi16(rsp->xv[ 1], 6), (UINT16)_mm_extract_epi16(rsp->xv[ 1], 5), (UINT16)_mm_extract_epi16(rsp->xv[ 1], 4), (UINT16)_mm_extract_epi16(rsp->xv[ 1], 3), (UINT16)_mm_extract_epi16(rsp->xv[ 1], 2), (UINT16)_mm_extract_epi16(rsp->xv[ 1], 1), (UINT16)_mm_extract_epi16(rsp->xv[ 1], 0)); break;
9005		case CPUINFO_STR_REGISTER + RSP_V2:             sprintf(info->s, "V2: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X",  (UINT16)_mm_extract_epi16(rsp->xv[ 2], 7), (UINT16)_mm_extract_epi16(rsp->xv[ 2], 6), (UINT16)_mm_extract_epi16(rsp->xv[ 2], 5), (UINT16)_mm_extract_epi16(rsp->xv[ 2], 4), (UINT16)_mm_extract_epi16(rsp->xv[ 2], 3), (UINT16)_mm_extract_epi16(rsp->xv[ 2], 2), (UINT16)_mm_extract_epi16(rsp->xv[ 2], 1), (UINT16)_mm_extract_epi16(rsp->xv[ 2], 0)); break;
9006		case CPUINFO_STR_REGISTER + RSP_V3:             sprintf(info->s, "V3: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X",  (UINT16)_mm_extract_epi16(rsp->xv[ 3], 7), (UINT16)_mm_extract_epi16(rsp->xv[ 3], 6), (UINT16)_mm_extract_epi16(rsp->xv[ 3], 5), (UINT16)_mm_extract_epi16(rsp->xv[ 3], 4), (UINT16)_mm_extract_epi16(rsp->xv[ 3], 3), (UINT16)_mm_extract_epi16(rsp->xv[ 3], 2), (UINT16)_mm_extract_epi16(rsp->xv[ 3], 1), (UINT16)_mm_extract_epi16(rsp->xv[ 3], 0)); break;
9007		case CPUINFO_STR_REGISTER + RSP_V4:             sprintf(info->s, "V4: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X",  (UINT16)_mm_extract_epi16(rsp->xv[ 4], 7), (UINT16)_mm_extract_epi16(rsp->xv[ 4], 6), (UINT16)_mm_extract_epi16(rsp->xv[ 4], 5), (UINT16)_mm_extract_epi16(rsp->xv[ 4], 4), (UINT16)_mm_extract_epi16(rsp->xv[ 4], 3), (UINT16)_mm_extract_epi16(rsp->xv[ 4], 2), (UINT16)_mm_extract_epi16(rsp->xv[ 4], 1), (UINT16)_mm_extract_epi16(rsp->xv[ 4], 0)); break;
9008		case CPUINFO_STR_REGISTER + RSP_V5:             sprintf(info->s, "V5: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X",  (UINT16)_mm_extract_epi16(rsp->xv[ 5], 7), (UINT16)_mm_extract_epi16(rsp->xv[ 5], 6), (UINT16)_mm_extract_epi16(rsp->xv[ 5], 5), (UINT16)_mm_extract_epi16(rsp->xv[ 5], 4), (UINT16)_mm_extract_epi16(rsp->xv[ 5], 3), (UINT16)_mm_extract_epi16(rsp->xv[ 5], 2), (UINT16)_mm_extract_epi16(rsp->xv[ 5], 1), (UINT16)_mm_extract_epi16(rsp->xv[ 5], 0)); break;
9009		case CPUINFO_STR_REGISTER + RSP_V6:             sprintf(info->s, "V6: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X",  (UINT16)_mm_extract_epi16(rsp->xv[ 6], 7), (UINT16)_mm_extract_epi16(rsp->xv[ 6], 6), (UINT16)_mm_extract_epi16(rsp->xv[ 6], 5), (UINT16)_mm_extract_epi16(rsp->xv[ 6], 4), (UINT16)_mm_extract_epi16(rsp->xv[ 6], 3), (UINT16)_mm_extract_epi16(rsp->xv[ 6], 2), (UINT16)_mm_extract_epi16(rsp->xv[ 6], 1), (UINT16)_mm_extract_epi16(rsp->xv[ 6], 0)); break;
9010		case CPUINFO_STR_REGISTER + RSP_V7:             sprintf(info->s, "V7: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X",  (UINT16)_mm_extract_epi16(rsp->xv[ 7], 7), (UINT16)_mm_extract_epi16(rsp->xv[ 7], 6), (UINT16)_mm_extract_epi16(rsp->xv[ 7], 5), (UINT16)_mm_extract_epi16(rsp->xv[ 7], 4), (UINT16)_mm_extract_epi16(rsp->xv[ 7], 3), (UINT16)_mm_extract_epi16(rsp->xv[ 7], 2), (UINT16)_mm_extract_epi16(rsp->xv[ 7], 1), (UINT16)_mm_extract_epi16(rsp->xv[ 7], 0)); break;
9011		case CPUINFO_STR_REGISTER + RSP_V8:             sprintf(info->s, "V8: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X",  (UINT16)_mm_extract_epi16(rsp->xv[ 8], 7), (UINT16)_mm_extract_epi16(rsp->xv[ 8], 6), (UINT16)_mm_extract_epi16(rsp->xv[ 8], 5), (UINT16)_mm_extract_epi16(rsp->xv[ 8], 4), (UINT16)_mm_extract_epi16(rsp->xv[ 8], 3), (UINT16)_mm_extract_epi16(rsp->xv[ 8], 2), (UINT16)_mm_extract_epi16(rsp->xv[ 8], 1), (UINT16)_mm_extract_epi16(rsp->xv[ 8], 0)); break;
9012		case CPUINFO_STR_REGISTER + RSP_V9:             sprintf(info->s, "V9: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X",  (UINT16)_mm_extract_epi16(rsp->xv[ 9], 7), (UINT16)_mm_extract_epi16(rsp->xv[ 9], 6), (UINT16)_mm_extract_epi16(rsp->xv[ 9], 5), (UINT16)_mm_extract_epi16(rsp->xv[ 9], 4), (UINT16)_mm_extract_epi16(rsp->xv[ 9], 3), (UINT16)_mm_extract_epi16(rsp->xv[ 9], 2), (UINT16)_mm_extract_epi16(rsp->xv[ 9], 1), (UINT16)_mm_extract_epi16(rsp->xv[ 9], 0)); break;
9013		case CPUINFO_STR_REGISTER + RSP_V10:            sprintf(info->s, "V10: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(rsp->xv[10], 7), (UINT16)_mm_extract_epi16(rsp->xv[10], 6), (UINT16)_mm_extract_epi16(rsp->xv[10], 5), (UINT16)_mm_extract_epi16(rsp->xv[10], 4), (UINT16)_mm_extract_epi16(rsp->xv[10], 3), (UINT16)_mm_extract_epi16(rsp->xv[10], 2), (UINT16)_mm_extract_epi16(rsp->xv[10], 1), (UINT16)_mm_extract_epi16(rsp->xv[10], 0)); break;
9014		case CPUINFO_STR_REGISTER + RSP_V11:            sprintf(info->s, "V11: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(rsp->xv[11], 7), (UINT16)_mm_extract_epi16(rsp->xv[11], 6), (UINT16)_mm_extract_epi16(rsp->xv[11], 5), (UINT16)_mm_extract_epi16(rsp->xv[11], 4), (UINT16)_mm_extract_epi16(rsp->xv[11], 3), (UINT16)_mm_extract_epi16(rsp->xv[11], 2), (UINT16)_mm_extract_epi16(rsp->xv[11], 1), (UINT16)_mm_extract_epi16(rsp->xv[11], 0)); break;
9015		case CPUINFO_STR_REGISTER + RSP_V12:            sprintf(info->s, "V12: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(rsp->xv[12], 7), (UINT16)_mm_extract_epi16(rsp->xv[12], 6), (UINT16)_mm_extract_epi16(rsp->xv[12], 5), (UINT16)_mm_extract_epi16(rsp->xv[12], 4), (UINT16)_mm_extract_epi16(rsp->xv[12], 3), (UINT16)_mm_extract_epi16(rsp->xv[12], 2), (UINT16)_mm_extract_epi16(rsp->xv[12], 1), (UINT16)_mm_extract_epi16(rsp->xv[12], 0)); break;
9016		case CPUINFO_STR_REGISTER + RSP_V13:            sprintf(info->s, "V13: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(rsp->xv[13], 7), (UINT16)_mm_extract_epi16(rsp->xv[13], 6), (UINT16)_mm_extract_epi16(rsp->xv[13], 5), (UINT16)_mm_extract_epi16(rsp->xv[13], 4), (UINT16)_mm_extract_epi16(rsp->xv[13], 3), (UINT16)_mm_extract_epi16(rsp->xv[13], 2), (UINT16)_mm_extract_epi16(rsp->xv[13], 1), (UINT16)_mm_extract_epi16(rsp->xv[13], 0)); break;
9017		case CPUINFO_STR_REGISTER + RSP_V14:            sprintf(info->s, "V14: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(rsp->xv[14], 7), (UINT16)_mm_extract_epi16(rsp->xv[14], 6), (UINT16)_mm_extract_epi16(rsp->xv[14], 5), (UINT16)_mm_extract_epi16(rsp->xv[14], 4), (UINT16)_mm_extract_epi16(rsp->xv[14], 3), (UINT16)_mm_extract_epi16(rsp->xv[14], 2), (UINT16)_mm_extract_epi16(rsp->xv[14], 1), (UINT16)_mm_extract_epi16(rsp->xv[14], 0)); break;
9018		case CPUINFO_STR_REGISTER + RSP_V15:            sprintf(info->s, "V15: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(rsp->xv[15], 7), (UINT16)_mm_extract_epi16(rsp->xv[15], 6), (UINT16)_mm_extract_epi16(rsp->xv[15], 5), (UINT16)_mm_extract_epi16(rsp->xv[15], 4), (UINT16)_mm_extract_epi16(rsp->xv[15], 3), (UINT16)_mm_extract_epi16(rsp->xv[15], 2), (UINT16)_mm_extract_epi16(rsp->xv[15], 1), (UINT16)_mm_extract_epi16(rsp->xv[15], 0)); break;
9019		case CPUINFO_STR_REGISTER + RSP_V16:            sprintf(info->s, "V16: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(rsp->xv[16], 7), (UINT16)_mm_extract_epi16(rsp->xv[16], 6), (UINT16)_mm_extract_epi16(rsp->xv[16], 5), (UINT16)_mm_extract_epi16(rsp->xv[16], 4), (UINT16)_mm_extract_epi16(rsp->xv[16], 3), (UINT16)_mm_extract_epi16(rsp->xv[16], 2), (UINT16)_mm_extract_epi16(rsp->xv[16], 1), (UINT16)_mm_extract_epi16(rsp->xv[16], 0)); break;
9020		case CPUINFO_STR_REGISTER + RSP_V17:            sprintf(info->s, "V17: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(rsp->xv[17], 7), (UINT16)_mm_extract_epi16(rsp->xv[17], 6), (UINT16)_mm_extract_epi16(rsp->xv[17], 5), (UINT16)_mm_extract_epi16(rsp->xv[17], 4), (UINT16)_mm_extract_epi16(rsp->xv[17], 3), (UINT16)_mm_extract_epi16(rsp->xv[17], 2), (UINT16)_mm_extract_epi16(rsp->xv[17], 1), (UINT16)_mm_extract_epi16(rsp->xv[17], 0)); break;
9021		case CPUINFO_STR_REGISTER + RSP_V18:            sprintf(info->s, "V18: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(rsp->xv[18], 7), (UINT16)_mm_extract_epi16(rsp->xv[18], 6), (UINT16)_mm_extract_epi16(rsp->xv[18], 5), (UINT16)_mm_extract_epi16(rsp->xv[18], 4), (UINT16)_mm_extract_epi16(rsp->xv[18], 3), (UINT16)_mm_extract_epi16(rsp->xv[18], 2), (UINT16)_mm_extract_epi16(rsp->xv[18], 1), (UINT16)_mm_extract_epi16(rsp->xv[18], 0)); break;
9022		case CPUINFO_STR_REGISTER + RSP_V19:            sprintf(info->s, "V19: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(rsp->xv[19], 7), (UINT16)_mm_extract_epi16(rsp->xv[19], 6), (UINT16)_mm_extract_epi16(rsp->xv[19], 5), (UINT16)_mm_extract_epi16(rsp->xv[19], 4), (UINT16)_mm_extract_epi16(rsp->xv[19], 3), (UINT16)_mm_extract_epi16(rsp->xv[19], 2), (UINT16)_mm_extract_epi16(rsp->xv[19], 1), (UINT16)_mm_extract_epi16(rsp->xv[19], 0)); break;
9023		case CPUINFO_STR_REGISTER + RSP_V20:            sprintf(info->s, "V20: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(rsp->xv[20], 7), (UINT16)_mm_extract_epi16(rsp->xv[20], 6), (UINT16)_mm_extract_epi16(rsp->xv[20], 5), (UINT16)_mm_extract_epi16(rsp->xv[20], 4), (UINT16)_mm_extract_epi16(rsp->xv[20], 3), (UINT16)_mm_extract_epi16(rsp->xv[20], 2), (UINT16)_mm_extract_epi16(rsp->xv[20], 1), (UINT16)_mm_extract_epi16(rsp->xv[20], 0)); break;
9024		case CPUINFO_STR_REGISTER + RSP_V21:            sprintf(info->s, "V21: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(rsp->xv[21], 7), (UINT16)_mm_extract_epi16(rsp->xv[21], 6), (UINT16)_mm_extract_epi16(rsp->xv[21], 5), (UINT16)_mm_extract_epi16(rsp->xv[21], 4), (UINT16)_mm_extract_epi16(rsp->xv[21], 3), (UINT16)_mm_extract_epi16(rsp->xv[21], 2), (UINT16)_mm_extract_epi16(rsp->xv[21], 1), (UINT16)_mm_extract_epi16(rsp->xv[21], 0)); break;
9025		case CPUINFO_STR_REGISTER + RSP_V22:            sprintf(info->s, "V22: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(rsp->xv[22], 7), (UINT16)_mm_extract_epi16(rsp->xv[22], 6), (UINT16)_mm_extract_epi16(rsp->xv[22], 5), (UINT16)_mm_extract_epi16(rsp->xv[22], 4), (UINT16)_mm_extract_epi16(rsp->xv[22], 3), (UINT16)_mm_extract_epi16(rsp->xv[22], 2), (UINT16)_mm_extract_epi16(rsp->xv[22], 1), (UINT16)_mm_extract_epi16(rsp->xv[22], 0)); break;
9026		case CPUINFO_STR_REGISTER + RSP_V23:            sprintf(info->s, "V23: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(rsp->xv[23], 7), (UINT16)_mm_extract_epi16(rsp->xv[23], 6), (UINT16)_mm_extract_epi16(rsp->xv[23], 5), (UINT16)_mm_extract_epi16(rsp->xv[23], 4), (UINT16)_mm_extract_epi16(rsp->xv[23], 3), (UINT16)_mm_extract_epi16(rsp->xv[23], 2), (UINT16)_mm_extract_epi16(rsp->xv[23], 1), (UINT16)_mm_extract_epi16(rsp->xv[23], 0)); break;
9027		case CPUINFO_STR_REGISTER + RSP_V24:            sprintf(info->s, "V24: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(rsp->xv[24], 7), (UINT16)_mm_extract_epi16(rsp->xv[24], 6), (UINT16)_mm_extract_epi16(rsp->xv[24], 5), (UINT16)_mm_extract_epi16(rsp->xv[24], 4), (UINT16)_mm_extract_epi16(rsp->xv[24], 3), (UINT16)_mm_extract_epi16(rsp->xv[24], 2), (UINT16)_mm_extract_epi16(rsp->xv[24], 1), (UINT16)_mm_extract_epi16(rsp->xv[24], 0)); break;
9028		case CPUINFO_STR_REGISTER + RSP_V25:            sprintf(info->s, "V25: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(rsp->xv[25], 7), (UINT16)_mm_extract_epi16(rsp->xv[25], 6), (UINT16)_mm_extract_epi16(rsp->xv[25], 5), (UINT16)_mm_extract_epi16(rsp->xv[25], 4), (UINT16)_mm_extract_epi16(rsp->xv[25], 3), (UINT16)_mm_extract_epi16(rsp->xv[25], 2), (UINT16)_mm_extract_epi16(rsp->xv[25], 1), (UINT16)_mm_extract_epi16(rsp->xv[25], 0)); break;
9029		case CPUINFO_STR_REGISTER + RSP_V26:            sprintf(info->s, "V26: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(rsp->xv[26], 7), (UINT16)_mm_extract_epi16(rsp->xv[26], 6), (UINT16)_mm_extract_epi16(rsp->xv[26], 5), (UINT16)_mm_extract_epi16(rsp->xv[26], 4), (UINT16)_mm_extract_epi16(rsp->xv[26], 3), (UINT16)_mm_extract_epi16(rsp->xv[26], 2), (UINT16)_mm_extract_epi16(rsp->xv[26], 1), (UINT16)_mm_extract_epi16(rsp->xv[26], 0)); break;
9030		case CPUINFO_STR_REGISTER + RSP_V27:            sprintf(info->s, "V27: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(rsp->xv[27], 7), (UINT16)_mm_extract_epi16(rsp->xv[27], 6), (UINT16)_mm_extract_epi16(rsp->xv[27], 5), (UINT16)_mm_extract_epi16(rsp->xv[27], 4), (UINT16)_mm_extract_epi16(rsp->xv[27], 3), (UINT16)_mm_extract_epi16(rsp->xv[27], 2), (UINT16)_mm_extract_epi16(rsp->xv[27], 1), (UINT16)_mm_extract_epi16(rsp->xv[27], 0)); break;
9031		case CPUINFO_STR_REGISTER + RSP_V28:            sprintf(info->s, "V28: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(rsp->xv[28], 7), (UINT16)_mm_extract_epi16(rsp->xv[28], 6), (UINT16)_mm_extract_epi16(rsp->xv[28], 5), (UINT16)_mm_extract_epi16(rsp->xv[28], 4), (UINT16)_mm_extract_epi16(rsp->xv[28], 3), (UINT16)_mm_extract_epi16(rsp->xv[28], 2), (UINT16)_mm_extract_epi16(rsp->xv[28], 1), (UINT16)_mm_extract_epi16(rsp->xv[28], 0)); break;
9032		case CPUINFO_STR_REGISTER + RSP_V29:            sprintf(info->s, "V29: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(rsp->xv[29], 7), (UINT16)_mm_extract_epi16(rsp->xv[29], 6), (UINT16)_mm_extract_epi16(rsp->xv[29], 5), (UINT16)_mm_extract_epi16(rsp->xv[29], 4), (UINT16)_mm_extract_epi16(rsp->xv[29], 3), (UINT16)_mm_extract_epi16(rsp->xv[29], 2), (UINT16)_mm_extract_epi16(rsp->xv[29], 1), (UINT16)_mm_extract_epi16(rsp->xv[29], 0)); break;
9033		case CPUINFO_STR_REGISTER + RSP_V30:            sprintf(info->s, "V30: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(rsp->xv[30], 7), (UINT16)_mm_extract_epi16(rsp->xv[30], 6), (UINT16)_mm_extract_epi16(rsp->xv[30], 5), (UINT16)_mm_extract_epi16(rsp->xv[30], 4), (UINT16)_mm_extract_epi16(rsp->xv[30], 3), (UINT16)_mm_extract_epi16(rsp->xv[30], 2), (UINT16)_mm_extract_epi16(rsp->xv[30], 1), (UINT16)_mm_extract_epi16(rsp->xv[30], 0)); break;
9034		case CPUINFO_STR_REGISTER + RSP_V31:            sprintf(info->s, "V31: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(rsp->xv[31], 7), (UINT16)_mm_extract_epi16(rsp->xv[31], 6), (UINT16)_mm_extract_epi16(rsp->xv[31], 5), (UINT16)_mm_extract_epi16(rsp->xv[31], 4), (UINT16)_mm_extract_epi16(rsp->xv[31], 3), (UINT16)_mm_extract_epi16(rsp->xv[31], 2), (UINT16)_mm_extract_epi16(rsp->xv[31], 1), (UINT16)_mm_extract_epi16(rsp->xv[31], 0)); break;
9035		#else
9036		case CPUINFO_STR_REGISTER + RSP_V0:             sprintf(info->s, "V0: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X",  (UINT16)VREG_S( 0, 0), (UINT16)VREG_S( 0, 1), (UINT16)VREG_S( 0, 2), (UINT16)VREG_S( 0, 3), (UINT16)VREG_S( 0, 4), (UINT16)VREG_S( 0, 5), (UINT16)VREG_S( 0, 6), (UINT16)VREG_S( 0, 7)); break;
9037		case CPUINFO_STR_REGISTER + RSP_V1:             sprintf(info->s, "V1: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X",  (UINT16)VREG_S( 1, 0), (UINT16)VREG_S( 1, 1), (UINT16)VREG_S( 1, 2), (UINT16)VREG_S( 1, 3), (UINT16)VREG_S( 1, 4), (UINT16)VREG_S( 1, 5), (UINT16)VREG_S( 1, 6), (UINT16)VREG_S( 1, 7)); break;
9038		case CPUINFO_STR_REGISTER + RSP_V2:             sprintf(info->s, "V2: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X",  (UINT16)VREG_S( 2, 0), (UINT16)VREG_S( 2, 1), (UINT16)VREG_S( 2, 2), (UINT16)VREG_S( 2, 3), (UINT16)VREG_S( 2, 4), (UINT16)VREG_S( 2, 5), (UINT16)VREG_S( 2, 6), (UINT16)VREG_S( 2, 7)); break;
9039		case CPUINFO_STR_REGISTER + RSP_V3:             sprintf(info->s, "V3: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X",  (UINT16)VREG_S( 3, 0), (UINT16)VREG_S( 3, 1), (UINT16)VREG_S( 3, 2), (UINT16)VREG_S( 3, 3), (UINT16)VREG_S( 3, 4), (UINT16)VREG_S( 3, 5), (UINT16)VREG_S( 3, 6), (UINT16)VREG_S( 3, 7)); break;
9040		case CPUINFO_STR_REGISTER + RSP_V4:             sprintf(info->s, "V4: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X",  (UINT16)VREG_S( 4, 0), (UINT16)VREG_S( 4, 1), (UINT16)VREG_S( 4, 2), (UINT16)VREG_S( 4, 3), (UINT16)VREG_S( 4, 4), (UINT16)VREG_S( 4, 5), (UINT16)VREG_S( 4, 6), (UINT16)VREG_S( 4, 7)); break;
9041		case CPUINFO_STR_REGISTER + RSP_V5:             sprintf(info->s, "V5: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X",  (UINT16)VREG_S( 5, 0), (UINT16)VREG_S( 5, 1), (UINT16)VREG_S( 5, 2), (UINT16)VREG_S( 5, 3), (UINT16)VREG_S( 5, 4), (UINT16)VREG_S( 5, 5), (UINT16)VREG_S( 5, 6), (UINT16)VREG_S( 5, 7)); break;
9042		case CPUINFO_STR_REGISTER + RSP_V6:             sprintf(info->s, "V6: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X",  (UINT16)VREG_S( 6, 0), (UINT16)VREG_S( 6, 1), (UINT16)VREG_S( 6, 2), (UINT16)VREG_S( 6, 3), (UINT16)VREG_S( 6, 4), (UINT16)VREG_S( 6, 5), (UINT16)VREG_S( 6, 6), (UINT16)VREG_S( 6, 7)); break;
9043		case CPUINFO_STR_REGISTER + RSP_V7:             sprintf(info->s, "V7: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X",  (UINT16)VREG_S( 7, 0), (UINT16)VREG_S( 7, 1), (UINT16)VREG_S( 7, 2), (UINT16)VREG_S( 7, 3), (UINT16)VREG_S( 7, 4), (UINT16)VREG_S( 7, 5), (UINT16)VREG_S( 7, 6), (UINT16)VREG_S( 7, 7)); break;
9044		case CPUINFO_STR_REGISTER + RSP_V8:             sprintf(info->s, "V8: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X",  (UINT16)VREG_S( 8, 0), (UINT16)VREG_S( 8, 1), (UINT16)VREG_S( 8, 2), (UINT16)VREG_S( 8, 3), (UINT16)VREG_S( 8, 4), (UINT16)VREG_S( 8, 5), (UINT16)VREG_S( 8, 6), (UINT16)VREG_S( 8, 7)); break;
9045		case CPUINFO_STR_REGISTER + RSP_V9:             sprintf(info->s, "V9: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X",  (UINT16)VREG_S( 9, 0), (UINT16)VREG_S( 9, 1), (UINT16)VREG_S( 9, 2), (UINT16)VREG_S( 9, 3), (UINT16)VREG_S( 9, 4), (UINT16)VREG_S( 9, 5), (UINT16)VREG_S( 9, 6), (UINT16)VREG_S( 9, 7)); break;
9046		case CPUINFO_STR_REGISTER + RSP_V10:            sprintf(info->s, "V10: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(10, 0), (UINT16)VREG_S(10, 1), (UINT16)VREG_S(10, 2), (UINT16)VREG_S(10, 3), (UINT16)VREG_S(10, 4), (UINT16)VREG_S(10, 5), (UINT16)VREG_S(10, 6), (UINT16)VREG_S(10, 7)); break;
9047		case CPUINFO_STR_REGISTER + RSP_V11:            sprintf(info->s, "V11: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(11, 0), (UINT16)VREG_S(11, 1), (UINT16)VREG_S(11, 2), (UINT16)VREG_S(11, 3), (UINT16)VREG_S(11, 4), (UINT16)VREG_S(11, 5), (UINT16)VREG_S(11, 6), (UINT16)VREG_S(11, 7)); break;
9048		case CPUINFO_STR_REGISTER + RSP_V12:            sprintf(info->s, "V12: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(12, 0), (UINT16)VREG_S(12, 1), (UINT16)VREG_S(12, 2), (UINT16)VREG_S(12, 3), (UINT16)VREG_S(12, 4), (UINT16)VREG_S(12, 5), (UINT16)VREG_S(12, 6), (UINT16)VREG_S(12, 7)); break;
9049		case CPUINFO_STR_REGISTER + RSP_V13:            sprintf(info->s, "V13: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(13, 0), (UINT16)VREG_S(13, 1), (UINT16)VREG_S(13, 2), (UINT16)VREG_S(13, 3), (UINT16)VREG_S(13, 4), (UINT16)VREG_S(13, 5), (UINT16)VREG_S(13, 6), (UINT16)VREG_S(13, 7)); break;
9050		case CPUINFO_STR_REGISTER + RSP_V14:            sprintf(info->s, "V14: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(14, 0), (UINT16)VREG_S(14, 1), (UINT16)VREG_S(14, 2), (UINT16)VREG_S(14, 3), (UINT16)VREG_S(14, 4), (UINT16)VREG_S(14, 5), (UINT16)VREG_S(14, 6), (UINT16)VREG_S(14, 7)); break;
9051		case CPUINFO_STR_REGISTER + RSP_V15:            sprintf(info->s, "V15: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(15, 0), (UINT16)VREG_S(15, 1), (UINT16)VREG_S(15, 2), (UINT16)VREG_S(15, 3), (UINT16)VREG_S(15, 4), (UINT16)VREG_S(15, 5), (UINT16)VREG_S(15, 6), (UINT16)VREG_S(15, 7)); break;
9052		case CPUINFO_STR_REGISTER + RSP_V16:            sprintf(info->s, "V16: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(16, 0), (UINT16)VREG_S(16, 1), (UINT16)VREG_S(16, 2), (UINT16)VREG_S(16, 3), (UINT16)VREG_S(16, 4), (UINT16)VREG_S(16, 5), (UINT16)VREG_S(16, 6), (UINT16)VREG_S(16, 7)); break;
9053		case CPUINFO_STR_REGISTER + RSP_V17:            sprintf(info->s, "V17: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(17, 0), (UINT16)VREG_S(17, 1), (UINT16)VREG_S(17, 2), (UINT16)VREG_S(17, 3), (UINT16)VREG_S(17, 4), (UINT16)VREG_S(17, 5), (UINT16)VREG_S(17, 6), (UINT16)VREG_S(17, 7)); break;
9054		case CPUINFO_STR_REGISTER + RSP_V18:            sprintf(info->s, "V18: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(18, 0), (UINT16)VREG_S(18, 1), (UINT16)VREG_S(18, 2), (UINT16)VREG_S(18, 3), (UINT16)VREG_S(18, 4), (UINT16)VREG_S(18, 5), (UINT16)VREG_S(18, 6), (UINT16)VREG_S(18, 7)); break;
9055		case CPUINFO_STR_REGISTER + RSP_V19:            sprintf(info->s, "V19: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(19, 0), (UINT16)VREG_S(19, 1), (UINT16)VREG_S(19, 2), (UINT16)VREG_S(19, 3), (UINT16)VREG_S(19, 4), (UINT16)VREG_S(19, 5), (UINT16)VREG_S(19, 6), (UINT16)VREG_S(19, 7)); break;
9056		case CPUINFO_STR_REGISTER + RSP_V20:            sprintf(info->s, "V20: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(20, 0), (UINT16)VREG_S(20, 1), (UINT16)VREG_S(20, 2), (UINT16)VREG_S(20, 3), (UINT16)VREG_S(20, 4), (UINT16)VREG_S(20, 5), (UINT16)VREG_S(20, 6), (UINT16)VREG_S(20, 7)); break;
9057		case CPUINFO_STR_REGISTER + RSP_V21:            sprintf(info->s, "V21: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(21, 0), (UINT16)VREG_S(21, 1), (UINT16)VREG_S(21, 2), (UINT16)VREG_S(21, 3), (UINT16)VREG_S(21, 4), (UINT16)VREG_S(21, 5), (UINT16)VREG_S(21, 6), (UINT16)VREG_S(21, 7)); break;
9058		case CPUINFO_STR_REGISTER + RSP_V22:            sprintf(info->s, "V22: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(22, 0), (UINT16)VREG_S(22, 1), (UINT16)VREG_S(22, 2), (UINT16)VREG_S(22, 3), (UINT16)VREG_S(22, 4), (UINT16)VREG_S(22, 5), (UINT16)VREG_S(22, 6), (UINT16)VREG_S(22, 7)); break;
9059		case CPUINFO_STR_REGISTER + RSP_V23:            sprintf(info->s, "V23: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(23, 0), (UINT16)VREG_S(23, 1), (UINT16)VREG_S(23, 2), (UINT16)VREG_S(23, 3), (UINT16)VREG_S(23, 4), (UINT16)VREG_S(23, 5), (UINT16)VREG_S(23, 6), (UINT16)VREG_S(23, 7)); break;
9060		case CPUINFO_STR_REGISTER + RSP_V24:            sprintf(info->s, "V24: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(24, 0), (UINT16)VREG_S(24, 1), (UINT16)VREG_S(24, 2), (UINT16)VREG_S(24, 3), (UINT16)VREG_S(24, 4), (UINT16)VREG_S(24, 5), (UINT16)VREG_S(24, 6), (UINT16)VREG_S(24, 7)); break;
9061		case CPUINFO_STR_REGISTER + RSP_V25:            sprintf(info->s, "V25: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(25, 0), (UINT16)VREG_S(25, 1), (UINT16)VREG_S(25, 2), (UINT16)VREG_S(25, 3), (UINT16)VREG_S(25, 4), (UINT16)VREG_S(25, 5), (UINT16)VREG_S(25, 6), (UINT16)VREG_S(25, 7)); break;
9062		case CPUINFO_STR_REGISTER + RSP_V26:            sprintf(info->s, "V26: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(26, 0), (UINT16)VREG_S(26, 1), (UINT16)VREG_S(26, 2), (UINT16)VREG_S(26, 3), (UINT16)VREG_S(26, 4), (UINT16)VREG_S(26, 5), (UINT16)VREG_S(26, 6), (UINT16)VREG_S(26, 7)); break;
9063		case CPUINFO_STR_REGISTER + RSP_V27:            sprintf(info->s, "V27: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(27, 0), (UINT16)VREG_S(27, 1), (UINT16)VREG_S(27, 2), (UINT16)VREG_S(27, 3), (UINT16)VREG_S(27, 4), (UINT16)VREG_S(27, 5), (UINT16)VREG_S(27, 6), (UINT16)VREG_S(27, 7)); break;
9064		case CPUINFO_STR_REGISTER + RSP_V28:            sprintf(info->s, "V28: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(28, 0), (UINT16)VREG_S(28, 1), (UINT16)VREG_S(28, 2), (UINT16)VREG_S(28, 3), (UINT16)VREG_S(28, 4), (UINT16)VREG_S(28, 5), (UINT16)VREG_S(28, 6), (UINT16)VREG_S(28, 7)); break;
9065		case CPUINFO_STR_REGISTER + RSP_V29:            sprintf(info->s, "V29: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(29, 0), (UINT16)VREG_S(29, 1), (UINT16)VREG_S(29, 2), (UINT16)VREG_S(29, 3), (UINT16)VREG_S(29, 4), (UINT16)VREG_S(29, 5), (UINT16)VREG_S(29, 6), (UINT16)VREG_S(29, 7)); break;
9066		case CPUINFO_STR_REGISTER + RSP_V30:            sprintf(info->s, "V30: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(30, 0), (UINT16)VREG_S(30, 1), (UINT16)VREG_S(30, 2), (UINT16)VREG_S(30, 3), (UINT16)VREG_S(30, 4), (UINT16)VREG_S(30, 5), (UINT16)VREG_S(30, 6), (UINT16)VREG_S(30, 7)); break;
9067		case CPUINFO_STR_REGISTER + RSP_V31:            sprintf(info->s, "V31: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(31, 0), (UINT16)VREG_S(31, 1), (UINT16)VREG_S(31, 2), (UINT16)VREG_S(31, 3), (UINT16)VREG_S(31, 4), (UINT16)VREG_S(31, 5), (UINT16)VREG_S(31, 6), (UINT16)VREG_S(31, 7)); break;
9068		#endif
9069		case CPUINFO_STR_REGISTER + RSP_SR:             sprintf(info->s, "SR: %08X",  rsp->sr);    break;
9070		case CPUINFO_STR_REGISTER + RSP_NEXTPC:         sprintf(info->s, "NPC: %08X", rsp->nextpc);break;
9071		case CPUINFO_STR_REGISTER + RSP_STEPCNT:        sprintf(info->s, "STEP: %d",  rsp->step_count);  break;
9072		}
9073		}
9074
9075		rsp_drc_device::rsp_drc_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock)
9076		: rsp_cpu_device(mconfig, type, tag, owner, clock, CPU_GET_INFO_NAME(rsp_drc))
9077		{
9078		}
9079
9080		const device_type RSP_DRC = &legacy_device_creator<rsp_drc_device>;

trunk/src/emu/cpu/rsp/rspfe.c

r31833	r31834
22	22	//  rsp_frontend - constructor
23	23	//-------------------------------------------------
24	24
25		rsp_frontend::rsp_frontend(rsp_state &state, UINT32 window_start, UINT32 window_end, UINT32 max_sequence)
26		: drc_frontend(*state.device, window_start, window_end, max_sequence),
27		m_context(state)
	25	rsp_frontend::rsp_frontend(rsp_device &rsp, UINT32 window_start, UINT32 window_end, UINT32 max_sequence)
	26	: drc_frontend(rsp, window_start, window_end, max_sequence),
	27	m_rsp(rsp)
28	28	{
29	29	}
30	30
r31833	r31834
39	39	UINT32 op, opswitch;
40	40
41	41	// fetch the opcode
42		op = desc.opptr.l[0] = m_context.direct->read_decrypted_dword(desc.physpc | 0x1000);
	42	op = desc.opptr.l[0] = m_rsp.m_direct->read_decrypted_dword(desc.physpc | 0x1000);
43	43
44	44	// all instructions are 4 bytes and default to a single cycle each
45	45	desc.length = 4;

trunk/src/emu/cpu/rsp/rsp.c

r31833	r31834
8	8	#include "debugger.h"
9	9	#include "rsp.h"
10	10	#include "rspdiv.h"
	11	#include "rspfe.h"
11	12
12		CPU_DISASSEMBLE( rsp );
13	13
	14	const device_type RSP = &device_creator<rsp_device>;
	15
	16
14	17	#define LOG_INSTRUCTION_EXECUTION       0
15	18	#define SAVE_DISASM                     0
16	19	#define SAVE_DMEM                       0
r31833	r31834
28	31
29	32	extern offs_t rsp_dasm_one(char *buffer, offs_t pc, UINT32 op);
30	33
31		INLINE rsp_state *get_safe_token(device_t *device)
32		{
33		assert(device != NULL);
34		assert(device->type() == RSP_INT);
35		return (rsp_state *)downcast<legacy_cpu_device *>(device)->token();
36		}
37	34
38	35	#define SIMM16      ((INT32)(INT16)(op))
39	36	#define UIMM16      ((UINT16)(op))
40	37	#define UIMM26      (op & 0x03ffffff)
41	38
42		#define JUMP_ABS(addr)          { rsp->nextpc = 0x04001000 | (((addr) << 2) & 0xfff); }
43		#define JUMP_ABS_L(addr,l)      { rsp->nextpc = 0x04001000 | (((addr) << 2) & 0xfff); rsp->r[l] = rsp->pc + 4; }
44		#define JUMP_REL(offset)        { rsp->nextpc = 0x04001000 | ((rsp->pc + ((offset) << 2)) & 0xfff); }
45		#define JUMP_REL_L(offset,l)    { rsp->nextpc = 0x04001000 | ((rsp->pc + ((offset) << 2)) & 0xfff); rsp->r[l] = rsp->pc + 4; }
46		#define JUMP_PC(addr)           { rsp->nextpc = 0x04001000 | ((addr) & 0xfff); }
47		#define JUMP_PC_L(addr,l)       { rsp->nextpc = 0x04001000 | ((addr) & 0xfff); rsp->r[l] = rsp->pc + 4; }
48		#define LINK(l)                 { rsp->r[l] = rsp->pc + 4; }
	39	#define JUMP_ABS(addr)          { m_nextpc = 0x04001000 | (((addr) << 2) & 0xfff); }
	40	#define JUMP_ABS_L(addr,l)      { m_nextpc = 0x04001000 | (((addr) << 2) & 0xfff); m_rsp_state->r[l] = m_rsp_state->pc + 4; }
	41	#define JUMP_REL(offset)        { m_nextpc = 0x04001000 | ((m_rsp_state->pc + ((offset) << 2)) & 0xfff); }
	42	#define JUMP_REL_L(offset,l)    { m_nextpc = 0x04001000 | ((m_rsp_state->pc + ((offset) << 2)) & 0xfff); m_rsp_state->r[l] = m_rsp_state->pc + 4; }
	43	#define JUMP_PC(addr)           { m_nextpc = 0x04001000 | ((addr) & 0xfff); }
	44	#define JUMP_PC_L(addr,l)       { m_nextpc = 0x04001000 | ((addr) & 0xfff); m_rsp_state->r[l] = m_rsp_state->pc + 4; }
	45	#define LINK(l)                 { m_rsp_state->r[l] = m_rsp_state->pc + 4; }
49	46
50		#define VREG_B(reg, offset)     rsp->v[(reg)].b[(offset)^1]
51		#define VREG_S(reg, offset)     rsp->v[(reg)].s[(offset)]
52		#define VREG_L(reg, offset)     rsp->v[(reg)].l[(offset)]
	47	#define VREG_B(reg, offset)     m_v[(reg)].b[(offset)^1]
	48	#define VREG_S(reg, offset)     m_v[(reg)].s[(offset)]
	49	#define VREG_L(reg, offset)     m_v[(reg)].l[(offset)]
53	50
54		#define R_VREG_B(reg, offset)       rsp->v[(reg)].b[(offset)^1]
55		#define R_VREG_S(reg, offset)       (INT16)rsp->v[(reg)].s[(offset)]
56		#define R_VREG_L(reg, offset)       rsp->v[(reg)].l[(offset)]
	51	#define R_VREG_B(reg, offset)       m_v[(reg)].b[(offset)^1]
	52	#define R_VREG_S(reg, offset)       (INT16)m_v[(reg)].s[(offset)]
	53	#define R_VREG_L(reg, offset)       m_v[(reg)].l[(offset)]
57	54
58		#define W_VREG_B(reg, offset, val)  (rsp->v[(reg)].b[(offset)^1] = val)
59		#define W_VREG_S(reg, offset, val)  (rsp->v[(reg)].s[(offset)] = val)
60		#define W_VREG_L(reg, offset, val)  (rsp->v[(reg)].l[(offset)] = val)
	55	#define W_VREG_B(reg, offset, val)  (m_v[(reg)].b[(offset)^1] = val)
	56	#define W_VREG_S(reg, offset, val)  (m_v[(reg)].s[(offset)] = val)
	57	#define W_VREG_L(reg, offset, val)  (m_v[(reg)].l[(offset)] = val)
61	58
62	59	#define VEC_EL_2(x,z)           (vector_elements[(x)][(z)])
63	60
64		#define ACCUM(x)        rsp->accum[((x))].q
65		#define ACCUM_H(x)      rsp->accum[((x))].w[3]
66		#define ACCUM_M(x)      rsp->accum[((x))].w[2]
67		#define ACCUM_L(x)      rsp->accum[((x))].w[1]
	61	#define ACCUM(x)        m_accum[((x))].q
	62	#define ACCUM_H(x)      m_accum[((x))].w[3]
	63	#define ACCUM_M(x)      m_accum[((x))].w[2]
	64	#define ACCUM_L(x)      m_accum[((x))].w[1]
68	65
69	66	#define CARRY       0
70	67	#define COMPARE     1
r31833	r31834
72	69	#define ZERO        3
73	70	#define CLIP2       4
74	71
75		#define CARRY_FLAG(x)           (rsp->vflag[CARRY][x & 7] != 0 ? 0xffff : 0)
76		#define COMPARE_FLAG(x)         (rsp->vflag[COMPARE][x & 7] != 0 ? 0xffff : 0)
77		#define CLIP1_FLAG(x)           (rsp->vflag[CLIP1][x & 7] != 0 ? 0xffff : 0)
78		#define ZERO_FLAG(x)            (rsp->vflag[ZERO][x & 7] != 0 ? 0xffff : 0)
79		#define CLIP2_FLAG(x)           (rsp->vflag[CLIP2][x & 7] != 0 ? 0xffff : 0)
	72	#define CARRY_FLAG(x)           (m_vflag[CARRY][x & 7] != 0 ? 0xffff : 0)
	73	#define COMPARE_FLAG(x)         (m_vflag[COMPARE][x & 7] != 0 ? 0xffff : 0)
	74	#define CLIP1_FLAG(x)           (m_vflag[CLIP1][x & 7] != 0 ? 0xffff : 0)
	75	#define ZERO_FLAG(x)            (m_vflag[ZERO][x & 7] != 0 ? 0xffff : 0)
	76	#define CLIP2_FLAG(x)           (m_vflag[CLIP2][x & 7] != 0 ? 0xffff : 0)
80	77
81		#define CLEAR_CARRY_FLAGS()     { memset(rsp->vflag[0], 0, 16); }
82		#define CLEAR_COMPARE_FLAGS()   { memset(rsp->vflag[1], 0, 16); }
83		#define CLEAR_CLIP1_FLAGS()     { memset(rsp->vflag[2], 0, 16); }
84		#define CLEAR_ZERO_FLAGS()      { memset(rsp->vflag[3], 0, 16); }
85		#define CLEAR_CLIP2_FLAGS()     { memset(rsp->vflag[4], 0, 16); }
	78	#define CLEAR_CARRY_FLAGS()     { memset(m_vflag[0], 0, 16); }
	79	#define CLEAR_COMPARE_FLAGS()   { memset(m_vflag[1], 0, 16); }
	80	#define CLEAR_CLIP1_FLAGS()     { memset(m_vflag[2], 0, 16); }
	81	#define CLEAR_ZERO_FLAGS()      { memset(m_vflag[3], 0, 16); }
	82	#define CLEAR_CLIP2_FLAGS()     { memset(m_vflag[4], 0, 16); }
86	83
87		#define SET_CARRY_FLAG(x)       { rsp->vflag[0][x & 7] = 0xffff; }
88		#define SET_COMPARE_FLAG(x)     { rsp->vflag[1][x & 7] = 0xffff; }
89		#define SET_CLIP1_FLAG(x)       { rsp->vflag[2][x & 7] = 0xffff; }
90		#define SET_ZERO_FLAG(x)        { rsp->vflag[3][x & 7] = 0xffff; }
91		#define SET_CLIP2_FLAG(x)       { rsp->vflag[4][x & 7] = 0xffff; }
	84	#define SET_CARRY_FLAG(x)       { m_vflag[0][x & 7] = 0xffff; }
	85	#define SET_COMPARE_FLAG(x)     { m_vflag[1][x & 7] = 0xffff; }
	86	#define SET_CLIP1_FLAG(x)       { m_vflag[2][x & 7] = 0xffff; }
	87	#define SET_ZERO_FLAG(x)        { m_vflag[3][x & 7] = 0xffff; }
	88	#define SET_CLIP2_FLAG(x)       { m_vflag[4][x & 7] = 0xffff; }
92	89
93		#define CLEAR_CARRY_FLAG(x)     { rsp->vflag[0][x & 7] = 0; }
94		#define CLEAR_COMPARE_FLAG(x)   { rsp->vflag[1][x & 7] = 0; }
95		#define CLEAR_CLIP1_FLAG(x)     { rsp->vflag[2][x & 7] = 0; }
96		#define CLEAR_ZERO_FLAG(x)      { rsp->vflag[3][x & 7] = 0; }
97		#define CLEAR_CLIP2_FLAG(x)     { rsp->vflag[4][x & 7] = 0; }
	90	#define CLEAR_CARRY_FLAG(x)     { m_vflag[0][x & 7] = 0; }
	91	#define CLEAR_COMPARE_FLAG(x)   { m_vflag[1][x & 7] = 0; }
	92	#define CLEAR_CLIP1_FLAG(x)     { m_vflag[2][x & 7] = 0; }
	93	#define CLEAR_ZERO_FLAG(x)      { m_vflag[3][x & 7] = 0; }
	94	#define CLEAR_CLIP2_FLAG(x)     { m_vflag[4][x & 7] = 0; }
98	95
99		#define ROPCODE(pc)     rsp->program->read_dword(pc)
	96	#define ROPCODE(pc)     m_program->read_dword(pc)
100	97
101		INLINE UINT8 READ8(rsp_state *rsp, UINT32 address)
	98
	99	/***************************************************************************
	100	DEBUGGING
	101	***************************************************************************/
	102
	103	#define SINGLE_INSTRUCTION_MODE         (0)
	104
	105	/***************************************************************************
	106	CONSTANTS
	107	***************************************************************************/
	108
	109	/* compilation boundaries -- how far back/forward does the analysis extend? */
	110	#define COMPILE_BACKWARDS_BYTES         128
	111	#define COMPILE_FORWARDS_BYTES          512
	112	#define COMPILE_MAX_INSTRUCTIONS        ((COMPILE_BACKWARDS_BYTES/4) + (COMPILE_FORWARDS_BYTES/4))
	113	#define COMPILE_MAX_SEQUENCE            64
	114
	115	/* size of the execution code cache */
	116	#define CACHE_SIZE                      (32 * 1024 * 1024)
	117
	118
	119	rsp_device::rsp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	120	: cpu_device(mconfig, RSP, "RSP", tag, owner, clock, "rsp", __FILE__)
	121	, m_program_config("program", ENDIANNESS_BIG, 32, 32)
	122	, m_cache(CACHE_SIZE + sizeof(internal_rsp_state))
	123	, m_drcuml(NULL)
	124	//  , m_drcuml(*this, m_cache, ( RSP_LOG_UML ? DRCUML_OPTION_LOG_UML : 0 ) | ( RSP_LOG_NATIVE ? DRCUML_OPTION_LOG_NATIVE : 0 ), 8, 32, 2)
	125	, m_drcfe(NULL)
	126	, m_drcoptions(0)
	127	, m_cache_dirty(TRUE)
	128	, m_numcycles(0)
	129	, m_format(NULL)
	130	, m_arg2(0)
	131	, m_arg3(0)
	132	, m_entry(NULL)
	133	, m_nocode(NULL)
	134	, m_out_of_cycles(NULL)
	135	, m_read8(NULL)
	136	, m_write8(NULL)
	137	, m_read16(NULL)
	138	, m_write16(NULL)
	139	, m_read32(NULL)
	140	, m_write32(NULL)
	141	, m_rsp_state(NULL)
	142	, m_exec_output(NULL)
	143	#if SIMUL_SIMD
	144	, m_old_reciprocal_res(0)
	145	, m_old_reciprocal_high(0)
	146	, m_old_dp_allowed(0)
	147	, m_scalar_reciprocal_res(0)
	148	, m_scalar_reciprocal_high(0)
	149	, m_scalar_dp_allowed(0)
	150	, m_simd_reciprocal_res(0)
	151	, m_simd_reciprocal_high(0)
	152	, m_simd_dp_allowed(0)
	153	#endif
	154	, m_sr(0)
	155	, m_step_count(0)
	156	#if USE_SIMD
	157	, m_accum_h(0)
	158	, m_accum_m(0)
	159	, m_accum_l(0)
	160	, m_accum_ll(0)
	161	#endif
	162	, m_reciprocal_res(0)
	163	, m_reciprocal_high(0)
	164	, m_dp_allowed(0)
	165	, m_ppc(0)
	166	, m_nextpc(0)
	167	, m_dmem32(NULL)
	168	, m_dmem16(NULL)
	169	, m_dmem8(NULL)
	170	, m_imem32(NULL)
	171	, m_imem16(NULL)
	172	, m_imem8(NULL)
	173	, m_debugger_temp(0)
	174	, m_dp_reg_r_func(*this)
	175	, m_dp_reg_w_func(*this)
	176	, m_sp_reg_r_func(*this)
	177	, m_sp_reg_w_func(*this)
	178	, m_sp_set_status_func(*this)
102	179	{
	180	m_isdrc = mconfig.options().drc() ? true : false;
	181	memset(m_vres, 0, sizeof(m_vres));
	182	memset(m_v, 0, sizeof(m_v));
	183	memset(m_vflag, 0, sizeof(m_vflag));
	184	#if SIMUL_SIMD
	185	memset(m_old_r, 0, sizeof(m_old_r));
	186	memset(m_old_dmem, 0, sizeof(m_old_dmem));
	187	memset(m_scalar_r, 0, sizeof(m_scalar_r));
	188	memset(m_scalar_dmem, 0, sizeof(m_scalar_dmem));
	189	#endif
	190	#if USE_SIMD
	191	memset(m_xv, 0, sizeof(m_xv));
	192	memset(m_xvflag, 0, sizeof(m_xvflag));
	193	#endif
	194	memset(m_accum, 0, sizeof(m_accum));
	195	}
	196
	197	offs_t rsp_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
	198	{
	199	extern CPU_DISASSEMBLE( rsp );
	200	return CPU_DISASSEMBLE_NAME( rsp )(this, buffer, pc, oprom, opram, options);
	201	}
	202
	203	inline UINT8 rsp_device::READ8(UINT32 address)
	204	{
103	205	UINT8 ret;
104	206	address = 0x04000000 | (address & 0xfff);
105		ret = rsp->program->read_byte(address);
	207	ret = m_program->read_byte(address);
106	208	//printf("%04xr%02x\n", address & 0x0000ffff, ret);
107	209	return ret;
108	210	}
109	211
110		INLINE UINT16 READ16(rsp_state *rsp, UINT32 address)
	212	inline UINT16 rsp_device::READ16(UINT32 address)
111	213	{
112	214	UINT16 ret;
113	215	address = 0x04000000 | (address & 0xfff);
114	216
115	217	if(address & 1)
116	218	{
117		ret = ((rsp->program->read_byte(address + 0) & 0xff) << 8) | (rsp->program->read_byte(address + 1) & 0xff);
	219	ret = ((m_program->read_byte(address + 0) & 0xff) << 8) | (m_program->read_byte(address + 1) & 0xff);
118	220	}
119	221	else
120	222	{
121		ret = rsp->program->read_word(address);
	223	ret = m_program->read_word(address);
122	224	}
123	225
124	226	//printf("%04xr%04x\n", address & 0x0000ffff, ret);
r31833	r31834
126	228	return ret;
127	229	}
128	230
129		INLINE UINT32 READ32(rsp_state *rsp, UINT32 address)
	231	inline UINT32 rsp_device::READ32(UINT32 address)
130	232	{
131	233	UINT32 ret;
132	234	address = 0x04000000 | (address & 0xfff);
133	235
134	236	if(address & 3)
135	237	{
136		ret =  ((rsp->program->read_byte(address + 0) & 0xff) << 24) |
137		((rsp->program->read_byte(address + 1) & 0xff) << 16) |
138		((rsp->program->read_byte(address + 2) & 0xff) << 8) |
139		((rsp->program->read_byte(address + 3) & 0xff) << 0);
	238	ret =  ((m_program->read_byte(address + 0) & 0xff) << 24) |
	239	((m_program->read_byte(address + 1) & 0xff) << 16) |
	240	((m_program->read_byte(address + 2) & 0xff) << 8) |
	241	((m_program->read_byte(address + 3) & 0xff) << 0);
140	242	}
141	243	else
142	244	{
143		ret = rsp->program->read_dword(address);
	245	ret = m_program->read_dword(address);
144	246	}
145	247
146	248	//printf("%04xr%08x\n", address & 0x0000ffff, ret);
147	249	return ret;
148	250	}
149	251
150		INLINE void WRITE8(rsp_state *rsp, UINT32 address, UINT8 data)
	252	void rsp_device::WRITE8(UINT32 address, UINT8 data)
151	253	{
152	254	address = 0x04000000 | (address & 0xfff);
153	255	//printf("%04x:%02x\n", address & 0x0000ffff, data);
154		rsp->program->write_byte(address, data);
	256	m_program->write_byte(address, data);
155	257	}
156	258
157		INLINE void WRITE16(rsp_state *rsp, UINT32 address, UINT16 data)
	259	void rsp_device::WRITE16(UINT32 address, UINT16 data)
158	260	{
159	261	address = 0x04000000 | (address & 0xfff);
160	262	//printf("%04x:%04x\n", address & 0x0000ffff, data);
161	263
162	264	if(address & 1)
163	265	{
164		rsp->program->write_byte(address + 0, (data >> 8) & 0xff);
165		rsp->program->write_byte(address + 1, (data >> 0) & 0xff);
	266	m_program->write_byte(address + 0, (data >> 8) & 0xff);
	267	m_program->write_byte(address + 1, (data >> 0) & 0xff);
166	268	return;
167	269	}
168	270
169		rsp->program->write_word(address, data);
	271	m_program->write_word(address, data);
170	272	}
171	273
172		INLINE void WRITE32(rsp_state *rsp, UINT32 address, UINT32 data)
	274	void rsp_device::WRITE32(UINT32 address, UINT32 data)
173	275	{
174	276	address = 0x04000000 | (address & 0xfff);
175	277	//printf("%04x:%08x\n", address & 0x0000ffff, data);
176	278
177	279	if(address & 3)
178	280	{
179		rsp->program->write_byte(address + 0, (data >> 24) & 0xff);
180		rsp->program->write_byte(address + 1, (data >> 16) & 0xff);
181		rsp->program->write_byte(address + 2, (data >> 8) & 0xff);
182		rsp->program->write_byte(address + 3, (data >> 0) & 0xff);
	281	m_program->write_byte(address + 0, (data >> 24) & 0xff);
	282	m_program->write_byte(address + 1, (data >> 16) & 0xff);
	283	m_program->write_byte(address + 2, (data >> 8) & 0xff);
	284	m_program->write_byte(address + 3, (data >> 0) & 0xff);
183	285	return;
184	286	}
185	287
186		rsp->program->write_dword(address, data);
	288	m_program->write_dword(address, data);
187	289	}
188	290
189	291	/*****************************************************************************/
190	292
191		static UINT32 get_cop0_reg(rsp_state *rsp, int reg)
	293	UINT32 rsp_device::get_cop0_reg(int reg)
192	294	{
193	295	reg &= 0xf;
194	296	if (reg < 8)
195	297	{
196		return (rsp->device->sp_reg_r_func)(reg, 0xffffffff);
	298	return m_sp_reg_r_func(reg, 0xffffffff);
197	299	}
198	300	else if (reg >= 8 && reg < 16)
199	301	{
200		return (rsp->device->dp_reg_r_func)(reg - 8, 0xffffffff);
	302	return m_dp_reg_r_func(reg - 8, 0xffffffff);
201	303	}
202	304
203	305	return 0;
204	306	}
205	307
206		static void set_cop0_reg(rsp_state *rsp, int reg, UINT32 data)
	308	void rsp_device::set_cop0_reg(int reg, UINT32 data)
207	309	{
208	310	reg &= 0xf;
209	311	if (reg < 8)
210	312	{
211		(rsp->device->sp_reg_w_func)(reg, data, 0xffffffff);
	313	m_sp_reg_w_func(reg, data, 0xffffffff);
212	314	}
213	315	else if (reg >= 8 && reg < 16)
214	316	{
215		(rsp->device->dp_reg_w_func)(reg - 8, data, 0xffffffff);
	317	m_dp_reg_w_func(reg - 8, data, 0xffffffff);
216	318	}
217	319	}
218	320
219		static void unimplemented_opcode(rsp_state *rsp, UINT32 op)
	321	void rsp_device::unimplemented_opcode(UINT32 op)
220	322	{
221		if ((rsp->device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
	323	if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
222	324	{
223	325	char string[200];
224		rsp_dasm_one(string, rsp->ppc, op);
225		osd_printf_debug("%08X: %s\n", rsp->ppc, string);
	326	rsp_dasm_one(string, m_ppc, op);
	327	osd_printf_debug("%08X: %s\n", m_ppc, string);
226	328	}
227	329
228	330	#if SAVE_DISASM
r31833	r31834
255	357	}
256	358	#endif
257	359
258		fatalerror("RSP: unknown opcode %02X (%08X) at %08X\n", op >> 26, op, rsp->ppc);
	360	fatalerror("RSP: unknown opcode %02X (%08X) at %08X\n", op >> 26, op, m_ppc);
259	361	}
260	362
261	363	/*****************************************************************************/
r31833	r31834
280	382	{ 7, 7, 7, 7, 7, 7, 7, 7 },     // 7
281	383	};
282	384
283		void rsp_cpu_device::resolve_cb()
	385	void rsp_device::resolve_cb()
284	386	{
285		dp_reg_r_func.resolve();
286		dp_reg_w_func.resolve();
287		sp_reg_r_func.resolve();
288		sp_reg_w_func.resolve();
289		sp_set_status_func.resolve();
	387	m_dp_reg_r_func.resolve();
	388	m_dp_reg_w_func.resolve();
	389	m_sp_reg_r_func.resolve();
	390	m_sp_reg_w_func.resolve();
	391	m_sp_set_status_func.resolve();
290	392	}
291	393
292		static CPU_INIT( rsp )
	394	void rsp_device::device_start()
293	395	{
294		rsp_state *rsp = get_safe_token(device);
295		int regIdx;
296		int accumIdx;
	396	m_rsp_state = (internal_rsp_state *)m_cache.alloc_near(sizeof(internal_rsp_state));
297	397
298	398	if (LOG_INSTRUCTION_EXECUTION)
299		rsp->exec_output = fopen("rsp_execute.txt", "wt");
	399	m_exec_output = fopen("rsp_execute.txt", "wt");
300	400
301		rsp->irq_callback = irqcallback;
302		rsp->device = downcast<rsp_cpu_device *>(device);
303		rsp->program = &device->space(AS_PROGRAM);
304		rsp->direct = &rsp->program->direct();
305		rsp->device->resolve_cb();
	401	m_program = &space(AS_PROGRAM);
	402	m_direct = &m_program->direct();
	403	resolve_cb();
306	404
307		#if 1
308	405	// Inaccurate.  RSP registers power on to a random state...
309		for(regIdx = 0; regIdx < 32; regIdx++ )
	406	for(int regIdx = 0; regIdx < 32; regIdx++ )
310	407	{
311		rsp->r[regIdx] = 0;
312		rsp->v[regIdx].d[0] = 0;
313		rsp->v[regIdx].d[1] = 0;
	408	m_rsp_state->r[regIdx] = 0;
	409	m_v[regIdx].d[0] = 0;
	410	m_v[regIdx].d[1] = 0;
314	411	}
315	412	CLEAR_CARRY_FLAGS();
316	413	CLEAR_COMPARE_FLAGS();
317	414	CLEAR_CLIP1_FLAGS();
318	415	CLEAR_ZERO_FLAGS();
319	416	CLEAR_CLIP2_FLAGS();
320		//rsp->square_root_res = 0;
321		//rsp->square_root_high = 0;
322		rsp->reciprocal_res = 0;
323		rsp->reciprocal_high = 0;
324		#endif
	417	//m_square_root_res = 0;
	418	//m_square_root_high = 0;
	419	m_reciprocal_res = 0;
	420	m_reciprocal_high = 0;
325	421
326	422	// ...except for the accumulators.
327	423	// We're not calling machine.rand() because initializing something with machine.rand()
328	424	//   makes me retch uncontrollably.
329		for(accumIdx = 0; accumIdx < 8; accumIdx++ )
	425	for(int accumIdx = 0; accumIdx < 8; accumIdx++ )
330	426	{
331		rsp->accum[accumIdx].q = 0;
	427	m_accum[accumIdx].q = 0;
332	428	}
333	429
334		rsp->sr = RSP_STATUS_HALT;
335		rsp->step_count = 0;
	430	m_sr = RSP_STATUS_HALT;
	431	m_step_count = 0;
	432
	433	/* initialize the UML generator */
	434	UINT32 drc_flags = 0;
	435	if (RSP_LOG_UML)
	436	{
	437	drc_flags |= DRCUML_OPTION_LOG_UML;
	438	}
	439	if (RSP_LOG_NATIVE)
	440	{
	441	drc_flags |= DRCUML_OPTION_LOG_NATIVE;
	442	}
	443	m_drcuml = auto_alloc(machine(), drcuml_state(*this, m_cache, drc_flags, 8, 32, 2));
	444
	445	/* add symbols for our stuff */
	446	m_drcuml->symbol_add(&m_rsp_state->pc, sizeof(m_rsp_state->pc), "pc");
	447	m_drcuml->symbol_add(&m_rsp_state->icount, sizeof(m_rsp_state->icount), "icount");
	448	for (int regnum = 0; regnum < 32; regnum++)
	449	{
	450	char buf[10];
	451	sprintf(buf, "r%d", regnum);
	452	m_drcuml->symbol_add(&m_rsp_state->r[regnum], sizeof(m_rsp_state->r[regnum]), buf);
	453	}
	454	m_drcuml->symbol_add(&m_rsp_state->arg0, sizeof(m_rsp_state->arg0), "arg0");
	455	m_drcuml->symbol_add(&m_rsp_state->arg1, sizeof(m_rsp_state->arg1), "arg1");
	456	m_drcuml->symbol_add(&m_arg2, sizeof(m_arg2), "arg2");
	457	m_drcuml->symbol_add(&m_arg3, sizeof(m_arg3), "arg3");
	458	m_drcuml->symbol_add(&m_numcycles, sizeof(m_numcycles), "numcycles");
	459
	460	/* initialize the front-end helper */
	461	m_drcfe = auto_alloc(machine(), rsp_frontend(*this, COMPILE_BACKWARDS_BYTES, COMPILE_FORWARDS_BYTES, SINGLE_INSTRUCTION_MODE ? 1 : COMPILE_MAX_SEQUENCE));
	462
	463	/* compute the register parameters */
	464	for (int regnum = 0; regnum < 32; regnum++)
	465	{
	466	m_regmap[regnum] = (regnum == 0) ? uml::parameter(0) : uml::parameter::make_memory(&m_rsp_state->r[regnum]);
	467	}
	468
	469	/*
	470	drcbe_info beinfo;
	471	m_drcuml->get_backend_info(beinfo);
	472	if (beinfo.direct_iregs > 2)
	473	{
	474	m_regmap[30] = I2;
	475	}
	476	if (beinfo.direct_iregs > 3)
	477	{
	478	m_regmap[31] = I3;
	479	}
	480	if (beinfo.direct_iregs > 4)
	481	{
	482	m_regmap[2] = I4;
	483	}
	484	if (beinfo.direct_iregs > 5)
	485	{
	486	m_regmap[3] = I5;
	487	}
	488	if (beinfo.direct_iregs > 6)
	489	{
	490	m_regmap[4] = I6;
	491	}
	492	*/
	493
	494	/* mark the cache dirty so it is updated on next execute */
	495	m_cache_dirty = TRUE;
	496
	497	state_add( RSP_PC,      "PC", m_debugger_temp).callimport().callexport().formatstr("%08X");
	498	state_add( RSP_R0,      "R0", m_rsp_state->r[0]).formatstr("%08X");
	499	state_add( RSP_R1,      "R1", m_rsp_state->r[1]).formatstr("%08X");
	500	state_add( RSP_R2,      "R2", m_rsp_state->r[2]).formatstr("%08X");
	501	state_add( RSP_R3,      "R3", m_rsp_state->r[3]).formatstr("%08X");
	502	state_add( RSP_R4,      "R4", m_rsp_state->r[4]).formatstr("%08X");
	503	state_add( RSP_R5,      "R5", m_rsp_state->r[5]).formatstr("%08X");
	504	state_add( RSP_R6,      "R6", m_rsp_state->r[6]).formatstr("%08X");
	505	state_add( RSP_R7,      "R7", m_rsp_state->r[7]).formatstr("%08X");
	506	state_add( RSP_R8,      "R8", m_rsp_state->r[8]).formatstr("%08X");
	507	state_add( RSP_R9,      "R9", m_rsp_state->r[9]).formatstr("%08X");
	508	state_add( RSP_R10,     "R10", m_rsp_state->r[10]).formatstr("%08X");
	509	state_add( RSP_R11,     "R11", m_rsp_state->r[11]).formatstr("%08X");
	510	state_add( RSP_R12,     "R12", m_rsp_state->r[12]).formatstr("%08X");
	511	state_add( RSP_R13,     "R13", m_rsp_state->r[13]).formatstr("%08X");
	512	state_add( RSP_R14,     "R14", m_rsp_state->r[14]).formatstr("%08X");
	513	state_add( RSP_R15,     "R15", m_rsp_state->r[15]).formatstr("%08X");
	514	state_add( RSP_R16,     "R16", m_rsp_state->r[16]).formatstr("%08X");
	515	state_add( RSP_R17,     "R17", m_rsp_state->r[17]).formatstr("%08X");
	516	state_add( RSP_R18,     "R18", m_rsp_state->r[18]).formatstr("%08X");
	517	state_add( RSP_R19,     "R19", m_rsp_state->r[19]).formatstr("%08X");
	518	state_add( RSP_R20,     "R20", m_rsp_state->r[20]).formatstr("%08X");
	519	state_add( RSP_R21,     "R21", m_rsp_state->r[21]).formatstr("%08X");
	520	state_add( RSP_R22,     "R22", m_rsp_state->r[22]).formatstr("%08X");
	521	state_add( RSP_R23,     "R23", m_rsp_state->r[23]).formatstr("%08X");
	522	state_add( RSP_R24,     "R24", m_rsp_state->r[24]).formatstr("%08X");
	523	state_add( RSP_R25,     "R25", m_rsp_state->r[25]).formatstr("%08X");
	524	state_add( RSP_R26,     "R26", m_rsp_state->r[26]).formatstr("%08X");
	525	state_add( RSP_R27,     "R27", m_rsp_state->r[27]).formatstr("%08X");
	526	state_add( RSP_R28,     "R28", m_rsp_state->r[28]).formatstr("%08X");
	527	state_add( RSP_R29,     "R29", m_rsp_state->r[29]).formatstr("%08X");
	528	state_add( RSP_R30,     "R30", m_rsp_state->r[30]).formatstr("%08X");
	529	state_add( RSP_R31,     "R31", m_rsp_state->r[31]).formatstr("%08X");
	530	state_add( RSP_SR,      "SR",  m_sr).formatstr("%08X");
	531	state_add( RSP_NEXTPC,  "NPC", m_debugger_temp).callimport().callexport().formatstr("%08X");
	532	state_add( RSP_STEPCNT, "STEP",  m_step_count).formatstr("%08X");
	533
	534	state_add( RSP_V0,      "V0",  m_debugger_temp).formatstr("%39s");
	535	state_add( RSP_V1,      "V1",  m_debugger_temp).formatstr("%39s");
	536	state_add( RSP_V2,      "V2",  m_debugger_temp).formatstr("%39s");
	537	state_add( RSP_V3,      "V3",  m_debugger_temp).formatstr("%39s");
	538	state_add( RSP_V4,      "V4",  m_debugger_temp).formatstr("%39s");
	539	state_add( RSP_V5,      "V5",  m_debugger_temp).formatstr("%39s");
	540	state_add( RSP_V6,      "V6",  m_debugger_temp).formatstr("%39s");
	541	state_add( RSP_V7,      "V7",  m_debugger_temp).formatstr("%39s");
	542	state_add( RSP_V8,      "V8",  m_debugger_temp).formatstr("%39s");
	543	state_add( RSP_V9,      "V9",  m_debugger_temp).formatstr("%39s");
	544	state_add( RSP_V10,     "V10", m_debugger_temp).formatstr("%39s");
	545	state_add( RSP_V11,     "V11", m_debugger_temp).formatstr("%39s");
	546	state_add( RSP_V12,     "V12", m_debugger_temp).formatstr("%39s");
	547	state_add( RSP_V13,     "V13", m_debugger_temp).formatstr("%39s");
	548	state_add( RSP_V14,     "V14", m_debugger_temp).formatstr("%39s");
	549	state_add( RSP_V15,     "V15", m_debugger_temp).formatstr("%39s");
	550	state_add( RSP_V16,     "V16", m_debugger_temp).formatstr("%39s");
	551	state_add( RSP_V17,     "V17", m_debugger_temp).formatstr("%39s");
	552	state_add( RSP_V18,     "V18", m_debugger_temp).formatstr("%39s");
	553	state_add( RSP_V19,     "V19", m_debugger_temp).formatstr("%39s");
	554	state_add( RSP_V20,     "V20", m_debugger_temp).formatstr("%39s");
	555	state_add( RSP_V21,     "V21", m_debugger_temp).formatstr("%39s");
	556	state_add( RSP_V22,     "V22", m_debugger_temp).formatstr("%39s");
	557	state_add( RSP_V23,     "V23", m_debugger_temp).formatstr("%39s");
	558	state_add( RSP_V24,     "V24", m_debugger_temp).formatstr("%39s");
	559	state_add( RSP_V25,     "V25", m_debugger_temp).formatstr("%39s");
	560	state_add( RSP_V26,     "V26", m_debugger_temp).formatstr("%39s");
	561	state_add( RSP_V27,     "V27", m_debugger_temp).formatstr("%39s");
	562	state_add( RSP_V28,     "V28", m_debugger_temp).formatstr("%39s");
	563	state_add( RSP_V29,     "V29", m_debugger_temp).formatstr("%39s");
	564	state_add( RSP_V30,     "V30", m_debugger_temp).formatstr("%39s");
	565	state_add( RSP_V31,     "V31", m_debugger_temp).formatstr("%39s");
	566
	567	state_add( STATE_GENPC, "GENPC", m_debugger_temp).callimport().callexport().noshow();
	568	state_add( STATE_GENFLAGS, "GENFLAGS", m_debugger_temp).formatstr("%1s").noshow();
	569	state_add( STATE_GENSP, "GENSP", m_rsp_state->r[31]).noshow();
	570	state_add( STATE_GENPCBASE, "GENPCBASE", m_debugger_temp).callimport().callexport().noshow();
	571
	572	m_icountptr = &m_rsp_state->icount;
336	573	}
337	574
338		static CPU_EXIT( rsp )
	575	void rsp_device::state_import(const device_state_entry &entry)
339	576	{
340		rsp_state *rsp = get_safe_token(device);
	577	switch (entry.index())
	578	{
	579	case STATE_GENPC:
	580	case RSP_PC:
	581	m_rsp_state->pc = m_debugger_temp;
	582	break;
341	583
	584	case STATE_GENPCBASE:
	585	m_ppc = m_debugger_temp;
	586	break;
	587
	588	case RSP_NEXTPC:
	589	m_nextpc = m_debugger_temp;
	590	break;
	591	}
	592	}
	593
	594
	595	void rsp_device::state_export(const device_state_entry &entry)
	596	{
	597	switch (entry.index())
	598	{
	599	case STATE_GENPC:
	600	case RSP_PC:
	601	m_debugger_temp = m_rsp_state->pc | 0x04000000;
	602	break;
	603
	604	case STATE_GENPCBASE:
	605	m_debugger_temp = m_ppc | 0x04000000;
	606	break;
	607
	608	case RSP_NEXTPC:
	609	m_debugger_temp = m_nextpc | 0x04000000;
	610	break;
	611	}
	612	}
	613
	614	void rsp_device::state_string_export(const device_state_entry &entry, astring &string)
	615	{
	616	switch (entry.index())
	617	{
	618	case STATE_GENFLAGS:
	619	string.printf("");
	620	break;
	621
	622	#if USE_SIMD
	623	case RSP_V0:
	624	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[ 0], 7), (UINT16)_mm_extract_epi16(m_xv[ 0], 6), (UINT16)_mm_extract_epi16(m_xv[ 0], 5), (UINT16)_mm_extract_epi16(m_xv[ 0], 4), (UINT16)_mm_extract_epi16(m_xv[ 0], 3), (UINT16)_mm_extract_epi16(m_xv[ 0], 2), (UINT16)_mm_extract_epi16(m_xv[ 0], 1), (UINT16)_mm_extract_epi16(m_xv[ 0], 0));
	625	break;
	626	case RSP_V1:
	627	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[ 1], 7), (UINT16)_mm_extract_epi16(m_xv[ 1], 6), (UINT16)_mm_extract_epi16(m_xv[ 1], 5), (UINT16)_mm_extract_epi16(m_xv[ 1], 4), (UINT16)_mm_extract_epi16(m_xv[ 1], 3), (UINT16)_mm_extract_epi16(m_xv[ 1], 2), (UINT16)_mm_extract_epi16(m_xv[ 1], 1), (UINT16)_mm_extract_epi16(m_xv[ 1], 0));
	628	break;
	629	case RSP_V2:
	630	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[ 2], 7), (UINT16)_mm_extract_epi16(m_xv[ 2], 6), (UINT16)_mm_extract_epi16(m_xv[ 2], 5), (UINT16)_mm_extract_epi16(m_xv[ 2], 4), (UINT16)_mm_extract_epi16(m_xv[ 2], 3), (UINT16)_mm_extract_epi16(m_xv[ 2], 2), (UINT16)_mm_extract_epi16(m_xv[ 2], 1), (UINT16)_mm_extract_epi16(m_xv[ 2], 0));
	631	break;
	632	case RSP_V3:
	633	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[ 3], 7), (UINT16)_mm_extract_epi16(m_xv[ 3], 6), (UINT16)_mm_extract_epi16(m_xv[ 3], 5), (UINT16)_mm_extract_epi16(m_xv[ 3], 4), (UINT16)_mm_extract_epi16(m_xv[ 3], 3), (UINT16)_mm_extract_epi16(m_xv[ 3], 2), (UINT16)_mm_extract_epi16(m_xv[ 3], 1), (UINT16)_mm_extract_epi16(m_xv[ 3], 0));
	634	break;
	635	case RSP_V4:
	636	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[ 4], 7), (UINT16)_mm_extract_epi16(m_xv[ 4], 6), (UINT16)_mm_extract_epi16(m_xv[ 4], 5), (UINT16)_mm_extract_epi16(m_xv[ 4], 4), (UINT16)_mm_extract_epi16(m_xv[ 4], 3), (UINT16)_mm_extract_epi16(m_xv[ 4], 2), (UINT16)_mm_extract_epi16(m_xv[ 4], 1), (UINT16)_mm_extract_epi16(m_xv[ 4], 0));
	637	break;
	638	case RSP_V5:
	639	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[ 5], 7), (UINT16)_mm_extract_epi16(m_xv[ 5], 6), (UINT16)_mm_extract_epi16(m_xv[ 5], 5), (UINT16)_mm_extract_epi16(m_xv[ 5], 4), (UINT16)_mm_extract_epi16(m_xv[ 5], 3), (UINT16)_mm_extract_epi16(m_xv[ 5], 2), (UINT16)_mm_extract_epi16(m_xv[ 5], 1), (UINT16)_mm_extract_epi16(m_xv[ 5], 0));
	640	break;
	641	case RSP_V6:
	642	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[ 6], 7), (UINT16)_mm_extract_epi16(m_xv[ 6], 6), (UINT16)_mm_extract_epi16(m_xv[ 6], 5), (UINT16)_mm_extract_epi16(m_xv[ 6], 4), (UINT16)_mm_extract_epi16(m_xv[ 6], 3), (UINT16)_mm_extract_epi16(m_xv[ 6], 2), (UINT16)_mm_extract_epi16(m_xv[ 6], 1), (UINT16)_mm_extract_epi16(m_xv[ 6], 0));
	643	break;
	644	case RSP_V7:
	645	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[ 7], 7), (UINT16)_mm_extract_epi16(m_xv[ 7], 6), (UINT16)_mm_extract_epi16(m_xv[ 7], 5), (UINT16)_mm_extract_epi16(m_xv[ 7], 4), (UINT16)_mm_extract_epi16(m_xv[ 7], 3), (UINT16)_mm_extract_epi16(m_xv[ 7], 2), (UINT16)_mm_extract_epi16(m_xv[ 7], 1), (UINT16)_mm_extract_epi16(m_xv[ 7], 0));
	646	break;
	647	case RSP_V8:
	648	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[ 8], 7), (UINT16)_mm_extract_epi16(m_xv[ 8], 6), (UINT16)_mm_extract_epi16(m_xv[ 8], 5), (UINT16)_mm_extract_epi16(m_xv[ 8], 4), (UINT16)_mm_extract_epi16(m_xv[ 8], 3), (UINT16)_mm_extract_epi16(m_xv[ 8], 2), (UINT16)_mm_extract_epi16(m_xv[ 8], 1), (UINT16)_mm_extract_epi16(m_xv[ 8], 0));
	649	break;
	650	case RSP_V9:
	651	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[ 9], 7), (UINT16)_mm_extract_epi16(m_xv[ 9], 6), (UINT16)_mm_extract_epi16(m_xv[ 9], 5), (UINT16)_mm_extract_epi16(m_xv[ 9], 4), (UINT16)_mm_extract_epi16(m_xv[ 9], 3), (UINT16)_mm_extract_epi16(m_xv[ 9], 2), (UINT16)_mm_extract_epi16(m_xv[ 9], 1), (UINT16)_mm_extract_epi16(m_xv[ 9], 0));
	652	break;
	653	case RSP_V10:
	654	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[10], 7), (UINT16)_mm_extract_epi16(m_xv[10], 6), (UINT16)_mm_extract_epi16(m_xv[10], 5), (UINT16)_mm_extract_epi16(m_xv[10], 4), (UINT16)_mm_extract_epi16(m_xv[10], 3), (UINT16)_mm_extract_epi16(m_xv[10], 2), (UINT16)_mm_extract_epi16(m_xv[10], 1), (UINT16)_mm_extract_epi16(m_xv[10], 0));
	655	break;
	656	case RSP_V11:
	657	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[11], 7), (UINT16)_mm_extract_epi16(m_xv[11], 6), (UINT16)_mm_extract_epi16(m_xv[11], 5), (UINT16)_mm_extract_epi16(m_xv[11], 4), (UINT16)_mm_extract_epi16(m_xv[11], 3), (UINT16)_mm_extract_epi16(m_xv[11], 2), (UINT16)_mm_extract_epi16(m_xv[11], 1), (UINT16)_mm_extract_epi16(m_xv[11], 0));
	658	break;
	659	case RSP_V12:
	660	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[12], 7), (UINT16)_mm_extract_epi16(m_xv[12], 6), (UINT16)_mm_extract_epi16(m_xv[12], 5), (UINT16)_mm_extract_epi16(m_xv[12], 4), (UINT16)_mm_extract_epi16(m_xv[12], 3), (UINT16)_mm_extract_epi16(m_xv[12], 2), (UINT16)_mm_extract_epi16(m_xv[12], 1), (UINT16)_mm_extract_epi16(m_xv[12], 0));
	661	break;
	662	case RSP_V13:
	663	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[13], 7), (UINT16)_mm_extract_epi16(m_xv[13], 6), (UINT16)_mm_extract_epi16(m_xv[13], 5), (UINT16)_mm_extract_epi16(m_xv[13], 4), (UINT16)_mm_extract_epi16(m_xv[13], 3), (UINT16)_mm_extract_epi16(m_xv[13], 2), (UINT16)_mm_extract_epi16(m_xv[13], 1), (UINT16)_mm_extract_epi16(m_xv[13], 0));
	664	break;
	665	case RSP_V14:
	666	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[14], 7), (UINT16)_mm_extract_epi16(m_xv[14], 6), (UINT16)_mm_extract_epi16(m_xv[14], 5), (UINT16)_mm_extract_epi16(m_xv[14], 4), (UINT16)_mm_extract_epi16(m_xv[14], 3), (UINT16)_mm_extract_epi16(m_xv[14], 2), (UINT16)_mm_extract_epi16(m_xv[14], 1), (UINT16)_mm_extract_epi16(m_xv[14], 0));
	667	break;
	668	case RSP_V15:
	669	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[15], 7), (UINT16)_mm_extract_epi16(m_xv[15], 6), (UINT16)_mm_extract_epi16(m_xv[15], 5), (UINT16)_mm_extract_epi16(m_xv[15], 4), (UINT16)_mm_extract_epi16(m_xv[15], 3), (UINT16)_mm_extract_epi16(m_xv[15], 2), (UINT16)_mm_extract_epi16(m_xv[15], 1), (UINT16)_mm_extract_epi16(m_xv[15], 0));
	670	break;
	671	case RSP_V16:
	672	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[16], 7), (UINT16)_mm_extract_epi16(m_xv[16], 6), (UINT16)_mm_extract_epi16(m_xv[16], 5), (UINT16)_mm_extract_epi16(m_xv[16], 4), (UINT16)_mm_extract_epi16(m_xv[16], 3), (UINT16)_mm_extract_epi16(m_xv[16], 2), (UINT16)_mm_extract_epi16(m_xv[16], 1), (UINT16)_mm_extract_epi16(m_xv[16], 0));
	673	break;
	674	case RSP_V17:
	675	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[17], 7), (UINT16)_mm_extract_epi16(m_xv[17], 6), (UINT16)_mm_extract_epi16(m_xv[17], 5), (UINT16)_mm_extract_epi16(m_xv[17], 4), (UINT16)_mm_extract_epi16(m_xv[17], 3), (UINT16)_mm_extract_epi16(m_xv[17], 2), (UINT16)_mm_extract_epi16(m_xv[17], 1), (UINT16)_mm_extract_epi16(m_xv[17], 0));
	676	break;
	677	case RSP_V18:
	678	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[18], 7), (UINT16)_mm_extract_epi16(m_xv[18], 6), (UINT16)_mm_extract_epi16(m_xv[18], 5), (UINT16)_mm_extract_epi16(m_xv[18], 4), (UINT16)_mm_extract_epi16(m_xv[18], 3), (UINT16)_mm_extract_epi16(m_xv[18], 2), (UINT16)_mm_extract_epi16(m_xv[18], 1), (UINT16)_mm_extract_epi16(m_xv[18], 0));
	679	break;
	680	case RSP_V19:
	681	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[19], 7), (UINT16)_mm_extract_epi16(m_xv[19], 6), (UINT16)_mm_extract_epi16(m_xv[19], 5), (UINT16)_mm_extract_epi16(m_xv[19], 4), (UINT16)_mm_extract_epi16(m_xv[19], 3), (UINT16)_mm_extract_epi16(m_xv[19], 2), (UINT16)_mm_extract_epi16(m_xv[19], 1), (UINT16)_mm_extract_epi16(m_xv[19], 0));
	682	break;
	683	case RSP_V20:
	684	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[20], 7), (UINT16)_mm_extract_epi16(m_xv[20], 6), (UINT16)_mm_extract_epi16(m_xv[20], 5), (UINT16)_mm_extract_epi16(m_xv[20], 4), (UINT16)_mm_extract_epi16(m_xv[20], 3), (UINT16)_mm_extract_epi16(m_xv[20], 2), (UINT16)_mm_extract_epi16(m_xv[20], 1), (UINT16)_mm_extract_epi16(m_xv[20], 0));
	685	break;
	686	case RSP_V21:
	687	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[21], 7), (UINT16)_mm_extract_epi16(m_xv[21], 6), (UINT16)_mm_extract_epi16(m_xv[21], 5), (UINT16)_mm_extract_epi16(m_xv[21], 4), (UINT16)_mm_extract_epi16(m_xv[21], 3), (UINT16)_mm_extract_epi16(m_xv[21], 2), (UINT16)_mm_extract_epi16(m_xv[21], 1), (UINT16)_mm_extract_epi16(m_xv[21], 0));
	688	break;
	689	case RSP_V22:
	690	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[22], 7), (UINT16)_mm_extract_epi16(m_xv[22], 6), (UINT16)_mm_extract_epi16(m_xv[22], 5), (UINT16)_mm_extract_epi16(m_xv[22], 4), (UINT16)_mm_extract_epi16(m_xv[22], 3), (UINT16)_mm_extract_epi16(m_xv[22], 2), (UINT16)_mm_extract_epi16(m_xv[22], 1), (UINT16)_mm_extract_epi16(m_xv[22], 0));
	691	break;
	692	case RSP_V23:
	693	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[23], 7), (UINT16)_mm_extract_epi16(m_xv[23], 6), (UINT16)_mm_extract_epi16(m_xv[23], 5), (UINT16)_mm_extract_epi16(m_xv[23], 4), (UINT16)_mm_extract_epi16(m_xv[23], 3), (UINT16)_mm_extract_epi16(m_xv[23], 2), (UINT16)_mm_extract_epi16(m_xv[23], 1), (UINT16)_mm_extract_epi16(m_xv[23], 0));
	694	break;
	695	case RSP_V24:
	696	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[24], 7), (UINT16)_mm_extract_epi16(m_xv[24], 6), (UINT16)_mm_extract_epi16(m_xv[24], 5), (UINT16)_mm_extract_epi16(m_xv[24], 4), (UINT16)_mm_extract_epi16(m_xv[24], 3), (UINT16)_mm_extract_epi16(m_xv[24], 2), (UINT16)_mm_extract_epi16(m_xv[24], 1), (UINT16)_mm_extract_epi16(m_xv[24], 0));
	697	break;
	698	case RSP_V25:
	699	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[25], 7), (UINT16)_mm_extract_epi16(m_xv[25], 6), (UINT16)_mm_extract_epi16(m_xv[25], 5), (UINT16)_mm_extract_epi16(m_xv[25], 4), (UINT16)_mm_extract_epi16(m_xv[25], 3), (UINT16)_mm_extract_epi16(m_xv[25], 2), (UINT16)_mm_extract_epi16(m_xv[25], 1), (UINT16)_mm_extract_epi16(m_xv[25], 0));
	700	break;
	701	case RSP_V26:
	702	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[26], 7), (UINT16)_mm_extract_epi16(m_xv[26], 6), (UINT16)_mm_extract_epi16(m_xv[26], 5), (UINT16)_mm_extract_epi16(m_xv[26], 4), (UINT16)_mm_extract_epi16(m_xv[26], 3), (UINT16)_mm_extract_epi16(m_xv[26], 2), (UINT16)_mm_extract_epi16(m_xv[26], 1), (UINT16)_mm_extract_epi16(m_xv[26], 0));
	703	break;
	704	case RSP_V27:
	705	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[27], 7), (UINT16)_mm_extract_epi16(m_xv[27], 6), (UINT16)_mm_extract_epi16(m_xv[27], 5), (UINT16)_mm_extract_epi16(m_xv[27], 4), (UINT16)_mm_extract_epi16(m_xv[27], 3), (UINT16)_mm_extract_epi16(m_xv[27], 2), (UINT16)_mm_extract_epi16(m_xv[27], 1), (UINT16)_mm_extract_epi16(m_xv[27], 0));
	706	break;
	707	case RSP_V28:
	708	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[28], 7), (UINT16)_mm_extract_epi16(m_xv[28], 6), (UINT16)_mm_extract_epi16(m_xv[28], 5), (UINT16)_mm_extract_epi16(m_xv[28], 4), (UINT16)_mm_extract_epi16(m_xv[28], 3), (UINT16)_mm_extract_epi16(m_xv[28], 2), (UINT16)_mm_extract_epi16(m_xv[28], 1), (UINT16)_mm_extract_epi16(m_xv[28], 0));
	709	break;
	710	case RSP_V29:
	711	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[29], 7), (UINT16)_mm_extract_epi16(m_xv[29], 6), (UINT16)_mm_extract_epi16(m_xv[29], 5), (UINT16)_mm_extract_epi16(m_xv[29], 4), (UINT16)_mm_extract_epi16(m_xv[29], 3), (UINT16)_mm_extract_epi16(m_xv[29], 2), (UINT16)_mm_extract_epi16(m_xv[29], 1), (UINT16)_mm_extract_epi16(m_xv[29], 0));
	712	break;
	713	case RSP_V30:
	714	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[30], 7), (UINT16)_mm_extract_epi16(m_xv[30], 6), (UINT16)_mm_extract_epi16(m_xv[30], 5), (UINT16)_mm_extract_epi16(m_xv[30], 4), (UINT16)_mm_extract_epi16(m_xv[30], 3), (UINT16)_mm_extract_epi16(m_xv[30], 2), (UINT16)_mm_extract_epi16(m_xv[30], 1), (UINT16)_mm_extract_epi16(m_xv[30], 0));
	715	break;
	716	case RSP_V31:
	717	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)_mm_extract_epi16(m_xv[31], 7), (UINT16)_mm_extract_epi16(m_xv[31], 6), (UINT16)_mm_extract_epi16(m_xv[31], 5), (UINT16)_mm_extract_epi16(m_xv[31], 4), (UINT16)_mm_extract_epi16(m_xv[31], 3), (UINT16)_mm_extract_epi16(m_xv[31], 2), (UINT16)_mm_extract_epi16(m_xv[31], 1), (UINT16)_mm_extract_epi16(m_xv[31], 0));
	718	break;
	719	#else
	720	case RSP_V0:
	721	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S( 0, 0), (UINT16)VREG_S( 0, 1), (UINT16)VREG_S( 0, 2), (UINT16)VREG_S( 0, 3), (UINT16)VREG_S( 0, 4), (UINT16)VREG_S( 0, 5), (UINT16)VREG_S( 0, 6), (UINT16)VREG_S( 0, 7));
	722	break;
	723	case RSP_V1:
	724	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S( 1, 0), (UINT16)VREG_S( 1, 1), (UINT16)VREG_S( 1, 2), (UINT16)VREG_S( 1, 3), (UINT16)VREG_S( 1, 4), (UINT16)VREG_S( 1, 5), (UINT16)VREG_S( 1, 6), (UINT16)VREG_S( 1, 7));
	725	break;
	726	case RSP_V2:
	727	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S( 2, 0), (UINT16)VREG_S( 2, 1), (UINT16)VREG_S( 2, 2), (UINT16)VREG_S( 2, 3), (UINT16)VREG_S( 2, 4), (UINT16)VREG_S( 2, 5), (UINT16)VREG_S( 2, 6), (UINT16)VREG_S( 2, 7));
	728	break;
	729	case RSP_V3:
	730	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S( 3, 0), (UINT16)VREG_S( 3, 1), (UINT16)VREG_S( 3, 2), (UINT16)VREG_S( 3, 3), (UINT16)VREG_S( 3, 4), (UINT16)VREG_S( 3, 5), (UINT16)VREG_S( 3, 6), (UINT16)VREG_S( 3, 7));
	731	break;
	732	case RSP_V4:
	733	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S( 4, 0), (UINT16)VREG_S( 4, 1), (UINT16)VREG_S( 4, 2), (UINT16)VREG_S( 4, 3), (UINT16)VREG_S( 4, 4), (UINT16)VREG_S( 4, 5), (UINT16)VREG_S( 4, 6), (UINT16)VREG_S( 4, 7));
	734	break;
	735	case RSP_V5:
	736	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S( 5, 0), (UINT16)VREG_S( 5, 1), (UINT16)VREG_S( 5, 2), (UINT16)VREG_S( 5, 3), (UINT16)VREG_S( 5, 4), (UINT16)VREG_S( 5, 5), (UINT16)VREG_S( 5, 6), (UINT16)VREG_S( 5, 7));
	737	break;
	738	case RSP_V6:
	739	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S( 6, 0), (UINT16)VREG_S( 6, 1), (UINT16)VREG_S( 6, 2), (UINT16)VREG_S( 6, 3), (UINT16)VREG_S( 6, 4), (UINT16)VREG_S( 6, 5), (UINT16)VREG_S( 6, 6), (UINT16)VREG_S( 6, 7));
	740	break;
	741	case RSP_V7:
	742	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S( 7, 0), (UINT16)VREG_S( 7, 1), (UINT16)VREG_S( 7, 2), (UINT16)VREG_S( 7, 3), (UINT16)VREG_S( 7, 4), (UINT16)VREG_S( 7, 5), (UINT16)VREG_S( 7, 6), (UINT16)VREG_S( 7, 7));
	743	break;
	744	case RSP_V8:
	745	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S( 8, 0), (UINT16)VREG_S( 8, 1), (UINT16)VREG_S( 8, 2), (UINT16)VREG_S( 8, 3), (UINT16)VREG_S( 8, 4), (UINT16)VREG_S( 8, 5), (UINT16)VREG_S( 8, 6), (UINT16)VREG_S( 8, 7));
	746	break;
	747	case RSP_V9:
	748	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S( 9, 0), (UINT16)VREG_S( 9, 1), (UINT16)VREG_S( 9, 2), (UINT16)VREG_S( 9, 3), (UINT16)VREG_S( 9, 4), (UINT16)VREG_S( 9, 5), (UINT16)VREG_S( 9, 6), (UINT16)VREG_S( 9, 7));
	749	break;
	750	case RSP_V10:
	751	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(10, 0), (UINT16)VREG_S(10, 1), (UINT16)VREG_S(10, 2), (UINT16)VREG_S(10, 3), (UINT16)VREG_S(10, 4), (UINT16)VREG_S(10, 5), (UINT16)VREG_S(10, 6), (UINT16)VREG_S(10, 7));
	752	break;
	753	case RSP_V11:
	754	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(11, 0), (UINT16)VREG_S(11, 1), (UINT16)VREG_S(11, 2), (UINT16)VREG_S(11, 3), (UINT16)VREG_S(11, 4), (UINT16)VREG_S(11, 5), (UINT16)VREG_S(11, 6), (UINT16)VREG_S(11, 7));
	755	break;
	756	case RSP_V12:
	757	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(12, 0), (UINT16)VREG_S(12, 1), (UINT16)VREG_S(12, 2), (UINT16)VREG_S(12, 3), (UINT16)VREG_S(12, 4), (UINT16)VREG_S(12, 5), (UINT16)VREG_S(12, 6), (UINT16)VREG_S(12, 7));
	758	break;
	759	case RSP_V13:
	760	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(13, 0), (UINT16)VREG_S(13, 1), (UINT16)VREG_S(13, 2), (UINT16)VREG_S(13, 3), (UINT16)VREG_S(13, 4), (UINT16)VREG_S(13, 5), (UINT16)VREG_S(13, 6), (UINT16)VREG_S(13, 7));
	761	break;
	762	case RSP_V14:
	763	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(14, 0), (UINT16)VREG_S(14, 1), (UINT16)VREG_S(14, 2), (UINT16)VREG_S(14, 3), (UINT16)VREG_S(14, 4), (UINT16)VREG_S(14, 5), (UINT16)VREG_S(14, 6), (UINT16)VREG_S(14, 7));
	764	break;
	765	case RSP_V15:
	766	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(15, 0), (UINT16)VREG_S(15, 1), (UINT16)VREG_S(15, 2), (UINT16)VREG_S(15, 3), (UINT16)VREG_S(15, 4), (UINT16)VREG_S(15, 5), (UINT16)VREG_S(15, 6), (UINT16)VREG_S(15, 7));
	767	break;
	768	case RSP_V16:
	769	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(16, 0), (UINT16)VREG_S(16, 1), (UINT16)VREG_S(16, 2), (UINT16)VREG_S(16, 3), (UINT16)VREG_S(16, 4), (UINT16)VREG_S(16, 5), (UINT16)VREG_S(16, 6), (UINT16)VREG_S(16, 7));
	770	break;
	771	case RSP_V17:
	772	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(17, 0), (UINT16)VREG_S(17, 1), (UINT16)VREG_S(17, 2), (UINT16)VREG_S(17, 3), (UINT16)VREG_S(17, 4), (UINT16)VREG_S(17, 5), (UINT16)VREG_S(17, 6), (UINT16)VREG_S(17, 7));
	773	break;
	774	case RSP_V18:
	775	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(18, 0), (UINT16)VREG_S(18, 1), (UINT16)VREG_S(18, 2), (UINT16)VREG_S(18, 3), (UINT16)VREG_S(18, 4), (UINT16)VREG_S(18, 5), (UINT16)VREG_S(18, 6), (UINT16)VREG_S(18, 7));
	776	break;
	777	case RSP_V19:
	778	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(19, 0), (UINT16)VREG_S(19, 1), (UINT16)VREG_S(19, 2), (UINT16)VREG_S(19, 3), (UINT16)VREG_S(19, 4), (UINT16)VREG_S(19, 5), (UINT16)VREG_S(19, 6), (UINT16)VREG_S(19, 7));
	779	break;
	780	case RSP_V20:
	781	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(20, 0), (UINT16)VREG_S(20, 1), (UINT16)VREG_S(20, 2), (UINT16)VREG_S(20, 3), (UINT16)VREG_S(20, 4), (UINT16)VREG_S(20, 5), (UINT16)VREG_S(20, 6), (UINT16)VREG_S(20, 7));
	782	break;
	783	case RSP_V21:
	784	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(21, 0), (UINT16)VREG_S(21, 1), (UINT16)VREG_S(21, 2), (UINT16)VREG_S(21, 3), (UINT16)VREG_S(21, 4), (UINT16)VREG_S(21, 5), (UINT16)VREG_S(21, 6), (UINT16)VREG_S(21, 7));
	785	break;
	786	case RSP_V22:
	787	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(22, 0), (UINT16)VREG_S(22, 1), (UINT16)VREG_S(22, 2), (UINT16)VREG_S(22, 3), (UINT16)VREG_S(22, 4), (UINT16)VREG_S(22, 5), (UINT16)VREG_S(22, 6), (UINT16)VREG_S(22, 7));
	788	break;
	789	case RSP_V23:
	790	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(23, 0), (UINT16)VREG_S(23, 1), (UINT16)VREG_S(23, 2), (UINT16)VREG_S(23, 3), (UINT16)VREG_S(23, 4), (UINT16)VREG_S(23, 5), (UINT16)VREG_S(23, 6), (UINT16)VREG_S(23, 7));
	791	break;
	792	case RSP_V24:
	793	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(24, 0), (UINT16)VREG_S(24, 1), (UINT16)VREG_S(24, 2), (UINT16)VREG_S(24, 3), (UINT16)VREG_S(24, 4), (UINT16)VREG_S(24, 5), (UINT16)VREG_S(24, 6), (UINT16)VREG_S(24, 7));
	794	break;
	795	case RSP_V25:
	796	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(25, 0), (UINT16)VREG_S(25, 1), (UINT16)VREG_S(25, 2), (UINT16)VREG_S(25, 3), (UINT16)VREG_S(25, 4), (UINT16)VREG_S(25, 5), (UINT16)VREG_S(25, 6), (UINT16)VREG_S(25, 7));
	797	break;
	798	case RSP_V26:
	799	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(26, 0), (UINT16)VREG_S(26, 1), (UINT16)VREG_S(26, 2), (UINT16)VREG_S(26, 3), (UINT16)VREG_S(26, 4), (UINT16)VREG_S(26, 5), (UINT16)VREG_S(26, 6), (UINT16)VREG_S(26, 7));
	800	break;
	801	case RSP_V27:
	802	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(27, 0), (UINT16)VREG_S(27, 1), (UINT16)VREG_S(27, 2), (UINT16)VREG_S(27, 3), (UINT16)VREG_S(27, 4), (UINT16)VREG_S(27, 5), (UINT16)VREG_S(27, 6), (UINT16)VREG_S(27, 7));
	803	break;
	804	case RSP_V28:
	805	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(28, 0), (UINT16)VREG_S(28, 1), (UINT16)VREG_S(28, 2), (UINT16)VREG_S(28, 3), (UINT16)VREG_S(28, 4), (UINT16)VREG_S(28, 5), (UINT16)VREG_S(28, 6), (UINT16)VREG_S(28, 7));
	806	break;
	807	case RSP_V29:
	808	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(29, 0), (UINT16)VREG_S(29, 1), (UINT16)VREG_S(29, 2), (UINT16)VREG_S(29, 3), (UINT16)VREG_S(29, 4), (UINT16)VREG_S(29, 5), (UINT16)VREG_S(29, 6), (UINT16)VREG_S(29, 7));
	809	break;
	810	case RSP_V30:
	811	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(30, 0), (UINT16)VREG_S(30, 1), (UINT16)VREG_S(30, 2), (UINT16)VREG_S(30, 3), (UINT16)VREG_S(30, 4), (UINT16)VREG_S(30, 5), (UINT16)VREG_S(30, 6), (UINT16)VREG_S(30, 7));
	812	break;
	813	case RSP_V31:
	814	string.printf("%04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X", (UINT16)VREG_S(31, 0), (UINT16)VREG_S(31, 1), (UINT16)VREG_S(31, 2), (UINT16)VREG_S(31, 3), (UINT16)VREG_S(31, 4), (UINT16)VREG_S(31, 5), (UINT16)VREG_S(31, 6), (UINT16)VREG_S(31, 7));
	815	break;
	816	#endif
	817
	818	}
	819	}
	820
	821	void rsp_device::device_stop()
	822	{
342	823	#if SAVE_DISASM
343	824	{
344	825	char string[200];
r31833	r31834
364	845
365	846	for (i=0; i < 0x1000; i+=4)
366	847	{
367		fprintf(dmem, "%08X: %08X\n", 0x04000000 + i, READ32(rsp, 0x04000000 + i));
	848	fprintf(dmem, "%08X: %08X\n", 0x04000000 + i, READ32(0x04000000 + i));
368	849	}
369	850	fclose(dmem);
370	851	#endif
r31833	r31834
372	853
373	854	for (i=0; i < 0x1000; i++)
374	855	{
375		fputc(READ8(rsp, 0x04000000 + i), dmem);
	856	fputc(READ8(0x04000000 + i), dmem);
376	857	}
377	858	fclose(dmem);
378	859	}
379	860	#endif
380	861
381		if (rsp->exec_output)
382		fclose(rsp->exec_output);
383		rsp->exec_output = NULL;
	862	if (m_exec_output)
	863	fclose(m_exec_output);
	864	m_exec_output = NULL;
	865
	866	/* clean up the DRC */
	867	if ( m_drcuml )
	868	{
	869	auto_free(machine(), m_drcuml);
	870	}
	871	if (m_drcfe )
	872	{
	873	auto_free(machine(), m_drcfe);
	874	}
384	875	}
385	876
386		static CPU_RESET( rsp )
	877	void rsp_device::device_reset()
387	878	{
388		rsp_state *rsp = get_safe_token(device);
389		rsp->nextpc = ~0;
	879	m_nextpc = ~0;
390	880	}
391	881
392		static void handle_lwc2(rsp_state *rsp, UINT32 op)
	882	void rsp_device::handle_lwc2(UINT32 op)
393	883	{
394	884	int i, end;
395	885	UINT32 ea;
r31833	r31834
411	901	//
412	902	// Load 1 byte to vector byte index
413	903
414		ea = (base) ? rsp->r[base] + offset : offset;
415		VREG_B(dest, index) = READ8(rsp, ea);
	904	ea = (base) ? m_rsp_state->r[base] + offset : offset;
	905	VREG_B(dest, index) = READ8(ea);
416	906	break;
417	907	}
418	908	case 0x01:      /* LSV */
r31833	r31834
424	914	//
425	915	// Loads 2 bytes starting from vector byte index
426	916
427		ea = (base) ? rsp->r[base] + (offset * 2) : (offset * 2);
	917	ea = (base) ? m_rsp_state->r[base] + (offset * 2) : (offset * 2);
428	918
429	919	end = index + 2;
430	920
431	921	for (i=index; i < end; i++)
432	922	{
433		VREG_B(dest, i) = READ8(rsp, ea);
	923	VREG_B(dest, i) = READ8(ea);
434	924	ea++;
435	925	}
436	926	break;
r31833	r31834
444	934	//
445	935	// Loads 4 bytes starting from vector byte index
446	936
447		ea = (base) ? rsp->r[base] + (offset * 4) : (offset * 4);
	937	ea = (base) ? m_rsp_state->r[base] + (offset * 4) : (offset * 4);
448	938
449	939	end = index + 4;
450	940
451	941	for (i=index; i < end; i++)
452	942	{
453		VREG_B(dest, i) = READ8(rsp, ea);
	943	VREG_B(dest, i) = READ8(ea);
454	944	ea++;
455	945	}
456	946	break;
r31833	r31834
464	954	//
465	955	// Loads 8 bytes starting from vector byte index
466	956
467		ea = (base) ? rsp->r[base] + (offset * 8) : (offset * 8);
	957	ea = (base) ? m_rsp_state->r[base] + (offset * 8) : (offset * 8);
468	958
469	959	end = index + 8;
470	960
471	961	for (i=index; i < end; i++)
472	962	{
473		VREG_B(dest, i) = READ8(rsp, ea);
	963	VREG_B(dest, i) = READ8(ea);
474	964	ea++;
475	965	}
476	966	break;
r31833	r31834
484	974	//
485	975	// Loads up to 16 bytes starting from vector byte index
486	976
487		ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	977	ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
488	978
489	979	end = index + (16 - (ea & 0xf));
490	980	if (end > 16) end = 16;
491	981
492	982	for (i=index; i < end; i++)
493	983	{
494		VREG_B(dest, i) = READ8(rsp, ea);
	984	VREG_B(dest, i) = READ8(ea);
495	985	ea++;
496	986	}
497	987	break;
r31833	r31834
505	995	//
506	996	// Stores up to 16 bytes starting from right side until 16-byte boundary
507	997
508		ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	998	ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
509	999
510	1000	index = 16 - ((ea & 0xf) - index);
511	1001	end = 16;
r31833	r31834
513	1003
514	1004	for (i=index; i < end; i++)
515	1005	{
516		VREG_B(dest, i) = READ8(rsp, ea);
	1006	VREG_B(dest, i) = READ8(ea);
517	1007	ea++;
518	1008	}
519	1009	break;
r31833	r31834
527	1017	//
528	1018	// Loads a byte as the upper 8 bits of each element
529	1019
530		ea = (base) ? rsp->r[base] + (offset * 8) : (offset * 8);
	1020	ea = (base) ? m_rsp_state->r[base] + (offset * 8) : (offset * 8);
531	1021
532	1022	for (i=0; i < 8; i++)
533	1023	{
534		VREG_S(dest, i) = READ8(rsp, ea + (((16-index) + i) & 0xf)) << 8;
	1024	VREG_S(dest, i) = READ8(ea + (((16-index) + i) & 0xf)) << 8;
535	1025	}
536	1026	break;
537	1027	}
r31833	r31834
544	1034	//
545	1035	// Loads a byte as the bits 14-7 of each element
546	1036
547		ea = (base) ? rsp->r[base] + (offset * 8) : (offset * 8);
	1037	ea = (base) ? m_rsp_state->r[base] + (offset * 8) : (offset * 8);
548	1038
549	1039	for (i=0; i < 8; i++)
550	1040	{
551		VREG_S(dest, i) = READ8(rsp, ea + (((16-index) + i) & 0xf)) << 7;
	1041	VREG_S(dest, i) = READ8(ea + (((16-index) + i) & 0xf)) << 7;
552	1042	}
553	1043	break;
554	1044	}
r31833	r31834
561	1051	//
562	1052	// Loads a byte as the bits 14-7 of each element, with 2-byte stride
563	1053
564		ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	1054	ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
565	1055
566	1056	for (i=0; i < 8; i++)
567	1057	{
568		VREG_S(dest, i) = READ8(rsp, ea + (((16-index) + (i<<1)) & 0xf)) << 7;
	1058	VREG_S(dest, i) = READ8(ea + (((16-index) + (i<<1)) & 0xf)) << 7;
569	1059	}
570	1060	break;
571	1061	}
r31833	r31834
578	1068	//
579	1069	// Loads a byte as the bits 14-7 of upper or lower quad, with 4-byte stride
580	1070
581		ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	1071	ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
582	1072
583	1073	// not sure what happens if 16-byte boundary is crossed...
584	1074
r31833	r31834
586	1076
587	1077	for (i=index >> 1; i < end; i++)
588	1078	{
589		VREG_S(dest, i) = READ8(rsp, ea) << 7;
	1079	VREG_S(dest, i) = READ8(ea) << 7;
590	1080	ea += 4;
591	1081	}
592	1082	break;
r31833	r31834
601	1091	// Loads the full 128-bit vector starting from vector byte index and wrapping to index 0
602	1092	// after byte index 15
603	1093
604		ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	1094	ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
605	1095
606	1096	// not sure what happens if 16-byte boundary is crossed...
607		if ((ea & 0xf) > 0) fatalerror("RSP: LWV: 16-byte boundary crossing at %08X, recheck this!\n", rsp->ppc);
	1097	if ((ea & 0xf) > 0) fatalerror("RSP: LWV: 16-byte boundary crossing at %08X, recheck this!\n", m_ppc);
608	1098
609	1099	end = (16 - index) + 16;
610	1100
611	1101	for (i=(16 - index); i < end; i++)
612	1102	{
613		VREG_B(dest, i & 0xf) = READ8(rsp, ea);
	1103	VREG_B(dest, i & 0xf) = READ8(ea);
614	1104	ea += 4;
615	1105	}
616	1106	break;
r31833	r31834
636	1126
637	1127	if (index & 1)  fatalerror("RSP: LTV: index = %d\n", index);
638	1128
639		ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	1129	ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
640	1130
641	1131	ea = ((ea + 8) & ~0xf) + (index & 1);
642	1132	for (i=vs; i < ve; i++)
643	1133	{
644	1134	element = ((8 - (index >> 1) + (i-vs)) << 1);
645		VREG_B(i, (element & 0xf)) = READ8(rsp, ea);
646		VREG_B(i, ((element + 1) & 0xf)) = READ8(rsp, ea + 1);
	1135	VREG_B(i, (element & 0xf)) = READ8(ea);
	1136	VREG_B(i, ((element + 1) & 0xf)) = READ8(ea + 1);
647	1137
648	1138	ea += 2;
649	1139	}
r31833	r31834
652	1142
653	1143	default:
654	1144	{
655		unimplemented_opcode(rsp, op);
	1145	unimplemented_opcode(op);
656	1146	break;
657	1147	}
658	1148	}
659	1149	}
660	1150
661		static void handle_swc2(rsp_state *rsp, UINT32 op)
	1151	void rsp_device::handle_swc2(UINT32 op)
662	1152	{
663	1153	int i, end;
664	1154	int eaoffset;
r31833	r31834
681	1171	//
682	1172	// Stores 1 byte from vector byte index
683	1173
684		ea = (base) ? rsp->r[base] + offset : offset;
685		WRITE8(rsp, ea, VREG_B(dest, index));
	1174	ea = (base) ? m_rsp_state->r[base] + offset : offset;
	1175	WRITE8(ea, VREG_B(dest, index));
686	1176	break;
687	1177	}
688	1178	case 0x01:      /* SSV */
r31833	r31834
694	1184	//
695	1185	// Stores 2 bytes starting from vector byte index
696	1186
697		ea = (base) ? rsp->r[base] + (offset * 2) : (offset * 2);
	1187	ea = (base) ? m_rsp_state->r[base] + (offset * 2) : (offset * 2);
698	1188
699	1189	end = index + 2;
700	1190
701	1191	for (i=index; i < end; i++)
702	1192	{
703		WRITE8(rsp, ea, VREG_B(dest, i));
	1193	WRITE8(ea, VREG_B(dest, i));
704	1194	ea++;
705	1195	}
706	1196	break;
r31833	r31834
714	1204	//
715	1205	// Stores 4 bytes starting from vector byte index
716	1206
717		ea = (base) ? rsp->r[base] + (offset * 4) : (offset * 4);
	1207	ea = (base) ? m_rsp_state->r[base] + (offset * 4) : (offset * 4);
718	1208
719	1209	end = index + 4;
720	1210
721	1211	for (i=index; i < end; i++)
722	1212	{
723		WRITE8(rsp, ea, VREG_B(dest, i));
	1213	WRITE8(ea, VREG_B(dest, i));
724	1214	ea++;
725	1215	}
726	1216	break;
r31833	r31834
734	1224	//
735	1225	// Stores 8 bytes starting from vector byte index
736	1226
737		ea = (base) ? rsp->r[base] + (offset * 8) : (offset * 8);
	1227	ea = (base) ? m_rsp_state->r[base] + (offset * 8) : (offset * 8);
738	1228
739	1229	end = index + 8;
740	1230
741	1231	for (i=index; i < end; i++)
742	1232	{
743		WRITE8(rsp, ea, VREG_B(dest, i));
	1233	WRITE8(ea, VREG_B(dest, i));
744	1234	ea++;
745	1235	}
746	1236	break;
r31833	r31834
754	1244	//
755	1245	// Stores up to 16 bytes starting from vector byte index until 16-byte boundary
756	1246
757		ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	1247	ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
758	1248
759	1249	end = index + (16 - (ea & 0xf));
760	1250
761	1251	for (i=index; i < end; i++)
762	1252	{
763		WRITE8(rsp, ea, VREG_B(dest, i & 0xf));
	1253	WRITE8(ea, VREG_B(dest, i & 0xf));
764	1254	ea++;
765	1255	}
766	1256	break;
r31833	r31834
775	1265	// Stores up to 16 bytes starting from right side until 16-byte boundary
776	1266
777	1267	int o;
778		ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	1268	ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
779	1269
780	1270	end = index + (ea & 0xf);
781	1271	o = (16 - (ea & 0xf)) & 0xf;
r31833	r31834
783	1273
784	1274	for (i=index; i < end; i++)
785	1275	{
786		WRITE8(rsp, ea, VREG_B(dest, ((i + o) & 0xf)));
	1276	WRITE8(ea, VREG_B(dest, ((i + o) & 0xf)));
787	1277	ea++;
788	1278	}
789	1279	break;
r31833	r31834
797	1287	//
798	1288	// Stores upper 8 bits of each element
799	1289
800		ea = (base) ? rsp->r[base] + (offset * 8) : (offset * 8);
	1290	ea = (base) ? m_rsp_state->r[base] + (offset * 8) : (offset * 8);
801	1291	end = index + 8;
802	1292
803	1293	for (i=index; i < end; i++)
804	1294	{
805	1295	if ((i & 0xf) < 8)
806	1296	{
807		WRITE8(rsp, ea, VREG_B(dest, ((i & 0xf) << 1)));
	1297	WRITE8(ea, VREG_B(dest, ((i & 0xf) << 1)));
808	1298	}
809	1299	else
810	1300	{
811		WRITE8(rsp, ea, VREG_S(dest, (i & 0x7)) >> 7);
	1301	WRITE8(ea, VREG_S(dest, (i & 0x7)) >> 7);
812	1302	}
813	1303	ea++;
814	1304	}
r31833	r31834
823	1313	//
824	1314	// Stores bits 14-7 of each element
825	1315
826		ea = (base) ? rsp->r[base] + (offset * 8) : (offset * 8);
	1316	ea = (base) ? m_rsp_state->r[base] + (offset * 8) : (offset * 8);
827	1317	end = index + 8;
828	1318
829	1319	for (i=index; i < end; i++)
830	1320	{
831	1321	if ((i & 0xf) < 8)
832	1322	{
833		WRITE8(rsp, ea, VREG_S(dest, (i & 0x7)) >> 7);
	1323	WRITE8(ea, VREG_S(dest, (i & 0x7)) >> 7);
834	1324	}
835	1325	else
836	1326	{
837		WRITE8(rsp, ea, VREG_B(dest, ((i & 0x7) << 1)));
	1327	WRITE8(ea, VREG_B(dest, ((i & 0x7) << 1)));
838	1328	}
839	1329	ea++;
840	1330	}
r31833	r31834
849	1339	//
850	1340	// Stores bits 14-7 of each element, with 2-byte stride
851	1341
852		ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	1342	ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
853	1343
854	1344	for (i=0; i < 8; i++)
855	1345	{
856	1346	UINT8 d = ((VREG_B(dest, ((index + (i << 1) + 0) & 0xf))) << 1) |
857	1347	((VREG_B(dest, ((index + (i << 1) + 1) & 0xf))) >> 7);
858	1348
859		WRITE8(rsp, ea, d);
	1349	WRITE8(ea, d);
860	1350	ea += 2;
861	1351	}
862	1352	break;
r31833	r31834
872	1362
873	1363	// FIXME: only works for index 0 and index 8
874	1364
875		if (index & 0x7)    osd_printf_debug("RSP: SFV: index = %d at %08X\n", index, rsp->ppc);
	1365	if (index & 0x7)    osd_printf_debug("RSP: SFV: index = %d at %08X\n", index, m_ppc);
876	1366
877		ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	1367	ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
878	1368
879	1369	eaoffset = ea & 0xf;
880	1370	ea &= ~0xf;
r31833	r31834
883	1373
884	1374	for (i=index >> 1; i < end; i++)
885	1375	{
886		WRITE8(rsp, ea + (eaoffset & 0xf), VREG_S(dest, i) >> 7);
	1376	WRITE8(ea + (eaoffset & 0xf), VREG_S(dest, i) >> 7);
887	1377	eaoffset += 4;
888	1378	}
889	1379	break;
r31833	r31834
898	1388	// Stores the full 128-bit vector starting from vector byte index and wrapping to index 0
899	1389	// after byte index 15
900	1390
901		ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	1391	ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
902	1392
903	1393	eaoffset = ea & 0xf;
904	1394	ea &= ~0xf;
r31833	r31834
907	1397
908	1398	for (i=index; i < end; i++)
909	1399	{
910		WRITE8(rsp, ea + (eaoffset & 0xf), VREG_B(dest, i & 0xf));
	1400	WRITE8(ea + (eaoffset & 0xf), VREG_B(dest, i & 0xf));
911	1401	eaoffset++;
912	1402	}
913	1403	break;
r31833	r31834
929	1419
930	1420	element = 8 - (index >> 1);
931	1421
932		ea = (base) ? rsp->r[base] + (offset * 16) : (offset * 16);
	1422	ea = (base) ? m_rsp_state->r[base] + (offset * 16) : (offset * 16);
933	1423
934	1424	eaoffset = (ea & 0xf) + (element * 2);
935	1425	ea &= ~0xf;
936	1426
937	1427	for (i=vs; i < ve; i++)
938	1428	{
939		WRITE16(rsp, ea + (eaoffset & 0xf), VREG_S(i, element & 0x7));
	1429	WRITE16(ea + (eaoffset & 0xf), VREG_S(i, element & 0x7));
940	1430	eaoffset += 2;
941	1431	element++;
942	1432	}
r31833	r31834
945	1435
946	1436	default:
947	1437	{
948		unimplemented_opcode(rsp, op);
	1438	unimplemented_opcode(op);
949	1439	break;
950	1440	}
951	1441	}
952	1442	}
953	1443
954		INLINE UINT16 SATURATE_ACCUM(rsp_state *rsp, int accum, int slice, UINT16 negative, UINT16 positive)
	1444	inline UINT16 rsp_device::SATURATE_ACCUM(int accum, int slice, UINT16 negative, UINT16 positive)
955	1445	{
956	1446	if ((INT16)ACCUM_H(accum) < 0)
957	1447	{
r31833	r31834
1007	1497	return 0;
1008	1498	}
1009	1499
1010		INLINE UINT16 SATURATE_ACCUM1(rsp_state *rsp, int accum, UINT16 negative, UINT16 positive)
	1500	inline UINT16 rsp_device::SATURATE_ACCUM1(int accum, UINT16 negative, UINT16 positive)
1011	1501	{
1012	1502	if ((INT16)ACCUM_H(accum) < 0)
1013	1503	{
r31833	r31834
1049	1539	return 0;
1050	1540	}
1051	1541
1052		#define WRITEBACK_RESULT() {memcpy(&rsp->v[VDREG].s[0], &vres[0], 16);}
	1542	#define WRITEBACK_RESULT() {memcpy(&m_v[VDREG].s[0], &vres[0], 16);}
1053	1543
1054	1544	#if 0
1055	1545	static float float_round(float input)
r31833	r31834
1069	1559	}
1070	1560	#endif
1071	1561
1072		static void handle_vector_ops(rsp_state *rsp, UINT32 op)
	1562	void rsp_device::handle_vector_ops(UINT32 op)
1073	1563	{
1074	1564	int i;
1075	1565	UINT32 VS1REG = (op >> 11) & 0x1f;
r31833	r31834
1315	1805	r = s1 * s2;
1316	1806
1317	1807	ACCUM(i) += (INT64)(r) << 17;
1318		res = SATURATE_ACCUM(rsp, i, 1, 0x8000, 0x7fff);
	1808	res = SATURATE_ACCUM(i, 1, 0x8000, 0x7fff);
1319	1809
1320	1810	vres[i] = res;
1321	1811	}
r31833	r31834
1406	1896	ACCUM_M(i) = (UINT16)(r3);
1407	1897	ACCUM_H(i) += (INT16)(r3 >> 16);
1408	1898
1409		res = SATURATE_ACCUM(rsp, i, 0, 0x0000, 0xffff);
	1899	res = SATURATE_ACCUM(i, 0, 0x0000, 0xffff);
1410	1900
1411	1901	vres[i] = res;
1412	1902	}
r31833	r31834
1444	1934	if ((INT32)(r1) < 0)
1445	1935	ACCUM_H(i) -= 1;
1446	1936
1447		res = SATURATE_ACCUM(rsp, i, 1, 0x8000, 0x7fff);
	1937	res = SATURATE_ACCUM(i, 1, 0x8000, 0x7fff);
1448	1938
1449	1939	vres[i] = res;
1450	1940	}
r31833	r31834
1474	1964
1475	1965	ACCUM(i) += (INT64)(s1*s2)<<16;
1476	1966
1477		res = SATURATE_ACCUM(rsp, i, 0, 0x0000, 0xffff);
	1967	res = SATURATE_ACCUM(i, 0, 0x0000, 0xffff);
1478	1968	vres[i] = res;
1479	1969	}
1480	1970	WRITEBACK_RESULT();
r31833	r31834
1502	1992	s1 = (INT32)(INT16)VREG_S(VS1REG, i);
1503	1993	s2 = (INT32)(INT16)VREG_S(VS2REG, sel);
1504	1994
1505		rsp->accum[i].l[1] += s1*s2;
	1995	m_accum[i].l[1] += s1*s2;
1506	1996
1507		res = SATURATE_ACCUM1(rsp, i, 0x8000, 0x7fff);
	1997	res = SATURATE_ACCUM1(i, 0x8000, 0x7fff);
1508	1998
1509	1999	vres[i] = res;
1510	2000	}
r31833	r31834
2351	2841	}
2352	2842	rec = temp;
2353	2843
2354		rsp->reciprocal_res = rec;
2355		rsp->dp_allowed = 0;
	2844	m_reciprocal_res = rec;
	2845	m_dp_allowed = 0;
2356	2846
2357	2847	VREG_S(VDREG, del) = (UINT16)(rec & 0xffff);
2358	2848
r31833	r31834
2379	2869	int sel = EL & 7;
2380	2870	INT32 shifter = 0;
2381	2871
2382		INT32 rec = ((UINT16)(VREG_S(VS2REG, sel)) | ((UINT32)(rsp->reciprocal_high) & 0xffff0000));
	2872	INT32 rec = ((UINT16)(VREG_S(VS2REG, sel)) | ((UINT32)(m_reciprocal_high) & 0xffff0000));
2383	2873
2384	2874	INT32 datainput = rec;
2385	2875
2386	2876	if (rec < 0)
2387	2877	{
2388		if (rsp->dp_allowed)
	2878	if (m_dp_allowed)
2389	2879	{
2390	2880	if (rec < -32768)
2391	2881	{
r31833	r31834
2416	2906	}
2417	2907	else
2418	2908	{
2419		if (rsp->dp_allowed)
	2909	if (m_dp_allowed)
2420	2910	{
2421	2911	shifter = 0;
2422	2912	}
r31833	r31834
2443	2933	}
2444	2934	rec = temp;
2445	2935
2446		rsp->reciprocal_res = rec;
2447		rsp->dp_allowed = 0;
	2936	m_reciprocal_res = rec;
	2937	m_dp_allowed = 0;
2448	2938
2449	2939	VREG_S(VDREG, del) = (UINT16)(rec & 0xffff);
2450	2940
r31833	r31834
2469	2959	int del = VS1REG & 7;
2470	2960	int sel = EL & 7;
2471	2961
2472		rsp->reciprocal_high = (VREG_S(VS2REG, sel)) << 16;
2473		rsp->dp_allowed = 1;
	2962	m_reciprocal_high = (VREG_S(VS2REG, sel)) << 16;
	2963	m_dp_allowed = 1;
2474	2964
2475	2965	for (i = 0; i < 8; i++)
2476	2966	{
r31833	r31834
2478	2968	ACCUM_L(i) = VREG_S(VS2REG, sel);
2479	2969	}
2480	2970
2481		VREG_S(VDREG, del) = (INT16)(rsp->reciprocal_res >> 16);
	2971	VREG_S(VDREG, del) = (INT16)(m_reciprocal_res >> 16);
2482	2972
2483	2973	break;
2484	2974	}
r31833	r31834
2554	3044	}
2555	3045	rec = temp;
2556	3046
2557		rsp->reciprocal_res = rec;
2558		rsp->dp_allowed = 0;
	3047	m_reciprocal_res = rec;
	3048	m_dp_allowed = 0;
2559	3049
2560	3050	VREG_S(VDREG, del) = (UINT16)(rec & 0xffff);
2561	3051
r31833	r31834
2581	3071	int sel = EL & 7;
2582	3072	INT32 shifter = 0;
2583	3073
2584		INT32 rec = ((UINT16)(VREG_S(VS2REG, sel)) | ((UINT32)(rsp->reciprocal_high) & 0xffff0000));
	3074	INT32 rec = ((UINT16)(VREG_S(VS2REG, sel)) | ((UINT32)(m_reciprocal_high) & 0xffff0000));
2585	3075
2586	3076	INT32 datainput = rec;
2587	3077
2588	3078	if (rec < 0)
2589	3079	{
2590		if (rsp->dp_allowed)
	3080	if (m_dp_allowed)
2591	3081	{
2592	3082	if (rec < -32768)//VDIV.C,208
2593	3083	{
r31833	r31834
2617	3107	}
2618	3108	else
2619	3109	{
2620		if (rsp->dp_allowed)
	3110	if (m_dp_allowed)
2621	3111	{
2622	3112	shifter = 0;
2623	3113	}
r31833	r31834
2646	3136	}
2647	3137	rec = temp;
2648	3138
2649		rsp->reciprocal_res = rec;
2650		rsp->dp_allowed = 0;
	3139	m_reciprocal_res = rec;
	3140	m_dp_allowed = 0;
2651	3141
2652	3142	VREG_S(VDREG, del) = (UINT16)(rec & 0xffff);
2653	3143
r31833	r31834
2672	3162	int del = VS1REG & 7;
2673	3163	int sel = EL & 7;
2674	3164
2675		rsp->reciprocal_high = (VREG_S(VS2REG, sel)) << 16;
2676		rsp->dp_allowed = 1;
	3165	m_reciprocal_high = (VREG_S(VS2REG, sel)) << 16;
	3166	m_dp_allowed = 1;
2677	3167
2678	3168	for (i=0; i < 8; i++)
2679	3169	{
r31833	r31834
2681	3171	ACCUM_L(i) = VREG_S(VS2REG, sel);
2682	3172	}
2683	3173
2684		VREG_S(VDREG, del) = (INT16)(rsp->reciprocal_res >> 16);    // store high part
	3174	VREG_S(VDREG, del) = (INT16)(m_reciprocal_res >> 16);    // store high part
2685	3175	break;
2686	3176	}
2687	3177
r31833	r31834
2697	3187	break;
2698	3188	}
2699	3189
2700		default:    unimplemented_opcode(rsp, op); break;
	3190	default:    unimplemented_opcode(op); break;
2701	3191	}
2702	3192	}
2703	3193
2704		static CPU_EXECUTE( rsp )
	3194	void rsp_device::execute_run()
2705	3195	{
2706		rsp_state *rsp = get_safe_token(device);
2707		UINT32 op;
	3196	if (m_isdrc)
	3197	{
	3198	execute_run_drc();
	3199	return;
	3200	}
2708	3201
2709		rsp->pc = 0x4001000 | (rsp->pc & 0xfff);
	3202	m_rsp_state->pc = 0x4001000 | (m_rsp_state->pc & 0xfff);
2710	3203
2711		if( rsp->sr & ( RSP_STATUS_HALT | RSP_STATUS_BROKE ) )
	3204	if( m_sr & ( RSP_STATUS_HALT | RSP_STATUS_BROKE ) )
2712	3205	{
2713		rsp->icount = MIN(rsp->icount, 0);
	3206	m_rsp_state->icount = MIN(m_rsp_state->icount, 0);
2714	3207	}
2715	3208
2716		while (rsp->icount > 0)
	3209	while (m_rsp_state->icount > 0)
2717	3210	{
2718		rsp->ppc = rsp->pc;
2719		debugger_instruction_hook(device, rsp->pc);
	3211	m_ppc = m_rsp_state->pc;
	3212	debugger_instruction_hook(this, m_rsp_state->pc);
2720	3213
2721		op = ROPCODE(rsp->pc);
2722		if (rsp->nextpc != ~0)
	3214	UINT32 op = ROPCODE(m_rsp_state->pc);
	3215	if (m_nextpc != ~0)
2723	3216	{
2724		rsp->pc = rsp->nextpc;
2725		rsp->nextpc = ~0;
	3217	m_rsp_state->pc = m_nextpc;
	3218	m_nextpc = ~0;
2726	3219	}
2727	3220	else
2728	3221	{
2729		rsp->pc += 4;
	3222	m_rsp_state->pc += 4;
2730	3223	}
2731	3224
2732	3225	switch (op >> 26)
r31833	r31834
2745	3238	case 0x09:  /* JALR */      JUMP_PC_L(RSVAL, RDREG); break;
2746	3239	case 0x0d:  /* BREAK */
2747	3240	{
2748		(rsp->device->sp_set_status_func)(0, 0x3, 0xffffffff);
2749		rsp->icount = MIN(rsp->icount, 1);
	3241	m_sp_set_status_func(0, 0x3, 0xffffffff);
	3242	m_rsp_state->icount = MIN(m_rsp_state->icount, 1);
2750	3243
2751		if (LOG_INSTRUCTION_EXECUTION) fprintf(rsp->exec_output, "\n---------- break ----------\n\n");
	3244	if (LOG_INSTRUCTION_EXECUTION) fprintf(m_exec_output, "\n---------- break ----------\n\n");
2752	3245
2753	3246	break;
2754	3247	}
r31833	r31834
2762	3255	case 0x27:  /* NOR */       if (RDREG) RDVAL = ~(RSVAL | RTVAL); break;
2763	3256	case 0x2a:  /* SLT */       if (RDREG) RDVAL = (INT32)RSVAL < (INT32)RTVAL; break;
2764	3257	case 0x2b:  /* SLTU */      if (RDREG) RDVAL = (UINT32)RSVAL < (UINT32)RTVAL; break;
2765		default:    unimplemented_opcode(rsp, op); break;
	3258	default:    unimplemented_opcode(op); break;
2766	3259	}
2767	3260	break;
2768	3261	}
r31833	r31834
2775	3268	case 0x01:  /* BGEZ */      if ((INT32)(RSVAL) >= 0) JUMP_REL(SIMM16); break;
2776	3269	case 0x10:  /* BLTZAL */    if ((INT32)(RSVAL) < 0) JUMP_REL_L(SIMM16, 31); break;
2777	3270	case 0x11:  /* BGEZAL */    if ((INT32)(RSVAL) >= 0) JUMP_REL_L(SIMM16, 31); break;
2778		default:    unimplemented_opcode(rsp, op); break;
	3271	default:    unimplemented_opcode(op); break;
2779	3272	}
2780	3273	break;
2781	3274	}
r31833	r31834
2799	3292	{
2800	3293	switch ((op >> 21) & 0x1f)
2801	3294	{
2802		case 0x00:  /* MFC0 */      if (RTREG) RTVAL = get_cop0_reg(rsp, RDREG); break;
2803		case 0x04:  /* MTC0 */      set_cop0_reg(rsp, RDREG, RTVAL); break;
2804		default:    unimplemented_opcode(rsp, op); break;
	3295	case 0x00:  /* MFC0 */      if (RTREG) RTVAL = get_cop0_reg(RDREG); break;
	3296	case 0x04:  /* MTC0 */      set_cop0_reg(RDREG, RTVAL); break;
	3297	default:    unimplemented_opcode(op); break;
2805	3298	}
2806	3299	break;
2807	3300	}
r31833	r31834
2978	3471	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
2979	3472	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
2980	3473	{
2981		handle_vector_ops(rsp, op);
	3474	handle_vector_ops(op);
2982	3475	break;
2983	3476	}
2984	3477
2985		default:    unimplemented_opcode(rsp, op); break;
	3478	default:    unimplemented_opcode(op); break;
2986	3479	}
2987	3480	break;
2988	3481	}
2989	3482
2990		case 0x20:  /* LB */        if (RTREG) RTVAL = (INT32)(INT8)READ8(rsp, RSVAL + SIMM16); break;
2991		case 0x21:  /* LH */        if (RTREG) RTVAL = (INT32)(INT16)READ16(rsp, RSVAL + SIMM16); break;
2992		case 0x23:  /* LW */        if (RTREG) RTVAL = READ32(rsp, RSVAL + SIMM16); break;
2993		case 0x24:  /* LBU */       if (RTREG) RTVAL = (UINT8)READ8(rsp, RSVAL + SIMM16); break;
2994		case 0x25:  /* LHU */       if (RTREG) RTVAL = (UINT16)READ16(rsp, RSVAL + SIMM16); break;
2995		case 0x28:  /* SB */        WRITE8(rsp, RSVAL + SIMM16, RTVAL); break;
2996		case 0x29:  /* SH */        WRITE16(rsp, RSVAL + SIMM16, RTVAL); break;
2997		case 0x2b:  /* SW */        WRITE32(rsp, RSVAL + SIMM16, RTVAL); break;
2998		case 0x32:  /* LWC2 */      handle_lwc2(rsp, op); break;
2999		case 0x3a:  /* SWC2 */      handle_swc2(rsp, op); break;
	3483	case 0x20:  /* LB */        if (RTREG) RTVAL = (INT32)(INT8)READ8(RSVAL + SIMM16); break;
	3484	case 0x21:  /* LH */        if (RTREG) RTVAL = (INT32)(INT16)READ16(RSVAL + SIMM16); break;
	3485	case 0x23:  /* LW */        if (RTREG) RTVAL = READ32(RSVAL + SIMM16); break;
	3486	case 0x24:  /* LBU */       if (RTREG) RTVAL = (UINT8)READ8(RSVAL + SIMM16); break;
	3487	case 0x25:  /* LHU */       if (RTREG) RTVAL = (UINT16)READ16(RSVAL + SIMM16); break;
	3488	case 0x28:  /* SB */        WRITE8(RSVAL + SIMM16, RTVAL); break;
	3489	case 0x29:  /* SH */        WRITE16(RSVAL + SIMM16, RTVAL); break;
	3490	case 0x2b:  /* SW */        WRITE32(RSVAL + SIMM16, RTVAL); break;
	3491	case 0x32:  /* LWC2 */      handle_lwc2(op); break;
	3492	case 0x3a:  /* SWC2 */      handle_swc2(op); break;
3000	3493
3001	3494	default:
3002	3495	{
3003		unimplemented_opcode(rsp, op);
	3496	unimplemented_opcode(op);
3004	3497	break;
3005	3498	}
3006	3499	}
r31833	r31834
3011	3504	static UINT32 prev_regs[32];
3012	3505	static VECTOR_REG prev_vecs[32];
3013	3506	char string[200];
3014		rsp_dasm_one(string, rsp->ppc, op);
	3507	rsp_dasm_one(string, m_ppc, op);
3015	3508
3016		fprintf(rsp->exec_output, "%08X: %s", rsp->ppc, string);
	3509	fprintf(m_exec_output, "%08X: %s", m_ppc, string);
3017	3510
3018	3511	l = strlen(string);
3019	3512	if (l < 36)
3020	3513	{
3021	3514	for (i=l; i < 36; i++)
3022	3515	{
3023		fprintf(rsp->exec_output, " ");
	3516	fprintf(m_exec_output, " ");
3024	3517	}
3025	3518	}
3026	3519
3027		fprintf(rsp->exec_output, "| ");
	3520	fprintf(m_exec_output, "| ");
3028	3521
3029	3522	for (i=0; i < 32; i++)
3030	3523	{
3031		if (rsp->r[i] != prev_regs[i])
	3524	if (m_rsp_state->r[i] != prev_regs[i])
3032	3525	{
3033		fprintf(rsp->exec_output, "R%d: %08X ", i, rsp->r[i]);
	3526	fprintf(m_exec_output, "R%d: %08X ", i, m_rsp_state->r[i]);
3034	3527	}
3035		prev_regs[i] = rsp->r[i];
	3528	prev_regs[i] = m_rsp_state->r[i];
3036	3529	}
3037	3530
3038	3531	for (i=0; i < 32; i++)
3039	3532	{
3040		if (rsp->v[i].d[0] != prev_vecs[i].d[0] || rsp->v[i].d[1] != prev_vecs[i].d[1])
	3533	if (m_v[i].d[0] != prev_vecs[i].d[0] || m_v[i].d[1] != prev_vecs[i].d[1])
3041	3534	{
3042		fprintf(rsp->exec_output, "V%d: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X ", i,
	3535	fprintf(m_exec_output, "V%d: %04X|%04X|%04X|%04X|%04X|%04X|%04X|%04X ", i,
3043	3536	(UINT16)VREG_S(i,0), (UINT16)VREG_S(i,1), (UINT16)VREG_S(i,2), (UINT16)VREG_S(i,3), (UINT16)VREG_S(i,4), (UINT16)VREG_S(i,5), (UINT16)VREG_S(i,6), (UINT16)VREG_S(i,7));
3044	3537	}
3045		prev_vecs[i].d[0] = rsp->v[i].d[0];
3046		prev_vecs[i].d[1] = rsp->v[i].d[1];
	3538	prev_vecs[i].d[0] = m_v[i].d[0];
	3539	prev_vecs[i].d[1] = m_v[i].d[1];
3047	3540	}
3048	3541
3049		fprintf(rsp->exec_output, "\n");
	3542	fprintf(m_exec_output, "\n");
3050	3543
3051	3544	}
3052	3545
3053		--rsp->icount;
	3546	--m_rsp_state->icount;
3054	3547
3055		if( rsp->sr & RSP_STATUS_SSTEP )
	3548	if( m_sr & RSP_STATUS_SSTEP )
3056	3549	{
3057		if( rsp->step_count )
	3550	if( m_step_count )
3058	3551	{
3059		rsp->step_count--;
	3552	m_step_count--;
3060	3553	}
3061	3554	else
3062	3555	{
3063		rsp->sr |= RSP_STATUS_BROKE;
	3556	m_sr |= RSP_STATUS_BROKE;
3064	3557	}
3065	3558	}
3066	3559
3067		if( rsp->sr & ( RSP_STATUS_HALT | RSP_STATUS_BROKE ) )
	3560	if( m_sr & ( RSP_STATUS_HALT | RSP_STATUS_BROKE ) )
3068	3561	{
3069		rsp->icount = MIN(rsp->icount, 0);
	3562	m_rsp_state->icount = MIN(m_rsp_state->icount, 0);
3070	3563	}
3071	3564
3072	3565	}
3073	3566	}
3074	3567
3075	3568
3076
3077
3078		/*****************************************************************************/
3079
3080		static CPU_SET_INFO( rsp )
3081		{
3082		rsp_state *rsp = get_safe_token(device);
3083
3084		switch (state)
3085		{
3086		/* --- the following bits of info are set as 64-bit signed integers --- */
3087		case CPUINFO_INT_PC:
3088		case CPUINFO_INT_REGISTER + RSP_PC:             rsp->pc = info->i;        break;
3089		case CPUINFO_INT_REGISTER + RSP_R0:             rsp->r[0] = info->i;        break;
3090		case CPUINFO_INT_REGISTER + RSP_R1:             rsp->r[1] = info->i;        break;
3091		case CPUINFO_INT_REGISTER + RSP_R2:             rsp->r[2] = info->i;        break;
3092		case CPUINFO_INT_REGISTER + RSP_R3:             rsp->r[3] = info->i;        break;
3093		case CPUINFO_INT_REGISTER + RSP_R4:             rsp->r[4] = info->i;        break;
3094		case CPUINFO_INT_REGISTER + RSP_R5:             rsp->r[5] = info->i;        break;
3095		case CPUINFO_INT_REGISTER + RSP_R6:             rsp->r[6] = info->i;        break;
3096		case CPUINFO_INT_REGISTER + RSP_R7:             rsp->r[7] = info->i;        break;
3097		case CPUINFO_INT_REGISTER + RSP_R8:             rsp->r[8] = info->i;        break;
3098		case CPUINFO_INT_REGISTER + RSP_R9:             rsp->r[9] = info->i;        break;
3099		case CPUINFO_INT_REGISTER + RSP_R10:            rsp->r[10] = info->i;        break;
3100		case CPUINFO_INT_REGISTER + RSP_R11:            rsp->r[11] = info->i;        break;
3101		case CPUINFO_INT_REGISTER + RSP_R12:            rsp->r[12] = info->i;        break;
3102		case CPUINFO_INT_REGISTER + RSP_R13:            rsp->r[13] = info->i;        break;
3103		case CPUINFO_INT_REGISTER + RSP_R14:            rsp->r[14] = info->i;        break;
3104		case CPUINFO_INT_REGISTER + RSP_R15:            rsp->r[15] = info->i;        break;
3105		case CPUINFO_INT_REGISTER + RSP_R16:            rsp->r[16] = info->i;        break;
3106		case CPUINFO_INT_REGISTER + RSP_R17:            rsp->r[17] = info->i;        break;
3107		case CPUINFO_INT_REGISTER + RSP_R18:            rsp->r[18] = info->i;        break;
3108		case CPUINFO_INT_REGISTER + RSP_R19:            rsp->r[19] = info->i;        break;
3109		case CPUINFO_INT_REGISTER + RSP_R20:            rsp->r[20] = info->i;        break;
3110		case CPUINFO_INT_REGISTER + RSP_R21:            rsp->r[21] = info->i;        break;
3111		case CPUINFO_INT_REGISTER + RSP_R22:            rsp->r[22] = info->i;        break;
3112		case CPUINFO_INT_REGISTER + RSP_R23:            rsp->r[23] = info->i;        break;
3113		case CPUINFO_INT_REGISTER + RSP_R24:            rsp->r[24] = info->i;        break;
3114		case CPUINFO_INT_REGISTER + RSP_R25:            rsp->r[25] = info->i;        break;
3115		case CPUINFO_INT_REGISTER + RSP_R26:            rsp->r[26] = info->i;        break;
3116		case CPUINFO_INT_REGISTER + RSP_R27:            rsp->r[27] = info->i;        break;
3117		case CPUINFO_INT_REGISTER + RSP_R28:            rsp->r[28] = info->i;        break;
3118		case CPUINFO_INT_REGISTER + RSP_R29:            rsp->r[29] = info->i;        break;
3119		case CPUINFO_INT_REGISTER + RSP_R30:            rsp->r[30] = info->i;        break;
3120		case CPUINFO_INT_SP:
3121		case CPUINFO_INT_REGISTER + RSP_R31:            rsp->r[31] = info->i;        break;
3122		case CPUINFO_INT_REGISTER + RSP_SR:             rsp->sr = info->i;           break;
3123		case CPUINFO_INT_REGISTER + RSP_NEXTPC:         rsp->nextpc = info->i;       break;
3124		case CPUINFO_INT_REGISTER + RSP_STEPCNT:        rsp->step_count = info->i;   break;
3125		}
3126		}
3127
3128		CPU_GET_INFO( rsp_int )
3129		{
3130		rsp_state *rsp = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
3131
3132		switch(state)
3133		{
3134		/* --- the following bits of info are returned as 64-bit signed integers --- */
3135		case CPUINFO_INT_CONTEXT_SIZE:                  info->i = sizeof(rsp_state);            break;
3136		case CPUINFO_INT_INPUT_LINES:                   info->i = 1;                            break;
3137		case CPUINFO_INT_DEFAULT_IRQ_VECTOR:            info->i = 0;                            break;
3138		case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_BIG;               break;
3139		case CPUINFO_INT_CLOCK_MULTIPLIER:              info->i = 1;                            break;
3140		case CPUINFO_INT_CLOCK_DIVIDER:                 info->i = 1;                            break;
3141		case CPUINFO_INT_MIN_INSTRUCTION_BYTES:         info->i = 4;                            break;
3142		case CPUINFO_INT_MAX_INSTRUCTION_BYTES:         info->i = 4;                            break;
3143		case CPUINFO_INT_MIN_CYCLES:                    info->i = 1;                            break;
3144		case CPUINFO_INT_MAX_CYCLES:                    info->i = 1;                            break;
3145
3146		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:    info->i = 32;                   break;
3147		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32;                  break;
3148		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0;                   break;
3149		case CPUINFO_INT_DATABUS_WIDTH + AS_DATA:   info->i = 0;                    break;
3150		case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA:   info->i = 0;                    break;
3151		case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA:   info->i = 0;                    break;
3152		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:     info->i = 0;                    break;
3153		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO:     info->i = 0;                    break;
3154		case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO:     info->i = 0;                    break;
3155
3156		case CPUINFO_INT_INPUT_STATE:                   info->i = CLEAR_LINE;                   break;
3157
3158		case CPUINFO_INT_PREVIOUSPC:                    info->i = rsp->ppc;                     break;
3159
3160		case CPUINFO_INT_PC:    /* intentional fallthrough */
3161		case CPUINFO_INT_REGISTER + RSP_PC:             info->i = rsp->pc;                      break;
3162
3163		case CPUINFO_INT_REGISTER + RSP_R0:             info->i = rsp->r[0];                        break;
3164		case CPUINFO_INT_REGISTER + RSP_R1:             info->i = rsp->r[1];                        break;
3165		case CPUINFO_INT_REGISTER + RSP_R2:             info->i = rsp->r[2];                        break;
3166		case CPUINFO_INT_REGISTER + RSP_R3:             info->i = rsp->r[3];                        break;
3167		case CPUINFO_INT_REGISTER + RSP_R4:             info->i = rsp->r[4];                        break;
3168		case CPUINFO_INT_REGISTER + RSP_R5:             info->i = rsp->r[5];                        break;
3169		case CPUINFO_INT_REGISTER + RSP_R6:             info->i = rsp->r[6];                        break;
3170		case CPUINFO_INT_REGISTER + RSP_R7:             info->i = rsp->r[7];                        break;
3171		case CPUINFO_INT_REGISTER + RSP_R8:             info->i = rsp->r[8];                        break;
3172		case CPUINFO_INT_REGISTER + RSP_R9:             info->i = rsp->r[9];                        break;
3173		case CPUINFO_INT_REGISTER + RSP_R10:            info->i = rsp->r[10];                   break;
3174		case CPUINFO_INT_REGISTER + RSP_R11:            info->i = rsp->r[11];                   break;
3175		case CPUINFO_INT_REGISTER + RSP_R12:            info->i = rsp->r[12];                   break;
3176		case CPUINFO_INT_REGISTER + RSP_R13:            info->i = rsp->r[13];                   break;
3177		case CPUINFO_INT_REGISTER + RSP_R14:            info->i = rsp->r[14];                   break;
3178		case CPUINFO_INT_REGISTER + RSP_R15:            info->i = rsp->r[15];                   break;
3179		case CPUINFO_INT_REGISTER + RSP_R16:            info->i = rsp->r[16];                   break;
3180		case CPUINFO_INT_REGISTER + RSP_R17:            info->i = rsp->r[17];                   break;
3181		case CPUINFO_INT_REGISTER + RSP_R18:            info->i = rsp->r[18];                   break;
3182		case CPUINFO_INT_REGISTER + RSP_R19:            info->i = rsp->r[19];                   break;
3183		case CPUINFO_INT_REGISTER + RSP_R20:            info->i = rsp->r[20];                   break;
3184		case CPUINFO_INT_REGISTER + RSP_R21:            info->i = rsp->r[21];                   break;
3185		case CPUINFO_INT_REGISTER + RSP_R22:            info->i = rsp->r[22];                   break;
3186		case CPUINFO_INT_REGISTER + RSP_R23:            info->i = rsp->r[23];                   break;
3187		case CPUINFO_INT_REGISTER + RSP_R24:            info->i = rsp->r[24];                   break;
3188		case CPUINFO_INT_REGISTER + RSP_R25:            info->i = rsp->r[25];                   break;
3189		case CPUINFO_INT_REGISTER + RSP_R26:            info->i = rsp->r[26];                   break;
3190		case CPUINFO_INT_REGISTER + RSP_R27:            info->i = rsp->r[27];                   break;
3191		case CPUINFO_INT_REGISTER + RSP_R28:            info->i = rsp->r[28];                   break;
3192		case CPUINFO_INT_REGISTER + RSP_R29:            info->i = rsp->r[29];                   break;
3193		case CPUINFO_INT_REGISTER + RSP_R30:            info->i = rsp->r[30];                   break;
3194		case CPUINFO_INT_SP:
3195		case CPUINFO_INT_REGISTER + RSP_R31:            info->i = rsp->r[31];                   break;
3196		case CPUINFO_INT_REGISTER + RSP_SR:             info->i = rsp->sr;                       break;
3197		case CPUINFO_INT_REGISTER + RSP_NEXTPC:         info->i = rsp->nextpc;                   break;
3198		case CPUINFO_INT_REGISTER + RSP_STEPCNT:        info->i = rsp->step_count;               break;
3199
3200		/* --- the following bits of info are returned as pointers to data or functions --- */
3201		case CPUINFO_FCT_SET_INFO:                      info->setinfo = CPU_SET_INFO_NAME(rsp);         break;
3202		case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(rsp);                    break;
3203		case CPUINFO_FCT_RESET:                         info->reset = CPU_RESET_NAME(rsp);              break;
3204		case CPUINFO_FCT_EXIT:                          info->exit = CPU_EXIT_NAME(rsp);                    break;
3205		case CPUINFO_FCT_EXECUTE:                       info->execute = CPU_EXECUTE_NAME(rsp);          break;
3206		case CPUINFO_FCT_BURN:                          info->burn = NULL;                      break;
3207		case CPUINFO_FCT_DISASSEMBLE:                   info->disassemble = CPU_DISASSEMBLE_NAME(rsp);          break;
3208		case CPUINFO_PTR_INSTRUCTION_COUNTER:           info->icount = &rsp->icount;                break;
3209
3210		/* --- the following bits of info are returned as NULL-terminated strings --- */
3211		case CPUINFO_STR_NAME:                          strcpy(info->s, "RSP");                 break;
3212		case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "rsp");                 break;
3213		case CPUINFO_STR_FAMILY:                    strcpy(info->s, "RSP");                 break;
3214		case CPUINFO_STR_VERSION:                   strcpy(info->s, "1.0");                 break;
3215		case CPUINFO_STR_SOURCE_FILE:                       strcpy(info->s, __FILE__);              break;
3216		case CPUINFO_STR_CREDITS:                   strcpy(info->s, "Copyright Nicola Salmoria and the MAME Team"); break;
3217
3218		case CPUINFO_STR_FLAGS:                         strcpy(info->s, " ");                   break;
3219
3220		case CPUINFO_STR_REGISTER + RSP_PC:             sprintf(info->s, "PC: %08X", rsp->pc);  break;
3221
3222		case CPUINFO_STR_REGISTER + RSP_R0:             sprintf(info->s, "R0: %08X", rsp->r[0]); break;
3223		case CPUINFO_STR_REGISTER + RSP_R1:             sprintf(info->s, "R1: %08X", rsp->r[1]); break;
3224		case CPUINFO_STR_REGISTER + RSP_R2:             sprintf(info->s, "R2: %08X", rsp->r[2]); break;
3225		case CPUINFO_STR_REGISTER + RSP_R3:             sprintf(info->s, "R3: %08X", rsp->r[3]); break;
3226		case CPUINFO_STR_REGISTER + RSP_R4:             sprintf(info->s, "R4: %08X", rsp->r[4]); break;
3227		case CPUINFO_STR_REGISTER + RSP_R5:             sprintf(info->s, "R5: %08X", rsp->r[5]); break;
3228		case CPUINFO_STR_REGISTER + RSP_R6:             sprintf(info->s, "R6: %08X", rsp->r[6]); break;
3229		case CPUINFO_STR_REGISTER + RSP_R7:             sprintf(info->s, "R7: %08X", rsp->r[7]); break;
3230		case CPUINFO_STR_REGISTER + RSP_R8:             sprintf(info->s, "R8: %08X", rsp->r[8]); break;
3231		case CPUINFO_STR_REGISTER + RSP_R9:             sprintf(info->s, "R9: %08X", rsp->r[9]); break;
3232		case CPUINFO_STR_REGISTER + RSP_R10:            sprintf(info->s, "R10: %08X", rsp->r[10]); break;
3233		case CPUINFO_STR_REGISTER + RSP_R11:            sprintf(info->s, "R11: %08X", rsp->r[11]); break;
3234		case CPUINFO_STR_REGISTER + RSP_R12:            sprintf(info->s, "R12: %08X", rsp->r[12]); break;
3235		case CPUINFO_STR_REGISTER + RSP_R13:            sprintf(info->s, "R13: %08X", rsp->r[13]); break;
3236		case CPUINFO_STR_REGISTER + RSP_R14:            sprintf(info->s, "R14: %08X", rsp->r[14]); break;
3237		case CPUINFO_STR_REGISTER + RSP_R15:            sprintf(info->s, "R15: %08X", rsp->r[15]); break;
3238		case CPUINFO_STR_REGISTER + RSP_R16:            sprintf(info->s, "R16: %08X", rsp->r[16]); break;
3239		case CPUINFO_STR_REGISTER + RSP_R17:            sprintf(info->s, "R17: %08X", rsp->r[17]); break;
3240		case CPUINFO_STR_REGISTER + RSP_R18:            sprintf(info->s, "R18: %08X", rsp->r[18]); break;
3241		case CPUINFO_STR_REGISTER + RSP_R19:            sprintf(info->s, "R19: %08X", rsp->r[19]); break;
3242		case CPUINFO_STR_REGISTER + RSP_R20:            sprintf(info->s, "R20: %08X", rsp->r[20]); break;
3243		case CPUINFO_STR_REGISTER + RSP_R21:            sprintf(info->s, "R21: %08X", rsp->r[21]); break;
3244		case CPUINFO_STR_REGISTER + RSP_R22:            sprintf(info->s, "R22: %08X", rsp->r[22]); break;
3245		case CPUINFO_STR_REGISTER + RSP_R23:            sprintf(info->s, "R23: %08X", rsp->r[23]); break;
3246		case CPUINFO_STR_REGISTER + RSP_R24:            sprintf(info->s, "R24: %08X", rsp->r[24]); break;
3247		case CPUINFO_STR_REGISTER + RSP_R25:            sprintf(info->s, "R25: %08X", rsp->r[25]); break;
3248		case CPUINFO_STR_REGISTER + RSP_R26:            sprintf(info->s, "R26: %08X", rsp->r[26]); break;
3249		case CPUINFO_STR_REGISTER + RSP_R27:            sprintf(info->s, "R27: %08X", rsp->r[27]); break;
3250		case CPUINFO_STR_REGISTER + RSP_R28:            sprintf(info->s, "R28: %08X", rsp->r[28]); break;
3251		case CPUINFO_STR_REGISTER + RSP_R29:            sprintf(info->s, "R29: %08X", rsp->r[29]); break;
3252		case CPUINFO_STR_REGISTER + RSP_R30:            sprintf(info->s, "R30: %08X", rsp->r[30]); break;
3253		case CPUINFO_STR_REGISTER + RSP_R31:            sprintf(info->s, "R31: %08X", rsp->r[31]); break;
3254		case CPUINFO_STR_REGISTER + RSP_SR:             sprintf(info->s, "SR: %08X",  rsp->sr);    break;
3255		case CPUINFO_STR_REGISTER + RSP_NEXTPC:         sprintf(info->s, "NPC: %08X", rsp->nextpc);break;
3256		case CPUINFO_STR_REGISTER + RSP_STEPCNT:        sprintf(info->s, "STEP: %d",  rsp->step_count);  break;
3257		}
3258		}
3259
3260		rsp_cpu_device::rsp_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock, cpu_get_info_func get_info)
3261		: legacy_cpu_device(mconfig, type, tag, owner, clock, get_info),
3262		dp_reg_r_func(*this),
3263		dp_reg_w_func(*this),
3264		sp_reg_r_func(*this),
3265		sp_reg_w_func(*this),
3266		sp_set_status_func(*this)
3267		{
3268		}
3269
3270		rsp_int_device::rsp_int_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock)
3271		: rsp_cpu_device(mconfig, type, tag, owner, clock, CPU_GET_INFO_NAME(rsp_int))
3272		{
3273		}
3274
3275		const device_type RSP_INT = &legacy_device_creator<rsp_drc_device>;
3276
3277		const device_type RSP = &legacy_device_creator_drc<rsp_int_device, rsp_drc_device>;

trunk/src/emu/cpu/rsp/rspfe.h

r31833	r31834
36	36	{
37	37	public:
38	38	// construction/destruction
39		rsp_frontend(rsp_state &state, UINT32 window_start, UINT32 window_end, UINT32 max_sequence);
	39	rsp_frontend(rsp_device &rsp, UINT32 window_start, UINT32 window_end, UINT32 max_sequence);
40	40
41	41	protected:
42	42	// required overrides
r31833	r31834
50	50	bool describe_cop2(UINT32 op, opcode_desc &desc);
51	51
52	52	// internal state
53		rsp_state &m_context;
	53	rsp_device &m_rsp;
54	54	};
55	55
56	56

trunk/src/emu/cpu/rsp/rsp.h

r31833	r31834
16	16	#ifndef __RSP_H__
17	17	#define __RSP_H__
18	18
	19
	20	#include "cpu/drcfe.h"
	21	#include "cpu/drcuml.h"
	22
19	23	#define USE_SIMD        (0)
20	24	#define SIMUL_SIMD      (0)
	25	#define RSP_LOG_UML     (0)
	26	#define RSP_LOG_NATIVE  (0)
21	27
22	28	#if USE_SIMD
23	29	#include <tmmintrin.h>
r31833	r31834
72	78	};
73	79
74	80	/***************************************************************************
75		PUBLIC FUNCTIONS
76		***************************************************************************/
77
78		void rspdrc_flush_drc_cache(device_t *device);
79		void rspdrc_set_options(device_t *device, UINT32 options);
80		void rspdrc_add_dmem(device_t *device, UINT32 *base);
81		void rspdrc_add_imem(device_t *device, UINT32 *base);
82
83		/***************************************************************************
84	81	HELPER MACROS
85	82	***************************************************************************/
86	83
r31833	r31834
92	89	#define RDREG           ((op >> 11) & 31)
93	90	#define SHIFT           ((op >> 6) & 31)
94	91
95		#define RSVAL           (rsp->r[RSREG])
96		#define RTVAL           (rsp->r[RTREG])
97		#define RDVAL           (rsp->r[RDREG])
	92	#define RSVAL           (m_rsp_state->r[RSREG])
	93	#define RTVAL           (m_rsp_state->r[RTREG])
	94	#define RDVAL           (m_rsp_state->r[RDREG])
98	95
99	96	#define FRREG           ((op >> 21) & 31)
100	97	#define FTREG           ((op >> 16) & 31)
r31833	r31834
144	141	};
145	142
146	143	#define MCFG_RSP_DP_REG_R_CB(_devcb) \
147		devcb = &rsp_cpu_device::static_set_dp_reg_r_callback(*device, DEVCB_##_devcb);
	144	devcb = &rsp_device::static_set_dp_reg_r_callback(*device, DEVCB_##_devcb);
148	145
149	146	#define MCFG_RSP_DP_REG_W_CB(_devcb) \
150		devcb = &rsp_cpu_device::static_set_dp_reg_w_callback(*device, DEVCB_##_devcb);
	147	devcb = &rsp_device::static_set_dp_reg_w_callback(*device, DEVCB_##_devcb);
151	148
152	149	#define MCFG_RSP_SP_REG_R_CB(_devcb) \
153		devcb = &rsp_cpu_device::static_set_sp_reg_r_callback(*device, DEVCB_##_devcb);
	150	devcb = &rsp_device::static_set_sp_reg_r_callback(*device, DEVCB_##_devcb);
154	151
155	152	#define MCFG_RSP_SP_REG_W_CB(_devcb) \
156		devcb = &rsp_cpu_device::static_set_sp_reg_w_callback(*device, DEVCB_##_devcb);
	153	devcb = &rsp_device::static_set_sp_reg_w_callback(*device, DEVCB_##_devcb);
157	154
158	155	#define MCFG_RSP_SP_SET_STATUS_CB(_devcb) \
159		devcb = &rsp_cpu_device::static_set_status_callback(*device, DEVCB_##_devcb);
	156	devcb = &rsp_device::static_set_status_callback(*device, DEVCB_##_devcb);
160	157
161		class rsp_cpu_device : public legacy_cpu_device
	158
	159	class rsp_frontend;
	160
	161	class rsp_device : public cpu_device
162	162	{
163		protected:
	163	friend class rsp_frontend;
	164
	165	public:
164	166	// construction/destruction
165		rsp_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock, cpu_get_info_func info);
	167	rsp_device(const machine_config &mconfig, const char *_tag, device_t *_owner, UINT32 _clock);
166	168
167		public:
168	169	void resolve_cb();
169		template<class _Object> static devcb_base &static_set_dp_reg_r_callback(device_t &device, _Object object) { return downcast<rsp_cpu_device &>(device).dp_reg_r_func.set_callback(object); }
170		template<class _Object> static devcb_base &static_set_dp_reg_w_callback(device_t &device, _Object object) { return downcast<rsp_cpu_device &>(device).dp_reg_w_func.set_callback(object); }
171		template<class _Object> static devcb_base &static_set_sp_reg_r_callback(device_t &device, _Object object) { return downcast<rsp_cpu_device &>(device).sp_reg_r_func.set_callback(object); }
172		template<class _Object> static devcb_base &static_set_sp_reg_w_callback(device_t &device, _Object object) { return downcast<rsp_cpu_device &>(device).sp_reg_w_func.set_callback(object); }
173		template<class _Object> static devcb_base &static_set_status_callback(device_t &device, _Object object) { return downcast<rsp_cpu_device &>(device).sp_set_status_func.set_callback(object); }
	170	template<class _Object> static devcb_base &static_set_dp_reg_r_callback(device_t &device, _Object object) { return downcast<rsp_device &>(device).m_dp_reg_r_func.set_callback(object); }
	171	template<class _Object> static devcb_base &static_set_dp_reg_w_callback(device_t &device, _Object object) { return downcast<rsp_device &>(device).m_dp_reg_w_func.set_callback(object); }
	172	template<class _Object> static devcb_base &static_set_sp_reg_r_callback(device_t &device, _Object object) { return downcast<rsp_device &>(device).m_sp_reg_r_func.set_callback(object); }
	173	template<class _Object> static devcb_base &static_set_sp_reg_w_callback(device_t &device, _Object object) { return downcast<rsp_device &>(device).m_sp_reg_w_func.set_callback(object); }
	174	template<class _Object> static devcb_base &static_set_status_callback(device_t &device, _Object object) { return downcast<rsp_device &>(device).m_sp_set_status_func.set_callback(object); }
174	175
	176	void rspdrc_flush_drc_cache();
	177	void rspdrc_set_options(UINT32 options);
	178	void rspdrc_add_dmem(UINT32 *base);
	179	void rspdrc_add_imem(UINT32 *base);
175	180
176		devcb_read32 dp_reg_r_func;
177		devcb_write32 dp_reg_w_func;
178		devcb_read32 sp_reg_r_func;
179		devcb_write32 sp_reg_w_func;
180		devcb_write32 sp_set_status_func;
181		};
	181	void ccfunc_read8();
	182	void ccfunc_read16();
	183	void ccfunc_read32();
	184	void ccfunc_write8();
	185	void ccfunc_write16();
	186	void ccfunc_write32();
	187	void ccfunc_get_cop0_reg();
	188	void ccfunc_set_cop0_reg();
	189	void ccfunc_unimplemented_opcode();
	190	void ccfunc_sp_set_status_cb();
	191	void ccfunc_unimplemented();
	192	#if USE_SIMD
	193	void ccfunc_rsp_lbv_simd();
	194	void ccfunc_rsp_lsv_simd();
	195	void ccfunc_rsp_llv_simd();
	196	void ccfunc_rsp_ldv_simd();
	197	void ccfunc_rsp_lqv_simd();
	198	void ccfunc_rsp_lrv_simd();
	199	void ccfunc_rsp_lpv_simd();
	200	void ccfunc_rsp_luv_simd();
	201	void ccfunc_rsp_lhv_simd();
	202	void ccfunc_rsp_lfv_simd();
	203	void ccfunc_rsp_lwv_simd();
	204	void ccfunc_rsp_ltv_simd();
	205	void ccfunc_rsp_sbv_simd();
	206	void ccfunc_rsp_ssv_simd();
	207	void ccfunc_rsp_slv_simd();
	208	void ccfunc_rsp_sdv_simd();
	209	void ccfunc_rsp_sqv_simd();
	210	void ccfunc_rsp_srv_simd();
	211	void ccfunc_rsp_spv_simd();
	212	void ccfunc_rsp_suv_simd();
	213	void ccfunc_rsp_shv_simd();
	214	void ccfunc_rsp_sfv_simd();
	215	void ccfunc_rsp_swv_simd();
	216	void ccfunc_rsp_stv_simd();
	217	void ccfunc_rsp_vmulf_simd();
	218	void ccfunc_rsp_vmulu_simd();
	219	void ccfunc_rsp_vmudl_simd();
	220	void ccfunc_rsp_vmudm_simd();
	221	void ccfunc_rsp_vmudn_simd();
	222	void ccfunc_rsp_vmudh_simd();
	223	void ccfunc_rsp_vmacf_simd();
	224	void ccfunc_rsp_vmacu_simd();
	225	void ccfunc_rsp_vmadl_simd();
	226	void ccfunc_rsp_vmadm_simd();
	227	void ccfunc_rsp_vmadn_simd();
	228	void ccfunc_rsp_vmadh_simd();
	229	void ccfunc_rsp_vadd_simd();
	230	void ccfunc_rsp_vsub_simd();
	231	void ccfunc_rsp_vabs_simd();
	232	void ccfunc_rsp_vaddc_simd();
	233	void ccfunc_rsp_vsubc_simd();
	234	void ccfunc_rsp_vsaw_simd();
	235	void ccfunc_rsp_vlt_simd();
	236	void ccfunc_rsp_veq_simd();
	237	void ccfunc_rsp_vne_simd();
	238	void ccfunc_rsp_vge_simd();
	239	void ccfunc_rsp_vcl_simd();
	240	void ccfunc_rsp_vch_simd();
	241	void ccfunc_rsp_vcr_simd();
	242	void ccfunc_rsp_vmrg_simd();
	243	void ccfunc_rsp_vand_simd();
	244	void ccfunc_rsp_vnand_simd();
	245	void ccfunc_rsp_vor_simd();
	246	void ccfunc_rsp_vnor_simd();
	247	void ccfunc_rsp_vxor_simd();
	248	void ccfunc_rsp_vnxor_simd();
	249	void ccfunc_rsp_vrcp_simd();
	250	void ccfunc_rsp_vrcpl_simd();
	251	void ccfunc_rsp_vrcph_simd();
	252	void ccfunc_rsp_vmov_simd();
	253	void ccfunc_rsp_vrsql_simd();
	254	void ccfunc_rsp_vrsqh_simd();
	255	void ccfunc_mfc2_simd();
	256	void ccfunc_cfc2_simd();
	257	void ccfunc_mtc2_simd();
	258	void ccfunc_ctc2_simd();
	259	#endif
	260	#if (!USE_SIMD || SIMUL_SIMD)
	261	void ccfunc_rsp_lbv_scalar();
	262	void ccfunc_rsp_lsv_scalar();
	263	void ccfunc_rsp_llv_scalar();
	264	void ccfunc_rsp_ldv_scalar();
	265	void ccfunc_rsp_lqv_scalar();
	266	void ccfunc_rsp_lrv_scalar();
	267	void ccfunc_rsp_lpv_scalar();
	268	void ccfunc_rsp_luv_scalar();
	269	void ccfunc_rsp_lhv_scalar();
	270	void ccfunc_rsp_lfv_scalar();
	271	void ccfunc_rsp_lwv_scalar();
	272	void ccfunc_rsp_ltv_scalar();
	273	void ccfunc_rsp_sbv_scalar();
	274	void ccfunc_rsp_ssv_scalar();
	275	void ccfunc_rsp_slv_scalar();
	276	void ccfunc_rsp_sdv_scalar();
	277	void ccfunc_rsp_sqv_scalar();
	278	void ccfunc_rsp_srv_scalar();
	279	void ccfunc_rsp_spv_scalar();
	280	void ccfunc_rsp_suv_scalar();
	281	void ccfunc_rsp_shv_scalar();
	282	void ccfunc_rsp_sfv_scalar();
	283	void ccfunc_rsp_swv_scalar();
	284	void ccfunc_rsp_stv_scalar();
	285	void ccfunc_rsp_vmulf_scalar();
	286	void ccfunc_rsp_vmulu_scalar();
	287	void ccfunc_rsp_vmudl_scalar();
	288	void ccfunc_rsp_vmudm_scalar();
	289	void ccfunc_rsp_vmudn_scalar();
	290	void ccfunc_rsp_vmudh_scalar();
	291	void ccfunc_rsp_vmacf_scalar();
	292	void ccfunc_rsp_vmacu_scalar();
	293	void ccfunc_rsp_vmadl_scalar();
	294	void ccfunc_rsp_vmadm_scalar();
	295	void ccfunc_rsp_vmadn_scalar();
	296	void ccfunc_rsp_vmadh_scalar();
	297	void ccfunc_rsp_vadd_scalar();
	298	void ccfunc_rsp_vsub_scalar();
	299	void ccfunc_rsp_vabs_scalar();
	300	void ccfunc_rsp_vaddc_scalar();
	301	void ccfunc_rsp_vsubc_scalar();
	302	void ccfunc_rsp_vsaw_scalar();
	303	void ccfunc_rsp_vlt_scalar();
	304	void ccfunc_rsp_veq_scalar();
	305	void ccfunc_rsp_vne_scalar();
	306	void ccfunc_rsp_vge_scalar();
	307	void ccfunc_rsp_vcl_scalar();
	308	void ccfunc_rsp_vch_scalar();
	309	void ccfunc_rsp_vcr_scalar();
	310	void ccfunc_rsp_vmrg_scalar();
	311	void ccfunc_rsp_vand_scalar();
	312	void ccfunc_rsp_vnand_scalar();
	313	void ccfunc_rsp_vor_scalar();
	314	void ccfunc_rsp_vnor_scalar();
	315	void ccfunc_rsp_vxor_scalar();
	316	void ccfunc_rsp_vnxor_scalar();
	317	void ccfunc_rsp_vrcp_scalar();
	318	void ccfunc_rsp_vrcpl_scalar();
	319	void ccfunc_rsp_vrcph_scalar();
	320	void ccfunc_rsp_vmov_scalar();
	321	void ccfunc_rsp_vrsql_scalar();
	322	void ccfunc_rsp_vrsqh_scalar();
	323	void ccfunc_mfc2_scalar();
	324	void ccfunc_cfc2_scalar();
	325	void ccfunc_mtc2_scalar();
	326	void ccfunc_ctc2_scalar();
	327	#endif
	328	#if USE_SIMD && SIMUL_SIMD
	329	void ccfunc_backup_regs();
	330	void ccfunc_restore_regs();
	331	void ccfunc_verify_regs();
	332	#endif
182	333
	334	protected:
	335	// device-level overrides
	336	virtual void device_start();
	337	virtual void device_reset();
	338	virtual void device_stop();
183	339
184		struct rspimp_state;
185		struct rsp_state
186		{
187		FILE *exec_output;
	340	// device_execute_interface overrides
	341	virtual UINT32 execute_min_cycles() const { return 1; }
	342	virtual UINT32 execute_max_cycles() const { return 1; }
	343	virtual UINT32 execute_input_lines() const { return 1; }
	344	virtual UINT32 execute_default_irq_vector() const { return 0; }
	345	virtual void execute_run();
	346	virtual void execute_set_input(int inputnum, int state) { }
188	347
189		UINT32 pc;
190		UINT32 r[35];
191		VECTOR_REG v[32];
192		UINT16 vflag[6][8];
	348	// device_memory_interface overrides
	349	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
193	350
	351	// device_state_interface overrides
	352	virtual void state_import(const device_state_entry &entry);
	353	virtual void state_export(const device_state_entry &entry);
	354	void state_string_export(const device_state_entry &entry, astring &string);
	355
	356	// device_disasm_interface overrides
	357	virtual UINT32 disasm_min_opcode_bytes() const { return 4; }
	358	virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
	359	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
	360
	361	private:
	362	address_space_config m_program_config;
	363
	364	/* fast RAM info */
	365	struct fast_ram_info
	366	{
	367	offs_t              start;                      /* start of the RAM block */
	368	offs_t              end;                        /* end of the RAM block */
	369	UINT8               readonly;                   /* TRUE if read-only */
	370	void *              base;                       /* base in memory where the RAM lives */
	371	};
	372
	373
	374	/* internal compiler state */
	375	struct compiler_state
	376	{
	377	UINT32              cycles;                   /* accumulated cycles */
	378	UINT8               checkints;                /* need to check interrupts before next instruction */
	379	UINT8               checksoftints;            /* need to check software interrupts before next instruction */
	380	uml::code_label     labelnum;                 /* index for local labels */
	381	};
	382
	383
	384	/* core state */
	385	drc_cache           m_cache;                      /* pointer to the DRC code cache */
	386	drcuml_state *      m_drcuml;                     /* DRC UML generator state */
	387	rsp_frontend *      m_drcfe;                      /* pointer to the DRC front-end state */
	388	UINT32              m_drcoptions;                 /* configurable DRC options */
	389
	390	/* internal stuff */
	391	UINT8               m_cache_dirty;                /* true if we need to flush the cache */
	392
	393	/* parameters for subroutines */
	394	UINT64              m_numcycles;                  /* return value from gettotalcycles */
	395	const char *        m_format;                     /* format string for print_debug */
	396	UINT32              m_arg2;                       /* print_debug argument 3 */
	397	UINT32              m_arg3;                       /* print_debug argument 4 */
	398	UINT32              m_vres[8];                    /* used for temporary vector results */
	399
	400	/* register mappings */
	401	uml::parameter   m_regmap[34];                 /* parameter to register mappings for all 32 integer registers */
	402
	403	/* subroutines */
	404	uml::code_handle *   m_entry;                      /* entry point */
	405	uml::code_handle *   m_nocode;                     /* nocode exception handler */
	406	uml::code_handle *   m_out_of_cycles;              /* out of cycles exception handler */
	407	uml::code_handle *   m_read8;                      /* read byte */
	408	uml::code_handle *   m_write8;                     /* write byte */
	409	uml::code_handle *   m_read16;                     /* read half */
	410	uml::code_handle *   m_write16;                    /* write half */
	411	uml::code_handle *   m_read32;                     /* read word */
	412	uml::code_handle *   m_write32;                    /* write word */
	413
	414	struct internal_rsp_state
	415	{
	416	UINT32 pc;
	417	UINT32 r[35];
	418	UINT32 arg0;
	419	UINT32 arg1;
	420	UINT32 jmpdest;
	421	int icount;
	422	};
	423
	424	internal_rsp_state *m_rsp_state;
	425
	426	FILE *m_exec_output;
	427
	428	VECTOR_REG m_v[32];
	429	UINT16 m_vflag[6][8];
	430
194	431	#if SIMUL_SIMD
195		UINT32 old_r[35];
196		UINT8 old_dmem[4096];
	432	UINT32 m_old_r[35];
	433	UINT8 m_old_dmem[4096];
197	434
198		UINT32 scalar_r[35];
199		UINT8 scalar_dmem[4096];
	435	UINT32 m_scalar_r[35];
	436	UINT8 m_scalar_dmem[4096];
200	437
201		INT32 old_reciprocal_res;
202		UINT32 old_reciprocal_high;
203		INT32 old_dp_allowed;
	438	INT32 m_old_reciprocal_res;
	439	UINT32 m_old_reciprocal_high;
	440	INT32 m_old_dp_allowed;
204	441
205		INT32 scalar_reciprocal_res;
206		UINT32 scalar_reciprocal_high;
207		INT32 scalar_dp_allowed;
	442	INT32 m_scalar_reciprocal_res;
	443	UINT32 m_scalar_reciprocal_high;
	444	INT32 m_scalar_dp_allowed;
208	445
209		INT32 simd_reciprocal_res;
210		UINT32 simd_reciprocal_high;
211		INT32 simd_dp_allowed;
	446	INT32 m_simd_reciprocal_res;
	447	UINT32 m_simd_reciprocal_high;
	448	INT32 m_simd_dp_allowed;
212	449	#endif
213	450
214	451	#if USE_SIMD
215	452	// Mirror of v[] for now, to be used in parallel as
216	453	// more vector ops are transitioned over
217		__m128i xv[32];
218		__m128i xvflag[6];
	454	__m128i m_xv[32];
	455	__m128i m_xvflag[6];
219	456	#endif
220		UINT32 sr;
221		UINT32 step_count;
	457	UINT32 m_sr;
	458	UINT32 m_step_count;
222	459
223		ACCUMULATOR_REG accum[8];
	460	ACCUMULATOR_REG m_accum[8];
224	461	#if USE_SIMD
225		__m128i accum_h;
226		__m128i accum_m;
227		__m128i accum_l;
228		__m128i accum_ll;
	462	__m128i m_accum_h;
	463	__m128i m_accum_m;
	464	__m128i m_accum_l;
	465	__m128i m_accum_ll;
229	466	#endif
230		INT32 reciprocal_res;
231		UINT32 reciprocal_high;
232		INT32 dp_allowed;
	467	INT32 m_reciprocal_res;
	468	UINT32 m_reciprocal_high;
	469	INT32 m_dp_allowed;
233	470
234		UINT32 ppc;
235		UINT32 nextpc;
	471	UINT32 m_ppc;
	472	UINT32 m_nextpc;
236	473
237		device_irq_acknowledge_delegate irq_callback;
238		rsp_cpu_device *device;
239		address_space *program;
240		direct_read_data *direct;
241		int icount;
	474	address_space *m_program;
	475	protected:
	476	direct_read_data *m_direct;
242	477
243		UINT32 *dmem32;
244		UINT16 *dmem16;
245		UINT8 *dmem8;
	478	private:
	479	UINT32 *m_dmem32;
	480	UINT16 *m_dmem16;
	481	UINT8 *m_dmem8;
246	482
247		UINT32 *imem32;
248		UINT16 *imem16;
249		UINT8 *imem8;
	483	UINT32 *m_imem32;
	484	UINT16 *m_imem16;
	485	UINT8 *m_imem8;
250	486
251		rspimp_state* impstate;
252		};
	487	UINT32 m_debugger_temp;
	488	bool m_isdrc;
253	489
254		CPU_GET_INFO( rsp_int );
	490	devcb_read32 m_dp_reg_r_func;
	491	devcb_write32 m_dp_reg_w_func;
	492	devcb_read32 m_sp_reg_r_func;
	493	devcb_write32 m_sp_reg_w_func;
	494	devcb_write32 m_sp_set_status_func;
255	495
256		class rsp_int_device : public rsp_cpu_device
257		{
258		public:
259		rsp_int_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock);
	496	UINT8 READ8(UINT32 address);
	497	UINT16 READ16(UINT32 address);
	498	UINT32 READ32(UINT32 address);
	499	void WRITE8(UINT32 address, UINT8 data);
	500	void WRITE16(UINT32 address, UINT16 data);
	501	void WRITE32(UINT32 address, UINT32 data);
	502	UINT32 get_cop0_reg(int reg);
	503	void set_cop0_reg(int reg, UINT32 data);
	504	void unimplemented_opcode(UINT32 op);
	505	void handle_lwc2(UINT32 op);
	506	void handle_swc2(UINT32 op);
	507	UINT16 SATURATE_ACCUM(int accum, int slice, UINT16 negative, UINT16 positive);
	508	UINT16 SATURATE_ACCUM1(int accum, UINT16 negative, UINT16 positive);
	509	void handle_vector_ops(UINT32 op);
	510	#if USE_SIMD
	511	UINT16 VEC_ACCUM_H(int x);
	512	UINT16 VEC_ACCUM_M(int x);
	513	UINT16 VEC_ACCUM_L(int x);
	514	UINT16 VEC_ACCUM_LL(int x);
	515	UINT16 VEC_CARRY_FLAG(const int x);
	516	UINT16 VEC_COMPARE_FLAG(const int x);
	517	UINT16 VEC_CLIP1_FLAG(const int x);
	518	UINT16 VEC_ZERO_FLAG(const int x);
	519	UINT16 VEC_CLIP2_FLAG(const int x);
	520	UINT16 VEC_SATURATE_ACCUM(int accum, int slice, UINT16 negative, UINT16 positive);
	521	#endif
	522	void load_fast_iregs(drcuml_block *block);
	523	void save_fast_iregs(drcuml_block *block);
	524	UINT8 DM_READ8(UINT32 address);
	525	UINT16 DM_READ16(UINT32 address);
	526	UINT32 DM_READ32(UINT32 address);
	527	void DM_WRITE8(UINT32 address, UINT8 data);
	528	void DM_WRITE16(UINT32 address, UINT16 data);
	529	void DM_WRITE32(UINT32 address, UINT32 data);
	530	void rspcom_init();
	531	int generate_lwc2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
	532	int generate_swc2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
	533	void execute_run_drc();
	534	void code_flush_cache();
	535	void code_compile_block(offs_t pc);
	536	void static_generate_entry_point();
	537	void static_generate_nocode_handler();
	538	void static_generate_out_of_cycles();
	539	void static_generate_memory_accessor(int size, int iswrite, const char *name, uml::code_handle *&handleptr);
	540	void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception);
	541	void generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast);
	542	void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
	543	void generate_delay_slot_and_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 linkreg);
	544	int generate_vector_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
	545	int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
	546	int generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
	547	int generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
	548	int generate_cop2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
	549	int generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
	550	void log_add_disasm_comment(drcuml_block *block, UINT32 pc, UINT32 op);
260	551	};
261	552
262		extern const device_type RSP_INT;
263	553
264		CPU_GET_INFO( rsp_drc );
265
266		class rsp_drc_device : public rsp_cpu_device
267		{
268		public:
269		rsp_drc_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock);
270		};
271
272		extern const device_type RSP_DRC;
273
274	554	extern const device_type RSP;
275	555
276		extern offs_t rsp_dasm_one(char *buffer, offs_t pc, UINT32 op);
277	556
278	557	#endif /* __RSP_H__ */

Previous

199869 Revisions

Next

---

© 1997-2024 The MAME Team