trunk/src/mame/drivers/segaybd.c
| r31807 | r31808 | |
|---|
| 667 | 667 | logerror("link2_w %04x\n", data); |
| 668 | 668 | } |
| 669 | 669 | |
| 670 | READ8_MEMBER(segaybd_state::linkram_r) |
| 671 | { |
| 672 | return m_linkram[offset]; |
| 673 | } |
| 674 | |
| 675 | WRITE8_MEMBER(segaybd_state::linkram_w) |
| 676 | { |
| 677 | m_linkram[offset] = data; |
| 678 | } |
| 679 | |
| 670 | 680 | //************************************************************************** |
| 671 | 681 | // MAIN CPU ADDRESS MAPS |
| 672 | 682 | //************************************************************************** |
| r31807 | r31808 | |
|---|
| 686 | 696 | ADDRESS_MAP_END |
| 687 | 697 | |
| 688 | 698 | static ADDRESS_MAP_START( main_map_link, AS_PROGRAM, 16, segaybd_state ) |
| 689 | | AM_RANGE(0x190000, 0x190fff) AM_RAM // ram to share with link CPU? |
| 699 | AM_RANGE(0x190000, 0x190fff) AM_READWRITE8(linkram_r, linkram_w, 0x00ff) // ram to share with link CPU? |
| 690 | 700 | AM_RANGE(0x191000, 0x191001) AM_READ(link_r) |
| 691 | 701 | AM_RANGE(0x192000, 0x192001) AM_READWRITE(link2_r, link2_w) |
| 692 | 702 | |
| r31807 | r31808 | |
|---|
| 752 | 762 | AM_RANGE(0x0000, 0x0fff) AM_ROM |
| 753 | 763 | AM_RANGE(0x2000, 0x2fff) AM_RAM |
| 754 | 764 | AM_RANGE(0x3000, 0x3fff) AM_RAM |
| 755 | | AM_RANGE(0x4000, 0x47ff) AM_RAM |
| 765 | AM_RANGE(0x4000, 0x47ff) AM_RAM AM_SHARE("linkram") |
| 756 | 766 | ADDRESS_MAP_END |
| 757 | 767 | |
| 758 | 768 | static ADDRESS_MAP_START( link_portmap, AS_IO, 8, segaybd_state ) |
| r31807 | r31808 | |
|---|
| 1128 | 1138 | PORT_DIPSETTING( 0xc0, DEF_STR( 5C_1C ) ) |
| 1129 | 1139 | PORT_DIPSETTING( 0xb0, DEF_STR( 6C_1C ) ) |
| 1130 | 1140 | PORT_DIPSETTING( 0x00, "Free Play (if Coin A too) or 1/1" ) |
| 1141 | |
| 1142 | PORT_START("LinkDSW") |
| 1143 | PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) |
| 1144 | PORT_DIPSETTING( 0x01, DEF_STR( Off ) ) |
| 1145 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 1146 | PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) |
| 1147 | PORT_DIPSETTING( 0x02, DEF_STR( Off ) ) |
| 1148 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 1149 | PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) |
| 1150 | PORT_DIPSETTING( 0x04, DEF_STR( Off ) ) |
| 1151 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 1152 | PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) |
| 1153 | PORT_DIPSETTING( 0x08, DEF_STR( Off ) ) |
| 1154 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 1155 | PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) |
| 1156 | PORT_DIPSETTING( 0x10, DEF_STR( Off ) ) |
| 1157 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 1158 | PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) |
| 1159 | PORT_DIPSETTING( 0x20, DEF_STR( Off ) ) |
| 1160 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 1161 | PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) |
| 1162 | PORT_DIPSETTING( 0x40, DEF_STR( Off ) ) |
| 1163 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 1164 | PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) |
| 1165 | PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) |
| 1166 | PORT_DIPSETTING( 0x00, DEF_STR( On ) ) |
| 1131 | 1167 | INPUT_PORTS_END |
| 1132 | 1168 | |
| 1133 | 1169 | |
| r31807 | r31808 | |
|---|
| 1301 | 1337 | MCFG_CPU_ADD("linkcpu", Z80, LINK_CLOCK/4 ) // ?? mhz |
| 1302 | 1338 | MCFG_CPU_PROGRAM_MAP(link_map) |
| 1303 | 1339 | MCFG_CPU_IO_MAP(link_portmap) |
| 1340 | // valid code at 0x28 and 0x38 |
| 1304 | 1341 | MACHINE_CONFIG_END |
| 1305 | 1342 | |
| 1306 | 1343 | //************************************************************************** |
trunk/src/mame/includes/segaybd.h
| r31807 | r31808 | |
|---|
| 33 | 33 | m_irq2_scanline(0), |
| 34 | 34 | m_timer_irq_state(0), |
| 35 | 35 | m_vblank_irq_state(0), |
| 36 | | m_tmp_bitmap(512, 512) |
| 36 | m_tmp_bitmap(512, 512), |
| 37 | m_linkram(*this, "linkram") |
| 37 | 38 | { |
| 38 | 39 | memset(m_analog_data, 0, sizeof(m_analog_data)); |
| 39 | 40 | memset(m_misc_io_data, 0, sizeof(m_misc_io_data)); |
| r31807 | r31808 | |
|---|
| 48 | 49 | DECLARE_READ16_MEMBER( io_chip_r ); |
| 49 | 50 | DECLARE_WRITE16_MEMBER( io_chip_w ); |
| 50 | 51 | DECLARE_WRITE16_MEMBER( sound_data_w ); |
| 51 | | DECLARE_READ16_MEMBER(link_r); |
| 52 | | DECLARE_READ16_MEMBER(link2_r); |
| 53 | | DECLARE_WRITE16_MEMBER(link2_w); |
| 54 | 52 | |
| 55 | 53 | // sound Z80 CPU read/write handlers |
| 56 | 54 | DECLARE_READ8_MEMBER( sound_data_r ); |
| r31807 | r31808 | |
|---|
| 116 | 114 | UINT8 m_vblank_irq_state; |
| 117 | 115 | UINT8 m_misc_io_data[0x10]; |
| 118 | 116 | bitmap_ind16 m_tmp_bitmap; |
| 117 | |
| 118 | public: |
| 119 | // linkpcb support |
| 120 | DECLARE_READ16_MEMBER(link_r); |
| 121 | DECLARE_READ16_MEMBER(link2_r); |
| 122 | DECLARE_WRITE16_MEMBER(link2_w); |
| 123 | |
| 124 | DECLARE_READ8_MEMBER(linkram_r); |
| 125 | DECLARE_WRITE8_MEMBER(linkram_w); |
| 126 | |
| 127 | optional_shared_ptr<UINT8> m_linkram; |
| 119 | 128 | }; |