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r31797 Wednesday 27th August, 2014 at 07:19:47 UTC by Ryan Holtz
(nw) mips3drc: Made badcop exception handling cleaner. If you haven't read Bob Martin's "Clean Code" yet, do so.
[src/emu/cpu/mips]mips3.h mips3drc.c

trunk/src/emu/cpu/mips/mips3.h
r31796r31797
544544   void static_generate_tlb_mismatch();
545545   void static_generate_exception(UINT8 exception, int recover, const char *name);
546546   void static_generate_memory_accessor(int mode, int size, int iswrite, int ismasked, const char *name, uml::code_handle **handleptr);
547
547548   void generate_update_mode(drcuml_block *block);
548549   void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception);
549550   void generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast);
550551   void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
551552   void generate_delay_slot_and_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 linkreg);
553
552554   int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
553555   int generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
554556   int generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
555557   int generate_idt(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
558
556559   int generate_set_cop0_reg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 reg);
557560   int generate_get_cop0_reg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 reg);
558561   int generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
559562   int generate_cop1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
560563   int generate_cop1x(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
564
565   void check_cop0_access(drcuml_block *block);
566   void check_cop1_access(drcuml_block *block);
567   void generate_badcop(drcuml_block *block, const int cop);
568
561569   void log_add_disasm_comment(drcuml_block *block, UINT32 pc, UINT32 op);
562570   const char *log_desc_flags_to_string(UINT32 flags);
563571   void log_register_list(drcuml_state *drcuml, const char *string, const UINT32 *reglist, const UINT32 *regnostarlist);
r31796r31797
743751
744752/* fix me -- how do we make this work?? */
745753#define MIPS3DRC_STRICT_VERIFY      0x0001          /* verify all instructions */
746#define MIPS3DRC_STRICT_COP1        0x0002          /* validate all COP1 instructions */
747#define MIPS3DRC_STRICT_COP2        0x0004          /* validate all COP2 instructions */
748#define MIPS3DRC_FLUSH_PC           0x0008          /* flush the PC value before each memory access */
749#define MIPS3DRC_CHECK_OVERFLOWS    0x0010          /* actually check overflows on add/sub instructions */
754#define MIPS3DRC_STRICT_COP0        0x0002          /* validate all COP0 instructions */
755#define MIPS3DRC_STRICT_COP1        0x0004          /* validate all COP1 instructions */
756#define MIPS3DRC_STRICT_COP2        0x0008          /* validate all COP2 instructions */
757#define MIPS3DRC_FLUSH_PC           0x0010          /* flush the PC value before each memory access */
758#define MIPS3DRC_CHECK_OVERFLOWS    0x0020          /* actually check overflows on add/sub instructions */
750759
751#define MIPS3DRC_COMPATIBLE_OPTIONS (MIPS3DRC_STRICT_VERIFY | MIPS3DRC_STRICT_COP1 | MIPS3DRC_STRICT_COP2 | MIPS3DRC_FLUSH_PC)
760#define MIPS3DRC_COMPATIBLE_OPTIONS (MIPS3DRC_STRICT_VERIFY | MIPS3DRC_STRICT_COP1 | MIPS3DRC_STRICT_COP0 | MIPS3DRC_STRICT_COP2 | MIPS3DRC_FLUSH_PC)
752761#define MIPS3DRC_FASTEST_OPTIONS    (0)
753762
754763
trunk/src/emu/cpu/mips/mips3drc.c
r31796r31797
16171617         return TRUE;
16181618
16191619      case 0x31:  /* LWC1 - MIPS I */
1620         UML_TEST(block, CPR032(COP0_Status), SR_COP1);                          // test    [Status],SR_COP1
1621         UML_EXHc(block, COND_Z, *m_exception[EXCEPTION_BADCOP], 1);            // exh     cop,1,Z
1620         check_cop1_access(block);
16221621         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
16231622         UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh   read32
16241623         UML_MOV(block, FPR32(RTREG), I0);                                   // mov     <cpr1_rt>,i0
r31796r31797
16271626         return TRUE;
16281627
16291628      case 0x35:  /* LDC1 - MIPS III */
1630         UML_TEST(block, CPR032(COP0_Status), SR_COP1);                          // test    [Status],SR_COP1
1631         UML_EXHc(block, COND_Z, *m_exception[EXCEPTION_BADCOP], 1);            // exh     cop,1,Z
1629         check_cop1_access(block);
16321630         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
16331631         UML_CALLH(block, *m_read64[m_core->mode >> 1]); // callh   read64
16341632         UML_DMOV(block, FPR64(RTREG), I0);                                  // dmov    <cpr1_rt>,i0
r31796r31797
17721770         return TRUE;
17731771
17741772      case 0x39:  /* SWC1 - MIPS I */
1775         UML_TEST(block, CPR032(COP0_Status), SR_COP1);                          // test    [Status],SR_COP1
1776         UML_EXHc(block, COND_Z, *m_exception[EXCEPTION_BADCOP], 1);            // exh     cop,1,Z
1773         check_cop1_access(block);
17771774         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
17781775         UML_MOV(block, I1, FPR32(RTREG));                                   // mov     i1,<cpr1_rt>
17791776         UML_CALLH(block, *m_write32[m_core->mode >> 1]);    // callh   write32
r31796r31797
17821779         return TRUE;
17831780
17841781      case 0x3d:  /* SDC1 - MIPS III */
1785         UML_TEST(block, CPR032(COP0_Status), SR_COP1);                          // test    [Status],SR_COP1
1786         UML_EXHc(block, COND_Z, *m_exception[EXCEPTION_BADCOP], 1);            // exh     cop,1,Z
1782         check_cop1_access(block);
17871783         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
17881784         UML_DMOV(block, I1, FPR64(RTREG));                                  // dmov    i1,<cpr1_rt>
17891785         UML_CALLH(block, *m_write64[m_core->mode >> 1]);    // callh   write64
r31796r31797
24802476}
24812477
24822478
2479/*-------------------------------------------------------------------------
2480    generate_badcop - raise a BADCOP exception
2481-------------------------------------------------------------------------*/
2482
2483void mips3_device::generate_badcop(drcuml_block *block, const int cop)
2484{
2485   UML_TEST(block, CPR032(COP0_Status), SR_COP0 << cop);               // test    [Status], SR_COP0 << cop
2486   UML_EXHc(block, COND_Z, *m_exception[EXCEPTION_BADCOP], cop);      // exh     badcop,cop,Z
2487}
2488
2489/*-------------------------------------------------------------------------
2490    check_cop0_access - raise a BADCOP exception if we're not in kernel mode
2491-------------------------------------------------------------------------*/
2492
2493void mips3_device::check_cop0_access(drcuml_block *block)
2494{
2495   if ((m_core->mode >> 1) != MODE_KERNEL)
2496   {
2497      generate_badcop(block, 0);
2498   }
2499}
2500
24832501/*-------------------------------------------------
24842502    generate_cop0 - compile COP0 opcodes
24852503-------------------------------------------------*/
r31796r31797
26062624    COP1 RECOMPILATION
26072625***************************************************************************/
26082626
2627/*-------------------------------------------------------------------------
2628    check_cop1_access - raise a BADCOP exception if COP1 is not enabled
2629-------------------------------------------------------------------------*/
2630
2631void mips3_device::check_cop1_access(drcuml_block *block)
2632{
2633   if (m_drcoptions & MIPS3DRC_STRICT_COP1)
2634   {
2635      generate_badcop(block, 1);
2636   }
2637}
2638
26092639/*-------------------------------------------------
26102640    generate_cop1 - compile COP1 opcodes
26112641-------------------------------------------------*/
r31796r31797
26162646   code_label skip;
26172647   condition_t condition;
26182648
2619   /* generate an exception if COP1 is disabled */
2620   if (m_drcoptions & MIPS3DRC_STRICT_COP1)
2621   {
2622      UML_TEST(block, CPR032(COP0_Status), SR_COP1);                          // test    [Status],SR_COP1
2623      UML_EXHc(block, COND_Z, *m_exception[EXCEPTION_BADCOP], 1);// exh     cop,1,Z
2624   }
2649   check_cop1_access(block);
26252650
26262651   switch (RSREG)
26272652   {
2628      case 0x00:  /* MFCz - MIPS I */
2653      case 0x00:  /* MFC1 - MIPS I */
26292654         if (RTREG != 0)
26302655            UML_DSEXT(block, R64(RTREG), FPR32(RDREG), SIZE_DWORD);                 // dsext   <rtreg>,fpr[rdreg],dword
26312656         return TRUE;
26322657
2633      case 0x01:  /* DMFCz - MIPS III */
2658      case 0x01:  /* DMFC1 - MIPS III */
26342659         if (RTREG != 0)
26352660            UML_DMOV(block, R64(RTREG), FPR64(RDREG));                          // dmov    <rtreg>,fpr[rdreg]
26362661         return TRUE;
26372662
2638      case 0x02:  /* CFCz - MIPS I */
2663      case 0x02:  /* CFC1 - MIPS I */
26392664         if (RTREG != 0)
26402665            UML_DSEXT(block, R64(RTREG), CCR132(RDREG), SIZE_DWORD);                    // dsext   <rtreg>,ccr132[rdreg],dword
26412666         return TRUE;
26422667
2643      case 0x04:  /* MTCz - MIPS I */
2668      case 0x04:  /* MTC1 - MIPS I */
26442669         UML_MOV(block, FPR32(RDREG), R32(RTREG));                               // mov     fpr[rdreg],<rtreg>
26452670         return TRUE;
26462671
2647      case 0x05:  /* DMTCz - MIPS III */
2672      case 0x05:  /* DMTC1 - MIPS III */
26482673         UML_DMOV(block, FPR64(RDREG), R64(RTREG));                              // dmov    fpr[rdreg],<rtreg>
26492674         return TRUE;
26502675
2651      case 0x06:  /* CTCz - MIPS I */
2676      case 0x06:  /* CTC1 - MIPS I */
26522677         if (RDREG != 31)
26532678            UML_DSEXT(block, CCR164(RDREG), R32(RTREG), SIZE_DWORD);                    // dsext   ccr1[rdreg],<rtreg>,dword
26542679         else
r31796r31797
29913016   int in_delay_slot = ((desc->flags & OPFLAG_IN_DELAY_SLOT) != 0);
29923017   UINT32 op = desc->opptr.l[0];
29933018
2994   if (m_drcoptions & MIPS3DRC_STRICT_COP1)
2995   {
2996      UML_TEST(block, CPR032(COP0_Status), SR_COP1);                          // test    [Status],SR_COP1
2997      UML_EXHc(block, COND_Z, *m_exception[EXCEPTION_BADCOP], 1);// exh     cop,1,Z
2998   }
3019   check_cop1_access(block);
29993020
30003021   switch (op & 0x3f)
30013022   {

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