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r31651 Thursday 14th August, 2014 at 10:21:26 UTC by hap
small cleanup
[src/emu/cpu/i86]i186.c
[src/emu/machine]pit8253.c pit8253.h
[src/mame/audio]leland.c

trunk/src/emu/machine/pit8253.c
r31650r31651
4141#define LOG1(msg)       do { if (VERBOSE >= 1) logerror msg; } while (0)
4242#define LOG2(msg)       do { if (VERBOSE >= 2) logerror msg; } while (0)
4343
44#define CYCLES_NEVER ((UINT32) -1)
44#define CYCLES_NEVER    (0xffffffff)
4545
4646
4747const device_type PIT8253 = &device_creator<pit8253_device>;
r31650r31651
5656   m_out1_handler(*this),
5757   m_out2_handler(*this)
5858{
59   for(int i = 0; i < ARRAY_LENGTH(m_timers); ++i)
59   for (int i = 0; i < PIT8253_MAX_TIMER; i++)
6060   {
6161      m_timers[i].gate = 1;
6262      m_timers[i].phase = 0;
r31650r31651
7373   m_out1_handler(*this),
7474   m_out2_handler(*this)
7575{
76   for(int i = 0; i < ARRAY_LENGTH(m_timers); ++i)
76   for (int i = 0; i < PIT8253_MAX_TIMER; i++)
7777   {
7878      m_timers[i].gate = 1;
7979      m_timers[i].phase = 0;
r31650r31651
129129      save_item(NAME(timer->latched_status), timerno);
130130      save_item(NAME(timer->null_count), timerno);
131131      save_item(NAME(timer->phase), timerno);
132      save_item(NAME(timer->cycles_to_output), timerno);
133132      save_item(NAME(timer->last_updated), timerno);
134133      save_item(NAME(timer->clock), timerno);
135134   }
r31650r31651
158157      timer->latched_count = 0;
159158      timer->latched_status = 0;
160159      timer->null_count = 1;
161      timer->cycles_to_output = CYCLES_NEVER;
162160
163161      timer->last_updated = machine().time();
164162
r31650r31651
215213
216214static UINT32 adjusted_count(int bcd, UINT16 val)
217215{
218   if (bcd == 0)
219      return val == 0 ? 0x10000 : val;
220   return val == 0 ? 10000 : decimal_from_bcd(val);
216   if (!bcd)
217      return (val == 0) ? 0x10000 : val;
218   return (val == 0) ? 10000 : decimal_from_bcd(val);
221219}
222220
223221
224222/* This function subtracts 1 from timer->value "cycles" times, taking into
225223   account binary or BCD operation, and wrapping around from 0 to 0xFFFF or
226224   0x9999 as necessary. */
227void pit8253_device::decrease_counter_value(pit8253_timer *timer, UINT64 cycles)
225void pit8253_device::decrease_counter_value(pit8253_timer *timer, INT64 cycles)
228226{
229227   UINT16 value;
230228   UINT8 units, tens, hundreds, thousands;
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250248      cycles -= units;
251249      units = (10 - cycles % 10) % 10;
252250
253      cycles =(cycles + 9) / 10; /* the +9    is so we get a carry if cycles%10 wasn't 0 */
251      cycles = (cycles + 9) / 10; /* the +9 is so we get a carry if cycles%10 wasn't 0 */
254252      if (cycles <= tens)
255253      {
256254         tens -= cycles;
r31650r31651
269267         {
270268            cycles -= hundreds;
271269            hundreds = (10 - cycles % 10) % 10;
272            cycles=(cycles + 9) / 10;
270            cycles = (cycles + 9) / 10;
273271            thousands = (10 + thousands - cycles % 10) % 10;
274272         }
275273      }
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321319   UINT32 adjusted_value;
322320   int bcd = CTRL_BCD(timer->control);
323321   int mode = CTRL_MODE(timer->control);
324   int cycles_to_output = 0;
322   UINT32 cycles_to_output = CYCLES_NEVER;
325323
326324   LOG2(("pit8253: simulate2(): simulating %d cycles for %d in mode %d, bcd = %d, phase = %d, gate = %d, output %d, value = 0x%04x\n",
327325         (int)elapsed_cycles, timer->index, mode, bcd, timer->phase, pit8253_gate(timer), timer->output, timer->value));
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503501            {
504502               if (elapsed_cycles + 1 >= adjusted_value)
505503               {
506                  /* Coounter hits 1, output goes low */
504                  /* Counter hits 1, output goes low */
507505                  timer->phase = 3;
508506                  set_output(timer, 0);
509507               }
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527525         switch (timer->phase)
528526         {
529527         case 1:   cycles_to_output = 1; break;
530         default:  cycles_to_output = (timer->value == 1 ? 1 : (adjusted_count(bcd, timer->value) - 1));
528         default:  cycles_to_output = (timer->value == 1) ? 1 : (adjusted_count(bcd, timer->value) - 1); break;
531529         }
532530      }
533531      break;
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604602            while ((timer->phase == 2 && elapsed_cycles >= ((adjusted_value + 1) >> 1)) ||
605603                  (timer->phase == 3 && elapsed_cycles >= (adjusted_value >> 1)));
606604
607            decrease_counter_value(timer, elapsed_cycles << 1);
605            decrease_counter_value(timer, elapsed_cycles * 2);
606
608607            switch (timer->phase)
609608            {
610609            case 1:  cycles_to_output = 1; break;
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692691      break;
693692   }
694693
695   timer->cycles_to_output = cycles_to_output;
696694   if (cycles_to_output == CYCLES_NEVER || timer->clockin == 0)
697695   {
698696      timer->updatetimer->adjust(attotime::never, timer->index);
r31650r31651
730728{
731729   if (elapsed_cycles > 0)
732730      simulate2(timer, elapsed_cycles);
733   else
734      if (timer->clockin)
735         timer->updatetimer->adjust(attotime::from_hz(timer->clockin), timer->index);
731   else if (timer->clockin)
732      timer->updatetimer->adjust(attotime::from_hz(timer->clockin), timer->index);
736733}
737734
738735
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741738{
742739   /* With the 82C54's maximum clockin of 10MHz, 64 bits is nearly 60,000
743740      years of time. Should be enough for now. */
744   attotime now = machine().time();
741   attotime now = machine().time();
745742   attotime elapsed_time = now - timer->last_updated;
746   INT64 elapsed_cycles = elapsed_time.as_double() * timer->clockin;
743   INT64 elapsed_cycles = elapsed_time.as_double() * timer->clockin;
747744
748745   LOG1(("pit8253: update(): timer %d, %" I64FMT "d elapsed_cycles\n", timer->index, elapsed_cycles));
749746
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811808         if (timer->latched_count != 0)
812809         {
813810            /* Read back latched count */
814            data = (timer->latch >> (timer->rmsb != 0 ? 8 : 0)) & 0xff;
811            data = (timer->latch >> (timer->rmsb ? 8 : 0)) & 0xff;
815812            timer->rmsb = 1 - timer->rmsb;
816813            --timer->latched_count;
817814         }
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840837
841838            case 3:
842839               /* read bits 0-7 first, then 8-15 */
843               data = (value >> (timer->rmsb != 0 ? 8 : 0)) & 0xff;
840               data = (value >> (timer->rmsb ? 8 : 0)) & 0xff;
844841               timer->rmsb = 1 - timer->rmsb;
845842               break;
846843            }
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892889   if ((command & 1) == 0)
893890   {
894891      /* readback status command */
895      if (timer->latched_status == 0)
892      if (!timer->latched_status)
896893      {
897         timer->status = (timer->control & 0x3f) | (timer->output != 0 ? 0x80 : 0) | (timer->null_count != 0 ? 0x40 : 0);
894         timer->status = (timer->control & 0x3f) | ((timer->output != 0) ? 0x80 : 0) | (timer->null_count ? 0x40 : 0);
895         timer->latched_status = 1;
898896      }
899
900      timer->latched_status = 1;
901897   }
902898   /* Experimentally determined: the read latch command seems to have no
903899      effect if we're halfway through a 16-bit read */
904   if ((command & 2) == 0 && timer->rmsb == 0)
900   if ((command & 2) == 0 && !timer->rmsb)
905901   {
906902      /* readback count command */
907903
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984980         /* Experimentally verified: this command does not affect the mode control register */
985981         readback(timer, 1);
986982      }
987      else {
983      else
984      {
988985         LOG1(("pit8253: write(): timer=%d bytes=%d mode=%d bcd=%d\n", (data >> 6) & 3, (data >> 4) & 3, (data >> 1) & 7, data & 1));
989986
990987         timer->control = (data & 0x3f);
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10391036
10401037      case 3:
10411038         /* read/write bits 0-7 first, then 8-15 */
1042         if (timer->wmsb != 0)
1039         if (timer->wmsb)
10431040         {
10441041            /* check if we should compensate for not being on a cycle boundary */
10451042            if (middle_of_a_cycle)
trunk/src/emu/machine/pit8253.h
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6262   UINT8 control;                  /* 6-bit control byte */
6363   UINT8 status;                   /* status byte - 8254 only */
6464   UINT8 lowcount;                 /* LSB of new counter value for 16-bit writes */
65   INT32 rmsb;                     /* 1 = Next read is MSB of 16-bit value */
66   INT32 wmsb;                     /* 1 = Next write is MSB of 16-bit value */
67   INT32 output;                       /* 0 = low, 1 = high */
65   int rmsb;                       /* 1 = Next read is MSB of 16-bit value */
66   int wmsb;                       /* 1 = Next write is MSB of 16-bit value */
67   int output;                     /* 0 = low, 1 = high */
6868
69   INT32 gate;                     /* gate input (0 = low, 1 = high) */
70   INT32 latched_count;                /* number of bytes of count latched */
71   INT32 latched_status;               /* 1 = status latched (8254 only) */
72   INT32 null_count;                   /* 1 = mode control or count written, 0 = count loaded */
73   INT32 phase;                        /* see phase definition tables in simulate2(), below */
74
75   UINT32 cycles_to_output;        /* cycles until output callback called */
69   int gate;                       /* gate input (0 = low, 1 = high) */
70   int latched_count;              /* number of bytes of count latched */
71   int latched_status;             /* 1 = status latched (8254 only) */
72   int null_count;                 /* 1 = mode control or count written, 0 = count loaded */
73   int phase;                      /* see phase definition tables in simulate2(), below */
7674};
7775
7876class pit8253_device : public device_t
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125123
126124private:
127125   int pit8253_gate(pit8253_timer *timer);
128   void decrease_counter_value(pit8253_timer *timer, UINT64 cycles);
126   void decrease_counter_value(pit8253_timer *timer, INT64 cycles);
129127   void load_counter_value(pit8253_timer *timer);
130128   void set_output(pit8253_timer *timer, int output);
131129   void simulate2(pit8253_timer *timer, INT64 elapsed_cycles);
trunk/src/emu/cpu/i86/i186.c
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10321032            t->int_timer->adjust(attotime::never, which);
10331033         break;
10341034      }
1035
10351036      default:
10361037         break;
10371038   }
r31650r31651
10521053   struct timer_state *t = &m_timer[which];
10531054
10541055   t->count++;
1055   if(t->control & 2)
1056   if (t->control & 2)
10561057   {
1057      if(t->count == (t->active_count ? t->maxB : t->maxA))
1058      if (t->count == (t->active_count ? t->maxB : t->maxA))
10581059         device_timer(*t->int_timer, which, which, NULL);
10591060   }
1060   else if(t->count == t->maxA)
1061   else if (t->count == t->maxA)
10611062      device_timer(*t->int_timer, which, which, NULL);
10621063}
10631064
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10881089         internal_timer_sync(which);
10891090         update_int_timer = 1;
10901091      }
1092
10911093      t->maxA = new_maxA;
1094
10921095      if (new_maxA == 0)
10931096      {
1094            new_maxA = 0x10000;
1097         new_maxA = 0x10000;
10951098      }
10961099   }
10971100
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11081111
11091112      if (new_maxB == 0)
11101113      {
1111            new_maxB = 0x10000;
1114         new_maxB = 0x10000;
11121115      }
11131116   }
11141117
1115
11161118   /* handle control changes */
11171119   if (new_control != -1)
11181120   {
r31650r31651
13671369      case 0x30:
13681370         if (LOG_PORTS) logerror("%05X:read 80186 Timer %d count\n", pc(), (offset - 0x28) / 4);
13691371         which = (offset - 0x28) / 4;
1370         if (!(offset & 1))
1372         if (ACCESSING_BITS_0_7)
13711373            internal_timer_sync(which);
13721374         return m_timer[which].count;
13731375
r31650r31651
14661468WRITE16_MEMBER(i80186_cpu_device::internal_port_w)
14671469{
14681470   int which;
1469
1471   
14701472   switch (offset)
14711473   {
14721474      case 0x11:
r31650r31651
16701672         {
16711673            UINT32 newmap = (data & 0xfff) << 8;
16721674            UINT32 oldmap = (m_reloc & 0xfff) << 8;
1673            if(!(data & 0x1000) || ((data & 0x1000) && (m_reloc & 0x1000)))
1675            if (!(data & 0x1000) || ((data & 0x1000) && (m_reloc & 0x1000)))
16741676               m_program->unmap_readwrite(oldmap, oldmap + 0xff);
1675            if(data & 0x1000) // TODO: make work with 80188 if needed
1677            if (data & 0x1000) // TODO: make work with 80188 if needed
16761678               m_program->install_readwrite_handler(newmap, newmap + 0xff, read16_delegate(FUNC(i80186_cpu_device::internal_port_r), this), write16_delegate(FUNC(i80186_cpu_device::internal_port_w), this));
16771679         }
16781680         m_reloc = data;
trunk/src/mame/audio/leland.c
r31650r31651
124124
125125WRITE_LINE_MEMBER(leland_80186_sound_device::i80186_tmr1_w)
126126{
127   if(state)
127   if (state)
128128   {
129      if(m_ext_active && (m_ext_start < m_ext_stop))
129      if (m_ext_active && (m_ext_start < m_ext_stop))
130130      {
131131         m_dac_sample[7] = (m_ext_base[m_ext_start] << 8) - 0x8000;
132132         m_ext_start++;
r31650r31651
248248   m_audiocpu = downcast<i80186_cpu_device *>(machine().device("audiocpu"));
249249
250250   /* determine which sound hardware is installed */
251   if(m_type == TYPE_WSF)
251   if (m_type == TYPE_WSF)
252252      m_ext_base = machine().root_device().memregion("dac")->base();
253253
254254   m_dac_timer = timer_alloc();
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257257void leland_80186_sound_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
258258{
259259   INT32 out = 0;
260   for(int i = 0; i < 8; i++)
260   for (int i = 0; i < 8; i++)
261261      out += m_dac_sample[i] * m_dac_volume[i];
262   m_dac->write(out>>10);
262
263   m_dac->write(out >> 10);
263264}
264265
265266void leland_80186_sound_device::device_reset()
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324325
325326WRITE16_MEMBER(leland_80186_sound_device::peripheral_ctrl)
326327{
327   switch(offset)
328   switch (offset)
328329   {
329330      case 2:
330331         m_peripheral = data;
331332         break;
333
332334      case 4:
333335      {
334336         UINT32 temp = (m_peripheral & 0xffc0) << 4;
r31650r31651
343345         }
344346         break;
345347      }
348
346349      default:
347350         break;
348351   }
r31650r31651
494497   /* handle value changes */
495498   if (ACCESSING_BITS_0_7)
496499   {
497      m_dac_sample[which] = (data << 8) - 0x8000;
500      m_dac_sample[which] = (data << 8 & 0xff00) - 0x8000;
498501      m_clock_active &= ~(1<<which);
499502   }
500503
r31650r31651
535538         if (ACCESSING_BITS_0_7)
536539            dac_w(space, 1, data, mem_mask);
537540         return;
541     
542      default:
543         break;
538544   }
539545
540546   /* if we have a YM2151 (and an external DAC), handle those offsets */
r31650r31651
565571            m_ext_stop <<= 4;
566572            if (LOG_EXTERN) logerror("External DAC stop = %05X\n", m_ext_stop);
567573            return;
574         
575         default:
576            break;
568577      }
569578   }
570579   logerror("%05X:Unexpected peripheral write %d/%02X = %02X\n", m_audiocpu->device_t::safe_pc(), 5, offset, data);
r31650r31651
601610         return main_to_sound_comm_r(space, offset, mem_mask);
602611
603612      case 2:
604         if(mem_mask == 0xff00)
605            return 0xffff;
606         return m_pit0->read(space, offset & 3);
613         if (mem_mask != 0xff00)
614            return m_pit0->read(space, offset & 3);
615         break;
607616
608617      case 3:
609618         if (m_type <= TYPE_REDLINE)
610619         {
611            if(mem_mask == 0xff00)
612               return 0xffff;
613            return m_pit1->read(space, offset & 3);
620            if (mem_mask != 0xff00)
621               return m_pit1->read(space, offset & 3);
614622         }
615         else if(m_type == TYPE_WSF)
623         else if (m_type == TYPE_WSF)
616624            return m_ymsnd->read(space, offset);
617625         break;
618626
619627      case 4:
620628         if (m_type == TYPE_REDLINE)
621629         {
622            if(mem_mask == 0xff00)
623               return 0xffff;
624            return m_pit2->read(space, offset & 3);
630            if (mem_mask != 0xff00)
631               return m_pit2->read(space, offset & 3);
625632         }
626633         else
627634            logerror("%05X:Unexpected peripheral read %d/%02X\n", m_audiocpu->device_t::safe_pc(), select, offset*2);
r31650r31651
647654         break;
648655
649656      case 2:
650         if(mem_mask == 0xff00)
651            return;
652         m_pit0->write(space, offset & 3, data);
657         if (mem_mask != 0xff00)
658            m_pit0->write(space, offset & 3, data);
653659         break;
654660
655661      case 3:
656662         if (m_type <= TYPE_REDLINE)
657663         {
658            if(mem_mask == 0xff00)
659               return;
660            m_pit1->write(space, offset & 3, data);
664            if (mem_mask != 0xff00)
665               m_pit1->write(space, offset & 3, data);
661666         }
662667         else if(m_type == TYPE_WSF)
663668            m_ymsnd->write(space, offset, data);
r31650r31651
666671      case 4:
667672         if (m_type == TYPE_REDLINE)
668673         {
669            if(mem_mask == 0xff00)
670               return;
671            m_pit2->write(space, offset & 3, data);
674            if (mem_mask != 0xff00)
675               m_pit2->write(space, offset & 3, data);
672676         }
673         else if(mem_mask == 0xffff)
677         else if (mem_mask == 0xffff)
674678         {
675679            m_dac_sample[6] = (data << 6) - 0x8000;
676680            m_clock_active &= ~(1<<6);
r31650r31651
678682         break;
679683
680684      case 5: /* Ataxx/WSF/Indy Heat only */
681         if(m_type > TYPE_REDLINE)
685         if (m_type > TYPE_REDLINE)
682686            ataxx_dac_control(space, offset, data, mem_mask);
683687         break;
684688

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