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r31646 Wednesday 13th August, 2014 at 23:11:06 UTC by Phil Bennett
02124: nebulray, nebulrayj: Nebulas Ray is missing a rotation effect in the first level [Phil Bennett]

namconb1.c - Improved interrupt handling, fixing raster-effects (used by nebulray and machbrkr) and nebulray test mode. [Phil Bennett]
[src/mame/drivers]namconb1.c
[src/mame/includes]namconb1.h

trunk/src/mame/includes/namconb1.h
r31645r31646
4343   required_shared_ptr<UINT16> m_namconb_shareram;
4444   required_shared_ptr<UINT32> m_generic_paletteram_32;
4545
46   UINT8 m_namconb_cpureg[32];
47   int m_vblank_irq_active;
48   int m_pos_irq_active;
46   UINT8 m_vbl_irq_level;
47   UINT8 m_pos_irq_level;
48   UINT8 m_unk_irq_level;
4949   UINT16 m_count;
5050   UINT8 m_nbx_port6;
5151   UINT32 m_tilemap_tile_bank[4];
5252
5353   DECLARE_READ32_MEMBER(randgen_r);
5454   DECLARE_WRITE32_MEMBER(srand_w);
55   DECLARE_WRITE32_MEMBER(namconb1_cpureg_w);
56   DECLARE_WRITE32_MEMBER(namconb2_cpureg_w);
57   DECLARE_READ32_MEMBER(namconb_cpureg_r);
55   DECLARE_WRITE8_MEMBER(namconb1_cpureg_w);
56   DECLARE_WRITE8_MEMBER(namconb2_cpureg_w);
57   DECLARE_READ8_MEMBER(namconb1_cpureg_r);
58   DECLARE_READ8_MEMBER(namconb2_cpureg_r);
5859   DECLARE_READ32_MEMBER(custom_key_r);
5960   DECLARE_READ32_MEMBER(gunbulet_gun_r);
6061   DECLARE_READ32_MEMBER(namconb_share_r);
r31645r31646
7172   DECLARE_READ8_MEMBER(dac2_r);
7273   DECLARE_READ8_MEMBER(dac1_r);
7374   DECLARE_READ8_MEMBER(dac0_r);
75
7476   DECLARE_DRIVER_INIT(sws95);
7577   DECLARE_DRIVER_INIT(machbrkr);
7678   DECLARE_DRIVER_INIT(sws97);
r31645r31646
8183   DECLARE_DRIVER_INIT(gslgr94j);
8284   DECLARE_DRIVER_INIT(outfxies);
8385   DECLARE_DRIVER_INIT(gslgr94u);
84   DECLARE_MACHINE_START(namconb);
86   DECLARE_MACHINE_RESET(namconb);
8587   DECLARE_VIDEO_START(namconb1);
8688   DECLARE_VIDEO_START(namconb2);
8789   UINT32 screen_update_namconb1(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
8890   UINT32 screen_update_namconb2(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
89   INTERRUPT_GEN_MEMBER(namconb1_interrupt);
90   INTERRUPT_GEN_MEMBER(namconb2_interrupt);
91   TIMER_CALLBACK_MEMBER(namconb1_TriggerPOSIRQ);
92   TIMER_CALLBACK_MEMBER(namconb2_TriggerPOSIRQ);
93   TIMER_DEVICE_CALLBACK_MEMBER(mcu_interrupt);
91
92   TIMER_DEVICE_CALLBACK_MEMBER(namconb_scantimer);
9493};
trunk/src/mame/drivers/namconb1.c
r31645r31646
281281
282282/****************************************************************************/
283283
284TIMER_DEVICE_CALLBACK_MEMBER(namconb1_state::mcu_interrupt)
284TIMER_DEVICE_CALLBACK_MEMBER(namconb1_state::namconb_scantimer)
285285{
286286   int scanline = param;
287287
288   /* TODO: real sources of these */
288   // Handle VBLANK
289   if (scanline == NAMCONB1_VBSTART)
290   {
291      if (m_vbl_irq_level != 0)
292         m_maincpu->set_input_line(m_vbl_irq_level, ASSERT_LINE);
293   }
294
295   // Handle POSIRQ
296   UINT32 posirq_scanline = (m_generic_paletteram_32[0x1808/4] & 0xffff) - 32;
297
298   if (scanline == posirq_scanline)
299   {
300      m_screen->update_partial(posirq_scanline);
301
302      if (m_pos_irq_level != 0)
303         m_maincpu->set_input_line(m_pos_irq_level, ASSERT_LINE);
304   }
305
306   // TODO: Real sources of these
289307   if (scanline == 224)
290308      m_mcu->set_input_line(M37710_LINE_IRQ0, HOLD_LINE);
291309   else if (scanline == 0)
r31645r31646
295313}
296314
297315
298TIMER_CALLBACK_MEMBER(namconb1_state::namconb1_TriggerPOSIRQ)
299{
300   if(m_pos_irq_active || !(m_namconb_cpureg[0x02] & 0xf0))
301      return;
302316
303   m_screen->update_partial(param);
304   m_pos_irq_active = 1;
305   m_maincpu->set_input_line(m_namconb_cpureg[0x02] & 0xf, ASSERT_LINE);
306}
317/****************************************************************************/
307318
308INTERRUPT_GEN_MEMBER(namconb1_state::namconb1_interrupt)
319WRITE8_MEMBER(namconb1_state::namconb1_cpureg_w)
309320{
310321   /**
311322    * 400000 0x00
312    * 400001 0x00
313    * 400002 0x00
323    * 400001 POS IRQ enable/level
324    * 400002 ??? IRQ enable/level
314325    * 400003 0x00
315    * 400004 0x35 // irq levels
326    * 400004 VBL IRQ enable/level
316327    * 400005 0x00
317    * 400006 0x00
318    * 400007 0x00
328    * 400006 POS IRQ ack
329    * 400007 ??? IRQ ack
319330    * 400008 0x00
320    * 400009 0x00 VBLANK ack
321    * 40000a 0x00
322    * 40000b 0x03
323    * 40000c 0x07
324    * 40000d 0x01
325    * 40000e 0x10
326    * 40000f 0x03
327    * 400010 0x00
328    * 400011 0x07
329    * 400012 0x10
330    * 400013 0x10
331    * 400014 0x00
332    * 400015 0x01
333    * 400016 (watchdog)
334    * 400017 0x00
335    * 400018 0x01
336    * 400019 0x00
337    * 40001a 0x00
338    * 40001b 0x00
339    * 40001c 0x00
340    * 40001d 0x00
341    * 40001e 0x00
342    * 40001f 0x00
331    * 400009 VBL IRQ ack
332    * 40000a ??? (0x00)
333    * 40000b ??? (0x03)
334    * 40000c ??? (0x07)
335    * 40000d ??? (0x01)
336    * 40000e ??? (0x10)
337    * 40000f ??? (0x03)
338    * 400010 ??? (0x00)
339    * 400011 ??? (0x07)
340    * 400012 ??? (0x10)
341    * 400013 ??? (0x10)
342    * 400014 ??? (0x00)
343    * 400015 ??? (0x01)
344    * 400016 Watchdog
345    * 400017 ??? (0x00)
346    * 400018 C75 Control
347    * 400019 ??? (0x00)
348    * 40001a ??? (0x00)
349    * 40001b ??? (0x00)
350    * 40001c ??? (0x00)
351    * 40001d ??? (0x00)
352    * 40001e ??? (0x00)
353    * 40001f ??? (0x00)
343354    */
344   int scanline = (m_generic_paletteram_32[0x1808/4]&0xffff)-32;
355   switch (offset)
356   {
357      case 0x01:
358         // Bits 5-4 unknown
359         m_maincpu->set_input_line(m_pos_irq_level, CLEAR_LINE);
360         m_pos_irq_level = data & 0x0f;
361         break;
345362
346   if((!m_vblank_irq_active) && (m_namconb_cpureg[0x04] & 0xf0)) {
347      device.execute().set_input_line(m_namconb_cpureg[0x04] & 0xf, ASSERT_LINE);
348      m_vblank_irq_active = 1;
349   }
363      case 0x02:
364         m_maincpu->set_input_line(m_unk_irq_level, CLEAR_LINE);
365         m_unk_irq_level = data & 0x0f;
366         break;
350367
351   if( scanline<0 )
352   {
353      scanline = 0;
354   }
355   if( scanline < NAMCONB1_VBSTART )
356   {
357      machine().scheduler().timer_set( m_screen->time_until_pos(scanline), timer_expired_delegate(FUNC(namconb1_state::namconb1_TriggerPOSIRQ),this), scanline);
358   }
359} /* namconb1_interrupt */
368      case 0x04:
369         m_maincpu->set_input_line(m_vbl_irq_level, CLEAR_LINE);
370         m_vbl_irq_level = data & 0x0f;
371         break;
360372
373      case 0x06:
374         m_maincpu->set_input_line(m_pos_irq_level, CLEAR_LINE);
375         break;
361376
362TIMER_CALLBACK_MEMBER(namconb1_state::namconb2_TriggerPOSIRQ)
363{
364   m_screen->update_partial(param);
365   m_pos_irq_active = 1;
366   m_maincpu->set_input_line(m_namconb_cpureg[0x02], ASSERT_LINE);
377      case 0x07:
378         m_maincpu->set_input_line(m_unk_irq_level, CLEAR_LINE);
379         break;
380
381      case 0x09:
382         m_maincpu->set_input_line(m_vbl_irq_level, CLEAR_LINE);
383         break;
384
385      case 0x16:
386         break;
387
388      case 0x18:
389         if (data & 1)
390         {
391            m_mcu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
392            m_mcu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
393            m_mcu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
394         }
395         else
396            m_mcu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
397         break;
398
399      default:
400         logerror("Unhandled CPU reg write to [0x%.2x] with 0x%.2x (PC=0x%x)\n", offset, data, space.device().safe_pc());
401   }
367402}
368403
369INTERRUPT_GEN_MEMBER(namconb1_state::namconb2_interrupt)
404
405WRITE8_MEMBER(namconb1_state::namconb2_cpureg_w)
370406{
371407   /**
372    * f00000 0x01 // VBLANK irq level
373    * f00001 0x00
374    * f00002 0x05 // POSIRQ level
375    * f00003 0x00
376    *
377    * f00004 VBLANK ack
378    * f00005
379    * f00006 POSIRQ ack
408    * f00000 VBL IRQ enable/level
409    * f00001 ??? IRQ enable/level
410    * f00002 POS IRQ enable/level
411    * f00003 ??? (0x00)
412    * f00004 VBL IRQ ack
413    * f00005 ??? IRQ ack
414    * f00006 POS IRQ ack
380415    * f00007
381    *
382416    * f00008
383    *
384    * f00009 0x62
385    * f0000a 0x0f
386    * f0000b 0x41
387    * f0000c 0x70
388    * f0000d 0x70
389    * f0000e 0x23
390    * f0000f 0x50
391    * f00010 0x00
392    * f00011 0x64
393    * f00012 0x18
394    * f00013 0xe7
395    * f00014 (watchdog)
396    * f00016 0x00
397    * f0001e 0x00
398    * f0001f 0x01
417    * f00009 ??? (0x62)
418    * f0000a ??? (0x0f)
419    * f0000b ??? (0x41)
420    * f0000c ??? (0x70)
421    * f0000d ??? (0x70)
422    * f0000e ??? (0x23)
423    * f0000f ??? (0x50)
424    * f00010 ??? (0x00)
425    * f00011 ??? (0x64)
426    * f00012 ??? (0x18)
427    * f00013 ??? (0xe7)
428    * f00014 Watchdog
429    * f00015
430    * f00016 C75 Control
431    * f00017
432    * f00018
433    * f00019
434    * f0001a
435    * f0001b
436    * f0001c
437    * f0001d
438    * f0001e ??? (0x00)
439    * f0001f ??? (0x01)
399440    */
400   int scanline = (m_generic_paletteram_32[0x1808/4]&0xffff)-32;
441   switch (offset)
442   {
443      case 0x00:
444         m_maincpu->set_input_line(m_vbl_irq_level, CLEAR_LINE);
445         m_vbl_irq_level = data & 0x0f;
446         break;
401447
402   if((!m_vblank_irq_active) && m_namconb_cpureg[0x00]) {
403      device.execute().set_input_line(m_namconb_cpureg[0x00], ASSERT_LINE);
404      m_vblank_irq_active = 1;
405   }
448      case 0x01:
449         m_maincpu->set_input_line(m_unk_irq_level, CLEAR_LINE);
450         m_unk_irq_level = data & 0x0f;
451         break;
406452
407   if( scanline<0 )
408      scanline = 0;
453      case 0x02:
454         m_maincpu->set_input_line(m_pos_irq_level, CLEAR_LINE);
455         m_pos_irq_level = data & 0x0f;
456         break;
409457
410   if( scanline < NAMCONB1_VBSTART )
411      machine().scheduler().timer_set( m_screen->time_until_pos(scanline), timer_expired_delegate(FUNC(namconb1_state::namconb2_TriggerPOSIRQ),this), scanline);
412} /* namconb2_interrupt */
458      case 0x04:
459         m_maincpu->set_input_line(m_vbl_irq_level, CLEAR_LINE);
460         break;
413461
414/****************************************************************************/
462      case 0x05:
463         m_maincpu->set_input_line(m_unk_irq_level, CLEAR_LINE);
464         break;
415465
416static void namconb1_cpureg8_w(running_machine &machine, int reg, UINT8 data)
417{
418   namconb1_state *state = machine.driver_data<namconb1_state>();
419   UINT8 prev = state->m_namconb_cpureg[reg];
420   state->m_namconb_cpureg[reg] = data;
421   switch(reg) {
422   case 0x02: // POS IRQ level/enable
423      if(state->m_pos_irq_active && (((prev & 0xf) != (data & 0xf)) || !(data & 0xf0))) {
424         state->m_maincpu->set_input_line(prev & 0xf, CLEAR_LINE);
425         if(data & 0xf0)
426            state->m_maincpu->set_input_line(data & 0xf, ASSERT_LINE);
427         else
428            state->m_pos_irq_active = 0;
429      }
430      break;
466      case 0x06:
467         m_maincpu->set_input_line(m_pos_irq_level, CLEAR_LINE);
468         break;
431469
432   case 0x04: // VBLANK IRQ level/enable
433      if(state->m_vblank_irq_active && (((prev & 0xf) != (data & 0xf)) || !(data & 0xf0))) {
434         state->m_maincpu->set_input_line(prev & 0xf, CLEAR_LINE);
435         if(data & 0xf0)
436            state->m_maincpu->set_input_line(data & 0xf, ASSERT_LINE);
470      case 0x14:
471         break;
472
473      case 0x16:
474         if (data & 1)
475         {
476            m_mcu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
477            m_mcu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
478            m_mcu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
479         }
437480         else
438            state->m_vblank_irq_active = 0;
439      }
440      break;
481         {
482            m_mcu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
483         }
484         break;
441485
442   case 0x07: // POS ack
443      if(state->m_pos_irq_active) {
444         state->m_maincpu->set_input_line(state->m_namconb_cpureg[0x02] & 0xf, CLEAR_LINE);
445         state->m_pos_irq_active = 0;
446      }
447      break;
448
449   case 0x09: // VBLANK ack
450      if(state->m_vblank_irq_active) {
451         state->m_maincpu->set_input_line(state->m_namconb_cpureg[0x04] & 0xf, CLEAR_LINE);
452         state->m_vblank_irq_active = 0;
453      }
454      break;
455
456   case 0x16: // Watchdog
457      break;
458
459   case 0x18: // C75 Control
460      if(data & 1) {
461         state->m_mcu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
462         state->m_mcu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
463         state->m_mcu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
464      } else
465         state->m_mcu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
466      break;
486      default:
487         logerror("Unhandled CPU reg write to [0x%.2x] with 0x%.2x (PC=0x%x)\n", offset, data, space.device().safe_pc());
467488   }
468489}
469490
470WRITE32_MEMBER(namconb1_state::namconb1_cpureg_w)
471{
472   if(mem_mask & 0xff000000)
473      namconb1_cpureg8_w(machine(), offset*4, data >> 24);
474   if(mem_mask & 0x00ff0000)
475      namconb1_cpureg8_w(machine(), offset*4+1, data >> 16);
476   if(mem_mask & 0x0000ff00)
477      namconb1_cpureg8_w(machine(), offset*4+2, data >> 8);
478   if(mem_mask & 0x000000ff)
479      namconb1_cpureg8_w(machine(), offset*4+3, data);
480}
481491
482
483static void namconb2_cpureg8_w(running_machine &machine, int reg, UINT8 data)
492READ8_MEMBER(namconb1_state::namconb1_cpureg_r)
484493{
485   namconb1_state *state = machine.driver_data<namconb1_state>();
486   UINT8 prev = state->m_namconb_cpureg[reg];
487   state->m_namconb_cpureg[reg] = data;
488   switch(reg) {
489   case 0x00: // VBLANK IRQ level
490      if(state->m_vblank_irq_active && (prev != data)) {
491         state->m_maincpu->set_input_line(prev, CLEAR_LINE);
492         if(data)
493            state->m_maincpu->set_input_line(data, ASSERT_LINE);
494         else
495            state->m_vblank_irq_active = 0;
496      }
497      break;
494   // 16: Watchdog
495   if (offset != 0x16)
496      logerror("Unhandled CPU reg read from [0x%.2x] (PC=0x%x)\n", offset, space.device().safe_pc());
498497
499   case 0x02: // POS IRQ level
500      if(state->m_pos_irq_active && (prev != data)) {
501         state->m_maincpu->set_input_line(prev, CLEAR_LINE);
502         if(data)
503            state->m_maincpu->set_input_line(data, ASSERT_LINE);
504         else
505            state->m_pos_irq_active = 0;
506      }
507      break;
508
509   case 0x04: // VBLANK ack
510      if(state->m_vblank_irq_active) {
511         state->m_maincpu->set_input_line(state->m_namconb_cpureg[0x00], CLEAR_LINE);
512         state->m_vblank_irq_active = 0;
513      }
514      break;
515
516   case 0x06: // POS ack
517      if(state->m_pos_irq_active) {
518         state->m_maincpu->set_input_line(state->m_namconb_cpureg[0x02], CLEAR_LINE);
519         state->m_pos_irq_active = 0;
520      }
521      break;
522
523   case 0x14: // Watchdog
524      break;
525
526   case 0x16: // C75 Control
527      if(data & 1) {
528         state->m_mcu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
529         state->m_mcu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
530         state->m_mcu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
531      } else {
532         state->m_mcu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
533      }
534      break;
535   }
498   return 0xff;
536499}
537500
538WRITE32_MEMBER(namconb1_state::namconb2_cpureg_w)
539{
540   if(mem_mask & 0xff000000)
541      namconb2_cpureg8_w(machine(), offset*4, data >> 24);
542   if(mem_mask & 0x00ff0000)
543      namconb2_cpureg8_w(machine(), offset*4+1, data >> 16);
544   if(mem_mask & 0x0000ff00)
545      namconb2_cpureg8_w(machine(), offset*4+2, data >> 8);
546   if(mem_mask & 0x000000ff)
547      namconb2_cpureg8_w(machine(), offset*4+3, data);
548}
549501
550READ32_MEMBER(namconb1_state::namconb_cpureg_r)
502READ8_MEMBER(namconb1_state::namconb2_cpureg_r)
551503{
552   return (m_namconb_cpureg[offset*4] << 24) | (m_namconb_cpureg[offset*4+1] << 16)
553      | (m_namconb_cpureg[offset*4+2] << 8) | m_namconb_cpureg[offset*4+3];
504   // 14: Watchdog
505   if (offset != 0x14)
506      logerror("Unhandled CPU reg read from [0x%.2x] (PC=0x%x)\n", offset, space.device().safe_pc());
507
508   return 0xff;
554509}
555510
556511
r31645r31646
565520      m_count = machine().rand();
566521   } while( m_count==old_count );
567522
568   switch( m_gametype )
523   switch (m_gametype)
569524   {
570525   /*
571526       Gunbullet/Point Blank keycus notes (thanks Guru):
r31645r31646
583538      return 0;
584539
585540   case NAMCONB1_SWS95:
586      switch( offset )
541      switch (offset)
587542      {
588      case 0: return 0x0189;
589      case 1: return  m_count<<16;
543         case 0: return 0x0189;
544         case 1: return  m_count<<16;
590545      }
591546      break;
592547
593548   case NAMCONB1_SWS96:
594      switch( offset )
549      switch (offset)
595550      {
596      case 0: return 0x01aa<<16;
597      case 4: return m_count<<16;
551         case 0: return 0x01aa<<16;
552         case 4: return m_count<<16;
598553      }
599554      break;
600555
601556   case NAMCONB1_SWS97:
602      switch( offset )
557      switch (offset)
603558      {
604      case 2: return 0x1b2<<16;
605      case 5: return m_count<<16;
559         case 2: return 0x1b2<<16;
560         case 5: return m_count<<16;
606561      }
607562      break;
608563
609564   case NAMCONB1_GSLGR94U:
610      switch( offset )
565      switch (offset)
611566      {
612      case 0: return 0x0167;
613      case 1: return m_count<<16;
567         case 0: return 0x0167;
568         case 1: return m_count<<16;
614569      }
615570      break;
616571
617572   case NAMCONB1_GSLGR94J:
618      switch( offset )
573      switch (offset)
619574      {
620575      case 1: return 0;
621576      case 3: return (0x0171<<16) | m_count;
r31645r31646
623578      break;
624579
625580   case NAMCONB1_NEBULRAY:
626      switch( offset )
581      switch (offset)
627582      {
628      case 1: return 0x016e;
629      case 3: return m_count;
583         case 1: return 0x016e;
584         case 3: return m_count;
630585      }
631586      break;
632587
633588   case NAMCONB1_VSHOOT:
634      switch( offset )
589      switch (offset)
635590      {
636      case 2: return m_count<<16;
637      case 3: return 0x0170<<16;
591         case 2: return m_count<<16;
592         case 3: return 0x0170<<16;
638593      }
639594      break;
640595
641596   case NAMCONB2_OUTFOXIES:
642      switch( offset )
597      switch (offset)
643598      {
644      case 0: return 0x0186;
645      case 1: return m_count<<16;
599         case 0: return 0x0186;
600         case 1: return m_count<<16;
646601      }
647602      break;
648603
r31645r31646
661616{
662617   int result = 0;
663618
664   switch( offset )
619   switch (offset)
665620   {
666   case 0: case 1: result = (UINT8)(0x0f + ioport("LIGHT1_Y")->read() * 224/255); break; /* Y (p2) */
667   case 2: case 3: result = (UINT8)(0x26 + ioport("LIGHT1_X")->read() * 288/314); break; /* X (p2) */
668   case 4: case 5: result = (UINT8)(0x0f + ioport("LIGHT0_Y")->read() * 224/255); break; /* Y (p1) */
669   case 6: case 7: result = (UINT8)(0x26 + ioport("LIGHT0_X")->read() * 288/314); break; /* X (p1) */
621      case 0: case 1: result = (UINT8)(0x0f + ioport("LIGHT1_Y")->read() * 224/255); break; /* Y (p2) */
622      case 2: case 3: result = (UINT8)(0x26 + ioport("LIGHT1_X")->read() * 288/314); break; /* X (p2) */
623      case 4: case 5: result = (UINT8)(0x0f + ioport("LIGHT0_Y")->read() * 224/255); break; /* Y (p1) */
624      case 6: case 7: result = (UINT8)(0x26 + ioport("LIGHT0_X")->read() * 288/314); break; /* X (p1) */
670625   }
671626   return result<<24;
672627} /* gunbulet_gun_r */
r31645r31646
704659   AM_RANGE(0x1e4000, 0x1e4003) AM_READWRITE(randgen_r,srand_w)
705660   AM_RANGE(0x200000, 0x207fff) AM_READWRITE(namconb_share_r, namconb_share_w)
706661   AM_RANGE(0x208000, 0x2fffff) AM_RAM
707   AM_RANGE(0x400000, 0x40001f) AM_READWRITE(namconb_cpureg_r, namconb1_cpureg_w)
662   AM_RANGE(0x400000, 0x40001f) AM_READWRITE8(namconb1_cpureg_r, namconb1_cpureg_w, 0xffffffff)
708663   AM_RANGE(0x580000, 0x5807ff) AM_DEVREADWRITE8("eeprom", eeprom_parallel_28xx_device, read, write, 0xffffffff)
709664   AM_RANGE(0x600000, 0x61ffff) AM_READWRITE16(c355_obj_ram_r,c355_obj_ram_w,0xffffffff) AM_SHARE("objram")
710665   AM_RANGE(0x620000, 0x620007) AM_READWRITE16(c355_obj_position_r,c355_obj_position_w,0xffffffff)
r31645r31646
735690   AM_RANGE(0x980000, 0x98000f) AM_READWRITE16(c169_roz_bank_r,c169_roz_bank_w,0xffffffff)
736691   AM_RANGE(0xa00000, 0xa007ff) AM_DEVREADWRITE8("eeprom", eeprom_parallel_28xx_device, read, write, 0xffffffff)
737692   AM_RANGE(0xc00000, 0xc0001f) AM_READ(custom_key_r) AM_WRITENOP
738   AM_RANGE(0xf00000, 0xf0001f) AM_READWRITE(namconb_cpureg_r, namconb2_cpureg_w)
693   AM_RANGE(0xf00000, 0xf0001f) AM_READWRITE8(namconb1_cpureg_r, namconb2_cpureg_w, 0xffffffff)
739694ADDRESS_MAP_END
740695
741696WRITE16_MEMBER(namconb1_state::nbmcu_shared_w)
r31645r31646
11221077
11231078static GFXDECODE_START( namconb1 )
11241079   GFXDECODE_ENTRY( NAMCONB1_TILEGFXREGION,    0, tile_layout, 0x1000, 0x10 )
1125   GFXDECODE_ENTRY( NAMCONB1_SPRITEGFXREGION,  0, obj_layout,      0x0000, 0x10 )
1080   GFXDECODE_ENTRY( NAMCONB1_SPRITEGFXREGION,  0, obj_layout,  0x0000, 0x10 )
11261081GFXDECODE_END /* gfxdecodeinfo */
11271082
11281083static GFXDECODE_START( 2 )
11291084   GFXDECODE_ENTRY( NAMCONB1_TILEGFXREGION,    0, tile_layout, 0x1000, 0x08 )
1130   GFXDECODE_ENTRY( NAMCONB1_SPRITEGFXREGION,  0, obj_layout,      0x0000, 0x10 )
1085   GFXDECODE_ENTRY( NAMCONB1_SPRITEGFXREGION,  0, obj_layout,  0x0000, 0x10 )
11311086   GFXDECODE_ENTRY( NAMCONB1_ROTGFXREGION, 0, roz_layout,      0x1800, 0x08 )
11321087GFXDECODE_END /* gfxdecodeinfo2 */
11331088
1089
11341090/***************************************************************/
11351091
1136MACHINE_START_MEMBER(namconb1_state,namconb)
1092MACHINE_RESET_MEMBER(namconb1_state, namconb)
11371093{
1138   m_vblank_irq_active = 0;
1139   m_pos_irq_active = 0;
1140   memset(m_namconb_cpureg, 0, sizeof(m_namconb_cpureg));
1094   m_pos_irq_level = 0;
1095   m_unk_irq_level = 0;
1096   m_vbl_irq_level = 0;
11411097}
11421098
1099
11431100/***************************************************************/
11441101
11451102static MACHINE_CONFIG_START( namconb1, namconb1_state )
11461103   MCFG_CPU_ADD("maincpu", M68EC020, MASTER_CLOCK/2)
11471104   MCFG_CPU_PROGRAM_MAP(namconb1_am)
1148   MCFG_CPU_VBLANK_INT_DRIVER("screen", namconb1_state,  namconb1_interrupt)
11491105
11501106   MCFG_CPU_ADD("mcu", M37702, MASTER_CLOCK/3)
11511107   MCFG_CPU_PROGRAM_MAP(namcoc75_am)
11521108   MCFG_CPU_IO_MAP(namcoc75_io)
1153   MCFG_TIMER_DRIVER_ADD_SCANLINE("mcu_st", namconb1_state, mcu_interrupt, "screen", 0, 1)
11541109
11551110   MCFG_EEPROM_2816_ADD("eeprom")
1156   MCFG_MACHINE_START_OVERRIDE(namconb1_state,namconb)
1111   MCFG_MACHINE_RESET_OVERRIDE(namconb1_state, namconb)
11571112
1113   MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", namconb1_state, namconb_scantimer, "screen", 0, 1)
1114
11581115   MCFG_SCREEN_ADD("screen", RASTER)
11591116   MCFG_SCREEN_REFRESH_RATE(59.7)
11601117   MCFG_SCREEN_SIZE(NAMCONB1_HTOTAL, NAMCONB1_VTOTAL)
r31645r31646
11801137static MACHINE_CONFIG_START( namconb2, namconb1_state )
11811138   MCFG_CPU_ADD("maincpu", M68EC020, MASTER_CLOCK/2)
11821139   MCFG_CPU_PROGRAM_MAP(namconb2_am)
1183   MCFG_CPU_VBLANK_INT_DRIVER("screen", namconb1_state,  namconb2_interrupt)
11841140
11851141   MCFG_CPU_ADD("mcu", M37702, MASTER_CLOCK/3)
11861142   MCFG_CPU_PROGRAM_MAP(namcoc75_am)
11871143   MCFG_CPU_IO_MAP(namcoc75_io)
1188   MCFG_TIMER_DRIVER_ADD_SCANLINE("mcu_st", namconb1_state, mcu_interrupt, "screen", 0, 1)
11891144
11901145   MCFG_EEPROM_2816_ADD("eeprom")
1191   MCFG_MACHINE_START_OVERRIDE(namconb1_state,namconb)
1146   MCFG_MACHINE_RESET_OVERRIDE(namconb1_state, namconb)
11921147
1148   MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", namconb1_state, namconb_scantimer, "screen", 0, 1)
1149
11931150   MCFG_SCREEN_ADD("screen", RASTER)
11941151   MCFG_SCREEN_REFRESH_RATE(59.7)
11951152   MCFG_SCREEN_SIZE(NAMCONB1_HTOTAL, NAMCONB1_VTOTAL)

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