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r31476 Thursday 31st July, 2014 at 03:44:55 UTC by Robbbert
by6803: preliminary work
[src/mame/drivers]by6803.c

trunk/src/mame/drivers/by6803.c
r31475r31476
1/*
1/********************************************************************************************
2
3    PINBALL
24    Bally MPU A084-91786-AH06 (6803)
3*/
45
6There are no dispswitches; everything is done with a numeric keypad located just inside the
7door. The system responds with messages on the display.
58
6#include "emu.h"
9ToDo:
10- Everything
11- Fails PIA test
12- Artwork
13- Operator keypad
14- Various sound boards
15- Inputs, Solenoids vary per game
16- Mechanical
17
18*********************************************************************************************/
19
20
21#include "machine/genpin.h"
722#include "cpu/m6800/m6800.h"
8#include "cpu/m6809/m6809.h"
23//#include "cpu/m6809/m6809.h"
24#include "machine/6821pia.h"
25#include "machine/nvram.h"
26//#include "audio/midway.h"
27//#include "by6803.lh"
928
10class by6803_state : public driver_device
29
30class by6803_state : public genpin_class
1131{
1232public:
1333   by6803_state(const machine_config &mconfig, device_type type, const char *tag)
14      : driver_device(mconfig, type, tag),
15         m_maincpu(*this, "maincpu")
34      : genpin_class(mconfig, type, tag)
35      , m_maincpu(*this, "maincpu")
36      , m_pia0(*this, "pia0")
37      , m_pia1(*this, "pia1")
38      , m_io_test(*this, "TEST")
39      , m_io_x0(*this, "X0")
40      , m_io_x1(*this, "X1")
41      , m_io_x2(*this, "X2")
42      , m_io_x3(*this, "X3")
43      , m_io_x4(*this, "X4")
1644   { }
1745
18protected:
19
20   // devices
21   required_device<cpu_device> m_maincpu;
22
23   // driver_device overrides
46   DECLARE_DRIVER_INIT(by6803);
47   DECLARE_READ8_MEMBER(port1_r);
48   DECLARE_WRITE8_MEMBER(port1_w);
49   DECLARE_READ8_MEMBER(port2_r);
50   DECLARE_WRITE8_MEMBER(port2_w);
51   DECLARE_READ8_MEMBER(pia0_a_r);
52   DECLARE_WRITE8_MEMBER(pia0_a_w);
53   DECLARE_READ8_MEMBER(pia0_b_r);
54   DECLARE_WRITE8_MEMBER(pia0_b_w);
55   DECLARE_READ8_MEMBER(pia1_a_r);
56   DECLARE_WRITE8_MEMBER(pia1_a_w);
57   DECLARE_WRITE8_MEMBER(pia1_b_w);
58   DECLARE_WRITE_LINE_MEMBER(pia0_ca2_w);
59   DECLARE_WRITE_LINE_MEMBER(pia0_cb2_w);
60   DECLARE_WRITE_LINE_MEMBER(pia1_cb2_w);
61   DECLARE_INPUT_CHANGED_MEMBER(activity_test);
62   DECLARE_INPUT_CHANGED_MEMBER(self_test);
63   TIMER_DEVICE_CALLBACK_MEMBER(pia0_timer);
64private:
65   UINT8 m_pia0_a;
66   UINT8 m_pia0_b;
67   UINT8 m_pia1_a;
68   UINT8 m_pia1_b;
69   bool m_pia0_cb2;
70   bool m_pia0_timer;
71   UINT8 m_port1, m_port2;
72   UINT8 m_digit;
73   UINT8 m_segment;
2474   virtual void machine_reset();
25public:
26   DECLARE_DRIVER_INIT(by6803);
75   required_device<m6803_cpu_device> m_maincpu;
76   required_device<pia6821_device> m_pia0;
77   required_device<pia6821_device> m_pia1;
78   required_ioport m_io_test;
79   required_ioport m_io_x0;
80   required_ioport m_io_x1;
81   required_ioport m_io_x2;
82   required_ioport m_io_x3;
83   required_ioport m_io_x4;
2784};
2885
2986
3087static ADDRESS_MAP_START( by6803_map, AS_PROGRAM, 8, by6803_state )
31   AM_RANGE(0x0000, 0xffff) AM_NOP
32   AM_RANGE(0x0000, 0x00ff) AM_RAM
33   AM_RANGE(0x1000, 0x17ff) AM_RAM
88   AM_RANGE(0x0020, 0x0023) AM_DEVREADWRITE("pia0", pia6821_device, read, write)
89   AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE("pia1", pia6821_device, read, write)
90   AM_RANGE(0x1000, 0x17ff) AM_RAM AM_SHARE("nvram") // 6116 ram
3491   AM_RANGE(0x8000, 0xffff) AM_ROM
3592ADDRESS_MAP_END
3693
94static ADDRESS_MAP_START( by6803_io, AS_IO, 8, by6803_state )
95   AM_RANGE(M6801_PORT1, M6801_PORT1) AM_READWRITE(port1_r, port1_w) // P10-P17
96   AM_RANGE(M6801_PORT2, M6801_PORT2) AM_READWRITE(port2_r, port2_w) // P20-P24
97ADDRESS_MAP_END
98
3799static INPUT_PORTS_START( by6803 )
100   PORT_START("TEST")
101   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 ) PORT_NAME("Self Test") PORT_IMPULSE(1) PORT_CHANGED_MEMBER(DEVICE_SELF, by6803_state, self_test, 0)
102   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE2 ) PORT_NAME("Activity") PORT_IMPULSE(1) PORT_CHANGED_MEMBER(DEVICE_SELF, by6803_state, activity_test, 0)
103
104   PORT_START("X0")
105   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_OTHER )
106   PORT_BIT( 0x0a, IP_ACTIVE_HIGH, IPT_UNUSED )
107   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_START2 )
108   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_OTHER )
109   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_START1 )
110   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_TILT )
111   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME("Outhole") PORT_CODE(KEYCODE_X)
112
113   PORT_START("X1")
114   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN2 )
115   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_COIN1 )
116   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_COIN3 )
117   PORT_BIT( 0x38, IP_ACTIVE_HIGH, IPT_UNUSED )
118   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_OTHER )
119   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_TILT1 ) PORT_NAME("Slam Tilt")
120
121   // from here, vary per game
122   PORT_START("X2")
123   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_A)
124   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_S)
125   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_D)
126   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_F)
127   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_G)
128   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_H)
129   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_J)
130   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_K)
131
132   PORT_START("X3")
133   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_Q)
134   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_W)
135   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_E)
136   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_R)
137   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_Y)
138   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_U)
139   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_I)
140   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_O)
141
142   PORT_START("X4")
143   PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_Z)
144   PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_C)
145   PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_V)
146   PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_B)
147   PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_N)
148   PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_M)
149   PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_COMMA)
150   PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_CODE(KEYCODE_STOP)
38151INPUT_PORTS_END
39152
153INPUT_CHANGED_MEMBER( by6803_state::activity_test )
154{
155   if(newval)
156      m_maincpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE);
157}
158
159INPUT_CHANGED_MEMBER( by6803_state::self_test )
160{
161   m_pia0->ca1_w(newval);
162}
163
164READ8_MEMBER( by6803_state::port1_r )
165{
166   return m_port1;
167}
168
169// P10-17 - goes to peripheral bus
170WRITE8_MEMBER( by6803_state::port1_w )
171{
172   m_port1 = data; // sound data = P10,11,12,13,24; P14-17 unknown
173}
174
175READ8_MEMBER( by6803_state::port2_r )
176{
177   return m_port2;
178}
179
180// P20 - input from a phase
181// P21 - output to phase circuit
182// P22 - LED, connects to reset circuit, could be a watchdog
183// P23 - high
184// P24 - sound strobe
185WRITE8_MEMBER( by6803_state::port2_w )
186{
187   m_port2 = data;
188   output_set_value("led0", BIT(data, 2)); // P22 drives LED
189}
190
191// display latch strobes; display blanking
192WRITE_LINE_MEMBER( by6803_state::pia0_ca2_w )
193{
194}
195
196// lamp strobe 1 when high
197WRITE_LINE_MEMBER( by6803_state::pia0_cb2_w )
198{
199}
200
201// sol bank select (0 to enable sol selection)
202WRITE_LINE_MEMBER( by6803_state::pia1_cb2_w )
203{
204}
205
206READ8_MEMBER( by6803_state::pia0_a_r )
207{
208   return m_pia0_a;
209}
210
211// d0=p1,2   d1=p3,4   d2=?   d3=?  (active low, also pia0:ca2 must be low)
212// d4-7 do digit select; d0-4 switch matrix
213// d0-3 lamp rows & d5=0 & pia0:cb2=1 (1st lamp bank)
214// d0-3 lamp rows & d6=0 & pia0:cb2=1 (2nd lamp bank)
215// d0-3 lamp rows & d7=0 & pia0:cb2=1 (3rd lamp bank)
216WRITE8_MEMBER( by6803_state::pia0_a_w )
217{
218   m_pia0_a = data;
219#if 0
220// This is all wrong
221   switch (m_pia0_a)
222   {
223      case 0x10: // wrong
224         output_set_digit_value(m_digit, m_segment);
225         break;
226      case 0x1d:
227         output_set_digit_value(8+m_digit, m_segment);
228         break;
229      case 0x1b:
230         output_set_digit_value(16+m_digit, m_segment);
231         break;
232      case 0x07:
233         output_set_digit_value(24+m_digit, m_segment);
234         break;
235      case 0x0f:
236         output_set_digit_value(32+m_digit, m_segment);
237         break;
238      default:
239         break;
240   }
241#endif
242}
243
244// switch returns
245READ8_MEMBER( by6803_state::pia0_b_r )
246{
247   UINT8 data = 0;
248
249   if (BIT(m_pia0_a, 0))
250      data |= m_io_x0->read();
251
252   if (BIT(m_pia0_a, 1))
253      data |= m_io_x1->read();
254
255   if (BIT(m_pia0_a, 2))
256      data |= m_io_x2->read();
257
258   if (BIT(m_pia0_a, 3))
259      data |= m_io_x3->read();
260
261   if (BIT(m_pia0_a, 4))
262      data |= m_io_x4->read();
263
264   return data;
265}
266
267WRITE8_MEMBER( by6803_state::pia0_b_w )
268{
269   m_pia0_b = data;
270}
271
272READ8_MEMBER( by6803_state::pia1_a_r )
273{
274   return m_pia1_a;
275}
276
277// segment data; d0 & pia0:ca2 = comma; passed to digits when PA0? is high (assume they mean pia0:pa0)
278WRITE8_MEMBER( by6803_state::pia1_a_w )
279{
280   m_pia1_a = data;
281   m_segment = data >> 1;
282}
283
284// solenoids, activated when pia1:cb2 is low
285WRITE8_MEMBER( by6803_state::pia1_b_w )
286{
287   m_pia1_b = data;
288   switch (data & 15)
289   {
290      case 0x0: //
291         //m_samples->start(0, 3);
292         break;
293      case 0x1: // chime 10
294         //m_samples->start(1, 1);
295         break;
296      case 0x2: // chime 100
297         //m_samples->start(2, 2);
298         break;
299      case 0x3: // chime 1000
300         //m_samples->start(3, 3);
301         break;
302      case 0x4: // chime 10000
303         //m_samples->start(0, 4);
304         break;
305      case 0x5: // knocker
306         //m_samples->start(0, 6);
307         break;
308      case 0x6: // outhole
309         //m_samples->start(0, 5);
310         break;
311      // from here, vary per game
312      case 0x7:
313      case 0x8:
314      case 0x9:
315         //m_samples->start(0, 5);
316         break;
317      case 0xa:
318         //m_samples->start(0, 5);
319         break;
320      case 0xb:
321         //m_samples->start(0, 0);
322         break;
323      case 0xc:
324         //m_samples->start(0, 5);
325         break;
326      case 0xd:
327         //m_samples->start(0, 0);
328         break;
329      case 0xe:
330         //m_samples->start(0, 5);
331         break;
332      case 0xf: // not used
333         break;
334   }
335}
336
40337void by6803_state::machine_reset()
41338{
339   m_pia0_a = 0;
340   m_pia0_b = 0;
341   m_pia0_cb2 = 0;
342   m_pia1_a = 0;
343   m_pia1_b = 0;
344   m_port2 = 2+8;
42345}
43346
44347DRIVER_INIT_MEMBER(by6803_state,by6803)
45348{
46349}
47350
351// zero-cross detection
352TIMER_DEVICE_CALLBACK_MEMBER( by6803_state::pia0_timer )
353{
354   // Phase A
355   if ((m_pia0_timer) && (!BIT(m_port2, 1)))
356      m_port2 |= 1; // set P20 high
357   else
358      m_port2 &= ~1;
359
360   // Is this the correct thing to do? No other driver uses this line.
361   // What polarity is it? I'm assuming that irq asserted = 1.
362   m_maincpu->set_input_line(M6801_TIN_LINE, BIT(m_port2, 0));
363
364   m_pia0_timer ^= 1;
365
366   // Phase B
367   m_pia0->cb1_w(m_pia0_timer);
368}
369
48370static MACHINE_CONFIG_START( by6803, by6803_state )
49371   /* basic machine hardware */
50   MCFG_CPU_ADD("maincpu", M6803, 1000000)
372   MCFG_CPU_ADD("maincpu", M6803, XTAL_3_579545MHz)
51373   MCFG_CPU_PROGRAM_MAP(by6803_map)
374   MCFG_CPU_IO_MAP(by6803_io)
375
376   MCFG_NVRAM_ADD_0FILL("nvram")
377
378   /* Video */
379   //MCFG_DEFAULT_LAYOUT(layout_by6803)
380
381   /* Sound */
382   MCFG_FRAGMENT_ADD( genpin_audio )
383
384   /* Devices */
385   MCFG_DEVICE_ADD("pia0", PIA6821, 0)
386   MCFG_PIA_READPA_HANDLER(READ8(by6803_state, pia0_a_r))
387   MCFG_PIA_WRITEPA_HANDLER(WRITE8(by6803_state, pia0_a_w))
388   MCFG_PIA_READPB_HANDLER(READ8(by6803_state, pia0_b_r))
389   MCFG_PIA_WRITEPB_HANDLER(WRITE8(by6803_state, pia0_b_w))
390   MCFG_PIA_CA2_HANDLER(WRITELINE(by6803_state, pia0_ca2_w))
391   MCFG_PIA_CB2_HANDLER(WRITELINE(by6803_state, pia0_cb2_w))
392   MCFG_PIA_IRQA_HANDLER(DEVWRITELINE("maincpu", m6803_cpu_device, irq_line))
393   MCFG_PIA_IRQB_HANDLER(DEVWRITELINE("maincpu", m6803_cpu_device, irq_line))
394   MCFG_TIMER_DRIVER_ADD_PERIODIC("timer_z", by6803_state, pia0_timer, attotime::from_hz(120)) // mains freq*2
395
396   MCFG_DEVICE_ADD("pia1", PIA6821, 0)
397   MCFG_PIA_READPA_HANDLER(READ8(by6803_state, pia1_a_r))
398   MCFG_PIA_WRITEPA_HANDLER(WRITE8(by6803_state, pia1_a_w))
399   MCFG_PIA_WRITEPB_HANDLER(WRITE8(by6803_state, pia1_b_w))
400   MCFG_PIA_CB2_HANDLER(WRITELINE(by6803_state, pia1_cb2_w))
401
402   //MCFG_SPEAKER_STANDARD_MONO("mono")
403   //MCFG_MIDWAY_TURBO_CHIP_SQUEAK_ADD("tcs") // Cheap Squeak Turbo
404   //MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
52405MACHINE_CONFIG_END
53406
407
54408/*-----------------------------------------------------------
55409/ Atlantis
56410/-----------------------------------------------------------*/

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