trunk/src/mame/layout/mpu5.lay
| r0 | r31431 | |
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trunk/src/mame/drivers/mpu5hw.c
| r31430 | r31431 | |
| 17 | 17 | |
| 18 | 18 | -- Much of the communication is done via a 68681 DUART. |
| 19 | 19 | |
| 20 | -- The ASIC acts as the main I/O control, including an interface to a Z89321 DSP and a 16bit DAC. |
| 21 | |
| 20 | 22 | -- Help wanted, the MFME sources (which are based on MAME anyway) should be of some help here, if somebody |
| 21 | 23 | in the FM emu community wants to adopt this driver they're welcome to it. |
| 22 | 24 | |
| r31430 | r31431 | |
| 39 | 41 | |
| 40 | 42 | |
| 41 | 43 | #include "emu.h" |
| 44 | |
| 45 | #include "machine/sec.h" |
| 46 | #include "mpu5.lh" |
| 47 | |
| 42 | 48 | #include "machine/68340.h" |
| 43 | 49 | |
| 44 | 50 | class mpu5_state : public driver_device |
| r31430 | r31431 | |
| 50 | 56 | { } |
| 51 | 57 | UINT32* m_cpuregion; |
| 52 | 58 | UINT32* m_mainram; |
| 59 | SEC sec; |
| 53 | 60 | |
| 61 | UINT8 m_led_strobe_temp; |
| 62 | UINT8 m_led_strobe; |
| 63 | UINT8 m_pic_clk; |
| 64 | bool m_pic_transfer_in_progress; |
| 65 | UINT8 m_pic_bit1; |
| 66 | UINT8 m_pic_data; |
| 67 | UINT8 m_pic_clocked_bits; |
| 68 | UINT8 m_pic_stored_input; |
| 69 | UINT8 m_pic_output_bit; |
| 70 | UINT8 m_input_strobe; |
| 71 | |
| 54 | 72 | DECLARE_READ32_MEMBER(mpu5_mem_r); |
| 55 | 73 | DECLARE_WRITE32_MEMBER(mpu5_mem_w); |
| 56 | 74 | |
| r31430 | r31431 | |
| 59 | 77 | DECLARE_WRITE32_MEMBER(asic_w32); |
| 60 | 78 | DECLARE_WRITE8_MEMBER(asic_w8); |
| 61 | 79 | |
| 80 | DECLARE_READ32_MEMBER(pic_r); |
| 81 | DECLARE_WRITE32_MEMBER(pic_w); |
| 82 | |
| 62 | 83 | protected: |
| 63 | 84 | |
| 64 | 85 | // devices |
| r31430 | r31431 | |
| 68 | 89 | |
| 69 | 90 | READ8_MEMBER(mpu5_state::asic_r8) |
| 70 | 91 | { |
| 71 | | int pc = space.device().safe_pc(); |
| 72 | | logerror("%08x maincpu read from ASIC - offset %01x\n", pc, offset); |
| 73 | | return 0; |
| 92 | switch (offset) |
| 93 | { |
| 94 | case 0x01: |
| 95 | { |
| 96 | return 0x99; |
| 97 | } |
| 98 | |
| 99 | case 0x02: |
| 100 | { |
| 101 | //send init and ready for now - need to work on full DSP |
| 102 | return 0x85; |
| 103 | } |
| 104 | |
| 105 | case 0x0b: |
| 106 | { |
| 107 | return 0; |
| 108 | } |
| 109 | default: |
| 110 | { |
| 111 | int pc = space.device().safe_pc(); |
| 112 | logerror("%08x maincpu read from ASIC - offset %01x\n", pc, offset); |
| 113 | return 0; |
| 114 | } |
| 115 | } |
| 74 | 116 | } |
| 75 | 117 | |
| 76 | 118 | |
| r31430 | r31431 | |
| 93 | 135 | switch ( cs ) |
| 94 | 136 | { |
| 95 | 137 | case 2: |
| 96 | | if ((addr & 0xf0) == 0xf0) |
| 138 | { |
| 139 | switch (addr & 0xf0) |
| 97 | 140 | { |
| 98 | | return asic_r32(space, offset&3,mem_mask); |
| 99 | | } |
| 100 | | else |
| 101 | | { |
| 141 | case 0xd0: |
| 142 | { |
| 143 | logerror("%08x PIC read\n", pc); |
| 144 | break; |
| 145 | } |
| 146 | case 0xe0: |
| 147 | { |
| 148 | logerror("%08x DUART read\n", pc); |
| 149 | break; |
| 150 | } |
| 151 | |
| 152 | case 0xf0: |
| 153 | { |
| 154 | return asic_r32(space, offset&3,mem_mask); |
| 155 | break; |
| 156 | } |
| 157 | |
| 158 | default: |
| 102 | 159 | logerror("%08x maincpu read access offset %08x mem_mask %08x cs %d\n", pc, offset*4, mem_mask, cs); |
| 160 | break; |
| 103 | 161 | } |
| 104 | | break; |
| 105 | | |
| 162 | } |
| 163 | break; |
| 164 | |
| 165 | case 3: |
| 106 | 166 | case 4: |
| 107 | 167 | offset &=0x3fff; |
| 108 | 168 | return (m_mainram[offset]); |
| r31430 | r31431 | |
| 119 | 179 | return 0x0000; |
| 120 | 180 | } |
| 121 | 181 | |
| 122 | | |
| 182 | // Each board is fitted with an ASIC that does most of the heavy lifting, including sound playback. |
| 123 | 183 | WRITE8_MEMBER(mpu5_state::asic_w8) |
| 124 | 184 | { |
| 125 | | int pc = space.device().safe_pc(); |
| 126 | | logerror("%08x maincpu write to ASIC - offset %01x data %02x\n", pc, offset, data); |
| 185 | switch (offset) |
| 186 | { |
| 187 | case 0x03: |
| 188 | { |
| 189 | if (m_led_strobe_temp != data) |
| 190 | { |
| 191 | m_led_strobe_temp = data; |
| 192 | |
| 193 | switch (m_led_strobe_temp) |
| 194 | { |
| 195 | case 0x00: |
| 196 | m_led_strobe = 0; |
| 197 | break; |
| 198 | case 0x01: |
| 199 | m_led_strobe = 1; |
| 200 | break; |
| 201 | case 0x02: |
| 202 | m_led_strobe = 2; |
| 203 | break; |
| 204 | case 0x04: |
| 205 | m_led_strobe = 3; |
| 206 | break; |
| 207 | case 0x08: |
| 208 | m_led_strobe = 4; |
| 209 | break; |
| 210 | case 0x10: |
| 211 | m_led_strobe = 5; |
| 212 | break; |
| 213 | case 0x20: |
| 214 | m_led_strobe = 6; |
| 215 | break; |
| 216 | case 0x40: |
| 217 | m_led_strobe = 7; |
| 218 | break; |
| 219 | case 0x80: |
| 220 | m_led_strobe = 8; |
| 221 | break; |
| 222 | } |
| 223 | } |
| 224 | break; |
| 225 | } |
| 226 | |
| 227 | case 0x09: |
| 228 | { |
| 229 | //Assume SEC fitted for now |
| 230 | sec.write_data_line(~data&0x01); |
| 231 | sec.write_clock_line(~data&0x02); |
| 232 | sec.write_cs_line(~data&0x04); |
| 233 | } |
| 234 | case 0x0b: |
| 235 | { |
| 236 | output_set_value("statuslamp1", ((data&0x10) != 0)); |
| 237 | |
| 238 | output_set_value("statuslamp2", ((data&0x20) != 0)); |
| 239 | |
| 240 | if (data & 0x40) |
| 241 | { |
| 242 | // m_dsp_pin =1; |
| 243 | } |
| 244 | } |
| 245 | break; |
| 246 | default: |
| 247 | { |
| 248 | int pc = space.device().safe_pc(); |
| 249 | logerror("%08x maincpu write to ASIC - offset %01x data %02x\n", pc, offset, data); |
| 250 | } |
| 251 | } |
| 127 | 252 | } |
| 128 | 253 | |
| 129 | 254 | |
| r31430 | r31431 | |
| 135 | 260 | if (mem_mask&0x000000ff) asic_w8(space,(offset*4)+3, (data>>0) &0xff); |
| 136 | 261 | } |
| 137 | 262 | |
| 263 | |
| 264 | READ32_MEMBER(mpu5_state::pic_r) |
| 265 | { |
| 266 | int pc = space.device().safe_pc(); |
| 267 | logerror("%08x maincpu read from PIC - offset %01x\n", pc, offset); |
| 268 | return m_pic_output_bit; |
| 269 | } |
| 270 | |
| 271 | WRITE32_MEMBER(mpu5_state::pic_w) |
| 272 | { |
| 273 | switch (offset) |
| 274 | { |
| 275 | case 0x04: |
| 276 | { |
| 277 | if (m_pic_clk) |
| 278 | { |
| 279 | m_pic_transfer_in_progress = true; |
| 280 | } |
| 281 | m_pic_bit1 = (data & 0x01); |
| 282 | break; |
| 283 | } |
| 284 | |
| 285 | case 0x06: |
| 286 | case 0x07: |
| 287 | { |
| 288 | if ( (!data) && (m_pic_transfer_in_progress) && (m_pic_clk)) |
| 289 | { |
| 290 | //clock in the stored bit (rudimentary protection here) |
| 291 | m_pic_data = (m_pic_data << 1); |
| 292 | m_pic_data |= m_pic_bit1; |
| 293 | m_pic_stored_input <<= 1; |
| 294 | m_pic_clocked_bits ++; |
| 295 | |
| 296 | if (m_pic_clocked_bits >=8) |
| 297 | { |
| 298 | m_pic_data =0; |
| 299 | m_pic_clocked_bits =0; |
| 300 | |
| 301 | if (m_input_strobe <4) |
| 302 | { |
| 303 | m_input_strobe +=1; |
| 304 | } |
| 305 | |
| 306 | } |
| 307 | } |
| 308 | else |
| 309 | { |
| 310 | m_pic_output_bit = BIT(m_pic_stored_input,7); |
| 311 | } |
| 312 | m_pic_transfer_in_progress = false; |
| 313 | m_pic_clk = (data != 0); |
| 314 | break; |
| 315 | } |
| 316 | default: |
| 317 | { |
| 318 | int pc = space.device().safe_pc(); |
| 319 | logerror("%08x maincpu write to PIC - offset %01x data %02x\n", pc, offset, data); |
| 320 | break; |
| 321 | } |
| 322 | } |
| 323 | |
| 324 | } |
| 325 | |
| 138 | 326 | WRITE32_MEMBER(mpu5_state::mpu5_mem_w) |
| 139 | 327 | { |
| 140 | 328 | int pc = space.device().safe_pc(); |
| r31430 | r31431 | |
| 144 | 332 | switch ( cs ) |
| 145 | 333 | { |
| 146 | 334 | case 2: |
| 147 | | if ((addr & 0xf0) == 0xf0) |
| 335 | { |
| 336 | switch (addr & 0xf0) |
| 148 | 337 | { |
| 149 | | asic_w32(space, offset&3,data,mem_mask); |
| 338 | case 0xd0: |
| 339 | { |
| 340 | pic_w(space, (addr& 0x0f),data,mem_mask); |
| 341 | break; |
| 342 | } |
| 343 | case 0xe0: |
| 344 | { |
| 345 | logerror("%08x DUART write\n", pc); |
| 346 | break; |
| 347 | } |
| 348 | |
| 349 | case 0xf0: |
| 350 | { |
| 351 | asic_w32(space, offset&3,data,mem_mask); |
| 352 | break; |
| 353 | } |
| 354 | |
| 355 | default: |
| 356 | logerror("%08x maincpu write access offset %08x data %08x mem_mask %08x cs %d\n", pc, offset*4, data, mem_mask, cs); |
| 357 | break; |
| 150 | 358 | } |
| 151 | | else |
| 152 | | { |
| 153 | | logerror("%08x maincpu write access offset %08x data %08x mem_mask %08x cs %d\n", pc, offset*4, data, mem_mask, cs); |
| 154 | | } |
| 155 | | break; |
| 359 | } |
| 360 | break; |
| 156 | 361 | |
| 157 | | |
| 362 | case 3: |
| 158 | 363 | case 4: |
| 159 | 364 | offset &=0x3fff; |
| 160 | 365 | COMBINE_DATA(&m_mainram[offset]); |
| r31430 | r31431 | |
| 181 | 386 | { |
| 182 | 387 | m_cpuregion = (UINT32*)memregion( "maincpu" )->base(); |
| 183 | 388 | m_mainram = (UINT32*)auto_alloc_array_clear(machine(), UINT32, 0x10000); |
| 184 | | |
| 389 | m_pic_output_bit =0; |
| 185 | 390 | } |
| 186 | 391 | |
| 187 | 392 | |
| r31430 | r31431 | |
| 189 | 394 | MCFG_CPU_ADD("maincpu", M68340, 16000000) // ? |
| 190 | 395 | MCFG_CPU_PROGRAM_MAP(mpu5_map) |
| 191 | 396 | |
| 397 | MCFG_DEFAULT_LAYOUT(layout_mpu5) |
| 192 | 398 | |
| 193 | 399 | MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") |
| 194 | 400 | /* unknown sound */ |
trunk/src/mame/drivers/aces1.c
| r31430 | r31431 | |
| 9 | 9 | ram at 0x8000-0x87ff |
| 10 | 10 | lots of reads from 0xe000 at the start |
| 11 | 11 | |
| 12 | | JPM style Reel MCU? |
| 12 | JPM style Reel MCU? Certainly reel data seems to be muxed together in aweird way |
| 13 | 13 | |
| 14 | 14 | Hardware overview |
| 15 | 15 | - Z80 |
| r31430 | r31431 | |
| 27 | 27 | #include "cpu/z80/z80.h" |
| 28 | 28 | #include "sound/ay8910.h" |
| 29 | 29 | #include "machine/i8255.h" |
| 30 | #include "machine/steppers.h" |
| 30 | 31 | #include "video/awpvid.h" |
| 31 | 32 | #include "aces1.lh" |
| 32 | 33 | |
| r31430 | r31431 | |
| 36 | 37 | public: |
| 37 | 38 | aces1_state(const machine_config &mconfig, device_type type, const char *tag) |
| 38 | 39 | : driver_device(mconfig, type, tag), |
| 39 | | m_maincpu(*this, "maincpu") |
| 40 | m_maincpu(*this, "maincpu"), |
| 41 | m_io1_port(*this, "IO1"), |
| 42 | m_io2_port(*this, "IO2"), |
| 43 | m_io3_port(*this, "IO3"), |
| 44 | m_io4_port(*this, "IO4"), |
| 45 | m_io5_port(*this, "IO5"), |
| 46 | m_io6_port(*this, "IO6"), |
| 47 | m_io7_port(*this, "IO7"), |
| 48 | m_io8_port(*this, "IO8") |
| 40 | 49 | { } |
| 41 | 50 | int m_input_strobe; |
| 42 | 51 | int m_lamp_strobe; |
| 43 | 52 | int m_led_strobe; |
| 53 | int m_reel_clock[4]; |
| 54 | int m_reel_phase[4]; |
| 55 | int m_reel_count[4]; |
| 44 | 56 | |
| 45 | 57 | DECLARE_READ8_MEMBER( aces1_unk_r ) |
| 46 | 58 | { |
| r31430 | r31431 | |
| 122 | 134 | |
| 123 | 135 | DECLARE_WRITE8_MEMBER(ic25_write_c) |
| 124 | 136 | { |
| 125 | | // printf("reels, extender strobe %02x\n", data); |
| 137 | //There needs to be some way of connecting these values to stepper coils, or doing the MCU properly |
| 138 | // We should be able to see an enable clock, a sense and a full/half step selector, we don't have the half step visible it seems. |
| 139 | |
| 140 | //3 1 16 14 |
| 141 | int phases[] = {0x05,0x01,0x09,0x08,0x0a,0x02,0x06,0x04,}; |
| 142 | for (int reel=0; reel <4; reel++) |
| 143 | { |
| 144 | int clock = (data & (1<<reel)); |
| 145 | if (m_reel_clock[reel] != clock) |
| 146 | { |
| 147 | if (clock != 0) |
| 148 | { |
| 149 | int sense = ((data & (4 + (1<<reel))) ? -2:2); |
| 150 | m_reel_phase[reel] = ((m_reel_phase[reel] + sense + 8) % 8); |
| 151 | stepper_update(reel, phases[m_reel_phase[reel]]); |
| 152 | m_reel_clock[reel] = clock; |
| 153 | if ( m_reel_phase[reel] % 4 ==0) |
| 154 | { |
| 155 | m_reel_count[reel]=1; |
| 156 | } |
| 157 | else |
| 158 | { |
| 159 | m_reel_count[reel]=0; |
| 160 | } |
| 161 | logerror("Reel %x Enable %x Sense %i Phase %x Data %x\n",reel, clock, sense, m_reel_phase[reel],phases[m_reel_phase[reel]] ); |
| 162 | } |
| 163 | else |
| 164 | { |
| 165 | logerror("Reel %x Enable %x \n",reel, clock ); |
| 166 | } |
| 167 | } |
| 168 | // logerror("Reel %x Enable %x Sense %i \n",reel, (data & (1<<reel)), (data & (4 + (1<<reel))) ? 1:-1 ); |
| 169 | } |
| 170 | |
| 171 | |
| 172 | // printf("reels, extender strobe %02x\n", data); |
| 126 | 173 | } |
| 127 | 174 | |
| 128 | 175 | DECLARE_READ8_MEMBER( ic37_read_a ) |
| 129 | 176 | { |
| 130 | | return 0xff; |
| 177 | //Should be coins and doors |
| 178 | return ioport("COINS")->read(); |
| 131 | 179 | } |
| 132 | 180 | |
| 133 | 181 | DECLARE_READ8_MEMBER( ic37_read_b ) |
| 134 | 182 | { |
| 135 | | return 0xff; |
| 183 | ioport_port * portnames[] = { m_io1_port, m_io2_port, m_io3_port, m_io4_port, m_io5_port, m_io6_port, m_io7_port, m_io8_port,m_io1_port, m_io2_port, m_io3_port, m_io4_port, m_io5_port, m_io6_port, m_io7_port, m_io8_port }; |
| 184 | |
| 185 | return (portnames[m_input_strobe])->read(); |
| 136 | 186 | } |
| 137 | 187 | |
| 138 | 188 | DECLARE_READ8_MEMBER( ic37_read_c ) |
| 139 | 189 | { |
| 140 | | return 0xff; |
| 190 | int pattern =0; |
| 191 | int action =0; |
| 192 | for (int reel = 0; reel < 4; reel++) |
| 193 | { |
| 194 | if (stepper_optic_state(reel)) pattern |= 1<<reel; |
| 195 | if (m_reel_count[reel]) action |= 1<<reel; |
| 196 | } |
| 197 | |
| 198 | return ((pattern << 4) | action); |
| 141 | 199 | } |
| 142 | 200 | |
| 143 | 201 | // devices |
| 144 | 202 | required_device<cpu_device> m_maincpu; |
| 203 | required_ioport m_io1_port; |
| 204 | required_ioport m_io2_port; |
| 205 | required_ioport m_io3_port; |
| 206 | required_ioport m_io4_port; |
| 207 | required_ioport m_io5_port; |
| 208 | required_ioport m_io6_port; |
| 209 | required_ioport m_io7_port; |
| 210 | required_ioport m_io8_port; |
| 145 | 211 | |
| 146 | 212 | DECLARE_DRIVER_INIT(aces1); |
| 147 | 213 | virtual void machine_start(); |
| r31430 | r31431 | |
| 170 | 236 | |
| 171 | 237 | void aces1_state::machine_start() |
| 172 | 238 | { |
| 239 | stepper_config(machine(), 0, &starpoint_interface_48step); |
| 240 | stepper_config(machine(), 1, &starpoint_interface_48step); |
| 241 | stepper_config(machine(), 2, &starpoint_interface_48step); |
| 242 | stepper_config(machine(), 3, &starpoint_interface_48step); |
| 243 | |
| 244 | for (int reel=0; reel <4; reel++) |
| 245 | { |
| 246 | m_reel_clock[reel] =0; |
| 247 | m_reel_phase[reel] =0; |
| 248 | } |
| 173 | 249 | m_aces1_irq_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(aces1_state::m_aces1_irq_timer_callback),this), 0); |
| 174 | 250 | m_aces1_nmi_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(aces1_state::m_aces1_nmi_timer_callback),this), 0); |
| 175 | 251 | } |
| r31430 | r31431 | |
| 198 | 274 | |
| 199 | 275 | |
| 200 | 276 | static INPUT_PORTS_START( aces1 ) |
| 277 | PORT_START("COINS") |
| 278 | PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_NAME("10p") |
| 279 | PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_NAME("20p") |
| 280 | PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN3 ) PORT_NAME("50p") |
| 281 | PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN4 ) PORT_NAME("100p") |
| 282 | PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 283 | PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 284 | PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 285 | PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 286 | |
| 287 | PORT_START("IO1") |
| 288 | PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 289 | PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 290 | PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 291 | PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 292 | PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 293 | PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 294 | PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 295 | PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 296 | |
| 297 | PORT_START("IO2") |
| 298 | PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 299 | PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 300 | PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 301 | PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 302 | PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 303 | PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 304 | PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 305 | PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 306 | |
| 307 | PORT_START("IO3") |
| 308 | PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 309 | PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 310 | PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 311 | PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 312 | PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 313 | PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 314 | PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 315 | PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 316 | |
| 317 | PORT_START("IO4") |
| 318 | PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 319 | PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 320 | PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 321 | PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 322 | PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 323 | PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 324 | PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 325 | PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 326 | |
| 327 | PORT_START("IO5") |
| 328 | PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 329 | PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 330 | PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 331 | PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 332 | PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 333 | PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 334 | PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 335 | PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 336 | |
| 337 | PORT_START("IO6") |
| 338 | PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 339 | PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 340 | PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 341 | PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 342 | PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 343 | PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 344 | PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 345 | PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 346 | |
| 347 | PORT_START("IO7") |
| 348 | PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 349 | PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 350 | PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 351 | PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 352 | PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 353 | PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 354 | PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 355 | PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 356 | |
| 357 | PORT_START("IO8") |
| 358 | PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 359 | PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 360 | PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 361 | PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 362 | PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 363 | PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 364 | PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 365 | PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED ) |
| 366 | |
| 201 | 367 | PORT_START("DSWA") |
| 202 | 368 | PORT_DIPNAME( 0x01, 0x01, "DSWA" ) |
| 203 | 369 | PORT_DIPSETTING( 0x01, DEF_STR( Off ) ) |