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r31297 Wednesday 16th July, 2014 at 22:55:49 UTC by hap
rewrote most of tms7000, fixing a few issues and adding preliminary support for TMS70x1/2 family

[src/emu/cpu]	cpu.mak
[src/emu/cpu/tms7000]	7000dasm.c tms7000.c tms7000.h tms70op.inc tms70tb.inc
[src/mess/drivers]	cc40.c exelv.c

trunk/src/emu/cpu/tms7000/tms70tb.inc

r31296	r31297
1		/*****************************************************************************
2		*
3		*   tms70tb.inc (function table)
4		*   Portable TMS7000 emulator (Texas Instruments 7000)
5		*
6		*   Copyright tim lindner, all rights reserved.
7		*
8		*   - This source code is released as freeware for non-commercial purposes.
9		*   - You are free to use and redistribute this code in modified or
10		*     unmodified form, provided you list me in the credits.
11		*   - If you modify this source code, you must add a notice to each modified
12		*     source file that it has been changed.  If you're a nice person, you
13		*     will clearly mark each change too.  :)
14		*   - If you wish to use this for commercial purposes, please contact me at
15		*     tlindner@macmess.org
16		*   - This entire notice must remain in the source code.
17		*
18		*****************************************************************************/
19
20		const tms7000_device::opcode_func tms7000_device::s_opfn[0x100] = {
21		/*          0xX0,   0xX1,     0xX2,    0xX3,    0xX4,    0xX5,    0xX6,    0xX7,
22		0xX8,   0xX9,     0xXA,    0xXB,    0xXC,    0xXD,    0xXE,    0xXF   */
23
24		/* 0x0X */  &tms7000_device::nop,     &tms7000_device::idle,    &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::eint,    &tms7000_device::dint,    &tms7000_device::setc,
25		&tms7000_device::pop_st,  &tms7000_device::stsp,    &tms7000_device::rets,    &tms7000_device::reti,    &tms7000_device::illegal, &tms7000_device::ldsp,    &tms7000_device::push_st, &tms7000_device::illegal,
26
27		/* 0x1X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_r2a, &tms7000_device::and_r2a, &tms7000_device::or_r2a,  &tms7000_device::xor_r2a, &tms7000_device::btjo_r2a,&tms7000_device::btjz_r2a,
28		&tms7000_device::add_r2a, &tms7000_device::adc_r2a, &tms7000_device::sub_ra,  &tms7000_device::sbb_ra,  &tms7000_device::mpy_ra,  &tms7000_device::cmp_ra,  &tms7000_device::dac_r2a, &tms7000_device::dsb_r2a,
29
30		/* 0x2X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_i2a, &tms7000_device::and_i2a, &tms7000_device::or_i2a,  &tms7000_device::xor_i2a, &tms7000_device::btjo_i2a,&tms7000_device::btjz_i2a,
31		&tms7000_device::add_i2a, &tms7000_device::adc_i2a, &tms7000_device::sub_ia,  &tms7000_device::sbb_ia,  &tms7000_device::mpy_ia,  &tms7000_device::cmp_ia,  &tms7000_device::dac_i2a, &tms7000_device::dsb_i2a,
32
33		/* 0x3X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_r2b, &tms7000_device::and_r2b, &tms7000_device::or_r2b,  &tms7000_device::xor_r2b, &tms7000_device::btjo_r2b,&tms7000_device::btjz_r2b,
34		&tms7000_device::add_r2b, &tms7000_device::adc_r2b, &tms7000_device::sub_rb,  &tms7000_device::sbb_rb,  &tms7000_device::mpy_rb,  &tms7000_device::cmp_rb,  &tms7000_device::dac_r2b, &tms7000_device::dsb_r2b,
35
36		/* 0x4X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_r2r, &tms7000_device::and_r2r, &tms7000_device::or_r2r,  &tms7000_device::xor_r2r, &tms7000_device::btjo_r2r,&tms7000_device::btjz_r2r,
37		&tms7000_device::add_r2r, &tms7000_device::adc_r2r, &tms7000_device::sub_rr,  &tms7000_device::sbb_rr,  &tms7000_device::mpy_rr,  &tms7000_device::cmp_rr,  &tms7000_device::dac_r2r, &tms7000_device::dsb_r2r,
38
39		/* 0x5X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_i2b, &tms7000_device::and_i2b, &tms7000_device::or_i2b,  &tms7000_device::xor_i2b, &tms7000_device::btjo_i2b,&tms7000_device::btjz_i2b,
40		&tms7000_device::add_i2b, &tms7000_device::adc_i2b, &tms7000_device::sub_ib,  &tms7000_device::sbb_ib,  &tms7000_device::mpy_ib,  &tms7000_device::cmp_ib,  &tms7000_device::dac_i2b, &tms7000_device::dsb_i2b,
41
42		/* 0x6X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_b2a, &tms7000_device::and_b2a, &tms7000_device::or_b2a,  &tms7000_device::xor_b2a, &tms7000_device::btjo_b2a,&tms7000_device::btjz_b2a,
43		&tms7000_device::add_b2a, &tms7000_device::adc_b2a, &tms7000_device::sub_ba,  &tms7000_device::sbb_ba,  &tms7000_device::mpy_ba,  &tms7000_device::cmp_ba,  &tms7000_device::dac_b2a, &tms7000_device::dsb_b2a,
44
45		/* 0x7X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_i2r, &tms7000_device::and_i2r, &tms7000_device::or_i2r,  &tms7000_device::xor_i2r, &tms7000_device::btjo_i2r,&tms7000_device::btjz_i2r,
46		&tms7000_device::add_i2r, &tms7000_device::adc_i2r, &tms7000_device::sub_ir,  &tms7000_device::sbb_ir,  &tms7000_device::mpy_ir,  &tms7000_device::cmp_ir,  &tms7000_device::dac_i2r, &tms7000_device::dsb_i2r,
47
48		/* 0x8X */  &tms7000_device::movp_p2a,&tms7000_device::illegal, &tms7000_device::movp_a2p,&tms7000_device::andp_a2p,&tms7000_device::orp_a2p, &tms7000_device::xorp_a2p,&tms7000_device::btjop_ap,&tms7000_device::btjzp_ap,
49		&tms7000_device::movd_imm,&tms7000_device::illegal, &tms7000_device::lda_dir, &tms7000_device::sta_dir, &tms7000_device::br_dir,  &tms7000_device::cmpa_dir,&tms7000_device::call_dir,&tms7000_device::illegal,
50
51		/* 0x9X */  &tms7000_device::illegal, &tms7000_device::movp_p2b,&tms7000_device::movp_b2p,&tms7000_device::andp_b2p,&tms7000_device::orp_b2p, &tms7000_device::xorp_b2p,&tms7000_device::btjop_bp,&tms7000_device::btjzp_bp,
52		&tms7000_device::movd_r,  &tms7000_device::illegal, &tms7000_device::lda_ind, &tms7000_device::sta_ind, &tms7000_device::br_ind,  &tms7000_device::cmpa_ind,&tms7000_device::call_ind,&tms7000_device::illegal,
53
54		/* 0xAX */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::movp_i2p,&tms7000_device::andp_i2p,&tms7000_device::orp_i2p, &tms7000_device::xorp_i2p,&tms7000_device::btjop_ip,&tms7000_device::btjzp_ip,
55		&tms7000_device::movd_inx,&tms7000_device::illegal, &tms7000_device::lda_inx, &tms7000_device::sta_inx, &tms7000_device::br_inx,  &tms7000_device::cmpa_inx,&tms7000_device::call_inx,&tms7000_device::illegal,
56
57		/* 0xBX */  &tms7000_device::clrc,    &tms7000_device::illegal, &tms7000_device::dec_a,   &tms7000_device::inc_a,   &tms7000_device::inv_a,   &tms7000_device::clr_a,   &tms7000_device::xchb_a,  &tms7000_device::swap_a,
58		&tms7000_device::push_a,  &tms7000_device::pop_a,   &tms7000_device::djnz_a,  &tms7000_device::decd_a,  &tms7000_device::rr_a,    &tms7000_device::rrc_a,   &tms7000_device::rl_a,    &tms7000_device::rlc_a,
59
60		/* 0xCX */  &tms7000_device::mov_a2b, &tms7000_device::tstb,    &tms7000_device::dec_b,   &tms7000_device::inc_b,   &tms7000_device::inv_b,   &tms7000_device::clr_b,   &tms7000_device::xchb_b,  &tms7000_device::swap_b,
61		&tms7000_device::push_b,  &tms7000_device::pop_b,   &tms7000_device::djnz_b,  &tms7000_device::decd_b,  &tms7000_device::rr_b,    &tms7000_device::rrc_b,   &tms7000_device::rl_b,    &tms7000_device::rlc_b,
62
63		/* 0xDX */  &tms7000_device::mov_a2r, &tms7000_device::mov_b2r, &tms7000_device::dec_r,   &tms7000_device::inc_r,   &tms7000_device::inv_r,   &tms7000_device::clr_r,   &tms7000_device::xchb_r,  &tms7000_device::swap_r,
64		&tms7000_device::push_r,  &tms7000_device::pop_r,   &tms7000_device::djnz_r,  &tms7000_device::decd_r,  &tms7000_device::rr_r,    &tms7000_device::rrc_r,   &tms7000_device::rl_r,    &tms7000_device::rlc_r,
65
66		/* 0xEX */  &tms7000_device::jmp,     &tms7000_device::j_jn,    &tms7000_device::jeq,     &tms7000_device::jc,      &tms7000_device::jp,      &tms7000_device::jpz,     &tms7000_device::jne,     &tms7000_device::jl,
67		&tms7000_device::trap_23, &tms7000_device::trap_22, &tms7000_device::trap_21, &tms7000_device::trap_20, &tms7000_device::trap_19, &tms7000_device::trap_18, &tms7000_device::trap_17, &tms7000_device::trap_16,
68
69		/* 0xFX */  &tms7000_device::trap_15, &tms7000_device::trap_14, &tms7000_device::trap_13, &tms7000_device::trap_12, &tms7000_device::trap_11, &tms7000_device::trap_10, &tms7000_device::trap_9,  &tms7000_device::trap_8,
70		&tms7000_device::trap_7,  &tms7000_device::trap_6,  &tms7000_device::trap_5,  &tms7000_device::trap_4,  &tms7000_device::trap_3,  &tms7000_device::trap_2,  &tms7000_device::trap_1,  &tms7000_device::trap_0
71		};
72
73		const tms7000_device::opcode_func tms7000_device::s_opfn_exl[0x100] = {
74		/*          0xX0,   0xX1,     0xX2,    0xX3,    0xX4,    0xX5,    0xX6,    0xX7,
75		0xX8,   0xX9,     0xXA,    0xXB,    0xXC,    0xXD,    0xXE,    0xXF   */
76
77		/* 0x0X */  &tms7000_device::nop,     &tms7000_device::idle,    &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::eint,    &tms7000_device::dint,    &tms7000_device::setc,
78		&tms7000_device::pop_st,  &tms7000_device::stsp,    &tms7000_device::rets,    &tms7000_device::reti,    &tms7000_device::illegal, &tms7000_device::ldsp,    &tms7000_device::push_st, &tms7000_device::illegal,
79
80		/* 0x1X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_r2a, &tms7000_device::and_r2a, &tms7000_device::or_r2a,  &tms7000_device::xor_r2a, &tms7000_device::btjo_r2a,&tms7000_device::btjz_r2a,
81		&tms7000_device::add_r2a, &tms7000_device::adc_r2a, &tms7000_device::sub_ra,  &tms7000_device::sbb_ra,  &tms7000_device::mpy_ra,  &tms7000_device::cmp_ra,  &tms7000_device::dac_r2a, &tms7000_device::dsb_r2a,
82
83		/* 0x2X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_i2a, &tms7000_device::and_i2a, &tms7000_device::or_i2a,  &tms7000_device::xor_i2a, &tms7000_device::btjo_i2a,&tms7000_device::btjz_i2a,
84		&tms7000_device::add_i2a, &tms7000_device::adc_i2a, &tms7000_device::sub_ia,  &tms7000_device::sbb_ia,  &tms7000_device::mpy_ia,  &tms7000_device::cmp_ia,  &tms7000_device::dac_i2a, &tms7000_device::dsb_i2a,
85
86		/* 0x3X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_r2b, &tms7000_device::and_r2b, &tms7000_device::or_r2b,  &tms7000_device::xor_r2b, &tms7000_device::btjo_r2b,&tms7000_device::btjz_r2b,
87		&tms7000_device::add_r2b, &tms7000_device::adc_r2b, &tms7000_device::sub_rb,  &tms7000_device::sbb_rb,  &tms7000_device::mpy_rb,  &tms7000_device::cmp_rb,  &tms7000_device::dac_r2b, &tms7000_device::dsb_r2b,
88
89		/* 0x4X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_r2r, &tms7000_device::and_r2r, &tms7000_device::or_r2r,  &tms7000_device::xor_r2r, &tms7000_device::btjo_r2r,&tms7000_device::btjz_r2r,
90		&tms7000_device::add_r2r, &tms7000_device::adc_r2r, &tms7000_device::sub_rr,  &tms7000_device::sbb_rr,  &tms7000_device::mpy_rr,  &tms7000_device::cmp_rr,  &tms7000_device::dac_r2r, &tms7000_device::dsb_r2r,
91
92		/* 0x5X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_i2b, &tms7000_device::and_i2b, &tms7000_device::or_i2b,  &tms7000_device::xor_i2b, &tms7000_device::btjo_i2b,&tms7000_device::btjz_i2b,
93		&tms7000_device::add_i2b, &tms7000_device::adc_i2b, &tms7000_device::sub_ib,  &tms7000_device::sbb_ib,  &tms7000_device::mpy_ib,  &tms7000_device::cmp_ib,  &tms7000_device::dac_i2b, &tms7000_device::dsb_i2b,
94
95		/* 0x6X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_b2a, &tms7000_device::and_b2a, &tms7000_device::or_b2a,  &tms7000_device::xor_b2a, &tms7000_device::btjo_b2a,&tms7000_device::btjz_b2a,
96		&tms7000_device::add_b2a, &tms7000_device::adc_b2a, &tms7000_device::sub_ba,  &tms7000_device::sbb_ba,  &tms7000_device::mpy_ba,  &tms7000_device::cmp_ba,  &tms7000_device::dac_b2a, &tms7000_device::dsb_b2a,
97
98		/* 0x7X */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::mov_i2r, &tms7000_device::and_i2r, &tms7000_device::or_i2r,  &tms7000_device::xor_i2r, &tms7000_device::btjo_i2r,&tms7000_device::btjz_i2r,
99		&tms7000_device::add_i2r, &tms7000_device::adc_i2r, &tms7000_device::sub_ir,  &tms7000_device::sbb_ir,  &tms7000_device::mpy_ir,  &tms7000_device::cmp_ir,  &tms7000_device::dac_i2r, &tms7000_device::dsb_i2r,
100
101		/* 0x8X */  &tms7000_device::movp_p2a,&tms7000_device::illegal, &tms7000_device::movp_a2p,&tms7000_device::andp_a2p,&tms7000_device::orp_a2p, &tms7000_device::xorp_a2p,&tms7000_device::btjop_ap,&tms7000_device::btjzp_ap,
102		&tms7000_device::movd_imm,&tms7000_device::illegal, &tms7000_device::lda_dir, &tms7000_device::sta_dir, &tms7000_device::br_dir,  &tms7000_device::cmpa_dir,&tms7000_device::call_dir,&tms7000_device::illegal,
103
104		/* 0x9X */  &tms7000_device::illegal, &tms7000_device::movp_p2b,&tms7000_device::movp_b2p,&tms7000_device::andp_b2p,&tms7000_device::orp_b2p, &tms7000_device::xorp_b2p,&tms7000_device::btjop_bp,&tms7000_device::btjzp_bp,
105		&tms7000_device::movd_r,  &tms7000_device::illegal, &tms7000_device::lda_ind, &tms7000_device::sta_ind, &tms7000_device::br_ind,  &tms7000_device::cmpa_ind,&tms7000_device::call_ind,&tms7000_device::illegal,
106
107		/* 0xAX */  &tms7000_device::illegal, &tms7000_device::illegal, &tms7000_device::movp_i2p,&tms7000_device::andp_i2p,&tms7000_device::orp_i2p, &tms7000_device::xorp_i2p,&tms7000_device::btjop_ip,&tms7000_device::btjzp_ip,
108		&tms7000_device::movd_inx,&tms7000_device::illegal, &tms7000_device::lda_inx, &tms7000_device::sta_inx, &tms7000_device::br_inx,  &tms7000_device::cmpa_inx,&tms7000_device::call_inx,&tms7000_device::illegal,
109
110		/* 0xBX */  &tms7000_device::clrc,    &tms7000_device::illegal, &tms7000_device::dec_a,   &tms7000_device::inc_a,   &tms7000_device::inv_a,   &tms7000_device::clr_a,   &tms7000_device::xchb_a,  &tms7000_device::swap_a,
111		&tms7000_device::push_a,  &tms7000_device::pop_a,   &tms7000_device::djnz_a,  &tms7000_device::decd_a,  &tms7000_device::rr_a,    &tms7000_device::rrc_a,   &tms7000_device::rl_a,    &tms7000_device::rlc_a,
112
113		/* 0xCX */  &tms7000_device::mov_a2b, &tms7000_device::tstb,    &tms7000_device::dec_b,   &tms7000_device::inc_b,   &tms7000_device::inv_b,   &tms7000_device::clr_b,   &tms7000_device::xchb_b,  &tms7000_device::swap_b,
114		&tms7000_device::push_b,  &tms7000_device::pop_b,   &tms7000_device::djnz_b,  &tms7000_device::decd_b,  &tms7000_device::rr_b,    &tms7000_device::rrc_b,   &tms7000_device::rl_b,    &tms7000_device::rlc_b,
115
116		/* 0xDX */  &tms7000_device::mov_a2r, &tms7000_device::mov_b2r, &tms7000_device::dec_r,   &tms7000_device::inc_r,   &tms7000_device::inv_r,   &tms7000_device::clr_r,   &tms7000_device::xchb_r,  &tms7000_device::swap_r_exl,
117		&tms7000_device::push_r,  &tms7000_device::pop_r,   &tms7000_device::djnz_r,  &tms7000_device::decd_r,  &tms7000_device::rr_r,    &tms7000_device::rrc_r,   &tms7000_device::rl_r,    &tms7000_device::rlc_r,
118
119		/* 0xEX */  &tms7000_device::jmp,     &tms7000_device::j_jn,    &tms7000_device::jeq,     &tms7000_device::jc,      &tms7000_device::jp,      &tms7000_device::jpz,     &tms7000_device::jne,     &tms7000_device::jl,
120		&tms7000_device::trap_23, &tms7000_device::trap_22, &tms7000_device::trap_21, &tms7000_device::trap_20, &tms7000_device::trap_19, &tms7000_device::trap_18, &tms7000_device::trap_17, &tms7000_device::trap_16,
121
122		/* 0xFX */  &tms7000_device::trap_15, &tms7000_device::trap_14, &tms7000_device::trap_13, &tms7000_device::trap_12, &tms7000_device::trap_11, &tms7000_device::trap_10, &tms7000_device::trap_9,  &tms7000_device::trap_8,
123		&tms7000_device::trap_7,  &tms7000_device::trap_6,  &tms7000_device::trap_5,  &tms7000_device::trap_4,  &tms7000_device::trap_3,  &tms7000_device::trap_2,  &tms7000_device::trap_1,  &tms7000_device::trap_0
124		};

trunk/src/emu/cpu/tms7000/tms7000.c

r31296	r31297
18	18	*****************************************************************************
19	19	*  Misc. improvements were done over the years by team MESS/MAME
20	20	*
21		*  Currently this source emulates a TMS70x0, not any of the other variants
22		*  Unimplemented is the MC pin which (in conjunection with IOCNT0 bits 7 and 6
23		*  control the memory mapping.
	21	*  TODO:
	22	*  - dump CROM and emulate cpu at microinstruction level
	23	*  - memory modes with IOCNT0, currently ignored
	24	*  - timer event counter mode (timer control register, bit 6)
	25	*  - TMS70x1/2 serial port and timer 3
	26	*  - when they're needed, add TMS70Cx2, TMS7742, TMS77C82, SE70xxx
24	27	*
25		*  This source implements the MC pin at Vss and mode bits in single chip mode.
26	28	*****************************************************************************/
27	29
28	30	#include "debugger.h"
r31296	r31297
32	34
33	35	#define LOG(x)  do { if (VERBOSE) logerror x; } while (0)
34	36
	37	// flag helpers
	38	#define SR_C        0x80 /* Carry */
	39	#define SR_N        0x40 /* Negative */
	40	#define SR_Z        0x20 /* Zero */
	41	#define SR_I        0x10 /* Interrupt */
35	42
36		#define RM(Addr) ((unsigned)m_program->read_byte(Addr))
37		#define WM(Addr,Value) (m_program->write_byte(Addr, Value))
	43	#define GET_C()     (m_sr >> 7 & 1)
	44	#define SET_C(x)    m_sr = (m_sr & 0x7f) | ((x) >> 1 & 0x80)
	45	#define SET_NZ(x)   m_sr = (m_sr & 0x9f) | ((x) >> 1 & 0x40) | (((x) & 0xff) ? 0 : 0x20)
	46	#define SET_CNZ(x)  m_sr = (m_sr & 0x1f) | ((x) >> 1 & 0xc0) | (((x) & 0xff) ? 0 : 0x20)
38	47
39		#define IMMBYTE(b)  b = ((unsigned)m_direct->read_raw_byte(pPC)); pPC++
40		#define SKIPBYTE()  ((unsigned)m_direct->read_raw_byte(pPC)); pPC++
41		#define SIMMBYTE(b) b = ((signed)m_direct->read_raw_byte(pPC)); pPC++
42		#define IMMWORD(w)  w.b.h = (unsigned)m_direct->read_raw_byte(pPC++); w.b.l = (unsigned)m_direct->read_raw_byte(pPC++)
43	48
44		#define PUSHBYTE(b) pSP++; WM(pSP,b)
45		#define PUSHWORD(w) pSP++; WM(pSP,w.b.h); pSP++; WM(pSP,w.b.l)
46		#define PULLBYTE(b) b = RM(pSP); pSP--
47		#define PULLWORD(w) w.b.l = RM(pSP); pSP--; w.b.h = RM(pSP); pSP--
48
49
50	49	const device_type TMS7000 = &device_creator<tms7000_device>;
51	50	const device_type TMS7020 = &device_creator<tms7020_device>;
52	51	const device_type TMS7020_EXL = &device_creator<tms7020_exl_device>;
r31296	r31297
54	53	const device_type TMS70C00 = &device_creator<tms70c00_device>;
55	54	const device_type TMS70C20 = &device_creator<tms70c20_device>;
56	55	const device_type TMS70C40 = &device_creator<tms70c40_device>;
	56	const device_type TMS7001 = &device_creator<tms7001_device>;
	57	const device_type TMS7041 = &device_creator<tms7041_device>;
	58	const device_type TMS7002 = &device_creator<tms7002_device>;
	59	const device_type TMS7042 = &device_creator<tms7042_device>;
57	60
	61
	62	// internal memory maps
58	63	static ADDRESS_MAP_START(tms7000_io, AS_IO, 8, tms7000_device)
59		AM_RANGE(TMS7000_PORTA, TMS7000_PORTA) AM_WRITENOP
60	64	AM_RANGE(TMS7000_PORTB, TMS7000_PORTB) AM_READNOP
61	65	ADDRESS_MAP_END
62	66
63	67	static ADDRESS_MAP_START(tms7000_mem, AS_PROGRAM, 8, tms7000_device )
64	68	AM_RANGE(0x0000, 0x007f) AM_RAM // 128 bytes internal RAM
65		AM_RANGE(0x0100, 0x010f) AM_READWRITE(tms70x0_pf_r, tms70x0_pf_w)             /* tms7000 internal I/O ports */
	69	AM_RANGE(0x0080, 0x00ff) AM_READWRITE(tms7000_unmapped_rf_r, tms7000_unmapped_rf_w)
	70	AM_RANGE(0x0104, 0x0105) AM_WRITENOP // no port A write or ddr
	71	AM_RANGE(0x0100, 0x010b) AM_READWRITE(tms7000_pf_r, tms7000_pf_w)
66	72	ADDRESS_MAP_END
67	73
	74	static ADDRESS_MAP_START(tms7001_mem, AS_PROGRAM, 8, tms7000_device )
	75	AM_RANGE(0x0000, 0x007f) AM_RAM // 128 bytes internal RAM
	76	AM_RANGE(0x0080, 0x00ff) AM_READWRITE(tms7000_unmapped_rf_r, tms7000_unmapped_rf_w)
	77	AM_RANGE(0x0100, 0x010b) AM_READWRITE(tms7000_pf_r, tms7000_pf_w)
	78	AM_RANGE(0x0110, 0x0117) AM_READWRITE(tms7002_pf_r, tms7002_pf_w)
	79	ADDRESS_MAP_END
	80
	81	static ADDRESS_MAP_START(tms7002_mem, AS_PROGRAM, 8, tms7000_device )
	82	AM_RANGE(0x0000, 0x00ff) AM_RAM // 256 bytes internal RAM
	83	AM_RANGE(0x0100, 0x010b) AM_READWRITE(tms7000_pf_r, tms7000_pf_w)
	84	AM_RANGE(0x0110, 0x0117) AM_READWRITE(tms7002_pf_r, tms7002_pf_w)
	85	ADDRESS_MAP_END
	86
68	87	static ADDRESS_MAP_START(tms7020_mem, AS_PROGRAM, 8, tms7000_device )
69	88	AM_RANGE(0xf000, 0xffff) AM_ROM // 2kB internal ROM
70	89	AM_IMPORT_FROM( tms7000_mem )
r31296	r31297
75	94	AM_IMPORT_FROM( tms7000_mem )
76	95	ADDRESS_MAP_END
77	96
	97	static ADDRESS_MAP_START(tms7041_mem, AS_PROGRAM, 8, tms7000_device )
	98	AM_RANGE(0xf000, 0xffff) AM_ROM
	99	AM_IMPORT_FROM( tms7001_mem )
	100	ADDRESS_MAP_END
78	101
	102	static ADDRESS_MAP_START(tms7042_mem, AS_PROGRAM, 8, tms7000_device )
	103	AM_RANGE(0xf000, 0xffff) AM_ROM
	104	AM_IMPORT_FROM( tms7002_mem )
	105	ADDRESS_MAP_END
	106
	107
	108	// device definitions
79	109	tms7000_device::tms7000_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
80	110	: cpu_device(mconfig, TMS7000, "TMS7000", tag, owner, clock, "tms7000", __FILE__),
81	111	m_program_config("program", ENDIANNESS_BIG, 8, 16, 0, ADDRESS_MAP_NAME(tms7000_mem)),
82	112	m_io_config("io", ENDIANNESS_BIG, 8, 8, 0, ADDRESS_MAP_NAME(tms7000_io)),
83		m_opcode(s_opfn)
	113	m_info_flags(0)
84	114	{
85	115	}
86	116
87		tms7000_device::tms7000_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, address_map_constructor internal, const opcode_func *opcode, const char *shortname, const char *source)
	117	tms7000_device::tms7000_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, address_map_constructor internal, UINT32 info_flags, const char *shortname, const char *source)
88	118	: cpu_device(mconfig, type, name, tag, owner, clock, shortname, source),
89	119	m_program_config("program", ENDIANNESS_BIG, 8, 16, 0, internal),
90	120	m_io_config("io", ENDIANNESS_BIG, 8, 8, 0, ADDRESS_MAP_NAME(tms7000_io)),
91		m_opcode(opcode)
	121	m_info_flags(info_flags)
92	122	{
93	123	}
94	124
95	125	tms7020_device::tms7020_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
96		: tms7000_device(mconfig, TMS7020, "TMS7020", tag, owner, clock, ADDRESS_MAP_NAME(tms7020_mem), s_opfn, "tms7020", __FILE__)
	126	: tms7000_device(mconfig, TMS7020, "TMS7020", tag, owner, clock, ADDRESS_MAP_NAME(tms7020_mem), 0, "tms7020", __FILE__)
97	127	{
98	128	}
99	129
100	130	tms7020_exl_device::tms7020_exl_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
101		: tms7000_device(mconfig, TMS7020_EXL, "TMS7020 (EXL)", tag, owner, clock, ADDRESS_MAP_NAME(tms7020_mem), s_opfn_exl, "tms7020_exl", __FILE__)
	131	: tms7000_device(mconfig, TMS7020_EXL, "TMS7020 (Exelvision)", tag, owner, clock, ADDRESS_MAP_NAME(tms7020_mem), 0, "tms7020_exl", __FILE__)
102	132	{
103	133	}
104	134
105	135	tms7040_device::tms7040_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
106		: tms7000_device(mconfig, TMS7040, "TMS7040", tag, owner, clock, ADDRESS_MAP_NAME(tms7040_mem), s_opfn, "tms7040", __FILE__)
	136	: tms7000_device(mconfig, TMS7040, "TMS7040", tag, owner, clock, ADDRESS_MAP_NAME(tms7040_mem), 0, "tms7040", __FILE__)
107	137	{
108	138	}
109	139
110	140	tms70c00_device::tms70c00_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
111		: tms7000_device(mconfig, TMS70C00, "TMS70C00", tag, owner, clock, ADDRESS_MAP_NAME(tms7000_mem), s_opfn, "tms70c00", __FILE__)
	141	: tms7000_device(mconfig, TMS70C00, "TMS70C00", tag, owner, clock, ADDRESS_MAP_NAME(tms7000_mem), TMS7000_CHIP_IS_CMOS, "tms70c00", __FILE__)
112	142	{
113	143	}
114	144
115	145	tms70c20_device::tms70c20_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
116		: tms7000_device(mconfig, TMS70C20, "TMS70C20", tag, owner, clock, ADDRESS_MAP_NAME(tms7020_mem), s_opfn, "tms70c20", __FILE__)
	146	: tms7000_device(mconfig, TMS70C20, "TMS70C20", tag, owner, clock, ADDRESS_MAP_NAME(tms7020_mem), TMS7000_CHIP_IS_CMOS, "tms70c20", __FILE__)
117	147	{
118	148	}
119	149
120	150	tms70c40_device::tms70c40_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
121		: tms7000_device(mconfig, TMS70C40, "TMS70C40", tag, owner, clock, ADDRESS_MAP_NAME(tms7040_mem), s_opfn, "tms70c40", __FILE__)
	151	: tms7000_device(mconfig, TMS70C40, "TMS70C40", tag, owner, clock, ADDRESS_MAP_NAME(tms7040_mem), TMS7000_CHIP_IS_CMOS, "tms70c40", __FILE__)
122	152	{
123	153	}
124	154
125
126		offs_t tms7000_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
	155	tms7001_device::tms7001_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	156	: tms7000_device(mconfig, TMS7001, "TMS7001", tag, owner, clock, ADDRESS_MAP_NAME(tms7001_mem), TMS7000_CHIP_FAMILY_70X2, "tms7001", __FILE__)
127	157	{
128		extern CPU_DISASSEMBLE( tms7000 );
129		return CPU_DISASSEMBLE_NAME(tms7000)(this, buffer, pc, oprom, opram, options);
130	158	}
131	159
132
133		#define pPC     m_pc.w.l
134		#define PC      m_pc
135		#define pSP     m_sp
136		#define pSR     m_sr
137
138		#define RDA     RM(0x0000)
139		#define RDB     RM(0x0001)
140
141		#define WRA(Value) (WM(0x0000,Value))
142		#define WRB(Value) (WM(0x0001,Value))
143
144		#define SR_C    0x80        /* Carry */
145		#define SR_N    0x40        /* Negative */
146		#define SR_Z    0x20        /* Zero */
147		#define SR_I    0x10        /* Interrupt */
148
149		#define CLR_NZC     pSR&=~(SR_N|SR_Z|SR_C)
150		#define CLR_NZCI    pSR&=~(SR_N|SR_Z|SR_C|SR_I)
151		#define SET_C8(a)   pSR|=((a&0x0100)>>1)
152		#define SET_N8(a)   pSR|=((a&0x0080)>>1)
153		#define SET_Z(a)    if(!a)pSR|=SR_Z
154		#define SET_Z8(a)   SET_Z((UINT8)a)
155		#define SET_Z16(a)  SET_Z((UINT8)a>>8)
156		#define GET_C       (pSR >> 7)
157
158		#define SET_N16(a)   pSR|=(((a)&0x008000)>>9)
159
160		/* Not working */
161		#define SET_C16(a)  pSR|=((a&0x010000)>>9)
162
163		#define SETC        pSR |= SR_C
164		#define SETZ        pSR |= SR_Z
165		#define SETN        pSR |= SR_N
166
167
168		UINT16 tms7000_device::RM16( UINT32 mAddr ) /* Read memory (16-bit) */
	160	tms7041_device::tms7041_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	161	: tms7000_device(mconfig, TMS7041, "TMS7041", tag, owner, clock, ADDRESS_MAP_NAME(tms7041_mem), TMS7000_CHIP_FAMILY_70X2, "tms7041", __FILE__)
169	162	{
170		UINT32 result = RM(mAddr) << 8;
171		return result | RM((mAddr+1)&0xffff);
172	163	}
173	164
174		UINT16 tms7000_device::RRF16( UINT32 mAddr ) /* Read register file (16 bit) */
	165	tms7002_device::tms7002_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	166	: tms7000_device(mconfig, TMS7002, "TMS7002", tag, owner, clock, ADDRESS_MAP_NAME(tms7002_mem), TMS7000_CHIP_FAMILY_70X2, "tms7002", __FILE__)
175	167	{
176		PAIR result;
177		result.b.h = RM((mAddr-1)&0xffff);
178		result.b.l = RM(mAddr);
179		return result.w.l;
180	168	}
181	169
182		void tms7000_device::WRF16( UINT32 mAddr, PAIR p ) /* Write register file (16 bit) */
	170	tms7042_device::tms7042_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	171	: tms7000_device(mconfig, TMS7042, "TMS7042", tag, owner, clock, ADDRESS_MAP_NAME(tms7042_mem), TMS7000_CHIP_FAMILY_70X2, "tms7042", __FILE__)
183	172	{
184		WM( (mAddr-1)&0xffff, p.b.h );
185		WM( mAddr, p.b.l );
186	173	}
187	174
188	175
	176	//-------------------------------------------------
	177	//  device_start - device-specific startup
	178	//-------------------------------------------------
	179
189	180	void tms7000_device::device_start()
190	181	{
	182	// init/zerofill
191	183	m_program = &space(AS_PROGRAM);
192	184	m_direct = &m_program->direct();
193	185	m_io = &space(AS_IO);
194	186
195		memset(m_pf, 0, 0x100);
196		m_cycles_per_INT2 = 0;
197		m_t1_capture_latch = 0;
198		m_t1_prescaler = 0;
199		m_t1_decrementer = 0;
200		memset(&m_pc, 0x00, sizeof(m_pc));
	187	m_icountptr = &m_icount;
	188
	189	m_irq_state[TMS7000_INT1_LINE] = false;
	190	m_irq_state[TMS7000_INT3_LINE] = false;
	191
	192	m_idle_state = false;
	193	m_idle_halt = false;
	194	m_pc = 0;
201	195	m_sp = 0;
202	196	m_sr = 0;
203		m_idle_state = 0;
	197	m_op = 0;
204	198
205		/* Save register state */
206		save_item(NAME(pPC));
207		save_item(NAME(pSP));
208		save_item(NAME(pSR));
	199	memset(m_io_control, 0, 3);
209	200
210		/* Save Interrupt state */
	201	memset(m_port_latch, 0, 4);
	202	memset(m_port_ddr, 0, 4);
	203	m_port_ddr[1] = 0xff; // !
	204
	205	for (int tmr = 0; tmr < 2; tmr++)
	206	{
	207	m_timer_handle[tmr] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(tms7000_device::simple_timer_cb), this));
	208	m_timer_handle[tmr]->adjust(attotime::never, tmr);
	209
	210	m_timer_data[tmr] = 0;
	211	m_timer_control[tmr] = 0;
	212	m_timer_decrementer[tmr] = 0;
	213	m_timer_prescaler[tmr] = 0;
	214	m_timer_capture_latch[tmr] = 0;
	215	}
	216
	217	// register for savestates
211	218	save_item(NAME(m_irq_state));
	219	save_item(NAME(m_idle_state));
	220	save_item(NAME(m_pc));
	221	save_item(NAME(m_sp));
	222	save_item(NAME(m_sr));
	223	save_item(NAME(m_op));
212	224
213		/* Save register and perpherial file state */
214		save_item(NAME(m_pf));
	225	save_item(NAME(m_io_control));
	226	save_item(NAME(m_port_latch));
	227	save_item(NAME(m_port_ddr));
	228	save_item(NAME(m_timer_data));
	229	save_item(NAME(m_timer_control));
	230	save_item(NAME(m_timer_decrementer));
	231	save_item(NAME(m_timer_prescaler));
	232	save_item(NAME(m_timer_capture_latch));
215	233
216		/* Save timer state */
217		save_item(NAME(m_t1_prescaler));
218		save_item(NAME(m_t1_capture_latch));
219		save_item(NAME(m_t1_decrementer));
	234	// register for debugger
	235	state_add( TMS7000_PC, "PC", m_pc).formatstr("%02X");
	236	state_add( TMS7000_SP, "S", m_sp).formatstr("%02X");
	237	state_add( TMS7000_ST, "ST", m_sr).formatstr("%02X");
220	238
221		save_item(NAME(m_idle_state));
222
223		state_add( TMS7000_PC,     "PC",    m_pc.w.l).formatstr("%04X");
224		state_add( TMS7000_SP,     "S",     m_sp).formatstr("%02X");
225		state_add( TMS7000_ST,     "ST",    m_sr).formatstr("%02X");
226		state_add( TMS7000_IDLE,   "Idle",  m_idle_state).formatstr("%02X");
227		state_add( TMS7000_T1_CL,  "T1CL",  m_t1_capture_latch).formatstr("%02X");
228		state_add( TMS7000_T1_PS,  "T1PS",  m_t1_prescaler).mask(0x1f).formatstr("%02X");
229		state_add( TMS7000_T1_DEC, "T1DEC", m_t1_decrementer).mask(0xff).formatstr("%02X");
230
231		state_add(STATE_GENPC, "GENPC", m_pc.w.l).formatstr("%04X").noshow();
	239	state_add(STATE_GENPC, "GENPC", m_pc).formatstr("%02X").noshow();
232	240	state_add(STATE_GENSP, "GENSP", m_sp).formatstr("%02X").noshow();
233		state_add(STATE_GENFLAGS, "GENFLAGS",  m_sr).formatstr("%8s").noshow();
234
235		m_icountptr = &m_icount;
	241	state_add(STATE_GENFLAGS, "GENFLAGS", m_sr).formatstr("%8s").noshow();
236	242	}
237	243
238	244	void tms7000_device::state_string_export(const device_state_entry &entry, astring &string)
r31296	r31297
241	247	{
242	248	case STATE_GENFLAGS:
243	249	string.printf("%c%c%c%c%c%c%c%c",
244		m_sr & 0x80 ? 'C':'c',
245		m_sr & 0x40 ? 'N':'n',
246		m_sr & 0x20 ? 'Z':'z',
247		m_sr & 0x10 ? 'I':'i',
248		m_sr & 0x08 ? '?':'.',
249		m_sr & 0x04 ? '?':'.',
250		m_sr & 0x02 ? '?':'.',
251		m_sr & 0x01 ? '?':'.'
	250	m_sr & 0x80 ? 'C':'c',
	251	m_sr & 0x40 ? 'N':'n',
	252	m_sr & 0x20 ? 'Z':'z',
	253	m_sr & 0x10 ? 'I':'i',
	254	m_sr & 0x08 ? '?':'.',
	255	m_sr & 0x04 ? '?':'.',
	256	m_sr & 0x02 ? '?':'.',
	257	m_sr & 0x01 ? '?':'.'
252	258	);
253	259	break;
	260
	261	default: break;
254	262	}
255	263	}
256	264
257		void tms7000_device::device_reset()
	265	offs_t tms7000_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
258	266	{
259		//  m_architecture = (int)param;
	267	extern CPU_DISASSEMBLE( tms7000 );
	268	return CPU_DISASSEMBLE_NAME(tms7000)(this, buffer, pc, oprom, opram, options);
	269	}
260	270
261		m_idle_state = 0;
262		m_irq_state[ TMS7000_IRQ1_LINE ] = CLEAR_LINE;
263		m_irq_state[ TMS7000_IRQ2_LINE ] = CLEAR_LINE;
264		m_irq_state[ TMS7000_IRQ3_LINE ] = CLEAR_LINE;
265	271
266		WM( 0x100 + 9, 0 );     /* Data direction regs are cleared */
267		WM( 0x100 + 11, 0 );
	272	//-------------------------------------------------
	273	//  device_reset - device-specific reset
	274	//-------------------------------------------------
268	275
269		//  if( m_architecture == TMS7000_NMOS )
270		//  {
271		WM( 0x100 + 4, 0xff );      /* Output 0xff on port A */
272		WM( 0x100 + 8, 0xff );      /* Output 0xff on port C */
273		WM( 0x100 + 10, 0xff );     /* Output 0xff on port D */
274		//  }
275		//  else
276		//  {
277		//      WM( 0x100 + 4, 0xff );      /* Output 0xff on port A */
278		//  }
	276	void tms7000_device::device_reset()
	277	{
	278	if (m_idle_state)
	279	{
	280	m_pc++;
	281	m_idle_state = false;
	282	}
279	283
280		pSP = 0x01;             /* Set stack pointer to r1 */
281		pSR = 0x00;             /* Clear status register (disabling interrupts */
282		WM( 0x100 + 0, 0 );     /* Write a zero to IOCNT0 */
	284	// while _RESET is asserted:
	285	// clear ports
	286	write_p(0x04, 0xff); // port a
	287	write_p(0x06, 0xff); // port b
283	288
284		/* On TMS70x2 and TMS70Cx2 IOCNT1 is zero */
	289	write_p(0x05, 0x00); // ddr a
	290	write_p(0x09, 0x00); // ddr c
	291	write_p(0x0b, 0x00); // ddr d
	292
	293	if (!chip_is_cmos())
	294	{
	295	write_p(0x08, 0xff); // port c
	296	write_p(0x0a, 0xff); // port d
	297	}
	298
	299	// when _RESET goes inactive (0 to 1)
	300	m_sr = 0;
285	301
286		WRA( m_pc.b.h );    /* Write previous PC to A:B */
287		WRB( m_pc.b.l );
288		pPC = RM16(0xfffe);       /* Load reset vector */
	302	write_p(0x00, 0x00); // IOCNT0
	303	if (chip_is_family_70x2())
	304	write_p(0x10, 0x00); // IOCNT1
289	305
290		m_div_by_16_trigger = -16;
	306	write_mem16(0, m_pc); // previous PC
	307	m_sp = 0x01;
	308	m_pc = read_mem16(0xfffe);
	309	m_icount -= 17;
291	310	}
292	311
	312
	313	//-------------------------------------------------
	314	//  interrupts
	315	//-------------------------------------------------
	316
293	317	void tms7000_device::execute_set_input(int irqline, int state)
294	318	{
295		if (m_irq_state[irqline] != state)
296		{   /* check for transition */
297		m_irq_state[irqline] = state;
	319	assert(irqline == TMS7000_INT1_LINE || irqline == TMS7000_INT3_LINE);
	320	bool irqstate = (state == CLEAR_LINE) ? false : true;
298	321
299		LOG(("tms7000: (cpu '%s') set_irq_line (INT%d, state %d)\n", tag(), irqline+1, state));
	322	// reverse polarity (70cx2-only)
	323	if (m_io_control[2] & (0x01 << (4 * irqline)))
	324	irqstate = !irqstate;
300	325
301		if (state == CLEAR_LINE)
	326	if (m_irq_state[irqline] != irqstate)
	327	{
	328	m_irq_state[irqline] = irqstate;
	329
	330	// set/clear internal irq flag
	331	flag_ext_interrupt(irqline);
	332
	333	if (m_irq_state[irqline])
302	334	{
303		return;
304		}
	335	// latch timer 1 on INT3
	336	if (irqline == TMS7000_INT3_LINE)
	337	m_timer_capture_latch[0] = m_timer_decrementer[0];
305	338
306		m_pf[0] |= (0x02 << (irqline * 2)); /* Set INTx iocntl0 flag */
	339	// on 70cx2, latch timer 2 on INT1
	340	if (irqline == TMS7000_INT1_LINE && chip_is_family_70cx2())
	341	m_timer_capture_latch[1] = m_timer_decrementer[1];
	342
	343	// clear external if it's edge-triggered (70cx2-only)
	344	if (m_io_control[2] & (0x02 << (4 * irqline)))
	345	m_irq_state[irqline] = false;
307	346
308		if( irqline == TMS7000_IRQ3_LINE )
309		{
310		/* Latch the value in perpherial file register 3 */
311		m_t1_capture_latch = m_t1_decrementer & 0x00ff;
	347	check_interrupts();
312	348	}
313
314		tms7000_check_IRQ_lines();
315	349	}
316	350	}
317	351
318		void tms7000_device::tms7000_check_IRQ_lines()
	352	void tms7000_device::flag_ext_interrupt(int irqline)
319	353	{
320		if( pSR & SR_I ) /* Check Global Interrupt bit: Status register, bit 4 */
321		{
322		if ((m_irq_state[TMS7000_IRQ1_LINE] == ASSERT_LINE) || (m_pf[0] & 0x02))
323		{
324		if( m_pf[0] & 0x01 ) /* INT1 Enable bit */
325		{
326		tms7000_do_interrupt( 0xfffc, TMS7000_IRQ1_LINE );
327		m_pf[0] &= ~0x02; /* Data Manual, page: 9-41 */
328		return;
329		}
330		}
	354	if (irqline != TMS7000_INT1_LINE && irqline != TMS7000_INT3_LINE)
	355	return;
331	356
332		if( m_irq_state[ TMS7000_IRQ2_LINE ] == ASSERT_LINE )
333		{
334		if( m_pf[0] & 0x04 ) /* INT2 Enable bit */
335		{
336		tms7000_do_interrupt( 0xfffa, TMS7000_IRQ2_LINE );
337		return;
338		}
339		}
	357	// set/clear for pending external interrupt
	358	if (m_irq_state[irqline])
	359	m_io_control[0] |= (0x02 << (4 * irqline));
	360	else
	361	m_io_control[0] &= ~(0x02 << (4 * irqline));
	362	}
340	363
341		if ((m_irq_state[TMS7000_IRQ3_LINE] == ASSERT_LINE) || (m_pf[0] & 0x20))
	364	void tms7000_device::check_interrupts()
	365	{
	366	// global interrupt bit
	367	if (!(m_sr & SR_I))
	368	return;
	369
	370	// check for and handle interrupt
	371	for (int irqline = 0; irqline < 5; irqline++)
	372	{
	373	// INT 1,2,3 are in IOCNT0 d0-d5
	374	// INT 4,5 are in IOCNT1 d0-d3
	375	int shift = (irqline > 2) ? irqline * 2 - 6 : irqline * 2;
	376	if ((m_io_control[irqline > 2] >> shift & 3) == 3)
342	377	{
343		if( m_pf[0] & 0x10 ) /* INT3 Enable bit */
344		{
345		tms7000_do_interrupt( 0xfff8, TMS7000_IRQ3_LINE );
346		m_pf[0] &= ~0x20; /* Data Manual, page: 9-41 */
347		return;
348		}
	378	// ack
	379	m_io_control[irqline > 2] &= ~(0x02 << shift);
	380
	381	flag_ext_interrupt(irqline);
	382	do_interrupt(irqline);
	383	return;
349	384	}
350	385	}
351	386	}
352	387
353		void tms7000_device::tms7000_do_interrupt( UINT16 address, UINT8 line )
	388	void tms7000_device::do_interrupt(int irqline)
354	389	{
355		PUSHBYTE( pSR );        /* Push Status register */
356		PUSHWORD( PC );         /* Push Program Counter */
357		pSR = 0;                /* Clear Status register */
358		pPC = RM16(address);  /* Load PC with interrupt vector */
359
360		if( m_idle_state == 0 )
361		m_icount -= 19;     /* 19 cycles used */
362		else
	390	if (m_idle_state)
363	391	{
364		m_icount -= 17;     /* 17 if idled */
365		m_idle_state = 0;
	392	m_icount -= 17;
	393	m_pc++;
	394	m_idle_state = false;
366	395	}
	396	else
	397	m_icount -= 19;
367	398
368		standard_irq_callback(line);
	399	push8(m_sr);
	400	push16(m_pc);
	401	m_sr = 0;
	402	m_pc = read_mem16(0xfffc - irqline * 2);
	403
	404	standard_irq_callback(irqline);
369	405	}
370	406
371		#include "tms70op.inc"
372		#include "tms70tb.inc"
373	407
374		void tms7000_device::execute_run()
	408	//-------------------------------------------------
	409	//  timers
	410	//-------------------------------------------------
	411
	412	void tms7000_device::timer_run(int tmr)
375	413	{
376		int op;
	414	m_timer_prescaler[tmr] = m_timer_control[tmr] & 0x1f;
377	415
378		m_div_by_16_trigger += m_icount;
	416	// run automatic timer if source is internal
	417	if ((m_timer_control[tmr] & 0xe0) == 0x80)
	418	{
	419	attotime period = attotime::from_hz(clock()) * 16 * (m_timer_prescaler[tmr] + 1); // fOSC/16
	420	m_timer_handle[tmr]->adjust(period, tmr);
	421	}
	422	}
379	423
380		tms7000_check_IRQ_lines();
	424	void tms7000_device::timer_reload(int tmr)
	425	{
	426	// stop possible running timer
	427	m_timer_handle[tmr]->adjust(attotime::never, tmr);
	428
	429	if (m_timer_control[tmr] & 0x80)
	430	{
	431	m_timer_decrementer[tmr] = m_timer_data[tmr];
	432	timer_run(tmr);
	433	}
	434	}
381	435
382		do
	436	void tms7000_device::timer_tick_pre(int tmr)
	437	{
	438	// timer prescaler underflow
	439	if (--m_timer_prescaler[tmr] < 0)
383	440	{
384		debugger_instruction_hook(this, pPC);
	441	m_timer_prescaler[tmr] = m_timer_control[tmr] & 0x1f;
	442	timer_tick_low(tmr);
	443	}
	444	}
385	445
386		if( m_idle_state == 0 )
387		{
388		op = m_direct->read_decrypted_byte(pPC++);
	446	void tms7000_device::timer_tick_low(int tmr)
	447	{
	448	// timer decrementer underflow
	449	if (--m_timer_decrementer[tmr] < 0)
	450	{
	451	timer_reload(tmr);
389	452
390		(this->*m_opcode[op])();
391		}
392		else
393		m_icount -= 16;
	453	// set INT2/INT5
	454	m_io_control[tmr] |= 0x08;
	455
	456	// cascaded timer
	457	if (tmr == 0 && (m_timer_control[1] & 0xa0) == 0xa0)
	458	timer_tick_pre(tmr + 1);
	459	}
	460	}
394	461
395		/* Internal timer system */
396
397		while( m_icount < m_div_by_16_trigger )
398		{
399		m_div_by_16_trigger -= 16;
400
401		if( (m_pf[0x03] & 0x80) == 0x80 ) /* Is timer system active? */
402		{
403		if( (m_pf[0x03] & 0x40) != 0x40) /* Is system clock (divided by 16) the timer source? */
404		tms7000_service_timer1();
405		}
406		}
407
408		} while( m_icount > 0 );
409
410		m_div_by_16_trigger -= m_icount;
	462	TIMER_CALLBACK_MEMBER(tms7000_device::simple_timer_cb)
	463	{
	464	int tmr = param;
	465
	466	// tick and restart timer
	467	timer_tick_low(tmr);
	468	timer_run(tmr);
411	469	}
412	470
413	471
414		/****************************************************************************
415		* Trigger the event counter
416		****************************************************************************/
	472	//-------------------------------------------------
	473	//  peripheral file - read/write internal ports
	474	//  note: 7000 family is from $00 to $0b, 7002 family adds $10 to $17
	475	//-------------------------------------------------
417	476
418		void tms7000_device::tms7000_service_timer1()
	477	READ8_MEMBER(tms7000_device::tms7000_pf_r)
419	478	{
420		if( --m_t1_prescaler < 0 ) /* Decrement prescaler and check for underflow */
	479	switch (offset)
421	480	{
422		m_t1_prescaler = m_pf[3] & 0x1f; /* Reload prescaler (5 bit) */
	481	// i/o control
	482	case 0x00: case 0x10:
	483	return m_io_control[offset >> 4];
423	484
424		if( --m_t1_decrementer < 0 ) /* Decrement timer1 register and check for underflow */
	485	// timer 1/2 data
	486	case 0x02: case 0x12:
	487	// current decrementer value
	488	return m_timer_decrementer[offset >> 4];
	489
	490	// timer 1 control
	491	case 0x03:
	492	// timer capture (latched by INT3)
	493	return m_timer_capture_latch[0];
	494
	495	// port data
	496	case 0x04: case 0x06: case 0x08: case 0x0a:
425	497	{
426		m_t1_decrementer = m_pf[2]; /* Reload decrementer (8 bit) */
427		set_input_line(TMS7000_IRQ2_LINE, HOLD_LINE);
428		//LOG( ("tms7000: trigger int2 (cycles: %d)\t%d\tdelta %d\n", total_cycles(), total_cycles() - tick, m_cycles_per_INT2-(total_cycles() - tick) );
429		//tick = total_cycles() );
430		/* Also, cascade out to timer 2 - timer 2 unimplemented */
	498	// note: port B is write-only, reading it returns the output value as if ddr is 0xff
	499	int port = offset / 2 - 2;
	500	return (m_io->read_byte(port) & ~m_port_ddr[port]) | (m_port_latch[port] & m_port_ddr[port]);
431	501	}
	502
	503	// port direction (note: 7000 doesn't support it for port A)
	504	case 0x05: case 0x09: case 0x0b:
	505	return m_port_ddr[offset / 2 - 2];
	506
	507	default:
	508	logerror("%s: tms7000_pf_r @ $%04x\n", tag(), offset);
	509	break;
432	510	}
433		//  LOG( ( "tms7000: service timer1. 0x%2.2x 0x%2.2x (cycles %d)\t%d\t\n", m_t1_prescaler, m_t1_decrementer, total_cycles(), total_cycles() - tick2 ) );
434		//  tick2 = total_cycles();
	511
	512	return 0;
435	513	}
436	514
437		WRITE8_MEMBER( tms7000_device::tms70x0_pf_w )   /* Perpherial file write */
	515	WRITE8_MEMBER(tms7000_device::tms7000_pf_w)
438	516	{
439		UINT8   temp1, temp2, temp3;
440
441		switch( offset )
	517	switch (offset)
442	518	{
443		case 0x00:  /* IOCNT0, Input/Ouput control */
444		temp1 = data & 0x2a;                            /* Record which bits to clear */
445		temp2 = m_pf[0x00] & 0x2a;              /* Get copy of current bits */
446		temp3 = (~temp1) & temp2;                       /* Clear the requested bits */
447		m_pf[0x00] = temp3 | (data & (~0x2a) ); /* OR in the remaining data */
	519	// i/o control (IOCNT0)
	520	case 0x00:
	521	// d0,d2,d4: INT1,2,3 enable
	522	// d1,d3,d5: INT1,2,3 flag (write 1 to clear flag)
	523	// d6-d7: memory mode (currently not implemented)
	524	m_io_control[0] = (m_io_control[0] & (~data & 0x2a)) | (data & 0xd5);
	525
	526	// possibly need to reactivate flags
	527	if (data & 0x02)
	528	flag_ext_interrupt(TMS7000_INT1_LINE);
	529	if (data & 0x20)
	530	flag_ext_interrupt(TMS7000_INT3_LINE);
	531
	532	check_interrupts();
448	533	break;
449		case 0x02:
450		m_t1_decrementer = m_pf[0x02] = data;
451		m_cycles_per_INT2 = 0x10*((m_pf[3] & 0x1f)+1)*(m_pf[0x02]+1);
452		LOG( ( "tms7000: Timer adjusted. Decrementer: 0x%2.2x (Cycles per interrupt: %d)\n", m_t1_decrementer, m_cycles_per_INT2 ) );
	534
	535	// i/o control (IOCNT1)
	536	case 0x10:
	537	// d0,d2: INT4,5 enable
	538	// d1,d3: INT4,5 flag (write 1 to clear flag)
	539	m_io_control[1] = (m_io_control[1] & (~data & 0x0a)) | (data & 0x05);
	540	check_interrupts();
453	541	break;
454		case 0x03:  /* T1CTL, timer 1 control */
455		if( ((m_pf[0x03] & 0x80) == 0) && ((data & 0x80) == 0x80 ) )   /* Start timer? */
	542
	543	// timer 1/2 data
	544	case 0x02: case 0x12:
	545	// decrementer reload value
	546	m_timer_data[offset >> 4] = data;
	547	break;
	548
	549	// timer 1/2 control
	550	case 0x03:
	551	// d5: t1: cmos low-power mode when IDLE opcode is used (not emulated)
	552	// 0(normal), or 1(halt) - indicating it can only wake up with RESET or external interrupt
	553	if (chip_is_cmos())
456	554	{
457		m_pf[0x03] = data;
458		m_t1_prescaler = m_pf[3] & 0x1f; /* Reload prescaler (5 bit) */
459		m_cycles_per_INT2 = 0x10*((m_pf[3] & 0x1f)+1)*(m_pf[0x02]+1);
460		LOG( ( "tms7000: Timer started. Prescaler: 0x%2.2x (Cycles per interrupt: %d)\n", m_pf[3] & 0x1f, m_cycles_per_INT2 ) );
	555	m_idle_halt = (data & 0x20) ? true : false;
	556	if (m_idle_halt)
	557	logerror("%s: CMOS low-power halt mode enabled\n", tag());
461	558	}
462		else if( ((data & 0x80) == 0x80 ) && ((m_pf[0x03] & 0x80) == 0) )   /* Timer Stopped? */
463		{
464		m_pf[0x03] = data;
465		m_t1_prescaler = m_pf[3] & 0x1f; /* Reload prescaler (5 bit) */
466		m_cycles_per_INT2 = 0x10*((m_pf[3] & 0x1f)+1)*(m_pf[0x02]+1);
467		LOG( ( "tms7000: Timer stopped. Prescaler: 0x%2.2x (Cycles per interrupt: %d)\n", m_pf[3] & 0x1f, m_cycles_per_INT2 ) );
468		}
469		else /* Don't modify timer state, but still store data */
470		{
471		m_pf[0x03] = data;
472		m_cycles_per_INT2 = 0x10*((m_pf[3] & 0x1f)+1)*(m_pf[0x02]+1);
473		LOG( ( "tms7000: Timer adjusted. Prescaler: 0x%2.2x (Cycles per interrupt: %d)\n", m_pf[3] & 0x1f, m_cycles_per_INT2 ) );
474		}
	559	data &= ~0x20;
	560	case 0x13:
	561	// d0-d4: prescaler reload value
	562	// d5: t2: cascade from t1
	563	// d6: source (internal/external)
	564	// d7: stop/start timer
	565	m_timer_control[offset >> 4] = data;
	566	timer_reload(offset >> 4);
	567
	568	// on cmos chip, clear INT2/INT5 as well
	569	if (~data & 0x80 && chip_is_cmos())
	570	m_io_control[offset >> 4] &= ~0x08;
	571
475	572	break;
476	573
477		case 0x04: /* Port A write */
478		/* Port A is read only so this is a NOP */
	574	// port data (note: 7000 doesn't support it for port A)
	575	case 0x04: case 0x06: case 0x08: case 0x0a:
	576	{
	577	// note: in memory expansion modes, some port output pins are used for memory strobes.
	578	// this is currently ignored, since port writes will always be visible externally on peripheral expansion anyway.
	579	int port = offset / 2 - 2;
	580	m_io->write_byte(port, data & m_port_ddr[port]);
	581	m_port_latch[port] = data;
479	582	break;
480
481		case 0x06: /* Port B write */
482		m_io->write_byte( TMS7000_PORTB, data );
483		m_pf[ 0x06 ] = data;
	583	}
	584
	585	// port direction (note: 7000 doesn't support it for port A)
	586	case 0x05: case 0x09: case 0x0b:
	587	// note: changing port direction does not change(refresh) the output pins
	588	m_port_ddr[offset / 2 - 2] = data;
484	589	break;
485	590
486		case 0x08: /* Port C write */
487		temp1 = data & m_pf[ 0x09 ];    /* Mask off input bits */
488		m_io->write_byte( TMS7000_PORTC, temp1 );
489		m_pf[ 0x08 ] = temp1;
490		break;
491
492		case 0x0a: /* Port D write */
493		temp1 = data & m_pf[ 0x0b ];    /* Mask off input bits */
494		m_io->write_byte( TMS7000_PORTD, temp1 );
495		m_pf[ 0x0a ] = temp1;
496		break;
497
498	591	default:
499		/* Just stuff the other registers */
500		m_pf[ offset ] = data;
	592	logerror("%s: tms7000_pf_w @ $%04x = $%02x\n", tag(), offset, data);
501	593	break;
502	594	}
503	595	}
504	596
505		READ8_MEMBER( tms7000_device::tms70x0_pf_r )    /* Perpherial file read */
	597
	598	//-------------------------------------------------
	599	//  execute
	600	//-------------------------------------------------
	601
	602	#include "tms70op.inc"
	603
	604	void tms7000_device::execute_run()
506	605	{
507		UINT8 result;
508		UINT8   temp1, temp2, temp3;
	606	check_interrupts();
509	607
510		switch( offset )
	608	do
511	609	{
512		case 0x00:  /* IOCNT0, Input/Ouput control */
513		result = m_pf[0x00];
514		if (m_irq_state[TMS7000_IRQ1_LINE] == ASSERT_LINE)
515		result |= 0x02;
516		if (m_irq_state[TMS7000_IRQ3_LINE] == ASSERT_LINE)
517		result |= 0x20;
518		break;
	610	debugger_instruction_hook(this, m_pc);
519	611
520		case 0x02:  /* T1DATA, timer 1 8-bit decrementer */
521		result = (m_t1_decrementer & 0x00ff);
522		break;
	612	m_op = m_direct->read_decrypted_byte(m_pc++);
	613	execute_one(m_op);
	614	} while (m_icount > 0);
	615	}
523	616
524		case 0x03:  /* T1CTL, timer 1 capture (latched by INT3) */
525		result = m_t1_capture_latch;
526		break;
	617	void tms7000_device::execute_one(UINT8 op)
	618	{
	619	switch (op)
	620	{
	621	case 0x00: nop(); break;
	622	case 0x01: idle(); break;
	623	case 0x05: eint(); break;
	624	case 0x06: dint(); break;
	625	case 0x07: setc(); break;
	626	case 0x08: pop_st(); break;
	627	case 0x09: stsp(); break;
	628	case 0x0a: rets(); break;
	629	case 0x0b: reti(); break;
	630	case 0x0d: ldsp(); break;
	631	case 0x0e: push_st(); break;
	632
	633	case 0x12: am_r2a(&tms7000_device::op_mov); break;
	634	case 0x13: am_r2a(&tms7000_device::op_and); break;
	635	case 0x14: am_r2a(&tms7000_device::op_or); break;
	636	case 0x15: am_r2a(&tms7000_device::op_xor); break;
	637	case 0x16: am_r2a(&tms7000_device::op_btjo); break;
	638	case 0x17: am_r2a(&tms7000_device::op_btjz); break;
	639	case 0x18: am_r2a(&tms7000_device::op_add); break;
	640	case 0x19: am_r2a(&tms7000_device::op_adc); break;
	641	case 0x1a: am_r2a(&tms7000_device::op_sub); break;
	642	case 0x1b: am_r2a(&tms7000_device::op_sbb); break;
	643	case 0x1c: am_r2a(&tms7000_device::op_mpy); break;
	644	case 0x1d: am_r2a(&tms7000_device::op_cmp); break;
	645	case 0x1e: am_r2a(&tms7000_device::op_dac); break;
	646	case 0x1f: am_r2a(&tms7000_device::op_dsb); break;
527	647
528		case 0x04: /* Port A read */
529		result = m_io->read_byte( TMS7000_PORTA );
530		break;
	648	case 0x22: am_i2a(&tms7000_device::op_mov); break;
	649	case 0x23: am_i2a(&tms7000_device::op_and); break;
	650	case 0x24: am_i2a(&tms7000_device::op_or); break;
	651	case 0x25: am_i2a(&tms7000_device::op_xor); break;
	652	case 0x26: am_i2a(&tms7000_device::op_btjo); break;
	653	case 0x27: am_i2a(&tms7000_device::op_btjz); break;
	654	case 0x28: am_i2a(&tms7000_device::op_add); break;
	655	case 0x29: am_i2a(&tms7000_device::op_adc); break;
	656	case 0x2a: am_i2a(&tms7000_device::op_sub); break;
	657	case 0x2b: am_i2a(&tms7000_device::op_sbb); break;
	658	case 0x2c: am_i2a(&tms7000_device::op_mpy); break;
	659	case 0x2d: am_i2a(&tms7000_device::op_cmp); break;
	660	case 0x2e: am_i2a(&tms7000_device::op_dac); break;
	661	case 0x2f: am_i2a(&tms7000_device::op_dsb); break;
531	662
	663	case 0x32: am_r2b(&tms7000_device::op_mov); break;
	664	case 0x33: am_r2b(&tms7000_device::op_and); break;
	665	case 0x34: am_r2b(&tms7000_device::op_or); break;
	666	case 0x35: am_r2b(&tms7000_device::op_xor); break;
	667	case 0x36: am_r2b(&tms7000_device::op_btjo); break;
	668	case 0x37: am_r2b(&tms7000_device::op_btjz); break;
	669	case 0x38: am_r2b(&tms7000_device::op_add); break;
	670	case 0x39: am_r2b(&tms7000_device::op_adc); break;
	671	case 0x3a: am_r2b(&tms7000_device::op_sub); break;
	672	case 0x3b: am_r2b(&tms7000_device::op_sbb); break;
	673	case 0x3c: am_r2b(&tms7000_device::op_mpy); break;
	674	case 0x3d: am_r2b(&tms7000_device::op_cmp); break;
	675	case 0x3e: am_r2b(&tms7000_device::op_dac); break;
	676	case 0x3f: am_r2b(&tms7000_device::op_dsb); break;
532	677
533		case 0x06: /* Port B read */
534		/* Port B is write only, return a previous written value */
535		result = m_pf[ 0x06 ];
536		break;
	678	case 0x42: am_r2r(&tms7000_device::op_mov); break;
	679	case 0x43: am_r2r(&tms7000_device::op_and); break;
	680	case 0x44: am_r2r(&tms7000_device::op_or); break;
	681	case 0x45: am_r2r(&tms7000_device::op_xor); break;
	682	case 0x46: am_r2r(&tms7000_device::op_btjo); break;
	683	case 0x47: am_r2r(&tms7000_device::op_btjz); break;
	684	case 0x48: am_r2r(&tms7000_device::op_add); break;
	685	case 0x49: am_r2r(&tms7000_device::op_adc); break;
	686	case 0x4a: am_r2r(&tms7000_device::op_sub); break;
	687	case 0x4b: am_r2r(&tms7000_device::op_sbb); break;
	688	case 0x4c: am_r2r(&tms7000_device::op_mpy); break;
	689	case 0x4d: am_r2r(&tms7000_device::op_cmp); break;
	690	case 0x4e: am_r2r(&tms7000_device::op_dac); break;
	691	case 0x4f: am_r2r(&tms7000_device::op_dsb); break;
537	692
538		case 0x08: /* Port C read */
539		temp1 = m_pf[ 0x08 ] & m_pf[ 0x09 ];    /* Get previous output bits */
540		temp2 = m_io->read_byte( TMS7000_PORTC );           /* Read port */
541		temp3 = temp2 & (~m_pf[ 0x09 ]);                /* Mask off output bits */
542		result = temp1 | temp3;                             /* OR together */
543		break;
	693	case 0x52: am_i2b(&tms7000_device::op_mov); break;
	694	case 0x53: am_i2b(&tms7000_device::op_and); break;
	695	case 0x54: am_i2b(&tms7000_device::op_or); break;
	696	case 0x55: am_i2b(&tms7000_device::op_xor); break;
	697	case 0x56: am_i2b(&tms7000_device::op_btjo); break;
	698	case 0x57: am_i2b(&tms7000_device::op_btjz); break;
	699	case 0x58: am_i2b(&tms7000_device::op_add); break;
	700	case 0x59: am_i2b(&tms7000_device::op_adc); break;
	701	case 0x5a: am_i2b(&tms7000_device::op_sub); break;
	702	case 0x5b: am_i2b(&tms7000_device::op_sbb); break;
	703	case 0x5c: am_i2b(&tms7000_device::op_mpy); break;
	704	case 0x5d: am_i2b(&tms7000_device::op_cmp); break;
	705	case 0x5e: am_i2b(&tms7000_device::op_dac); break;
	706	case 0x5f: am_i2b(&tms7000_device::op_dsb); break;
544	707
545		case 0x0a: /* Port D read */
546		temp1 = m_pf[ 0x0a ] & m_pf[ 0x0b ];    /* Get previous output bits */
547		temp2 = m_io->read_byte( TMS7000_PORTD );           /* Read port */
548		temp3 = temp2 & (~m_pf[ 0x0b ]);                /* Mask off output bits */
549		result = temp1 | temp3;                             /* OR together */
550		break;
	708	case 0x62: am_b2a(&tms7000_device::op_mov); break;
	709	case 0x63: am_b2a(&tms7000_device::op_and); break;
	710	case 0x64: am_b2a(&tms7000_device::op_or); break;
	711	case 0x65: am_b2a(&tms7000_device::op_xor); break;
	712	case 0x66: am_b2a(&tms7000_device::op_btjo); break;
	713	case 0x67: am_b2a(&tms7000_device::op_btjz); break;
	714	case 0x68: am_b2a(&tms7000_device::op_add); break;
	715	case 0x69: am_b2a(&tms7000_device::op_adc); break;
	716	case 0x6a: am_b2a(&tms7000_device::op_sub); break;
	717	case 0x6b: am_b2a(&tms7000_device::op_sbb); break;
	718	case 0x6c: am_b2a(&tms7000_device::op_mpy); break;
	719	case 0x6d: am_b2a(&tms7000_device::op_cmp); break;
	720	case 0x6e: am_b2a(&tms7000_device::op_dac); break;
	721	case 0x6f: am_b2a(&tms7000_device::op_dsb); break;
551	722
552		default:
553		/* Just unstuff the other registers */
554		result = m_pf[ offset ];
555		break;
556		}
	723	case 0x72: am_i2r(&tms7000_device::op_mov); break;
	724	case 0x73: am_i2r(&tms7000_device::op_and); break;
	725	case 0x74: am_i2r(&tms7000_device::op_or); break;
	726	case 0x75: am_i2r(&tms7000_device::op_xor); break;
	727	case 0x76: am_i2r(&tms7000_device::op_btjo); break;
	728	case 0x77: am_i2r(&tms7000_device::op_btjz); break;
	729	case 0x78: am_i2r(&tms7000_device::op_add); break;
	730	case 0x79: am_i2r(&tms7000_device::op_adc); break;
	731	case 0x7a: am_i2r(&tms7000_device::op_sub); break;
	732	case 0x7b: am_i2r(&tms7000_device::op_sbb); break;
	733	case 0x7c: am_i2r(&tms7000_device::op_mpy); break;
	734	case 0x7d: am_i2r(&tms7000_device::op_cmp); break;
	735	case 0x7e: am_i2r(&tms7000_device::op_dac); break;
	736	case 0x7f: am_i2r(&tms7000_device::op_dsb); break;
	737
	738	case 0x80: am_p2a(&tms7000_device::op_mov); break;
	739	case 0x82: am_a2p(&tms7000_device::op_mov); break;
	740	case 0x83: am_a2p(&tms7000_device::op_and); break;
	741	case 0x84: am_a2p(&tms7000_device::op_or); break;
	742	case 0x85: am_a2p(&tms7000_device::op_xor); break;
	743	case 0x86: am_a2p(&tms7000_device::op_btjo); break;
	744	case 0x87: am_a2p(&tms7000_device::op_btjz); break;
	745	case 0x88: movd_dir(); break;
	746	case 0x8a: lda_dir(); break;
	747	case 0x8b: sta_dir(); break;
	748	case 0x8c: br_dir(); break;
	749	case 0x8d: cmpa_dir(); break;
	750	case 0x8e: call_dir(); break;
557	751
558		return result;
559		}
	752	case 0x91: am_p2b(&tms7000_device::op_mov); break;
	753	case 0x92: am_b2p(&tms7000_device::op_mov); break;
	754	case 0x93: am_b2p(&tms7000_device::op_and); break;
	755	case 0x94: am_b2p(&tms7000_device::op_or); break;
	756	case 0x95: am_b2p(&tms7000_device::op_xor); break;
	757	case 0x96: am_b2p(&tms7000_device::op_btjo); break;
	758	case 0x97: am_b2p(&tms7000_device::op_btjz); break;
	759	case 0x98: movd_ind(); break;
	760	case 0x9a: lda_ind(); break;
	761	case 0x9b: sta_ind(); break;
	762	case 0x9c: br_ind(); break;
	763	case 0x9d: cmpa_ind(); break;
	764	case 0x9e: call_ind(); break;
560	765
561		// BCD arthrimetic handling
562		static const UINT8 lut_bcd_out[6] = { 0x00, 0x06, 0x00, 0x66, 0x60, 0x66 };
	766	case 0xa2: am_i2p(&tms7000_device::op_mov); break;
	767	case 0xa3: am_i2p(&tms7000_device::op_and); break;
	768	case 0xa4: am_i2p(&tms7000_device::op_or); break;
	769	case 0xa5: am_i2p(&tms7000_device::op_xor); break;
	770	case 0xa6: am_i2p(&tms7000_device::op_btjo); break;
	771	case 0xa7: am_i2p(&tms7000_device::op_btjz); break;
	772	case 0xa8: movd_inx(); break;
	773	case 0xaa: lda_inx(); break;
	774	case 0xab: sta_inx(); break;
	775	case 0xac: br_inx(); break;
	776	case 0xad: cmpa_inx(); break;
	777	case 0xae: call_inx(); break;
	778
	779	case 0xb0: am_a2a(&tms7000_device::op_mov); break; // aka clrc/tsta
	780	case 0xb1: am_b2a(&tms7000_device::op_mov); break; // undocumented
	781	case 0xb2: am_a(&tms7000_device::op_dec); break;
	782	case 0xb3: am_a(&tms7000_device::op_inc); break;
	783	case 0xb4: am_a(&tms7000_device::op_inv); break;
	784	case 0xb5: am_a(&tms7000_device::op_clr); break;
	785	case 0xb6: am_a(&tms7000_device::op_xchb); break;
	786	case 0xb7: am_a(&tms7000_device::op_swap); break;
	787	case 0xb8: push_a(); break;
	788	case 0xb9: pop_a(); break;
	789	case 0xba: am_a(&tms7000_device::op_djnz); break;
	790	case 0xbb: decd_a(); break;
	791	case 0xbc: am_a(&tms7000_device::op_rr); break;
	792	case 0xbd: am_a(&tms7000_device::op_rrc); break;
	793	case 0xbe: am_a(&tms7000_device::op_rl); break;
	794	case 0xbf: am_a(&tms7000_device::op_rlc); break;
563	795
564		inline UINT8 tms7000_device::bcd_add( UINT8 a, UINT8 b, UINT8 c )
565		{
566		c = (c != 0) ? 1 : 0;
	796	case 0xc0: am_a2b(&tms7000_device::op_mov); break;
	797	case 0xc1: am_b2b(&tms7000_device::op_mov); break; // aka tstb
	798	case 0xc2: am_b(&tms7000_device::op_dec); break;
	799	case 0xc3: am_b(&tms7000_device::op_inc); break;
	800	case 0xc4: am_b(&tms7000_device::op_inv); break;
	801	case 0xc5: am_b(&tms7000_device::op_clr); break;
	802	case 0xc6: am_b(&tms7000_device::op_xchb); break; // result equivalent to tstb
	803	case 0xc7: am_b(&tms7000_device::op_swap); break;
	804	case 0xc8: push_b(); break;
	805	case 0xc9: pop_b(); break;
	806	case 0xca: am_b(&tms7000_device::op_djnz); break;
	807	case 0xcb: decd_b(); break;
	808	case 0xcc: am_b(&tms7000_device::op_rr); break;
	809	case 0xcd: am_b(&tms7000_device::op_rrc); break;
	810	case 0xce: am_b(&tms7000_device::op_rl); break;
	811	case 0xcf: am_b(&tms7000_device::op_rlc); break;
567	812
568		UINT8 h1 = a >> 4 & 0xf;
569		UINT8 l1 = a >> 0 & 0xf;
570		UINT8 h2 = b >> 4 & 0xf;
571		UINT8 l2 = b >> 0 & 0xf;
572
573		// compute bcd constant
574		UINT8 d = ((l1 + l2 + c) < 10) ? 0 : 1;
575		if ((h1 + h2) == 9)
576		d |= 2;
577		else if ((h1 + h2) > 9)
578		d |= 4;
579
580		UINT8 ret = a + b + c + lut_bcd_out[d];
581
582		CLR_NZC;
583		SET_N8(ret);
584		SET_Z8(ret);
585
586		if (d > 2)
587		pSR |= SR_C;
588
589		return ret;
	813	case 0xd0: am_a2r(&tms7000_device::op_mov); break;
	814	case 0xd1: am_b2r(&tms7000_device::op_mov); break;
	815	case 0xd2: am_r(&tms7000_device::op_dec); break;
	816	case 0xd3: am_r(&tms7000_device::op_inc); break;
	817	case 0xd4: am_r(&tms7000_device::op_inv); break;
	818	case 0xd5: am_r(&tms7000_device::op_clr); break;
	819	case 0xd6: am_r(&tms7000_device::op_xchb); break;
	820	case 0xd7: am_r(&tms7000_device::op_swap); break;
	821	case 0xd8: push_r(); break;
	822	case 0xd9: pop_r(); break;
	823	case 0xda: am_r(&tms7000_device::op_djnz); break;
	824	case 0xdb: decd_r(); break;
	825	case 0xdc: am_r(&tms7000_device::op_rr); break;
	826	case 0xdd: am_r(&tms7000_device::op_rrc); break;
	827	case 0xde: am_r(&tms7000_device::op_rl); break;
	828	case 0xdf: am_r(&tms7000_device::op_rlc); break;
	829
	830	case 0xe0: jmp(true); break;
	831	case 0xe1: jmp(m_sr & SR_N); break; // jn/jlt
	832	case 0xe2: jmp(m_sr & SR_Z); break; // jz/jeq
	833	case 0xe3: jmp(m_sr & SR_C); break; // jc/jhs
	834	case 0xe4: jmp(!(m_sr & (SR_Z | SR_N))); break; // jp/jgt
	835	case 0xe5: jmp(!(m_sr & SR_N)); break; // jpz/jge - note: error in TI official documentation
	836	case 0xe6: jmp(!(m_sr & SR_Z)); break; // jnz/jne
	837	case 0xe7: jmp(!(m_sr & SR_C)); break; // jnc/jl
	838
	839	case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee: case 0xef:
	840	case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7:
	841	case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff:
	842	trap(op << 1); break;
	843
	844	default: illegal(op); break;
	845	}
590	846	}
591	847
592		inline UINT8 tms7000_device::bcd_sub( UINT8 a, UINT8 b, UINT8 c )
	848	void tms7020_exl_device::execute_one(UINT8 op)
593	849	{
594		c = (c != 0) ? 0 : 1;
595
596		UINT8 h1 = a >> 4 & 0xf;
597		UINT8 l1 = a >> 0 & 0xf;
598		UINT8 h2 = b >> 4 & 0xf;
599		UINT8 l2 = b >> 0 & 0xf;
600
601		// compute bcd constant
602		UINT8 d = ((l1 - c) >= l2) ? 0 : 1;
603		if (h1 == h2)
604		d |= 2;
605		else if (h1 < h2)
606		d |= 4;
607
608		UINT8 ret = a - b - c - lut_bcd_out[d];
609
610		CLR_NZC;
611		SET_N8(ret);
612		SET_Z8(ret);
613
614		if (d > 2)
615		pSR |= SR_C;
616
617		return ret;
	850	// TMS7020 Exelvision EXL 100 custom opcode(s)
	851	if (op == 0xd7)
	852	lvdp();
	853	else
	854	tms7000_device::execute_one(op);
618	855	}

trunk/src/emu/cpu/tms7000/7000dasm.c

r31296	r31297
395	395	case UI8:
396	396	a = (UINT8)opram[pos++];
397	397	buffer += sprintf(buffer, of[j].opstr[k], (unsigned int)a);
398		//size += 1;
399	398	break;
400	399	case I8:
401	400	b = (INT8)opram[pos++];
402	401	buffer += sprintf (buffer, of[j].opstr[k], (INT8)b);
403		//size += 1;
404	402	break;
405	403	case UI16:
406	404	c = (UINT16)opram[pos++];
407	405	c <<= 8;
408	406	c += opram[pos++];
409	407	buffer += sprintf (buffer, of[j].opstr[k], (unsigned int)c);
410		//size += 2;
411	408	break;
412	409	case I16:
413	410	d = (INT16)opram[pos++];
414	411	d <<= 8;
415	412	d += opram[pos++];
416	413	buffer += sprintf (buffer, of[j].opstr[k], (signed int)d);
417		//size += 2;
418	414	break;
419	415	case PCREL:
420	416	b = (INT8)opram[pos++];
421	417	sprintf(tmpbuf, "$%04X", pc+2+k+b);
422	418	buffer += sprintf (buffer, of[j].opstr[k], tmpbuf);
423		//size += 1;
424	419	break;
425	420	case PCABS:
426	421	c = (UINT16)opram[pos++];
r31296	r31297
428	423	c += opram[pos++];
429	424	sprintf(tmpbuf, "$%04X", c);
430	425	buffer += sprintf (buffer, of[j].opstr[k], tmpbuf);
431		//size += 2;
432	426	break;
433	427	case TRAP:
434	428	vector = 0xffff - ((0xff - opcode) * 2);
435		c = vector;//(UINT16)((memory_decrypted_read_byte( vector-1 ) << 8) + memory_decrypted_read_byte( vector ));
	429	c = vector;
436	430	break;
437	431	}
438	432	}

trunk/src/emu/cpu/tms7000/tms7000.h

r31296	r31297
25	25	#include "emu.h"
26	26
27	27
28		enum { TMS7000_PC=1, TMS7000_SP, TMS7000_ST, TMS7000_IDLE, TMS7000_T1_CL, TMS7000_T1_PS, TMS7000_T1_DEC };
	28	enum { TMS7000_PC=1, TMS7000_SP, TMS7000_ST };
29	29
30	30	enum
31	31	{
32		TMS7000_IRQ1_LINE = 0,   /* INT1 */
33		TMS7000_IRQ2_LINE,       /* INT2 */
34		TMS7000_IRQ3_LINE,       /* INT3 */
35		TMS7000_IRQNONE = 255
	32	/* note: INT2,4,5 are generated internally */
	33	TMS7000_INT1_LINE = 0,
	34	TMS7000_INT3_LINE
36	35	};
37	36
38	37	enum
39	38	{
40		TMS7000_PORTA = 0, /* read-only */
41		TMS7000_PORTB,     /* write-only */
	39	TMS7000_PORTA = 0,      /* read-only on 70x0 */
	40	TMS7000_PORTB,          /* write-only */
42	41	TMS7000_PORTC,
43	42	TMS7000_PORTD
44	43	};
45	44
	45	// chip info flags
	46	#define TMS7000_CHIP_IS_CMOS        0x01
	47	#define TMS7000_CHIP_FAMILY_70X0    0x00
	48	#define TMS7000_CHIP_FAMILY_70X2    0x02
	49	#define TMS7000_CHIP_FAMILY_70CX2   0x04
	50	#define TMS7000_CHIP_FAMILY_MASK    0x06
46	51
	52
47	53	class tms7000_device : public cpu_device
48	54	{
49	55	public:
50		typedef void ( tms7000_device::*opcode_func ) ();
51		static const opcode_func s_opfn[0x100];
52		static const opcode_func s_opfn_exl[0x100];
53
54	56	// construction/destruction
55	57	tms7000_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
56		tms7000_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, address_map_constructor internal, const opcode_func *opcode, const char *shortname, const char *source);
	58	tms7000_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, address_map_constructor internal, UINT32 info_flags, const char *shortname, const char *source);
57	59
58		DECLARE_WRITE8_MEMBER( tms70x0_pf_w );
59		DECLARE_READ8_MEMBER( tms70x0_pf_r );
	60	DECLARE_READ8_MEMBER(tms7000_unmapped_rf_r) { logerror("%s: unmapped_rf_r @ $%04x\n", tag(), offset + 0x80); return 0; };
	61	DECLARE_WRITE8_MEMBER(tms7000_unmapped_rf_w) { logerror("%s: unmapped_rf_w @ $%04x = $%02x\n", tag(), offset + 0x80, data); };
60	62
	63	DECLARE_READ8_MEMBER(tms7000_pf_r);
	64	DECLARE_WRITE8_MEMBER(tms7000_pf_w);
	65	DECLARE_READ8_MEMBER(tms7002_pf_r) { return tms7000_pf_r(space, offset + 0x10); }
	66	DECLARE_WRITE8_MEMBER(tms7002_pf_w) { tms7000_pf_w(space, offset + 0x10, data); }
	67
	68	bool chip_is_cmos() { return (m_info_flags & TMS7000_CHIP_IS_CMOS) ? true : false; }
	69	UINT32 chip_get_family() { return m_info_flags & TMS7000_CHIP_FAMILY_MASK; }
	70	bool chip_is_family_70x0() { return chip_get_family() == TMS7000_CHIP_FAMILY_70X0; }
	71	bool chip_is_family_70x2() { return chip_get_family() == TMS7000_CHIP_FAMILY_70X2; }
	72	bool chip_is_family_70cx2() { return chip_get_family() == TMS7000_CHIP_FAMILY_70CX2; }
	73
61	74	protected:
62	75	// device-level overrides
63	76	virtual void device_start();
64	77	virtual void device_reset();
65	78
66	79	// device_execute_interface overrides
67		virtual UINT32 execute_min_cycles() const { return 1; }
68		virtual UINT32 execute_max_cycles() const { return 48; }
69		virtual UINT32 execute_input_lines() const { return 3; }
	80	virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 2 - 1) / 2; } // internal /2 divider
	81	virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 2); } // internal /2 divider
	82	virtual UINT32 execute_min_cycles() const { return 5; }
	83	virtual UINT32 execute_max_cycles() const { return 49; }
	84	virtual UINT32 execute_input_lines() const { return 2; }
70	85	virtual void execute_run();
71	86	virtual void execute_set_input(int inputnum, int state);
72	87
r31296	r31297
81	96	virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
82	97	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
83	98
84		private:
	99	virtual void execute_one(UINT8 op);
	100
85	101	address_space_config m_program_config;
86	102	address_space_config m_io_config;
87	103
88		const opcode_func *m_opcode;
	104	UINT32 m_info_flags;
89	105
90		inline UINT8 bcd_add( UINT8 a, UINT8 b, UINT8 c );
91		inline UINT8 bcd_sub( UINT8 a, UINT8 b, UINT8 c );
92
93		PAIR        m_pc;               /* Program counter */
94		UINT8       m_sp;               /* Stack Pointer */
95		UINT8       m_sr;               /* Status Register */
96		UINT8       m_irq_state[3];     /* State of the three IRQs */
97		UINT8       m_pf[0x100];        /* Perpherial file */
98
99		int         m_icount;
100		int         m_div_by_16_trigger;
101		int         m_cycles_per_INT2;
102		UINT8       m_t1_capture_latch; /* Timer 1 capture latch */
103		INT8        m_t1_prescaler;     /* Timer 1 prescaler (5 bits) */
104		INT16       m_t1_decrementer;   /* Timer 1 decrementer (8 bits) */
105		UINT8       m_idle_state;       /* Set after the execution of an idle instruction */
106
107	106	address_space *m_program;
108	107	direct_read_data *m_direct;
109	108	address_space *m_io;
	109	int m_icount;
110	110
111		inline UINT16 RM16( UINT32 mAddr );
112		inline UINT16 RRF16( UINT32 mAddr );
113		inline void WRF16( UINT32 mAddr, PAIR p );
	111	bool m_irq_state[2];
	112	bool m_idle_state;
	113	bool m_idle_halt;
	114	UINT16 m_pc;
	115	UINT8 m_sp;
	116	UINT8 m_sr;
	117	UINT8 m_op;
114	118
115		void tms7000_check_IRQ_lines();
116		void tms7000_do_interrupt( UINT16 address, UINT8 line );
117		void tms7000_service_timer1();
	119	UINT8 m_io_control[3];
118	120
119		void illegal();
120		void adc_b2a();
121		void adc_r2a();
122		void adc_r2b();
123		void adc_r2r();
124		void adc_i2a();
125		void adc_i2b();
126		void adc_i2r();
127		void add_b2a();
128		void add_r2a();
129		void add_r2b();
130		void add_r2r();
131		void add_i2a();
132		void add_i2b();
133		void add_i2r();
134		void and_b2a();
135		void and_r2a();
136		void and_r2b();
137		void and_r2r();
138		void and_i2a();
139		void and_i2b();
140		void and_i2r();
141		void andp_a2p();
142		void andp_b2p();
143		void movp_i2p();
144		void andp_i2p();
	121	emu_timer *m_timer_handle[2];
	122	UINT8 m_timer_data[2];
	123	UINT8 m_timer_control[2];
	124	int m_timer_decrementer[2];
	125	int m_timer_prescaler[2];
	126	UINT16 m_timer_capture_latch[2];
	127
	128	UINT8 m_port_latch[4];
	129	UINT8 m_port_ddr[4];
	130
	131	void flag_ext_interrupt(int irqline);
	132	void check_interrupts();
	133	void do_interrupt(int irqline);
	134
	135	TIMER_CALLBACK_MEMBER(simple_timer_cb);
	136	void timer_run(int tmr);
	137	void timer_reload(int tmr);
	138	void timer_tick_pre(int tmr);
	139	void timer_tick_low(int tmr);
	140
	141	// internal read/write
	142	inline UINT8 read_r8(UINT8 address) { return m_program->read_byte(address); }
	143	inline void write_r8(UINT8 address, UINT8 data) { m_program->write_byte(address, data); }
	144	inline UINT16 read_r16(UINT8 address) { return m_program->read_byte((address - 1) & 0xff) << 8 | m_program->read_byte(address); }
	145	inline void write_r16(UINT8 address, UINT16 data) { m_program->write_byte((address - 1) & 0xff, data >> 8 & 0xff); m_program->write_byte(address, data & 0xff); }
	146
	147	inline UINT8 read_p(UINT8 address) { return m_program->read_byte(0x100 + address); }
	148	inline void write_p(UINT8 address, UINT8 data) { m_program->write_byte(0x100 + address, data); }
	149
	150	inline UINT8 read_mem8(UINT16 address) { return m_program->read_byte(address); }
	151	inline void write_mem8(UINT16 address, UINT8 data) { m_program->write_byte(address, data); }
	152	inline UINT16 read_mem16(UINT16 address) { return m_program->read_byte(address) << 8 | m_program->read_byte((address + 1) & 0xffff); }
	153	inline void write_mem16(UINT16 address, UINT16 data) { m_program->write_byte(address, data >> 8 & 0xff); m_program->write_byte((address + 1) & 0xffff, data & 0xff); }
	154
	155	inline UINT8 imm8() { return m_direct->read_raw_byte(m_pc++); }
	156	inline UINT16 imm16() { UINT16 ret = m_direct->read_raw_byte(m_pc++) << 8; return ret | m_direct->read_raw_byte(m_pc++); }
	157
	158	inline UINT8 pull8() { return m_program->read_byte(m_sp--); }
	159	inline void push8(UINT8 data) { m_program->write_byte(++m_sp, data); }
	160	inline UINT16 pull16() { UINT16 ret = m_program->read_byte(m_sp--); return ret | m_program->read_byte(m_sp--) << 8; }
	161	inline void push16(UINT16 data) { m_program->write_byte(++m_sp, data >> 8 & 0xff); m_program->write_byte(++m_sp, data & 0xff); }
	162
	163	// opcode handlers
145	164	void br_dir();
146		void br_ind();
147	165	void br_inx();
148		void btjo_b2a();
149		void btjo_r2a();
150		void btjo_r2b();
151		void btjo_r2r();
152		void btjo_i2a();
153		void btjo_i2b();
154		void btjo_i2r();
155		void btjop_ap();
156		void btjop_bp();
157		void btjop_ip();
158		void btjz_b2a();
159		void btjz_r2a();
160		void btjz_r2b();
161		void btjz_r2r();
162		void btjz_i2a();
163		void btjz_i2b();
164		void btjz_i2r();
165		void btjzp_ap();
166		void btjzp_bp();
167		void btjzp_ip();
	166	void br_ind();
168	167	void call_dir();
169		void call_ind();
170	168	void call_inx();
171		void clr_a();
172		void clr_b();
173		void clr_r();
174		void clrc();
175		void cmp_ba();
176		void cmp_ra();
177		void cmp_rb();
178		void cmp_rr();
179		void cmp_ia();
180		void cmp_ib();
181		void cmp_ir();
	169	void call_ind();
182	170	void cmpa_dir();
183		void cmpa_ind();
184	171	void cmpa_inx();
185		void dac_b2a();
186		void dac_r2a();
187		void dac_r2b();
188		void dac_r2r();
189		void dac_i2a();
190		void dac_i2b();
191		void dac_i2r();
192		void dec_a();
193		void dec_b();
194		void dec_r();
	172	void cmpa_ind();
195	173	void decd_a();
196	174	void decd_b();
197	175	void decd_r();
198	176	void dint();
199		void djnz_a();
200		void djnz_b();
201		void djnz_r();
202		void dsb_b2a();
203		void dsb_r2a();
204		void dsb_r2b();
205		void dsb_r2r();
206		void dsb_i2a();
207		void dsb_i2b();
208		void dsb_i2r();
209	177	void eint();
210	178	void idle();
211		void inc_a();
212		void inc_b();
213		void inc_r();
214		void inv_a();
215		void inv_b();
216		void inv_r();
217		void jc();
218		void jeq();
219		void jl();
220		void jmp();
221		void j_jn();
222		void jne();
223		void jp();
224		void jpz();
225	179	void lda_dir();
226		void lda_ind();
227	180	void lda_inx();
	181	void lda_ind();
228	182	void ldsp();
229		void mov_a2b();
230		void mov_b2a();
231		void mov_a2r();
232		void mov_b2r();
233		void mov_r2a();
234		void mov_r2b();
235		void mov_r2r();
236		void mov_i2a();
237		void mov_i2b();
238		void mov_i2r();
239		void movd_imm();
240		void movd_r();
	183	void movd_dir();
241	184	void movd_inx();
242		void movp_a2p();
243		void movp_b2p();
244		void movp_r2p();
245		void movp_p2a();
246		void movp_p2b();
247		void mpy_ba();
248		void mpy_ra();
249		void mpy_rb();
250		void mpy_rr();
251		void mpy_ia();
252		void mpy_ib();
253		void mpy_ir();
	185	void movd_ind();
254	186	void nop();
255		void or_b2a();
256		void or_r2a();
257		void or_r2b();
258		void or_r2r();
259		void or_i2a();
260		void or_i2b();
261		void or_i2r();
262		void orp_a2p();
263		void orp_b2p();
264		void orp_i2p();
265	187	void pop_a();
266	188	void pop_b();
267	189	void pop_r();
r31296	r31297
272	194	void push_st();
273	195	void reti();
274	196	void rets();
275		void rl_a();
276		void rl_b();
277		void rl_r();
278		void rlc_a();
279		void rlc_b();
280		void rlc_r();
281		void rr_a();
282		void rr_b();
283		void rr_r();
284		void rrc_a();
285		void rrc_b();
286		void rrc_r();
287		void sbb_ba();
288		void sbb_ra();
289		void sbb_rb();
290		void sbb_rr();
291		void sbb_ia();
292		void sbb_ib();
293		void sbb_ir();
294	197	void setc();
295	198	void sta_dir();
296		void sta_ind();
297	199	void sta_inx();
	200	void sta_ind();
298	201	void stsp();
299		void sub_ba();
300		void sub_ra();
301		void sub_rb();
302		void sub_rr();
303		void sub_ia();
304		void sub_ib();
305		void sub_ir();
306		void trap_0();
307		void trap_1();
308		void trap_2();
309		void trap_3();
310		void trap_4();
311		void trap_5();
312		void trap_6();
313		void trap_7();
314		void trap_8();
315		void trap_9();
316		void trap_10();
317		void trap_11();
318		void trap_12();
319		void trap_13();
320		void trap_14();
321		void trap_15();
322		void trap_16();
323		void trap_17();
324		void trap_18();
325		void trap_19();
326		void trap_20();
327		void trap_21();
328		void trap_22();
329		void trap_23();
330		void swap_a();
331		void swap_b();
332		void swap_r();
333		void swap_r_exl();
334		void tstb();
335		void xchb_a();
336		void xchb_b();
337		void xchb_r();
338		void xor_b2a();
339		void xor_r2a();
340		void xor_r2b();
341		void xor_r2r();
342		void xor_i2a();
343		void xor_i2b();
344		void xor_i2r();
345		void xorp_a2p();
346		void xorp_b2p();
347		void xorp_i2p();
	202	void trap(UINT8 address);
	203	void illegal(UINT8 op);
	204
	205	typedef int (tms7000_device::*op_func)(UINT8, UINT8);
	206	int op_clr(UINT8 param1, UINT8 param2);
	207	int op_dec(UINT8 param1, UINT8 param2);
	208	int op_inc(UINT8 param1, UINT8 param2);
	209	int op_inv(UINT8 param1, UINT8 param2);
	210	int op_rl(UINT8 param1, UINT8 param2);
	211	int op_rlc(UINT8 param1, UINT8 param2);
	212	int op_rr(UINT8 param1, UINT8 param2);
	213	int op_rrc(UINT8 param1, UINT8 param2);
	214	int op_swap(UINT8 param1, UINT8 param2);
	215	int op_xchb(UINT8 param1, UINT8 param2);
	216
	217	int op_adc(UINT8 param1, UINT8 param2);
	218	int op_add(UINT8 param1, UINT8 param2);
	219	int op_and(UINT8 param1, UINT8 param2);
	220	int op_cmp(UINT8 param1, UINT8 param2);
	221	int op_dac(UINT8 param1, UINT8 param2);
	222	int op_dsb(UINT8 param1, UINT8 param2);
	223	int op_mpy(UINT8 param1, UINT8 param2);
	224	int op_mov(UINT8 param1, UINT8 param2);
	225	int op_or(UINT8 param1, UINT8 param2);
	226	int op_sbb(UINT8 param1, UINT8 param2);
	227	int op_sub(UINT8 param1, UINT8 param2);
	228	int op_xor(UINT8 param1, UINT8 param2);
	229
	230	inline void shortbranch(bool check);
	231	inline void jmp(bool check);
	232	int op_djnz(UINT8 param1, UINT8 param2);
	233	int op_btjo(UINT8 param1, UINT8 param2);
	234	int op_btjz(UINT8 param1, UINT8 param2);
	235
	236	void am_a(op_func op);
	237	void am_b(op_func op);
	238	void am_r(op_func op);
	239	void am_a2a(op_func op);
	240	void am_a2b(op_func op);
	241	void am_a2r(op_func op);
	242	void am_a2p(op_func op);
	243	void am_b2a(op_func op);
	244	void am_b2b(op_func op);
	245	void am_b2r(op_func op);
	246	void am_b2p(op_func op);
	247	void am_r2a(op_func op);
	248	void am_r2b(op_func op);
	249	void am_r2r(op_func op);
	250	void am_i2a(op_func op);
	251	void am_i2b(op_func op);
	252	void am_i2r(op_func op);
	253	void am_i2p(op_func op);
	254	void am_p2a(op_func op);
	255	void am_p2b(op_func op);
348	256	};
349	257
350	258
r31296	r31297
359	267	{
360	268	public:
361	269	tms7020_exl_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	270	protected:
	271	virtual void execute_one(UINT8 op);
	272
	273	private:
	274	void lvdp();
362	275	};
363	276
364	277
r31296	r31297
390	303	};
391	304
392	305
	306	class tms7001_device : public tms7000_device
	307	{
	308	public:
	309	tms7001_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	310	};
	311
	312
	313	class tms7041_device : public tms7000_device
	314	{
	315	public:
	316	tms7041_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	317	};
	318
	319
	320	class tms7002_device : public tms7000_device
	321	{
	322	public:
	323	tms7002_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	324	};
	325
	326
	327	class tms7042_device : public tms7000_device
	328	{
	329	public:
	330	tms7042_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	331	};
	332
	333
393	334	extern const device_type TMS7000;
394	335	extern const device_type TMS7020;
395	336	extern const device_type TMS7020_EXL;
r31296	r31297
397	338	extern const device_type TMS70C00;
398	339	extern const device_type TMS70C20;
399	340	extern const device_type TMS70C40;
	341	extern const device_type TMS7001;
	342	extern const device_type TMS7041;
	343	extern const device_type TMS7002;
	344	extern const device_type TMS7042;
400	345
401
402	346	#endif /* __TMS7000_H__ */

trunk/src/emu/cpu/tms7000/tms70op.inc

r31296	r31297
1	1	/*****************************************************************************
2	2	*
3		*   tms70op.inc (Op code functions)
4		*   Portable TMS7000 emulator (Texas Instruments 7000)
	3	* tms70op.inc (Op code functions)
5	4	*
6		*   Copyright tim lindner, all rights reserved.
7		*
8		*   - This source code is released as freeware for non-commercial purposes.
9		*   - You are free to use and redistribute this code in modified or
10		*     unmodified form, provided you list me in the credits.
11		*   - If you modify this source code, you must add a notice to each modified
12		*     source file that it has been changed.  If you're a nice person, you
13		*     will clearly mark each change too.  :)
14		*   - If you wish to use this for commercial purposes, please contact me at
15		*     tlindner@macmess.org
16		*   - This entire notice must remain in the source code.
17		*
18	5	*****************************************************************************/
19	6
20		void tms7000_device::illegal()
21		{
22		/* This is a guess */
23		m_icount -= 4;
24		}
	7	// addressing modes (not all opcodes have a write cycle)
	8	#define WB_NO -1
	9	#define AM_WB(write_func, address, param1, param2) \
	10	int result = (this->*op)(param1, param2); \
	11	if (result > WB_NO) write_func(address, result)
25	12
26		void tms7000_device::adc_b2a()
	13	void tms7000_device::am_a(op_func op)
27	14	{
28		UINT16  t;
29
30		t = RDA + RDB + GET_C;
31		WRA(t);
32
33		CLR_NZC;
34		SET_C8(t);
35		SET_N8(t);
36		SET_Z8(t);
37
38	15	m_icount -= 5;
	16	AM_WB(write_r8, 0, read_r8(0), 0);
39	17	}
40	18
41		void tms7000_device::adc_r2a()
	19	void tms7000_device::am_b(op_func op)
42	20	{
43		UINT16  t;
44		UINT8   v;
45
46		IMMBYTE(v);
47
48		t = RM(v) + RDA + GET_C;
49		WRA(t);
50
51		CLR_NZC;
52		SET_C8(t);
53		SET_N8(t);
54		SET_Z8(t);
55
56		m_icount -= 8;
	21	m_icount -= 5;
	22	AM_WB(write_r8, 1, read_r8(1), 0);
57	23	}
58	24
59		void tms7000_device::adc_r2b()
	25	void tms7000_device::am_r(op_func op)
60	26	{
61		UINT16  t;
62		UINT8   v;
63
64		IMMBYTE(v);
65
66		t = RM(v) + RDB + GET_C;
67		WRB(t);
68
69		CLR_NZC;
70		SET_C8(t);
71		SET_N8(t);
72		SET_Z8(t);
73
74		m_icount -= 8;
75		}
76
77		void tms7000_device::adc_r2r()
78		{
79		UINT16  t;
80		UINT8   i,j;
81
82		IMMBYTE(i);
83		IMMBYTE(j);
84
85		t = RM(i)+RM(j) + GET_C;
86		WM(j,t);
87
88		CLR_NZC;
89		SET_C8(t);
90		SET_N8(t);
91		SET_Z8(t);
92
93		m_icount -= 10;
94		}
95
96		void tms7000_device::adc_i2a()
97		{
98		UINT16  t;
99		UINT8   v;
100
101		IMMBYTE(v);
102
103		t = v + RDA + GET_C;
104		WRA(t);
105
106		CLR_NZC;
107		SET_C8(t);
108		SET_N8(t);
109		SET_Z8(t);
110
111	27	m_icount -= 7;
	28	UINT8 r = imm8();
	29	AM_WB(write_r8, r, read_r8(r), 0);
112	30	}
113	31
114		void tms7000_device::adc_i2b()
	32	void tms7000_device::am_a2a(op_func op)
115	33	{
116		UINT16  t;
117		UINT8   v;
118
119		IMMBYTE(v);
120
121		t = v + RDB + GET_C;
122		WRB(t);
123
124		CLR_NZC;
125		SET_C8(t);
126		SET_N8(t);
127		SET_Z8(t);
128
129		m_icount -= 7;
	34	m_icount -= 6;
	35	AM_WB(write_r8, 0, read_r8(0), read_r8(0));
130	36	}
131	37
132		void tms7000_device::adc_i2r()
	38	void tms7000_device::am_a2b(op_func op)
133	39	{
134		UINT16  t;
135		UINT8   i,j;
136
137		IMMBYTE(i);
138		IMMBYTE(j);
139
140		t = i+RM(j) + GET_C;
141		WM(j,t);
142
143		CLR_NZC;
144		SET_C8(t);
145		SET_N8(t);
146		SET_Z8(t);
147
148		m_icount -= 9;
	40	m_icount -= 6;
	41	AM_WB(write_r8, 1, read_r8(1), read_r8(0));
149	42	}
150	43
151		void tms7000_device::add_b2a()
	44	void tms7000_device::am_a2p(op_func op)
152	45	{
153		UINT16  t;
154
155		t = RDA + RDB;
156		WRA(t);
157
158		CLR_NZC;
159		SET_C8(t);
160		SET_N8(t);
161		SET_Z8(t);
162
163		m_icount -= 5;
	46	m_icount -= 10;
	47	UINT8 r = imm8();
	48	AM_WB(write_p, r, read_p(r), read_r8(0));
164	49	}
165	50
166		void tms7000_device::add_r2a()
	51	void tms7000_device::am_a2r(op_func op)
167	52	{
168		UINT16  t;
169		UINT8   v;
170
171		IMMBYTE(v);
172
173		t = RM(v) + RDA;
174		WRA(t);
175
176		CLR_NZC;
177		SET_C8(t);
178		SET_N8(t);
179		SET_Z8(t);
180
181	53	m_icount -= 8;
	54	UINT8 r = imm8();
	55	AM_WB(write_r8, r, read_r8(r), read_r8(0));
182	56	}
183	57
184		void tms7000_device::add_r2b()
	58	void tms7000_device::am_b2a(op_func op)
185	59	{
186		UINT16  t;
187		UINT8   v;
188
189		IMMBYTE(v);
190
191		t = RM(v) + RDB;
192		WRB(t);
193
194		CLR_NZC;
195		SET_C8(t);
196		SET_N8(t);
197		SET_Z8(t);
198
199		m_icount -= 8;
	60	m_icount -= 5;
	61	AM_WB(write_r8, 0, read_r8(0), read_r8(1));
200	62	}
201	63
202		void tms7000_device::add_r2r()
	64	void tms7000_device::am_b2b(op_func op)
203	65	{
204		UINT16  t;
205		UINT8   i,j;
206
207		IMMBYTE(i);
208		IMMBYTE(j);
209
210		t = RM(i)+RM(j);
211		WM(j,t);
212
213		CLR_NZC;
214		SET_C8(t);
215		SET_N8(t);
216		SET_Z8(t);
217
218		m_icount -= 10;
	66	m_icount -= 6;
	67	AM_WB(write_r8, 1, read_r8(1), read_r8(1));
219	68	}
220	69
221		void tms7000_device::add_i2a()
	70	void tms7000_device::am_b2r(op_func op)
222	71	{
223		UINT16  t;
224		UINT8   v;
225
226		IMMBYTE(v);
227
228		t = v + RDA;
229		WRA(t);
230
231		CLR_NZC;
232		SET_C8(t);
233		SET_N8(t);
234		SET_Z8(t);
235
236	72	m_icount -= 7;
	73	UINT8 r = imm8();
	74	AM_WB(write_r8, r, read_r8(r), read_r8(1));
237	75	}
238	76
239		void tms7000_device::add_i2b()
	77	void tms7000_device::am_b2p(op_func op)
240	78	{
241		UINT16  t;
242		UINT8   v;
243
244		IMMBYTE(v);
245
246		t = v + RDB;
247		WRB(t);
248
249		CLR_NZC;
250		SET_C8(t);
251		SET_N8(t);
252		SET_Z8(t);
253
254		m_icount -= 7;
255		}
256
257		void tms7000_device::add_i2r()
258		{
259		UINT16  t;
260		UINT8   i,j;
261
262		IMMBYTE(i);
263		IMMBYTE(j);
264
265		t = i+RM(j);
266		WM(j,t);
267
268		CLR_NZC;
269		SET_C8(t);
270		SET_N8(t);
271		SET_Z8(t);
272
273	79	m_icount -= 9;
	80	UINT8 r = imm8();
	81	AM_WB(write_p, r, read_p(r), read_r8(1));
274	82	}
275	83
276		void tms7000_device::and_b2a()
	84	void tms7000_device::am_r2a(op_func op)
277	85	{
278		UINT8   t;
279
280		t = RDA & RDB;
281		WRA(t);
282
283		CLR_NZC;
284		SET_N8(t);
285		SET_Z8(t);
286
287		m_icount -= 5;
288		}
289
290		void tms7000_device::and_r2a()
291		{
292		UINT8   t;
293		UINT8   v;
294
295		IMMBYTE(v);
296
297		t = RM(v) & RDA;
298		WRA(t);
299
300		CLR_NZC;
301		SET_N8(t);
302		SET_Z8(t);
303
304	86	m_icount -= 8;
	87	AM_WB(write_r8, 0, read_r8(0), read_r8(imm8()));
305	88	}
306	89
307		void tms7000_device::and_r2b()
	90	void tms7000_device::am_r2b(op_func op)
308	91	{
309		UINT8   t;
310		UINT8   v;
311
312		IMMBYTE(v);
313
314		t = RM(v) & RDB;
315		WRB(t);
316
317		CLR_NZC;
318		SET_N8(t);
319		SET_Z8(t);
320
321	92	m_icount -= 8;
	93	AM_WB(write_r8, 1, read_r8(1), read_r8(imm8()));
322	94	}
323	95
324		void tms7000_device::and_r2r()
	96	void tms7000_device::am_r2r(op_func op)
325	97	{
326		UINT8   t;
327		UINT8   i,j;
328
329		IMMBYTE(i);
330		IMMBYTE(j);
331
332		t = RM(i) & RM(j);
333		WM(j,t);
334
335		CLR_NZC;
336		SET_N8(t);
337		SET_Z8(t);
338
339	98	m_icount -= 10;
	99	UINT8 param2 = read_r8(imm8());
	100	UINT8 r = imm8();
	101	AM_WB(write_r8, r, read_r8(r), param2);
340	102	}
341	103
342		void tms7000_device::and_i2a()
	104	void tms7000_device::am_i2a(op_func op)
343	105	{
344		UINT8   t;
345		UINT8   v;
346
347		IMMBYTE(v);
348
349		t = v & RDA;
350		WRA(t);
351
352		CLR_NZC;
353		SET_N8(t);
354		SET_Z8(t);
355
356	106	m_icount -= 7;
	107	AM_WB(write_r8, 0, read_r8(0), imm8());
357	108	}
358	109
359		void tms7000_device::and_i2b()
	110	void tms7000_device::am_i2b(op_func op)
360	111	{
361		UINT8   t;
362		UINT8   v;
363
364		IMMBYTE(v);
365
366		t = v & RDB;
367		WRB(t);
368
369		CLR_NZC;
370		SET_N8(t);
371		SET_Z8(t);
372
373	112	m_icount -= 7;
	113	AM_WB(write_r8, 1, read_r8(1), imm8());
374	114	}
375	115
376		void tms7000_device::and_i2r()
	116	void tms7000_device::am_i2r(op_func op)
377	117	{
378		UINT8   t;
379		UINT8   i,j;
380
381		IMMBYTE(i);
382		IMMBYTE(j);
383
384		t = i & RM(j);
385		WM(j,t);
386
387		CLR_NZC;
388		SET_N8(t);
389		SET_Z8(t);
390
391	118	m_icount -= 9;
	119	UINT8 param2 = imm8();
	120	UINT8 r = imm8();
	121	AM_WB(write_r8, r, read_r8(r), param2);
392	122	}
393	123
394		void tms7000_device::andp_a2p()
	124	void tms7000_device::am_i2p(op_func op)
395	125	{
396		UINT8   t;
397		UINT8   v;
398
399		IMMBYTE(v);
400		t = RDA & RM( 0x0100 + v);
401		WM( 0x0100+v, t);
402
403		CLR_NZC;
404		SET_N8(t);
405		SET_Z8(t);
406
407		m_icount -= 10;
	126	m_icount -= 11;
	127	UINT8 param2 = imm8();
	128	UINT8 r = imm8();
	129	AM_WB(write_p, r, read_p(r), param2);
408	130	}
409	131
410		void tms7000_device::andp_b2p()
	132	void tms7000_device::am_p2a(op_func op)
411	133	{
412		UINT8   t;
413		UINT8   v;
414
415		IMMBYTE(v);
416		t = RDB & RM( 0x0100 + v);
417		WM( 0x0100+v, t);
418
419		CLR_NZC;
420		SET_N8(t);
421		SET_Z8(t);
422
423	134	m_icount -= 9;
	135	AM_WB(write_r8, 0, read_r8(0), read_p(imm8()));
424	136	}
425	137
426
427		void tms7000_device::movp_i2p()
	138	void tms7000_device::am_p2b(op_func op)
428	139	{
429		UINT8   i,v;
430
431		IMMBYTE(i);
432		IMMBYTE(v);
433		WM( 0x0100+v, i);
434
435		CLR_NZC;
436		SET_N8(i);
437		SET_Z8(i);
438
439		m_icount -= 11;
	140	m_icount -= 8;
	141	AM_WB(write_r8, 1, read_r8(1), read_p(imm8()));
440	142	}
441	143
442		void tms7000_device::andp_i2p()
443		{
444		UINT8   t;
445		UINT8   i,v;
446	144
447		IMMBYTE(i);
448		IMMBYTE(v);
449		t = i & RM( 0x0100 + v);
450		WM( 0x0100+v, t);
451	145
452		CLR_NZC;
453		SET_N8(t);
454		SET_Z8(t);
455
456		m_icount -= 11;
457		}
458
459		void tms7000_device::br_dir()
	146	// common opcodes
	147	// 1 param
	148	int tms7000_device::op_clr(UINT8 param1, UINT8 param2)
460	149	{
461		PAIR p;
462
463		IMMWORD( p );
464		pPC = p.d;
465		m_icount -= 10;
	150	UINT8 t = 0;
	151	SET_CNZ(t);
	152	return t;
466	153	}
467	154
468		void tms7000_device::br_ind()
	155	int tms7000_device::op_dec(UINT8 param1, UINT8 param2)
469	156	{
470		UINT8   v;
471
472		IMMBYTE( v );
473		PC.w.l = RRF16(v);
474
475		m_icount -= 9;
	157	UINT16 t = param1 - 1;
	158	SET_NZ(t);
	159	SET_C(~t);
	160	return t;
476	161	}
477	162
478		void tms7000_device::br_inx()
	163	int tms7000_device::op_inc(UINT8 param1, UINT8 param2)
479	164	{
480		PAIR p;
481
482		IMMWORD( p );
483		pPC = p.w.l + RDB;
484		m_icount -= 12;
	165	UINT16 t = param1 + 1;
	166	SET_CNZ(t);
	167	return t;
485	168	}
486	169
487		void tms7000_device::btjo_b2a()
	170	int tms7000_device::op_inv(UINT8 param1, UINT8 param2)
488	171	{
489		UINT8   t;
490
491		t = RDB & RDA;
492
493		CLR_NZC;
494		SET_N8(t);
495		SET_Z8(t);
496
497		if(t != 0)
498		{
499		INT8    j;
500
501		SIMMBYTE( j );
502		pPC += j;
503		m_icount -= 9;
504		}
505		else
506		{
507		pPC++;
508		m_icount -= 7;
509		}
	172	UINT8 t = ~param1;
	173	SET_CNZ(t);
	174	return t;
510	175	}
511	176
512		void tms7000_device::btjo_r2a()
	177	int tms7000_device::op_rl(UINT8 param1, UINT8 param2)
513	178	{
514		UINT8   t,r;
515
516		IMMBYTE( r );
517		t = RM( r ) & RDA;
518
519		CLR_NZC;
520		SET_N8(t);
521		SET_Z8(t);
522
523		if(t != 0)
524		{
525		INT8    j;
526
527		SIMMBYTE( j );
528		pPC += j;
529		m_icount -= 9;
530		}
531		else
532		{
533		pPC++;
534		m_icount -= 7;
535		}
	179	UINT16 t = param1 << 1 | param1 >> 7;
	180	SET_CNZ(t);
	181	return t;
536	182	}
537	183
538		void tms7000_device::btjo_r2b()
	184	int tms7000_device::op_rlc(UINT8 param1, UINT8 param2)
539	185	{
540		UINT8   t,r;
541
542		IMMBYTE(r);
543		t = RM(r) & RDB;
544
545		CLR_NZC;
546		SET_N8(t);
547		SET_Z8(t);
548
549		if(t != 0)
550		{
551		INT8    j;
552
553		SIMMBYTE(j);
554		pPC += j;
555		m_icount -= 12;
556		}
557		else
558		{
559		pPC++;
560		m_icount -= 10;
561		}
	186	UINT16 t = param1 << 1 | GET_C();
	187	SET_CNZ(t);
	188	return t;
562	189	}
563	190
564		void tms7000_device::btjo_r2r()
	191	int tms7000_device::op_rr(UINT8 param1, UINT8 param2)
565	192	{
566		UINT8   t,r,s;
567
568		IMMBYTE(r);
569		IMMBYTE(s);
570		t = RM(r) & RM(s);
571
572		CLR_NZC;
573		SET_N8(t);
574		SET_Z8(t);
575
576		if(t != 0)
577		{
578		INT8    j;
579
580		SIMMBYTE(j);
581		pPC += j;
582		m_icount -= 14;
583		}
584		else
585		{
586		pPC++;
587		m_icount -= 12;
588		}
	193	UINT16 t = param1 >> 1 | param1 << 8 | (param1 << 7 & 0x80);
	194	SET_CNZ(t);
	195	return t;
589	196	}
590	197
591		void tms7000_device::btjo_i2a()
	198	int tms7000_device::op_rrc(UINT8 param1, UINT8 param2)
592	199	{
593		UINT8   t,r;
594
595		IMMBYTE(r);
596		t = r & RDA;
597
598		CLR_NZC;
599		SET_N8(t);
600		SET_Z8(t);
601
602		if(t != 0)
603		{
604		INT8    j;
605
606		SIMMBYTE(j);
607		pPC += j;
608		m_icount -= 11;
609		}
610		else
611		{
612		pPC++;
613		m_icount -= 9;
614		}
	200	UINT16 t = param1 >> 1 | param1 << 8 | GET_C() << 7;
	201	SET_CNZ(t);
	202	return t;
615	203	}
616	204
617		void tms7000_device::btjo_i2b()
	205	int tms7000_device::op_swap(UINT8 param1, UINT8 param2)
618	206	{
619		UINT8   t,i;
620
621		IMMBYTE(i);
622		t = i & RDB;
623
624		CLR_NZC;
625		SET_N8(t);
626		SET_Z8(t);
627
628		if(t != 0)
629		{
630		INT8    j;
631
632		SIMMBYTE(j);
633		pPC += j;
634		m_icount -= 11;
635		}
636		else
637		{
638		pPC++;
639		m_icount -= 9;
640		}
	207	m_icount -= 3;
	208	UINT16 t = param1 >> 4 | param1 << 4;
	209	SET_CNZ(t);
	210	return t;
641	211	}
642	212
643		void tms7000_device::btjo_i2r()
	213	int tms7000_device::op_xchb(UINT8 param1, UINT8 param2)
644	214	{
645		UINT8   t,i,r;
646
647		IMMBYTE(i);
648		IMMBYTE(r);
649		t = i & RM(r);
650
651		CLR_NZC;
652		SET_N8(t);
653		SET_Z8(t);
654
655		if(t != 0)
656		{
657		INT8    j;
658
659		SIMMBYTE(j);
660		pPC += j;
661		m_icount -= 13;
662		}
663		else
664		{
665		pPC++;
666		m_icount -= 11;
667		}
	215	m_icount -= 1;
	216	UINT8 t = read_r8(1);
	217	SET_CNZ(t);
	218	write_r8(1, param1);
	219	return t;
668	220	}
669	221
670		void tms7000_device::btjop_ap()
	222	// 2 params
	223	int tms7000_device::op_adc(UINT8 param1, UINT8 param2)
671	224	{
672		UINT8   t,p;
673
674		IMMBYTE(p);
675
676		t = RM(0x100+p) & RDA;
677
678		CLR_NZC;
679		SET_N8(t);
680		SET_Z8(t);
681
682		if(t != 0)
683		{
684		INT8    j;
685
686		SIMMBYTE(j);
687		pPC += j;
688		m_icount -= 13;
689		}
690		else
691		{
692		pPC++;
693		m_icount -= 11;
694		}
	225	UINT16 t = param1 + param2 + GET_C();
	226	SET_CNZ(t);
	227	return t;
695	228	}
696	229
697		void tms7000_device::btjop_bp()
	230	int tms7000_device::op_add(UINT8 param1, UINT8 param2)
698	231	{
699		UINT8   t,p;
700
701		IMMBYTE(p);
702
703		t = RM(0x100+p) & RDB;
704
705		CLR_NZC;
706		SET_N8(t);
707		SET_Z8(t);
708
709		if(t != 0)
710		{
711		INT8    j;
712
713		SIMMBYTE(j);
714		pPC += j;
715		m_icount -= 12;
716		}
717		else
718		{
719		pPC++;
720		m_icount -= 10;
721		}
	232	UINT16 t = param1 + param2;
	233	SET_CNZ(t);
	234	return t;
722	235	}
723	236
724		void tms7000_device::btjop_ip()
	237	int tms7000_device::op_and(UINT8 param1, UINT8 param2)
725	238	{
726		UINT8   t,p,i;
727
728		IMMBYTE(i);
729		IMMBYTE(p);
730
731		t = RM(0x100+p) & i;
732
733		CLR_NZC;
734		SET_N8(t);
735		SET_Z8(t);
736
737		if(t != 0)
738		{
739		INT8    j;
740
741		SIMMBYTE(j);
742		pPC += j;
743		m_icount -= 14;
744		}
745		else
746		{
747		pPC++;
748		m_icount -= 12;
749		}
	239	UINT8 t = param1 & param2;
	240	SET_CNZ(t);
	241	return t;
750	242	}
751	243
752		void tms7000_device::btjz_b2a()
	244	int tms7000_device::op_cmp(UINT8 param1, UINT8 param2)
753	245	{
754		UINT8   t;
755
756		t = RDB & (~RDA);
757
758		CLR_NZC;
759		SET_N8(t);
760		SET_Z8(t);
761
762		if(t != 0)
763		{
764		INT8    j;
765
766		SIMMBYTE( j );
767		pPC += j;
768		m_icount -= 9;
769		}
770		else
771		{
772		pPC++;
773		m_icount -= 7;
774		}
	246	UINT16 t = param1 - param2;
	247	SET_NZ(t);
	248	SET_C(~t);
	249	return WB_NO;
775	250	}
776	251
777		void tms7000_device::btjz_r2a()
	252	int tms7000_device::op_mpy(UINT8 param1, UINT8 param2)
778	253	{
779		UINT8   t,r;
780
781		IMMBYTE( r );
782		t = RM( r ) & (~RDA);
783
784		CLR_NZC;
785		SET_N8(t);
786		SET_Z8(t);
787
788		if(t != 0)
789		{
790		INT8    j;
791
792		SIMMBYTE( j );
793		pPC += j;
794		m_icount -= 9;
795		}
796		else
797		{
798		pPC++;
799		m_icount -= 7;
800		}
	254	m_icount -= 39;
	255	UINT16 t = param1 * param2;
	256	SET_CNZ(t >> 8 & 0xff);
	257	write_mem16(0, t); // always writes result to regs A-B
	258	return WB_NO;
801	259	}
802	260
803		void tms7000_device::btjz_r2b()
	261	int tms7000_device::op_mov(UINT8 param1, UINT8 param2)
804	262	{
805		UINT8   t,r;
806
807		IMMBYTE(r);
808		t = RM(r) & (~RDB);
809
810		CLR_NZC;
811		SET_N8(t);
812		SET_Z8(t);
813
814		if(t != 0)
815		{
816		INT8    j;
817
818		SIMMBYTE(j);
819		pPC += j;
820		m_icount -= 12;
821		}
822		else
823		{
824		pPC++;
825		m_icount -= 10;
826		}
	263	UINT8 t = param2;
	264	SET_CNZ(t);
	265	return t;
827	266	}
828	267
829		void tms7000_device::btjz_r2r()
	268	int tms7000_device::op_or(UINT8 param1, UINT8 param2)
830	269	{
831		UINT8   t,r,s;
832
833		IMMBYTE(r);
834		IMMBYTE(s);
835		t = RM(r) & (~RM(s));
836
837		CLR_NZC;
838		SET_N8(t);
839		SET_Z8(t);
840
841		if(t != 0)
842		{
843		INT8    j;
844
845		SIMMBYTE(j);
846		pPC += j;
847		m_icount -= 14;
848		}
849		else
850		{
851		pPC++;
852		m_icount -= 12;
853		}
	270	UINT8 t = param1 | param2;
	271	SET_CNZ(t);
	272	return t;
854	273	}
855	274
856		void tms7000_device::btjz_i2a()
	275	int tms7000_device::op_sbb(UINT8 param1, UINT8 param2)
857	276	{
858		UINT8   t,r;
859
860		IMMBYTE(r);
861		t = r & (~RDA);
862
863		CLR_NZC;
864		SET_N8(t);
865		SET_Z8(t);
866
867		if(t != 0)
868		{
869		INT8    j;
870
871		SIMMBYTE(j);
872		pPC += j;
873		m_icount -= 11;
874		}
875		else
876		{
877		pPC++;
878		m_icount -= 9;
879		}
	277	UINT8 t = param1 - param2 - (!GET_C());
	278	SET_NZ(t);
	279	SET_C(~t);
	280	return t;
880	281	}
881	282
882		void tms7000_device::btjz_i2b()
	283	int tms7000_device::op_sub(UINT8 param1, UINT8 param2)
883	284	{
884		UINT8   t,i;
885
886		IMMBYTE(i);
887		t = i & (~RDB);
888
889		CLR_NZC;
890		SET_N8(t);
891		SET_Z8(t);
892
893		if(t != 0)
894		{
895		INT8    j;
896
897		SIMMBYTE(j);
898		pPC += j;
899		m_icount -= 11;
900		}
901		else
902		{
903		pPC++;
904		m_icount -= 9;
905		}
	285	UINT16 t = param1 - param2;
	286	SET_NZ(t);
	287	SET_C(~t);
	288	return t;
906	289	}
907	290
908		void tms7000_device::btjz_i2r()
	291	int tms7000_device::op_xor(UINT8 param1, UINT8 param2)
909	292	{
910		UINT8   t,i,r;
911
912		IMMBYTE(i);
913		IMMBYTE(r);
914		t = i & (~RM(r));
915
916		CLR_NZC;
917		SET_N8(t);
918		SET_Z8(t);
919
920		if(t != 0)
921		{
922		INT8    j;
923
924		SIMMBYTE(j);
925		pPC += j;
926		m_icount -= 13;
927		}
928		else
929		{
930		pPC++;
931		m_icount -= 11;
932		}
	293	UINT8 t = param1 ^ param2;
	294	SET_CNZ(t);
	295	return t;
933	296	}
934	297
935		void tms7000_device::btjzp_ap()
	298	// BCD arthrimetic handling
	299	static const UINT8 lut_bcd_out[6] = { 0x00, 0x06, 0x00, 0x66, 0x60, 0x66 };
	300
	301	int tms7000_device::op_dac(UINT8 param1, UINT8 param2)
936	302	{
937		UINT8   t,p;
	303	m_icount -= 2;
	304	int c = GET_C();
938	305
939		IMMBYTE(p);
940
941		t = RDA & (~RM(0x100+p));
942
943		CLR_NZC;
944		SET_N8(t);
945		SET_Z8(t);
946
947		if(t != 0)
948		{
949		INT8    j;
950
951		SIMMBYTE(j);
952		pPC += j;
953		m_icount -= 13;
954		}
955		else
956		{
957		pPC++;
958		m_icount -= 11;
959		}
	306	UINT8 h1 = param1 >> 4 & 0xf;
	307	UINT8 l1 = param1 >> 0 & 0xf;
	308	UINT8 h2 = param2 >> 4 & 0xf;
	309	UINT8 l2 = param2 >> 0 & 0xf;
	310
	311	// compute bcd constant
	312	UINT8 d = ((l1 + l2 + c) < 10) ? 0 : 1;
	313	if ((h1 + h2) == 9)
	314	d |= 2;
	315	else if ((h1 + h2) > 9)
	316	d |= 4;
	317
	318	UINT8 t = param1 + param2 + c + lut_bcd_out[d];
	319	SET_CNZ(t);
	320	if (d > 2)
	321	m_sr |= SR_C;
	322
	323	return t;
960	324	}
961	325
962		void tms7000_device::btjzp_bp()
	326	int tms7000_device::op_dsb(UINT8 param1, UINT8 param2)
963	327	{
964		UINT8   t,p;
	328	m_icount -= 2;
	329	int c = !GET_C();
965	330
966		IMMBYTE(p);
	331	UINT8 h1 = param1 >> 4 & 0xf;
	332	UINT8 l1 = param1 >> 0 & 0xf;
	333	UINT8 h2 = param2 >> 4 & 0xf;
	334	UINT8 l2 = param2 >> 0 & 0xf;
967	335
968		t = RDB & (~RM(0x100+p));
	336	// compute bcd constant
	337	UINT8 d = ((l1 - c) >= l2) ? 0 : 1;
	338	if (h1 == h2)
	339	d |= 2;
	340	else if (h1 < h2)
	341	d |= 4;
969	342
970		CLR_NZC;
971		SET_N8(t);
972		SET_Z8(t);
973
974		if(t != 0)
975		{
976		INT8    j;
977
978		SIMMBYTE(j);
979		pPC += j;
980		m_icount -= 12;
981		}
982		else
983		{
984		pPC++;
985		m_icount -= 10;
986		}
	343	UINT8 t = param1 - param2 - c - lut_bcd_out[d];
	344	SET_CNZ(t);
	345	if (d <= 2)
	346	m_sr |= SR_C;
	347
	348	return t;
987	349	}
988	350
989		void tms7000_device::btjzp_ip()
	351	// branches
	352	inline void tms7000_device::shortbranch(bool check)
990	353	{
991		UINT8   t,p,i;
	354	m_icount -= 2;
	355	INT8 d = (INT8)imm8();
992	356
993		IMMBYTE(i);
994		IMMBYTE(p);
995
996		t = i & (~RM(0x100+p));
997
998		CLR_NZC;
999		SET_N8(t);
1000		SET_Z8(t);
1001
1002		if(t != 0)
	357	if (check)
1003	358	{
1004		INT8    j;
1005
1006		SIMMBYTE(j);
1007		pPC += j;
1008		m_icount -= 14;
	359	m_pc += d;
	360	m_icount -= 2;
1009	361	}
1010		else
1011		{
1012		pPC++;
1013		m_icount -= 12;
1014		}
1015	362	}
1016	363
1017		void tms7000_device::call_dir()
	364	inline void tms7000_device::jmp(bool check)
1018	365	{
1019		PAIR    tPC;
1020
1021		IMMWORD( tPC );
1022		PUSHWORD( PC );
1023		pPC = tPC.d;
1024
1025		m_icount -= 14;
	366	m_icount -= 3;
	367	shortbranch(check);
1026	368	}
1027	369
1028		void tms7000_device::call_ind()
	370	int tms7000_device::op_djnz(UINT8 param1, UINT8 param2)
1029	371	{
1030		UINT8   v;
1031
1032		IMMBYTE( v );
1033		PUSHWORD( PC );
1034		PC.w.l = RRF16(v);
1035
1036		m_icount -= 13;
	372	UINT16 t = param1 - 1;
	373	shortbranch(t != 0);
	374	return t;
1037	375	}
1038	376
1039		void tms7000_device::call_inx()
	377	int tms7000_device::op_btjo(UINT8 param1, UINT8 param2)
1040	378	{
1041		PAIR    tPC;
1042
1043		IMMWORD( tPC );
1044		PUSHWORD( PC );
1045		pPC = tPC.w.l + RDB;
1046		m_icount -= 16;
	379	UINT8 t = param1 & param2;
	380	SET_CNZ(t);
	381	shortbranch(t != 0);
	382	return WB_NO;
1047	383	}
1048	384
1049		void tms7000_device::clr_a()
	385	int tms7000_device::op_btjz(UINT8 param1, UINT8 param2)
1050	386	{
1051		WRA(0);
1052		CLR_NZC;
1053		SETZ;
1054		m_icount -= 5;
	387	UINT8 t = ~param1 & param2;
	388	SET_CNZ(t);
	389	shortbranch(t != 0);
	390	return WB_NO;
1055	391	}
1056	392
1057		void tms7000_device::clr_b()
1058		{
1059		WRB(0);
1060		CLR_NZC;
1061		SETZ;
1062		m_icount -= 5;
1063		}
1064	393
1065		void tms7000_device::clr_r()
1066		{
1067		UINT8   r;
1068	394
1069		IMMBYTE(r);
1070		WM(r,0);
1071		CLR_NZC;
1072		SETZ;
1073		m_icount -= 7;
1074		}
1075
1076		void tms7000_device::clrc()
1077		{
1078		UINT8   a;
1079
1080		a = RDA;
1081
1082		CLR_NZC;
1083		SET_N8(a);
1084		SET_Z8(a);
1085
1086		m_icount -= 6;
1087		}
1088
1089		void tms7000_device::cmp_ba()
1090		{
1091		UINT16 t;
1092
1093		t = RDA - RDB;
1094
1095		CLR_NZC;
1096		SET_N8(t);
1097		SET_Z8(t);
1098
1099		SET_C8( ~t );
1100		m_icount -= 5;
1101		}
1102
1103		void tms7000_device::cmp_ra()
1104		{
1105		UINT16  t;
1106		UINT8   r;
1107
1108		IMMBYTE(r);
1109		t = RDA - RM(r);
1110
1111		CLR_NZC;
1112		SET_N8(t);
1113		SET_Z8(t);
1114
1115		SET_C8( ~t );
1116
1117		m_icount -= 8;
1118		}
1119
1120		void tms7000_device::cmp_rb()
1121		{
1122		UINT16  t;
1123		UINT8   r;
1124
1125		IMMBYTE(r);
1126		t = RDB - RM(r);
1127
1128		CLR_NZC;
1129		SET_N8(t);
1130		SET_Z8(t);
1131
1132		SET_C8( ~t );
1133
1134		m_icount -= 8;
1135		}
1136
1137		void tms7000_device::cmp_rr()
1138		{
1139		UINT16  t;
1140		UINT8   r,s;
1141
1142		IMMBYTE(r);
1143		IMMBYTE(s);
1144		t = RM(s) - RM(r);
1145
1146		CLR_NZC;
1147		SET_N8(t);
1148		SET_Z8(t);
1149
1150		SET_C8( ~t );
1151
1152		m_icount -= 10;
1153		}
1154
1155		void tms7000_device::cmp_ia()
1156		{
1157		UINT16  t;
1158		UINT8   i;
1159
1160		IMMBYTE(i);
1161		t = RDA - i;
1162
1163		CLR_NZC;
1164		SET_N8(t);
1165		SET_Z8(t);
1166
1167		SET_C8( ~t );
1168
1169		m_icount -= 7;
1170		}
1171
1172		void tms7000_device::cmp_ib()
1173		{
1174		UINT16  t;
1175		UINT8   i;
1176
1177		IMMBYTE(i);
1178		t = RDB - i;
1179
1180		CLR_NZC;
1181		SET_N8(t);
1182		SET_Z8(t);
1183		SET_C8( ~t );
1184
1185		m_icount -= 7;
1186		}
1187
1188		void tms7000_device::cmp_ir()
1189		{
1190		UINT16  t;
1191		UINT8   i,r;
1192
1193		IMMBYTE(i);
1194		IMMBYTE(r);
1195		t = RM(r) - i;
1196
1197		CLR_NZC;
1198		SET_N8(t);
1199		SET_Z8(t);
1200		SET_C8( ~t );
1201
1202		m_icount -= 9;
1203		}
1204
1205		void tms7000_device::cmpa_dir()
1206		{
1207		UINT16  t;
1208		PAIR    i;
1209
1210		IMMWORD( i );
1211		t = RDA - RM(i.w.l);
1212
1213		CLR_NZC;
1214		SET_N8(t);
1215		SET_Z8(t);
1216		SET_C8( ~t );
1217
1218		m_icount -= 12;
1219		}
1220
1221		void tms7000_device::cmpa_ind()
1222		{
1223		UINT16  t;
1224		PAIR    p;
1225		INT8    i;
1226
1227		IMMBYTE(i);
1228		p.w.l = RRF16(i);
1229		t = RDA - RM(p.w.l);
1230
1231		CLR_NZC;
1232		SET_N8(t);
1233		SET_Z8(t);
1234		SET_C8( ~t );
1235
1236		m_icount -= 11;
1237		}
1238
1239		void tms7000_device::cmpa_inx()
1240		{
1241		UINT16  t;
1242		PAIR    i;
1243
1244		IMMWORD( i );
1245		t = RDA - RM(i.w.l + RDB);
1246
1247		CLR_NZC;
1248		SET_N8(t);
1249		SET_Z8(t);
1250		SET_C8( ~t );
1251
1252		m_icount -= 14;
1253		}
1254
1255		void tms7000_device::dac_b2a()
1256		{
1257		WRA(bcd_add(RDA, RDB, pSR & SR_C));
1258
1259		m_icount -= 7;
1260		}
1261
1262		void tms7000_device::dac_r2a()
1263		{
1264		UINT8 r;
1265		IMMBYTE(r);
1266
1267		WRA(bcd_add(RDA, RM(r), pSR & SR_C));
1268
1269		m_icount -= 10;
1270		}
1271
1272		void tms7000_device::dac_r2b()
1273		{
1274		UINT8 r;
1275		IMMBYTE(r);
1276
1277		WRB(bcd_add(RDB, RM(r), pSR & SR_C));
1278
1279		m_icount -= 10;
1280		}
1281
1282		void tms7000_device::dac_r2r()
1283		{
1284		UINT8 s, r;
1285		IMMBYTE(s);
1286		IMMBYTE(r);
1287
1288		WM(r, bcd_add(RM(s), RM(r), pSR & SR_C));
1289
1290		m_icount -= 12;
1291		}
1292
1293		void tms7000_device::dac_i2a()
1294		{
1295		UINT8 i;
1296		IMMBYTE(i);
1297
1298		WRA(bcd_add(i, RDA, pSR & SR_C));
1299
1300		m_icount -= 9;
1301		}
1302
1303		void tms7000_device::dac_i2b()
1304		{
1305		UINT8 i;
1306		IMMBYTE(i);
1307
1308		WRB(bcd_add(i, RDB, pSR & SR_C));
1309
1310		m_icount -= 9;
1311		}
1312
1313		void tms7000_device::dac_i2r()
1314		{
1315		UINT8 i, r;
1316		IMMBYTE(i);
1317		IMMBYTE(r);
1318
1319		WM(r, bcd_add(i, RM(r), pSR & SR_C));
1320
1321		m_icount -= 11;
1322		}
1323
1324		void tms7000_device::dec_a()
1325		{
1326		UINT16 t;
1327
1328		t = RDA - 1;
1329
1330		WRA( t );
1331
1332		CLR_NZC;
1333		SET_N8(t);
1334		SET_Z8(t);
1335		if ((t&0xFF)!=0xFF) SETC;
1336
1337		m_icount -= 5;
1338		}
1339
1340		void tms7000_device::dec_b()
1341		{
1342		UINT16 t;
1343
1344		t = RDB - 1;
1345
1346		WRB( t );
1347
1348		CLR_NZC;
1349		SET_N8(t);
1350		SET_Z8(t);
1351		if ((t&0xFF)!=0xFF) SETC;
1352
1353		m_icount -= 5;
1354		}
1355
1356		void tms7000_device::dec_r()
1357		{
1358		UINT16  t;
1359		UINT8   r;
1360
1361		IMMBYTE(r);
1362
1363		t = RM(r) - 1;
1364
1365		WM( r, t );
1366
1367		CLR_NZC;
1368		SET_N8(t);
1369		SET_Z8(t);
1370		if ((t&0xFF)!=0xFF) SETC;
1371
1372		m_icount -= 7;
1373		}
1374
	395	// other opcodes
	396	// dec double
1375	397	void tms7000_device::decd_a()
1376	398	{
1377		PAIR    t;
1378
1379		t.w.h = 0;
1380		t.w.l = RRF16(0);
1381		t.d -= 1;
1382		WRF16(0,t);
1383
1384		CLR_NZC;
1385
1386		SET_N16(t.d);
1387
1388		if ((t.d&0xFF00)==0) SETZ;
1389		if ((t.d&0xFFFF)!=0xFFFF) SETC;
1390
1391
1392	399	m_icount -= 9;
	400	UINT32 t = read_r16(0) - 1;
	401	write_r16(0, t);
	402	SET_NZ(t >> 8);
	403	SET_C(~(t >> 8));
1393	404	}
1394	405
1395	406	void tms7000_device::decd_b()
1396	407	{
1397		PAIR    t;
1398
1399		t.w.h = 0;
1400		t.w.l = RRF16(1);
1401		t.d -= 1;
1402		WRF16(1,t);
1403
1404		CLR_NZC;
1405		SET_N16(t.d);
1406
1407		if ((t.d&0xFF00)==0) SETZ;
1408		if ((t.d&0xFFFF)!=0xFFFF) SETC;
1409
1410	408	m_icount -= 9;
	409	UINT32 t = read_r16(1) - 1;
	410	write_r16(1, t);
	411	SET_NZ(t >> 8);
	412	SET_C(~(t >> 8));
1411	413	}
1412	414
1413	415	void tms7000_device::decd_r()
1414	416	{
1415		UINT8   r;
1416		PAIR    t;
1417
1418		IMMBYTE(r);
1419		t.w.h = 0;
1420		t.w.l = RRF16(r);
1421		t.d -= 1;
1422		WRF16(r,t);
1423
1424		CLR_NZC;
1425		SET_N16(t.d);
1426
1427		if ((t.d&0xFF00)==0) SETZ;
1428		if ((t.d&0xFFFF)!=0xFFFF) SETC;
1429
1430	417	m_icount -= 11;
	418	UINT8 r = imm8();
	419	UINT32 t = read_r16(r) - 1;
	420	write_r16(r, t);
	421	SET_NZ(t >> 8);
	422	SET_C(~(t >> 8));
1431	423	}
1432	424
1433		void tms7000_device::dint()
	425	// cmpa extended
	426	void tms7000_device::cmpa_dir()
1434	427	{
1435		CLR_NZCI;
1436		m_icount -= 5;
1437		}
1438
1439		void tms7000_device::djnz_a()
1440		{
1441		UINT16 t;
1442
1443		t = RDA - 1;
1444
1445		WRA( t );
1446
1447		if( t != 0 )
1448		{
1449		INT8    s;
1450
1451		SIMMBYTE(s);
1452		pPC += s;
1453		m_icount -= 7;
1454		}
1455		else
1456		{
1457		pPC++;
1458		m_icount -= 2;
1459		}
1460		}
1461
1462		void tms7000_device::djnz_b()
1463		{
1464		UINT16 t;
1465
1466		t = RDB - 1;
1467
1468		WRB( t );
1469
1470		if( t != 0 )
1471		{
1472		INT8    s;
1473
1474		SIMMBYTE(s);
1475		pPC += s;
1476		m_icount -= 7;
1477		}
1478		else
1479		{
1480		pPC++;
1481		m_icount -= 2;
1482		}
1483		}
1484
1485		void tms7000_device::djnz_r()
1486		{
1487		UINT16  t;
1488		UINT8   r;
1489
1490		IMMBYTE(r);
1491
1492		t = RM(r) - 1;
1493
1494		WM(r,t);
1495		if( t != 0 )
1496		{
1497		INT8    s;
1498
1499		SIMMBYTE(s);
1500		pPC += s;
1501		m_icount -= 9;
1502		}
1503		else
1504		{
1505		pPC++;
1506		m_icount -= 3;
1507		}
1508		}
1509
1510		void tms7000_device::dsb_b2a()
1511		{
1512		WRA(bcd_sub(RDA, RDB, pSR & SR_C));
1513
1514		m_icount -= 7;
1515		}
1516
1517		void tms7000_device::dsb_r2a()
1518		{
1519		UINT8 r;
1520		IMMBYTE(r);
1521
1522		WRA(bcd_sub(RDA, RM(r), pSR & SR_C));
1523
1524		m_icount -= 10;
1525		}
1526
1527		void tms7000_device::dsb_r2b()
1528		{
1529		UINT8 r;
1530		IMMBYTE(r);
1531
1532		WRB(bcd_sub(RDB, RM(r), pSR & SR_C));
1533
1534		m_icount -= 10;
1535		}
1536
1537		void tms7000_device::dsb_r2r()
1538		{
1539		UINT8 s, r;
1540		IMMBYTE(s);
1541		IMMBYTE(r);
1542
1543		WM(r, bcd_sub(RM(s), RM(r), pSR & SR_C));
1544
1545	428	m_icount -= 12;
	429	UINT16 t = read_r8(0) - read_mem8(imm16());
	430	SET_NZ(t);
	431	SET_C(~t);
1546	432	}
1547	433
1548		void tms7000_device::dsb_i2a()
	434	void tms7000_device::cmpa_inx()
1549	435	{
1550		UINT8 i;
1551		IMMBYTE(i);
1552
1553		WRA(bcd_sub(RDA, i, pSR & SR_C));
1554
1555		m_icount -= 9;
	436	m_icount -= 14;
	437	UINT16 t = read_r8(0) - read_mem8(imm16() + read_r8(1));
	438	SET_NZ(t);
	439	SET_C(~t);
1556	440	}
1557	441
1558		void tms7000_device::dsb_i2b()
	442	void tms7000_device::cmpa_ind()
1559	443	{
1560		UINT8 i;
1561		IMMBYTE(i);
1562
1563		WRB(bcd_sub(RDB, i, pSR & SR_C));
1564
1565		m_icount -= 9;
1566		}
1567
1568		void tms7000_device::dsb_i2r()
1569		{
1570		UINT8 i, r;
1571		IMMBYTE(i);
1572		IMMBYTE(r);
1573
1574		WM(r, bcd_sub(RM(r), i, pSR & SR_C));
1575
1576	444	m_icount -= 11;
	445	UINT16 t = read_r8(0) - read_mem8(read_r16(imm8()));
	446	SET_NZ(t);
	447	SET_C(~t);
1577	448	}
1578	449
1579		void tms7000_device::eint()
1580		{
1581		pSR |= (SR_N|SR_Z|SR_C|SR_I);
1582		m_icount -= 5;
1583		tms7000_check_IRQ_lines();
1584		}
1585
1586		void tms7000_device::idle()
1587		{
1588		m_idle_state = 1;
1589		m_icount -= 6;
1590		}
1591
1592		void tms7000_device::inc_a()
1593		{
1594		UINT16  t;
1595
1596		t = RDA + 1;
1597
1598		WRA( t );
1599
1600		CLR_NZC;
1601		SET_C8(t);
1602		SET_N8(t);
1603		SET_Z8(t);
1604
1605		m_icount -= 5;
1606		}
1607
1608		void tms7000_device::inc_b()
1609		{
1610		UINT16  t;
1611
1612		t = RDB + 1;
1613
1614		WRB( t );
1615
1616		CLR_NZC;
1617		SET_C8(t);
1618		SET_N8(t);
1619		SET_Z8(t);
1620
1621		m_icount -= 5;
1622		}
1623
1624		void tms7000_device::inc_r()
1625		{
1626		UINT16  t;
1627		UINT8   r;
1628
1629		IMMBYTE(r);
1630
1631		t = RM(r) + 1;
1632
1633		WM( r, t );
1634
1635		CLR_NZC;
1636		SET_N8(t);
1637		SET_Z8(t);
1638		SET_C8(t);
1639
1640		m_icount -= 7;
1641		}
1642
1643		void tms7000_device::inv_a()
1644		{
1645		UINT16 t;
1646
1647		t = ~(RDA);
1648		WRA(t);
1649
1650		CLR_NZC;
1651		SET_N8(t);
1652		SET_Z8(t);
1653
1654		m_icount -= 5;
1655		}
1656
1657		void tms7000_device::inv_b()
1658		{
1659		UINT16 t;
1660
1661		t = ~(RDB);
1662		WRB(t);
1663
1664		CLR_NZC;
1665		SET_N8(t);
1666		SET_Z8(t);
1667
1668		m_icount -= 5;
1669		}
1670
1671		void tms7000_device::inv_r()
1672		{
1673		UINT16  t;
1674		UINT8   r;
1675
1676		IMMBYTE(r);
1677
1678		t = ~(RM(r));
1679
1680		WM( r, t );
1681
1682		CLR_NZC;
1683		SET_N8(t);
1684		SET_Z8(t);
1685
1686		m_icount -= 7;
1687		}
1688
1689		void tms7000_device::jc()
1690		{
1691		if( pSR & SR_C )
1692		{
1693		INT8 s;
1694
1695		SIMMBYTE( s );
1696		pPC += s;
1697		m_icount -= 7;
1698		}
1699		else
1700		{
1701		pPC++;
1702		m_icount -= 5;
1703		}
1704		}
1705
1706		void tms7000_device::jeq()
1707		{
1708		if( pSR & SR_Z )
1709		{
1710		INT8 s;
1711
1712		SIMMBYTE( s );
1713		pPC += s;
1714		m_icount -= 7;
1715		}
1716		else
1717		{
1718		pPC++;
1719		m_icount -= 5;
1720		}
1721		}
1722
1723		void tms7000_device::jl()
1724		{
1725		if( pSR & SR_C )
1726		{
1727		pPC++;
1728		m_icount -= 5;
1729		}
1730		else
1731		{
1732		INT8 s;
1733
1734		SIMMBYTE( s );
1735		pPC += s;
1736		m_icount -= 7;
1737		}
1738		}
1739
1740		void tms7000_device::jmp()
1741		{
1742		INT8 s;
1743
1744		SIMMBYTE( s );
1745		pPC += s;
1746		m_icount -= 7;
1747		}
1748
1749		void tms7000_device::j_jn()
1750		{
1751		if( pSR & SR_N )
1752		{
1753		INT8 s;
1754
1755		SIMMBYTE( s );
1756		pPC += s;
1757		m_icount -= 7;
1758		}
1759		else
1760		{
1761		pPC++;
1762		m_icount -= 5;
1763		}
1764
1765		}
1766
1767		void tms7000_device::jne()
1768		{
1769		if( pSR & SR_Z )
1770		{
1771		pPC++;
1772		m_icount -= 5;
1773		}
1774		else
1775		{
1776		INT8 s;
1777
1778		SIMMBYTE( s );
1779		pPC += s;
1780		m_icount -= 7;
1781		}
1782		}
1783
1784		void tms7000_device::jp()
1785		{
1786		if( pSR & (SR_Z|SR_N) )
1787		{
1788		pPC++;
1789		m_icount -= 5;
1790		}
1791		else
1792		{
1793		INT8 s;
1794
1795		SIMMBYTE( s );
1796		pPC += s;
1797		m_icount -= 7;
1798		}
1799		}
1800
1801		void tms7000_device::jpz()
1802		{
1803		// NOTE: JPZ in TI documentation was wrong:
1804		//     if ((pSR & SR_N) == 0 && (pSR & SR_Z) != 0)
1805		// should be:
1806		//     if ((pSR & SR_N) == 0)
1807		if ((pSR & SR_N) == 0)
1808		{
1809		INT8 s;
1810
1811		SIMMBYTE( s );
1812		pPC += s;
1813		m_icount -= 7;
1814		}
1815		else
1816		{
1817		pPC++;
1818		m_icount -= 5;
1819		}
1820		}
1821
	450	// lda extended
1822	451	void tms7000_device::lda_dir()
1823	452	{
1824		UINT16  t;
1825		PAIR    i;
1826
1827		IMMWORD( i );
1828		t = RM(i.w.l);
1829		WRA(t);
1830
1831		CLR_NZC;
1832		SET_N8(t);
1833		SET_Z8(t);
1834
1835	453	m_icount -= 11;
	454	UINT8 t = read_mem8(imm16());
	455	write_r8(0, t);
	456	SET_CNZ(t);
1836	457	}
1837	458
1838		void tms7000_device::lda_ind()
1839		{
1840		UINT16  t;
1841		PAIR    p;
1842		INT8    i;
1843
1844		IMMBYTE(i);
1845		p.w.l=RRF16(i);
1846		t = RM(p.w.l);
1847		WRA(t);
1848
1849		CLR_NZC;
1850		SET_N8(t);
1851		SET_Z8(t);
1852
1853		m_icount -= 10;
1854		}
1855
1856	459	void tms7000_device::lda_inx()
1857	460	{
1858		UINT16  t;
1859		PAIR    i;
1860
1861		IMMWORD( i );
1862		t = RM(i.w.l + RDB);
1863		WRA(t);
1864
1865		CLR_NZC;
1866		SET_N8(t);
1867		SET_Z8(t);
1868
1869	461	m_icount -= 13;
	462	UINT8 t = read_mem8(imm16() + read_r8(1));
	463	write_r8(0, t);
	464	SET_CNZ(t);
1870	465	}
1871	466
1872		void tms7000_device::ldsp()
	467	void tms7000_device::lda_ind()
1873	468	{
1874		pSP = RDB;
1875		m_icount -= 5;
	469	m_icount -= 10;
	470	UINT8 t = read_mem8(read_r16(imm8()));
	471	write_r8(0, t);
	472	SET_CNZ(t);
1876	473	}
1877	474
1878		void tms7000_device::mov_a2b()
	475	// sta extended
	476	void tms7000_device::sta_dir()
1879	477	{
1880		UINT16  t;
1881
1882		t = RDA;
1883		WRB(t);
1884
1885		CLR_NZC;
1886		SET_N8(t);
1887		SET_Z8(t);
1888
1889		m_icount -= 6;
	478	m_icount -= 11;
	479	UINT8 t = read_r8(0);
	480	write_mem8(imm16(), t);
	481	SET_CNZ(t);
1890	482	}
1891	483
1892		void tms7000_device::mov_b2a()
	484	void tms7000_device::sta_inx()
1893	485	{
1894		UINT16  t;
1895
1896		t = RDB;
1897		WRA(t);
1898
1899		CLR_NZC;
1900		SET_N8(t);
1901		SET_Z8(t);
1902
1903		m_icount -= 5;
	486	m_icount -= 13;
	487	UINT8 t = read_r8(0);
	488	write_mem8(imm16() + read_r8(1), t);
	489	SET_CNZ(t);
1904	490	}
1905	491
1906
1907		void tms7000_device::mov_a2r()
	492	void tms7000_device::sta_ind()
1908	493	{
1909		UINT8   r;
1910		UINT16  t;
1911
1912		IMMBYTE(r);
1913
1914		t = RDA;
1915		WM(r,t);
1916
1917		CLR_NZC;
1918		SET_N8(t);
1919		SET_Z8(t);
1920
1921		m_icount -= 8;
1922		}
1923
1924		void tms7000_device::mov_b2r()
1925		{
1926		UINT8   r;
1927		UINT16  t;
1928
1929		IMMBYTE(r);
1930
1931		t = RDB;
1932		WM(r,t);
1933
1934		CLR_NZC;
1935		SET_N8(t);
1936		SET_Z8(t);
1937
1938		m_icount -= 7;
1939		}
1940
1941		void tms7000_device::mov_r2a()
1942		{
1943		UINT8   r;
1944		UINT16  t;
1945
1946		IMMBYTE(r);
1947		t = RM(r);
1948		WRA(t);
1949
1950		CLR_NZC;
1951		SET_N8(t);
1952		SET_Z8(t);
1953
1954		m_icount -= 8;
1955		}
1956
1957		void tms7000_device::mov_r2b()
1958		{
1959		UINT8   r;
1960		UINT16  t;
1961
1962		IMMBYTE(r);
1963		t = RM(r);
1964		WRB(t);
1965
1966		CLR_NZC;
1967		SET_N8(t);
1968		SET_Z8(t);
1969
1970		m_icount -= 8;
1971		}
1972
1973		void tms7000_device::mov_r2r()
1974		{
1975		UINT8   r,s;
1976		UINT16  t;
1977
1978		IMMBYTE(r);
1979		IMMBYTE(s);
1980		t = RM(r);
1981		WM(s,t);
1982
1983		CLR_NZC;
1984		SET_N8(t);
1985		SET_Z8(t);
1986
1987	494	m_icount -= 10;
	495	UINT8 t = read_r8(0);
	496	write_mem8(read_r16(imm8()), t);
	497	SET_CNZ(t);
1988	498	}
1989	499
1990		void tms7000_device::mov_i2a()
	500	// mov double
	501	void tms7000_device::movd_dir()
1991	502	{
1992		UINT16  t;
1993
1994		IMMBYTE(t);
1995		WRA(t);
1996
1997		CLR_NZC;
1998		SET_N8(t);
1999		SET_Z8(t);
2000
2001		m_icount -= 7;
2002		}
2003
2004		void tms7000_device::mov_i2b()
2005		{
2006		UINT16  t;
2007
2008		IMMBYTE(t);
2009		WRB(t);
2010
2011		CLR_NZC;
2012		SET_N8(t);
2013		SET_Z8(t);
2014
2015		m_icount -= 7;
2016		}
2017
2018		void tms7000_device::mov_i2r()
2019		{
2020		UINT16  t;
2021		UINT8   r;
2022
2023		IMMBYTE(t);
2024		IMMBYTE(r);
2025		WM(r,t);
2026
2027		CLR_NZC;
2028		SET_N8(t);
2029		SET_Z8(t);
2030
2031		m_icount -= 9;
2032		}
2033
2034		void tms7000_device::movd_imm()
2035		{
2036		PAIR    t;
2037		UINT8   r;
2038
2039		IMMWORD(t);
2040		IMMBYTE(r);
2041		WRF16(r,t);
2042
2043		CLR_NZC;
2044		SET_N8(t.b.h);
2045		SET_Z8(t.b.h);
2046
2047	503	m_icount -= 15;
2048
	504	UINT16 t = imm16();
	505	write_r16(imm8(), t);
	506	SET_CNZ(t >> 8 & 0xff);
2049	507	}
2050	508
2051		void tms7000_device::movd_r()
2052		{
2053		PAIR    t;
2054		UINT8   r,s;
2055
2056		IMMBYTE(r);
2057		IMMBYTE(s);
2058		t.w.l = RRF16(r);
2059		WRF16(s,t);
2060
2061		CLR_NZC;
2062		SET_N8(t.b.h);
2063		SET_Z8(t.b.h);
2064
2065		m_icount -= 14;
2066
2067		}
2068
2069	509	void tms7000_device::movd_inx()
2070	510	{
2071		PAIR    t;
2072		UINT8   r;
2073
2074		IMMWORD(t);
2075		t.w.l = (t.w.l+RDB)&0xFFFF;
2076		IMMBYTE(r);
2077		WRF16(r,t);
2078
2079		CLR_NZC;
2080		SET_N8(t.b.h);
2081		SET_Z8(t.b.h);
2082
2083	511	m_icount -= 17;
	512	UINT16 t = imm16() + read_r8(1);
	513	write_r16(imm8(), t);
	514	SET_CNZ(t >> 8 & 0xff);
2084	515	}
2085	516
2086		void tms7000_device::movp_a2p()
	517	void tms7000_device::movd_ind()
2087	518	{
2088		UINT8   p;
2089		UINT16  t;
2090
2091		IMMBYTE(p);
2092		t=RDA;
2093		WM( 0x0100+p,t);
2094
2095		CLR_NZC;
2096		SET_N8(t);
2097		SET_Z8(t);
2098
2099		m_icount -= 10;
	519	m_icount -= 14;
	520	UINT16 t = read_r16(imm8());
	521	write_r16(imm8(), t);
	522	SET_CNZ(t >> 8 & 0xff);
2100	523	}
2101	524
2102		void tms7000_device::movp_b2p()
	525	// long branch
	526	void tms7000_device::br_dir()
2103	527	{
2104		UINT8   p;
2105		UINT16  t;
2106
2107		IMMBYTE(p);
2108		t=RDB;
2109		WM( 0x0100+p,t);
2110
2111		CLR_NZC;
2112		SET_N8(t);
2113		SET_Z8(t);
2114
2115	528	m_icount -= 10;
	529	m_pc = imm16();
2116	530	}
2117	531
2118		#if 0
2119		/* this appears to be unused */
2120		void tms7000_device::movp_r2p()
	532	void tms7000_device::br_inx()
2121	533	{
2122		UINT8   p,r;
2123		UINT16  t;
2124
2125		IMMBYTE(r);
2126		IMMBYTE(p);
2127		t=RM(r);
2128		WM( 0x0100+p,t);
2129
2130		CLR_NZC;
2131		SET_N8(t);
2132		SET_Z8(t);
2133
2134		m_icount -= 11;
	534	m_icount -= 12;
	535	m_pc = imm16() + read_r8(1);
2135	536	}
2136		#endif
2137	537
2138		void tms7000_device::movp_p2a()
	538	void tms7000_device::br_ind()
2139	539	{
2140		UINT8   p;
2141		UINT16  t;
2142
2143		IMMBYTE(p);
2144		t=RM(0x0100+p);
2145		WRA(t);
2146
2147		CLR_NZC;
2148		SET_N8(t);
2149		SET_Z8(t);
2150
2151	540	m_icount -= 9;
	541	m_pc = read_r16(imm8());
2152	542	}
2153	543
2154		void tms7000_device::movp_p2b()
	544	// call/return
	545	void tms7000_device::call_dir()
2155	546	{
2156		UINT8   p;
2157		UINT16  t;
2158
2159		IMMBYTE(p);
2160		t=RM(0x0100+p);
2161		WRB(t);
2162
2163		CLR_NZC;
2164		SET_N8(t);
2165		SET_Z8(t);
2166
2167		m_icount -= 8;
	547	m_icount -= 14;
	548	UINT16 t = imm16();
	549	push16(m_pc);
	550	m_pc = t;
2168	551	}
2169	552
2170		void tms7000_device::mpy_ba()
	553	void tms7000_device::call_inx()
2171	554	{
2172		PAIR t;
2173
2174		t.w.l = RDA * RDB;
2175
2176		WRF16(0x01,t);
2177
2178		CLR_NZC;
2179		SET_N8(t.b.h);
2180		SET_Z8(t.b.h);
2181
2182		m_icount -= 43;
2183
	555	m_icount -= 16;
	556	UINT16 t = imm16() + read_r8(1);
	557	push16(m_pc);
	558	m_pc = t;
2184	559	}
2185	560
2186		void tms7000_device::mpy_ra()
	561	void tms7000_device::call_ind()
2187	562	{
2188		PAIR    t;
2189		UINT8   r;
2190
2191		IMMBYTE(r);
2192
2193		t.w.l = RDA * RM(r);
2194
2195		WRF16(0x01,t);
2196
2197		CLR_NZC;
2198		SET_N8(t.b.h);
2199		SET_Z8(t.b.h);
2200
2201		m_icount -= 46;
2202
	563	m_icount -= 13;
	564	UINT16 t = read_r16(imm8());
	565	push16(m_pc);
	566	m_pc = t;
2203	567	}
2204	568
2205		void tms7000_device::mpy_rb()
	569	void tms7000_device::trap(UINT8 address)
2206	570	{
2207		PAIR    t;
2208		UINT8   r;
2209
2210		IMMBYTE(r);
2211
2212		t.w.l = RDB * RM(r);
2213
2214		WRF16(0x01,t);
2215
2216		CLR_NZC;
2217		SET_N8(t.b.h);
2218		SET_Z8(t.b.h);
2219
2220		m_icount -= 46;
2221
	571	m_icount -= 14;
	572	push16(m_pc);
	573	m_pc = read_mem16(0xff00 | address);
2222	574	}
2223	575
2224		void tms7000_device::mpy_rr()
	576	void tms7000_device::reti()
2225	577	{
2226		PAIR    t;
2227		UINT8   r,s;
2228
2229		IMMBYTE(r);
2230		IMMBYTE(s);
2231
2232		t.w.l = RM(s) * RM(r);
2233
2234		WRF16(0x01,t);
2235
2236		CLR_NZC;
2237		SET_N8(t.b.h);
2238		SET_Z8(t.b.h);
2239
2240		m_icount -= 48;
2241
	578	m_icount -= 9;
	579	m_pc = pull16();
	580	m_sr = pull8() & 0xf0;
	581	check_interrupts();
2242	582	}
2243	583
2244		void tms7000_device::mpy_ia()
	584	void tms7000_device::rets()
2245	585	{
2246		PAIR    t;
2247		UINT8   i;
2248
2249		IMMBYTE(i);
2250
2251		t.w.l = RDA * i;
2252
2253		WRF16(0x01,t);
2254
2255		CLR_NZC;
2256		SET_N8(t.b.h);
2257		SET_Z8(t.b.h);
2258
2259		m_icount -= 45;
2260
2261		}
2262
2263		void tms7000_device::mpy_ib()
2264		{
2265		PAIR    t;
2266		UINT8   i;
2267
2268		IMMBYTE(i);
2269
2270		t.w.l = RDB * i;
2271
2272		WRF16(0x01,t);
2273
2274		CLR_NZC;
2275		SET_N8(t.b.h);
2276		SET_Z8(t.b.h);
2277
2278		m_icount -= 45;
2279
2280		}
2281
2282		void tms7000_device::mpy_ir()
2283		{
2284		PAIR    t;
2285		UINT8   i,r;
2286
2287		IMMBYTE(i);
2288		IMMBYTE(r);
2289
2290		t.w.l = RM(r) * i;
2291
2292		WRF16(0x01,t);
2293
2294		CLR_NZC;
2295		SET_N8(t.b.h);
2296		SET_Z8(t.b.h);
2297
2298		m_icount -= 47;
2299
2300		}
2301
2302		void tms7000_device::nop()
2303		{
2304		m_icount -= 4;
2305		}
2306
2307		void tms7000_device::or_b2a()
2308		{
2309		UINT8   t;
2310
2311		t = RDA | RDB;
2312		WRA(t);
2313
2314		CLR_NZC;
2315		SET_N8(t);
2316		SET_Z8(t);
2317
2318		m_icount -= 5;
2319		}
2320
2321		void tms7000_device::or_r2a()
2322		{
2323		UINT8   t;
2324		UINT8   v;
2325
2326		IMMBYTE(v);
2327
2328		t = RM(v) | RDA;
2329		WRA(t);
2330
2331		CLR_NZC;
2332		SET_N8(t);
2333		SET_Z8(t);
2334
2335		m_icount -= 8;
2336		}
2337
2338		void tms7000_device::or_r2b()
2339		{
2340		UINT8   t;
2341		UINT8   v;
2342
2343		IMMBYTE(v);
2344
2345		t = RM(v) | RDB;
2346		WRB(t);
2347
2348		CLR_NZC;
2349		SET_N8(t);
2350		SET_Z8(t);
2351
2352		m_icount -= 8;
2353		}
2354
2355		void tms7000_device::or_r2r()
2356		{
2357		UINT8   t;
2358		UINT8   i,j;
2359
2360		IMMBYTE(i);
2361		IMMBYTE(j);
2362
2363		t = RM(i) | RM(j);
2364		WM(j,t);
2365
2366		CLR_NZC;
2367		SET_N8(t);
2368		SET_Z8(t);
2369
2370		m_icount -= 10;
2371		}
2372
2373		void tms7000_device::or_i2a()
2374		{
2375		UINT8   t;
2376		UINT8   v;
2377
2378		IMMBYTE(v);
2379
2380		t = v | RDA;
2381		WRA(t);
2382
2383		CLR_NZC;
2384		SET_N8(t);
2385		SET_Z8(t);
2386
2387	586	m_icount -= 7;
	587	m_pc = pull16();
2388	588	}
2389	589
2390		void tms7000_device::or_i2b()
2391		{
2392		UINT8   t;
2393		UINT8   v;
2394
2395		IMMBYTE(v);
2396
2397		t = v | RDB;
2398		WRB(t);
2399
2400		CLR_NZC;
2401		SET_N8(t);
2402		SET_Z8(t);
2403
2404		m_icount -= 7;
2405		}
2406
2407		void tms7000_device::or_i2r()
2408		{
2409		UINT8   t;
2410		UINT8   i,j;
2411
2412		IMMBYTE(i);
2413		IMMBYTE(j);
2414
2415		t = i | RM(j);
2416		WM(j,t);
2417
2418		CLR_NZC;
2419		SET_N8(t);
2420		SET_Z8(t);
2421
2422		m_icount -= 9;
2423		}
2424
2425		void tms7000_device::orp_a2p()
2426		{
2427		UINT8   t;
2428		UINT8   v;
2429
2430		IMMBYTE(v);
2431		t = RDA | RM( 0x0100 + v);
2432		WM( 0x0100+v, t);
2433
2434		CLR_NZC;
2435		SET_N8(t);
2436		SET_Z8(t);
2437
2438		m_icount -= 10;
2439		}
2440
2441		void tms7000_device::orp_b2p()
2442		{
2443		UINT8   t;
2444		UINT8   v;
2445
2446		IMMBYTE(v);
2447		t = RDB | RM( 0x0100 + v);
2448		WM( 0x0100+v, t);
2449
2450		CLR_NZC;
2451		SET_N8(t);
2452		SET_Z8(t);
2453
2454		m_icount -= 9;
2455		}
2456
2457		void tms7000_device::orp_i2p()
2458		{
2459		UINT8   t;
2460		UINT8   i,v;
2461
2462		IMMBYTE(i);
2463		IMMBYTE(v);
2464		t = i | RM( 0x0100 + v);
2465		WM( 0x0100+v, t);
2466
2467		CLR_NZC;
2468		SET_N8(t);
2469		SET_Z8(t);
2470
2471		m_icount -= 11;
2472		}
2473
	590	// pop
2474	591	void tms7000_device::pop_a()
2475	592	{
2476		UINT16  t;
2477
2478		PULLBYTE(t);
2479		WRA(t);
2480
2481		CLR_NZC;
2482		SET_N8(t);
2483		SET_Z8(t);
2484
2485	593	m_icount -= 6;
	594	UINT8 t = pull8();
	595	write_r8(0, t);
	596	SET_CNZ(t);
2486	597	}
2487	598
2488	599	void tms7000_device::pop_b()
2489	600	{
2490		UINT16  t;
2491
2492		PULLBYTE(t);
2493		WRB(t);
2494
2495		CLR_NZC;
2496		SET_N8(t);
2497		SET_Z8(t);
2498
2499	601	m_icount -= 6;
	602	UINT8 t = pull8();
	603	write_r8(1, t);
	604	SET_CNZ(t);
2500	605	}
2501	606
2502	607	void tms7000_device::pop_r()
2503	608	{
2504		UINT16  t;
2505		UINT8   r;
2506
2507		IMMBYTE(r);
2508		PULLBYTE(t);
2509		WM(r,t);
2510
2511		CLR_NZC;
2512		SET_N8(t);
2513		SET_Z8(t);
2514
2515	609	m_icount -= 8;
	610	UINT8 t = pull8();
	611	write_r8(imm8(), t);
	612	SET_CNZ(t);
2516	613	}
2517	614
2518	615	void tms7000_device::pop_st()
2519	616	{
2520		UINT16  t;
2521
2522		PULLBYTE(t);
2523		pSR = t;
2524
2525	617	m_icount -= 6;
	618	m_sr = pull8() & 0xf0;
	619	check_interrupts();
2526	620	}
2527	621
	622	// push
2528	623	void tms7000_device::push_a()
2529	624	{
2530		UINT16  t;
2531
2532		t = RDA;
2533		PUSHBYTE(t);
2534
2535		CLR_NZC;
2536		SET_N8(t);
2537		SET_Z8(t);
2538
2539	625	m_icount -= 6;
	626	UINT8 t = read_r8(0);
	627	push8(t);
	628	SET_CNZ(t);
2540	629	}
2541	630
2542	631	void tms7000_device::push_b()
2543	632	{
2544		UINT16  t;
2545
2546		t = RDB;
2547		PUSHBYTE(t);
2548
2549		CLR_NZC;
2550		SET_N8(t);
2551		SET_Z8(t);
2552
2553	633	m_icount -= 6;
	634	UINT8 t = read_r8(1);
	635	push8(t);
	636	SET_CNZ(t);
2554	637	}
2555	638
2556	639	void tms7000_device::push_r()
2557	640	{
2558		UINT16  t;
2559		INT8    r;
2560
2561		IMMBYTE(r);
2562		t = RM(r);
2563		PUSHBYTE(t);
2564
2565		CLR_NZC;
2566		SET_N8(t);
2567		SET_Z8(t);
2568
2569	641	m_icount -= 8;
	642	UINT8 t = read_r8(imm8());
	643	push8(t);
	644	SET_CNZ(t);
2570	645	}
2571	646
2572	647	void tms7000_device::push_st()
2573	648	{
2574		UINT16  t;
2575		t = pSR;
2576		PUSHBYTE(t);
2577
2578	649	m_icount -= 6;
	650	push8(m_sr);
2579	651	}
2580	652
2581		void tms7000_device::reti()
	653	// other
	654	void tms7000_device::nop()
2582	655	{
2583		PULLWORD( PC );
2584		PULLBYTE( pSR );
2585
2586		m_icount -= 9;
2587		tms7000_check_IRQ_lines();
2588		}
2589
2590		void tms7000_device::rets()
2591		{
2592		PULLWORD( PC );
2593		m_icount -= 7;
2594		}
2595
2596		void tms7000_device::rl_a()
2597		{
2598		UINT16  t;
2599
2600		t = RDA << 1;
2601
2602		CLR_NZC;
2603		SET_C8(t);
2604
2605		if( pSR & SR_C )
2606		t |= 0x01;
2607
2608		SET_N8(t);
2609		SET_Z8(t);
2610		WRA(t);
2611
2612	656	m_icount -= 5;
2613	657	}
2614	658
2615		void tms7000_device::rl_b()
	659	void tms7000_device::idle()
2616	660	{
2617		UINT16  t;
2618
2619		t = RDB << 1;
2620
2621		CLR_NZC;
2622		SET_C8(t);
2623
2624		if( pSR & SR_C )
2625		t |= 0x01;
2626
2627		SET_N8(t);
2628		SET_Z8(t);
2629		WRB(t);
2630
2631		m_icount -= 5;
	661	m_icount -= 6;
	662	m_pc--;
	663	m_idle_state = true;
2632	664	}
2633	665
2634		void tms7000_device::rl_r()
	666	void tms7000_device::dint()
2635	667	{
2636		UINT16  t;
2637		UINT8   r;
2638
2639		IMMBYTE(r);
2640		t = RM(r) << 1;
2641
2642		CLR_NZC;
2643		SET_C8(t);
2644
2645		if( pSR & SR_C )
2646		t |= 0x01;
2647
2648		SET_N8(t);
2649		SET_Z8(t);
2650		WM(r,t);
2651
2652		m_icount -= 7;
2653		}
2654
2655		void tms7000_device::rlc_a()
2656		{
2657		UINT16  t;
2658		int     old_carry;
2659
2660		old_carry = (pSR & SR_C);
2661
2662		t = RDA << 1;
2663
2664		CLR_NZC;
2665		SET_C8(t);
2666
2667		if( old_carry )
2668		t |= 0x01;
2669
2670		SET_N8(t);
2671		SET_Z8(t);
2672		WRA(t);
2673
2674	668	m_icount -= 5;
	669	m_sr &= ~(SR_N | SR_Z | SR_C | SR_I);
2675	670	}
2676	671
2677		void tms7000_device::rlc_b()
	672	void tms7000_device::eint()
2678	673	{
2679		UINT16  t;
2680		int     old_carry;
2681
2682		old_carry = (pSR & SR_C);
2683
2684		t = RDB << 1;
2685
2686		CLR_NZC;
2687		SET_C8(t);
2688
2689		if( old_carry )
2690		t |= 0x01;
2691
2692		SET_N8(t);
2693		SET_Z8(t);
2694		WRB(t);
2695
2696	674	m_icount -= 5;
	675	m_sr |= (SR_N | SR_Z | SR_C | SR_I);
	676	check_interrupts();
2697	677	}
2698	678
2699		void tms7000_device::rlc_r()
	679	void tms7000_device::ldsp()
2700	680	{
2701		UINT16  t;
2702		UINT8   r;
2703		int     old_carry;
2704
2705		old_carry = (pSR & SR_C);
2706
2707		IMMBYTE(r);
2708		t = RM(r) << 1;
2709
2710		CLR_NZC;
2711		SET_C8(t);
2712
2713		if( old_carry )
2714		t |= 0x01;
2715
2716		SET_N8(t);
2717		SET_Z8(t);
2718		WM(r,t);
2719
2720		m_icount -= 7;
2721		}
2722
2723		void tms7000_device::rr_a()
2724		{
2725		UINT16  t;
2726		int     old_bit0;
2727
2728		t = RDA;
2729
2730		old_bit0 = t & 0x0001;
2731		t = t >> 1;
2732
2733		CLR_NZC;
2734
2735		if( old_bit0 )
2736		{
2737		SETC;
2738		t |= 0x80;
2739		}
2740
2741		SET_N8(t);
2742		SET_Z8(t);
2743
2744		WRA(t);
2745
2746	681	m_icount -= 5;
	682	m_sp = read_r8(1);
2747	683	}
2748	684
2749		void tms7000_device::rr_b()
2750		{
2751		UINT16  t;
2752		int     old_bit0;
2753
2754		t = RDB;
2755
2756		old_bit0 = t & 0x0001;
2757		t = t >> 1;
2758
2759		CLR_NZC;
2760
2761		if( old_bit0 )
2762		{
2763		SETC;
2764		t |= 0x80;
2765		}
2766
2767		SET_N8(t);
2768		SET_Z8(t);
2769
2770		WRB(t);
2771
2772		m_icount -= 5;
2773		}
2774
2775		void tms7000_device::rr_r()
2776		{
2777		UINT16  t;
2778		UINT8   r;
2779
2780		int     old_bit0;
2781
2782		IMMBYTE(r);
2783		t = RM(r);
2784
2785		old_bit0 = t & 0x0001;
2786		t = t >> 1;
2787
2788		CLR_NZC;
2789
2790		if( old_bit0 )
2791		{
2792		SETC;
2793		t |= 0x80;
2794		}
2795
2796		SET_N8(t);
2797		SET_Z8(t);
2798
2799		WM(r,t);
2800
2801		m_icount -= 7;
2802		}
2803
2804		void tms7000_device::rrc_a()
2805		{
2806		UINT16  t;
2807		int     old_bit0;
2808
2809		t = RDA;
2810
2811		old_bit0 = t & 0x0001;
2812		/* Place carry bit in 9th position */
2813		t |= ((pSR & SR_C) << 1);
2814		t = t >> 1;
2815
2816		CLR_NZC;
2817
2818		if( old_bit0 )
2819		SETC;
2820		SET_N8(t);
2821		SET_Z8(t);
2822
2823		WRA(t);
2824
2825		m_icount -= 5;
2826		}
2827
2828		void tms7000_device::rrc_b()
2829		{
2830		UINT16  t;
2831		int     old_bit0;
2832
2833		t = RDB;
2834
2835		old_bit0 = t & 0x0001;
2836		/* Place carry bit in 9th position */
2837		t |= ((pSR & SR_C) << 1);
2838		t = t >> 1;
2839
2840		CLR_NZC;
2841
2842		if( old_bit0 )
2843		SETC;
2844		SET_N8(t);
2845		SET_Z8(t);
2846
2847		WRB(t);
2848
2849		m_icount -= 5;
2850		}
2851
2852		void tms7000_device::rrc_r()
2853		{
2854		UINT16  t;
2855		UINT8   r;
2856		int     old_bit0;
2857
2858		IMMBYTE(r);
2859		t = RM(r);
2860
2861		old_bit0 = t & 0x0001;
2862		/* Place carry bit in 9th position */
2863		t |= ((pSR & SR_C) << 1);
2864		t = t >> 1;
2865
2866		CLR_NZC;
2867
2868		if( old_bit0 )
2869		SETC;
2870		SET_N8(t);
2871		SET_Z8(t);
2872
2873		WM(r,t);
2874
2875		m_icount -= 7;
2876		}
2877
2878		void tms7000_device::sbb_ba()
2879		{
2880		UINT16  t;
2881
2882		t = RDA - RDB - ((pSR & SR_C) ? 0 : 1);
2883		WRA(t);
2884
2885		CLR_NZC;
2886		SET_C8(~t);
2887		SET_N8(t);
2888		SET_Z8(t);
2889
2890		m_icount -= 5;
2891		}
2892
2893		void tms7000_device::sbb_ra()
2894		{
2895		UINT16  t;
2896		UINT8   r;
2897
2898		IMMBYTE(r);
2899		t = RDA - RM(r) - ((pSR & SR_C) ? 0 : 1);
2900		WRA(t);
2901
2902		CLR_NZC;
2903		SET_C8(~t);
2904		SET_N8(t);
2905		SET_Z8(t);
2906
2907		m_icount -= 8;
2908		}
2909
2910		void tms7000_device::sbb_rb()
2911		{
2912		UINT16  t;
2913		UINT8   r;
2914
2915		IMMBYTE(r);
2916		t = RDB - RM(r) - ((pSR & SR_C) ? 0 : 1);
2917		WRB(t);
2918
2919		CLR_NZC;
2920		SET_C8(~t);
2921		SET_N8(t);
2922		SET_Z8(t);
2923
2924		m_icount -= 8;
2925		}
2926
2927		void tms7000_device::sbb_rr()
2928		{
2929		UINT16  t;
2930		UINT8   r,s;
2931
2932		IMMBYTE(s);
2933		IMMBYTE(r);
2934		t = RM(r) - RM(s) - ((pSR & SR_C) ? 0 : 1);
2935		WM(r,t);
2936
2937		CLR_NZC;
2938		SET_C8(~t);
2939		SET_N8(t);
2940		SET_Z8(t);
2941
2942		m_icount -= 10;
2943		}
2944
2945		void tms7000_device::sbb_ia()
2946		{
2947		UINT16  t;
2948		UINT8   i;
2949
2950		IMMBYTE(i);
2951		t = RDA - i - ((pSR & SR_C) ? 0 : 1);
2952		WRA(t);
2953
2954		CLR_NZC;
2955		SET_C8(~t);
2956		SET_N8(t);
2957		SET_Z8(t);
2958
2959		m_icount -= 7;
2960		}
2961
2962		void tms7000_device::sbb_ib()
2963		{
2964		UINT16  t;
2965		UINT8   i;
2966
2967		IMMBYTE(i);
2968		t = RDB - i - ((pSR & SR_C) ? 0 : 1);
2969		WRB(t);
2970
2971		CLR_NZC;
2972		SET_C8(~t);
2973		SET_N8(t);
2974		SET_Z8(t);
2975
2976		m_icount -= 7;
2977		}
2978
2979		void tms7000_device::sbb_ir()
2980		{
2981		UINT16  t;
2982		UINT8   r,i;
2983
2984		IMMBYTE(i);
2985		IMMBYTE(r);
2986		t = RM(r) - i - ((pSR & SR_C) ? 0 : 1);
2987		WM(r,t);
2988
2989		CLR_NZC;
2990		SET_C8(~t);
2991		SET_N8(t);
2992		SET_Z8(t);
2993
2994		m_icount -= 9;
2995		}
2996
2997		void tms7000_device::setc()
2998		{
2999		CLR_NZC;
3000		pSR |= (SR_C|SR_Z);
3001
3002		m_icount -= 5;
3003		}
3004
3005		void tms7000_device::sta_dir()
3006		{
3007		UINT16  t;
3008		PAIR    i;
3009
3010		t = RDA;
3011		IMMWORD( i );
3012
3013		WM(i.w.l,t);
3014
3015		CLR_NZC;
3016		SET_N8(t);
3017		SET_Z8(t);
3018
3019		m_icount -= 11;
3020		}
3021
3022		void tms7000_device::sta_ind()
3023		{
3024		UINT16  t;
3025		PAIR    p;
3026		INT8    r;
3027
3028		IMMBYTE(r);
3029		p.w.l = RRF16(r);
3030		t = RDA;
3031		WM(p.w.l,t);
3032
3033		CLR_NZC;
3034		SET_N8(t);
3035		SET_Z8(t);
3036
3037		m_icount -= 10;
3038		}
3039
3040		void tms7000_device::sta_inx()
3041		{
3042		UINT16  t;
3043		PAIR    i;
3044
3045		IMMWORD( i );
3046		t = RDA;
3047		WM(i.w.l+RDB,t);
3048
3049		CLR_NZC;
3050		SET_N8(t);
3051		SET_Z8(t);
3052
3053		m_icount -= 13;
3054		}
3055
3056	685	void tms7000_device::stsp()
3057	686	{
3058		WRB(pSP);
3059
3060	687	m_icount -= 6;
	688	write_r8(1, m_sp);
3061	689	}
3062	690
3063		void tms7000_device::sub_ba()
	691	void tms7000_device::setc()
3064	692	{
3065		UINT16  t;
3066
3067		t = RDA - RDB;
3068		WRA(t);
3069
3070		CLR_NZC;
3071		SET_C8(~t);
3072		SET_N8(t);
3073		SET_Z8(t);
3074
3075	693	m_icount -= 5;
	694	m_sr = (m_sr & ~SR_N) | SR_C | SR_Z;
3076	695	}
3077	696
3078		void tms7000_device::sub_ra()
	697	// not standard
	698	void tms7020_exl_device::lvdp()
3079	699	{
3080		UINT16  t;
3081		UINT8   r;
3082
3083		IMMBYTE(r);
3084		t = RDA - RM(r);
3085		WRA(t);
3086
3087		CLR_NZC;
3088		SET_C8(~t);
3089		SET_N8(t);
3090		SET_Z8(t);
3091
3092		m_icount -= 8;
	700	/* on EXL100, opcode D7 ?? (SWAP R) was changed to LVDP, mostly equivalent to:
	701	* MOVP P40,xx
	702	* MOVP P36,A
	703	*/
	704	m_icount -= 10; // TODO: check real timing
	705	imm8(); // always 0x28? discarded?
	706	read_p(0x28);
	707	UINT8 t = read_p(0x24);
	708	write_r8(0, t);
	709	SET_CNZ(t);
3093	710	}
3094	711
3095		void tms7000_device::sub_rb()
	712	// illegal opcode handling
	713	void tms7000_device::illegal(UINT8 op)
3096	714	{
3097		UINT16  t;
3098		UINT8   r;
3099
3100		IMMBYTE(r);
3101		t = RDB - RM(r);
3102		WRB(t);
3103
3104		CLR_NZC;
3105		SET_C8(~t);
3106		SET_N8(t);
3107		SET_Z8(t);
3108
3109		m_icount -= 8;
	715	m_icount -= 5; // guessed
	716	logerror("%s: illegal opcode $%02X @ $%04x\n", tag(), op, m_pc);
3110	717	}
3111
3112		void tms7000_device::sub_rr()
3113		{
3114		UINT16  t;
3115		UINT8   r,s;
3116
3117		IMMBYTE(s);
3118		IMMBYTE(r);
3119		t = RM(r) - RM(s);
3120		WM(r,t);
3121
3122		CLR_NZC;
3123		SET_C8(~t);
3124		SET_N8(t);
3125		SET_Z8(t);
3126
3127		m_icount -= 10;
3128		}
3129
3130		void tms7000_device::sub_ia()
3131		{
3132		UINT16  t;
3133		UINT8   i;
3134
3135		IMMBYTE(i);
3136		t = RDA - i;
3137		WRA(t);
3138
3139		CLR_NZC;
3140		SET_C8(~t);
3141		SET_N8(t);
3142		SET_Z8(t);
3143
3144		m_icount -= 7;
3145		}
3146
3147		void tms7000_device::sub_ib()
3148		{
3149		UINT16  t;
3150		UINT8   i;
3151
3152		IMMBYTE(i);
3153		t = RDB - i;
3154		WRB(t);
3155
3156		CLR_NZC;
3157		SET_C8(~t);
3158		SET_N8(t);
3159		SET_Z8(t);
3160
3161		m_icount -= 7;
3162		}
3163
3164		void tms7000_device::sub_ir()
3165		{
3166		UINT16  t;
3167		UINT8   r,i;
3168
3169		IMMBYTE(i);
3170		IMMBYTE(r);
3171		t = RM(r) - i;
3172		WM(r,t);
3173
3174		CLR_NZC;
3175		SET_C8(~t);
3176		SET_N8(t);
3177		SET_Z8(t);
3178
3179		m_icount -= 9;
3180		}
3181
3182		void tms7000_device::trap_0()
3183		{
3184		PUSHWORD( PC );
3185		pPC = RM16(0xfffe);
3186		m_icount -= 14;
3187		}
3188
3189		void tms7000_device::trap_1()
3190		{
3191		PUSHWORD( PC );
3192		pPC = RM16(0xfffc);
3193		m_icount -= 14;
3194		}
3195
3196		void tms7000_device::trap_2()
3197		{
3198		PUSHWORD( PC );
3199		pPC = RM16(0xfffa);
3200		m_icount -= 14;
3201		}
3202
3203		void tms7000_device::trap_3()
3204		{
3205		PUSHWORD( PC );
3206		pPC = RM16(0xfff8);
3207		m_icount -= 14;
3208		}
3209
3210		void tms7000_device::trap_4()
3211		{
3212		PUSHWORD( PC );
3213		pPC = RM16(0xfff6);
3214		m_icount -= 14;
3215		}
3216
3217		void tms7000_device::trap_5()
3218		{
3219		PUSHWORD( PC );
3220		pPC = RM16(0xfff4);
3221		m_icount -= 14;
3222		}
3223
3224		void tms7000_device::trap_6()
3225		{
3226		PUSHWORD( PC );
3227		pPC = RM16(0xfff2);
3228		m_icount -= 14;
3229		}
3230
3231		void tms7000_device::trap_7()
3232		{
3233		PUSHWORD( PC );
3234		pPC = RM16(0xfff0);
3235		m_icount -= 14;
3236		}
3237
3238		void tms7000_device::trap_8()
3239		{
3240		PUSHWORD( PC );
3241		pPC = RM16(0xffee);
3242		m_icount -= 14;
3243		}
3244
3245		void tms7000_device::trap_9()
3246		{
3247		PUSHWORD( PC );
3248		pPC = RM16(0xffec);
3249		m_icount -= 14;
3250		}
3251
3252		void tms7000_device::trap_10()
3253		{
3254		PUSHWORD( PC );
3255		pPC = RM16(0xffea);
3256		m_icount -= 14;
3257		}
3258
3259		void tms7000_device::trap_11()
3260		{
3261		PUSHWORD( PC );
3262		pPC = RM16(0xffe8);
3263		m_icount -= 14;
3264		}
3265
3266		void tms7000_device::trap_12()
3267		{
3268		PUSHWORD( PC );
3269		pPC = RM16(0xffe6);
3270		m_icount -= 14;
3271		}
3272
3273		void tms7000_device::trap_13()
3274		{
3275		PUSHWORD( PC );
3276		pPC = RM16(0xffe4);
3277		m_icount -= 14;
3278		}
3279
3280		void tms7000_device::trap_14()
3281		{
3282		PUSHWORD( PC );
3283		pPC = RM16(0xffe2);
3284		m_icount -= 14;
3285		}
3286
3287		void tms7000_device::trap_15()
3288		{
3289		PUSHWORD( PC );
3290		pPC = RM16(0xffe0);
3291		m_icount -= 14;
3292		}
3293
3294		void tms7000_device::trap_16()
3295		{
3296		PUSHWORD( PC );
3297		pPC = RM16(0xffde);
3298		m_icount -= 14;
3299		}
3300
3301		void tms7000_device::trap_17()
3302		{
3303		PUSHWORD( PC );
3304		pPC = RM16(0xffdc);
3305		m_icount -= 14;
3306		}
3307
3308		void tms7000_device::trap_18()
3309		{
3310		PUSHWORD( PC );
3311		pPC = RM16(0xffda);
3312		m_icount -= 14;
3313		}
3314
3315		void tms7000_device::trap_19()
3316		{
3317		PUSHWORD( PC );
3318		pPC = RM16(0xffd8);
3319		m_icount -= 14;
3320		}
3321
3322		void tms7000_device::trap_20()
3323		{
3324		PUSHWORD( PC );
3325		pPC = RM16(0xffd6);
3326		m_icount -= 14;
3327		}
3328
3329		void tms7000_device::trap_21()
3330		{
3331		PUSHWORD( PC );
3332		pPC = RM16(0xffd4);
3333		m_icount -= 14;
3334		}
3335
3336		void tms7000_device::trap_22()
3337		{
3338		PUSHWORD( PC );
3339		pPC = RM16(0xffd2);
3340		m_icount -= 14;
3341		}
3342
3343		void tms7000_device::trap_23()
3344		{
3345		PUSHWORD( PC );
3346		pPC = RM16(0xffd0);
3347		m_icount -= 14;
3348		}
3349
3350		void tms7000_device::swap_a()
3351		{
3352		UINT8   a,b;
3353		UINT16  t;
3354
3355		a = b = RDA;
3356
3357		a <<= 4;
3358		b >>= 4;
3359		t = a+b;
3360
3361		WRA(t);
3362
3363		CLR_NZC;
3364
3365		pSR|=((t&0x0001)<<7);
3366		SET_N8(t);
3367		SET_Z8(t);
3368
3369		m_icount -=8;
3370		}
3371
3372		void tms7000_device::swap_b()
3373		{
3374		UINT8   a,b;
3375		UINT16  t;
3376
3377		a = b = RDB;
3378
3379		a <<= 4;
3380		b >>= 4;
3381		t = a+b;
3382
3383		WRB(t);
3384
3385		CLR_NZC;
3386
3387		pSR|=((t&0x0001)<<7);
3388		SET_N8(t);
3389		SET_Z8(t);
3390
3391		m_icount -=8;
3392		}
3393
3394		void tms7000_device::swap_r()
3395		{
3396		UINT8   a,b,r;
3397		UINT16  t;
3398
3399		IMMBYTE(r);
3400		a = b = RM(r);
3401
3402		a <<= 4;
3403		b >>= 4;
3404		t = a+b;
3405
3406		WM(r,t);
3407
3408		CLR_NZC;
3409
3410		pSR|=((t&0x0001)<<7);
3411		SET_N8(t);
3412		SET_Z8(t);
3413
3414		m_icount -=8;
3415		}
3416
3417		void tms7000_device::swap_r_exl()
3418		{
3419		UINT16   t;
3420
3421		SKIPBYTE();
3422
3423		/* opcode D7 ?? (LVDP) mostly equivalent to
3424		* MOVP P40,xx
3425		* MOVP P36,A
3426		*/
3427		RM(0x0128);
3428		t=RM(0x0124);
3429		WM(0,t);
3430
3431		CLR_NZC;
3432		SET_N8(t);
3433		SET_Z8(t);
3434
3435		m_icount -= 9;   /* FIXME : check real timing */
3436		}
3437
3438		void tms7000_device::tstb()
3439		{
3440		UINT16  t;
3441
3442		t=RDB;
3443
3444		CLR_NZC;
3445		SET_N8(t);
3446		SET_Z8(t);
3447
3448		m_icount -= 6;
3449		}
3450
3451		void tms7000_device::xchb_a()
3452		{
3453		UINT16  t,u;
3454
3455		t = RDB;
3456		u = RDA;
3457
3458		WRA(t);
3459		WRB(u);
3460
3461		CLR_NZC;
3462		SET_N8(t);
3463		SET_Z8(t);
3464
3465		m_icount -= 6;
3466		}
3467
3468		void tms7000_device::xchb_b()
3469		{
3470		UINT16  t;
3471
3472		t = RDB;
3473
3474		CLR_NZC;
3475		SET_N8(t);
3476		SET_Z8(t);
3477
3478		m_icount -= 6;
3479		}
3480
3481		void tms7000_device::xchb_r()
3482		{
3483		UINT16  t,u;
3484		UINT8   r;
3485
3486		IMMBYTE(r);
3487
3488		t = RDB;
3489		u = RM(r);
3490
3491		WM(r,t);
3492		WRB(u);
3493
3494		CLR_NZC;
3495		SET_N8(t);
3496		SET_Z8(t);
3497
3498		m_icount -= 8;
3499		}
3500
3501		void tms7000_device::xor_b2a()
3502		{
3503		UINT8   t;
3504
3505		t = RDA ^ RDB;
3506		WRA(t);
3507
3508		CLR_NZC;
3509		SET_N8(t);
3510		SET_Z8(t);
3511
3512		m_icount -= 5;
3513		}
3514
3515		void tms7000_device::xor_r2a()
3516		{
3517		UINT8   t;
3518		UINT8   v;
3519
3520		IMMBYTE(v);
3521
3522		t = RM(v) ^ RDA;
3523		WRA(t);
3524
3525		CLR_NZC;
3526		SET_N8(t);
3527		SET_Z8(t);
3528
3529		m_icount -= 8;
3530		}
3531
3532		void tms7000_device::xor_r2b()
3533		{
3534		UINT8   t;
3535		UINT8   v;
3536
3537		IMMBYTE(v);
3538
3539		t = RM(v) ^ RDB;
3540		WRB(t);
3541
3542		CLR_NZC;
3543		SET_N8(t);
3544		SET_Z8(t);
3545
3546		m_icount -= 8;
3547		}
3548
3549		void tms7000_device::xor_r2r()
3550		{
3551		UINT8   t;
3552		UINT8   i,j;
3553
3554		IMMBYTE(i);
3555		IMMBYTE(j);
3556
3557		t = RM(i) ^ RM(j);
3558		WM(j,t);
3559
3560		CLR_NZC;
3561		SET_N8(t);
3562		SET_Z8(t);
3563
3564		m_icount -= 10;
3565		}
3566
3567		void tms7000_device::xor_i2a()
3568		{
3569		UINT8   t;
3570		UINT8   v;
3571
3572		IMMBYTE(v);
3573
3574		t = v ^ RDA;
3575		WRA(t);
3576
3577		CLR_NZC;
3578		SET_N8(t);
3579		SET_Z8(t);
3580
3581		m_icount -= 7;
3582		}
3583
3584		void tms7000_device::xor_i2b()
3585		{
3586		UINT8   t;
3587		UINT8   v;
3588
3589		IMMBYTE(v);
3590
3591		t = v ^ RDB;
3592		WRB(t);
3593
3594		CLR_NZC;
3595		SET_N8(t);
3596		SET_Z8(t);
3597
3598		m_icount -= 7;
3599		}
3600
3601		void tms7000_device::xor_i2r()
3602		{
3603		UINT8   t;
3604		UINT8   i,j;
3605
3606		IMMBYTE(i);
3607		IMMBYTE(j);
3608
3609		t = i ^ RM(j);
3610		WM(j,t);
3611
3612		CLR_NZC;
3613		SET_N8(t);
3614		SET_Z8(t);
3615
3616		m_icount -= 9;
3617		}
3618
3619		void tms7000_device::xorp_a2p()
3620		{
3621		UINT8   t;
3622		UINT8   v;
3623
3624		IMMBYTE(v);
3625		t = RDA ^ RM( 0x0100 + v);
3626		WM( 0x0100+v, t);
3627
3628		CLR_NZC;
3629		SET_N8(t);
3630		SET_Z8(t);
3631
3632		m_icount -= 10;
3633		}
3634
3635		void tms7000_device::xorp_b2p()
3636		{
3637		UINT8   t;
3638		UINT8   v;
3639
3640		IMMBYTE(v);
3641		t = RDB ^ RM( 0x0100 + v);
3642		WM( 0x0100+v, t);
3643
3644		CLR_NZC;
3645		SET_N8(t);
3646		SET_Z8(t);
3647
3648		m_icount -= 9;
3649		}
3650
3651		void tms7000_device::xorp_i2p()
3652		{
3653		UINT8   t;
3654		UINT8   i,v;
3655
3656		IMMBYTE(i);
3657		IMMBYTE(v);
3658		t = i ^ RM( 0x0100 + v);
3659		WM( 0x0100+v, t);
3660
3661		CLR_NZC;
3662		SET_N8(t);
3663		SET_Z8(t);
3664
3665		m_icount -= 11;
3666		}

trunk/src/emu/cpu/cpu.mak

r31296	r31297
2011	2011
2012	2012	$(CPUOBJ)/tms7000/tms7000.o:    $(CPUSRC)/tms7000/tms7000.h \
2013	2013	$(CPUSRC)/tms7000/tms7000.c \
2014		$(CPUSRC)/tms7000/tms70op.inc \
2015		$(CPUSRC)/tms7000/tms70tb.inc
	2014	$(CPUSRC)/tms7000/tms70op.inc
2016	2015
2017	2016	$(CPUOBJ)/tms7000/7000dasm.o:   $(CPUSRC)/tms7000/tms7000.h \
2018	2017	$(CPUSRC)/tms7000/7000dasm.c

trunk/src/mess/drivers/exelv.c

r31296	r31297
223	223
224	224	READ8_MEMBER(exelv_state::mailbox_wx319_r)
225	225	{
226		logerror("[TMS7220] reading mailbox %d", m_wx319);
	226	logerror("[TMS7220] reading mailbox %d\n", m_wx319);
227	227	return m_wx319;
228	228	}
229	229
r31296	r31297
325	325	m_tms5220c->rsq_w((data & 0x02) ? 1 : 0);
326	326
327	327	logerror("TMS7020 %s int1\n",((data & 0x04) ? "clear" : "assert"));
328		m_maincpu->set_input_line(TMS7000_IRQ1_LINE, (data & 0x04) ? CLEAR_LINE : ASSERT_LINE);
	328	m_maincpu->set_input_line(TMS7000_INT1_LINE, (data & 0x04) ? CLEAR_LINE : ASSERT_LINE);
329	329
330	330	/* Check for low->high transition on B6 */
331	331	if (!(m_tms7041_portb & 0x40) && (data & 0x40))
r31296	r31297
434	434	AM_RANGE(TMS7000_PORTB, TMS7000_PORTB) AM_WRITE(tms7020_portb_w)
435	435	ADDRESS_MAP_END
436	436
437
438		static ADDRESS_MAP_START(tms7041_map, AS_PROGRAM, 8, exelv_state)
439		AM_RANGE(0x0080, 0x00ff) AM_RAM
440		ADDRESS_MAP_END
441
442	437	static ADDRESS_MAP_START(tms7041_port, AS_IO, 8, exelv_state)
443	438	AM_RANGE(TMS7000_PORTA, TMS7000_PORTA) AM_READ(tms7041_porta_r)
444	439	AM_RANGE(TMS7000_PORTB, TMS7000_PORTB) AM_WRITE(tms7041_portb_w)
r31296	r31297
462	457	ADDRESS_MAP_END
463	458
464	459
465		static ADDRESS_MAP_START(tms7042_map, AS_PROGRAM, 8, exelv_state)
466		AM_RANGE(0x0080, 0x00ff) AM_RAM
467		ADDRESS_MAP_END
468
469
470	460	/* keyboard: ??? */
471	461	static INPUT_PORTS_START(exelv)
472	462
r31296	r31297
515	505	MCFG_CPU_IO_MAP(tms7020_port)
516	506	MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", exelv_state, exelv_hblank_interrupt, "screen", 0, 1)
517	507
518		MCFG_CPU_ADD("tms7041", TMS7040, XTAL_4_9152MHz) // should be TMS7041
519		MCFG_CPU_PROGRAM_MAP(tms7041_map)
	508	MCFG_CPU_ADD("tms7041", TMS7041, XTAL_4_9152MHz)
520	509	MCFG_CPU_IO_MAP(tms7041_port)
521	510
522	511	MCFG_QUANTUM_PERFECT_CPU("maincpu")
r31296	r31297
567	556	MCFG_CPU_IO_MAP(tms7020_port)
568	557	MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", exelv_state, exelv_hblank_interrupt, "screen", 0, 1)
569	558
570		MCFG_CPU_ADD("tms7042", TMS7040, XTAL_4_9152MHz) // should be TMS7042
571		MCFG_CPU_PROGRAM_MAP(tms7042_map)
	559	MCFG_CPU_ADD("tms7042", TMS7042, XTAL_4_9152MHz)
572	560	MCFG_CPU_IO_MAP(tms7041_port)
573	561
574	562	MCFG_QUANTUM_PERFECT_CPU("maincpu")

trunk/src/mess/drivers/cc40.c

r31296	r31297
36	36
37	37	HM6116LP-4    - Hitachi 2KB SRAM
38	38	HN61256PC09   - Hitachi DIP-28 32KB CMOS Mask PROM
39		TMX70C20N2L   - Texas Instruments TMS70C20 CPU (128 bytes RAM, 2KB ROM) @ 2.5MHz - "X" implies prototype?
	39	TMX70C20N2L   - Texas Instruments TMS70C20 CPU (128 bytes RAM, 2KB ROM) @ 2.5MHz - "X" implies prototype
40	40	AMI 8304BXH   - 74-pin QFP AMI Gate Array
41	41	HD44100H      - 60-pin QFP Hitachi HD44100 LCD Driver
42	42	HD44780A00    - 80-pin TFP Hitachi HD44780 LCD Controller

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