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| r31291 Tuesday 15th July, 2014 at 22:04:00 UTC by Carl |
|---|
| (mess) rmnimbus: make scsi work (nw) scsi: synchronize the data output lines with the input buffer device (nw) --- The nimbus reads the disk but it won't accept a PC MBR so without the missing machine specific fdisk it isn't possible to create a partition table |
| [src/emu/bus/scsi] | scsi.c |
| [src/emu/cpu/i86] | i186.h |
| [src/mess/includes] | rmnimbus.h |
| [src/mess/machine] | rmnimbus.c |
| r31290 | r31291 | |
|---|---|---|
| 111 | 111 | static const device_timer_id TIMER_INT0 = 0; |
| 112 | 112 | static const device_timer_id TIMER_INT1 = 1; |
| 113 | 113 | static const device_timer_id TIMER_INT2 = 2; |
| 114 | static const device_timer_id TIMER_TIME0 = 3; | |
| 115 | static const device_timer_id TIMER_TIME1 = 4; | |
| 116 | static const device_timer_id TIMER_TIME2 = 5; | |
| 117 | 114 | |
| 118 | 115 | struct timer_state m_timer[3]; |
| 119 | 116 | struct dma_state m_dma[2]; |
| r31290 | r31291 | |
|---|---|---|
| 113 | 113 | m_data5_handler.resolve_safe(); |
| 114 | 114 | m_data6_handler.resolve_safe(); |
| 115 | 115 | m_data7_handler.resolve_safe(); |
| 116 | ||
| 117 | m_data0_handler(0); | |
| 118 | m_data1_handler(0); | |
| 119 | m_data2_handler(0); | |
| 120 | m_data3_handler(0); | |
| 121 | m_data4_handler(0); | |
| 122 | m_data5_handler(0); | |
| 123 | m_data6_handler(0); | |
| 124 | m_data7_handler(0); | |
| 116 | 125 | } |
| 117 | 126 | |
| 118 | 127 | void SCSI_PORT_DEVICE::update_bsy() |
| r31290 | r31291 | |
|---|---|---|
| 6 | 6 | Phill Harvey-Smith |
| 7 | 7 | 2009-11-29. |
| 8 | 8 | |
| 9 | 80186 internal DMA/Timer/PIC code borrowed from Compis driver. | |
| 10 | Perhaps this needs merging into the 80186 core..... | |
| 11 | 9 | */ |
| 12 | 10 | |
| 13 | 11 | /* |
| r31290 | r31291 | |
| 1131 | 1129 | |
| 1132 | 1130 | // if we enable hdc drq with a pending condition, act on it |
| 1133 | 1131 | if((data & HDC_DRQ_MASK) && (~reg400_old & HDC_DRQ_MASK)) |
| 1134 | hdc_drq(); | |
| 1132 | hdc_drq(true); | |
| 1135 | 1133 | } |
| 1136 | 1134 | |
| 1137 | 1135 | /* |
| r31290 | r31291 | |
| 1164 | 1162 | |
| 1165 | 1163 | void rmnimbus_state::hdc_reset() |
| 1166 | 1164 | { |
| 1167 | m_nimbus_drives.drq_ff=0; | |
| 1168 | 1165 | m_scsi_iena = 0; |
| 1169 | 1166 | m_scsi_msg = 0; |
| 1170 | 1167 | m_scsi_bsy = 0; |
| r31290 | r31291 | |
| 1188 | 1185 | { |
| 1189 | 1186 | if(m_scsi_req) |
| 1190 | 1187 | m_scsibus->write_ack(1); |
| 1191 | ||
| 1192 | m_nimbus_drives.drq_ff=0; | |
| 1193 | 1188 | } |
| 1194 | 1189 | |
| 1195 | void rmnimbus_state::hdc_drq() | |
| 1190 | void rmnimbus_state::hdc_drq(bool state) | |
| 1196 | 1191 | { |
| 1197 | if(HDC_DRQ_ENABLED() && m_nimbus_drives.drq_ff) | |
| 1198 | { | |
| 1199 | m_maincpu->drq1_w(1); | |
| 1200 | } | |
| 1192 | m_maincpu->drq1_w(HDC_DRQ_ENABLED() && !m_scsi_cd && state); | |
| 1201 | 1193 | } |
| 1202 | 1194 | |
| 1203 | 1195 | WRITE_LINE_MEMBER( rmnimbus_state::write_scsi_bsy ) |
| r31290 | r31291 | |
| 1234 | 1226 | |
| 1235 | 1227 | if (state) |
| 1236 | 1228 | { |
| 1237 | if (m_scsi_cd && last) | |
| 1229 | if (!m_scsi_cd && !last) | |
| 1238 | 1230 | { |
| 1239 | m_nimbus_drives.drq_ff=1; | |
| 1240 | hdc_drq(); | |
| 1231 | hdc_drq(true); | |
| 1241 | 1232 | } |
| 1242 | 1233 | } |
| 1243 | 1234 | else |
| 1244 | 1235 | { |
| 1236 | hdc_drq(false); | |
| 1245 | 1237 | m_scsibus->write_ack(0); |
| 1246 | 1238 | } |
| 1247 | 1239 | check_scsi_irq(); |
| r31290 | r31291 | |
|---|---|---|
| 151 | 151 | void hdc_reset(); |
| 152 | 152 | void hdc_ctrl_write(UINT8 data); |
| 153 | 153 | void hdc_post_rw(); |
| 154 | void hdc_drq(); | |
| 154 | void hdc_drq(bool state); | |
| 155 | 155 | void pc8031_reset(); |
| 156 | 156 | //void ipc_dumpregs(); |
| 157 | 157 | void iou_reset(); |
| r31290 | r31291 | |
| 177 | 177 | struct |
| 178 | 178 | { |
| 179 | 179 | UINT8 reg400; |
| 180 | UINT8 reg418; | |
| 181 | ||
| 182 | UINT8 drq_ff; | |
| 183 | 180 | } m_nimbus_drives; |
| 184 | 181 | |
| 185 | 182 | /* 8031 Peripheral controler */ |
| r31290 | r31291 | |
| 189 | 186 | UINT8 ipc_out; |
| 190 | 187 | UINT8 status_in; |
| 191 | 188 | UINT8 status_out; |
| 192 | UINT8 int_8c_pending; | |
| 193 | UINT8 int_8e_pending; | |
| 194 | UINT8 int_8f_pending; | |
| 195 | 189 | } m_ipc_interface; |
| 196 | 190 | |
| 197 | 191 | /* Mouse/Joystick */ |
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