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r31224 Monday 7th July, 2014 at 21:35:48 UTC by Carl
(mess) rmnimbus: more refactoring, simplfy and better document the video controller (nw)
[src/mess/drivers]rmnimbus.c
[src/mess/includes]rmnimbus.h
[src/mess/machine]rmnimbus.c
[src/mess/video]rmnimbus.c

trunk/src/mess/drivers/rmnimbus.c
r31223r31224
8282static ADDRESS_MAP_START(nimbus_iocpu_mem, AS_PROGRAM, 8, rmnimbus_state )
8383   ADDRESS_MAP_UNMAP_HIGH
8484   AM_RANGE(0x0000, 0x1fff) AM_ROM
85   //AM_RANGE(0x2000, 0x7fff) AM_RAM
8685ADDRESS_MAP_END
8786
8887static ADDRESS_MAP_START( nimbus_iocpu_io , AS_IO, 8, rmnimbus_state )
8988   ADDRESS_MAP_UNMAP_HIGH
9089   AM_RANGE(0x00000, 0x000FF) AM_READWRITE(nimbus_pc8031_iou_r, nimbus_pc8031_iou_w)
91   //AM_RANGE(0x00010, 0x07fff) AM_RAM
9290   AM_RANGE(0x20000, 0x20004) AM_READWRITE(nimbus_pc8031_port_r, nimbus_pc8031_port_w)
9391ADDRESS_MAP_END
9492
trunk/src/mess/machine/rmnimbus.c
r31223r31224
6464/* Defines, constants, and global variables                                */
6565/*-------------------------------------------------------------------------*/
6666
67#define LOG_KEYBOARD        0
67/* External int vectors for chained interrupts */
68#define EXTERNAL_INT_DISK       0x80
69#define EXTERNAL_INT_MSM5205    0x84
70#define EXTERNAL_INT_MOUSE_YU   0x88
71#define EXTERNAL_INT_MOUSE_YD   0x89
72#define EXTERNAL_INT_MOUSE_XL   0x8A
73#define EXTERNAL_INT_MOUSE_XR   0x8B
74#define EXTERNAL_INT_PC8031_8C  0x8c
75#define EXTERNAL_INT_PC8031_8E  0x8E
76#define EXTERNAL_INT_PC8031_8F  0x8F
77
78#define HDC_DRQ_MASK        0x40
79#define FDC_SIDE()          ((m_nimbus_drives.reg400 & 0x10) >> 4)
80#define FDC_MOTOR()         ((m_nimbus_drives.reg400 & 0x20) >> 5)
81#define FDC_DRIVE()         (fdc_driveno(m_nimbus_drives.reg400 & 0x0f))
82#define HDC_DRQ_ENABLED()   ((m_nimbus_drives.reg400 & 0x40) ? 1 : 0)
83#define FDC_DRQ_ENABLED()   ((m_nimbus_drives.reg400 & 0x80) ? 1 : 0)
84
85/* 8031/8051 Peripheral controller */
86
87#define IPC_OUT_ADDR        0X01
88#define IPC_OUT_READ_PEND   0X02
89#define IPC_OUT_BYTE_AVAIL  0X04
90
91#define IPC_IN_ADDR         0X01
92#define IPC_IN_BYTE_AVAIL   0X02
93#define IPC_IN_READ_PEND    0X04
94
95/* IO unit */
96
97#define DISK_INT_ENABLE         0x01
98#define MSM5205_INT_ENABLE      0x04
99#define MOUSE_INT_ENABLE        0x08
100#define PC8031_INT_ENABLE       0x10
101
102enum
103{
104   MOUSE_PHASE_STATIC = 0,
105   MOUSE_PHASE_POSITIVE,
106   MOUSE_PHASE_NEGATIVE
107};
108
109#define MOUSE_INT_ENABLED(state)     (((state)->m_iou_reg092 & MOUSE_INT_ENABLE) ? 1 : 0)
110
111#define VIA_INT                 0x03
112
113#define LINEAR_ADDR(seg,ofs)    ((seg<<4)+ofs)
114
115#define OUTPUT_SEGOFS(mess,seg,ofs)  logerror("%s=%04X:%04X [%08X]\n",mess,seg,ofs,((seg<<4)+ofs))
116
68117#define LOG_SIO             0
69#define LOG_DISK_FDD        0
70118#define LOG_DISK_HDD        0
71119#define LOG_DISK            0
72120#define LOG_PC8031          0
73121#define LOG_PC8031_186      0
74122#define LOG_PC8031_PORT     0
75123#define LOG_IOU             0
76#define LOG_SOUND           0
77124#define LOG_RAM             0
78125
79126/* Debugging */
trunk/src/mess/includes/rmnimbus.h
r31223r31224
1919
2020#define MAINCPU_TAG "maincpu"
2121#define IOCPU_TAG   "iocpu"
22#define Z80SIO_TAG  "z80sio"
23#define FDC_TAG     "wd2793"
24#define SCSIBUS_TAG "scsibus"
25#define ER59256_TAG "er59256"
26#define AY8910_TAG  "ay8910"
27#define MONO_TAG    "mono"
28#define MSM5205_TAG "msm5205"
29#define VIA_TAG     "via6522"
30#define CENTRONICS_TAG "centronics"
2231
23/* Nimbus specific */
32/* Mouse / Joystick */
2433
25/* External int vectors for chained interupts */
26#define EXTERNAL_INT_DISK       0x80
27#define EXTERNAL_INT_MSM5205    0x84
28#define EXTERNAL_INT_MOUSE_YU   0x88
29#define EXTERNAL_INT_MOUSE_YD   0x89
30#define EXTERNAL_INT_MOUSE_XL   0x8A
31#define EXTERNAL_INT_MOUSE_XR   0x8B
32#define EXTERNAL_INT_PC8031_8C  0x8c
33#define EXTERNAL_INT_PC8031_8E  0x8E
34#define EXTERNAL_INT_PC8031_8F  0x8F
34#define JOYSTICK0_TAG           "joystick0"
35#define MOUSE_BUTTON_TAG        "mousebtn"
36#define MOUSEX_TAG              "mousex"
37#define MOUSEY_TAG              "mousey"
3538
36
37/* Memory controler */
39/* Memory controller */
3840#define RAM_BANK00_TAG  "bank0"
3941#define RAM_BANK01_TAG  "bank1"
4042#define RAM_BANK02_TAG  "bank2"
r31223r31224
4446#define RAM_BANK06_TAG  "bank6"
4547#define RAM_BANK07_TAG  "bank7"
4648
47#define HIBLOCK_BASE_MASK   0x08
48#define HIBLOCK_SELECT_MASK 0x10
49
50/* Z80 SIO for keyboard */
51
52#define Z80SIO_TAG          "z80sio"
53
54/* Floppy/Fixed drive interface */
55
56#define FDC_TAG                 "wd2793"
57
58#define NO_DRIVE_SELECTED   0xFF
59
60/* SASI harddisk interface */
61#define SCSIBUS_TAG             "scsibus"
62
63/* Masks for writes to port 0x400 */
64#define FDC_DRIVE0_MASK 0x01
65#define FDC_DRIVE1_MASK 0x02
66#define FDC_DRIVE2_MASK 0x04
67#define FDC_DRIVE3_MASK 0x08
68#define FDC_SIDE_MASK   0x10
69#define FDC_MOTOR_MASKO 0x20
70#define HDC_DRQ_MASK    0x40
71#define FDC_DRQ_MASK    0x80
72#define FDC_DRIVE_MASK  (FDC_DRIVE0_MASK | FDC_DRIVE1_MASK | FDC_DRIVE2_MASK | FDC_DRIVE3_MASK)
73
74#define FDC_SIDE()          ((m_nimbus_drives.reg400 & FDC_SIDE_MASK) >> 4)
75#define FDC_MOTOR()         ((m_nimbus_drives.reg400 & FDC_MOTOR_MASKO) >> 5)
76#define FDC_DRIVE()         (fdc_driveno(m_nimbus_drives.reg400 & FDC_DRIVE_MASK))
77#define HDC_DRQ_ENABLED()   ((m_nimbus_drives.reg400 & HDC_DRQ_MASK) ? 1 : 0)
78#define FDC_DRQ_ENABLED()   ((m_nimbus_drives.reg400 & FDC_DRQ_MASK) ? 1 : 0)
79
80
81/* 8031/8051 Peripheral controler */
82
83#define IPC_OUT_ADDR        0X01
84#define IPC_OUT_READ_PEND   0X02
85#define IPC_OUT_BYTE_AVAIL  0X04
86
87#define IPC_IN_ADDR         0X01
88#define IPC_IN_BYTE_AVAIL   0X02
89#define IPC_IN_READ_PEND    0X04
90
91
92
93
94#define ER59256_TAG             "er59256"
95
96/* IO unit */
97
98#define DISK_INT_ENABLE         0x01
99#define MSM5205_INT_ENABLE      0x04
100#define MOUSE_INT_ENABLE        0x08
101#define PC8031_INT_ENABLE       0x10
102
103
104/* Sound hardware */
105
106#define AY8910_TAG              "ay8910"
107#define MONO_TAG                "mono"
108
109
110
111
112#define MSM5205_TAG             "msm5205"
113
114/* Mouse / Joystick */
115
116#define JOYSTICK0_TAG           "joystick0"
117#define MOUSE_BUTTON_TAG        "mousebtn"
118#define MOUSEX_TAG              "mousex"
119#define MOUSEY_TAG              "mousey"
120
121enum
122{
123   MOUSE_PHASE_STATIC = 0,
124   MOUSE_PHASE_POSITIVE,
125   MOUSE_PHASE_NEGATIVE
126};
127
128
129#define MOUSE_INT_ENABLED(state)     (((state)->m_iou_reg092 & MOUSE_INT_ENABLE) ? 1 : 0)
130
131/* Paralell / User port BBC compatible ! */
132
133#define VIA_TAG                 "via6522"
134#define CENTRONICS_TAG          "centronics"
135
136#define VIA_INT                 0x03
137
138#define LINEAR_ADDR(seg,ofs)    ((seg<<4)+ofs)
139
140#define OUTPUT_SEGOFS(mess,seg,ofs)  logerror("%s=%04X:%04X [%08X]\n",mess,seg,ofs,((seg<<4)+ofs))
141
14249class rmnimbus_state : public driver_device
14350{
14451public:
r31223r31224
18491   UINT8 m_last_playmode;
18592   UINT8 m_ay8910_a;
18693   UINT8 m_sio_int_state;
187   UINT16 m_vidregs[24];
188   UINT16 m_x, m_y;
94   UINT16 m_x, m_y, m_yline;
95   UINT8 m_colours, m_mode, m_op;
18996   UINT32 m_debug_video;
19097   UINT8 m_vector;
19198   UINT8 m_eeprom_bits;
r31223r31224
236143   void write_pixel_line(UINT16 x, UINT16 y, UINT16, UINT8 pixels, UINT8 bpp);
237144   void move_pixel_line(UINT16 x, UINT16 y, UINT8 width);
238145   void write_pixel_data(UINT16 x, UINT16 y, UINT16    data);
239   void write_reg_004();
240   void write_reg_006();
241   void write_reg_00A();
242   void write_reg_00E();
243   void write_reg_010();
244   void write_reg_012();
245   void write_reg_014();
246   void write_reg_016();
247   void write_reg_01A();
248   void write_reg_01C();
249   void write_reg_01E();
250   void write_reg_026();
251146   void change_palette(UINT8 bank, UINT16 colours);
252147   void external_int(UINT16 intno, UINT8 vector);
253148   DECLARE_READ8_MEMBER(cascade_callback);
trunk/src/mess/video/rmnimbus.c
r31223r31224
2929
3030#define WIDTH_MASK      0x07
3131
32// Offsets of nimbus video registers within register array
33
34#define reg000          0x00
35#define reg002          0x01
36#define reg004          0x02
37#define reg006          0x03
38#define reg008          0x04
39#define reg00A          0x05
40#define reg00C          0x06
41#define reg00E          0x07
42#define reg010          0x08
43#define reg012          0x09
44#define reg014          0x0A
45#define reg016          0x0B
46#define reg018          0x0C
47#define reg01A          0x0D
48#define reg01C          0x0E
49#define reg01E          0x0F
50#define reg020          0x10
51#define reg022          0x11
52#define reg024          0x12
53#define reg026          0x13
54#define reg028          0x14
55#define reg02A          0x15
56#define reg02C          0x16
57#define reg02E          0x17
58
59#define FG_COLOUR       (m_vidregs[reg024]&0x0F)
60#define BG_COLOUR       ((m_vidregs[reg024]&0xF0)>>4)
32#define FG_COLOUR       (m_colours&0x0F)
33#define BG_COLOUR       ((m_colours&0xF0)>>4)
6134#define SELECT_COL(x,c)   (IS_80COL ? ((((x) & 1) ? ((c) << 2) : (c)) & 0xC) : (c))
6235#define FILL_WORD(c)   (((c) << 12) | ((c) << 8) | ((c) << 4) | (c))
6336
64#define IS_80COL        (m_vidregs[reg026]&0x10)
65#define IS_XOR          (m_vidregs[reg022]&8)
37#define IS_80COL        (m_mode&0x10)
38#define IS_XOR          (m_op&8)
6639
6740#define DEBUG_TEXT  0x01
6841#define DEBUG_DB    0x02
r31223r31224
7245
7346static void video_debug(running_machine &machine, int ref, int params, const char *param[]);
7447
75/*
76    I'm not sure which of thes return values on a real machine, so for the time being I'm going
77    to return the values for all of them, it doesn't seem to hurt !
78*/
79
8048READ16_MEMBER(rmnimbus_state::nimbus_video_io_r)
8149{
82   int     pc=space.device().safe_pc();
83   UINT16  result;
50   UINT16 result = 0;
8451
8552   switch (offset)
8653   {
87      case    reg000  : result=read_pixel_data(m_vidregs[reg002],m_vidregs[reg00C]); break;
88      case    reg002  : result=m_vidregs[reg002]; break;
89      case    reg004  : result=read_pixel_data(m_vidregs[reg002],++m_vidregs[reg00C]); break;
90      case    reg006  : result=m_vidregs[reg006]; break;
91      case    reg008  : result=m_vidregs[reg008]; break;
92      case    reg00A  : result=read_pixel_data(++m_vidregs[reg002],m_vidregs[reg00C]); break;
93      case    reg00C  : result=m_vidregs[reg00C]; break;
94      case    reg00E  : result=m_vidregs[reg00E]; break;
54      case 0x00:
55      case 0x08:
56         result = read_pixel_data(m_x, m_y);
57         break;
58      case 0x02:
59      case 0x0A:
60         result = read_pixel_data(m_x, ++m_y);
61         break;
62      case 0x05:
63      case 0x0D:
64         result = read_pixel_data(++m_x, m_y);
65         break;
9566
96      case    reg010  : result=read_pixel_data(m_vidregs[reg002],m_vidregs[reg00C]); break;
97      case    reg012  : result=m_vidregs[reg012]; break;
98      case    reg014  : result=m_vidregs[reg014]; break;
99      case    reg016  : result=m_vidregs[reg016]; break;
100      case    reg018  : result=m_vidregs[reg018]; break;
101      case    reg01A  : result=read_pixel_data(++m_vidregs[reg002],m_vidregs[reg00C]); break;
102      case    reg01C  : result=m_vidregs[reg01C]; break;
103      case    reg01E  : result=m_vidregs[reg01E]; break;
104
105      case    reg020  : result=m_vidregs[reg020]; break;
106      case    reg022  : result=m_vidregs[reg022]; break;
107      case    reg024  : result=m_vidregs[reg024]; break;
108      case    reg026  : result=m_vidregs[reg026]; break;
109      case    reg028  : result=m_screen->vpos() % 0xb; break; //result=m_vidregs[reg028]; break;
110      case    reg02A  : result=m_vidregs[reg002]; break;
111      case    reg02C  : result=m_vidregs[reg00C]; break;
112      case    reg02E  : result=m_vidregs[reg02E]; break;
113      default         : result=0; break;
67      case 0x10:
68         result = m_yline;
69         break;
70      case 0x11:
71         result = m_op;
72         break;
73      case 0x12:
74         result = m_colours;
75         break;
76      case 0x13:
77         result = m_mode;
78         break;
79      case 0x14:
80         result = m_screen->vpos() % 0xb; // TODO: verify
81         break;
82      case 0x15:
83         result = m_x;
84         break;
85      case 0x16:
86         result = m_y;
87         break;
88      default:
89         logerror("nimbus: unknown video reg read %02x\n", offset);
90         break;
11491   }
11592
11693   if(DEBUG_SET(DEBUG_TEXT))
117      logerror("Nimbus video IOR at %05X from %04X mask=%04X, data=%04X\n",pc,(offset*2),mem_mask,result);
94      logerror("Nimbus video IOR at %05X from %04X mask=%04X, data=%04X\n",space.device().safe_pc(),(offset*2),mem_mask,result);
11895
11996   return result;
12097}
r31223r31224
160137   UINT16  result=0;
161138
162139   if(DEBUG_SET(DEBUG_TEXT | DEBUG_PIXEL))
163      logerror("read_pixel_data(x=%d, y=%d), reg022=%04X\n",x,y,m_vidregs[reg022]);
140      logerror("read_pixel_data(x=%d, y=%d), reg022=%04X\n",x,y,m_op);
164141
165142   if(IS_80COL)
166143   {
167      switch (m_vidregs[reg022] & WIDTH_MASK)
144      switch (m_op & WIDTH_MASK)
168145      {
169146         case 0x00   : break;
170147
r31223r31224
189166   }
190167   else /* 40 Col */
191168   {
192      switch (m_vidregs[reg022] & WIDTH_MASK)
169      switch (m_op & WIDTH_MASK)
193170      {
194171         case 0x00   : break;
195172
r31223r31224
215192}
216193
217194/*
218    Write to the video registers, the default action is to write to the array of registers.
219    If a register also needs some special action call the action function for that register.
195    Write to the video registers.
220196
221197    Incase anyone wonders about the DEBUG_DB statement, this allows me to log which registers
222198    are being written to and then play them back at the real machine, this has helped greatly
r31223r31224
226202
227203WRITE16_MEMBER(rmnimbus_state::nimbus_video_io_w)
228204{
229   int pc=space.device().safe_pc();
230
231   if(offset<reg028)
205   UINT16 colours = data;
206   if(offset < 0x14)
232207   {
233208      if(DEBUG_SET(DEBUG_TEXT))
234         logerror("Nimbus video IOW at %05X write of %04X to %04X mask=%04X\n",pc,data,(offset*2),mem_mask);
209         logerror("Nimbus video IOW at %05X write of %04X to %04X mask=%04X\n",space.device().safe_pc(),data,(offset*2),mem_mask);
235210
236211      if(DEBUG_SET(DEBUG_DB))
237212         logerror("dw %05X,%05X\n",(offset*2),data);
r31223r31224
239214
240215   switch (offset)
241216   {
242      case    reg000  : m_vidregs[reg000]=data; break;
243      case    reg002  : m_vidregs[reg002]=data; break;
244      case    reg004  : m_vidregs[reg004]=data; write_reg_004(); break;
245      case    reg006  : m_vidregs[reg006]=data; write_reg_006(); break;
246      case    reg008  : m_vidregs[reg008]=data; break;
247      case    reg00A  : m_vidregs[reg00A]=data; write_reg_00A(); break;
248      case    reg00C  : m_vidregs[reg00C]=data; break;
249      case    reg00E  : m_vidregs[reg00E]=data; write_reg_00E(); break;
217      case 0x00:
218      case 0x08:
219         break;
250220
251      case    reg010  : m_vidregs[reg010]=data; write_reg_010(); break;
252      case    reg012  : m_vidregs[reg012]=data; write_reg_012(); break;
253      case    reg014  : m_vidregs[reg014]=data; write_reg_014(); break;
254      case    reg016  : m_vidregs[reg016]=data; write_reg_016(); break;
255      case    reg018  : m_vidregs[reg018]=data; break;
256      case    reg01A  : m_vidregs[reg01A]=data; write_reg_01A(); break;
257      case    reg01C  : m_vidregs[reg01C]=data; write_reg_01C();break;
258      case    reg01E  : m_vidregs[reg01E]=data; write_reg_01E();break;
221      case 0x09:
222         colours = FILL_WORD(FG_COLOUR);
223      case 0x01:
224         m_x = data;
225         break;
259226
260      case    reg020  : m_vidregs[reg020]=data; break;
261      case    reg022  : m_vidregs[reg022]=data; break;
262      case    reg024  : m_vidregs[reg024]=data; break;
263      case    reg026  : m_vidregs[reg026]=data; write_reg_026(); break;
264      case    reg028  : change_palette(0,data); break;
265      case    reg02A  : change_palette(1,data); break;
266      case    reg02C  : change_palette(2,data); break;
267      case    reg02E  : change_palette(3,data); break;
227      case 0x02:
228      case 0x0A:
229         m_y++;
230         break;
268231
269      default         : break;
232      case 0x0B:
233         colours = FILL_WORD(FG_COLOUR);
234      case 0x03:
235         m_x = data;
236         m_y++;
237         break;
238
239      case 0x05:
240      case 0x0D:
241         m_x++;
242         break;
243
244      case 0x0E:
245         colours = FILL_WORD(FG_COLOUR);
246      case 0x06:
247         m_y = data;
248         break;
249
250      case 0x0F:
251         colours = FILL_WORD(FG_COLOUR);
252      case 0x07:
253         m_y = data;
254         m_x++;
255         break;
256
257      case 0x10:
258         m_yline = data;
259         return;
260      case 0x11:
261         m_op = data;
262         return;
263      case 0x12:
264         m_colours = data;
265         return;
266      case 0x13:
267         /*
268             bits 0..3 of reg026 contain the border colour.
269             bit 5 contains the 40/80 column (320/640 pixel) flag.
270         */
271         m_mode = data;
272         return;
273      case 0x14:
274      case 0x15:
275      case 0x16:
276      case 0x17:
277         change_palette(offset - 0x14, data);
278         return;
279
280      default:
281         logerror("nimbus: unknown video reg write %02x %04x\n", offset, data);
282         return;
270283   }
284   if(offset & 0x08)
285      write_pixel_data(m_x, m_y, colours);
271286}
272287
273288void rmnimbus_state::set_pixel(UINT16 x, UINT16 y, UINT8 colour)
r31223r31224
327342   {
328343      if(DEBUG_SET(DEBUG_TEXT | DEBUG_PIXEL))
329344         logerror("x=%d\n",x + i);
330      m_video_mem.pix16(m_vidregs[reg020], x + i) = m_video_mem.pix16(y, x + i);
345      m_video_mem.pix16(m_yline, x + i) = m_video_mem.pix16(y, x + i);
331346   }
332347}
333348
r31223r31224
361376void rmnimbus_state::write_pixel_data(UINT16 x, UINT16 y, UINT16    data)
362377{
363378   if(DEBUG_SET(DEBUG_TEXT | DEBUG_PIXEL))
364      logerror("write_pixel_data(x=%d, y=%d, data=%04X), reg022=%04X\n",x,y,data,m_vidregs[reg022]);
379      logerror("write_pixel_data(x=%d, y=%d, data=%04X), reg022=%04X\n",x,y,data,m_op);
365380
366381   if(IS_80COL)
367382   {
368      switch (m_vidregs[reg022] & WIDTH_MASK)
383      switch (m_op & WIDTH_MASK)
369384      {
370385         case 0x00:
371386            write_pixel_line(x,y,data,16,1);
r31223r31224
402417   }
403418   else /* 40 Col */
404419   {
405      switch (m_vidregs[reg022] & WIDTH_MASK)
420      switch (m_op & WIDTH_MASK)
406421      {
407422         case 0x00:
408423            write_pixel_line(x,y,data,8,1);
r31223r31224
439454   }
440455}
441456
442void rmnimbus_state::write_reg_004()
443{
444   //m_vidregs[reg002]=0;
445   m_vidregs[reg00C]++;
446}
447
448void rmnimbus_state::write_reg_006()
449{
450   m_vidregs[reg00C]++;
451   m_vidregs[reg002]=m_vidregs[reg006];
452}
453
454void rmnimbus_state::write_reg_00A()
455{
456   m_vidregs[reg002]++;
457}
458
459void rmnimbus_state::write_reg_00E()
460{
461   m_vidregs[reg002]++;
462   m_vidregs[reg00C]=m_vidregs[reg00E];
463}
464
465void rmnimbus_state::write_reg_010()
466{
467   write_pixel_data(m_vidregs[reg002],m_vidregs[reg00C],m_vidregs[reg010]);
468}
469
470void rmnimbus_state::write_reg_012()
471{
472   // I dunno if this is actually what is happening as the regs seem to be write only....
473   // doing this however does seem to make some programs (worms from the welcom disk)
474   // work correctly.
475   m_vidregs[reg002]=m_vidregs[reg012];
476
477   write_pixel_data(m_vidregs[reg012],m_vidregs[reg00C],FILL_WORD(FG_COLOUR));
478}
479
480void rmnimbus_state::write_reg_014()
481{
482   write_pixel_data(m_vidregs[reg002],++m_vidregs[reg00C],m_vidregs[reg014]);
483}
484
485void rmnimbus_state::write_reg_016()
486{
487   m_vidregs[reg002]=m_vidregs[reg016];
488
489   write_pixel_data(m_vidregs[reg002],++m_vidregs[reg00C],FILL_WORD(FG_COLOUR));
490}
491
492
493void rmnimbus_state::write_reg_01A()
494{
495   write_pixel_data(++m_vidregs[reg002],m_vidregs[reg00C],m_vidregs[reg01A]);
496}
497
498void rmnimbus_state::write_reg_01C()
499{
500   // I dunno if this is actually what is happening as the regs seem to be write only....
501   // doing this however does seem to make some programs (welcome from the welcom disk,
502   // and others using the standard RM box menus) work correctly.
503   m_vidregs[reg00C]=m_vidregs[reg01C];
504
505   write_pixel_data(m_vidregs[reg002],m_vidregs[reg01C],FILL_WORD(FG_COLOUR));
506}
507
508void rmnimbus_state::write_reg_01E()
509{
510   m_vidregs[reg00C]=m_vidregs[reg01E];
511
512   write_pixel_data(++m_vidregs[reg002],m_vidregs[reg00C],FILL_WORD(FG_COLOUR));
513}
514
515/*
516    bits 0..3 of reg026 contain the border colour.
517    bit 5 contains the 40/80 column (320/640 pixel) flag.
518*/
519
520void rmnimbus_state::write_reg_026()
521{
522   if(DEBUG_SET(DEBUG_TEXT))
523      logerror("reg 026 write, border_colour=%02X\n",m_vidregs[reg026] & 0x0F);
524}
525
526457void rmnimbus_state::change_palette(UINT8 bank, UINT16 colours)
527458{
528459   // loop over changing colours
r31223r31224
532463      m_palette->set_pen_color(colourno, pal2bit((colours & 2) | i), pal2bit(((colours & 4) >> 1) | i), pal2bit(((colours & 1) << 1) | i));
533464
534465      if(DEBUG_SET(DEBUG_TEXT))
535         logerror("set colourno[%02X], colour=%02X\n",colourno, colours);
466         logerror("set colourno[%02X], colour=%02X\n",colourno, colours & 0xf);
536467      colours >>= 4;
537468   }
538469}
r31223r31224
557488
558489   m_screen->register_screen_bitmap(m_video_mem);
559490
560   save_item(NAME(m_vidregs));
561
562491   if (machine().debug_flags & DEBUG_FLAG_ENABLED)
563492   {
564493      debug_console_register_command(machine(), "nimbus_vid_debug", CMDFLAG_NONE, 0, 0, 1, video_debug);
r31223r31224
567496
568497void rmnimbus_state::video_reset()
569498{
570   // When we reset clear the video registers and video memory.
571   memset(&m_vidregs,0x00,sizeof(m_vidregs));
499   m_mode = 0;
500   m_x = 0;
501   m_y = 0;
502   m_op = 0;
503   m_yline = 0;
572504}
573505
574506UINT32 rmnimbus_state::screen_update_nimbus(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)

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