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r31222 Monday 7th July, 2014 at 20:02:49 UTC by Wilbert Pol
sh4: Modernized cpu core (nw)

[src/emu/cpu/sh4]	sh3comn.c sh4.c sh4.h sh4comn.c sh4comn.h sh4dmac.c sh4dmac.h sh4tmu.c sh4tmu.h
[src/mame/drivers]	aristmk6.c atvtrack.c cv1k.c naomi.c
[src/mame/includes]	dc.h
[src/mame/machine]	dc.c maple-dc.c
[src/mess/drivers]	dccons.c sh4robot.c
[src/mess/machine]	dccons.c

trunk/src/emu/cpu/sh4/sh4dmac.h

r31221	r31222
27	27
28	28	TIMER_CALLBACK( sh4_dmac_callback );
29	29
30		void sh4_handle_sar0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
31		void sh4_handle_sar1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
32		void sh4_handle_sar2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
33		void sh4_handle_sar3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
34		void sh4_handle_dar0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
35		void sh4_handle_dar1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
36		void sh4_handle_dar2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
37		void sh4_handle_dar3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
38		void sh4_handle_dmatcr0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
39		void sh4_handle_dmatcr1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
40		void sh4_handle_dmatcr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
41		void sh4_handle_dmatcr3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
42		void sh4_handle_chcr0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
43		void sh4_handle_chcr1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
44		void sh4_handle_chcr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
45		void sh4_handle_chcr3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
46		void sh4_handle_dmaor_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
47		UINT32 sh4_handle_sar0_addr_r(sh4_state *sh4, UINT32 mem_mask);
48		UINT32 sh4_handle_sar1_addr_r(sh4_state *sh4, UINT32 mem_mask);
49		UINT32 sh4_handle_sar2_addr_r(sh4_state *sh4, UINT32 mem_mask);
50		UINT32 sh4_handle_sar3_addr_r(sh4_state *sh4, UINT32 mem_mask);
51		UINT32 sh4_handle_dar0_addr_r(sh4_state *sh4, UINT32 mem_mask);
52		UINT32 sh4_handle_dar1_addr_r(sh4_state *sh4, UINT32 mem_mask);
53		UINT32 sh4_handle_dar2_addr_r(sh4_state *sh4, UINT32 mem_mask);
54		UINT32 sh4_handle_dar3_addr_r(sh4_state *sh4, UINT32 mem_mask);
55		UINT32 sh4_handle_dmatcr0_addr_r(sh4_state *sh4, UINT32 mem_mask);
56		UINT32 sh4_handle_dmatcr1_addr_r(sh4_state *sh4, UINT32 mem_mask);
57		UINT32 sh4_handle_dmatcr2_addr_r(sh4_state *sh4, UINT32 mem_mask);
58		UINT32 sh4_handle_dmatcr3_addr_r(sh4_state *sh4, UINT32 mem_mask);
59		UINT32 sh4_handle_chcr0_addr_r(sh4_state *sh4, UINT32 mem_mask);
60		UINT32 sh4_handle_chcr1_addr_r(sh4_state *sh4, UINT32 mem_mask);
61		UINT32 sh4_handle_chcr2_addr_r(sh4_state *sh4, UINT32 mem_mask);
62		UINT32 sh4_handle_chcr3_addr_r(sh4_state *sh4, UINT32 mem_mask);
63		UINT32 sh4_handle_dmaor_addr_r(sh4_state *sh4, UINT32 mem_mask);
	30	void sh4_handle_sar0_addr_w(UINT32 data, UINT32 mem_mask);
	31	void sh4_handle_sar1_addr_w(UINT32 data, UINT32 mem_mask);
	32	void sh4_handle_sar2_addr_w(UINT32 data, UINT32 mem_mask);
	33	void sh4_handle_sar3_addr_w(UINT32 data, UINT32 mem_mask);
	34	void sh4_handle_dar0_addr_w(UINT32 data, UINT32 mem_mask);
	35	void sh4_handle_dar1_addr_w(UINT32 data, UINT32 mem_mask);
	36	void sh4_handle_dar2_addr_w(UINT32 data, UINT32 mem_mask);
	37	void sh4_handle_dar3_addr_w(UINT32 data, UINT32 mem_mask);
	38	void sh4_handle_dmatcr0_addr_w(UINT32 data, UINT32 mem_mask);
	39	void sh4_handle_dmatcr1_addr_w(UINT32 data, UINT32 mem_mask);
	40	void sh4_handle_dmatcr2_addr_w(UINT32 data, UINT32 mem_mask);
	41	void sh4_handle_dmatcr3_addr_w(UINT32 data, UINT32 mem_mask);
	42	void sh4_handle_chcr0_addr_w(UINT32 data, UINT32 mem_mask);
	43	void sh4_handle_chcr1_addr_w(UINT32 data, UINT32 mem_mask);
	44	void sh4_handle_chcr2_addr_w(UINT32 data, UINT32 mem_mask);
	45	void sh4_handle_chcr3_addr_w(UINT32 data, UINT32 mem_mask);
	46	void sh4_handle_dmaor_addr_w(UINT32 data, UINT32 mem_mask);
	47	UINT32 sh4_handle_sar0_addr_r(UINT32 mem_mask);
	48	UINT32 sh4_handle_sar1_addr_r(UINT32 mem_mask);
	49	UINT32 sh4_handle_sar2_addr_r(UINT32 mem_mask);
	50	UINT32 sh4_handle_sar3_addr_r(UINT32 mem_mask);
	51	UINT32 sh4_handle_dar0_addr_r(UINT32 mem_mask);
	52	UINT32 sh4_handle_dar1_addr_r(UINT32 mem_mask);
	53	UINT32 sh4_handle_dar2_addr_r(UINT32 mem_mask);
	54	UINT32 sh4_handle_dar3_addr_r(UINT32 mem_mask);
	55	UINT32 sh4_handle_dmatcr0_addr_r(UINT32 mem_mask);
	56	UINT32 sh4_handle_dmatcr1_addr_r(UINT32 mem_mask);
	57	UINT32 sh4_handle_dmatcr2_addr_r(UINT32 mem_mask);
	58	UINT32 sh4_handle_dmatcr3_addr_r(UINT32 mem_mask);
	59	UINT32 sh4_handle_chcr0_addr_r(UINT32 mem_mask);
	60	UINT32 sh4_handle_chcr1_addr_r(UINT32 mem_mask);
	61	UINT32 sh4_handle_chcr2_addr_r(UINT32 mem_mask);
	62	UINT32 sh4_handle_chcr3_addr_r(UINT32 mem_mask);
	63	UINT32 sh4_handle_dmaor_addr_r(UINT32 mem_mask);

trunk/src/emu/cpu/sh4/sh4tmu.h

r31221	r31222
1	1	/* SH3/4 Timer Unit */
2
3		TIMER_CALLBACK( sh4_timer_callback );
4
5		UINT32 sh4_handle_tcnt0_addr_r(sh4_state *sh4, UINT32 mem_mask);
6		UINT32 sh4_handle_tcnt1_addr_r(sh4_state *sh4, UINT32 mem_mask);
7		UINT32 sh4_handle_tcnt2_addr_r(sh4_state *sh4, UINT32 mem_mask);
8		UINT32 sh4_handle_tcor0_addr_r(sh4_state *sh4, UINT32 mem_mask);
9		UINT32 sh4_handle_tcor1_addr_r(sh4_state *sh4, UINT32 mem_mask);
10		UINT32 sh4_handle_tcor2_addr_r(sh4_state *sh4, UINT32 mem_mask);
11		UINT32 sh4_handle_tcr0_addr_r(sh4_state *sh4, UINT32 mem_mask);
12		UINT32 sh4_handle_tcr1_addr_r(sh4_state *sh4, UINT32 mem_mask);
13		UINT32 sh4_handle_tcr2_addr_r(sh4_state *sh4, UINT32 mem_mask);
14		UINT32 sh4_handle_tstr_addr_r(sh4_state *sh4, UINT32 mem_mask);
15		UINT32 sh4_handle_tocr_addr_r(sh4_state *sh4, UINT32 mem_mask);
16		UINT32 sh4_handle_tcpr2_addr_r(sh4_state *sh4, UINT32 mem_mask);
17
18		void sh4_handle_tstr_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
19		void sh4_handle_tcr0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
20		void sh4_handle_tcr1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
21		void sh4_handle_tcr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
22		void sh4_handle_tcor0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
23		void sh4_handle_tcor1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
24		void sh4_handle_tcor2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
25		void sh4_handle_tcnt0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
26		void sh4_handle_tcnt1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
27		void sh4_handle_tcnt2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
28		void sh4_handle_tocr_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
29		void sh4_handle_tcpr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);

trunk/src/emu/cpu/sh4/sh3comn.c

r31221	r31222
10	10
11	11	/* High internal area (ffffxxxx) */
12	12
13		WRITE32_MEMBER( sh3_device::sh3_internal_high_w )
	13	WRITE32_MEMBER( sh3_base_device::sh3_internal_high_w )
14	14	{
15		sh4_state *sh4 = get_safe_token(this);
16		COMBINE_DATA(&sh4->m_sh3internal_upper[offset]);
	15	COMBINE_DATA(&m_sh3internal_upper[offset]);
17	16
18	17	switch (offset)
19	18	{
20	19	case SH3_ICR0_IPRA_ADDR:
21	20	if (mem_mask & 0xffff0000)
22	21	{
23		logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - ICR0)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask);
	22	logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - ICR0)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask);
24	23	}
25	24
26	25	if (mem_mask & 0x0000ffff)
27	26	{
28		logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - IPRA)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask);
29		sh4_handler_ipra_w(sh4,data&0xffff,mem_mask&0xffff);
	27	logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - IPRA)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask);
	28	sh4_handler_ipra_w(data&0xffff,mem_mask&0xffff);
30	29	}
31	30
32	31	break;
33	32
34	33	case SH3_IPRB_ADDR:
35		logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_IPRB_ADDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask);
	34	logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_IPRB_ADDR)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask);
36	35	break;
37	36
38	37	case SH3_TOCR_TSTR_ADDR:
39		logerror("'%s' (%08x): TMU internal write to %08x = %08x & %08x (SH3_TOCR_TSTR_ADDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask);
	38	logerror("'%s' (%08x): TMU internal write to %08x = %08x & %08x (SH3_TOCR_TSTR_ADDR)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask);
40	39	if (mem_mask&0xff000000)
41	40	{
42		sh4_handle_tocr_addr_w(sh4, (data>>24)&0xffff, (mem_mask>>24)&0xff);
	41	sh4_handle_tocr_addr_w((data>>24)&0xffff, (mem_mask>>24)&0xff);
43	42	}
44	43	if (mem_mask&0x0000ff00)
45	44	{
46		sh4_handle_tstr_addr_w(sh4, (data>>8)&0xff, (mem_mask>>8)&0xff);
	45	sh4_handle_tstr_addr_w((data>>8)&0xff, (mem_mask>>8)&0xff);
47	46	}
48	47	if (mem_mask&0x00ff00ff)
49	48	{
50	49	fatalerror("SH3_TOCR_TSTR_ADDR unused bits accessed (write)\n");
51	50	}
52	51	break;
53		case SH3_TCOR0_ADDR:  sh4_handle_tcor0_addr_w(sh4, data, mem_mask);break;
54		case SH3_TCOR1_ADDR:  sh4_handle_tcor1_addr_w(sh4, data, mem_mask);break;
55		case SH3_TCOR2_ADDR:  sh4_handle_tcor2_addr_w(sh4, data, mem_mask);break;
56		case SH3_TCNT0_ADDR:  sh4_handle_tcnt0_addr_w(sh4, data, mem_mask);break;
57		case SH3_TCNT1_ADDR:  sh4_handle_tcnt1_addr_w(sh4, data, mem_mask);break;
58		case SH3_TCNT2_ADDR:  sh4_handle_tcnt2_addr_w(sh4, data, mem_mask);break;
59		case SH3_TCR0_ADDR:   sh4_handle_tcr0_addr_w(sh4, data>>16, mem_mask>>16);break;
60		case SH3_TCR1_ADDR:   sh4_handle_tcr1_addr_w(sh4, data>>16, mem_mask>>16);break;
61		case SH3_TCR2_ADDR:   sh4_handle_tcr2_addr_w(sh4, data>>16, mem_mask>>16);break;
62		case SH3_TCPR2_ADDR:  sh4_handle_tcpr2_addr_w(sh4,data,  mem_mask);break;
	52	case SH3_TCOR0_ADDR:  sh4_handle_tcor0_addr_w(data, mem_mask);break;
	53	case SH3_TCOR1_ADDR:  sh4_handle_tcor1_addr_w(data, mem_mask);break;
	54	case SH3_TCOR2_ADDR:  sh4_handle_tcor2_addr_w(data, mem_mask);break;
	55	case SH3_TCNT0_ADDR:  sh4_handle_tcnt0_addr_w(data, mem_mask);break;
	56	case SH3_TCNT1_ADDR:  sh4_handle_tcnt1_addr_w(data, mem_mask);break;
	57	case SH3_TCNT2_ADDR:  sh4_handle_tcnt2_addr_w(data, mem_mask);break;
	58	case SH3_TCR0_ADDR:   sh4_handle_tcr0_addr_w(data>>16, mem_mask>>16);break;
	59	case SH3_TCR1_ADDR:   sh4_handle_tcr1_addr_w(data>>16, mem_mask>>16);break;
	60	case SH3_TCR2_ADDR:   sh4_handle_tcr2_addr_w(data>>16, mem_mask>>16);break;
	61	case SH3_TCPR2_ADDR:  sh4_handle_tcpr2_addr_w(data,  mem_mask);break;
63	62
64	63	default:
65		logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (unk)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask);
	64	logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (unk)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask);
66	65	break;
67	66
68	67	}
r31221	r31222
72	71
73	72	}
74	73
75		READ32_MEMBER( sh3_device::sh3_internal_high_r )
	74	READ32_MEMBER( sh3_base_device::sh3_internal_high_r )
76	75	{
77		sh4_state *sh4 = get_safe_token(this);
78
79	76	UINT32 ret = 0;
80	77
81	78	switch (offset)
82	79	{
83	80	case SH3_ICR0_IPRA_ADDR:
84		logerror("'%s' (%08x): INTC internal read from %08x mask %08x (SH3_ICR0_IPRA_ADDR - %08x)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, sh4->m_sh3internal_upper[offset]);
85		return (sh4->m_sh3internal_upper[offset] & 0xffff0000) | (sh4->SH4_IPRA & 0xffff);
	81	logerror("'%s' (%08x): INTC internal read from %08x mask %08x (SH3_ICR0_IPRA_ADDR - %08x)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]);
	82	return (m_sh3internal_upper[offset] & 0xffff0000) | (m_SH4_IPRA & 0xffff);
86	83
87	84	case SH3_IPRB_ADDR:
88		logerror("'%s' (%08x): INTC internal read from %08x mask %08x (SH3_IPRB_ADDR - %08x)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, sh4->m_sh3internal_upper[offset]);
89		return sh4->m_sh3internal_upper[offset];
	85	logerror("'%s' (%08x): INTC internal read from %08x mask %08x (SH3_IPRB_ADDR - %08x)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]);
	86	return m_sh3internal_upper[offset];
90	87
91	88	case SH3_TOCR_TSTR_ADDR:
92	89
93	90	if (mem_mask&0xff00000)
94	91	{
95		ret |= (sh4_handle_tocr_addr_r(sh4, mem_mask)&0xff)<<24;
	92	ret |= (sh4_handle_tocr_addr_r(mem_mask)&0xff)<<24;
96	93	}
97	94	if (mem_mask&0x0000ff00)
98	95	{
99		ret |= (sh4_handle_tstr_addr_r(sh4, mem_mask)&0xff)<<8;
	96	ret |= (sh4_handle_tstr_addr_r(mem_mask)&0xff)<<8;
100	97	}
101	98	if (mem_mask&0x00ff00ff)
102	99	{
103	100	fatalerror("SH3_TOCR_TSTR_ADDR unused bits accessed (read)\n");
104	101	}
105	102	return ret;
106		case SH3_TCOR0_ADDR:  return sh4_handle_tcor0_addr_r(sh4, mem_mask);
107		case SH3_TCOR1_ADDR:  return sh4_handle_tcor1_addr_r(sh4, mem_mask);
108		case SH3_TCOR2_ADDR:  return sh4_handle_tcor2_addr_r(sh4, mem_mask);
109		case SH3_TCNT0_ADDR:  return sh4_handle_tcnt0_addr_r(sh4, mem_mask);
110		case SH3_TCNT1_ADDR:  return sh4_handle_tcnt1_addr_r(sh4, mem_mask);
111		case SH3_TCNT2_ADDR:  return sh4_handle_tcnt2_addr_r(sh4, mem_mask);
112		case SH3_TCR0_ADDR:   return sh4_handle_tcr0_addr_r(sh4, mem_mask)<<16;
113		case SH3_TCR1_ADDR:   return sh4_handle_tcr1_addr_r(sh4, mem_mask)<<16;
114		case SH3_TCR2_ADDR:   return sh4_handle_tcr2_addr_r(sh4, mem_mask)<<16;
115		case SH3_TCPR2_ADDR:  return sh4_handle_tcpr2_addr_r(sh4, mem_mask);
	103	case SH3_TCOR0_ADDR:  return sh4_handle_tcor0_addr_r(mem_mask);
	104	case SH3_TCOR1_ADDR:  return sh4_handle_tcor1_addr_r(mem_mask);
	105	case SH3_TCOR2_ADDR:  return sh4_handle_tcor2_addr_r(mem_mask);
	106	case SH3_TCNT0_ADDR:  return sh4_handle_tcnt0_addr_r(mem_mask);
	107	case SH3_TCNT1_ADDR:  return sh4_handle_tcnt1_addr_r(mem_mask);
	108	case SH3_TCNT2_ADDR:  return sh4_handle_tcnt2_addr_r(mem_mask);
	109	case SH3_TCR0_ADDR:   return sh4_handle_tcr0_addr_r(mem_mask)<<16;
	110	case SH3_TCR1_ADDR:   return sh4_handle_tcr1_addr_r(mem_mask)<<16;
	111	case SH3_TCR2_ADDR:   return sh4_handle_tcr2_addr_r(mem_mask)<<16;
	112	case SH3_TCPR2_ADDR:  return sh4_handle_tcpr2_addr_r(mem_mask);
116	113
117	114
118	115	case SH3_TRA_ADDR:
119		logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 TRA - %08x)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, sh4->m_sh3internal_upper[offset]);
120		return sh4->m_sh3internal_upper[offset];
	116	logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 TRA - %08x)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]);
	117	return m_sh3internal_upper[offset];
121	118
122	119	case SH3_EXPEVT_ADDR:
123		logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 EXPEVT - %08x)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, sh4->m_sh3internal_upper[offset]);
124		return sh4->m_sh3internal_upper[offset];
	120	logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 EXPEVT - %08x)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]);
	121	return m_sh3internal_upper[offset];
125	122
126	123	case SH3_INTEVT_ADDR:
127		logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 INTEVT - %08x)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, sh4->m_sh3internal_upper[offset]);
	124	logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 INTEVT - %08x)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]);
128	125	fatalerror("INTEVT unsupported on SH3\n");
129		return sh4->m_sh3internal_upper[offset];
	126	return m_sh3internal_upper[offset];
130	127
131	128
132	129	default:
133		logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask);
134		return sh4->m_sh3internal_upper[offset];
	130	logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask);
	131	return m_sh3internal_upper[offset];
135	132	}
136	133	}
137	134
138	135
139		READ32_MEMBER( sh3_device::sh3_internal_r )
	136	READ32_MEMBER( sh3_base_device::sh3_internal_r )
140	137	{
141		sh4_state *sh4 = get_safe_token(this);
142
143	138	if (offset<0x1000)
144	139	{
145	140	switch (offset)
146	141	{
147		case SH3_SAR0_ADDR: return sh4_handle_sar0_addr_r(sh4,mem_mask);
148		case SH3_SAR1_ADDR: return sh4_handle_sar1_addr_r(sh4,mem_mask);
149		case SH3_SAR2_ADDR: return sh4_handle_sar2_addr_r(sh4,mem_mask);
150		case SH3_SAR3_ADDR: return sh4_handle_sar3_addr_r(sh4,mem_mask);
151		case SH3_DAR0_ADDR: return sh4_handle_dar0_addr_r(sh4,mem_mask);
152		case SH3_DAR1_ADDR: return sh4_handle_dar1_addr_r(sh4,mem_mask);
153		case SH3_DAR2_ADDR: return sh4_handle_dar2_addr_r(sh4,mem_mask);
154		case SH3_DAR3_ADDR: return sh4_handle_dar3_addr_r(sh4,mem_mask);
155		case SH3_DMATCR0_ADDR: return sh4_handle_dmatcr0_addr_r(sh4,mem_mask);
156		case SH3_DMATCR1_ADDR: return sh4_handle_dmatcr1_addr_r(sh4,mem_mask);
157		case SH3_DMATCR2_ADDR: return sh4_handle_dmatcr2_addr_r(sh4,mem_mask);
158		case SH3_DMATCR3_ADDR: return sh4_handle_dmatcr3_addr_r(sh4,mem_mask);
159		case SH3_CHCR0_ADDR: return sh4_handle_chcr0_addr_r(sh4,mem_mask);
160		case SH3_CHCR1_ADDR: return sh4_handle_chcr1_addr_r(sh4,mem_mask);
161		case SH3_CHCR2_ADDR: return sh4_handle_chcr2_addr_r(sh4,mem_mask);
162		case SH3_CHCR3_ADDR: return sh4_handle_chcr3_addr_r(sh4,mem_mask);
163		case SH3_DMAOR_ADDR: return sh4_handle_dmaor_addr_r(sh4,mem_mask)<<16;
	142	case SH3_SAR0_ADDR: return sh4_handle_sar0_addr_r(mem_mask);
	143	case SH3_SAR1_ADDR: return sh4_handle_sar1_addr_r(mem_mask);
	144	case SH3_SAR2_ADDR: return sh4_handle_sar2_addr_r(mem_mask);
	145	case SH3_SAR3_ADDR: return sh4_handle_sar3_addr_r(mem_mask);
	146	case SH3_DAR0_ADDR: return sh4_handle_dar0_addr_r(mem_mask);
	147	case SH3_DAR1_ADDR: return sh4_handle_dar1_addr_r(mem_mask);
	148	case SH3_DAR2_ADDR: return sh4_handle_dar2_addr_r(mem_mask);
	149	case SH3_DAR3_ADDR: return sh4_handle_dar3_addr_r(mem_mask);
	150	case SH3_DMATCR0_ADDR: return sh4_handle_dmatcr0_addr_r(mem_mask);
	151	case SH3_DMATCR1_ADDR: return sh4_handle_dmatcr1_addr_r(mem_mask);
	152	case SH3_DMATCR2_ADDR: return sh4_handle_dmatcr2_addr_r(mem_mask);
	153	case SH3_DMATCR3_ADDR: return sh4_handle_dmatcr3_addr_r(mem_mask);
	154	case SH3_CHCR0_ADDR: return sh4_handle_chcr0_addr_r(mem_mask);
	155	case SH3_CHCR1_ADDR: return sh4_handle_chcr1_addr_r(mem_mask);
	156	case SH3_CHCR2_ADDR: return sh4_handle_chcr2_addr_r(mem_mask);
	157	case SH3_CHCR3_ADDR: return sh4_handle_chcr3_addr_r(mem_mask);
	158	case SH3_DMAOR_ADDR: return sh4_handle_dmaor_addr_r(mem_mask)<<16;
164	159
165	160
166	161	case INTEVT2:
167	162	{
168		//  logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (INTEVT2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
169		return sh4->m_sh3internal_lower[offset];
	163	//  logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (INTEVT2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	164	return m_sh3internal_lower[offset];
170	165	}
171	166	break;
172	167
r31221	r31222
176	171	{
177	172	if (mem_mask & 0xff000000)
178	173	{
179		logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
180		return sh4->m_sh3internal_lower[offset];
	174	logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	175	return m_sh3internal_lower[offset];
181	176	}
182	177
183	178	if (mem_mask & 0x0000ff00)
184	179	{
185		logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR1)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
186		return sh4->m_sh3internal_lower[offset];
	180	logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR1)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	181	return m_sh3internal_lower[offset];
187	182	}
188	183
189		fatalerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0/1 unused bits)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
	184	fatalerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0/1 unused bits)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
190	185	}
191	186	}
192	187	break;
r31221	r31222
195	190	{
196	191	if (mem_mask & 0xffff0000)
197	192	{
198		//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PADR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
199		return sh4->io->read_qword(SH3_PORT_A)<<24;
	193	//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PADR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	194	return m_io->read_qword(SH3_PORT_A)<<24;
200	195	}
201	196
202	197	if (mem_mask & 0x0000ffff)
203	198	{
204		//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PBDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
205		return sh4->io->read_qword(SH3_PORT_B)<<8;
	199	//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PBDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	200	return m_io->read_qword(SH3_PORT_B)<<8;
206	201	}
207	202	}
208	203	break;
r31221	r31222
211	206	{
212	207	if (mem_mask & 0xffff0000)
213	208	{
214		//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PCDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
215		return sh4->io->read_qword(SH3_PORT_C)<<24;
	209	//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PCDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	210	return m_io->read_qword(SH3_PORT_C)<<24;
216	211	}
217	212
218	213	if (mem_mask & 0x0000ffff)
219	214	{
220		//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PDDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
221		return sh4->io->read_qword(SH3_PORT_D)<<8;
	215	//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PDDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	216	return m_io->read_qword(SH3_PORT_D)<<8;
222	217	}
223	218	}
224	219	break;
r31221	r31222
227	222	{
228	223	if (mem_mask & 0xffff0000)
229	224	{
230		//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PEDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
231		return sh4->io->read_qword(SH3_PORT_E)<<24;
	225	//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PEDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	226	return m_io->read_qword(SH3_PORT_E)<<24;
232	227	}
233	228
234	229	if (mem_mask & 0x0000ffff)
235	230	{
236		//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PFDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
237		return sh4->io->read_qword(SH3_PORT_F)<<8;
	231	//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PFDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	232	return m_io->read_qword(SH3_PORT_F)<<8;
238	233	}
239	234	}
240	235	break;
r31221	r31222
243	238	{
244	239	if (mem_mask & 0xffff0000)
245	240	{
246		//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PGDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
247		return sh4->io->read_qword(SH3_PORT_G)<<24;
	241	//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PGDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	242	return m_io->read_qword(SH3_PORT_G)<<24;
248	243	}
249	244
250	245	if (mem_mask & 0x0000ffff)
251	246	{
252		//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PHDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
253		return sh4->io->read_qword(SH3_PORT_H)<<8;
	247	//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PHDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	248	return m_io->read_qword(SH3_PORT_H)<<8;
254	249	}
255	250	}
256	251	break;
r31221	r31222
259	254	{
260	255	if (mem_mask & 0xffff0000)
261	256	{
262		//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PJDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
263		return sh4->io->read_qword(SH3_PORT_J)<<24;
	257	//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PJDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	258	return m_io->read_qword(SH3_PORT_J)<<24;
264	259	}
265	260
266	261	if (mem_mask & 0x0000ffff)
267	262	{
268		//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PKDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
269		return sh4->io->read_qword(SH3_PORT_K)<<8;
	263	//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PKDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	264	return m_io->read_qword(SH3_PORT_K)<<8;
270	265	}
271	266	}
272	267	break;
r31221	r31222
275	270	{
276	271	if (mem_mask & 0xffff0000)
277	272	{
278		//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PLDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
279		return sh4->io->read_qword(SH3_PORT_L)<<24;
	273	//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PLDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	274	return m_io->read_qword(SH3_PORT_L)<<24;
280	275	}
281	276
282	277	if (mem_mask & 0x0000ffff)
283	278	{
284		logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SCPDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
285		//return sh4->io->read_qword(SH3_PORT_K)<<8;
	279	logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SCPDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	280	//return m_io->read_qword(SH3_PORT_K)<<8;
286	281	}
287	282	}
288	283	break;
r31221	r31222
292	287	{
293	288	if (mem_mask & 0xff000000)
294	289	{
295		logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSMR2 - Serial Mode Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
296		return sh4->m_sh3internal_lower[offset];
	290	logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSMR2 - Serial Mode Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	291	return m_sh3internal_lower[offset];
297	292	}
298	293
299	294	if (mem_mask & 0x0000ff00)
300	295	{
301		logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCBRR2 - Bit Rate Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
302		return sh4->m_sh3internal_lower[offset];
	296	logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCBRR2 - Bit Rate Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	297	return m_sh3internal_lower[offset];
303	298	}
304	299	}
305	300	break;
r31221	r31222
308	303	{
309	304	if (mem_mask & 0xff000000)
310	305	{
311		logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSCR2 - Serial Control Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
312		return sh4->m_sh3internal_lower[offset];
	306	logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSCR2 - Serial Control Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	307	return m_sh3internal_lower[offset];
313	308	}
314	309
315	310	if (mem_mask & 0x0000ff00)
316	311	{
317		logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFTDR2 - Transmit FIFO Data Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
318		return sh4->m_sh3internal_lower[offset];
	312	logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFTDR2 - Transmit FIFO Data Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	313	return m_sh3internal_lower[offset];
319	314	}
320	315	}
321	316	break;
r31221	r31222
324	319	{
325	320	if (mem_mask & 0xffff0000)
326	321	{
327		logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSSR2 - Serial Status Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
328		return sh4->m_sh3internal_lower[offset];
	322	logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSSR2 - Serial Status Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	323	return m_sh3internal_lower[offset];
329	324	}
330	325
331	326	if (mem_mask & 0x0000ff00)
332	327	{
333		logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFRDR2 - Receive FIFO Data Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
334		return sh4->m_sh3internal_lower[offset];
	328	logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFRDR2 - Receive FIFO Data Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	329	return m_sh3internal_lower[offset];
335	330	}
336	331	}
337	332	break;
r31221	r31222
340	335	{
341	336	if (mem_mask & 0xff000000)
342	337	{
343		logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFCR2 - Fifo Control Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
344		return sh4->m_sh3internal_lower[offset];
	338	logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFCR2 - Fifo Control Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	339	return m_sh3internal_lower[offset];
345	340	}
346	341
347	342	if (mem_mask & 0x0000ffff)
348	343	{
349		logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFDR2 - Fifo Data Count Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask);
350		return sh4->m_sh3internal_lower[offset];
	344	logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFDR2 - Fifo Data Count Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
	345	return m_sh3internal_lower[offset];
351	346	}
352	347	}
353	348	break;
r31221	r31222
356	351	default:
357	352	{
358	353	logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n",
359		sh4->device->tag(), sh4->pc & AM,
	354	tag(), m_pc & AM,
360	355	(offset *4)+0x4000000,
361	356	mem_mask);
362	357	}
r31221	r31222
368	363	else
369	364	{
370	365	logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n",
371		sh4->device->tag(), sh4->pc & AM,
	366	tag(), m_pc & AM,
372	367	(offset *4)+0x4000000,
373	368	mem_mask);
374	369	}
r31221	r31222
378	373
379	374	/* Lower internal area */
380	375
381		WRITE32_MEMBER( sh3_device::sh3_internal_w )
	376	WRITE32_MEMBER( sh3_base_device::sh3_internal_w )
382	377	{
383		sh4_state *sh4 = get_safe_token(this);
384
385
386
387	378	if (offset<0x1000)
388	379	{
389		//UINT32 old = sh4->m_sh3internal_lower[offset];
390		COMBINE_DATA(&sh4->m_sh3internal_lower[offset]);
	380	//UINT32 old = m_sh3internal_lower[offset];
	381	COMBINE_DATA(&m_sh3internal_lower[offset]);
391	382
392	383	switch (offset)
393	384	{
394		case SH3_SAR0_ADDR: sh4_handle_sar0_addr_w(sh4,data,mem_mask);   break;
395		case SH3_SAR1_ADDR: sh4_handle_sar1_addr_w(sh4,data,mem_mask);   break;
396		case SH3_SAR2_ADDR: sh4_handle_sar2_addr_w(sh4,data,mem_mask);   break;
397		case SH3_SAR3_ADDR: sh4_handle_sar3_addr_w(sh4,data,mem_mask);   break;
398		case SH3_DAR0_ADDR: sh4_handle_dar0_addr_w(sh4,data,mem_mask);   break;
399		case SH3_DAR1_ADDR: sh4_handle_dar1_addr_w(sh4,data,mem_mask);   break;
400		case SH3_DAR2_ADDR: sh4_handle_dar2_addr_w(sh4,data,mem_mask);   break;
401		case SH3_DAR3_ADDR: sh4_handle_dar3_addr_w(sh4,data,mem_mask);   break;
402		case SH3_DMATCR0_ADDR: sh4_handle_dmatcr0_addr_w(sh4,data,mem_mask);   break;
403		case SH3_DMATCR1_ADDR: sh4_handle_dmatcr1_addr_w(sh4,data,mem_mask);   break;
404		case SH3_DMATCR2_ADDR: sh4_handle_dmatcr2_addr_w(sh4,data,mem_mask);   break;
405		case SH3_DMATCR3_ADDR: sh4_handle_dmatcr3_addr_w(sh4,data,mem_mask);   break;
406		case SH3_CHCR0_ADDR: sh4_handle_chcr0_addr_w(sh4,data,mem_mask);   break;
407		case SH3_CHCR1_ADDR: sh4_handle_chcr1_addr_w(sh4,data,mem_mask);   break;
408		case SH3_CHCR2_ADDR: sh4_handle_chcr2_addr_w(sh4,data,mem_mask);   break;
409		case SH3_CHCR3_ADDR: sh4_handle_chcr3_addr_w(sh4,data,mem_mask);   break;
410		case SH3_DMAOR_ADDR: sh4_handle_dmaor_addr_w(sh4,data>>16,mem_mask>>16);   break;
	385	case SH3_SAR0_ADDR: sh4_handle_sar0_addr_w(data,mem_mask);   break;
	386	case SH3_SAR1_ADDR: sh4_handle_sar1_addr_w(data,mem_mask);   break;
	387	case SH3_SAR2_ADDR: sh4_handle_sar2_addr_w(data,mem_mask);   break;
	388	case SH3_SAR3_ADDR: sh4_handle_sar3_addr_w(data,mem_mask);   break;
	389	case SH3_DAR0_ADDR: sh4_handle_dar0_addr_w(data,mem_mask);   break;
	390	case SH3_DAR1_ADDR: sh4_handle_dar1_addr_w(data,mem_mask);   break;
	391	case SH3_DAR2_ADDR: sh4_handle_dar2_addr_w(data,mem_mask);   break;
	392	case SH3_DAR3_ADDR: sh4_handle_dar3_addr_w(data,mem_mask);   break;
	393	case SH3_DMATCR0_ADDR: sh4_handle_dmatcr0_addr_w(data,mem_mask);   break;
	394	case SH3_DMATCR1_ADDR: sh4_handle_dmatcr1_addr_w(data,mem_mask);   break;
	395	case SH3_DMATCR2_ADDR: sh4_handle_dmatcr2_addr_w(data,mem_mask);   break;
	396	case SH3_DMATCR3_ADDR: sh4_handle_dmatcr3_addr_w(data,mem_mask);   break;
	397	case SH3_CHCR0_ADDR: sh4_handle_chcr0_addr_w(data,mem_mask);   break;
	398	case SH3_CHCR1_ADDR: sh4_handle_chcr1_addr_w(data,mem_mask);   break;
	399	case SH3_CHCR2_ADDR: sh4_handle_chcr2_addr_w(data,mem_mask);   break;
	400	case SH3_CHCR3_ADDR: sh4_handle_chcr3_addr_w(data,mem_mask);   break;
	401	case SH3_DMAOR_ADDR: sh4_handle_dmaor_addr_w(data>>16,mem_mask>>16);   break;
411	402
412	403
413	404	case IRR0_IRR1:
r31221	r31222
415	406	{
416	407	if (mem_mask & 0xff000000)
417	408	{
418		logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	409	logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
419	410	// not sure if this is how we should clear lines in this core...
420		if (!(data & 0x01000000)) sh4_set_irq_line(sh4, 0, CLEAR_LINE);
421		if (!(data & 0x02000000)) sh4_set_irq_line(sh4, 1, CLEAR_LINE);
422		if (!(data & 0x04000000)) sh4_set_irq_line(sh4, 2, CLEAR_LINE);
423		if (!(data & 0x08000000)) sh4_set_irq_line(sh4, 3, CLEAR_LINE);
	411	if (!(data & 0x01000000)) execute_set_input(0, CLEAR_LINE);
	412	if (!(data & 0x02000000)) execute_set_input(1, CLEAR_LINE);
	413	if (!(data & 0x04000000)) execute_set_input(2, CLEAR_LINE);
	414	if (!(data & 0x08000000)) execute_set_input(3, CLEAR_LINE);
424	415
425	416	}
426	417	if (mem_mask & 0x0000ff00)
427	418	{
428		logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR1)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	419	logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR1)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
429	420	}
430	421	if (mem_mask & 0x00ff00ff)
431	422	{
432		fatalerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0/1 unused bits)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	423	fatalerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0/1 unused bits)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
433	424	}
434	425	}
435	426	}
r31221	r31222
439	430	{
440	431	if (mem_mask & 0xffff0000)
441	432	{
442		logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PINTER)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	433	logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PINTER)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
443	434	}
444	435
445	436	if (mem_mask & 0x0000ffff)
446	437	{
447	438	data &= 0xffff; mem_mask &= 0xffff;
448		COMBINE_DATA(&sh4->SH4_IPRC);
449		logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (IPRC)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
450		sh4->exception_priority[SH4_INTC_IRL0]     = INTPRI((sh4->SH4_IPRC & 0x000f)>>0, SH4_INTC_IRL0);
451		sh4->exception_priority[SH4_INTC_IRL1]     = INTPRI((sh4->SH4_IPRC & 0x00f0)>>4, SH4_INTC_IRL1);
452		sh4->exception_priority[SH4_INTC_IRL2]     = INTPRI((sh4->SH4_IPRC & 0x0f00)>>8, SH4_INTC_IRL2);
453		sh4->exception_priority[SH4_INTC_IRL3]     = INTPRI((sh4->SH4_IPRC & 0xf000)>>12,SH4_INTC_IRL3);
454		sh4_exception_recompute(sh4);
	439	COMBINE_DATA(&m_SH4_IPRC);
	440	logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (IPRC)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
	441	m_exception_priority[SH4_INTC_IRL0]     = INTPRI((m_SH4_IPRC & 0x000f)>>0, SH4_INTC_IRL0);
	442	m_exception_priority[SH4_INTC_IRL1]     = INTPRI((m_SH4_IPRC & 0x00f0)>>4, SH4_INTC_IRL1);
	443	m_exception_priority[SH4_INTC_IRL2]     = INTPRI((m_SH4_IPRC & 0x0f00)>>8, SH4_INTC_IRL2);
	444	m_exception_priority[SH4_INTC_IRL3]     = INTPRI((m_SH4_IPRC & 0xf000)>>12,SH4_INTC_IRL3);
	445	sh4_exception_recompute();
455	446	}
456	447	}
457	448	break;
r31221	r31222
460	451	{
461	452	if (mem_mask & 0xffff0000)
462	453	{
463		logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PCCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	454	logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PCCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
464	455	}
465	456
466	457	if (mem_mask & 0x0000ffff)
467	458	{
468		logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PDCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	459	logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PDCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
469	460	}
470	461	}
471	462	break;
r31221	r31222
474	465	{
475	466	if (mem_mask & 0xffff0000)
476	467	{
477		logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PECR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	468	logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PECR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
478	469	}
479	470
480	471	if (mem_mask & 0x0000ffff)
481	472	{
482		logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	473	logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
483	474	}
484	475	}
485	476	break;
r31221	r31222
489	480	{
490	481	if (mem_mask & 0xffff0000)
491	482	{
492		logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PGCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	483	logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PGCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
493	484	}
494	485
495	486	if (mem_mask & 0x0000ffff)
496	487	{
497		logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PHCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	488	logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PHCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
498	489	}
499	490	}
500	491	break;
r31221	r31222
504	495	{
505	496	if (mem_mask & 0xffff0000)
506	497	{
507		logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	498	logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
508	499	}
509	500
510	501	if (mem_mask & 0x0000ffff)
511	502	{
512		logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	503	logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
513	504	}
514	505	}
515	506	break;
r31221	r31222
519	510	{
520	511	if (mem_mask & 0xffff0000)
521	512	{
522		logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PLCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	513	logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PLCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
523	514	}
524	515
525	516	if (mem_mask & 0x0000ffff)
526	517	{
527		logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (SCPCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	518	logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (SCPCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
528	519	}
529	520	}
530	521	break;
r31221	r31222
533	524	{
534	525	if (mem_mask & 0xffff0000)
535	526	{
536		sh4->io->write_qword(SH3_PORT_A, (data>>24)&0xff);
537		//  logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PADR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	527	m_io->write_qword(SH3_PORT_A, (data>>24)&0xff);
	528	//  logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PADR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
538	529	}
539	530
540	531	if (mem_mask & 0x0000ffff)
541	532	{
542		sh4->io->write_qword(SH3_PORT_B, (data>>8)&0xff);
543		//  logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PBDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	533	m_io->write_qword(SH3_PORT_B, (data>>8)&0xff);
	534	//  logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PBDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
544	535	}
545	536	}
546	537	break;
r31221	r31222
549	540	{
550	541	if (mem_mask & 0xffff0000)
551	542	{
552		sh4->io->write_qword(SH3_PORT_C, (data>>24)&0xff);
553		//  logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PADR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	543	m_io->write_qword(SH3_PORT_C, (data>>24)&0xff);
	544	//  logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PADR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
554	545	}
555	546
556	547	if (mem_mask & 0x0000ffff)
557	548	{
558		sh4->io->write_qword(SH3_PORT_D, (data>>8)&0xff);
559		//  logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PBDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	549	m_io->write_qword(SH3_PORT_D, (data>>8)&0xff);
	550	//  logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PBDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
560	551	}
561	552	}
562	553	break;
r31221	r31222
564	555	{
565	556	if (mem_mask & 0xffff0000)
566	557	{
567		sh4->io->write_qword(SH3_PORT_E, (data>>24)&0xff);
568		//  logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PEDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	558	m_io->write_qword(SH3_PORT_E, (data>>24)&0xff);
	559	//  logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PEDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
569	560	}
570	561
571	562	if (mem_mask & 0x0000ffff)
572	563	{
573		sh4->io->write_qword(SH3_PORT_F, (data>>8)&0xff);
574		//  logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	564	m_io->write_qword(SH3_PORT_F, (data>>8)&0xff);
	565	//  logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
575	566	}
576	567	}
577	568	break;
r31221	r31222
580	571	{
581	572	if (mem_mask & 0xffff0000)
582	573	{
583		sh4->io->write_qword(SH3_PORT_G, (data>>24)&0xff);
584		//  logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PGDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	574	m_io->write_qword(SH3_PORT_G, (data>>24)&0xff);
	575	//  logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PGDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
585	576	}
586	577
587	578	if (mem_mask & 0x0000ffff)
588	579	{
589		sh4->io->write_qword(SH3_PORT_H, (data>>8)&0xff);
590		//  logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PHDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	580	m_io->write_qword(SH3_PORT_H, (data>>8)&0xff);
	581	//  logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PHDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
591	582	}
592	583	}
593	584	break;
r31221	r31222
597	588	{
598	589	if (mem_mask & 0xffff0000)
599	590	{
600		sh4->io->write_qword(SH3_PORT_J, (data>>24)&0xff);
601		//  logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	591	m_io->write_qword(SH3_PORT_J, (data>>24)&0xff);
	592	//  logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
602	593	}
603	594
604	595	if (mem_mask & 0x0000ffff)
605	596	{
606		sh4->io->write_qword(SH3_PORT_K, (data>>8)&0xff);
607		//logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	597	m_io->write_qword(SH3_PORT_K, (data>>8)&0xff);
	598	//logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
608	599	}
609	600	}
610	601	break;
r31221	r31222
613	604	{
614	605	if (mem_mask & 0xff000000)
615	606	{
616		logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSMR2 - Serial Mode Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	607	logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSMR2 - Serial Mode Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
617	608	}
618	609
619	610	if (mem_mask & 0x0000ff00)
620	611	{
621		logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCBRR2 - Bit Rate Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	612	logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCBRR2 - Bit Rate Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
622	613	}
623	614	}
624	615	break;
r31221	r31222
627	618	{
628	619	if (mem_mask & 0xff000000)
629	620	{
630		logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSCR2 - Serial Control Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	621	logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSCR2 - Serial Control Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
631	622	}
632	623
633	624	if (mem_mask & 0x0000ff00)
634	625	{
635		logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFTDR2 - Transmit FIFO Data Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	626	logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFTDR2 - Transmit FIFO Data Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
636	627	}
637	628	}
638	629	break;
r31221	r31222
641	632	{
642	633	if (mem_mask & 0xffff0000)
643	634	{
644		logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSSR2 - Serial Status Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	635	logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSSR2 - Serial Status Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
645	636	}
646	637
647	638	if (mem_mask & 0x0000ff00)
648	639	{
649		logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFRDR2 - Receive FIFO Data Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	640	logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFRDR2 - Receive FIFO Data Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
650	641	}
651	642	}
652	643	break;
r31221	r31222
655	646	{
656	647	if (mem_mask & 0xff000000)
657	648	{
658		logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFCR2 - Fifo Control Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	649	logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFCR2 - Fifo Control Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
659	650	}
660	651
661	652	if (mem_mask & 0x0000ffff)
662	653	{
663		logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFDR2 - Fifo Data Count Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask);
	654	logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFDR2 - Fifo Data Count Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
664	655	}
665	656	}
666	657	break;
r31221	r31222
668	659	default:
669	660	{
670	661	logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x\n",
671		sh4->device->tag(), sh4->pc & AM,
	662	tag(), m_pc & AM,
672	663	(offset *4)+0x4000000,
673	664	data,
674	665	mem_mask);
r31221	r31222
680	671	else
681	672	{
682	673	logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x\n",
683		sh4->device->tag(), sh4->pc & AM,
	674	tag(), m_pc & AM,
684	675	(offset *4)+0x4000000,
685	676	data,
686	677	mem_mask);

trunk/src/emu/cpu/sh4/sh4comn.c

r31221	r31222
233	233
234	234
235	235
236		void sh4_change_register_bank(sh4_state *sh4, int to)
	236	void sh34_base_device::sh4_change_register_bank(int to)
237	237	{
238		int s;
	238	int s;
239	239
240	240	if (to) // 0 -> 1
241	241	{
242	242	for (s = 0;s < 8;s++)
243	243	{
244		sh4->rbnk[0][s] = sh4->r[s];
245		sh4->r[s] = sh4->rbnk[1][s];
	244	m_rbnk[0][s] = m_r[s];
	245	m_r[s] = m_rbnk[1][s];
246	246	}
247	247	}
248	248	else // 1 -> 0
249	249	{
250	250	for (s = 0;s < 8;s++)
251	251	{
252		sh4->rbnk[1][s] = sh4->r[s];
253		sh4->r[s] = sh4->rbnk[0][s];
	252	m_rbnk[1][s] = m_r[s];
	253	m_r[s] = m_rbnk[0][s];
254	254	}
255	255	}
256	256	}
257	257
258		void sh4_swap_fp_registers(sh4_state *sh4)
	258	void sh34_base_device::sh4_swap_fp_registers()
259	259	{
260		int s;
261		UINT32 z;
	260	int s;
	261	UINT32 z;
262	262
263	263	for (s = 0;s <= 15;s++)
264	264	{
265		z = sh4->fr[s];
266		sh4->fr[s] = sh4->xf[s];
267		sh4->xf[s] = z;
	265	z = m_fr[s];
	266	m_fr[s] = m_xf[s];
	267	m_xf[s] = z;
268	268	}
269	269	}
270	270
271		#ifdef LSB_FIRST
272		void sh4_swap_fp_couples(sh4_state *sh4)
	271	void sh34_base_device::sh4_swap_fp_couples()
273	272	{
274		int s;
275		UINT32 z;
	273	int s;
	274	UINT32 z;
276	275
277	276	for (s = 0;s <= 15;s = s+2)
278	277	{
279		z = sh4->fr[s];
280		sh4->fr[s] = sh4->fr[s + 1];
281		sh4->fr[s + 1] = z;
282		z = sh4->xf[s];
283		sh4->xf[s] = sh4->xf[s + 1];
284		sh4->xf[s + 1] = z;
	278	z = m_fr[s];
	279	m_fr[s] = m_fr[s + 1];
	280	m_fr[s + 1] = z;
	281	z = m_xf[s];
	282	m_xf[s] = m_xf[s + 1];
	283	m_xf[s + 1] = z;
285	284	}
286	285	}
287		#endif
288	286
289		void sh4_syncronize_register_bank(sh4_state *sh4, int to)
	287	void sh34_base_device::sh4_syncronize_register_bank(int to)
290	288	{
291		int s;
	289	int s;
292	290
293	291	for (s = 0;s < 8;s++)
294	292	{
295		sh4->rbnk[to][s] = sh4->r[s];
	293	m_rbnk[to][s] = m_r[s];
296	294	}
297	295	}
298	296
299		void sh4_default_exception_priorities(sh4_state *sh4) // setup default priorities for exceptions
	297	void sh34_base_device::sh4_default_exception_priorities() // setup default priorities for exceptions
300	298	{
301		int a;
	299	int a;
302	300
303	301	for (a=0;a <= SH4_INTC_NMI;a++)
304		sh4->exception_priority[a] = exception_priority_default[a];
	302	m_exception_priority[a] = exception_priority_default[a];
305	303	for (a=SH4_INTC_IRLn0;a <= SH4_INTC_IRLnE;a++)
306		sh4->exception_priority[a] = INTPRI(15-(a-SH4_INTC_IRLn0), a);
307		sh4->exception_priority[SH4_INTC_IRL0] = INTPRI(13, SH4_INTC_IRL0);
308		sh4->exception_priority[SH4_INTC_IRL1] = INTPRI(10, SH4_INTC_IRL1);
309		sh4->exception_priority[SH4_INTC_IRL2] = INTPRI(7, SH4_INTC_IRL2);
310		sh4->exception_priority[SH4_INTC_IRL3] = INTPRI(4, SH4_INTC_IRL3);
	304	m_exception_priority[a] = INTPRI(15-(a-SH4_INTC_IRLn0), a);
	305	m_exception_priority[SH4_INTC_IRL0] = INTPRI(13, SH4_INTC_IRL0);
	306	m_exception_priority[SH4_INTC_IRL1] = INTPRI(10, SH4_INTC_IRL1);
	307	m_exception_priority[SH4_INTC_IRL2] = INTPRI(7, SH4_INTC_IRL2);
	308	m_exception_priority[SH4_INTC_IRL3] = INTPRI(4, SH4_INTC_IRL3);
311	309	for (a=SH4_INTC_HUDI;a <= SH4_INTC_ROVI;a++)
312		sh4->exception_priority[a] = INTPRI(0, a);
	310	m_exception_priority[a] = INTPRI(0, a);
313	311	}
314	312
315		void sh4_exception_recompute(sh4_state *sh4) // checks if there is any interrupt with high enough priority
	313	void sh34_base_device::sh4_exception_recompute() // checks if there is any interrupt with high enough priority
316	314	{
317	315	int a,z;
318	316
319		sh4->test_irq = 0;
320		if ((!sh4->pending_irq) || ((sh4->sr & BL) && (sh4->exception_requesting[SH4_INTC_NMI] == 0)))
	317	m_test_irq = 0;
	318	if ((!m_pending_irq) || ((m_sr & BL) && (m_exception_requesting[SH4_INTC_NMI] == 0)))
321	319	return;
322		z = (sh4->sr >> 4) & 15;
	320	z = (m_sr >> 4) & 15;
323	321	for (a=0;a <= SH4_INTC_ROVI;a++)
324	322	{
325		if (sh4->exception_requesting[a])
	323	if (m_exception_requesting[a])
326	324	{
327		int pri = (((int)sh4->exception_priority[a] >> 8) & 255);
	325	int pri = (((int)m_exception_priority[a] >> 8) & 255);
328	326	//logerror("pri is %02x z is %02x\n",pri,z);
329	327	if (pri > z)
330	328	{
331	329	//logerror("will test\n");
332		sh4->test_irq = 1; // will check for exception at end of instructions
	330	m_test_irq = 1; // will check for exception at end of instructions
333	331	break;
334	332	}
335	333	}
336	334	}
337	335	}
338	336
339		void sh4_exception_request(sh4_state *sh4, int exception) // start requesting an exception
	337	void sh34_base_device::sh4_exception_request(int exception) // start requesting an exception
340	338	{
341	339	//logerror("sh4_exception_request a\n");
342		if (!sh4->exception_requesting[exception])
	340	if (!m_exception_requesting[exception])
343	341	{
344	342	//logerror("sh4_exception_request b\n");
345		sh4->exception_requesting[exception] = 1;
346		sh4->pending_irq++;
347		sh4_exception_recompute(sh4);
	343	m_exception_requesting[exception] = 1;
	344	m_pending_irq++;
	345	sh4_exception_recompute();
348	346	}
349	347	}
350	348
351		void sh4_exception_unrequest(sh4_state *sh4, int exception) // stop requesting an exception
	349	void sh34_base_device::sh4_exception_unrequest(int exception) // stop requesting an exception
352	350	{
353		if (sh4->exception_requesting[exception])
	351	if (m_exception_requesting[exception])
354	352	{
355		sh4->exception_requesting[exception] = 0;
356		sh4->pending_irq--;
357		sh4_exception_recompute(sh4);
	353	m_exception_requesting[exception] = 0;
	354	m_pending_irq--;
	355	sh4_exception_recompute();
358	356	}
359	357	}
360	358
361		void sh4_exception_checkunrequest(sh4_state *sh4, int exception)
	359	void sh34_base_device::sh4_exception_checkunrequest(int exception)
362	360	{
363	361	if (exception == SH4_INTC_NMI)
364		sh4_exception_unrequest(sh4, exception);
	362	sh4_exception_unrequest(exception);
365	363	if ((exception == SH4_INTC_DMTE0) || (exception == SH4_INTC_DMTE1) ||
366	364	(exception == SH4_INTC_DMTE2) || (exception == SH4_INTC_DMTE3))
367		sh4_exception_unrequest(sh4, exception);
	365	sh4_exception_unrequest(exception);
368	366	}
369	367
370		void sh4_exception(sh4_state *sh4, const char *message, int exception) // handle exception
	368	void sh34_base_device::sh4_exception(const char *message, int exception) // handle exception
371	369	{
372	370	UINT32 vector;
373	371
374	372
375		if (sh4->cpu_type == CPU_TYPE_SH4)
	373	if (m_cpu_type == CPU_TYPE_SH4)
376	374	{
377	375	if (exception < SH4_INTC_NMI)
378	376	return; // Not yet supported
379	377	if (exception == SH4_INTC_NMI) {
380		if ((sh4->sr & BL) && (!(sh4->m[ICR] & 0x200)))
	378	if ((m_sr & BL) && (!(m_m[ICR] & 0x200)))
381	379	return;
382	380
383		sh4->m[ICR] &= ~0x200;
384		sh4->m[INTEVT] = 0x1c0;
	381	m_m[ICR] &= ~0x200;
	382	m_m[INTEVT] = 0x1c0;
385	383
386	384
387	385	vector = 0x600;
388		sh4->irq_callback(*sh4->device, INPUT_LINE_NMI);
389		LOG(("SH-4 '%s' nmi exception after [%s]\n", sh4->device->tag(), message));
	386	standard_irq_callback(INPUT_LINE_NMI);
	387	LOG(("SH-4 '%s' nmi exception after [%s]\n", tag(), message));
390	388	} else {
391		//      if ((sh4->m[ICR] & 0x4000) && (sh4->nmi_line_state == ASSERT_LINE))
	389	//      if ((m_m[ICR] & 0x4000) && (m_nmi_line_state == ASSERT_LINE))
392	390	//          return;
393		if (sh4->sr & BL)
	391	if (m_sr & BL)
394	392	return;
395		if (((sh4->exception_priority[exception] >> 8) & 255) <= ((sh4->sr >> 4) & 15))
	393	if (((m_exception_priority[exception] >> 8) & 255) <= ((m_sr >> 4) & 15))
396	394	return;
397		sh4->m[INTEVT] = exception_codes[exception];
	395	m_m[INTEVT] = exception_codes[exception];
398	396	vector = 0x600;
399	397	if ((exception >= SH4_INTC_IRL0) && (exception <= SH4_INTC_IRL3))
400		sh4->irq_callback(*sh4->device, SH4_INTC_IRL0-exception+SH4_IRL0);
	398	standard_irq_callback(SH4_INTC_IRL0-exception+SH4_IRL0);
401	399	else
402		sh4->irq_callback(*sh4->device, SH4_IRL3+1);
403		LOG(("SH-4 '%s' interrupt exception #%d after [%s]\n", sh4->device->tag(), exception, message));
	400	standard_irq_callback(SH4_IRL3+1);
	401	LOG(("SH-4 '%s' interrupt exception #%d after [%s]\n", tag(), exception, message));
404	402	}
405	403	}
406	404	else /* SH3 exceptions */
r31221	r31222
415	413	}
416	414	else
417	415	{
418		if (sh4->sr & BL)
	416	if (m_sr & BL)
419	417	return;
420		if (((sh4->exception_priority[exception] >> 8) & 255) <= ((sh4->sr >> 4) & 15))
	418	if (((m_exception_priority[exception] >> 8) & 255) <= ((m_sr >> 4) & 15))
421	419	return;
422	420
423	421
424	422	vector = 0x600;
425	423
426	424	if ((exception >= SH4_INTC_IRL0) && (exception <= SH4_INTC_IRL3))
427		sh4->irq_callback(*sh4->device, SH4_INTC_IRL0-exception+SH4_IRL0);
	425	standard_irq_callback(SH4_INTC_IRL0-exception+SH4_IRL0);
428	426	else
429		sh4->irq_callback(*sh4->device, SH4_IRL3+1);
	427	standard_irq_callback(SH4_IRL3+1);
430	428
431	429	if (sh3_intevt2_exception_codes[exception]==-1)
432	430	fatalerror("sh3_intevt2_exception_codes unpopulated for exception %02x\n", exception);
433	431
434		sh4->m_sh3internal_lower[INTEVT2] = sh3_intevt2_exception_codes[exception];
435		sh4->m_sh3internal_upper[SH3_EXPEVT_ADDR] = exception_codes[exception];
	432	m_sh3internal_lower[INTEVT2] = sh3_intevt2_exception_codes[exception];
	433	m_sh3internal_upper[SH3_EXPEVT_ADDR] = exception_codes[exception];
436	434
437	435
438		LOG(("SH-3 '%s' interrupt exception #%d after [%s]\n", sh4->device->tag(), exception, message));
	436	LOG(("SH-3 '%s' interrupt exception #%d after [%s]\n", tag(), exception, message));
439	437	}
440	438
441	439	/***** END ASSUME THIS TO BE WRONG FOR NOW *****/
442	440	}
443		sh4_exception_checkunrequest(sh4, exception);
	441	sh4_exception_checkunrequest(exception);
444	442
445		sh4->spc = sh4->pc;
446		sh4->ssr = sh4->sr;
447		sh4->sgr = sh4->r[15];
	443	m_spc = m_pc;
	444	m_ssr = m_sr;
	445	m_sgr = m_r[15];
448	446
449		sh4->sr |= MD;
450		if ((sh4->device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
451		sh4_syncronize_register_bank(sh4, (sh4->sr & sRB) >> 29);
452		if (!(sh4->sr & sRB))
453		sh4_change_register_bank(sh4, 1);
454		sh4->sr |= sRB;
455		sh4->sr |= BL;
456		sh4_exception_recompute(sh4);
	447	m_sr |= MD;
	448	if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
	449	sh4_syncronize_register_bank((m_sr & sRB) >> 29);
	450	if (!(m_sr & sRB))
	451	sh4_change_register_bank(1);
	452	m_sr |= sRB;
	453	m_sr |= BL;
	454	sh4_exception_recompute();
457	455
458	456	/* fetch PC */
459		sh4->pc = sh4->vbr + vector;
	457	m_pc = m_vbr + vector;
460	458	/* wake up if a sleep opcode is triggered */
461		if(sh4->sleep_mode == 1) { sh4->sleep_mode = 2; }
	459	if(m_sleep_mode == 1) { m_sleep_mode = 2; }
462	460	}
463	461
464	462
465		static UINT32 compute_ticks_refresh_timer(emu_timer *timer, int hertz, int base, int divisor)
	463	UINT32 sh34_base_device::compute_ticks_refresh_timer(emu_timer *timer, int hertz, int base, int divisor)
466	464	{
467	465	// elapsed:total = x : ticks
468		// x=elapsed*tics/total -> x=elapsed*(double)100000000/rtcnt_div[(sh4->m[RTCSR] >> 3) & 7]
469		// ticks/total=ticks / ((rtcnt_div[(sh4->m[RTCSR] >> 3) & 7] * ticks) / 100000000)=1/((rtcnt_div[(sh4->m[RTCSR] >> 3) & 7] / 100000000)=100000000/rtcnt_div[(sh4->m[RTCSR] >> 3) & 7]
	466	// x=elapsed*tics/total -> x=elapsed*(double)100000000/rtcnt_div[(m_m[RTCSR] >> 3) & 7]
	467	// ticks/total=ticks / ((rtcnt_div[(m_m[RTCSR] >> 3) & 7] * ticks) / 100000000)=1/((rtcnt_div[(m_m[RTCSR] >> 3) & 7] / 100000000)=100000000/rtcnt_div[(m_m[RTCSR] >> 3) & 7]
470	468	return base + (UINT32)((timer->elapsed().as_double() * (double)hertz) / (double)divisor);
471	469	}
472	470
473		static void sh4_refresh_timer_recompute(sh4_state *sh4)
	471	void sh34_base_device::sh4_refresh_timer_recompute()
474	472	{
475		UINT32 ticks;
	473	UINT32 ticks;
476	474
477		if (sh4->cpu_type != CPU_TYPE_SH4)
478		fatalerror("sh4_refresh_timer_recompute uses sh4->m[] with SH3\n");
	475	if (m_cpu_type != CPU_TYPE_SH4)
	476	fatalerror("sh4_refresh_timer_recompute uses m_m[] with SH3\n");
479	477
480	478
481	479	//if rtcnt < rtcor then rtcor-rtcnt
482	480	//if rtcnt >= rtcor then 256-rtcnt+rtcor=256+rtcor-rtcnt
483		ticks = sh4->m[RTCOR]-sh4->m[RTCNT];
	481	ticks = m_m[RTCOR]-m_m[RTCNT];
484	482	if (ticks <= 0)
485	483	ticks = 256 + ticks;
486		sh4->refresh_timer->adjust(attotime::from_hz(sh4->bus_clock) * rtcnt_div[(sh4->m[RTCSR] >> 3) & 7] * ticks);
487		sh4->refresh_timer_base = sh4->m[RTCNT];
	484	m_refresh_timer->adjust(attotime::from_hz(m_bus_clock) * rtcnt_div[(m_m[RTCSR] >> 3) & 7] * ticks);
	485	m_refresh_timer_base = m_m[RTCNT];
488	486	}
489	487
490	488
491		static TIMER_CALLBACK( sh4_refresh_timer_callback )
	489	TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_refresh_timer_callback )
492	490	{
493		sh4_state *sh4 = (sh4_state *)ptr;
	491	if (m_cpu_type != CPU_TYPE_SH4)
	492	fatalerror("sh4_refresh_timer_callback uses m_m[] with SH3\n");
494	493
495		if (sh4->cpu_type != CPU_TYPE_SH4)
496		fatalerror("sh4_refresh_timer_callback uses sh4->m[] with SH3\n");
497
498		sh4->m[RTCNT] = 0;
499		sh4_refresh_timer_recompute(sh4);
500		sh4->m[RTCSR] |= 128;
501		if ((sh4->m[MCR] & 4) && !(sh4->m[MCR] & 2))
	494	m_m[RTCNT] = 0;
	495	sh4_refresh_timer_recompute();
	496	m_m[RTCSR] |= 128;
	497	if ((m_m[MCR] & 4) && !(m_m[MCR] & 2))
502	498	{
503		sh4->m[RFCR] = (sh4->m[RFCR] + 1) & 1023;
504		if (((sh4->m[RTCSR] & 1) && (sh4->m[RFCR] == 512)) || (sh4->m[RFCR] == 0))
	499	m_m[RFCR] = (m_m[RFCR] + 1) & 1023;
	500	if (((m_m[RTCSR] & 1) && (m_m[RFCR] == 512)) || (m_m[RFCR] == 0))
505	501	{
506		sh4->m[RFCR] = 0;
507		sh4->m[RTCSR] |= 4;
	502	m_m[RFCR] = 0;
	503	m_m[RTCSR] |= 4;
508	504	}
509	505	}
510	506	}
511	507
512		static void increment_rtc_time(sh4_state *sh4, int mode)
	508	void sh34_base_device::increment_rtc_time(int mode)
513	509	{
514	510	int carry, year, leap, days;
515	511
516		if (sh4->cpu_type != CPU_TYPE_SH4)
517		fatalerror("increment_rtc_time uses sh4->m[] with SH3\n");
	512	if (m_cpu_type != CPU_TYPE_SH4)
	513	fatalerror("increment_rtc_time uses m_m[] with SH3\n");
518	514
519	515	if (mode == 0)
520	516	{
521	517	carry = 0;
522		sh4->m[RSECCNT] = sh4->m[RSECCNT] + 1;
523		if ((sh4->m[RSECCNT] & 0xf) == 0xa)
524		sh4->m[RSECCNT] = sh4->m[RSECCNT] + 6;
525		if (sh4->m[RSECCNT] == 0x60)
	518	m_m[RSECCNT] = m_m[RSECCNT] + 1;
	519	if ((m_m[RSECCNT] & 0xf) == 0xa)
	520	m_m[RSECCNT] = m_m[RSECCNT] + 6;
	521	if (m_m[RSECCNT] == 0x60)
526	522	{
527		sh4->m[RSECCNT] = 0;
	523	m_m[RSECCNT] = 0;
528	524	carry=1;
529	525	}
530	526	else
r31221	r31222
533	529	else
534	530	carry = 1;
535	531
536		sh4->m[RMINCNT] = sh4->m[RMINCNT] + carry;
537		if ((sh4->m[RMINCNT] & 0xf) == 0xa)
538		sh4->m[RMINCNT] = sh4->m[RMINCNT] + 6;
	532	m_m[RMINCNT] = m_m[RMINCNT] + carry;
	533	if ((m_m[RMINCNT] & 0xf) == 0xa)
	534	m_m[RMINCNT] = m_m[RMINCNT] + 6;
539	535	carry=0;
540		if (sh4->m[RMINCNT] == 0x60)
	536	if (m_m[RMINCNT] == 0x60)
541	537	{
542		sh4->m[RMINCNT] = 0;
	538	m_m[RMINCNT] = 0;
543	539	carry = 1;
544	540	}
545	541
546		sh4->m[RHRCNT] = sh4->m[RHRCNT] + carry;
547		if ((sh4->m[RHRCNT] & 0xf) == 0xa)
548		sh4->m[RHRCNT] = sh4->m[RHRCNT] + 6;
	542	m_m[RHRCNT] = m_m[RHRCNT] + carry;
	543	if ((m_m[RHRCNT] & 0xf) == 0xa)
	544	m_m[RHRCNT] = m_m[RHRCNT] + 6;
549	545	carry = 0;
550		if (sh4->m[RHRCNT] == 0x24)
	546	if (m_m[RHRCNT] == 0x24)
551	547	{
552		sh4->m[RHRCNT] = 0;
	548	m_m[RHRCNT] = 0;
553	549	carry = 1;
554	550	}
555	551
556		sh4->m[RWKCNT] = sh4->m[RWKCNT] + carry;
557		if (sh4->m[RWKCNT] == 0x7)
	552	m_m[RWKCNT] = m_m[RWKCNT] + carry;
	553	if (m_m[RWKCNT] == 0x7)
558	554	{
559		sh4->m[RWKCNT] = 0;
	555	m_m[RWKCNT] = 0;
560	556	}
561	557
562	558	days = 0;
563		year = (sh4->m[RYRCNT] & 0xf) + ((sh4->m[RYRCNT] & 0xf0) >> 4)*10 + ((sh4->m[RYRCNT] & 0xf00) >> 8)*100 + ((sh4->m[RYRCNT] & 0xf000) >> 12)*1000;
	559	year = (m_m[RYRCNT] & 0xf) + ((m_m[RYRCNT] & 0xf0) >> 4)*10 + ((m_m[RYRCNT] & 0xf00) >> 8)*100 + ((m_m[RYRCNT] & 0xf000) >> 12)*1000;
564	560	leap = 0;
565	561	if (!(year%100))
566	562	{
r31221	r31222
569	565	}
570	566	else if (!(year%4))
571	567	leap = 1;
572		if (sh4->m[RMONCNT] != 2)
	568	if (m_m[RMONCNT] != 2)
573	569	leap = 0;
574		if (sh4->m[RMONCNT])
575		days = daysmonth[(sh4->m[RMONCNT] & 0xf) + ((sh4->m[RMONCNT] & 0xf0) >> 4)*10 - 1];
	570	if (m_m[RMONCNT])
	571	days = daysmonth[(m_m[RMONCNT] & 0xf) + ((m_m[RMONCNT] & 0xf0) >> 4)*10 - 1];
576	572
577		sh4->m[RDAYCNT] = sh4->m[RDAYCNT] + carry;
578		if ((sh4->m[RDAYCNT] & 0xf) == 0xa)
579		sh4->m[RDAYCNT] = sh4->m[RDAYCNT] + 6;
	573	m_m[RDAYCNT] = m_m[RDAYCNT] + carry;
	574	if ((m_m[RDAYCNT] & 0xf) == 0xa)
	575	m_m[RDAYCNT] = m_m[RDAYCNT] + 6;
580	576	carry = 0;
581		if (sh4->m[RDAYCNT] > (days+leap))
	577	if (m_m[RDAYCNT] > (days+leap))
582	578	{
583		sh4->m[RDAYCNT] = 1;
	579	m_m[RDAYCNT] = 1;
584	580	carry = 1;
585	581	}
586	582
587		sh4->m[RMONCNT] = sh4->m[RMONCNT] + carry;
588		if ((sh4->m[RMONCNT] & 0xf) == 0xa)
589		sh4->m[RMONCNT] = sh4->m[RMONCNT] + 6;
	583	m_m[RMONCNT] = m_m[RMONCNT] + carry;
	584	if ((m_m[RMONCNT] & 0xf) == 0xa)
	585	m_m[RMONCNT] = m_m[RMONCNT] + 6;
590	586	carry=0;
591		if (sh4->m[RMONCNT] == 0x13)
	587	if (m_m[RMONCNT] == 0x13)
592	588	{
593		sh4->m[RMONCNT] = 1;
	589	m_m[RMONCNT] = 1;
594	590	carry = 1;
595	591	}
596	592
597		sh4->m[RYRCNT] = sh4->m[RYRCNT] + carry;
598		if ((sh4->m[RYRCNT] & 0xf) >= 0xa)
599		sh4->m[RYRCNT] = sh4->m[RYRCNT] + 6;
600		if ((sh4->m[RYRCNT] & 0xf0) >= 0xa0)
601		sh4->m[RYRCNT] = sh4->m[RYRCNT] + 0x60;
602		if ((sh4->m[RYRCNT] & 0xf00) >= 0xa00)
603		sh4->m[RYRCNT] = sh4->m[RYRCNT] + 0x600;
604		if ((sh4->m[RYRCNT] & 0xf000) >= 0xa000)
605		sh4->m[RYRCNT] = 0;
	593	m_m[RYRCNT] = m_m[RYRCNT] + carry;
	594	if ((m_m[RYRCNT] & 0xf) >= 0xa)
	595	m_m[RYRCNT] = m_m[RYRCNT] + 6;
	596	if ((m_m[RYRCNT] & 0xf0) >= 0xa0)
	597	m_m[RYRCNT] = m_m[RYRCNT] + 0x60;
	598	if ((m_m[RYRCNT] & 0xf00) >= 0xa00)
	599	m_m[RYRCNT] = m_m[RYRCNT] + 0x600;
	600	if ((m_m[RYRCNT] & 0xf000) >= 0xa000)
	601	m_m[RYRCNT] = 0;
606	602	}
607	603
608		static TIMER_CALLBACK( sh4_rtc_timer_callback )
	604	TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_rtc_timer_callback )
609	605	{
610		sh4_state *sh4 = (sh4_state *)ptr;
611
612		if (sh4->cpu_type != CPU_TYPE_SH4)
	606	if (m_cpu_type != CPU_TYPE_SH4)
613	607	{
614		logerror("sh4_rtc_timer_callback uses sh4->m[] with SH3\n");
	608	logerror("sh4_rtc_timer_callback uses m_m[] with SH3\n");
615	609	return;
616	610	}
617	611
618		sh4->rtc_timer->adjust(attotime::from_hz(128));
619		sh4->m[R64CNT] = (sh4->m[R64CNT]+1) & 0x7f;
620		if (sh4->m[R64CNT] == 64)
	612	m_rtc_timer->adjust(attotime::from_hz(128));
	613	m_m[R64CNT] = (m_m[R64CNT]+1) & 0x7f;
	614	if (m_m[R64CNT] == 64)
621	615	{
622		sh4->m[RCR1] |= 0x80;
623		increment_rtc_time(sh4, 0);
624		//sh4_exception_request(sh4, SH4_INTC_NMI); // TEST
	616	m_m[RCR1] |= 0x80;
	617	increment_rtc_time(0);
	618	//sh4_exception_request(SH4_INTC_NMI); // TEST
625	619	}
626	620	}
627	621
628	622
629		static void sh4_dmac_nmi(sh4_state *sh4) // manage dma when nmi gets asserted
	623	void sh34_base_device::sh4_dmac_nmi() // manage dma when nmi gets asserted
630	624	{
631	625	int s;
632	626
633		sh4->SH4_DMAOR |= DMAOR_NMIF;
	627	m_SH4_DMAOR |= DMAOR_NMIF;
634	628	for (s = 0;s < 4;s++)
635	629	{
636		if (sh4->dma_timer_active[s])
	630	if (m_dma_timer_active[s])
637	631	{
638	632	logerror("SH4: DMA %d cancelled due to NMI but all data transferred", s);
639		sh4->dma_timer[s]->adjust(attotime::never, s);
640		sh4->dma_timer_active[s] = 0;
	633	m_dma_timer[s]->adjust(attotime::never, s);
	634	m_dma_timer_active[s] = 0;
641	635	}
642	636	}
643	637	}
644	638
645		void sh4_handler_ipra_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	639	void sh34_base_device::sh4_handler_ipra_w(UINT32 data, UINT32 mem_mask)
646	640	{
647		COMBINE_DATA(&sh4->SH4_IPRA);
	641	COMBINE_DATA(&m_SH4_IPRA);
648	642	/* 15 - 12 TMU0 */
649	643	/* 11 -  8 TMU1 */
650	644	/*  7 -  4 TMU2 */
651	645	/*  3 -  0 RTC  */
652		sh4->exception_priority[SH4_INTC_ATI]     = INTPRI(sh4->SH4_IPRA & 0x000f, SH4_INTC_ATI);
653		sh4->exception_priority[SH4_INTC_PRI]     = INTPRI(sh4->SH4_IPRA & 0x000f, SH4_INTC_PRI);
654		sh4->exception_priority[SH4_INTC_CUI]     = INTPRI(sh4->SH4_IPRA & 0x000f, SH4_INTC_CUI);
	646	m_exception_priority[SH4_INTC_ATI]     = INTPRI(m_SH4_IPRA & 0x000f, SH4_INTC_ATI);
	647	m_exception_priority[SH4_INTC_PRI]     = INTPRI(m_SH4_IPRA & 0x000f, SH4_INTC_PRI);
	648	m_exception_priority[SH4_INTC_CUI]     = INTPRI(m_SH4_IPRA & 0x000f, SH4_INTC_CUI);
655	649
656		sh4->exception_priority[SH4_INTC_TUNI2]  = INTPRI((sh4->SH4_IPRA & 0x00f0) >> 4, SH4_INTC_TUNI2);
657		sh4->exception_priority[SH4_INTC_TICPI2] = INTPRI((sh4->SH4_IPRA & 0x00f0) >> 4, SH4_INTC_TICPI2);
	650	m_exception_priority[SH4_INTC_TUNI2]  = INTPRI((m_SH4_IPRA & 0x00f0) >> 4, SH4_INTC_TUNI2);
	651	m_exception_priority[SH4_INTC_TICPI2] = INTPRI((m_SH4_IPRA & 0x00f0) >> 4, SH4_INTC_TICPI2);
658	652
659		sh4->exception_priority[SH4_INTC_TUNI1]  = INTPRI((sh4->SH4_IPRA & 0x0f00) >> 8, SH4_INTC_TUNI1);
	653	m_exception_priority[SH4_INTC_TUNI1]  = INTPRI((m_SH4_IPRA & 0x0f00) >> 8, SH4_INTC_TUNI1);
660	654
661		sh4->exception_priority[SH4_INTC_TUNI0]  = INTPRI((sh4->SH4_IPRA & 0xf000) >> 12, SH4_INTC_TUNI0);
	655	m_exception_priority[SH4_INTC_TUNI0]  = INTPRI((m_SH4_IPRA & 0xf000) >> 12, SH4_INTC_TUNI0);
662	656
663		logerror("setting priorities TMU0 %01x TMU1 %01x TMU2 %01x RTC %01x\n", (sh4->SH4_IPRA & 0xf000)>>12, (sh4->SH4_IPRA & 0x0f00)>>8, (sh4->SH4_IPRA & 0x00f0)>>4, (sh4->SH4_IPRA & 0x000f)>>0);
	657	logerror("setting priorities TMU0 %01x TMU1 %01x TMU2 %01x RTC %01x\n", (m_SH4_IPRA & 0xf000)>>12, (m_SH4_IPRA & 0x0f00)>>8, (m_SH4_IPRA & 0x00f0)>>4, (m_SH4_IPRA & 0x000f)>>0);
664	658
665		sh4_exception_recompute(sh4);
	659	sh4_exception_recompute();
666	660	}
667	661
668	662
669		WRITE32_MEMBER( sh4_device::sh4_internal_w )
	663	WRITE32_MEMBER( sh4_base_device::sh4_internal_w )
670	664	{
671		sh4_state *sh4 = get_safe_token(this);
672	665	int a;
673	666	UINT32 addr = (offset << 2) + 0xfe000000;
674	667	offset = ((addr & 0xfc) >> 2) | ((addr & 0x1fe0000) >> 11);
675	668
676		if (sh4->cpu_type != CPU_TYPE_SH4)
677		fatalerror("sh4_internal_w uses sh4->m[] with SH3\n");
	669	if (m_cpu_type != CPU_TYPE_SH4)
	670	fatalerror("sh4_internal_w uses m_m[] with SH3\n");
678	671
679		UINT32 old = sh4->m[offset];
680		COMBINE_DATA(sh4->m+offset);
	672	UINT32 old = m_m[offset];
	673	COMBINE_DATA(m_m+offset);
681	674
682	675	//  printf("sh4_internal_w:  Write %08x (%x), %08x @ %08x\n", 0xfe000000+((offset & 0x3fc0) << 11)+((offset & 0x3f) << 2), offset, data, mem_mask);
683	676
r31221	r31222
689	682	printf("SH4 MMU Enabled\n");
690	683	printf("If you're seeing this, but running something other than a Naomi GD-ROM game then chances are it won't work\n");
691	684	printf("The MMU emulation is a hack specific to that system\n");
692		sh4->sh4_mmu_enabled = 1;
	685	m_sh4_mmu_enabled = 1;
693	686
694	687	// should be a different bit!
695	688	{
696	689	int i;
697	690	for (i=0;i<64;i++)
698	691	{
699		sh4->sh4_tlb_address[i] = 0;
700		sh4->sh4_tlb_data[i] = 0;
	692	m_sh4_tlb_address[i] = 0;
	693	m_sh4_tlb_data[i] = 0;
701	694	}
702	695
703	696	}
704	697	}
705	698	else
706	699	{
707		sh4->sh4_mmu_enabled = 0;
	700	m_sh4_mmu_enabled = 0;
708	701	}
709	702
710	703	break;
711	704
712	705	// Memory refresh
713	706	case RTCSR:
714		sh4->m[RTCSR] &= 255;
	707	m_m[RTCSR] &= 255;
715	708	if ((old >> 3) & 7)
716		sh4->m[RTCNT] = compute_ticks_refresh_timer(sh4->refresh_timer, sh4->bus_clock, sh4->refresh_timer_base, rtcnt_div[(old >> 3) & 7]) & 0xff;
717		if ((sh4->m[RTCSR] >> 3) & 7)
	709	m_m[RTCNT] = compute_ticks_refresh_timer(m_refresh_timer, m_bus_clock, m_refresh_timer_base, rtcnt_div[(old >> 3) & 7]) & 0xff;
	710	if ((m_m[RTCSR] >> 3) & 7)
718	711	{ // activated
719		sh4_refresh_timer_recompute(sh4);
	712	sh4_refresh_timer_recompute();
720	713	}
721	714	else
722	715	{
723		sh4->refresh_timer->adjust(attotime::never);
	716	m_refresh_timer->adjust(attotime::never);
724	717	}
725	718	break;
726	719
727	720	case RTCNT:
728		sh4->m[RTCNT] &= 255;
729		if ((sh4->m[RTCSR] >> 3) & 7)
	721	m_m[RTCNT] &= 255;
	722	if ((m_m[RTCSR] >> 3) & 7)
730	723	{ // active
731		sh4_refresh_timer_recompute(sh4);
	724	sh4_refresh_timer_recompute();
732	725	}
733	726	break;
734	727
735	728	case RTCOR:
736		sh4->m[RTCOR] &= 255;
737		if ((sh4->m[RTCSR] >> 3) & 7)
	729	m_m[RTCOR] &= 255;
	730	if ((m_m[RTCSR] >> 3) & 7)
738	731	{ // active
739		sh4->m[RTCNT] = compute_ticks_refresh_timer(sh4->refresh_timer, sh4->bus_clock, sh4->refresh_timer_base, rtcnt_div[(sh4->m[RTCSR] >> 3) & 7]) & 0xff;
740		sh4_refresh_timer_recompute(sh4);
	732	m_m[RTCNT] = compute_ticks_refresh_timer(m_refresh_timer, m_bus_clock, m_refresh_timer_base, rtcnt_div[(m_m[RTCSR] >> 3) & 7]) & 0xff;
	733	sh4_refresh_timer_recompute();
741	734	}
742	735	break;
743	736
744	737	case RFCR:
745		sh4->m[RFCR] &= 1023;
	738	m_m[RFCR] &= 1023;
746	739	break;
747	740
748	741	// RTC
749	742	case RCR1:
750		if ((sh4->m[RCR1] & 8) && (~old & 8)) // 0 -> 1
751		sh4->m[RCR1] ^= 1;
	743	if ((m_m[RCR1] & 8) && (~old & 8)) // 0 -> 1
	744	m_m[RCR1] ^= 1;
752	745	break;
753	746
754	747	case RCR2:
755		if (sh4->m[RCR2] & 2)
	748	if (m_m[RCR2] & 2)
756	749	{
757		sh4->m[R64CNT] = 0;
758		sh4->m[RCR2] ^= 2;
	750	m_m[R64CNT] = 0;
	751	m_m[RCR2] ^= 2;
759	752	}
760		if (sh4->m[RCR2] & 4)
	753	if (m_m[RCR2] & 4)
761	754	{
762		sh4->m[R64CNT] = 0;
763		if (sh4->m[RSECCNT] >= 30)
764		increment_rtc_time(sh4, 1);
765		sh4->m[RSECCNT] = 0;
	755	m_m[R64CNT] = 0;
	756	if (m_m[RSECCNT] >= 30)
	757	increment_rtc_time(1);
	758	m_m[RSECCNT] = 0;
766	759	}
767		if ((sh4->m[RCR2] & 8) && (~old & 8))
	760	if ((m_m[RCR2] & 8) && (~old & 8))
768	761	{ // 0 -> 1
769		sh4->rtc_timer->adjust(attotime::from_hz(128));
	762	m_rtc_timer->adjust(attotime::from_hz(128));
770	763	}
771		else if (~(sh4->m[RCR2]) & 8)
	764	else if (~(m_m[RCR2]) & 8)
772	765	{ // 0
773		sh4->rtc_timer->adjust(attotime::never);
	766	m_rtc_timer->adjust(attotime::never);
774	767	}
775	768	break;
776	769
777	770	/*********************************************************************************************************************
778	771	TMU (Timer Unit)
779	772	*********************************************************************************************************************/
780		case SH4_TSTR_ADDR: sh4_handle_tstr_addr_w(sh4,data,mem_mask);   break;
781		case SH4_TCR0_ADDR: sh4_handle_tcr0_addr_w(sh4,data,mem_mask);   break;
782		case SH4_TCR1_ADDR: sh4_handle_tcr1_addr_w(sh4,data,mem_mask);   break;
783		case SH4_TCR2_ADDR: sh4_handle_tcr2_addr_w(sh4,data,mem_mask);   break;
784		case SH4_TCOR0_ADDR: sh4_handle_tcor0_addr_w(sh4,data,mem_mask); break;
785		case SH4_TCNT0_ADDR: sh4_handle_tcnt0_addr_w(sh4,data,mem_mask); break;
786		case SH4_TCOR1_ADDR: sh4_handle_tcor1_addr_w(sh4,data,mem_mask); break;
787		case SH4_TCNT1_ADDR: sh4_handle_tcnt1_addr_w(sh4,data,mem_mask); break;
788		case SH4_TCOR2_ADDR: sh4_handle_tcor2_addr_w(sh4,data,mem_mask); break;
789		case SH4_TCNT2_ADDR: sh4_handle_tcnt2_addr_w(sh4,data,mem_mask); break;
790		case SH4_TOCR_ADDR: sh4_handle_tocr_addr_w(sh4,data,mem_mask);   break; // not supported
791		case SH4_TCPR2_ADDR: sh4_handle_tcpr2_addr_w(sh4,data,mem_mask); break; // not supported
	773	case SH4_TSTR_ADDR: sh4_handle_tstr_addr_w(data,mem_mask);   break;
	774	case SH4_TCR0_ADDR: sh4_handle_tcr0_addr_w(data,mem_mask);   break;
	775	case SH4_TCR1_ADDR: sh4_handle_tcr1_addr_w(data,mem_mask);   break;
	776	case SH4_TCR2_ADDR: sh4_handle_tcr2_addr_w(data,mem_mask);   break;
	777	case SH4_TCOR0_ADDR: sh4_handle_tcor0_addr_w(data,mem_mask); break;
	778	case SH4_TCNT0_ADDR: sh4_handle_tcnt0_addr_w(data,mem_mask); break;
	779	case SH4_TCOR1_ADDR: sh4_handle_tcor1_addr_w(data,mem_mask); break;
	780	case SH4_TCNT1_ADDR: sh4_handle_tcnt1_addr_w(data,mem_mask); break;
	781	case SH4_TCOR2_ADDR: sh4_handle_tcor2_addr_w(data,mem_mask); break;
	782	case SH4_TCNT2_ADDR: sh4_handle_tcnt2_addr_w(data,mem_mask); break;
	783	case SH4_TOCR_ADDR: sh4_handle_tocr_addr_w(data,mem_mask);   break; // not supported
	784	case SH4_TCPR2_ADDR: sh4_handle_tcpr2_addr_w(data,mem_mask); break; // not supported
792	785	/*********************************************************************************************************************
793	786	INTC (Interrupt Controller)
794	787	*********************************************************************************************************************/
795	788	case ICR:
796		sh4->m[ICR] = (sh4->m[ICR] & 0x7fff) | (old & 0x8000);
	789	m_m[ICR] = (m_m[ICR] & 0x7fff) | (old & 0x8000);
797	790	break;
798		case IPRA: sh4_handler_ipra_w(sh4, data, mem_mask); break;
	791	case IPRA: sh4_handler_ipra_w(data, mem_mask); break;
799	792	case IPRB:
800		sh4->exception_priority[SH4_INTC_SCI1ERI] = INTPRI((sh4->m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1ERI);
801		sh4->exception_priority[SH4_INTC_SCI1RXI] = INTPRI((sh4->m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1RXI);
802		sh4->exception_priority[SH4_INTC_SCI1TXI] = INTPRI((sh4->m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1TXI);
803		sh4->exception_priority[SH4_INTC_SCI1TEI] = INTPRI((sh4->m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1TEI);
804		sh4->exception_priority[SH4_INTC_RCMI] = INTPRI((sh4->m[IPRB] & 0x0f00) >> 8, SH4_INTC_RCMI);
805		sh4->exception_priority[SH4_INTC_ROVI] = INTPRI((sh4->m[IPRB] & 0x0f00) >> 8, SH4_INTC_ROVI);
806		sh4->exception_priority[SH4_INTC_ITI] = INTPRI((sh4->m[IPRB] & 0xf000) >> 12, SH4_INTC_ITI);
807		sh4_exception_recompute(sh4);
	793	m_exception_priority[SH4_INTC_SCI1ERI] = INTPRI((m_m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1ERI);
	794	m_exception_priority[SH4_INTC_SCI1RXI] = INTPRI((m_m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1RXI);
	795	m_exception_priority[SH4_INTC_SCI1TXI] = INTPRI((m_m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1TXI);
	796	m_exception_priority[SH4_INTC_SCI1TEI] = INTPRI((m_m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1TEI);
	797	m_exception_priority[SH4_INTC_RCMI] = INTPRI((m_m[IPRB] & 0x0f00) >> 8, SH4_INTC_RCMI);
	798	m_exception_priority[SH4_INTC_ROVI] = INTPRI((m_m[IPRB] & 0x0f00) >> 8, SH4_INTC_ROVI);
	799	m_exception_priority[SH4_INTC_ITI] = INTPRI((m_m[IPRB] & 0xf000) >> 12, SH4_INTC_ITI);
	800	sh4_exception_recompute();
808	801	break;
809	802	case IPRC:
810		sh4->exception_priority[SH4_INTC_HUDI] = INTPRI(sh4->m[IPRC] & 0x000f, SH4_INTC_HUDI);
811		sh4->exception_priority[SH4_INTC_SCIFERI] = INTPRI((sh4->m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFERI);
812		sh4->exception_priority[SH4_INTC_SCIFRXI] = INTPRI((sh4->m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFRXI);
813		sh4->exception_priority[SH4_INTC_SCIFBRI] = INTPRI((sh4->m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFBRI);
814		sh4->exception_priority[SH4_INTC_SCIFTXI] = INTPRI((sh4->m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFTXI);
815		sh4->exception_priority[SH4_INTC_DMTE0] = INTPRI((sh4->m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE0);
816		sh4->exception_priority[SH4_INTC_DMTE1] = INTPRI((sh4->m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE1);
817		sh4->exception_priority[SH4_INTC_DMTE2] = INTPRI((sh4->m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE2);
818		sh4->exception_priority[SH4_INTC_DMTE3] = INTPRI((sh4->m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE3);
819		sh4->exception_priority[SH4_INTC_DMAE] = INTPRI((sh4->m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMAE);
820		sh4->exception_priority[SH4_INTC_GPOI] = INTPRI((sh4->m[IPRC] & 0xf000) >> 12, SH4_INTC_GPOI);
821		sh4_exception_recompute(sh4);
	803	m_exception_priority[SH4_INTC_HUDI] = INTPRI(m_m[IPRC] & 0x000f, SH4_INTC_HUDI);
	804	m_exception_priority[SH4_INTC_SCIFERI] = INTPRI((m_m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFERI);
	805	m_exception_priority[SH4_INTC_SCIFRXI] = INTPRI((m_m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFRXI);
	806	m_exception_priority[SH4_INTC_SCIFBRI] = INTPRI((m_m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFBRI);
	807	m_exception_priority[SH4_INTC_SCIFTXI] = INTPRI((m_m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFTXI);
	808	m_exception_priority[SH4_INTC_DMTE0] = INTPRI((m_m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE0);
	809	m_exception_priority[SH4_INTC_DMTE1] = INTPRI((m_m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE1);
	810	m_exception_priority[SH4_INTC_DMTE2] = INTPRI((m_m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE2);
	811	m_exception_priority[SH4_INTC_DMTE3] = INTPRI((m_m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE3);
	812	m_exception_priority[SH4_INTC_DMAE] = INTPRI((m_m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMAE);
	813	m_exception_priority[SH4_INTC_GPOI] = INTPRI((m_m[IPRC] & 0xf000) >> 12, SH4_INTC_GPOI);
	814	sh4_exception_recompute();
822	815	break;
823	816	/*********************************************************************************************************************
824	817	DMAC (DMA Controller)
825	818	*********************************************************************************************************************/
826		case SH4_SAR0_ADDR: sh4_handle_sar0_addr_w(sh4,data,mem_mask);   break;
827		case SH4_SAR1_ADDR: sh4_handle_sar1_addr_w(sh4,data,mem_mask);   break;
828		case SH4_SAR2_ADDR: sh4_handle_sar2_addr_w(sh4,data,mem_mask);   break;
829		case SH4_SAR3_ADDR: sh4_handle_sar3_addr_w(sh4,data,mem_mask);   break;
830		case SH4_DAR0_ADDR: sh4_handle_dar0_addr_w(sh4,data,mem_mask);   break;
831		case SH4_DAR1_ADDR: sh4_handle_dar1_addr_w(sh4,data,mem_mask);   break;
832		case SH4_DAR2_ADDR: sh4_handle_dar2_addr_w(sh4,data,mem_mask);   break;
833		case SH4_DAR3_ADDR: sh4_handle_dar3_addr_w(sh4,data,mem_mask);   break;
834		case SH4_DMATCR0_ADDR: sh4_handle_dmatcr0_addr_w(sh4,data,mem_mask);   break;
835		case SH4_DMATCR1_ADDR: sh4_handle_dmatcr1_addr_w(sh4,data,mem_mask);   break;
836		case SH4_DMATCR2_ADDR: sh4_handle_dmatcr2_addr_w(sh4,data,mem_mask);   break;
837		case SH4_DMATCR3_ADDR: sh4_handle_dmatcr3_addr_w(sh4,data,mem_mask);   break;
838		case SH4_CHCR0_ADDR: sh4_handle_chcr0_addr_w(sh4,data,mem_mask);   break;
839		case SH4_CHCR1_ADDR: sh4_handle_chcr1_addr_w(sh4,data,mem_mask);   break;
840		case SH4_CHCR2_ADDR: sh4_handle_chcr2_addr_w(sh4,data,mem_mask);   break;
841		case SH4_CHCR3_ADDR: sh4_handle_chcr3_addr_w(sh4,data,mem_mask);   break;
842		case SH4_DMAOR_ADDR: sh4_handle_dmaor_addr_w(sh4,data,mem_mask);   break;
	819	case SH4_SAR0_ADDR: sh4_handle_sar0_addr_w(data,mem_mask);   break;
	820	case SH4_SAR1_ADDR: sh4_handle_sar1_addr_w(data,mem_mask);   break;
	821	case SH4_SAR2_ADDR: sh4_handle_sar2_addr_w(data,mem_mask);   break;
	822	case SH4_SAR3_ADDR: sh4_handle_sar3_addr_w(data,mem_mask);   break;
	823	case SH4_DAR0_ADDR: sh4_handle_dar0_addr_w(data,mem_mask);   break;
	824	case SH4_DAR1_ADDR: sh4_handle_dar1_addr_w(data,mem_mask);   break;
	825	case SH4_DAR2_ADDR: sh4_handle_dar2_addr_w(data,mem_mask);   break;
	826	case SH4_DAR3_ADDR: sh4_handle_dar3_addr_w(data,mem_mask);   break;
	827	case SH4_DMATCR0_ADDR: sh4_handle_dmatcr0_addr_w(data,mem_mask);   break;
	828	case SH4_DMATCR1_ADDR: sh4_handle_dmatcr1_addr_w(data,mem_mask);   break;
	829	case SH4_DMATCR2_ADDR: sh4_handle_dmatcr2_addr_w(data,mem_mask);   break;
	830	case SH4_DMATCR3_ADDR: sh4_handle_dmatcr3_addr_w(data,mem_mask);   break;
	831	case SH4_CHCR0_ADDR: sh4_handle_chcr0_addr_w(data,mem_mask);   break;
	832	case SH4_CHCR1_ADDR: sh4_handle_chcr1_addr_w(data,mem_mask);   break;
	833	case SH4_CHCR2_ADDR: sh4_handle_chcr2_addr_w(data,mem_mask);   break;
	834	case SH4_CHCR3_ADDR: sh4_handle_chcr3_addr_w(data,mem_mask);   break;
	835	case SH4_DMAOR_ADDR: sh4_handle_dmaor_addr_w(data,mem_mask);   break;
843	836	/*********************************************************************************************************************
844	837	Store Queues
845	838	*********************************************************************************************************************/
r31221	r31222
850	843	I/O
851	844	*********************************************************************************************************************/
852	845	case PCTRA:
853		sh4->ioport16_pullup = 0;
854		sh4->ioport16_direction = 0;
	846	m_ioport16_pullup = 0;
	847	m_ioport16_direction = 0;
855	848	for (a=0;a < 16;a++) {
856		sh4->ioport16_direction |= (sh4->m[PCTRA] & (1 << (a*2))) >> a;
857		sh4->ioport16_pullup |= (sh4->m[PCTRA] & (1 << (a*2+1))) >> (a+1);
	849	m_ioport16_direction |= (m_m[PCTRA] & (1 << (a*2))) >> a;
	850	m_ioport16_pullup |= (m_m[PCTRA] & (1 << (a*2+1))) >> (a+1);
858	851	}
859		sh4->ioport16_direction &= 0xffff;
860		sh4->ioport16_pullup = (sh4->ioport16_pullup | sh4->ioport16_direction) ^ 0xffff;
861		if (sh4->m[BCR2] & 1)
862		sh4->io->write_dword(SH4_IOPORT_16, (UINT64)(sh4->m[PDTRA] & sh4->ioport16_direction) | ((UINT64)sh4->m[PCTRA] << 16));
	852	m_ioport16_direction &= 0xffff;
	853	m_ioport16_pullup = (m_ioport16_pullup | m_ioport16_direction) ^ 0xffff;
	854	if (m_m[BCR2] & 1)
	855	m_io->write_dword(SH4_IOPORT_16, (UINT64)(m_m[PDTRA] & m_ioport16_direction) | ((UINT64)m_m[PCTRA] << 16));
863	856	break;
864	857	case PDTRA:
865		if (sh4->m[BCR2] & 1)
866		sh4->io->write_dword(SH4_IOPORT_16, (UINT64)(sh4->m[PDTRA] & sh4->ioport16_direction) | ((UINT64)sh4->m[PCTRA] << 16));
	858	if (m_m[BCR2] & 1)
	859	m_io->write_dword(SH4_IOPORT_16, (UINT64)(m_m[PDTRA] & m_ioport16_direction) | ((UINT64)m_m[PCTRA] << 16));
867	860	break;
868	861	case PCTRB:
869		sh4->ioport4_pullup = 0;
870		sh4->ioport4_direction = 0;
	862	m_ioport4_pullup = 0;
	863	m_ioport4_direction = 0;
871	864	for (a=0;a < 4;a++) {
872		sh4->ioport4_direction |= (sh4->m[PCTRB] & (1 << (a*2))) >> a;
873		sh4->ioport4_pullup |= (sh4->m[PCTRB] & (1 << (a*2+1))) >> (a+1);
	865	m_ioport4_direction |= (m_m[PCTRB] & (1 << (a*2))) >> a;
	866	m_ioport4_pullup |= (m_m[PCTRB] & (1 << (a*2+1))) >> (a+1);
874	867	}
875		sh4->ioport4_direction &= 0xf;
876		sh4->ioport4_pullup = (sh4->ioport4_pullup | sh4->ioport4_direction) ^ 0xf;
877		if (sh4->m[BCR2] & 1)
878		sh4->io->write_dword(SH4_IOPORT_4, (sh4->m[PDTRB] & sh4->ioport4_direction) | (sh4->m[PCTRB] << 16));
	868	m_ioport4_direction &= 0xf;
	869	m_ioport4_pullup = (m_ioport4_pullup | m_ioport4_direction) ^ 0xf;
	870	if (m_m[BCR2] & 1)
	871	m_io->write_dword(SH4_IOPORT_4, (m_m[PDTRB] & m_ioport4_direction) | (m_m[PCTRB] << 16));
879	872	break;
880	873	case PDTRB:
881		if (sh4->m[BCR2] & 1)
882		sh4->io->write_dword(SH4_IOPORT_4, (sh4->m[PDTRB] & sh4->ioport4_direction) | (sh4->m[PCTRB] << 16));
	874	if (m_m[BCR2] & 1)
	875	m_io->write_dword(SH4_IOPORT_4, (m_m[PDTRB] & m_ioport4_direction) | (m_m[PCTRB] << 16));
883	876	break;
884	877
885	878	case SCBRR2:
r31221	r31222
894	887	}
895	888	}
896	889
897		READ32_MEMBER( sh4_device::sh4_internal_r )
	890	READ32_MEMBER( sh4_base_device::sh4_internal_r )
898	891	{
899		sh4_state *sh4 = get_safe_token(this);
	892	if (m_cpu_type != CPU_TYPE_SH4)
	893	fatalerror("sh4_internal_r uses m_m[] with SH3\n");
900	894
901		if (sh4->cpu_type != CPU_TYPE_SH4)
902		fatalerror("sh4_internal_r uses sh4->m[] with SH3\n");
903
904	895	UINT32 addr = (offset << 2) + 0xfe000000;
905	896	offset = ((addr & 0xfc) >> 2) | ((addr & 0x1fe0000) >> 11);
906	897
r31221	r31222
915	906	case IPRD:
916	907	return 0x00000000;  // SH7750 ignores writes here and always returns zero
917	908	case RTCNT:
918		if ((sh4->m[RTCSR] >> 3) & 7)
	909	if ((m_m[RTCSR] >> 3) & 7)
919	910	{ // activated
920		//((double)rtcnt_div[(sh4->m[RTCSR] >> 3) & 7] / (double)100000000)
921		//return (refresh_timer_base + (sh4->refresh_timer->elapsed() * (double)100000000) / (double)rtcnt_div[(sh4->m[RTCSR] >> 3) & 7]) & 0xff;
922		return compute_ticks_refresh_timer(sh4->refresh_timer, sh4->bus_clock, sh4->refresh_timer_base, rtcnt_div[(sh4->m[RTCSR] >> 3) & 7]) & 0xff;
	911	//((double)rtcnt_div[(m_m[RTCSR] >> 3) & 7] / (double)100000000)
	912	//return (refresh_timer_base + (m_refresh_timer->elapsed() * (double)100000000) / (double)rtcnt_div[(m_m[RTCSR] >> 3) & 7]) & 0xff;
	913	return compute_ticks_refresh_timer(m_refresh_timer, m_bus_clock, m_refresh_timer_base, rtcnt_div[(m_m[RTCSR] >> 3) & 7]) & 0xff;
923	914	}
924	915	else
925		return sh4->m[RTCNT];
	916	return m_m[RTCNT];
926	917
927	918	/*********************************************************************************************************************
928	919	INTC (Interrupt Controller)
929	920	*********************************************************************************************************************/
930	921
931	922	case IPRA:
932		return sh4->SH4_IPRA;
	923	return m_SH4_IPRA;
933	924
934	925	/*********************************************************************************************************************
935	926	TMU (Timer Unit)
936	927	*********************************************************************************************************************/
937		case SH4_TSTR_ADDR:  return sh4_handle_tstr_addr_r(sh4, mem_mask);
938		case SH4_TCR0_ADDR:  return sh4_handle_tcr0_addr_r(sh4, mem_mask);
939		case SH4_TCR1_ADDR:  return sh4_handle_tcr1_addr_r(sh4, mem_mask);
940		case SH4_TCR2_ADDR:  return sh4_handle_tcr2_addr_r(sh4, mem_mask);
941		case SH4_TCNT0_ADDR: return sh4_handle_tcnt0_addr_r(sh4, mem_mask);
942		case SH4_TCNT1_ADDR: return sh4_handle_tcnt1_addr_r(sh4, mem_mask);
943		case SH4_TCNT2_ADDR: return sh4_handle_tcnt2_addr_r(sh4, mem_mask);
944		case SH4_TCOR0_ADDR: return sh4_handle_tcor0_addr_r(sh4, mem_mask);
945		case SH4_TCOR1_ADDR: return sh4_handle_tcor1_addr_r(sh4, mem_mask);
946		case SH4_TCOR2_ADDR: return sh4_handle_tcor2_addr_r(sh4, mem_mask);
947		case SH4_TOCR_ADDR:  return sh4_handle_tocr_addr_r(sh4, mem_mask); // not supported
948		case SH4_TCPR2_ADDR: return sh4_handle_tcpr2_addr_r(sh4, mem_mask); // not supported
	928	case SH4_TSTR_ADDR:  return sh4_handle_tstr_addr_r(mem_mask);
	929	case SH4_TCR0_ADDR:  return sh4_handle_tcr0_addr_r(mem_mask);
	930	case SH4_TCR1_ADDR:  return sh4_handle_tcr1_addr_r(mem_mask);
	931	case SH4_TCR2_ADDR:  return sh4_handle_tcr2_addr_r(mem_mask);
	932	case SH4_TCNT0_ADDR: return sh4_handle_tcnt0_addr_r(mem_mask);
	933	case SH4_TCNT1_ADDR: return sh4_handle_tcnt1_addr_r(mem_mask);
	934	case SH4_TCNT2_ADDR: return sh4_handle_tcnt2_addr_r(mem_mask);
	935	case SH4_TCOR0_ADDR: return sh4_handle_tcor0_addr_r(mem_mask);
	936	case SH4_TCOR1_ADDR: return sh4_handle_tcor1_addr_r(mem_mask);
	937	case SH4_TCOR2_ADDR: return sh4_handle_tcor2_addr_r(mem_mask);
	938	case SH4_TOCR_ADDR:  return sh4_handle_tocr_addr_r(mem_mask); // not supported
	939	case SH4_TCPR2_ADDR: return sh4_handle_tcpr2_addr_r(mem_mask); // not supported
949	940	/*********************************************************************************************************************
950	941	DMAC (DMA Controller)
951	942	*********************************************************************************************************************/
952		case SH4_SAR0_ADDR: return sh4_handle_sar0_addr_r(sh4,mem_mask);
953		case SH4_SAR1_ADDR: return sh4_handle_sar1_addr_r(sh4,mem_mask);
954		case SH4_SAR2_ADDR: return sh4_handle_sar2_addr_r(sh4,mem_mask);
955		case SH4_SAR3_ADDR: return sh4_handle_sar3_addr_r(sh4,mem_mask);
956		case SH4_DAR0_ADDR: return sh4_handle_dar0_addr_r(sh4,mem_mask);
957		case SH4_DAR1_ADDR: return sh4_handle_dar1_addr_r(sh4,mem_mask);
958		case SH4_DAR2_ADDR: return sh4_handle_dar2_addr_r(sh4,mem_mask);
959		case SH4_DAR3_ADDR: return sh4_handle_dar3_addr_r(sh4,mem_mask);
960		case SH4_DMATCR0_ADDR: return sh4_handle_dmatcr0_addr_r(sh4,mem_mask);
961		case SH4_DMATCR1_ADDR: return sh4_handle_dmatcr1_addr_r(sh4,mem_mask);
962		case SH4_DMATCR2_ADDR: return sh4_handle_dmatcr2_addr_r(sh4,mem_mask);
963		case SH4_DMATCR3_ADDR: return sh4_handle_dmatcr3_addr_r(sh4,mem_mask);
964		case SH4_CHCR0_ADDR: return sh4_handle_chcr0_addr_r(sh4,mem_mask);
965		case SH4_CHCR1_ADDR: return sh4_handle_chcr1_addr_r(sh4,mem_mask);
966		case SH4_CHCR2_ADDR: return sh4_handle_chcr2_addr_r(sh4,mem_mask);
967		case SH4_CHCR3_ADDR: return sh4_handle_chcr3_addr_r(sh4,mem_mask);
968		case SH4_DMAOR_ADDR: return sh4_handle_dmaor_addr_r(sh4,mem_mask);
	943	case SH4_SAR0_ADDR: return sh4_handle_sar0_addr_r(mem_mask);
	944	case SH4_SAR1_ADDR: return sh4_handle_sar1_addr_r(mem_mask);
	945	case SH4_SAR2_ADDR: return sh4_handle_sar2_addr_r(mem_mask);
	946	case SH4_SAR3_ADDR: return sh4_handle_sar3_addr_r(mem_mask);
	947	case SH4_DAR0_ADDR: return sh4_handle_dar0_addr_r(mem_mask);
	948	case SH4_DAR1_ADDR: return sh4_handle_dar1_addr_r(mem_mask);
	949	case SH4_DAR2_ADDR: return sh4_handle_dar2_addr_r(mem_mask);
	950	case SH4_DAR3_ADDR: return sh4_handle_dar3_addr_r(mem_mask);
	951	case SH4_DMATCR0_ADDR: return sh4_handle_dmatcr0_addr_r(mem_mask);
	952	case SH4_DMATCR1_ADDR: return sh4_handle_dmatcr1_addr_r(mem_mask);
	953	case SH4_DMATCR2_ADDR: return sh4_handle_dmatcr2_addr_r(mem_mask);
	954	case SH4_DMATCR3_ADDR: return sh4_handle_dmatcr3_addr_r(mem_mask);
	955	case SH4_CHCR0_ADDR: return sh4_handle_chcr0_addr_r(mem_mask);
	956	case SH4_CHCR1_ADDR: return sh4_handle_chcr1_addr_r(mem_mask);
	957	case SH4_CHCR2_ADDR: return sh4_handle_chcr2_addr_r(mem_mask);
	958	case SH4_CHCR3_ADDR: return sh4_handle_chcr3_addr_r(mem_mask);
	959	case SH4_DMAOR_ADDR: return sh4_handle_dmaor_addr_r(mem_mask);
969	960	/*********************************************************************************************************************
970	961	I/O Ports
971	962	*********************************************************************************************************************/
972	963
973	964	case PDTRA:
974		if (sh4->m[BCR2] & 1)
975		return (sh4->io->read_dword(SH4_IOPORT_16) & ~sh4->ioport16_direction) | (sh4->m[PDTRA] & sh4->ioport16_direction);
	965	if (m_m[BCR2] & 1)
	966	return (m_io->read_dword(SH4_IOPORT_16) & ~m_ioport16_direction) | (m_m[PDTRA] & m_ioport16_direction);
976	967	break;
977	968	case PDTRB:
978		if (sh4->m[BCR2] & 1)
979		return (sh4->io->read_dword(SH4_IOPORT_4) & ~sh4->ioport4_direction) | (sh4->m[PDTRB] & sh4->ioport4_direction);
	969	if (m_m[BCR2] & 1)
	970	return (m_io->read_dword(SH4_IOPORT_4) & ~m_ioport4_direction) | (m_m[PDTRB] & m_ioport4_direction);
980	971	break;
981	972
982	973	// SCIF (UART with FIFO)
983	974	case SCFSR2:
984	975	return 0x60; //read-only status register
985	976	}
986		return sh4->m[offset];
	977	return m_m[offset];
987	978	}
988	979
989		void sh4_set_frt_input(device_t *device, int state)
	980	void sh34_base_device::sh4_set_frt_input(int state)
990	981	{
991		sh4_state *sh4 = get_safe_token(device);
	982	if (m_cpu_type != CPU_TYPE_SH4)
	983	fatalerror("sh4_set_frt_input uses m_m[] with SH3\n");
992	984
993		if (sh4->cpu_type != CPU_TYPE_SH4)
994		fatalerror("sh4_set_frt_input uses sh4->m[] with SH3\n");
995
996	985	if(state == PULSE_LINE)
997	986	{
998		sh4_set_frt_input(device, ASSERT_LINE);
999		sh4_set_frt_input(device, CLEAR_LINE);
	987	sh4_set_frt_input(ASSERT_LINE);
	988	sh4_set_frt_input(CLEAR_LINE);
1000	989	return;
1001	990	}
1002	991
1003		if(sh4->frt_input == state) {
	992	if(m_frt_input == state) {
1004	993	return;
1005	994	}
1006	995
1007		sh4->frt_input = state;
	996	m_frt_input = state;
1008	997
1009		if (sh4->cpu_type == CPU_TYPE_SH4)
	998	if (m_cpu_type == CPU_TYPE_SH4)
1010	999	{
1011		if(sh4->m[5] & 0x8000) {
	1000	if(m_m[5] & 0x8000) {
1012	1001	if(state == CLEAR_LINE) {
1013	1002	return;
1014	1003	}
r31221	r31222
1020	1009	}
1021	1010	else
1022	1011	{
1023		fatalerror("sh4_set_frt_input uses sh4->m[] with SH3\n");
	1012	fatalerror("sh4_set_frt_input uses m_m[] with SH3\n");
1024	1013	}
1025	1014
1026	1015	#if 0
1027	1016	sh4_timer_resync();
1028		sh4->icr = sh4->frc;
1029		sh4->m[4] |= ICF;
1030		logerror("SH4 '%s': ICF activated (%x)\n", sh4->device->tag(), sh4->pc & AM);
	1017	m_icr = m_frc;
	1018	m_m[4] |= ICF;
	1019	logerror("SH4 '%s': ICF activated (%x)\n", tag(), m_pc & AM);
1031	1020	sh4_recalc_irq();
1032	1021	#endif
1033	1022	}
1034	1023
1035		void sh4_set_irln_input(device_t *device, int value)
	1024	void sh34_base_device::sh4_set_irln_input(int value)
1036	1025	{
1037		sh4_state *sh4 = get_safe_token(device);
1038
1039		if (sh4->irln == value)
	1026	if (m_irln == value)
1040	1027	return;
1041		sh4->irln = value;
1042		device->execute().set_input_line(SH4_IRLn, ASSERT_LINE);
1043		device->execute().set_input_line(SH4_IRLn, CLEAR_LINE);
	1028	m_irln = value;
	1029	set_input_line(SH4_IRLn, ASSERT_LINE);
	1030	set_input_line(SH4_IRLn, CLEAR_LINE);
1044	1031	}
1045	1032
1046		void sh4_set_irq_line(sh4_state *sh4, int irqline, int state) // set state of external interrupt line
	1033	void sh34_base_device::execute_set_input(int irqline, int state) // set state of external interrupt line
1047	1034	{
1048		if (sh4->cpu_type == CPU_TYPE_SH3)
	1035	if (m_cpu_type == CPU_TYPE_SH3)
1049	1036	{
1050	1037	/***** ASSUME THIS TO BE WRONG FOR NOW *****/
1051	1038
r31221	r31222
1057	1044	{
1058	1045	//if (irqline > SH4_IRL3)
1059	1046	//  return;
1060		if (sh4->irq_line_state[irqline] == state)
	1047	if (m_irq_line_state[irqline] == state)
1061	1048	return;
1062		sh4->irq_line_state[irqline] = state;
	1049	m_irq_line_state[irqline] = state;
1063	1050
1064	1051	if( state == CLEAR_LINE )
1065	1052	{
1066		LOG(("SH-4 '%s' cleared external irq IRL%d\n", sh4->device->tag(), irqline));
1067		sh4_exception_unrequest(sh4, SH4_INTC_IRL0+irqline-SH4_IRL0);
	1053	LOG(("SH-4 '%s' cleared external irq IRL%d\n", tag(), irqline));
	1054	sh4_exception_unrequest(SH4_INTC_IRL0+irqline-SH4_IRL0);
1068	1055	}
1069	1056	else
1070	1057	{
1071		LOG(("SH-4 '%s' assert external irq IRL%d\n", sh4->device->tag(), irqline));
1072		sh4_exception_request(sh4, SH4_INTC_IRL0+irqline-SH4_IRL0);
	1058	LOG(("SH-4 '%s' assert external irq IRL%d\n", tag(), irqline));
	1059	sh4_exception_request(SH4_INTC_IRL0+irqline-SH4_IRL0);
1073	1060	}
1074	1061
1075	1062	}
r31221	r31222
1082	1069
1083	1070	if (irqline == INPUT_LINE_NMI)
1084	1071	{
1085		if (sh4->nmi_line_state == state)
	1072	if (m_nmi_line_state == state)
1086	1073	return;
1087		if (sh4->m[ICR] & 0x100)
	1074	if (m_m[ICR] & 0x100)
1088	1075	{
1089		if ((state == CLEAR_LINE) && (sh4->nmi_line_state == ASSERT_LINE))  // rising
	1076	if ((state == CLEAR_LINE) && (m_nmi_line_state == ASSERT_LINE))  // rising
1090	1077	{
1091		LOG(("SH-4 '%s' assert nmi\n", sh4->device->tag()));
1092		sh4_exception_request(sh4, SH4_INTC_NMI);
1093		sh4_dmac_nmi(sh4);
	1078	LOG(("SH-4 '%s' assert nmi\n", tag()));
	1079	sh4_exception_request(SH4_INTC_NMI);
	1080	sh4_dmac_nmi();
1094	1081	}
1095	1082	}
1096	1083	else
1097	1084	{
1098		if ((state == ASSERT_LINE) && (sh4->nmi_line_state == CLEAR_LINE)) // falling
	1085	if ((state == ASSERT_LINE) && (m_nmi_line_state == CLEAR_LINE)) // falling
1099	1086	{
1100		LOG(("SH-4 '%s' assert nmi\n", sh4->device->tag()));
1101		sh4_exception_request(sh4, SH4_INTC_NMI);
1102		sh4_dmac_nmi(sh4);
	1087	LOG(("SH-4 '%s' assert nmi\n", tag()));
	1088	sh4_exception_request(SH4_INTC_NMI);
	1089	sh4_dmac_nmi();
1103	1090	}
1104	1091	}
1105	1092	if (state == CLEAR_LINE)
1106		sh4->m[ICR] ^= 0x8000;
	1093	m_m[ICR] ^= 0x8000;
1107	1094	else
1108		sh4->m[ICR] |= 0x8000;
1109		sh4->nmi_line_state = state;
	1095	m_m[ICR] |= 0x8000;
	1096	m_nmi_line_state = state;
1110	1097	}
1111	1098	else
1112	1099	{
1113		if (sh4->m[ICR] & 0x80) // four independent external interrupt sources
	1100	if (m_m[ICR] & 0x80) // four independent external interrupt sources
1114	1101	{
1115	1102	if (irqline > SH4_IRL3)
1116	1103	return;
1117		if (sh4->irq_line_state[irqline] == state)
	1104	if (m_irq_line_state[irqline] == state)
1118	1105	return;
1119		sh4->irq_line_state[irqline] = state;
	1106	m_irq_line_state[irqline] = state;
1120	1107
1121	1108	if( state == CLEAR_LINE )
1122	1109	{
1123		LOG(("SH-4 '%s' cleared external irq IRL%d\n", sh4->device->tag(), irqline));
1124		sh4_exception_unrequest(sh4, SH4_INTC_IRL0+irqline-SH4_IRL0);
	1110	LOG(("SH-4 '%s' cleared external irq IRL%d\n", tag(), irqline));
	1111	sh4_exception_unrequest(SH4_INTC_IRL0+irqline-SH4_IRL0);
1125	1112	}
1126	1113	else
1127	1114	{
1128		LOG(("SH-4 '%s' assert external irq IRL%d\n", sh4->device->tag(), irqline));
1129		sh4_exception_request(sh4, SH4_INTC_IRL0+irqline-SH4_IRL0);
	1115	LOG(("SH-4 '%s' assert external irq IRL%d\n", tag(), irqline));
	1116	sh4_exception_request(SH4_INTC_IRL0+irqline-SH4_IRL0);
1130	1117	}
1131	1118	}
1132	1119	else // level-encoded interrupt
1133	1120	{
1134	1121	if (irqline != SH4_IRLn)
1135	1122	return;
1136		if ((sh4->irln > 15) || (sh4->irln < 0))
	1123	if ((m_irln > 15) || (m_irln < 0))
1137	1124	return;
1138	1125	for (s = 0; s < 15; s++)
1139		sh4_exception_unrequest(sh4, SH4_INTC_IRLn0+s);
1140		if (sh4->irln < 15)
1141		sh4_exception_request(sh4, SH4_INTC_IRLn0+sh4->irln);
1142		LOG(("SH-4 '%s' IRLn0-IRLn3 level #%d\n", sh4->device->tag(), sh4->irln));
	1126	sh4_exception_unrequest(SH4_INTC_IRLn0+s);
	1127	if (m_irln < 15)
	1128	sh4_exception_request(SH4_INTC_IRLn0+m_irln);
	1129	LOG(("SH-4 '%s' IRLn0-IRLn3 level #%d\n", tag(), m_irln));
1143	1130	}
1144	1131	}
1145		if (sh4->test_irq && (!sh4->delay))
1146		sh4_check_pending_irq(sh4, "sh4_set_irq_line");
	1132	if (m_test_irq && (!m_delay))
	1133	sh4_check_pending_irq("sh4_set_irq_line");
1147	1134	}
1148	1135	}
1149	1136
1150		void sh4_parse_configuration(sh4_state *sh4, const struct sh4_config *conf)
	1137	void sh34_base_device::sh4_parse_configuration()
1151	1138	{
1152		if(conf)
	1139	if(c_clock > 0)
1153	1140	{
1154		switch((conf->md2 << 2) | (conf->md1 << 1) | (conf->md0))
	1141	switch((c_md2 << 2) | (c_md1 << 1) | (c_md0))
1155	1142	{
1156	1143	case 0:
1157		sh4->cpu_clock = conf->clock;
1158		sh4->bus_clock = conf->clock / 4;
1159		sh4->pm_clock = conf->clock / 4;
	1144	m_cpu_clock = c_clock;
	1145	m_bus_clock = c_clock / 4;
	1146	m_pm_clock = c_clock / 4;
1160	1147	break;
1161	1148	case 1:
1162		sh4->cpu_clock = conf->clock;
1163		sh4->bus_clock = conf->clock / 6;
1164		sh4->pm_clock = conf->clock / 6;
	1149	m_cpu_clock = c_clock;
	1150	m_bus_clock = c_clock / 6;
	1151	m_pm_clock = c_clock / 6;
1165	1152	break;
1166	1153	case 2:
1167		sh4->cpu_clock = conf->clock;
1168		sh4->bus_clock = conf->clock / 3;
1169		sh4->pm_clock = conf->clock / 6;
	1154	m_cpu_clock = c_clock;
	1155	m_bus_clock = c_clock / 3;
	1156	m_pm_clock = c_clock / 6;
1170	1157	break;
1171	1158	case 3:
1172		sh4->cpu_clock = conf->clock;
1173		sh4->bus_clock = conf->clock / 3;
1174		sh4->pm_clock = conf->clock / 6;
	1159	m_cpu_clock = c_clock;
	1160	m_bus_clock = c_clock / 3;
	1161	m_pm_clock = c_clock / 6;
1175	1162	break;
1176	1163	case 4:
1177		sh4->cpu_clock = conf->clock;
1178		sh4->bus_clock = conf->clock / 2;
1179		sh4->pm_clock = conf->clock / 4;
	1164	m_cpu_clock = c_clock;
	1165	m_bus_clock = c_clock / 2;
	1166	m_pm_clock = c_clock / 4;
1180	1167	break;
1181	1168	case 5:
1182		sh4->cpu_clock = conf->clock;
1183		sh4->bus_clock = conf->clock / 2;
1184		sh4->pm_clock = conf->clock / 4;
	1169	m_cpu_clock = c_clock;
	1170	m_bus_clock = c_clock / 2;
	1171	m_pm_clock = c_clock / 4;
1185	1172	break;
1186	1173	}
1187		sh4->is_slave = (~(conf->md7)) & 1;
	1174	m_is_slave = (~(c_md7)) & 1;
1188	1175	}
1189	1176	else
1190	1177	{
1191		sh4->cpu_clock = 200000000;
1192		sh4->bus_clock = 100000000;
1193		sh4->pm_clock = 50000000;
1194		sh4->is_slave = 0;
	1178	m_cpu_clock = 200000000;
	1179	m_bus_clock = 100000000;
	1180	m_pm_clock = 50000000;
	1181	m_is_slave = 0;
1195	1182	}
1196	1183	}
1197	1184
1198		void sh4_common_init(device_t *device)
	1185	UINT32 sh34_base_device::sh4_getsqremap(UINT32 address)
1199	1186	{
1200		sh4_state *sh4 = get_safe_token(device);
1201		int i;
1202
1203		for (i=0; i<3; i++)
1204		{
1205		sh4->timer[i] = device->machine().scheduler().timer_alloc(FUNC(sh4_timer_callback), sh4);
1206		sh4->timer[i]->adjust(attotime::never, i);
1207		}
1208
1209		for (i=0; i<4; i++)
1210		{
1211		sh4->dma_timer[i] = device->machine().scheduler().timer_alloc(FUNC(sh4_dmac_callback), sh4);
1212		sh4->dma_timer[i]->adjust(attotime::never, i);
1213		}
1214
1215		sh4->refresh_timer = device->machine().scheduler().timer_alloc(FUNC(sh4_refresh_timer_callback), sh4);
1216		sh4->refresh_timer->adjust(attotime::never);
1217		sh4->refresh_timer_base = 0;
1218
1219		sh4->rtc_timer = device->machine().scheduler().timer_alloc(FUNC(sh4_rtc_timer_callback), sh4);
1220		sh4->rtc_timer->adjust(attotime::never);
1221		}
1222
1223		UINT32 sh4_getsqremap(sh4_state *sh4, UINT32 address)
1224		{
1225		if (!sh4->sh4_mmu_enabled)
	1187	if (!m_sh4_mmu_enabled)
1226	1188	return address;
1227	1189	else
1228	1190	{
r31221	r31222
1231	1193
1232	1194	for (i=0;i<64;i++)
1233	1195	{
1234		UINT32 topcmp = sh4->sh4_tlb_address[i]&0xfff00000;
	1196	UINT32 topcmp = m_sh4_tlb_address[i]&0xfff00000;
1235	1197	if (topcmp==topaddr)
1236		return (address&0x000fffff) | ((sh4->sh4_tlb_data[i])&0xfff00000);
	1198	return (address&0x000fffff) | ((m_sh4_tlb_data[i])&0xfff00000);
1237	1199	}
1238	1200
1239	1201	}
r31221	r31222
1241	1203	return address;
1242	1204	}
1243	1205
1244		READ64_MEMBER( sh4_device::sh4_tlb_r )
	1206	READ64_MEMBER( sh4_base_device::sh4_tlb_r )
1245	1207	{
1246		sh4_state *sh4 = get_safe_token(this);
1247
1248	1208	int offs = offset*8;
1249	1209
1250	1210	if (offs >= 0x01000000)
1251	1211	{
1252	1212	UINT8 i = (offs>>8)&63;
1253		return sh4->sh4_tlb_data[i];
	1213	return m_sh4_tlb_data[i];
1254	1214	}
1255	1215	else
1256	1216	{
1257	1217	UINT8 i = (offs>>8)&63;
1258		return sh4->sh4_tlb_address[i];
	1218	return m_sh4_tlb_address[i];
1259	1219	}
1260	1220	}
1261	1221
1262		WRITE64_MEMBER( sh4_device::sh4_tlb_w )
	1222	WRITE64_MEMBER( sh4_base_device::sh4_tlb_w )
1263	1223	{
1264		sh4_state *sh4 = get_safe_token(this);
1265
1266	1224	int offs = offset*8;
1267	1225
1268	1226	if (offs >= 0x01000000)
1269	1227	{
1270	1228	UINT8 i = (offs>>8)&63;
1271		sh4->sh4_tlb_data[i]  = data&0xffffffff;
	1229	m_sh4_tlb_data[i]  = data&0xffffffff;
1272	1230	}
1273	1231	else
1274	1232	{
1275	1233	UINT8 i = (offs>>8)&63;
1276		sh4->sh4_tlb_address[i] = data&0xffffffff;
	1234	m_sh4_tlb_address[i] = data&0xffffffff;
1277	1235	}
1278	1236	}

trunk/src/emu/cpu/sh4/sh4.c

r31221	r31222
30	30	#include "sh3comn.h"
31	31	#include "sh4tmu.h"
32	32
33		#ifndef USE_SH4DRC
34	33
35	34	CPU_DISASSEMBLE( sh4 );
36	35	CPU_DISASSEMBLE( sh4be );
37	36
38		typedef const void (*sh4ophandler)(sh4_state*, const UINT16);
39	37
40		sh4ophandler master_ophandler_table[0x10000];
41		void sh4_build_optable(sh4_state* sh4);
	38	const device_type SH3LE = &device_creator<sh3_device>;
	39	const device_type SH3BE = &device_creator<sh3be_device>;
	40	const device_type SH4LE = &device_creator<sh4_device>;
	41	const device_type SH4BE = &device_creator<sh4be_device>;
42	42
43	43
	44	#if 0
	45	/*When OC index mode is off (CCR.OIX = 0)*/
	46	static ADDRESS_MAP_START( sh4_internal_map, AS_PROGRAM, 64, sh4_base_device )
	47	AM_RANGE(0x1C000000, 0x1C000FFF) AM_RAM AM_MIRROR(0x03FFD000)
	48	AM_RANGE(0x1C002000, 0x1C002FFF) AM_RAM AM_MIRROR(0x03FFD000)
	49	AM_RANGE(0xE0000000, 0xE000003F) AM_RAM AM_MIRROR(0x03FFFFC0)
	50	ADDRESS_MAP_END
	51	#endif
	52
	53	/*When OC index mode is on (CCR.OIX = 1)*/
	54	static ADDRESS_MAP_START( sh4_internal_map, AS_PROGRAM, 64, sh4_base_device )
	55	AM_RANGE(0x1C000000, 0x1C000FFF) AM_RAM AM_MIRROR(0x01FFF000)
	56	AM_RANGE(0x1E000000, 0x1E000FFF) AM_RAM AM_MIRROR(0x01FFF000)
	57	AM_RANGE(0xE0000000, 0xE000003F) AM_RAM AM_MIRROR(0x03FFFFC0) // todo: store queues should be write only on DC's SH4, executing PREFM shouldn't cause an actual memory read access!
	58	AM_RANGE(0xF6000000, 0xF7FFFFFF) AM_READWRITE(sh4_tlb_r,sh4_tlb_w)
	59	AM_RANGE(0xFE000000, 0xFFFFFFFF) AM_READWRITE32(sh4_internal_r, sh4_internal_w, U64(0xffffffffffffffff))
	60	ADDRESS_MAP_END
	61
	62	static ADDRESS_MAP_START( sh3_internal_map, AS_PROGRAM, 64, sh3_base_device )
	63	AM_RANGE(SH3_LOWER_REGBASE, SH3_LOWER_REGEND) AM_READWRITE32(sh3_internal_r, sh3_internal_w, U64(0xffffffffffffffff))
	64	AM_RANGE(SH3_UPPER_REGBASE, SH3_UPPER_REGEND) AM_READWRITE32(sh3_internal_high_r, sh3_internal_high_w, U64(0xffffffffffffffff))
	65	ADDRESS_MAP_END
	66
	67
	68	sh34_base_device::sh34_base_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, endianness_t endianness, address_map_constructor internal)
	69	: cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__)
	70	, m_program_config("program", endianness, 64, 32, 0, internal)
	71	, m_io_config("io", endianness, 64, 8)
	72	, c_md2(0)
	73	, c_md1(0)
	74	, c_md0(0)
	75	, c_md6(0)
	76	, c_md4(0)
	77	, c_md3(0)
	78	, c_md5(0)
	79	, c_md7(0)
	80	, c_md8(0)
	81	, c_clock(0)
	82	{
	83	}
	84
	85
	86	sh3_base_device::sh3_base_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, endianness_t endianness)
	87	: sh34_base_device(mconfig, type, name, tag, owner, clock, shortname, endianness, ADDRESS_MAP_NAME(sh3_internal_map))
	88	{
	89	m_cpu_type = CPU_TYPE_SH3;
	90	}
	91
	92
	93	sh4_base_device::sh4_base_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, endianness_t endianness)
	94	: sh34_base_device(mconfig, type, name, tag, owner, clock, shortname, endianness, ADDRESS_MAP_NAME(sh4_internal_map))
	95	{
	96	m_cpu_type = CPU_TYPE_SH4;
	97	}
	98
	99
	100	sh3_device::sh3_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	101	: sh3_base_device(mconfig, SH3LE, "SH-3 (little)", tag, owner, clock, "sh3", ENDIANNESS_LITTLE)
	102	{
	103	}
	104
	105
	106	sh3be_device::sh3be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	107	: sh3_base_device(mconfig, SH3BE, "SH-3 (big)", tag, owner, clock, "sh3be", ENDIANNESS_BIG)
	108	{
	109	}
	110
	111
	112	sh4_device::sh4_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	113	: sh4_base_device(mconfig, SH4LE, "SH-4 (little)", tag, owner, clock, "sh4", ENDIANNESS_LITTLE)
	114	{
	115	}
	116
	117
	118	sh4be_device::sh4be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	119	: sh4_base_device(mconfig, SH4BE, "SH-4 (big)", tag, owner, clock, "sh4be", ENDIANNESS_BIG)
	120	{
	121	}
	122
	123
	124	offs_t sh34_base_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
	125	{
	126	extern CPU_DISASSEMBLE( sh4 );
	127
	128	return CPU_DISASSEMBLE_NAME(sh4)(this, buffer, pc, oprom, opram, options);
	129	}
	130
	131
	132	offs_t sh3be_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
	133	{
	134	extern CPU_DISASSEMBLE( sh4be );
	135
	136	return CPU_DISASSEMBLE_NAME(sh4be)(this, buffer, pc, oprom, opram, options);
	137	}
	138
	139
	140	offs_t sh4be_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
	141	{
	142	extern CPU_DISASSEMBLE( sh4be );
	143
	144	return CPU_DISASSEMBLE_NAME(sh4be)(this, buffer, pc, oprom, opram, options);
	145	}
	146
	147
44	148	/* Called for unimplemented opcodes */
45		const void TODO(sh4_state *sh4, const UINT16 opcode)
	149	void sh34_base_device::TODO(const UINT16 opcode)
46	150	{
47	151	}
48	152
49	153	#if 0
50	154	int sign_of(int n)
51	155	{
52		return(sh4->fr[n]>>31);
	156	return(m_fr[n]>>31);
53	157	}
54	158
55	159	void zero(int n,int sign)
56	160	{
57	161	if (sign == 0)
58		sh4->fr[n] = 0x00000000;
	162	m_fr[n] = 0x00000000;
59	163	else
60		sh4->fr[n] = 0x80000000;
61		if ((sh4->fpscr & PR) == 1)
62		sh4->fr[n+1] = 0x00000000;
	164	m_fr[n] = 0x80000000;
	165	if ((m_fpscr & PR) == 1)
	166	m_fr[n+1] = 0x00000000;
63	167	}
64	168
65	169	int data_type_of(int n)
66	170	{
67	171	UINT32 abs;
68	172
69		abs = sh4->fr[n] & 0x7fffffff;
70		if ((sh4->fpscr & PR) == 0) { /* Single-precision */
	173	abs = m_fr[n] & 0x7fffffff;
	174	if ((m_fpscr & PR) == 0) { /* Single-precision */
71	175	if (abs < 0x00800000) {
72		if (((sh4->fpscr & DN) == 1) || (abs == 0x00000000)) {
	176	if (((m_fpscr & DN) == 1) || (abs == 0x00000000)) {
73	177	if (sign_of(n) == 0) {
74	178	zero(n, 0);
75	179	return(SH4_FPU_PZERO);
r31221	r31222
95	199	return(SH4_FPU_sNaN);
96	200	} else { /* Double-precision */
97	201	if (abs < 0x00100000) {
98		if (((sh4->fpscr & DN) == 1) || ((abs == 0x00000000) && (sh4->fr[n+1] == 0x00000000))) {
	202	if (((m_fpscr & DN) == 1) || ((abs == 0x00000000) && (m_fr[n+1] == 0x00000000))) {
99	203	if(sign_of(n) == 0) {
100	204	zero(n, 0);
101	205	return(SH4_FPU_PZERO);
r31221	r31222
109	213	if (abs < 0x7ff00000)
110	214	return(SH4_FPU_NORM);
111	215	else
112		if ((abs == 0x7ff00000) && (sh4->fr[n+1] == 0x00000000)) {
	216	if ((abs == 0x7ff00000) && (m_fr[n+1] == 0x00000000)) {
113	217	if (sign_of(n) == 0)
114	218	return(SH4_FPU_PINF);
115	219	else
r31221	r31222
124	228	}
125	229	#endif
126	230
127		const UINT8 RB(sh4_state *sh4, offs_t A)
	231	UINT8 sh34_base_device::RB(offs_t A)
128	232	{
129	233	if (A >= 0xe0000000)
130		return sh4->program->read_byte(A);
	234	return m_program->read_byte(A);
131	235
132		return sh4->program->read_byte(A & AM);
	236	return m_program->read_byte(A & AM);
133	237	}
134	238
135		const UINT16 RW(sh4_state *sh4, offs_t A)
	239	UINT16 sh34_base_device::RW(offs_t A)
136	240	{
137	241	if (A >= 0xe0000000)
138		return sh4->program->read_word(A);
	242	return m_program->read_word(A);
139	243
140		return sh4->program->read_word(A & AM);
	244	return m_program->read_word(A & AM);
141	245	}
142	246
143		const UINT32 RL(sh4_state *sh4, offs_t A)
	247	UINT32 sh34_base_device::RL(offs_t A)
144	248	{
145	249	if (A >= 0xe0000000)
146		return sh4->program->read_dword(A);
	250	return m_program->read_dword(A);
147	251
148		return sh4->program->read_dword(A & AM);
	252	return m_program->read_dword(A & AM);
149	253	}
150	254
151		const void WB(sh4_state *sh4, offs_t A, UINT8 V)
	255	void sh34_base_device::WB(offs_t A, UINT8 V)
152	256	{
153	257	if (A >= 0xe0000000)
154	258	{
155		sh4->program->write_byte(A,V);
	259	m_program->write_byte(A,V);
156	260	return;
157	261	}
158	262
159		sh4->program->write_byte(A & AM,V);
	263	m_program->write_byte(A & AM,V);
160	264	}
161	265
162		const void WW(sh4_state *sh4, offs_t A, UINT16 V)
	266	void sh34_base_device::WW(offs_t A, UINT16 V)
163	267	{
164	268	if (A >= 0xe0000000)
165	269	{
166		sh4->program->write_word(A,V);
	270	m_program->write_word(A,V);
167	271	return;
168	272	}
169	273
170		sh4->program->write_word(A & AM,V);
	274	m_program->write_word(A & AM,V);
171	275	}
172	276
173		const void WL(sh4_state *sh4, offs_t A, UINT32 V)
	277	void sh34_base_device::WL(offs_t A, UINT32 V)
174	278	{
175	279	if (A >= 0xe0000000)
176	280	{
177		sh4->program->write_dword(A,V);
	281	m_program->write_dword(A,V);
178	282	return;
179	283	}
180	284
181		sh4->program->write_dword(A & AM,V);
	285	m_program->write_dword(A & AM,V);
182	286	}
183	287
184	288	/*  code                 cycles  t-bit
185	289	*  0011 nnnn mmmm 1100  1       -
186	290	*  ADD     Rm,Rn
187	291	*/
188		const void ADD(sh4_state *sh4, const UINT16 opcode)
	292	void sh34_base_device::ADD(const UINT16 opcode)
189	293	{
190		sh4->r[Rn] += sh4->r[Rm];
	294	m_r[Rn] += m_r[Rm];
191	295	}
192	296
193	297	/*  code                 cycles  t-bit
194	298	*  0111 nnnn iiii iiii  1       -
195	299	*  ADD     #imm,Rn
196	300	*/
197		const void ADDI(sh4_state *sh4, const UINT16 opcode)
	301	void sh34_base_device::ADDI(const UINT16 opcode)
198	302	{
199		sh4->r[Rn] += (INT32)(INT16)(INT8)(opcode&0xff);
	303	m_r[Rn] += (INT32)(INT16)(INT8)(opcode&0xff);
200	304	}
201	305
202	306	/*  code                 cycles  t-bit
203	307	*  0011 nnnn mmmm 1110  1       carry
204	308	*  ADDC    Rm,Rn
205	309	*/
206		const void ADDC(sh4_state *sh4, const UINT16 opcode)
	310	void sh34_base_device::ADDC(const UINT16 opcode)
207	311	{
208	312	UINT32 m = Rm; UINT32 n = Rn;
209	313	UINT32 tmp0, tmp1;
210	314
211		tmp1 = sh4->r[n] + sh4->r[m];
212		tmp0 = sh4->r[n];
213		sh4->r[n] = tmp1 + (sh4->sr & T);
	315	tmp1 = m_r[n] + m_r[m];
	316	tmp0 = m_r[n];
	317	m_r[n] = tmp1 + (m_sr & T);
214	318	if (tmp0 > tmp1)
215		sh4->sr |= T;
	319	m_sr |= T;
216	320	else
217		sh4->sr &= ~T;
218		if (tmp1 > sh4->r[n])
219		sh4->sr |= T;
	321	m_sr &= ~T;
	322	if (tmp1 > m_r[n])
	323	m_sr |= T;
220	324	}
221	325
222	326	/*  code                 cycles  t-bit
223	327	*  0011 nnnn mmmm 1111  1       overflow
224	328	*  ADDV    Rm,Rn
225	329	*/
226		const void ADDV(sh4_state *sh4, const UINT16 opcode)
	330	void sh34_base_device::ADDV(const UINT16 opcode)
227	331	{
228	332	UINT32 m = Rm; UINT32 n = Rn;
229	333	INT32 dest, src, ans;
230	334
231		if ((INT32) sh4->r[n] >= 0)
	335	if ((INT32) m_r[n] >= 0)
232	336	dest = 0;
233	337	else
234	338	dest = 1;
235		if ((INT32) sh4->r[m] >= 0)
	339	if ((INT32) m_r[m] >= 0)
236	340	src = 0;
237	341	else
238	342	src = 1;
239	343	src += dest;
240		sh4->r[n] += sh4->r[m];
241		if ((INT32) sh4->r[n] >= 0)
	344	m_r[n] += m_r[m];
	345	if ((INT32) m_r[n] >= 0)
242	346	ans = 0;
243	347	else
244	348	ans = 1;
r31221	r31222
246	350	if (src == 0 || src == 2)
247	351	{
248	352	if (ans == 1)
249		sh4->sr |= T;
	353	m_sr |= T;
250	354	else
251		sh4->sr &= ~T;
	355	m_sr &= ~T;
252	356	}
253	357	else
254		sh4->sr &= ~T;
	358	m_sr &= ~T;
255	359	}
256	360
257	361	/*  code                 cycles  t-bit
258	362	*  0010 nnnn mmmm 1001  1       -
259	363	*  AND     Rm,Rn
260	364	*/
261		const void AND(sh4_state *sh4, const UINT16 opcode)
	365	void sh34_base_device::AND(const UINT16 opcode)
262	366	{
263		sh4->r[Rn] &= sh4->r[Rm];
	367	m_r[Rn] &= m_r[Rm];
264	368	}
265	369
266	370
r31221	r31222
268	372	*  1100 1001 iiii iiii  1       -
269	373	*  AND     #imm,R0
270	374	*/
271		const void ANDI(sh4_state *sh4, const UINT16 opcode)
	375	void sh34_base_device::ANDI(const UINT16 opcode)
272	376	{
273		sh4->r[0] &= (opcode&0xff);
	377	m_r[0] &= (opcode&0xff);
274	378	}
275	379
276	380	/*  code                 cycles  t-bit
277	381	*  1100 1101 iiii iiii  1       -
278	382	*  AND.B   #imm,@(R0,GBR)
279	383	*/
280		const void ANDM(sh4_state *sh4, const UINT16 opcode)
	384	void sh34_base_device::ANDM(const UINT16 opcode)
281	385	{
282	386	UINT32 temp;
283	387
284		sh4->ea = sh4->gbr + sh4->r[0];
285		temp = (opcode&0xff) & RB(sh4,  sh4->ea );
286		WB(sh4, sh4->ea, temp );
287		sh4->sh4_icount -= 2;
	388	m_ea = m_gbr + m_r[0];
	389	temp = (opcode&0xff) & RB( m_ea );
	390	WB(m_ea, temp );
	391	m_sh4_icount -= 2;
288	392	}
289	393
290	394	/*  code                 cycles  t-bit
291	395	*  1000 1011 dddd dddd  3/1     -
292	396	*  BF      disp8
293	397	*/
294		const void BF(sh4_state *sh4, const UINT16 opcode)
	398	void sh34_base_device::BF(const UINT16 opcode)
295	399	{
296		if ((sh4->sr & T) == 0)
	400	if ((m_sr & T) == 0)
297	401	{
298	402	INT32 disp = ((INT32)(opcode&0xff) << 24) >> 24;
299		sh4->pc = sh4->ea = sh4->pc + disp * 2 + 2;
300		sh4->sh4_icount -= 2;
	403	m_pc = m_ea = m_pc + disp * 2 + 2;
	404	m_sh4_icount -= 2;
301	405	}
302	406	}
303	407
r31221	r31222
305	409	*  1000 1111 dddd dddd  3/1     -
306	410	*  BFS     disp8
307	411	*/
308		const void BFS(sh4_state *sh4, const UINT16 opcode)
	412	void sh34_base_device::BFS(const UINT16 opcode)
309	413	{
310		if ((sh4->sr & T) == 0)
	414	if ((m_sr & T) == 0)
311	415	{
312	416	INT32 disp = ((INT32)(opcode&0xff) << 24) >> 24;
313		sh4->delay = sh4->pc;
314		sh4->pc = sh4->ea = sh4->pc + disp * 2 + 2;
315		sh4->sh4_icount--;
	417	m_delay = m_pc;
	418	m_pc = m_ea = m_pc + disp * 2 + 2;
	419	m_sh4_icount--;
316	420	}
317	421	}
318	422
r31221	r31222
320	424	*  1010 dddd dddd dddd  2       -
321	425	*  BRA     disp12
322	426	*/
323		const void BRA(sh4_state *sh4, const UINT16 opcode)
	427	void sh34_base_device::BRA(const UINT16 opcode)
324	428	{
325	429	INT32 disp = ((INT32)(opcode&0xfff) << 20) >> 20;
326	430
327	431	#if BUSY_LOOP_HACKS
328	432	if (disp == -2)
329	433	{
330		UINT32 next_opcode = RW(sh4,sh4->ppc & AM);
	434	UINT32 next_opcode = RW(m_ppc & AM);
331	435	/* BRA  $
332	436	* NOP
333	437	*/
334	438	if (next_opcode == 0x0009)
335		sh4->sh4_icount %= 3;   /* cycles for BRA $ and NOP taken (3) */
	439	m_sh4_icount %= 3;   /* cycles for BRA $ and NOP taken (3) */
336	440	}
337	441	#endif
338		sh4->delay = sh4->pc;
339		sh4->pc = sh4->ea = sh4->pc + disp * 2 + 2;
340		sh4->sh4_icount--;
	442	m_delay = m_pc;
	443	m_pc = m_ea = m_pc + disp * 2 + 2;
	444	m_sh4_icount--;
341	445	}
342	446
343	447	/*  code                 cycles  t-bit
344	448	*  0000 mmmm 0010 0011  2       -
345	449	*  BRAF    Rm
346	450	*/
347		const void BRAF(sh4_state *sh4, const UINT16 opcode)
	451	void sh34_base_device::BRAF(const UINT16 opcode)
348	452	{
349		sh4->delay = sh4->pc;
350		sh4->pc += sh4->r[Rn] + 2;
351		sh4->sh4_icount--;
	453	m_delay = m_pc;
	454	m_pc += m_r[Rn] + 2;
	455	m_sh4_icount--;
352	456	}
353	457
354	458	/*  code                 cycles  t-bit
355	459	*  1011 dddd dddd dddd  2       -
356	460	*  BSR     disp12
357	461	*/
358		const void BSR(sh4_state *sh4, const UINT16 opcode)
	462	void sh34_base_device::BSR(const UINT16 opcode)
359	463	{
360	464	INT32 disp = ((INT32)(opcode&0xfff) << 20) >> 20;
361	465
362		sh4->pr = sh4->pc + 2;
363		sh4->delay = sh4->pc;
364		sh4->pc = sh4->ea = sh4->pc + disp * 2 + 2;
365		sh4->sh4_icount--;
	466	m_pr = m_pc + 2;
	467	m_delay = m_pc;
	468	m_pc = m_ea = m_pc + disp * 2 + 2;
	469	m_sh4_icount--;
366	470	}
367	471
368	472	/*  code                 cycles  t-bit
369	473	*  0000 mmmm 0000 0011  2       -
370	474	*  BSRF    Rm
371	475	*/
372		const void BSRF(sh4_state *sh4, const UINT16 opcode)
	476	void sh34_base_device::BSRF(const UINT16 opcode)
373	477	{
374		sh4->pr = sh4->pc + 2;
375		sh4->delay = sh4->pc;
376		sh4->pc += sh4->r[Rn] + 2;
377		sh4->sh4_icount--;
	478	m_pr = m_pc + 2;
	479	m_delay = m_pc;
	480	m_pc += m_r[Rn] + 2;
	481	m_sh4_icount--;
378	482	}
379	483
380	484	/*  code                 cycles  t-bit
381	485	*  1000 1001 dddd dddd  3/1     -
382	486	*  BT      disp8
383	487	*/
384		const void BT(sh4_state *sh4, const UINT16 opcode)
	488	void sh34_base_device::BT(const UINT16 opcode)
385	489	{
386		if ((sh4->sr & T) != 0)
	490	if ((m_sr & T) != 0)
387	491	{
388	492	INT32 disp = ((INT32)(opcode&0xff) << 24) >> 24;
389		sh4->pc = sh4->ea = sh4->pc + disp * 2 + 2;
390		sh4->sh4_icount -= 2;
	493	m_pc = m_ea = m_pc + disp * 2 + 2;
	494	m_sh4_icount -= 2;
391	495	}
392	496	}
393	497
r31221	r31222
395	499	*  1000 1101 dddd dddd  2/1     -
396	500	*  BTS     disp8
397	501	*/
398		const void BTS(sh4_state *sh4, const UINT16 opcode)
	502	void sh34_base_device::BTS(const UINT16 opcode)
399	503	{
400		if ((sh4->sr & T) != 0)
	504	if ((m_sr & T) != 0)
401	505	{
402	506	INT32 disp = ((INT32)(opcode&0xff) << 24) >> 24;
403		sh4->delay = sh4->pc;
404		sh4->pc = sh4->ea = sh4->pc + disp * 2 + 2;
405		sh4->sh4_icount--;
	507	m_delay = m_pc;
	508	m_pc = m_ea = m_pc + disp * 2 + 2;
	509	m_sh4_icount--;
406	510	}
407	511	}
408	512
r31221	r31222
410	514	*  0000 0000 0010 1000  1       -
411	515	*  CLRMAC
412	516	*/
413		const void CLRMAC(sh4_state *sh4, const UINT16 opcode)
	517	void sh34_base_device::CLRMAC(const UINT16 opcode)
414	518	{
415		sh4->mach = 0;
416		sh4->macl = 0;
	519	m_mach = 0;
	520	m_macl = 0;
417	521	}
418	522
419	523	/*  code                 cycles  t-bit
420	524	*  0000 0000 0000 1000  1       -
421	525	*  CLRT
422	526	*/
423		const void CLRT(sh4_state *sh4, const UINT16 opcode)
	527	void sh34_base_device::CLRT(const UINT16 opcode)
424	528	{
425		sh4->sr &= ~T;
	529	m_sr &= ~T;
426	530	}
427	531
428	532	/*  code                 cycles  t-bit
429	533	*  0011 nnnn mmmm 0000  1       comparison result
430	534	*  CMP_EQ  Rm,Rn
431	535	*/
432		const void CMPEQ(sh4_state *sh4, const UINT16 opcode)
	536	void sh34_base_device::CMPEQ(const UINT16 opcode)
433	537	{
434		if (sh4->r[Rn] == sh4->r[Rm])
435		sh4->sr |= T;
	538	if (m_r[Rn] == m_r[Rm])
	539	m_sr |= T;
436	540	else
437		sh4->sr &= ~T;
	541	m_sr &= ~T;
438	542	}
439	543
440	544	/*  code                 cycles  t-bit
441	545	*  0011 nnnn mmmm 0011  1       comparison result
442	546	*  CMP_GE  Rm,Rn
443	547	*/
444		const void CMPGE(sh4_state *sh4, const UINT16 opcode)
	548	void sh34_base_device::CMPGE(const UINT16 opcode)
445	549	{
446		if ((INT32) sh4->r[Rn] >= (INT32) sh4->r[Rm])
447		sh4->sr |= T;
	550	if ((INT32) m_r[Rn] >= (INT32) m_r[Rm])
	551	m_sr |= T;
448	552	else
449		sh4->sr &= ~T;
	553	m_sr &= ~T;
450	554	}
451	555
452	556	/*  code                 cycles  t-bit
453	557	*  0011 nnnn mmmm 0111  1       comparison result
454	558	*  CMP_GT  Rm,Rn
455	559	*/
456		const void CMPGT(sh4_state *sh4, const UINT16 opcode)
	560	void sh34_base_device::CMPGT(const UINT16 opcode)
457	561	{
458		if ((INT32) sh4->r[Rn] > (INT32) sh4->r[Rm])
459		sh4->sr |= T;
	562	if ((INT32) m_r[Rn] > (INT32) m_r[Rm])
	563	m_sr |= T;
460	564	else
461		sh4->sr &= ~T;
	565	m_sr &= ~T;
462	566	}
463	567
464	568	/*  code                 cycles  t-bit
465	569	*  0011 nnnn mmmm 0110  1       comparison result
466	570	*  CMP_HI  Rm,Rn
467	571	*/
468		const void CMPHI(sh4_state *sh4, const UINT16 opcode)
	572	void sh34_base_device::CMPHI(const UINT16 opcode)
469	573	{
470		if ((UINT32) sh4->r[Rn] > (UINT32) sh4->r[Rm])
471		sh4->sr |= T;
	574	if ((UINT32) m_r[Rn] > (UINT32) m_r[Rm])
	575	m_sr |= T;
472	576	else
473		sh4->sr &= ~T;
	577	m_sr &= ~T;
474	578	}
475	579
476	580	/*  code                 cycles  t-bit
477	581	*  0011 nnnn mmmm 0010  1       comparison result
478	582	*  CMP_HS  Rm,Rn
479	583	*/
480		const void CMPHS(sh4_state *sh4, const UINT16 opcode)
	584	void sh34_base_device::CMPHS(const UINT16 opcode)
481	585	{
482		if ((UINT32) sh4->r[Rn] >= (UINT32) sh4->r[Rm])
483		sh4->sr |= T;
	586	if ((UINT32) m_r[Rn] >= (UINT32) m_r[Rm])
	587	m_sr |= T;
484	588	else
485		sh4->sr &= ~T;
	589	m_sr &= ~T;
486	590	}
487	591
488	592
r31221	r31222
490	594	*  0100 nnnn 0001 0101  1       comparison result
491	595	*  CMP_PL  Rn
492	596	*/
493		const void CMPPL(sh4_state *sh4, const UINT16 opcode)
	597	void sh34_base_device::CMPPL(const UINT16 opcode)
494	598	{
495		if ((INT32) sh4->r[Rn] > 0)
496		sh4->sr |= T;
	599	if ((INT32) m_r[Rn] > 0)
	600	m_sr |= T;
497	601	else
498		sh4->sr &= ~T;
	602	m_sr &= ~T;
499	603	}
500	604
501	605	/*  code                 cycles  t-bit
502	606	*  0100 nnnn 0001 0001  1       comparison result
503	607	*  CMP_PZ  Rn
504	608	*/
505		const void CMPPZ(sh4_state *sh4, const UINT16 opcode)
	609	void sh34_base_device::CMPPZ(const UINT16 opcode)
506	610	{
507		if ((INT32) sh4->r[Rn] >= 0)
508		sh4->sr |= T;
	611	if ((INT32) m_r[Rn] >= 0)
	612	m_sr |= T;
509	613	else
510		sh4->sr &= ~T;
	614	m_sr &= ~T;
511	615	}
512	616
513	617	/*  code                 cycles  t-bit
514	618	*  0010 nnnn mmmm 1100  1       comparison result
515	619	* CMP_STR  Rm,Rn
516	620	*/
517		const void CMPSTR(sh4_state *sh4, const UINT16 opcode)
	621	void sh34_base_device::CMPSTR(const UINT16 opcode)
518	622	{
519	623	UINT32 temp;
520	624	INT32 HH, HL, LH, LL;
521		temp = sh4->r[Rn] ^ sh4->r[Rm];
	625	temp = m_r[Rn] ^ m_r[Rm];
522	626	HH = (temp >> 24) & 0xff;
523	627	HL = (temp >> 16) & 0xff;
524	628	LH = (temp >> 8) & 0xff;
525	629	LL = temp & 0xff;
526	630	if (HH && HL && LH && LL)
527		sh4->sr &= ~T;
	631	m_sr &= ~T;
528	632	else
529		sh4->sr |= T;
	633	m_sr |= T;
530	634	}
531	635
532	636
r31221	r31222
534	638	*  1000 1000 iiii iiii  1       comparison result
535	639	*  CMP/EQ #imm,R0
536	640	*/
537		const void CMPIM(sh4_state *sh4, const UINT16 opcode)
	641	void sh34_base_device::CMPIM(const UINT16 opcode)
538	642	{
539	643	UINT32 imm = (UINT32)(INT32)(INT16)(INT8)(opcode&0xff);
540	644
541		if (sh4->r[0] == imm)
542		sh4->sr |= T;
	645	if (m_r[0] == imm)
	646	m_sr |= T;
543	647	else
544		sh4->sr &= ~T;
	648	m_sr &= ~T;
545	649	}
546	650
547	651	/*  code                 cycles  t-bit
548	652	*  0010 nnnn mmmm 0111  1       calculation result
549	653	*  DIV0S   Rm,Rn
550	654	*/
551		const void DIV0S(sh4_state *sh4, const UINT16 opcode)
	655	void sh34_base_device::DIV0S(const UINT16 opcode)
552	656	{
553	657	UINT32 m = Rm; UINT32 n = Rn;
554	658
555		if ((sh4->r[n] & 0x80000000) == 0)
556		sh4->sr &= ~Q;
	659	if ((m_r[n] & 0x80000000) == 0)
	660	m_sr &= ~Q;
557	661	else
558		sh4->sr |= Q;
559		if ((sh4->r[m] & 0x80000000) == 0)
560		sh4->sr &= ~M;
	662	m_sr |= Q;
	663	if ((m_r[m] & 0x80000000) == 0)
	664	m_sr &= ~M;
561	665	else
562		sh4->sr |= M;
563		if ((sh4->r[m] ^ sh4->r[n]) & 0x80000000)
564		sh4->sr |= T;
	666	m_sr |= M;
	667	if ((m_r[m] ^ m_r[n]) & 0x80000000)
	668	m_sr |= T;
565	669	else
566		sh4->sr &= ~T;
	670	m_sr &= ~T;
567	671	}
568	672
569	673	/*  code                 cycles  t-bit
570	674	*  0000 0000 0001 1001  1       0
571	675	*  DIV0U
572	676	*/
573		const void DIV0U(sh4_state *sh4, const UINT16 opcode)
	677	void sh34_base_device::DIV0U(const UINT16 opcode)
574	678	{
575		sh4->sr &= ~(M | Q | T);
	679	m_sr &= ~(M | Q | T);
576	680	}
577	681
578	682	/*  code                 cycles  t-bit
579	683	*  0011 nnnn mmmm 0100  1       calculation result
580	684	*  DIV1 Rm,Rn
581	685	*/
582		const void DIV1(sh4_state *sh4, const UINT16 opcode)
	686	void sh34_base_device::DIV1(const UINT16 opcode)
583	687	{
584	688	UINT32 m = Rm; UINT32 n = Rn;
585	689
586	690	UINT32 tmp0;
587	691	UINT32 old_q;
588	692
589		old_q = sh4->sr & Q;
590		if (0x80000000 & sh4->r[n])
591		sh4->sr |= Q;
	693	old_q = m_sr & Q;
	694	if (0x80000000 & m_r[n])
	695	m_sr |= Q;
592	696	else
593		sh4->sr &= ~Q;
	697	m_sr &= ~Q;
594	698
595		sh4->r[n] = (sh4->r[n] << 1) | (sh4->sr & T);
	699	m_r[n] = (m_r[n] << 1) | (m_sr & T);
596	700
597	701	if (!old_q)
598	702	{
599		if (!(sh4->sr & M))
	703	if (!(m_sr & M))
600	704	{
601		tmp0 = sh4->r[n];
602		sh4->r[n] -= sh4->r[m];
603		if(!(sh4->sr & Q))
604		if(sh4->r[n] > tmp0)
605		sh4->sr |= Q;
	705	tmp0 = m_r[n];
	706	m_r[n] -= m_r[m];
	707	if(!(m_sr & Q))
	708	if(m_r[n] > tmp0)
	709	m_sr |= Q;
606	710	else
607		sh4->sr &= ~Q;
	711	m_sr &= ~Q;
608	712	else
609		if(sh4->r[n] > tmp0)
610		sh4->sr &= ~Q;
	713	if(m_r[n] > tmp0)
	714	m_sr &= ~Q;
611	715	else
612		sh4->sr |= Q;
	716	m_sr |= Q;
613	717	}
614	718	else
615	719	{
616		tmp0 = sh4->r[n];
617		sh4->r[n] += sh4->r[m];
618		if(!(sh4->sr & Q))
	720	tmp0 = m_r[n];
	721	m_r[n] += m_r[m];
	722	if(!(m_sr & Q))
619	723	{
620		if(sh4->r[n] < tmp0)
621		sh4->sr &= ~Q;
	724	if(m_r[n] < tmp0)
	725	m_sr &= ~Q;
622	726	else
623		sh4->sr |= Q;
	727	m_sr |= Q;
624	728	}
625	729	else
626	730	{
627		if(sh4->r[n] < tmp0)
628		sh4->sr |= Q;
	731	if(m_r[n] < tmp0)
	732	m_sr |= Q;
629	733	else
630		sh4->sr &= ~Q;
	734	m_sr &= ~Q;
631	735	}
632	736	}
633	737	}
634	738	else
635	739	{
636		if (!(sh4->sr & M))
	740	if (!(m_sr & M))
637	741	{
638		tmp0 = sh4->r[n];
639		sh4->r[n] += sh4->r[m];
640		if(!(sh4->sr & Q))
641		if(sh4->r[n] < tmp0)
642		sh4->sr |= Q;
	742	tmp0 = m_r[n];
	743	m_r[n] += m_r[m];
	744	if(!(m_sr & Q))
	745	if(m_r[n] < tmp0)
	746	m_sr |= Q;
643	747	else
644		sh4->sr &= ~Q;
	748	m_sr &= ~Q;
645	749	else
646		if(sh4->r[n] < tmp0)
647		sh4->sr &= ~Q;
	750	if(m_r[n] < tmp0)
	751	m_sr &= ~Q;
648	752	else
649		sh4->sr |= Q;
	753	m_sr |= Q;
650	754	}
651	755	else
652	756	{
653		tmp0 = sh4->r[n];
654		sh4->r[n] -= sh4->r[m];
655		if(!(sh4->sr & Q))
656		if(sh4->r[n] > tmp0)
657		sh4->sr &= ~Q;
	757	tmp0 = m_r[n];
	758	m_r[n] -= m_r[m];
	759	if(!(m_sr & Q))
	760	if(m_r[n] > tmp0)
	761	m_sr &= ~Q;
658	762	else
659		sh4->sr |= Q;
	763	m_sr |= Q;
660	764	else
661		if(sh4->r[n] > tmp0)
662		sh4->sr |= Q;
	765	if(m_r[n] > tmp0)
	766	m_sr |= Q;
663	767	else
664		sh4->sr &= ~Q;
	768	m_sr &= ~Q;
665	769	}
666	770	}
667	771
668		tmp0 = (sh4->sr & (Q | M));
	772	tmp0 = (m_sr & (Q | M));
669	773	if((!tmp0) || (tmp0 == 0x300)) /* if Q == M set T else clear T */
670		sh4->sr |= T;
	774	m_sr |= T;
671	775	else
672		sh4->sr &= ~T;
	776	m_sr &= ~T;
673	777	}
674	778
675	779	/*  DMULS.L Rm,Rn */
676		const void DMULS(sh4_state *sh4, const UINT16 opcode)
	780	void sh34_base_device::DMULS(const UINT16 opcode)
677	781	{
678	782	UINT32 m = Rm; UINT32 n = Rn;
679	783
r31221	r31222
681	785	UINT32 temp0, temp1, temp2, temp3;
682	786	INT32 tempm, tempn, fnLmL;
683	787
684		tempn = (INT32) sh4->r[n];
685		tempm = (INT32) sh4->r[m];
	788	tempn = (INT32) m_r[n];
	789	tempm = (INT32) m_r[m];
686	790	if (tempn < 0)
687	791	tempn = 0 - tempn;
688	792	if (tempm < 0)
689	793	tempm = 0 - tempm;
690		if ((INT32) (sh4->r[n] ^ sh4->r[m]) < 0)
	794	if ((INT32) (m_r[n] ^ m_r[m]) < 0)
691	795	fnLmL = -1;
692	796	else
693	797	fnLmL = 0;
r31221	r31222
718	822	else
719	823	Res0 = (~Res0) + 1;
720	824	}
721		sh4->mach = Res2;
722		sh4->macl = Res0;
723		sh4->sh4_icount--;
	825	m_mach = Res2;
	826	m_macl = Res0;
	827	m_sh4_icount--;
724	828	}
725	829
726	830	/*  DMULU.L Rm,Rn */
727		const void DMULU(sh4_state *sh4, const UINT16 opcode)
	831	void sh34_base_device::DMULU(const UINT16 opcode)
728	832	{
729	833	UINT32 m = Rm; UINT32 n = Rn;
730	834
731	835	UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;
732	836	UINT32 temp0, temp1, temp2, temp3;
733	837
734		RnL = sh4->r[n] & 0x0000ffff;
735		RnH = (sh4->r[n] >> 16) & 0x0000ffff;
736		RmL = sh4->r[m] & 0x0000ffff;
737		RmH = (sh4->r[m] >> 16) & 0x0000ffff;
	838	RnL = m_r[n] & 0x0000ffff;
	839	RnH = (m_r[n] >> 16) & 0x0000ffff;
	840	RmL = m_r[m] & 0x0000ffff;
	841	RmH = (m_r[m] >> 16) & 0x0000ffff;
738	842	temp0 = RmL * RnL;
739	843	temp1 = RmH * RnL;
740	844	temp2 = RmL * RnH;
r31221	r31222
748	852	if (Res0 < temp0)
749	853	Res2++;
750	854	Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;
751		sh4->mach = Res2;
752		sh4->macl = Res0;
753		sh4->sh4_icount--;
	855	m_mach = Res2;
	856	m_macl = Res0;
	857	m_sh4_icount--;
754	858	}
755	859
756	860	/*  DT      Rn */
757		const void DT(sh4_state *sh4, const UINT16 opcode)
	861	void sh34_base_device::DT(const UINT16 opcode)
758	862	{
759	863	UINT32 n = Rn;
760	864
761		sh4->r[n]--;
762		if (sh4->r[n] == 0)
763		sh4->sr |= T;
	865	m_r[n]--;
	866	if (m_r[n] == 0)
	867	m_sr |= T;
764	868	else
765		sh4->sr &= ~T;
	869	m_sr &= ~T;
766	870	#if BUSY_LOOP_HACKS
767	871	{
768		UINT32 next_opcode = RW(sh4,sh4->ppc & AM);
	872	UINT32 next_opcode = RW(m_ppc & AM);
769	873	/* DT   Rn
770	874	* BF   $-2
771	875	*/
772	876	if (next_opcode == 0x8bfd)
773	877	{
774		while (sh4->r[n] > 1 && sh4->sh4_icount > 4)
	878	while (m_r[n] > 1 && m_sh4_icount > 4)
775	879	{
776		sh4->r[n]--;
777		sh4->sh4_icount -= 4;   /* cycles for DT (1) and BF taken (3) */
	880	m_r[n]--;
	881	m_sh4_icount -= 4;   /* cycles for DT (1) and BF taken (3) */
778	882	}
779	883	}
780	884	}
r31221	r31222
782	886	}
783	887
784	888	/*  EXTS.B  Rm,Rn */
785		const void EXTSB(sh4_state *sh4, const UINT16 opcode)
	889	void sh34_base_device::EXTSB(const UINT16 opcode)
786	890	{
787		sh4->r[Rn] = ((INT32)sh4->r[Rm] << 24) >> 24;
	891	m_r[Rn] = ((INT32)m_r[Rm] << 24) >> 24;
788	892	}
789	893
790	894	/*  EXTS.W  Rm,Rn */
791		const void EXTSW(sh4_state *sh4, const UINT16 opcode)
	895	void sh34_base_device::EXTSW(const UINT16 opcode)
792	896	{
793		sh4->r[Rn] = ((INT32)sh4->r[Rm] << 16) >> 16;
	897	m_r[Rn] = ((INT32)m_r[Rm] << 16) >> 16;
794	898	}
795	899
796	900	/*  EXTU.B  Rm,Rn */
797		const void EXTUB(sh4_state *sh4, const UINT16 opcode)
	901	void sh34_base_device::EXTUB(const UINT16 opcode)
798	902	{
799		sh4->r[Rn] = sh4->r[Rm] & 0x000000ff;
	903	m_r[Rn] = m_r[Rm] & 0x000000ff;
800	904	}
801	905
802	906	/*  EXTU.W  Rm,Rn */
803		const void EXTUW(sh4_state *sh4, const UINT16 opcode)
	907	void sh34_base_device::EXTUW(const UINT16 opcode)
804	908	{
805		sh4->r[Rn] = sh4->r[Rm] & 0x0000ffff;
	909	m_r[Rn] = m_r[Rm] & 0x0000ffff;
806	910	}
807	911
808	912	/*  JMP     @Rm */
809		const void JMP(sh4_state *sh4, const UINT16 opcode)
	913	void sh34_base_device::JMP(const UINT16 opcode)
810	914	{
811		sh4->delay = sh4->pc;
812		sh4->pc = sh4->ea = sh4->r[Rn];
	915	m_delay = m_pc;
	916	m_pc = m_ea = m_r[Rn];
813	917	}
814	918
815	919	/*  JSR     @Rm */
816		const void JSR(sh4_state *sh4, const UINT16 opcode)
	920	void sh34_base_device::JSR(const UINT16 opcode)
817	921	{
818		sh4->delay = sh4->pc;
819		sh4->pr = sh4->pc + 2;
820		sh4->pc = sh4->ea = sh4->r[Rn];
821		sh4->sh4_icount--;
	922	m_delay = m_pc;
	923	m_pr = m_pc + 2;
	924	m_pc = m_ea = m_r[Rn];
	925	m_sh4_icount--;
822	926	}
823	927
824	928
825	929	/*  LDC     Rm,SR */
826		const void LDCSR(sh4_state *sh4, const UINT16 opcode)
	930	void sh34_base_device::LDCSR(const UINT16 opcode)
827	931	{
828	932	UINT32 reg;
829	933
830		reg = sh4->r[Rn];
831		if ((sh4->device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
832		sh4_syncronize_register_bank(sh4, (sh4->sr & sRB) >> 29);
833		if ((sh4->r[Rn] & sRB) != (sh4->sr & sRB))
834		sh4_change_register_bank(sh4, sh4->r[Rn] & sRB ? 1 : 0);
835		sh4->sr = reg & FLAGS;
836		sh4_exception_recompute(sh4);
	934	reg = m_r[Rn];
	935	if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
	936	sh4_syncronize_register_bank((m_sr & sRB) >> 29);
	937	if ((m_r[Rn] & sRB) != (m_sr & sRB))
	938	sh4_change_register_bank(m_r[Rn] & sRB ? 1 : 0);
	939	m_sr = reg & FLAGS;
	940	sh4_exception_recompute();
837	941	}
838	942
839	943	/*  LDC     Rm,GBR */
840		const void LDCGBR(sh4_state *sh4, const UINT16 opcode)
	944	void sh34_base_device::LDCGBR(const UINT16 opcode)
841	945	{
842		sh4->gbr = sh4->r[Rn];
	946	m_gbr = m_r[Rn];
843	947	}
844	948
845	949	/*  LDC     Rm,VBR */
846		const void LDCVBR(sh4_state *sh4, const UINT16 opcode)
	950	void sh34_base_device::LDCVBR(const UINT16 opcode)
847	951	{
848		sh4->vbr = sh4->r[Rn];
	952	m_vbr = m_r[Rn];
849	953	}
850	954
851	955	/*  LDC.L   @Rm+,SR */
852		const void LDCMSR(sh4_state *sh4, const UINT16 opcode)
	956	void sh34_base_device::LDCMSR(const UINT16 opcode)
853	957	{
854	958	UINT32 old;
855	959
856		old = sh4->sr;
857		sh4->ea = sh4->r[Rn];
858		sh4->sr = RL(sh4, sh4->ea ) & FLAGS;
859		if ((sh4->device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
860		sh4_syncronize_register_bank(sh4, (old & sRB) >> 29);
861		if ((old & sRB) != (sh4->sr & sRB))
862		sh4_change_register_bank(sh4, sh4->sr & sRB ? 1 : 0);
863		sh4->r[Rn] += 4;
864		sh4->sh4_icount -= 2;
865		sh4_exception_recompute(sh4);
	960	old = m_sr;
	961	m_ea = m_r[Rn];
	962	m_sr = RL(m_ea ) & FLAGS;
	963	if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
	964	sh4_syncronize_register_bank((old & sRB) >> 29);
	965	if ((old & sRB) != (m_sr & sRB))
	966	sh4_change_register_bank(m_sr & sRB ? 1 : 0);
	967	m_r[Rn] += 4;
	968	m_sh4_icount -= 2;
	969	sh4_exception_recompute();
866	970	}
867	971
868	972	/*  LDC.L   @Rm+,GBR */
869		const void LDCMGBR(sh4_state *sh4, const UINT16 opcode)
	973	void sh34_base_device::LDCMGBR(const UINT16 opcode)
870	974	{
871		sh4->ea = sh4->r[Rn];
872		sh4->gbr = RL(sh4, sh4->ea );
873		sh4->r[Rn] += 4;
874		sh4->sh4_icount -= 2;
	975	m_ea = m_r[Rn];
	976	m_gbr = RL(m_ea );
	977	m_r[Rn] += 4;
	978	m_sh4_icount -= 2;
875	979	}
876	980
877	981	/*  LDC.L   @Rm+,VBR */
878		const void LDCMVBR(sh4_state *sh4, const UINT16 opcode)
	982	void sh34_base_device::LDCMVBR(const UINT16 opcode)
879	983	{
880		sh4->ea = sh4->r[Rn];
881		sh4->vbr = RL(sh4, sh4->ea );
882		sh4->r[Rn] += 4;
883		sh4->sh4_icount -= 2;
	984	m_ea = m_r[Rn];
	985	m_vbr = RL(m_ea );
	986	m_r[Rn] += 4;
	987	m_sh4_icount -= 2;
884	988	}
885	989
886	990	/*  LDS     Rm,MACH */
887		const void LDSMACH(sh4_state *sh4, const UINT16 opcode)
	991	void sh34_base_device::LDSMACH(const UINT16 opcode)
888	992	{
889		sh4->mach = sh4->r[Rn];
	993	m_mach = m_r[Rn];
890	994	}
891	995
892	996	/*  LDS     Rm,MACL */
893		const void LDSMACL(sh4_state *sh4, const UINT16 opcode)
	997	void sh34_base_device::LDSMACL(const UINT16 opcode)
894	998	{
895		sh4->macl = sh4->r[Rn];
	999	m_macl = m_r[Rn];
896	1000	}
897	1001
898	1002	/*  LDS     Rm,PR */
899		const void LDSPR(sh4_state *sh4, const UINT16 opcode)
	1003	void sh34_base_device::LDSPR(const UINT16 opcode)
900	1004	{
901		sh4->pr = sh4->r[Rn];
	1005	m_pr = m_r[Rn];
902	1006	}
903	1007
904	1008	/*  LDS.L   @Rm+,MACH */
905		const void LDSMMACH(sh4_state *sh4, const UINT16 opcode)
	1009	void sh34_base_device::LDSMMACH(const UINT16 opcode)
906	1010	{
907		sh4->ea = sh4->r[Rn];
908		sh4->mach = RL(sh4, sh4->ea );
909		sh4->r[Rn] += 4;
	1011	m_ea = m_r[Rn];
	1012	m_mach = RL(m_ea );
	1013	m_r[Rn] += 4;
910	1014	}
911	1015
912	1016	/*  LDS.L   @Rm+,MACL */
913		const void LDSMMACL(sh4_state *sh4, const UINT16 opcode)
	1017	void sh34_base_device::LDSMMACL(const UINT16 opcode)
914	1018	{
915		sh4->ea = sh4->r[Rn];
916		sh4->macl = RL(sh4, sh4->ea );
917		sh4->r[Rn] += 4;
	1019	m_ea = m_r[Rn];
	1020	m_macl = RL(m_ea );
	1021	m_r[Rn] += 4;
918	1022	}
919	1023
920	1024	/*  LDS.L   @Rm+,PR */
921		const void LDSMPR(sh4_state *sh4, const UINT16 opcode)
	1025	void sh34_base_device::LDSMPR(const UINT16 opcode)
922	1026	{
923		sh4->ea = sh4->r[Rn];
924		sh4->pr = RL(sh4, sh4->ea );
925		sh4->r[Rn] += 4;
	1027	m_ea = m_r[Rn];
	1028	m_pr = RL(m_ea );
	1029	m_r[Rn] += 4;
926	1030	}
927	1031
928	1032	/*  MAC.L   @Rm+,@Rn+ */
929		const void MAC_L(sh4_state *sh4, const UINT16 opcode)
	1033	void sh34_base_device::MAC_L(const UINT16 opcode)
930	1034	{
931	1035	UINT32 m = Rm; UINT32 n = Rn;
932	1036
r31221	r31222
934	1038	UINT32 temp0, temp1, temp2, temp3;
935	1039	INT32 tempm, tempn, fnLmL;
936	1040
937		tempn = (INT32) RL(sh4, sh4->r[n] );
938		sh4->r[n] += 4;
939		tempm = (INT32) RL(sh4, sh4->r[m] );
940		sh4->r[m] += 4;
	1041	tempn = (INT32) RL(m_r[n] );
	1042	m_r[n] += 4;
	1043	tempm = (INT32) RL(m_r[m] );
	1044	m_r[m] += 4;
941	1045	if ((INT32) (tempn ^ tempm) < 0)
942	1046	fnLmL = -1;
943	1047	else
r31221	r31222
973	1077	else
974	1078	Res0 = (~Res0) + 1;
975	1079	}
976		if (sh4->sr & S)
	1080	if (m_sr & S)
977	1081	{
978		Res0 = sh4->macl + Res0;
979		if (sh4->macl > Res0)
	1082	Res0 = m_macl + Res0;
	1083	if (m_macl > Res0)
980	1084	Res2++;
981		Res2 += (sh4->mach & 0x0000ffff);
	1085	Res2 += (m_mach & 0x0000ffff);
982	1086	if (((INT32) Res2 < 0) && (Res2 < 0xffff8000))
983	1087	{
984	1088	Res2 = 0x00008000;
r31221	r31222
989	1093	Res2 = 0x00007fff;
990	1094	Res0 = 0xffffffff;
991	1095	}
992		sh4->mach = Res2;
993		sh4->macl = Res0;
	1096	m_mach = Res2;
	1097	m_macl = Res0;
994	1098	}
995	1099	else
996	1100	{
997		Res0 = sh4->macl + Res0;
998		if (sh4->macl > Res0)
	1101	Res0 = m_macl + Res0;
	1102	if (m_macl > Res0)
999	1103	Res2++;
1000		Res2 += sh4->mach;
1001		sh4->mach = Res2;
1002		sh4->macl = Res0;
	1104	Res2 += m_mach;
	1105	m_mach = Res2;
	1106	m_macl = Res0;
1003	1107	}
1004		sh4->sh4_icount -= 2;
	1108	m_sh4_icount -= 2;
1005	1109	}
1006	1110
1007	1111	/*  MAC.W   @Rm+,@Rn+ */
1008		const void MAC_W(sh4_state *sh4, const UINT16 opcode)
	1112	void sh34_base_device::MAC_W(const UINT16 opcode)
1009	1113	{
1010	1114	UINT32 m = Rm; UINT32 n = Rn;
1011	1115
1012	1116	INT32 tempm, tempn, dest, src, ans;
1013	1117	UINT32 templ;
1014	1118
1015		tempn = (INT32) RW(sh4, sh4->r[n] );
1016		sh4->r[n] += 2;
1017		tempm = (INT32) RW(sh4, sh4->r[m] );
1018		sh4->r[m] += 2;
1019		templ = sh4->macl;
	1119	tempn = (INT32) RW(m_r[n] );
	1120	m_r[n] += 2;
	1121	tempm = (INT32) RW(m_r[m] );
	1122	m_r[m] += 2;
	1123	templ = m_macl;
1020	1124	tempm = ((INT32) (short) tempn * (INT32) (short) tempm);
1021		if ((INT32) sh4->macl >= 0)
	1125	if ((INT32) m_macl >= 0)
1022	1126	dest = 0;
1023	1127	else
1024	1128	dest = 1;
r31221	r31222
1033	1137	tempn = 0xffffffff;
1034	1138	}
1035	1139	src += dest;
1036		sh4->macl += tempm;
1037		if ((INT32) sh4->macl >= 0)
	1140	m_macl += tempm;
	1141	if ((INT32) m_macl >= 0)
1038	1142	ans = 0;
1039	1143	else
1040	1144	ans = 1;
1041	1145	ans += dest;
1042		if (sh4->sr & S)
	1146	if (m_sr & S)
1043	1147	{
1044	1148	if (ans == 1)
1045	1149	{
1046	1150	if (src == 0)
1047		sh4->macl = 0x7fffffff;
	1151	m_macl = 0x7fffffff;
1048	1152	if (src == 2)
1049		sh4->macl = 0x80000000;
	1153	m_macl = 0x80000000;
1050	1154	}
1051	1155	}
1052	1156	else
1053	1157	{
1054		sh4->mach += tempn;
1055		if (templ > sh4->macl)
1056		sh4->mach += 1;
	1158	m_mach += tempn;
	1159	if (templ > m_macl)
	1160	m_mach += 1;
1057	1161	}
1058		sh4->sh4_icount -= 2;
	1162	m_sh4_icount -= 2;
1059	1163	}
1060	1164
1061	1165	/*  MOV     Rm,Rn */
1062		const void MOV(sh4_state *sh4, const UINT16 opcode)
	1166	void sh34_base_device::MOV(const UINT16 opcode)
1063	1167	{
1064		sh4->r[Rn] = sh4->r[Rm];
	1168	m_r[Rn] = m_r[Rm];
1065	1169	}
1066	1170
1067	1171	/*  MOV.B   Rm,@Rn */
1068		const void MOVBS(sh4_state *sh4, const UINT16 opcode)
	1172	void sh34_base_device::MOVBS(const UINT16 opcode)
1069	1173	{
1070		sh4->ea = sh4->r[Rn];
1071		WB(sh4, sh4->ea, sh4->r[Rm] & 0x000000ff);
	1174	m_ea = m_r[Rn];
	1175	WB(m_ea, m_r[Rm] & 0x000000ff);
1072	1176	}
1073	1177
1074	1178	/*  MOV.W   Rm,@Rn */
1075		const void MOVWS(sh4_state *sh4, const UINT16 opcode)
	1179	void sh34_base_device::MOVWS(const UINT16 opcode)
1076	1180	{
1077		sh4->ea = sh4->r[Rn];
1078		WW(sh4, sh4->ea, sh4->r[Rm] & 0x0000ffff);
	1181	m_ea = m_r[Rn];
	1182	WW(m_ea, m_r[Rm] & 0x0000ffff);
1079	1183	}
1080	1184
1081	1185	/*  MOV.L   Rm,@Rn */
1082		const void MOVLS(sh4_state *sh4, const UINT16 opcode)
	1186	void sh34_base_device::MOVLS(const UINT16 opcode)
1083	1187	{
1084		sh4->ea = sh4->r[Rn];
1085		WL(sh4, sh4->ea, sh4->r[Rm] );
	1188	m_ea = m_r[Rn];
	1189	WL(m_ea, m_r[Rm] );
1086	1190	}
1087	1191
1088	1192	/*  MOV.B   @Rm,Rn */
1089		const void MOVBL(sh4_state *sh4, const UINT16 opcode)
	1193	void sh34_base_device::MOVBL(const UINT16 opcode)
1090	1194	{
1091		sh4->ea = sh4->r[Rm];
1092		sh4->r[Rn] = (UINT32)(INT32)(INT16)(INT8) RB(sh4,  sh4->ea );
	1195	m_ea = m_r[Rm];
	1196	m_r[Rn] = (UINT32)(INT32)(INT16)(INT8) RB( m_ea );
1093	1197	}
1094	1198
1095	1199	/*  MOV.W   @Rm,Rn */
1096		const void MOVWL(sh4_state *sh4, const UINT16 opcode)
	1200	void sh34_base_device::MOVWL(const UINT16 opcode)
1097	1201	{
1098		sh4->ea = sh4->r[Rm];
1099		sh4->r[Rn] = (UINT32)(INT32)(INT16) RW(sh4, sh4->ea );
	1202	m_ea = m_r[Rm];
	1203	m_r[Rn] = (UINT32)(INT32)(INT16) RW(m_ea );
1100	1204	}
1101	1205
1102	1206	/*  MOV.L   @Rm,Rn */
1103		const void MOVLL(sh4_state *sh4, const UINT16 opcode)
	1207	void sh34_base_device::MOVLL(const UINT16 opcode)
1104	1208	{
1105		sh4->ea = sh4->r[Rm];
1106		sh4->r[Rn] = RL(sh4, sh4->ea );
	1209	m_ea = m_r[Rm];
	1210	m_r[Rn] = RL(m_ea );
1107	1211	}
1108	1212
1109	1213	/*  MOV.B   Rm,@-Rn */
1110		const void MOVBM(sh4_state *sh4, const UINT16 opcode)
	1214	void sh34_base_device::MOVBM(const UINT16 opcode)
1111	1215	{
1112		UINT32 data = sh4->r[Rm] & 0x000000ff;
	1216	UINT32 data = m_r[Rm] & 0x000000ff;
1113	1217
1114		sh4->r[Rn] -= 1;
1115		WB(sh4, sh4->r[Rn], data );
	1218	m_r[Rn] -= 1;
	1219	WB(m_r[Rn], data );
1116	1220	}
1117	1221
1118	1222	/*  MOV.W   Rm,@-Rn */
1119		const void MOVWM(sh4_state *sh4, const UINT16 opcode)
	1223	void sh34_base_device::MOVWM(const UINT16 opcode)
1120	1224	{
1121		UINT32 data = sh4->r[Rm] & 0x0000ffff;
	1225	UINT32 data = m_r[Rm] & 0x0000ffff;
1122	1226
1123		sh4->r[Rn] -= 2;
1124		WW(sh4, sh4->r[Rn], data );
	1227	m_r[Rn] -= 2;
	1228	WW(m_r[Rn], data );
1125	1229	}
1126	1230
1127	1231	/*  MOV.L   Rm,@-Rn */
1128		const void MOVLM(sh4_state *sh4, const UINT16 opcode)
	1232	void sh34_base_device::MOVLM(const UINT16 opcode)
1129	1233	{
1130		UINT32 data = sh4->r[Rm];
	1234	UINT32 data = m_r[Rm];
1131	1235
1132		sh4->r[Rn] -= 4;
1133		WL(sh4, sh4->r[Rn], data );
	1236	m_r[Rn] -= 4;
	1237	WL(m_r[Rn], data );
1134	1238	}
1135	1239
1136	1240	/*  MOV.B   @Rm+,Rn */
1137		const void MOVBP(sh4_state *sh4, const UINT16 opcode)
	1241	void sh34_base_device::MOVBP(const UINT16 opcode)
1138	1242	{
1139	1243	UINT32 m = Rm; UINT32 n = Rn;
1140	1244
1141		sh4->r[n] = (UINT32)(INT32)(INT16)(INT8) RB(sh4, sh4->r[m] );
	1245	m_r[n] = (UINT32)(INT32)(INT16)(INT8) RB( m_r[m] );
1142	1246	if (n != m)
1143		sh4->r[m] += 1;
	1247	m_r[m] += 1;
1144	1248	}
1145	1249
1146	1250	/*  MOV.W   @Rm+,Rn */
1147		const void MOVWP(sh4_state *sh4, const UINT16 opcode)
	1251	void sh34_base_device::MOVWP(const UINT16 opcode)
1148	1252	{
1149	1253	UINT32 m = Rm; UINT32 n = Rn;
1150	1254
1151		sh4->r[n] = (UINT32)(INT32)(INT16) RW(sh4, sh4->r[m] );
	1255	m_r[n] = (UINT32)(INT32)(INT16) RW(m_r[m] );
1152	1256	if (n != m)
1153		sh4->r[m] += 2;
	1257	m_r[m] += 2;
1154	1258	}
1155	1259
1156	1260	/*  MOV.L   @Rm+,Rn */
1157		const void MOVLP(sh4_state *sh4, const UINT16 opcode)
	1261	void sh34_base_device::MOVLP(const UINT16 opcode)
1158	1262	{
1159	1263	UINT32 m = Rm; UINT32 n = Rn;
1160	1264
1161		sh4->r[n] = RL(sh4, sh4->r[m] );
	1265	m_r[n] = RL(m_r[m] );
1162	1266	if (n != m)
1163		sh4->r[m] += 4;
	1267	m_r[m] += 4;
1164	1268	}
1165	1269
1166	1270	/*  MOV.B   Rm,@(R0,Rn) */
1167		const void MOVBS0(sh4_state *sh4, const UINT16 opcode)
	1271	void sh34_base_device::MOVBS0(const UINT16 opcode)
1168	1272	{
1169		sh4->ea = sh4->r[Rn] + sh4->r[0];
1170		WB(sh4, sh4->ea, sh4->r[Rm] & 0x000000ff );
	1273	m_ea = m_r[Rn] + m_r[0];
	1274	WB(m_ea, m_r[Rm] & 0x000000ff );
1171	1275	}
1172	1276
1173	1277	/*  MOV.W   Rm,@(R0,Rn) */
1174		const void MOVWS0(sh4_state *sh4, const UINT16 opcode)
	1278	void sh34_base_device::MOVWS0(const UINT16 opcode)
1175	1279	{
1176		sh4->ea = sh4->r[Rn] + sh4->r[0];
1177		WW(sh4, sh4->ea, sh4->r[Rm] & 0x0000ffff );
	1280	m_ea = m_r[Rn] + m_r[0];
	1281	WW(m_ea, m_r[Rm] & 0x0000ffff );
1178	1282	}
1179	1283
1180	1284	/*  MOV.L   Rm,@(R0,Rn) */
1181		const void MOVLS0(sh4_state *sh4, const UINT16 opcode)
	1285	void sh34_base_device::MOVLS0(const UINT16 opcode)
1182	1286	{
1183		sh4->ea = sh4->r[Rn] + sh4->r[0];
1184		WL(sh4, sh4->ea, sh4->r[Rm] );
	1287	m_ea = m_r[Rn] + m_r[0];
	1288	WL(m_ea, m_r[Rm] );
1185	1289	}
1186	1290
1187	1291	/*  MOV.B   @(R0,Rm),Rn */
1188		const void MOVBL0(sh4_state *sh4, const UINT16 opcode)
	1292	void sh34_base_device::MOVBL0(const UINT16 opcode)
1189	1293	{
1190		sh4->ea = sh4->r[Rm] + sh4->r[0];
1191		sh4->r[Rn] = (UINT32)(INT32)(INT16)(INT8) RB(sh4,  sh4->ea );
	1294	m_ea = m_r[Rm] + m_r[0];
	1295	m_r[Rn] = (UINT32)(INT32)(INT16)(INT8) RB( m_ea );
1192	1296	}
1193	1297
1194	1298	/*  MOV.W   @(R0,Rm),Rn */
1195		const void MOVWL0(sh4_state *sh4, const UINT16 opcode)
	1299	void sh34_base_device::MOVWL0(const UINT16 opcode)
1196	1300	{
1197		sh4->ea = sh4->r[Rm] + sh4->r[0];
1198		sh4->r[Rn] = (UINT32)(INT32)(INT16) RW(sh4, sh4->ea );
	1301	m_ea = m_r[Rm] + m_r[0];
	1302	m_r[Rn] = (UINT32)(INT32)(INT16) RW(m_ea );
1199	1303	}
1200	1304
1201	1305	/*  MOV.L   @(R0,Rm),Rn */
1202		const void MOVLL0(sh4_state *sh4, const UINT16 opcode)
	1306	void sh34_base_device::MOVLL0(const UINT16 opcode)
1203	1307	{
1204		sh4->ea = sh4->r[Rm] + sh4->r[0];
1205		sh4->r[Rn] = RL(sh4, sh4->ea );
	1308	m_ea = m_r[Rm] + m_r[0];
	1309	m_r[Rn] = RL(m_ea );
1206	1310	}
1207	1311
1208	1312	/*  MOV     #imm,Rn */
1209		const void MOVI(sh4_state *sh4, const UINT16 opcode)
	1313	void sh34_base_device::MOVI(const UINT16 opcode)
1210	1314	{
1211		sh4->r[Rn] = (UINT32)(INT32)(INT16)(INT8)(opcode&0xff);
	1315	m_r[Rn] = (UINT32)(INT32)(INT16)(INT8)(opcode&0xff);
1212	1316	}
1213	1317
1214	1318	/*  MOV.W   @(disp8,PC),Rn */
1215		const void MOVWI(sh4_state *sh4, const UINT16 opcode)
	1319	void sh34_base_device::MOVWI(const UINT16 opcode)
1216	1320	{
1217	1321	UINT32 disp = opcode & 0xff;
1218		sh4->ea = sh4->pc + disp * 2 + 2;
1219		sh4->r[Rn] = (UINT32)(INT32)(INT16) RW(sh4, sh4->ea );
	1322	m_ea = m_pc + disp * 2 + 2;
	1323	m_r[Rn] = (UINT32)(INT32)(INT16) RW(m_ea );
1220	1324	}
1221	1325
1222	1326	/*  MOV.L   @(disp8,PC),Rn */
1223		const void MOVLI(sh4_state *sh4, const UINT16 opcode)
	1327	void sh34_base_device::MOVLI(const UINT16 opcode)
1224	1328	{
1225	1329	UINT32 disp = opcode & 0xff;
1226		sh4->ea = ((sh4->pc + 2) & ~3) + disp * 4;
1227		sh4->r[Rn] = RL(sh4, sh4->ea );
	1330	m_ea = ((m_pc + 2) & ~3) + disp * 4;
	1331	m_r[Rn] = RL(m_ea );
1228	1332	}
1229	1333
1230	1334	/*  MOV.B   @(disp8,GBR),R0 */
1231		const void MOVBLG(sh4_state *sh4, const UINT16 opcode)
	1335	void sh34_base_device::MOVBLG(const UINT16 opcode)
1232	1336	{
1233	1337	UINT32 disp = opcode & 0xff;
1234		sh4->ea = sh4->gbr + disp;
1235		sh4->r[0] = (UINT32)(INT32)(INT16)(INT8) RB(sh4,  sh4->ea );
	1338	m_ea = m_gbr + disp;
	1339	m_r[0] = (UINT32)(INT32)(INT16)(INT8) RB( m_ea );
1236	1340	}
1237	1341
1238	1342	/*  MOV.W   @(disp8,GBR),R0 */
1239		const void MOVWLG(sh4_state *sh4, const UINT16 opcode)
	1343	void sh34_base_device::MOVWLG(const UINT16 opcode)
1240	1344	{
1241	1345	UINT32 disp = opcode & 0xff;
1242		sh4->ea = sh4->gbr + disp * 2;
1243		sh4->r[0] = (INT32)(INT16) RW(sh4, sh4->ea );
	1346	m_ea = m_gbr + disp * 2;
	1347	m_r[0] = (INT32)(INT16) RW(m_ea );
1244	1348	}
1245	1349
1246	1350	/*  MOV.L   @(disp8,GBR),R0 */
1247		const void MOVLLG(sh4_state *sh4, const UINT16 opcode)
	1351	void sh34_base_device::MOVLLG(const UINT16 opcode)
1248	1352	{
1249	1353	UINT32 disp = opcode & 0xff;
1250		sh4->ea = sh4->gbr + disp * 4;
1251		sh4->r[0] = RL(sh4, sh4->ea );
	1354	m_ea = m_gbr + disp * 4;
	1355	m_r[0] = RL(m_ea );
1252	1356	}
1253	1357
1254	1358	/*  MOV.B   R0,@(disp8,GBR) */
1255		const void MOVBSG(sh4_state *sh4, const UINT16 opcode)
	1359	void sh34_base_device::MOVBSG(const UINT16 opcode)
1256	1360	{
1257	1361	UINT32 disp = opcode & 0xff;
1258		sh4->ea = sh4->gbr + disp;
1259		WB(sh4, sh4->ea, sh4->r[0] & 0x000000ff );
	1362	m_ea = m_gbr + disp;
	1363	WB(m_ea, m_r[0] & 0x000000ff );
1260	1364	}
1261	1365
1262	1366	/*  MOV.W   R0,@(disp8,GBR) */
1263		const void MOVWSG(sh4_state *sh4, const UINT16 opcode)
	1367	void sh34_base_device::MOVWSG(const UINT16 opcode)
1264	1368	{
1265	1369	UINT32 disp = opcode & 0xff;
1266		sh4->ea = sh4->gbr + disp * 2;
1267		WW(sh4, sh4->ea, sh4->r[0] & 0x0000ffff );
	1370	m_ea = m_gbr + disp * 2;
	1371	WW(m_ea, m_r[0] & 0x0000ffff );
1268	1372	}
1269	1373
1270	1374	/*  MOV.L   R0,@(disp8,GBR) */
1271		const void MOVLSG(sh4_state *sh4, const UINT16 opcode)
	1375	void sh34_base_device::MOVLSG(const UINT16 opcode)
1272	1376	{
1273	1377	UINT32 disp = opcode & 0xff;
1274		sh4->ea = sh4->gbr + disp * 4;
1275		WL(sh4, sh4->ea, sh4->r[0] );
	1378	m_ea = m_gbr + disp * 4;
	1379	WL(m_ea, m_r[0] );
1276	1380	}
1277	1381
1278	1382	/*  MOV.B   R0,@(disp4,Rm) */
1279		const void MOVBS4(sh4_state *sh4, const UINT16 opcode)
	1383	void sh34_base_device::MOVBS4(const UINT16 opcode)
1280	1384	{
1281	1385	UINT32 disp = opcode & 0x0f;
1282		sh4->ea = sh4->r[Rm] + disp;
1283		WB(sh4, sh4->ea, sh4->r[0] & 0x000000ff );
	1386	m_ea = m_r[Rm] + disp;
	1387	WB(m_ea, m_r[0] & 0x000000ff );
1284	1388	}
1285	1389
1286	1390	/*  MOV.W   R0,@(disp4,Rm) */
1287		const void MOVWS4(sh4_state *sh4, const UINT16 opcode)
	1391	void sh34_base_device::MOVWS4(const UINT16 opcode)
1288	1392	{
1289	1393	UINT32 disp = opcode & 0x0f;
1290		sh4->ea = sh4->r[Rm] + disp * 2;
1291		WW(sh4, sh4->ea, sh4->r[0] & 0x0000ffff );
	1394	m_ea = m_r[Rm] + disp * 2;
	1395	WW(m_ea, m_r[0] & 0x0000ffff );
1292	1396	}
1293	1397
1294	1398	/* MOV.L Rm,@(disp4,Rn) */
1295		const void MOVLS4(sh4_state *sh4, const UINT16 opcode)
	1399	void sh34_base_device::MOVLS4(const UINT16 opcode)
1296	1400	{
1297	1401	UINT32 disp = opcode & 0x0f;
1298		sh4->ea = sh4->r[Rn] + disp * 4;
1299		WL(sh4, sh4->ea, sh4->r[Rm] );
	1402	m_ea = m_r[Rn] + disp * 4;
	1403	WL(m_ea, m_r[Rm] );
1300	1404	}
1301	1405
1302	1406	/*  MOV.B   @(disp4,Rm),R0 */
1303		const void MOVBL4(sh4_state *sh4, const UINT16 opcode)
	1407	void sh34_base_device::MOVBL4(const UINT16 opcode)
1304	1408	{
1305	1409	UINT32 disp = opcode & 0x0f;
1306		sh4->ea = sh4->r[Rm] + disp;
1307		sh4->r[0] = (UINT32)(INT32)(INT16)(INT8) RB(sh4,  sh4->ea );
	1410	m_ea = m_r[Rm] + disp;
	1411	m_r[0] = (UINT32)(INT32)(INT16)(INT8) RB( m_ea );
1308	1412	}
1309	1413
1310	1414	/*  MOV.W   @(disp4,Rm),R0 */
1311		const void MOVWL4(sh4_state *sh4, const UINT16 opcode)
	1415	void sh34_base_device::MOVWL4(const UINT16 opcode)
1312	1416	{
1313	1417	UINT32 disp = opcode & 0x0f;
1314		sh4->ea = sh4->r[Rm] + disp * 2;
1315		sh4->r[0] = (UINT32)(INT32)(INT16) RW(sh4, sh4->ea );
	1418	m_ea = m_r[Rm] + disp * 2;
	1419	m_r[0] = (UINT32)(INT32)(INT16) RW(m_ea );
1316	1420	}
1317	1421
1318	1422	/*  MOV.L   @(disp4,Rm),Rn */
1319		const void MOVLL4(sh4_state *sh4, const UINT16 opcode)
	1423	void sh34_base_device::MOVLL4(const UINT16 opcode)
1320	1424	{
1321	1425	UINT32 disp = opcode & 0x0f;
1322		sh4->ea = sh4->r[Rm] + disp * 4;
1323		sh4->r[Rn] = RL(sh4, sh4->ea );
	1426	m_ea = m_r[Rm] + disp * 4;
	1427	m_r[Rn] = RL(m_ea );
1324	1428	}
1325	1429
1326	1430	/*  MOVA    @(disp8,PC),R0 */
1327		const void MOVA(sh4_state *sh4, const UINT16 opcode)
	1431	void sh34_base_device::MOVA(const UINT16 opcode)
1328	1432	{
1329	1433	UINT32 disp = opcode & 0xff;
1330		sh4->ea = ((sh4->pc + 2) & ~3) + disp * 4;
1331		sh4->r[0] = sh4->ea;
	1434	m_ea = ((m_pc + 2) & ~3) + disp * 4;
	1435	m_r[0] = m_ea;
1332	1436	}
1333	1437
1334	1438	/*  MOVT    Rn */
1335		const void MOVT(sh4_state *sh4, const UINT16 opcode)
	1439	void sh34_base_device::MOVT(const UINT16 opcode)
1336	1440	{
1337		sh4->r[Rn] = sh4->sr & T;
	1441	m_r[Rn] = m_sr & T;
1338	1442	}
1339	1443
1340	1444	/*  MUL.L   Rm,Rn */
1341		const void MULL(sh4_state *sh4, const UINT16 opcode)
	1445	void sh34_base_device::MULL(const UINT16 opcode)
1342	1446	{
1343		sh4->macl = sh4->r[Rn] * sh4->r[Rm];
1344		sh4->sh4_icount--;
	1447	m_macl = m_r[Rn] * m_r[Rm];
	1448	m_sh4_icount--;
1345	1449	}
1346	1450
1347	1451	/*  MULS    Rm,Rn */
1348		const void MULS(sh4_state *sh4, const UINT16 opcode)
	1452	void sh34_base_device::MULS(const UINT16 opcode)
1349	1453	{
1350		sh4->macl = (INT16) sh4->r[Rn] * (INT16) sh4->r[Rm];
	1454	m_macl = (INT16) m_r[Rn] * (INT16) m_r[Rm];
1351	1455	}
1352	1456
1353	1457	/*  MULU    Rm,Rn */
1354		const void MULU(sh4_state *sh4, const UINT16 opcode)
	1458	void sh34_base_device::MULU(const UINT16 opcode)
1355	1459	{
1356		sh4->macl = (UINT16) sh4->r[Rn] * (UINT16) sh4->r[Rm];
	1460	m_macl = (UINT16) m_r[Rn] * (UINT16) m_r[Rm];
1357	1461	}
1358	1462
1359	1463	/*  NEG     Rm,Rn */
1360		const void NEG(sh4_state *sh4, const UINT16 opcode)
	1464	void sh34_base_device::NEG(const UINT16 opcode)
1361	1465	{
1362		sh4->r[Rn] = 0 - sh4->r[Rm];
	1466	m_r[Rn] = 0 - m_r[Rm];
1363	1467	}
1364	1468
1365	1469	/*  NEGC    Rm,Rn */
1366		const void NEGC(sh4_state *sh4, const UINT16 opcode)
	1470	void sh34_base_device::NEGC(const UINT16 opcode)
1367	1471	{
1368	1472	UINT32 temp;
1369	1473
1370		temp = sh4->r[Rm];
1371		sh4->r[Rn] = -temp - (sh4->sr & T);
1372		if (temp || (sh4->sr & T))
1373		sh4->sr |= T;
	1474	temp = m_r[Rm];
	1475	m_r[Rn] = -temp - (m_sr & T);
	1476	if (temp || (m_sr & T))
	1477	m_sr |= T;
1374	1478	else
1375		sh4->sr &= ~T;
	1479	m_sr &= ~T;
1376	1480	}
1377	1481
1378	1482	/*  NOP */
1379		const void NOP(sh4_state *sh4, const UINT16 opcode)
	1483	void sh34_base_device::NOP(const UINT16 opcode)
1380	1484	{
1381	1485	}
1382	1486
1383	1487	/*  NOT     Rm,Rn */
1384		const void NOT(sh4_state *sh4, const UINT16 opcode)
	1488	void sh34_base_device::NOT(const UINT16 opcode)
1385	1489	{
1386		sh4->r[Rn] = ~sh4->r[Rm];
	1490	m_r[Rn] = ~m_r[Rm];
1387	1491	}
1388	1492
1389	1493	/*  OR      Rm,Rn */
1390		const void OR(sh4_state *sh4, const UINT16 opcode)
	1494	void sh34_base_device::OR(const UINT16 opcode)
1391	1495	{
1392		sh4->r[Rn] |= sh4->r[Rm];
	1496	m_r[Rn] |= m_r[Rm];
1393	1497	}
1394	1498
1395	1499	/*  OR      #imm,R0 */
1396		const void ORI(sh4_state *sh4, const UINT16 opcode)
	1500	void sh34_base_device::ORI(const UINT16 opcode)
1397	1501	{
1398		sh4->r[0] |= (opcode&0xff);
1399		sh4->sh4_icount -= 2;
	1502	m_r[0] |= (opcode&0xff);
	1503	m_sh4_icount -= 2;
1400	1504	}
1401	1505
1402	1506	/*  OR.B    #imm,@(R0,GBR) */
1403		const void ORM(sh4_state *sh4, const UINT16 opcode)
	1507	void sh34_base_device::ORM(const UINT16 opcode)
1404	1508	{
1405	1509	UINT32 temp;
1406	1510
1407		sh4->ea = sh4->gbr + sh4->r[0];
1408		temp = RB(sh4,  sh4->ea );
	1511	m_ea = m_gbr + m_r[0];
	1512	temp = RB( m_ea );
1409	1513	temp |= (opcode&0xff);
1410		WB(sh4, sh4->ea, temp );
	1514	WB(m_ea, temp );
1411	1515	}
1412	1516
1413	1517	/*  ROTCL   Rn */
1414		const void ROTCL(sh4_state *sh4, const UINT16 opcode)
	1518	void sh34_base_device::ROTCL(const UINT16 opcode)
1415	1519	{
1416	1520	UINT32 n = Rn;
1417	1521
1418	1522	UINT32 temp;
1419	1523
1420		temp = (sh4->r[n] >> 31) & T;
1421		sh4->r[n] = (sh4->r[n] << 1) | (sh4->sr & T);
1422		sh4->sr = (sh4->sr & ~T) | temp;
	1524	temp = (m_r[n] >> 31) & T;
	1525	m_r[n] = (m_r[n] << 1) | (m_sr & T);
	1526	m_sr = (m_sr & ~T) | temp;
1423	1527	}
1424	1528
1425	1529	/*  ROTCR   Rn */
1426		const void ROTCR(sh4_state *sh4, const UINT16 opcode)
	1530	void sh34_base_device::ROTCR(const UINT16 opcode)
1427	1531	{
1428	1532	UINT32 n = Rn;
1429	1533
1430	1534	UINT32 temp;
1431		temp = (sh4->sr & T) << 31;
1432		if (sh4->r[n] & T)
1433		sh4->sr |= T;
	1535	temp = (m_sr & T) << 31;
	1536	if (m_r[n] & T)
	1537	m_sr |= T;
1434	1538	else
1435		sh4->sr &= ~T;
1436		sh4->r[n] = (sh4->r[n] >> 1) | temp;
	1539	m_sr &= ~T;
	1540	m_r[n] = (m_r[n] >> 1) | temp;
1437	1541	}
1438	1542
1439	1543	/*  ROTL    Rn */
1440		const void ROTL(sh4_state *sh4, const UINT16 opcode)
	1544	void sh34_base_device::ROTL(const UINT16 opcode)
1441	1545	{
1442	1546	UINT32 n = Rn;
1443	1547
1444		sh4->sr = (sh4->sr & ~T) | ((sh4->r[n] >> 31) & T);
1445		sh4->r[n] = (sh4->r[n] << 1) | (sh4->r[n] >> 31);
	1548	m_sr = (m_sr & ~T) | ((m_r[n] >> 31) & T);
	1549	m_r[n] = (m_r[n] << 1) | (m_r[n] >> 31);
1446	1550	}
1447	1551
1448	1552	/*  ROTR    Rn */
1449		const void ROTR(sh4_state *sh4, const UINT16 opcode)
	1553	void sh34_base_device::ROTR(const UINT16 opcode)
1450	1554	{
1451	1555	UINT32 n = Rn;
1452	1556
1453		sh4->sr = (sh4->sr & ~T) | (sh4->r[n] & T);
1454		sh4->r[n] = (sh4->r[n] >> 1) | (sh4->r[n] << 31);
	1557	m_sr = (m_sr & ~T) | (m_r[n] & T);
	1558	m_r[n] = (m_r[n] >> 1) | (m_r[n] << 31);
1455	1559	}
1456	1560
1457	1561	/*  RTE */
1458		const void RTE(sh4_state *sh4, const UINT16 opcode)
	1562	void sh34_base_device::RTE(const UINT16 opcode)
1459	1563	{
1460		sh4->delay = sh4->pc;
1461		sh4->pc = sh4->ea = sh4->spc;
1462		if ((sh4->device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
1463		sh4_syncronize_register_bank(sh4, (sh4->sr & sRB) >> 29);
1464		if ((sh4->ssr & sRB) != (sh4->sr & sRB))
1465		sh4_change_register_bank(sh4, sh4->ssr & sRB ? 1 : 0);
1466		sh4->sr = sh4->ssr;
1467		sh4->sh4_icount--;
1468		sh4_exception_recompute(sh4);
	1564	m_delay = m_pc;
	1565	m_pc = m_ea = m_spc;
	1566	if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
	1567	sh4_syncronize_register_bank((m_sr & sRB) >> 29);
	1568	if ((m_ssr & sRB) != (m_sr & sRB))
	1569	sh4_change_register_bank(m_ssr & sRB ? 1 : 0);
	1570	m_sr = m_ssr;
	1571	m_sh4_icount--;
	1572	sh4_exception_recompute();
1469	1573	}
1470	1574
1471	1575	/*  RTS */
1472		const void RTS(sh4_state *sh4, const UINT16 opcode)
	1576	void sh34_base_device::RTS(const UINT16 opcode)
1473	1577	{
1474		sh4->delay = sh4->pc;
1475		sh4->pc = sh4->ea = sh4->pr;
1476		sh4->sh4_icount--;
	1578	m_delay = m_pc;
	1579	m_pc = m_ea = m_pr;
	1580	m_sh4_icount--;
1477	1581	}
1478	1582
1479	1583	/*  SETT */
1480		const void SETT(sh4_state *sh4, const UINT16 opcode)
	1584	void sh34_base_device::SETT(const UINT16 opcode)
1481	1585	{
1482		sh4->sr |= T;
	1586	m_sr |= T;
1483	1587	}
1484	1588
1485	1589	/*  SHAL    Rn      (same as SHLL) */
1486		const void SHAL(sh4_state *sh4, const UINT16 opcode)
	1590	void sh34_base_device::SHAL(const UINT16 opcode)
1487	1591	{
1488	1592	UINT32 n = Rn;
1489	1593
1490		sh4->sr = (sh4->sr & ~T) | ((sh4->r[n] >> 31) & T);
1491		sh4->r[n] <<= 1;
	1594	m_sr = (m_sr & ~T) | ((m_r[n] >> 31) & T);
	1595	m_r[n] <<= 1;
1492	1596	}
1493	1597
1494	1598	/*  SHAR    Rn */
1495		const void SHAR(sh4_state *sh4, const UINT16 opcode)
	1599	void sh34_base_device::SHAR(const UINT16 opcode)
1496	1600	{
1497	1601	UINT32 n = Rn;
1498	1602
1499		sh4->sr = (sh4->sr & ~T) | (sh4->r[n] & T);
1500		sh4->r[n] = (UINT32)((INT32)sh4->r[n] >> 1);
	1603	m_sr = (m_sr & ~T) | (m_r[n] & T);
	1604	m_r[n] = (UINT32)((INT32)m_r[n] >> 1);
1501	1605	}
1502	1606
1503	1607	/*  SHLL    Rn      (same as SHAL) */
1504		const void SHLL(sh4_state *sh4, const UINT16 opcode)
	1608	void sh34_base_device::SHLL(const UINT16 opcode)
1505	1609	{
1506	1610	UINT32 n = Rn;
1507	1611
1508		sh4->sr = (sh4->sr & ~T) | ((sh4->r[n] >> 31) & T);
1509		sh4->r[n] <<= 1;
	1612	m_sr = (m_sr & ~T) | ((m_r[n] >> 31) & T);
	1613	m_r[n] <<= 1;
1510	1614	}
1511	1615
1512	1616	/*  SHLL2   Rn */
1513		const void SHLL2(sh4_state *sh4, const UINT16 opcode)
	1617	void sh34_base_device::SHLL2(const UINT16 opcode)
1514	1618	{
1515		sh4->r[Rn] <<= 2;
	1619	m_r[Rn] <<= 2;
1516	1620	}
1517	1621
1518	1622	/*  SHLL8   Rn */
1519		const void SHLL8(sh4_state *sh4, const UINT16 opcode)
	1623	void sh34_base_device::SHLL8(const UINT16 opcode)
1520	1624	{
1521		sh4->r[Rn] <<= 8;
	1625	m_r[Rn] <<= 8;
1522	1626	}
1523	1627
1524	1628	/*  SHLL16  Rn */
1525		const void SHLL16(sh4_state *sh4, const UINT16 opcode)
	1629	void sh34_base_device::SHLL16(const UINT16 opcode)
1526	1630	{
1527		sh4->r[Rn] <<= 16;
	1631	m_r[Rn] <<= 16;
1528	1632	}
1529	1633
1530	1634	/*  SHLR    Rn */
1531		const void SHLR(sh4_state *sh4, const UINT16 opcode)
	1635	void sh34_base_device::SHLR(const UINT16 opcode)
1532	1636	{
1533	1637	UINT32 n = Rn;
1534	1638
1535		sh4->sr = (sh4->sr & ~T) | (sh4->r[n] & T);
1536		sh4->r[n] >>= 1;
	1639	m_sr = (m_sr & ~T) | (m_r[n] & T);
	1640	m_r[n] >>= 1;
1537	1641	}
1538	1642
1539	1643	/*  SHLR2   Rn */
1540		const void SHLR2(sh4_state *sh4, const UINT16 opcode)
	1644	void sh34_base_device::SHLR2(const UINT16 opcode)
1541	1645	{
1542		sh4->r[Rn] >>= 2;
	1646	m_r[Rn] >>= 2;
1543	1647	}
1544	1648
1545	1649	/*  SHLR8   Rn */
1546		const void SHLR8(sh4_state *sh4, const UINT16 opcode)
	1650	void sh34_base_device::SHLR8(const UINT16 opcode)
1547	1651	{
1548		sh4->r[Rn] >>= 8;
	1652	m_r[Rn] >>= 8;
1549	1653	}
1550	1654
1551	1655	/*  SHLR16  Rn */
1552		const void SHLR16(sh4_state *sh4, const UINT16 opcode)
	1656	void sh34_base_device::SHLR16(const UINT16 opcode)
1553	1657	{
1554		sh4->r[Rn] >>= 16;
	1658	m_r[Rn] >>= 16;
1555	1659	}
1556	1660
1557	1661	/*  SLEEP */
1558		const void SLEEP(sh4_state *sh4, const UINT16 opcode)
	1662	void sh34_base_device::SLEEP(const UINT16 opcode)
1559	1663	{
1560	1664	/* 0 = normal mode */
1561	1665	/* 1 = enters into power-down mode */
1562	1666	/* 2 = go out the power-down mode after an exception */
1563		if(sh4->sleep_mode != 2)
1564		sh4->pc -= 2;
1565		sh4->sh4_icount -= 2;
	1667	if(m_sleep_mode != 2)
	1668	m_pc -= 2;
	1669	m_sh4_icount -= 2;
1566	1670	/* Wait_for_exception; */
1567		if(sh4->sleep_mode == 0)
1568		sh4->sleep_mode = 1;
1569		else if(sh4->sleep_mode == 2)
1570		sh4->sleep_mode = 0;
	1671	if(m_sleep_mode == 0)
	1672	m_sleep_mode = 1;
	1673	else if(m_sleep_mode == 2)
	1674	m_sleep_mode = 0;
1571	1675	}
1572	1676
1573	1677	/*  STC     SR,Rn */
1574		const void STCSR(sh4_state *sh4, const UINT16 opcode)
	1678	void sh34_base_device::STCSR(const UINT16 opcode)
1575	1679	{
1576		sh4->r[Rn] = sh4->sr;
	1680	m_r[Rn] = m_sr;
1577	1681	}
1578	1682
1579	1683	/*  STC     GBR,Rn */
1580		const void STCGBR(sh4_state *sh4, const UINT16 opcode)
	1684	void sh34_base_device::STCGBR(const UINT16 opcode)
1581	1685	{
1582		sh4->r[Rn] = sh4->gbr;
	1686	m_r[Rn] = m_gbr;
1583	1687	}
1584	1688
1585	1689	/*  STC     VBR,Rn */
1586		const void STCVBR(sh4_state *sh4, const UINT16 opcode)
	1690	void sh34_base_device::STCVBR(const UINT16 opcode)
1587	1691	{
1588		sh4->r[Rn] = sh4->vbr;
	1692	m_r[Rn] = m_vbr;
1589	1693	}
1590	1694
1591	1695	/*  STC.L   SR,@-Rn */
1592		const void STCMSR(sh4_state *sh4, const UINT16 opcode)
	1696	void sh34_base_device::STCMSR(const UINT16 opcode)
1593	1697	{
1594	1698	UINT32 n = Rn;
1595	1699
1596		sh4->r[n] -= 4;
1597		sh4->ea = sh4->r[n];
1598		WL(sh4, sh4->ea, sh4->sr );
1599		sh4->sh4_icount--;
	1700	m_r[n] -= 4;
	1701	m_ea = m_r[n];
	1702	WL(m_ea, m_sr );
	1703	m_sh4_icount--;
1600	1704	}
1601	1705
1602	1706	/*  STC.L   GBR,@-Rn */
1603		const void STCMGBR(sh4_state *sh4, const UINT16 opcode)
	1707	void sh34_base_device::STCMGBR(const UINT16 opcode)
1604	1708	{
1605	1709	UINT32 n = Rn;
1606	1710
1607		sh4->r[n] -= 4;
1608		sh4->ea = sh4->r[n];
1609		WL(sh4, sh4->ea, sh4->gbr );
1610		sh4->sh4_icount--;
	1711	m_r[n] -= 4;
	1712	m_ea = m_r[n];
	1713	WL(m_ea, m_gbr );
	1714	m_sh4_icount--;
1611	1715	}
1612	1716
1613	1717	/*  STC.L   VBR,@-Rn */
1614		const void STCMVBR(sh4_state *sh4, const UINT16 opcode)
	1718	void sh34_base_device::STCMVBR(const UINT16 opcode)
1615	1719	{
1616	1720	UINT32 n = Rn;
1617	1721
1618		sh4->r[n] -= 4;
1619		sh4->ea = sh4->r[n];
1620		WL(sh4, sh4->ea, sh4->vbr );
1621		sh4->sh4_icount--;
	1722	m_r[n] -= 4;
	1723	m_ea = m_r[n];
	1724	WL(m_ea, m_vbr );
	1725	m_sh4_icount--;
1622	1726	}
1623	1727
1624	1728	/*  STS     MACH,Rn */
1625		const void STSMACH(sh4_state *sh4, const UINT16 opcode)
	1729	void sh34_base_device::STSMACH(const UINT16 opcode)
1626	1730	{
1627		sh4->r[Rn] = sh4->mach;
	1731	m_r[Rn] = m_mach;
1628	1732	}
1629	1733
1630	1734	/*  STS     MACL,Rn */
1631		const void STSMACL(sh4_state *sh4, const UINT16 opcode)
	1735	void sh34_base_device::STSMACL(const UINT16 opcode)
1632	1736	{
1633		sh4->r[Rn] = sh4->macl;
	1737	m_r[Rn] = m_macl;
1634	1738	}
1635	1739
1636	1740	/*  STS     PR,Rn */
1637		const void STSPR(sh4_state *sh4, const UINT16 opcode)
	1741	void sh34_base_device::STSPR(const UINT16 opcode)
1638	1742	{
1639		sh4->r[Rn] = sh4->pr;
	1743	m_r[Rn] = m_pr;
1640	1744	}
1641	1745
1642	1746	/*  STS.L   MACH,@-Rn */
1643		const void STSMMACH(sh4_state *sh4, const UINT16 opcode)
	1747	void sh34_base_device::STSMMACH(const UINT16 opcode)
1644	1748	{
1645	1749	UINT32 n = Rn;
1646	1750
1647		sh4->r[n] -= 4;
1648		sh4->ea = sh4->r[n];
1649		WL(sh4, sh4->ea, sh4->mach );
	1751	m_r[n] -= 4;
	1752	m_ea = m_r[n];
	1753	WL(m_ea, m_mach );
1650	1754	}
1651	1755
1652	1756	/*  STS.L   MACL,@-Rn */
1653		const void STSMMACL(sh4_state *sh4, const UINT16 opcode)
	1757	void sh34_base_device::STSMMACL(const UINT16 opcode)
1654	1758	{
1655	1759	UINT32 n = Rn;
1656	1760
1657		sh4->r[n] -= 4;
1658		sh4->ea = sh4->r[n];
1659		WL(sh4, sh4->ea, sh4->macl );
	1761	m_r[n] -= 4;
	1762	m_ea = m_r[n];
	1763	WL(m_ea, m_macl );
1660	1764	}
1661	1765
1662	1766	/*  STS.L   PR,@-Rn */
1663		const void STSMPR(sh4_state *sh4, const UINT16 opcode)
	1767	void sh34_base_device::STSMPR(const UINT16 opcode)
1664	1768	{
1665	1769	UINT32 n = Rn;
1666	1770
1667		sh4->r[n] -= 4;
1668		sh4->ea = sh4->r[n];
1669		WL(sh4, sh4->ea, sh4->pr );
	1771	m_r[n] -= 4;
	1772	m_ea = m_r[n];
	1773	WL(m_ea, m_pr );
1670	1774	}
1671	1775
1672	1776	/*  SUB     Rm,Rn */
1673		const void SUB(sh4_state *sh4, const UINT16 opcode)
	1777	void sh34_base_device::SUB(const UINT16 opcode)
1674	1778	{
1675		sh4->r[Rn] -= sh4->r[Rm];
	1779	m_r[Rn] -= m_r[Rm];
1676	1780	}
1677	1781
1678	1782	/*  SUBC    Rm,Rn */
1679		const void SUBC(sh4_state *sh4, const UINT16 opcode)
	1783	void sh34_base_device::SUBC(const UINT16 opcode)
1680	1784	{
1681	1785	UINT32 m = Rm; UINT32 n = Rn;
1682	1786
1683	1787	UINT32 tmp0, tmp1;
1684	1788
1685		tmp1 = sh4->r[n] - sh4->r[m];
1686		tmp0 = sh4->r[n];
1687		sh4->r[n] = tmp1 - (sh4->sr & T);
	1789	tmp1 = m_r[n] - m_r[m];
	1790	tmp0 = m_r[n];
	1791	m_r[n] = tmp1 - (m_sr & T);
1688	1792	if (tmp0 < tmp1)
1689		sh4->sr |= T;
	1793	m_sr |= T;
1690	1794	else
1691		sh4->sr &= ~T;
1692		if (tmp1 < sh4->r[n])
1693		sh4->sr |= T;
	1795	m_sr &= ~T;
	1796	if (tmp1 < m_r[n])
	1797	m_sr |= T;
1694	1798	}
1695	1799
1696	1800	/*  SUBV    Rm,Rn */
1697		const void SUBV(sh4_state *sh4, const UINT16 opcode)
	1801	void sh34_base_device::SUBV(const UINT16 opcode)
1698	1802	{
1699	1803	UINT32 m = Rm; UINT32 n = Rn;
1700	1804
1701	1805	INT32 dest, src, ans;
1702	1806
1703		if ((INT32) sh4->r[n] >= 0)
	1807	if ((INT32) m_r[n] >= 0)
1704	1808	dest = 0;
1705	1809	else
1706	1810	dest = 1;
1707		if ((INT32) sh4->r[m] >= 0)
	1811	if ((INT32) m_r[m] >= 0)
1708	1812	src = 0;
1709	1813	else
1710	1814	src = 1;
1711	1815	src += dest;
1712		sh4->r[n] -= sh4->r[m];
1713		if ((INT32) sh4->r[n] >= 0)
	1816	m_r[n] -= m_r[m];
	1817	if ((INT32) m_r[n] >= 0)
1714	1818	ans = 0;
1715	1819	else
1716	1820	ans = 1;
r31221	r31222
1718	1822	if (src == 1)
1719	1823	{
1720	1824	if (ans == 1)
1721		sh4->sr |= T;
	1825	m_sr |= T;
1722	1826	else
1723		sh4->sr &= ~T;
	1827	m_sr &= ~T;
1724	1828	}
1725	1829	else
1726		sh4->sr &= ~T;
	1830	m_sr &= ~T;
1727	1831	}
1728	1832
1729	1833	/*  SWAP.B  Rm,Rn */
1730		const void SWAPB(sh4_state *sh4, const UINT16 opcode)
	1834	void sh34_base_device::SWAPB(const UINT16 opcode)
1731	1835	{
1732	1836	UINT32 m = Rm; UINT32 n = Rn;
1733	1837
1734	1838	UINT32 temp0, temp1;
1735	1839
1736		temp0 = sh4->r[m] & 0xffff0000;
1737		temp1 = (sh4->r[m] & 0x000000ff) << 8;
1738		sh4->r[n] = (sh4->r[m] >> 8) & 0x000000ff;
1739		sh4->r[n] = sh4->r[n] | temp1 | temp0;
	1840	temp0 = m_r[m] & 0xffff0000;
	1841	temp1 = (m_r[m] & 0x000000ff) << 8;
	1842	m_r[n] = (m_r[m] >> 8) & 0x000000ff;
	1843	m_r[n] = m_r[n] | temp1 | temp0;
1740	1844	}
1741	1845
1742	1846	/*  SWAP.W  Rm,Rn */
1743		const void SWAPW(sh4_state *sh4, const UINT16 opcode)
	1847	void sh34_base_device::SWAPW(const UINT16 opcode)
1744	1848	{
1745	1849	UINT32 m = Rm; UINT32 n = Rn;
1746	1850
1747	1851	UINT32 temp;
1748	1852
1749		temp = (sh4->r[m] >> 16) & 0x0000ffff;
1750		sh4->r[n] = (sh4->r[m] << 16) | temp;
	1853	temp = (m_r[m] >> 16) & 0x0000ffff;
	1854	m_r[n] = (m_r[m] << 16) | temp;
1751	1855	}
1752	1856
1753	1857	/*  TAS.B   @Rn */
1754		const void TAS(sh4_state *sh4, const UINT16 opcode)
	1858	void sh34_base_device::TAS(const UINT16 opcode)
1755	1859	{
1756	1860	UINT32 n = Rn;
1757	1861
1758	1862	UINT32 temp;
1759		sh4->ea = sh4->r[n];
	1863	m_ea = m_r[n];
1760	1864	/* Bus Lock enable */
1761		temp = RB(sh4, sh4->ea );
	1865	temp = RB( m_ea );
1762	1866	if (temp == 0)
1763		sh4->sr |= T;
	1867	m_sr |= T;
1764	1868	else
1765		sh4->sr &= ~T;
	1869	m_sr &= ~T;
1766	1870	temp |= 0x80;
1767	1871	/* Bus Lock disable */
1768		WB(sh4, sh4->ea, temp );
1769		sh4->sh4_icount -= 3;
	1872	WB(m_ea, temp );
	1873	m_sh4_icount -= 3;
1770	1874	}
1771	1875
1772	1876	/*  TRAPA   #imm */
1773		const void TRAPA(sh4_state *sh4, const UINT16 opcode)
	1877	void sh34_base_device::TRAPA(const UINT16 opcode)
1774	1878	{
1775	1879	UINT32 imm = opcode & 0xff;
1776	1880
1777		if (sh4->cpu_type == CPU_TYPE_SH4)
	1881	if (m_cpu_type == CPU_TYPE_SH4)
1778	1882	{
1779		sh4->m[TRA] = imm << 2;
	1883	m_m[TRA] = imm << 2;
1780	1884	}
1781	1885	else /* SH3 */
1782	1886	{
1783		sh4->m_sh3internal_upper[SH3_TRA_ADDR] = imm << 2;
	1887	m_sh3internal_upper[SH3_TRA_ADDR] = imm << 2;
1784	1888	}
1785	1889
1786	1890
1787		sh4->ssr = sh4->sr;
1788		sh4->spc = sh4->pc;
1789		sh4->sgr = sh4->r[15];
	1891	m_ssr = m_sr;
	1892	m_spc = m_pc;
	1893	m_sgr = m_r[15];
1790	1894
1791		sh4->sr |= MD;
1792		if ((sh4->device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
1793		sh4_syncronize_register_bank(sh4, (sh4->sr & sRB) >> 29);
1794		if (!(sh4->sr & sRB))
1795		sh4_change_register_bank(sh4, 1);
1796		sh4->sr |= sRB;
1797		sh4->sr |= BL;
1798		sh4_exception_recompute(sh4);
	1895	m_sr |= MD;
	1896	if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
	1897	sh4_syncronize_register_bank((m_sr & sRB) >> 29);
	1898	if (!(m_sr & sRB))
	1899	sh4_change_register_bank(1);
	1900	m_sr |= sRB;
	1901	m_sr |= BL;
	1902	sh4_exception_recompute();
1799	1903
1800		if (sh4->cpu_type == CPU_TYPE_SH4)
	1904	if (m_cpu_type == CPU_TYPE_SH4)
1801	1905	{
1802		sh4->m[EXPEVT] = 0x00000160;
	1906	m_m[EXPEVT] = 0x00000160;
1803	1907	}
1804	1908	else /* SH3 */
1805	1909	{
1806		sh4->m_sh3internal_upper[SH3_EXPEVT_ADDR] = 0x00000160;
	1910	m_sh3internal_upper[SH3_EXPEVT_ADDR] = 0x00000160;
1807	1911	}
1808	1912
1809		sh4->pc = sh4->vbr + 0x00000100;
	1913	m_pc = m_vbr + 0x00000100;
1810	1914
1811		sh4->sh4_icount -= 7;
	1915	m_sh4_icount -= 7;
1812	1916	}
1813	1917
1814	1918	/*  TST     Rm,Rn */
1815		const void TST(sh4_state *sh4, const UINT16 opcode)
	1919	void sh34_base_device::TST(const UINT16 opcode)
1816	1920	{
1817		if ((sh4->r[Rn] & sh4->r[Rm]) == 0)
1818		sh4->sr |= T;
	1921	if ((m_r[Rn] & m_r[Rm]) == 0)
	1922	m_sr |= T;
1819	1923	else
1820		sh4->sr &= ~T;
	1924	m_sr &= ~T;
1821	1925	}
1822	1926
1823	1927	/*  TST     #imm,R0 */
1824		const void TSTI(sh4_state *sh4, const UINT16 opcode)
	1928	void sh34_base_device::TSTI(const UINT16 opcode)
1825	1929	{
1826	1930	UINT32 imm = opcode & 0xff;
1827	1931
1828		if ((imm & sh4->r[0]) == 0)
1829		sh4->sr |= T;
	1932	if ((imm & m_r[0]) == 0)
	1933	m_sr |= T;
1830	1934	else
1831		sh4->sr &= ~T;
	1935	m_sr &= ~T;
1832	1936	}
1833	1937
1834	1938	/*  TST.B   #imm,@(R0,GBR) */
1835		const void TSTM(sh4_state *sh4, const UINT16 opcode)
	1939	void sh34_base_device::TSTM(const UINT16 opcode)
1836	1940	{
1837	1941	UINT32 imm = opcode & 0xff;
1838	1942
1839		sh4->ea = sh4->gbr + sh4->r[0];
1840		if ((imm & RB(sh4,  sh4->ea )) == 0)
1841		sh4->sr |= T;
	1943	m_ea = m_gbr + m_r[0];
	1944	if ((imm & RB( m_ea )) == 0)
	1945	m_sr |= T;
1842	1946	else
1843		sh4->sr &= ~T;
1844		sh4->sh4_icount -= 2;
	1947	m_sr &= ~T;
	1948	m_sh4_icount -= 2;
1845	1949	}
1846	1950
1847	1951	/*  XOR     Rm,Rn */
1848		const void XOR(sh4_state *sh4, const UINT16 opcode)
	1952	void sh34_base_device::XOR(const UINT16 opcode)
1849	1953	{
1850		sh4->r[Rn] ^= sh4->r[Rm];
	1954	m_r[Rn] ^= m_r[Rm];
1851	1955	}
1852	1956
1853	1957	/*  XOR     #imm,R0 */
1854		const void XORI(sh4_state *sh4, const UINT16 opcode)
	1958	void sh34_base_device::XORI(const UINT16 opcode)
1855	1959	{
1856	1960	UINT32 imm = opcode & 0xff;
1857		sh4->r[0] ^= imm;
	1961	m_r[0] ^= imm;
1858	1962	}
1859	1963
1860	1964	/*  XOR.B   #imm,@(R0,GBR) */
1861		const void XORM(sh4_state *sh4, const UINT16 opcode)
	1965	void sh34_base_device::XORM(const UINT16 opcode)
1862	1966	{
1863	1967	UINT32 imm = opcode & 0xff;
1864	1968	UINT32 temp;
1865	1969
1866		sh4->ea = sh4->gbr + sh4->r[0];
1867		temp = RB(sh4,  sh4->ea );
	1970	m_ea = m_gbr + m_r[0];
	1971	temp = RB( m_ea );
1868	1972	temp ^= imm;
1869		WB(sh4, sh4->ea, temp );
1870		sh4->sh4_icount -= 2;
	1973	WB(m_ea, temp );
	1974	m_sh4_icount -= 2;
1871	1975	}
1872	1976
1873	1977	/*  XTRCT   Rm,Rn */
1874		const void XTRCT(sh4_state *sh4, const UINT16 opcode)
	1978	void sh34_base_device::XTRCT(const UINT16 opcode)
1875	1979	{
1876	1980	UINT32 m = Rm; UINT32 n = Rn;
1877	1981
1878	1982	UINT32 temp;
1879	1983
1880		temp = (sh4->r[m] << 16) & 0xffff0000;
1881		sh4->r[n] = (sh4->r[n] >> 16) & 0x0000ffff;
1882		sh4->r[n] |= temp;
	1984	temp = (m_r[m] << 16) & 0xffff0000;
	1985	m_r[n] = (m_r[n] >> 16) & 0x0000ffff;
	1986	m_r[n] |= temp;
1883	1987	}
1884	1988
1885	1989	/*  STC     SSR,Rn */
1886		const void STCSSR(sh4_state *sh4, const UINT16 opcode)
	1990	void sh34_base_device::STCSSR(const UINT16 opcode)
1887	1991	{
1888		sh4->r[Rn] = sh4->ssr;
	1992	m_r[Rn] = m_ssr;
1889	1993	}
1890	1994
1891	1995	/*  STC     SPC,Rn */
1892		const void STCSPC(sh4_state *sh4, const UINT16 opcode)
	1996	void sh34_base_device::STCSPC(const UINT16 opcode)
1893	1997	{
1894		sh4->r[Rn] = sh4->spc;
	1998	m_r[Rn] = m_spc;
1895	1999	}
1896	2000
1897	2001	/*  STC     SGR,Rn */
1898		const void STCSGR(sh4_state *sh4, const UINT16 opcode)
	2002	void sh34_base_device::STCSGR(const UINT16 opcode)
1899	2003	{
1900		sh4->r[Rn] = sh4->sgr;
	2004	m_r[Rn] = m_sgr;
1901	2005	}
1902	2006
1903	2007	/*  STS     FPUL,Rn */
1904		const void STSFPUL(sh4_state *sh4, const UINT16 opcode)
	2008	void sh34_base_device::STSFPUL(const UINT16 opcode)
1905	2009	{
1906		sh4->r[Rn] = sh4->fpul;
	2010	m_r[Rn] = m_fpul;
1907	2011	}
1908	2012
1909	2013	/*  STS     FPSCR,Rn */
1910		const void STSFPSCR(sh4_state *sh4, const UINT16 opcode)
	2014	void sh34_base_device::STSFPSCR(const UINT16 opcode)
1911	2015	{
1912		sh4->r[Rn] = sh4->fpscr & 0x003FFFFF;
	2016	m_r[Rn] = m_fpscr & 0x003FFFFF;
1913	2017	}
1914	2018
1915	2019	/*  STC     DBR,Rn */
1916		const void STCDBR(sh4_state *sh4, const UINT16 opcode)
	2020	void sh34_base_device::STCDBR(const UINT16 opcode)
1917	2021	{
1918		sh4->r[Rn] = sh4->dbr;
	2022	m_r[Rn] = m_dbr;
1919	2023	}
1920	2024
1921	2025	/*  STCRBANK   Rm_BANK,Rn */
1922		const void STCRBANK(sh4_state *sh4, const UINT16 opcode)
	2026	void sh34_base_device::STCRBANK(const UINT16 opcode)
1923	2027	{
1924	2028	UINT32 m = Rm;
1925	2029
1926		sh4->r[Rn] = sh4->rbnk[sh4->sr&sRB ? 0 : 1][m & 7];
	2030	m_r[Rn] = m_rbnk[m_sr&sRB ? 0 : 1][m & 7];
1927	2031	}
1928	2032
1929	2033	/*  STCMRBANK   Rm_BANK,@-Rn */
1930		const void STCMRBANK(sh4_state *sh4, const UINT16 opcode)
	2034	void sh34_base_device::STCMRBANK(const UINT16 opcode)
1931	2035	{
1932	2036	UINT32 m = Rm; UINT32 n = Rn;
1933	2037
1934		sh4->r[n] -= 4;
1935		sh4->ea = sh4->r[n];
1936		WL(sh4, sh4->ea, sh4->rbnk[sh4->sr&sRB ? 0 : 1][m & 7]);
1937		sh4->sh4_icount--;
	2038	m_r[n] -= 4;
	2039	m_ea = m_r[n];
	2040	WL(m_ea, m_rbnk[m_sr&sRB ? 0 : 1][m & 7]);
	2041	m_sh4_icount--;
1938	2042	}
1939	2043
1940	2044	/*  MOVCA.L     R0,@Rn */
1941		const void MOVCAL(sh4_state *sh4, const UINT16 opcode)
	2045	void sh34_base_device::MOVCAL(const UINT16 opcode)
1942	2046	{
1943		sh4->ea = sh4->r[Rn];
1944		WL(sh4, sh4->ea, sh4->r[0] );
	2047	m_ea = m_r[Rn];
	2048	WL(m_ea, m_r[0] );
1945	2049	}
1946	2050
1947		const void CLRS(sh4_state *sh4, const UINT16 opcode)
	2051	void sh34_base_device::CLRS(const UINT16 opcode)
1948	2052	{
1949		sh4->sr &= ~S;
	2053	m_sr &= ~S;
1950	2054	}
1951	2055
1952		const void SETS(sh4_state *sh4, const UINT16 opcode)
	2056	void sh34_base_device::SETS(const UINT16 opcode)
1953	2057	{
1954		sh4->sr |= S;
	2058	m_sr |= S;
1955	2059	}
1956	2060
1957	2061	/*  STS.L   SGR,@-Rn */
1958		const void STCMSGR(sh4_state *sh4, const UINT16 opcode)
	2062	void sh34_base_device::STCMSGR(const UINT16 opcode)
1959	2063	{
1960	2064	UINT32 n = Rn;
1961	2065
1962		sh4->r[n] -= 4;
1963		sh4->ea = sh4->r[n];
1964		WL(sh4, sh4->ea, sh4->sgr );
	2066	m_r[n] -= 4;
	2067	m_ea = m_r[n];
	2068	WL(m_ea, m_sgr );
1965	2069	}
1966	2070
1967	2071	/*  STS.L   FPUL,@-Rn */
1968		const void STSMFPUL(sh4_state *sh4, const UINT16 opcode)
	2072	void sh34_base_device::STSMFPUL(const UINT16 opcode)
1969	2073	{
1970	2074	UINT32 n = Rn;
1971	2075
1972		sh4->r[n] -= 4;
1973		sh4->ea = sh4->r[n];
1974		WL(sh4, sh4->ea, sh4->fpul );
	2076	m_r[n] -= 4;
	2077	m_ea = m_r[n];
	2078	WL(m_ea, m_fpul );
1975	2079	}
1976	2080
1977	2081	/*  STS.L   FPSCR,@-Rn */
1978		const void STSMFPSCR(sh4_state *sh4, const UINT16 opcode)
	2082	void sh34_base_device::STSMFPSCR(const UINT16 opcode)
1979	2083	{
1980	2084	UINT32 n = Rn;
1981	2085
1982		sh4->r[n] -= 4;
1983		sh4->ea = sh4->r[n];
1984		WL(sh4, sh4->ea, sh4->fpscr & 0x003FFFFF);
	2086	m_r[n] -= 4;
	2087	m_ea = m_r[n];
	2088	WL(m_ea, m_fpscr & 0x003FFFFF);
1985	2089	}
1986	2090
1987	2091	/*  STC.L   DBR,@-Rn */
1988		const void STCMDBR(sh4_state *sh4, const UINT16 opcode)
	2092	void sh34_base_device::STCMDBR(const UINT16 opcode)
1989	2093	{
1990	2094	UINT32 n = Rn;
1991	2095
1992		sh4->r[n] -= 4;
1993		sh4->ea = sh4->r[n];
1994		WL(sh4, sh4->ea, sh4->dbr );
	2096	m_r[n] -= 4;
	2097	m_ea = m_r[n];
	2098	WL(m_ea, m_dbr );
1995	2099	}
1996	2100
1997	2101	/*  STC.L   SSR,@-Rn */
1998		const void STCMSSR(sh4_state *sh4, const UINT16 opcode)
	2102	void sh34_base_device::STCMSSR(const UINT16 opcode)
1999	2103	{
2000	2104	UINT32 n = Rn;
2001	2105
2002		sh4->r[n] -= 4;
2003		sh4->ea = sh4->r[n];
2004		WL(sh4, sh4->ea, sh4->ssr );
	2106	m_r[n] -= 4;
	2107	m_ea = m_r[n];
	2108	WL(m_ea, m_ssr );
2005	2109	}
2006	2110
2007	2111	/*  STC.L   SPC,@-Rn */
2008		const void STCMSPC(sh4_state *sh4, const UINT16 opcode)
	2112	void sh34_base_device::STCMSPC(const UINT16 opcode)
2009	2113	{
2010	2114	UINT32 n = Rn;
2011	2115
2012		sh4->r[n] -= 4;
2013		sh4->ea = sh4->r[n];
2014		WL(sh4, sh4->ea, sh4->spc );
	2116	m_r[n] -= 4;
	2117	m_ea = m_r[n];
	2118	WL(m_ea, m_spc );
2015	2119	}
2016	2120
2017	2121	/*  LDS.L   @Rm+,FPUL */
2018		const void LDSMFPUL(sh4_state *sh4, const UINT16 opcode)
	2122	void sh34_base_device::LDSMFPUL(const UINT16 opcode)
2019	2123	{
2020		sh4->ea = sh4->r[Rn];
2021		sh4->fpul = RL(sh4, sh4->ea );
2022		sh4->r[Rn] += 4;
	2124	m_ea = m_r[Rn];
	2125	m_fpul = RL(m_ea );
	2126	m_r[Rn] += 4;
2023	2127	}
2024	2128
2025	2129	/*  LDS.L   @Rm+,FPSCR */
2026		const void LDSMFPSCR(sh4_state *sh4, const UINT16 opcode)
	2130	void sh34_base_device::LDSMFPSCR(const UINT16 opcode)
2027	2131	{
2028	2132	UINT32 s;
2029	2133
2030		s = sh4->fpscr;
2031		sh4->ea = sh4->r[Rn];
2032		sh4->fpscr = RL(sh4, sh4->ea );
2033		sh4->fpscr &= 0x003FFFFF;
2034		sh4->r[Rn] += 4;
2035		if ((s & FR) != (sh4->fpscr & FR))
2036		sh4_swap_fp_registers(sh4);
	2134	s = m_fpscr;
	2135	m_ea = m_r[Rn];
	2136	m_fpscr = RL(m_ea );
	2137	m_fpscr &= 0x003FFFFF;
	2138	m_r[Rn] += 4;
	2139	if ((s & FR) != (m_fpscr & FR))
	2140	sh4_swap_fp_registers();
2037	2141	#ifdef LSB_FIRST
2038		if ((s & PR) != (sh4->fpscr & PR))
2039		sh4_swap_fp_couples(sh4);
	2142	if ((s & PR) != (m_fpscr & PR))
	2143	sh4_swap_fp_couples();
2040	2144	#endif
2041		sh4->fpu_sz = (sh4->fpscr & SZ) ? 1 : 0;
2042		sh4->fpu_pr = (sh4->fpscr & PR) ? 1 : 0;
	2145	m_fpu_sz = (m_fpscr & SZ) ? 1 : 0;
	2146	m_fpu_pr = (m_fpscr & PR) ? 1 : 0;
2043	2147	}
2044	2148
2045	2149	/*  LDC.L   @Rm+,DBR */
2046		const void LDCMDBR(sh4_state *sh4, const UINT16 opcode)
	2150	void sh34_base_device::LDCMDBR(const UINT16 opcode)
2047	2151	{
2048		sh4->ea = sh4->r[Rn];
2049		sh4->dbr = RL(sh4, sh4->ea );
2050		sh4->r[Rn] += 4;
	2152	m_ea = m_r[Rn];
	2153	m_dbr = RL(m_ea );
	2154	m_r[Rn] += 4;
2051	2155	}
2052	2156
2053	2157	/*  LDC.L   @Rn+,Rm_BANK */
2054		const void LDCMRBANK(sh4_state *sh4, const UINT16 opcode)
	2158	void sh34_base_device::LDCMRBANK(const UINT16 opcode)
2055	2159	{
2056	2160	UINT32 m = Rm; UINT32 n = Rn;
2057	2161
2058		sh4->ea = sh4->r[n];
2059		sh4->rbnk[sh4->sr&sRB ? 0 : 1][m & 7] = RL(sh4, sh4->ea );
2060		sh4->r[n] += 4;
	2162	m_ea = m_r[n];
	2163	m_rbnk[m_sr&sRB ? 0 : 1][m & 7] = RL(m_ea );
	2164	m_r[n] += 4;
2061	2165	}
2062	2166
2063	2167	/*  LDC.L   @Rm+,SSR */
2064		const void LDCMSSR(sh4_state *sh4, const UINT16 opcode)
	2168	void sh34_base_device::LDCMSSR(const UINT16 opcode)
2065	2169	{
2066		sh4->ea = sh4->r[Rn];
2067		sh4->ssr = RL(sh4, sh4->ea );
2068		sh4->r[Rn] += 4;
	2170	m_ea = m_r[Rn];
	2171	m_ssr = RL(m_ea );
	2172	m_r[Rn] += 4;
2069	2173	}
2070	2174
2071	2175	/*  LDC.L   @Rm+,SPC */
2072		const void LDCMSPC(sh4_state *sh4, const UINT16 opcode)
	2176	void sh34_base_device::LDCMSPC(const UINT16 opcode)
2073	2177	{
2074		sh4->ea = sh4->r[Rn];
2075		sh4->spc = RL(sh4, sh4->ea );
2076		sh4->r[Rn] += 4;
	2178	m_ea = m_r[Rn];
	2179	m_spc = RL(m_ea );
	2180	m_r[Rn] += 4;
2077	2181	}
2078	2182
2079	2183	/*  LDS     Rm,FPUL */
2080		const void LDSFPUL(sh4_state *sh4, const UINT16 opcode)
	2184	void sh34_base_device::LDSFPUL(const UINT16 opcode)
2081	2185	{
2082		sh4->fpul = sh4->r[Rn];
	2186	m_fpul = m_r[Rn];
2083	2187	}
2084	2188
2085	2189	/*  LDS     Rm,FPSCR */
2086		const void LDSFPSCR(sh4_state *sh4, const UINT16 opcode)
	2190	void sh34_base_device::LDSFPSCR(const UINT16 opcode)
2087	2191	{
2088	2192	UINT32 s;
2089	2193
2090		s = sh4->fpscr;
2091		sh4->fpscr = sh4->r[Rn] & 0x003FFFFF;
2092		if ((s & FR) != (sh4->fpscr & FR))
2093		sh4_swap_fp_registers(sh4);
	2194	s = m_fpscr;
	2195	m_fpscr = m_r[Rn] & 0x003FFFFF;
	2196	if ((s & FR) != (m_fpscr & FR))
	2197	sh4_swap_fp_registers();
2094	2198	#ifdef LSB_FIRST
2095		if ((s & PR) != (sh4->fpscr & PR))
2096		sh4_swap_fp_couples(sh4);
	2199	if ((s & PR) != (m_fpscr & PR))
	2200	sh4_swap_fp_couples();
2097	2201	#endif
2098		sh4->fpu_sz = (sh4->fpscr & SZ) ? 1 : 0;
2099		sh4->fpu_pr = (sh4->fpscr & PR) ? 1 : 0;
	2202	m_fpu_sz = (m_fpscr & SZ) ? 1 : 0;
	2203	m_fpu_pr = (m_fpscr & PR) ? 1 : 0;
2100	2204	}
2101	2205
2102	2206	/*  LDC     Rm,DBR */
2103		const void LDCDBR(sh4_state *sh4, const UINT16 opcode)
	2207	void sh34_base_device::LDCDBR(const UINT16 opcode)
2104	2208	{
2105		sh4->dbr = sh4->r[Rn];
	2209	m_dbr = m_r[Rn];
2106	2210	}
2107	2211
2108	2212	/*  SHAD    Rm,Rn */
2109		const void SHAD(sh4_state *sh4, const UINT16 opcode)
	2213	void sh34_base_device::SHAD(const UINT16 opcode)
2110	2214	{
2111	2215	UINT32 m = Rm; UINT32 n = Rn;
2112	2216
2113		if ((sh4->r[m] & 0x80000000) == 0)
2114		sh4->r[n] = sh4->r[n] << (sh4->r[m] & 0x1F);
2115		else if ((sh4->r[m] & 0x1F) == 0) {
2116		if ((sh4->r[n] & 0x80000000) == 0)
2117		sh4->r[n] = 0;
	2217	if ((m_r[m] & 0x80000000) == 0)
	2218	m_r[n] = m_r[n] << (m_r[m] & 0x1F);
	2219	else if ((m_r[m] & 0x1F) == 0) {
	2220	if ((m_r[n] & 0x80000000) == 0)
	2221	m_r[n] = 0;
2118	2222	else
2119		sh4->r[n] = 0xFFFFFFFF;
	2223	m_r[n] = 0xFFFFFFFF;
2120	2224	} else
2121		sh4->r[n]=(INT32)sh4->r[n] >> ((~sh4->r[m] & 0x1F)+1);
	2225	m_r[n]=(INT32)m_r[n] >> ((~m_r[m] & 0x1F)+1);
2122	2226	}
2123	2227
2124	2228	/*  SHLD    Rm,Rn */
2125		const void SHLD(sh4_state *sh4, const UINT16 opcode)
	2229	void sh34_base_device::SHLD(const UINT16 opcode)
2126	2230	{
2127	2231	UINT32 m = Rm; UINT32 n = Rn;
2128	2232
2129		if ((sh4->r[m] & 0x80000000) == 0)
2130		sh4->r[n] = sh4->r[n] << (sh4->r[m] & 0x1F);
2131		else if ((sh4->r[m] & 0x1F) == 0)
2132		sh4->r[n] = 0;
	2233	if ((m_r[m] & 0x80000000) == 0)
	2234	m_r[n] = m_r[n] << (m_r[m] & 0x1F);
	2235	else if ((m_r[m] & 0x1F) == 0)
	2236	m_r[n] = 0;
2133	2237	else
2134		sh4->r[n] = sh4->r[n] >> ((~sh4->r[m] & 0x1F)+1);
	2238	m_r[n] = m_r[n] >> ((~m_r[m] & 0x1F)+1);
2135	2239	}
2136	2240
2137	2241	/*  LDCRBANK   Rn,Rm_BANK */
2138		const void LDCRBANK(sh4_state *sh4, const UINT16 opcode)
	2242	void sh34_base_device::LDCRBANK(const UINT16 opcode)
2139	2243	{
2140	2244	UINT32 m = Rm;
2141	2245
2142		sh4->rbnk[sh4->sr&sRB ? 0 : 1][m & 7] = sh4->r[Rn];
	2246	m_rbnk[m_sr&sRB ? 0 : 1][m & 7] = m_r[Rn];
2143	2247	}
2144	2248
2145	2249	/*  LDC     Rm,SSR */
2146		const void LDCSSR(sh4_state *sh4, const UINT16 opcode)
	2250	void sh34_base_device::LDCSSR(const UINT16 opcode)
2147	2251	{
2148		sh4->ssr = sh4->r[Rn];
	2252	m_ssr = m_r[Rn];
2149	2253	}
2150	2254
2151	2255	/*  LDC     Rm,SPC */
2152		const void LDCSPC(sh4_state *sh4, const UINT16 opcode)
	2256	void sh34_base_device::LDCSPC(const UINT16 opcode)
2153	2257	{
2154		sh4->spc = sh4->r[Rn];
	2258	m_spc = m_r[Rn];
2155	2259	}
2156	2260
2157	2261	/*  PREF     @Rn */
2158		const void PREFM(sh4_state *sh4, const UINT16 opcode)
	2262	void sh34_base_device::PREFM(const UINT16 opcode)
2159	2263	{
2160	2264	int a;
2161	2265	UINT32 addr,dest,sq;
2162	2266
2163		addr = sh4->r[Rn]; // address
	2267	addr = m_r[Rn]; // address
2164	2268	if ((addr >= 0xE0000000) && (addr <= 0xE3FFFFFF))
2165	2269	{
2166		if (sh4->sh4_mmu_enabled)
	2270	if (m_sh4_mmu_enabled)
2167	2271	{
2168	2272	addr = addr & 0xFFFFFFE0;
2169		dest = sh4_getsqremap(sh4, addr); // good enough for naomi-gd rom, probably not much else
	2273	dest = sh4_getsqremap(addr); // good enough for naomi-gd rom, probably not much else
2170	2274
2171	2275	}
2172	2276	else
r31221	r31222
2175	2279	dest = addr & 0x03FFFFE0;
2176	2280	if (sq == 0)
2177	2281	{
2178		if (sh4->cpu_type == CPU_TYPE_SH4)
	2282	if (m_cpu_type == CPU_TYPE_SH4)
2179	2283	{
2180		dest |= (sh4->m[QACR0] & 0x1C) << 24;
	2284	dest |= (m_m[QACR0] & 0x1C) << 24;
2181	2285	}
2182	2286	else
2183	2287	{
2184		fatalerror("sh4->cpu_type != CPU_TYPE_SH4 but access internal regs\n");
	2288	fatalerror("m_cpu_type != CPU_TYPE_SH4 but access internal regs\n");
2185	2289	}
2186	2290	}
2187	2291	else
2188	2292	{
2189		if (sh4->cpu_type == CPU_TYPE_SH4)
	2293	if (m_cpu_type == CPU_TYPE_SH4)
2190	2294	{
2191		dest |= (sh4->m[QACR1] & 0x1C) << 24;
	2295	dest |= (m_m[QACR1] & 0x1C) << 24;
2192	2296	}
2193	2297	else
2194	2298	{
2195		fatalerror("sh4->cpu_type != CPU_TYPE_SH4 but access internal regs\n");
	2299	fatalerror("m_cpu_type != CPU_TYPE_SH4 but access internal regs\n");
2196	2300	}
2197	2301
2198	2302	}
r31221	r31222
2202	2306	for (a = 0;a < 4;a++)
2203	2307	{
2204	2308	// shouldn't be causing a memory read, should store sq writes in registers.
2205		sh4->program->write_qword(dest, sh4->program->read_qword(addr));
	2309	m_program->write_qword(dest, m_program->read_qword(addr));
2206	2310	addr += 8;
2207	2311	dest += 8;
2208	2312	}
r31221	r31222
2233	2337	/*  FMOV    @Rm+,DRn PR=0 SZ=1 1111nnn0mmmm1001 */
2234	2338	/*  FMOV    @Rm+,XDn PR=0 SZ=1 1111nnn1mmmm1001 */
2235	2339	/*  FMOV    @Rm+,XDn PR=1      1111nnn1mmmm1001 */
2236		const void FMOVMRIFR(sh4_state *sh4, const UINT16 opcode)
	2340	void sh34_base_device::FMOVMRIFR(const UINT16 opcode)
2237	2341	{
2238	2342	UINT32 m = Rm; UINT32 n = Rn;
2239	2343
2240		if (sh4->fpu_pr) { /* PR = 1 */
	2344	if (m_fpu_pr) { /* PR = 1 */
2241	2345	n = n & 14;
2242		sh4->ea = sh4->r[m];
2243		sh4->r[m] += 8;
2244		sh4->xf[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(sh4, sh4->ea );
2245		sh4->xf[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(sh4, sh4->ea+4 );
	2346	m_ea = m_r[m];
	2347	m_r[m] += 8;
	2348	m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(m_ea );
	2349	m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(m_ea+4 );
2246	2350	} else {              /* PR = 0 */
2247		if (sh4->fpu_sz) { /* SZ = 1 */
	2351	if (m_fpu_sz) { /* SZ = 1 */
2248	2352	if (n & 1) {
2249	2353	n = n & 14;
2250		sh4->ea = sh4->r[m];
2251		sh4->xf[n] = RL(sh4, sh4->ea );
2252		sh4->r[m] += 4;
2253		sh4->xf[n+1] = RL(sh4, sh4->ea+4 );
2254		sh4->r[m] += 4;
	2354	m_ea = m_r[m];
	2355	m_xf[n] = RL(m_ea );
	2356	m_r[m] += 4;
	2357	m_xf[n+1] = RL(m_ea+4 );
	2358	m_r[m] += 4;
2255	2359	} else {
2256		sh4->ea = sh4->r[m];
2257		sh4->fr[n] = RL(sh4, sh4->ea );
2258		sh4->r[m] += 4;
2259		sh4->fr[n+1] = RL(sh4, sh4->ea+4 );
2260		sh4->r[m] += 4;
	2360	m_ea = m_r[m];
	2361	m_fr[n] = RL(m_ea );
	2362	m_r[m] += 4;
	2363	m_fr[n+1] = RL(m_ea+4 );
	2364	m_r[m] += 4;
2261	2365	}
2262	2366	} else {              /* SZ = 0 */
2263		sh4->ea = sh4->r[m];
2264		sh4->fr[n] = RL(sh4, sh4->ea );
2265		sh4->r[m] += 4;
	2367	m_ea = m_r[m];
	2368	m_fr[n] = RL(m_ea );
	2369	m_r[m] += 4;
2266	2370	}
2267	2371	}
2268	2372	}
r31221	r31222
2271	2375	/*  FMOV    DRm,@Rn PR=0 SZ=1 1111nnnnmmm01010 */
2272	2376	/*  FMOV    XDm,@Rn PR=0 SZ=1 1111nnnnmmm11010 */
2273	2377	/*  FMOV    XDm,@Rn PR=1      1111nnnnmmm11010 */
2274		const void FMOVFRMR(sh4_state *sh4, const UINT16 opcode)
	2378	void sh34_base_device::FMOVFRMR(const UINT16 opcode)
2275	2379	{
2276	2380	UINT32 m = Rm; UINT32 n = Rn;
2277	2381
2278		if (sh4->fpu_pr) { /* PR = 1 */
	2382	if (m_fpu_pr) { /* PR = 1 */
2279	2383	m= m & 14;
2280		sh4->ea = sh4->r[n];
2281		WL(sh4, sh4->ea,sh4->xf[m+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] );
2282		WL(sh4, sh4->ea+4,sh4->xf[m+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] );
	2384	m_ea = m_r[n];
	2385	WL(m_ea,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] );
	2386	WL(m_ea+4,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] );
2283	2387	} else {              /* PR = 0 */
2284		if (sh4->fpu_sz) { /* SZ = 1 */
	2388	if (m_fpu_sz) { /* SZ = 1 */
2285	2389	if (m & 1) {
2286	2390	m= m & 14;
2287		sh4->ea = sh4->r[n];
2288		WL(sh4, sh4->ea,sh4->xf[m] );
2289		WL(sh4, sh4->ea+4,sh4->xf[m+1] );
	2391	m_ea = m_r[n];
	2392	WL(m_ea,m_xf[m] );
	2393	WL(m_ea+4,m_xf[m+1] );
2290	2394	} else {
2291		sh4->ea = sh4->r[n];
2292		WL(sh4, sh4->ea,sh4->fr[m] );
2293		WL(sh4, sh4->ea+4,sh4->fr[m+1] );
	2395	m_ea = m_r[n];
	2396	WL(m_ea,m_fr[m] );
	2397	WL(m_ea+4,m_fr[m+1] );
2294	2398	}
2295	2399	} else {              /* SZ = 0 */
2296		sh4->ea = sh4->r[n];
2297		WL(sh4, sh4->ea,sh4->fr[m] );
	2400	m_ea = m_r[n];
	2401	WL(m_ea,m_fr[m] );
2298	2402	}
2299	2403	}
2300	2404	}
r31221	r31222
2303	2407	/*  FMOV    DRm,@-Rn PR=0 SZ=1 1111nnnnmmm01011 */
2304	2408	/*  FMOV    XDm,@-Rn PR=0 SZ=1 1111nnnnmmm11011 */
2305	2409	/*  FMOV    XDm,@-Rn PR=1      1111nnnnmmm11011 */
2306		const void FMOVFRMDR(sh4_state *sh4, const UINT16 opcode)
	2410	void sh34_base_device::FMOVFRMDR(const UINT16 opcode)
2307	2411	{
2308	2412	UINT32 m = Rm; UINT32 n = Rn;
2309	2413
2310		if (sh4->fpu_pr) { /* PR = 1 */
	2414	if (m_fpu_pr) { /* PR = 1 */
2311	2415	m= m & 14;
2312		sh4->r[n] -= 8;
2313		sh4->ea = sh4->r[n];
2314		WL(sh4, sh4->ea,sh4->xf[m+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] );
2315		WL(sh4, sh4->ea+4,sh4->xf[m+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] );
	2416	m_r[n] -= 8;
	2417	m_ea = m_r[n];
	2418	WL(m_ea,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] );
	2419	WL(m_ea+4,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] );
2316	2420	} else {              /* PR = 0 */
2317		if (sh4->fpu_sz) { /* SZ = 1 */
	2421	if (m_fpu_sz) { /* SZ = 1 */
2318	2422	if (m & 1) {
2319	2423	m= m & 14;
2320		sh4->r[n] -= 8;
2321		sh4->ea = sh4->r[n];
2322		WL(sh4, sh4->ea,sh4->xf[m] );
2323		WL(sh4, sh4->ea+4,sh4->xf[m+1] );
	2424	m_r[n] -= 8;
	2425	m_ea = m_r[n];
	2426	WL(m_ea,m_xf[m] );
	2427	WL(m_ea+4,m_xf[m+1] );
2324	2428	} else {
2325		sh4->r[n] -= 8;
2326		sh4->ea = sh4->r[n];
2327		WL(sh4, sh4->ea,sh4->fr[m] );
2328		WL(sh4, sh4->ea+4,sh4->fr[m+1] );
	2429	m_r[n] -= 8;
	2430	m_ea = m_r[n];
	2431	WL(m_ea,m_fr[m] );
	2432	WL(m_ea+4,m_fr[m+1] );
2329	2433	}
2330	2434	} else {              /* SZ = 0 */
2331		sh4->r[n] -= 4;
2332		sh4->ea = sh4->r[n];
2333		WL(sh4, sh4->ea,sh4->fr[m] );
	2435	m_r[n] -= 4;
	2436	m_ea = m_r[n];
	2437	WL(m_ea,m_fr[m] );
2334	2438	}
2335	2439	}
2336	2440	}
r31221	r31222
2339	2443	/*  FMOV    DRm,@(R0,Rn) PR=0 SZ=1 1111nnnnmmm00111 */
2340	2444	/*  FMOV    XDm,@(R0,Rn) PR=0 SZ=1 1111nnnnmmm10111 */
2341	2445	/*  FMOV    XDm,@(R0,Rn) PR=1      1111nnnnmmm10111 */
2342		const void FMOVFRS0(sh4_state *sh4, const UINT16 opcode)
	2446	void sh34_base_device::FMOVFRS0(const UINT16 opcode)
2343	2447	{
2344	2448	UINT32 m = Rm; UINT32 n = Rn;
2345	2449
2346		if (sh4->fpu_pr) { /* PR = 1 */
	2450	if (m_fpu_pr) { /* PR = 1 */
2347	2451	m= m & 14;
2348		sh4->ea = sh4->r[0] + sh4->r[n];
2349		WL(sh4, sh4->ea,sh4->xf[m+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] );
2350		WL(sh4, sh4->ea+4,sh4->xf[m+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] );
	2452	m_ea = m_r[0] + m_r[n];
	2453	WL(m_ea,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] );
	2454	WL(m_ea+4,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] );
2351	2455	} else {              /* PR = 0 */
2352		if (sh4->fpu_sz) { /* SZ = 1 */
	2456	if (m_fpu_sz) { /* SZ = 1 */
2353	2457	if (m & 1) {
2354	2458	m= m & 14;
2355		sh4->ea = sh4->r[0] + sh4->r[n];
2356		WL(sh4, sh4->ea,sh4->xf[m] );
2357		WL(sh4, sh4->ea+4,sh4->xf[m+1] );
	2459	m_ea = m_r[0] + m_r[n];
	2460	WL(m_ea,m_xf[m] );
	2461	WL(m_ea+4,m_xf[m+1] );
2358	2462	} else {
2359		sh4->ea = sh4->r[0] + sh4->r[n];
2360		WL(sh4, sh4->ea,sh4->fr[m] );
2361		WL(sh4, sh4->ea+4,sh4->fr[m+1] );
	2463	m_ea = m_r[0] + m_r[n];
	2464	WL(m_ea,m_fr[m] );
	2465	WL(m_ea+4,m_fr[m+1] );
2362	2466	}
2363	2467	} else {              /* SZ = 0 */
2364		sh4->ea = sh4->r[0] + sh4->r[n];
2365		WL(sh4, sh4->ea,sh4->fr[m] );
	2468	m_ea = m_r[0] + m_r[n];
	2469	WL(m_ea,m_fr[m] );
2366	2470	}
2367	2471	}
2368	2472	}
r31221	r31222
2371	2475	/*  FMOV    @(R0,Rm),DRn PR=0 SZ=1 1111nnn0mmmm0110 */
2372	2476	/*  FMOV    @(R0,Rm),XDn PR=0 SZ=1 1111nnn1mmmm0110 */
2373	2477	/*  FMOV    @(R0,Rm),XDn PR=1      1111nnn1mmmm0110 */
2374		const void FMOVS0FR(sh4_state *sh4, const UINT16 opcode)
	2478	void sh34_base_device::FMOVS0FR(const UINT16 opcode)
2375	2479	{
2376	2480	UINT32 m = Rm; UINT32 n = Rn;
2377	2481
2378		if (sh4->fpu_pr) { /* PR = 1 */
	2482	if (m_fpu_pr) { /* PR = 1 */
2379	2483	n= n & 14;
2380		sh4->ea = sh4->r[0] + sh4->r[m];
2381		sh4->xf[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(sh4, sh4->ea );
2382		sh4->xf[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(sh4, sh4->ea+4 );
	2484	m_ea = m_r[0] + m_r[m];
	2485	m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(m_ea );
	2486	m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(m_ea+4 );
2383	2487	} else {              /* PR = 0 */
2384		if (sh4->fpu_sz) { /* SZ = 1 */
	2488	if (m_fpu_sz) { /* SZ = 1 */
2385	2489	if (n & 1) {
2386	2490	n= n & 14;
2387		sh4->ea = sh4->r[0] + sh4->r[m];
2388		sh4->xf[n] = RL(sh4, sh4->ea );
2389		sh4->xf[n+1] = RL(sh4, sh4->ea+4 );
	2491	m_ea = m_r[0] + m_r[m];
	2492	m_xf[n] = RL(m_ea );
	2493	m_xf[n+1] = RL(m_ea+4 );
2390	2494	} else {
2391		sh4->ea = sh4->r[0] + sh4->r[m];
2392		sh4->fr[n] = RL(sh4, sh4->ea );
2393		sh4->fr[n+1] = RL(sh4, sh4->ea+4 );
	2495	m_ea = m_r[0] + m_r[m];
	2496	m_fr[n] = RL(m_ea );
	2497	m_fr[n+1] = RL(m_ea+4 );
2394	2498	}
2395	2499	} else {              /* SZ = 0 */
2396		sh4->ea = sh4->r[0] + sh4->r[m];
2397		sh4->fr[n] = RL(sh4, sh4->ea );
	2500	m_ea = m_r[0] + m_r[m];
	2501	m_fr[n] = RL(m_ea );
2398	2502	}
2399	2503	}
2400	2504	}
r31221	r31222
2404	2508	/*  FMOV    @Rm,XDn PR=0 SZ=1 1111nnn1mmmm1000 */
2405	2509	/*  FMOV    @Rm,XDn PR=1      1111nnn1mmmm1000 */
2406	2510	/*  FMOV    @Rm,DRn PR=1      1111nnn0mmmm1000 */
2407		const void FMOVMRFR(sh4_state *sh4, const UINT16 opcode)
	2511	void sh34_base_device::FMOVMRFR(const UINT16 opcode)
2408	2512	{
2409	2513	UINT32 m = Rm; UINT32 n = Rn;
2410	2514
2411		if (sh4->fpu_pr) { /* PR = 1 */
	2515	if (m_fpu_pr) { /* PR = 1 */
2412	2516	if (n & 1) {
2413	2517	n= n & 14;
2414		sh4->ea = sh4->r[m];
2415		sh4->xf[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(sh4, sh4->ea );
2416		sh4->xf[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(sh4, sh4->ea+4 );
	2518	m_ea = m_r[m];
	2519	m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(m_ea );
	2520	m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(m_ea+4 );
2417	2521	} else {
2418	2522	n= n & 14;
2419		sh4->ea = sh4->r[m];
2420		sh4->fr[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(sh4, sh4->ea );
2421		sh4->fr[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(sh4, sh4->ea+4 );
	2523	m_ea = m_r[m];
	2524	m_fr[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(m_ea );
	2525	m_fr[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(m_ea+4 );
2422	2526	}
2423	2527	} else {              /* PR = 0 */
2424		if (sh4->fpu_sz) { /* SZ = 1 */
	2528	if (m_fpu_sz) { /* SZ = 1 */
2425	2529	if (n & 1) {
2426	2530	n= n & 14;
2427		sh4->ea = sh4->r[m];
2428		sh4->xf[n] = RL(sh4, sh4->ea );
2429		sh4->xf[n+1] = RL(sh4, sh4->ea+4 );
	2531	m_ea = m_r[m];
	2532	m_xf[n] = RL(m_ea );
	2533	m_xf[n+1] = RL(m_ea+4 );
2430	2534	} else {
2431	2535	n= n & 14;
2432		sh4->ea = sh4->r[m];
2433		sh4->fr[n] = RL(sh4, sh4->ea );
2434		sh4->fr[n+1] = RL(sh4, sh4->ea+4 );
	2536	m_ea = m_r[m];
	2537	m_fr[n] = RL(m_ea );
	2538	m_fr[n+1] = RL(m_ea+4 );
2435	2539	}
2436	2540	} else {              /* SZ = 0 */
2437		sh4->ea = sh4->r[m];
2438		sh4->fr[n] = RL(sh4, sh4->ea );
	2541	m_ea = m_r[m];
	2542	m_fr[n] = RL(m_ea );
2439	2543	}
2440	2544	}
2441	2545	}
r31221	r31222
2445	2549	/*  FMOV    XDm,DRn PR=1      XDm -> DRn 1111nnn0mmm11100 */
2446	2550	/*  FMOV    DRm,XDn PR=1      DRm -> XDn 1111nnn1mmm01100 */
2447	2551	/*  FMOV    XDm,XDn PR=1      XDm -> XDn 1111nnn1mmm11100 */
2448		const void FMOVFR(sh4_state *sh4, const UINT16 opcode)
	2552	void sh34_base_device::FMOVFR(const UINT16 opcode)
2449	2553	{
2450	2554	UINT32 m = Rm; UINT32 n = Rn;
2451	2555
2452		if ((sh4->fpu_sz == 0) && (sh4->fpu_pr == 0)) /* SZ = 0 */
2453		sh4->fr[n] = sh4->fr[m];
	2556	if ((m_fpu_sz == 0) && (m_fpu_pr == 0)) /* SZ = 0 */
	2557	m_fr[n] = m_fr[m];
2454	2558	else { /* SZ = 1 or PR = 1 */
2455	2559	if (m & 1) {
2456	2560	if (n & 1) {
2457		sh4->xf[n & 14] = sh4->xf[m & 14];
2458		sh4->xf[n | 1] = sh4->xf[m | 1];
	2561	m_xf[n & 14] = m_xf[m & 14];
	2562	m_xf[n | 1] = m_xf[m | 1];
2459	2563	} else {
2460		sh4->fr[n] = sh4->xf[m & 14];
2461		sh4->fr[n | 1] = sh4->xf[m | 1];
	2564	m_fr[n] = m_xf[m & 14];
	2565	m_fr[n | 1] = m_xf[m | 1];
2462	2566	}
2463	2567	} else {
2464	2568	if (n & 1) {
2465		sh4->xf[n & 14] = sh4->fr[m];
2466		sh4->xf[n | 1] = sh4->fr[m | 1]; // (a&14)+1 -> a|1
	2569	m_xf[n & 14] = m_fr[m];
	2570	m_xf[n | 1] = m_fr[m | 1]; // (a&14)+1 -> a|1
2467	2571	} else {
2468		sh4->fr[n] = sh4->fr[m];
2469		sh4->fr[n | 1] = sh4->fr[m | 1];
	2572	m_fr[n] = m_fr[m];
	2573	m_fr[n | 1] = m_fr[m | 1];
2470	2574	}
2471	2575	}
2472	2576	}
2473	2577	}
2474	2578
2475	2579	/*  FLDI1  FRn 1111nnnn10011101 */
2476		const void FLDI1(sh4_state *sh4, const UINT16 opcode)
	2580	void sh34_base_device::FLDI1(const UINT16 opcode)
2477	2581	{
2478		sh4->fr[Rn] = 0x3F800000;
	2582	m_fr[Rn] = 0x3F800000;
2479	2583	}
2480	2584
2481	2585	/*  FLDI0  FRn 1111nnnn10001101 */
2482		const void FLDI0(sh4_state *sh4, const UINT16 opcode)
	2586	void sh34_base_device::FLDI0(const UINT16 opcode)
2483	2587	{
2484		sh4->fr[Rn] = 0;
	2588	m_fr[Rn] = 0;
2485	2589	}
2486	2590
2487	2591	/*  FLDS FRm,FPUL 1111mmmm00011101 */
2488		const void FLDS(sh4_state *sh4, const UINT16 opcode)
	2592	void sh34_base_device:: FLDS(const UINT16 opcode)
2489	2593	{
2490		sh4->fpul = sh4->fr[Rn];
	2594	m_fpul = m_fr[Rn];
2491	2595	}
2492	2596
2493	2597	/*  FSTS FPUL,FRn 1111nnnn00001101 */
2494		const void FSTS(sh4_state *sh4, const UINT16 opcode)
	2598	void sh34_base_device:: FSTS(const UINT16 opcode)
2495	2599	{
2496		sh4->fr[Rn] = sh4->fpul;
	2600	m_fr[Rn] = m_fpul;
2497	2601	}
2498	2602
2499	2603	/* FRCHG 1111101111111101 */
2500		const void FRCHG(sh4_state *sh4)
	2604	void sh34_base_device::FRCHG()
2501	2605	{
2502		sh4->fpscr ^= FR;
2503		sh4_swap_fp_registers(sh4);
	2606	m_fpscr ^= FR;
	2607	sh4_swap_fp_registers();
2504	2608	}
2505	2609
2506	2610	/* FSCHG 1111001111111101 */
2507		const void FSCHG(sh4_state *sh4)
	2611	void sh34_base_device::FSCHG()
2508	2612	{
2509		sh4->fpscr ^= SZ;
2510		sh4->fpu_sz = (sh4->fpscr & SZ) ? 1 : 0;
	2613	m_fpscr ^= SZ;
	2614	m_fpu_sz = (m_fpscr & SZ) ? 1 : 0;
2511	2615	}
2512	2616
2513	2617	/* FTRC FRm,FPUL PR=0 1111mmmm00111101 */
2514	2618	/* FTRC DRm,FPUL PR=1 1111mmm000111101 */
2515		const void FTRC(sh4_state *sh4, const UINT16 opcode)
	2619	void sh34_base_device::FTRC(const UINT16 opcode)
2516	2620	{
2517	2621	UINT32 n = Rn;
2518	2622
2519		if (sh4->fpu_pr) { /* PR = 1 */
	2623	if (m_fpu_pr) { /* PR = 1 */
2520	2624	if(n & 1)
2521	2625	fatalerror("SH-4: FTRC opcode used with n %d",n);
2522	2626
2523	2627	n = n & 14;
2524		*((INT32 *)&sh4->fpul) = (INT32)FP_RFD(n);
	2628	*((INT32 *)&m_fpul) = (INT32)FP_RFD(n);
2525	2629	} else {              /* PR = 0 */
2526		/* read sh4->fr[n] as float -> truncate -> fpul(32) */
2527		*((INT32 *)&sh4->fpul) = (INT32)FP_RFS(n);
	2630	/* read m_fr[n] as float -> truncate -> fpul(32) */
	2631	*((INT32 *)&m_fpul) = (INT32)FP_RFS(n);
2528	2632	}
2529	2633	}
2530	2634
2531	2635	/* FLOAT FPUL,FRn PR=0 1111nnnn00101101 */
2532	2636	/* FLOAT FPUL,DRn PR=1 1111nnn000101101 */
2533		const void FLOAT(sh4_state *sh4, const UINT16 opcode)
	2637	void sh34_base_device::FLOAT(const UINT16 opcode)
2534	2638	{
2535	2639	UINT32 n = Rn;
2536	2640
2537		if (sh4->fpu_pr) { /* PR = 1 */
	2641	if (m_fpu_pr) { /* PR = 1 */
2538	2642	if(n & 1)
2539	2643	fatalerror("SH-4: FLOAT opcode used with n %d",n);
2540	2644
2541	2645	n = n & 14;
2542		FP_RFD(n) = (double)*((INT32 *)&sh4->fpul);
	2646	FP_RFD(n) = (double)*((INT32 *)&m_fpul);
2543	2647	} else {              /* PR = 0 */
2544		FP_RFS(n) = (float)*((INT32 *)&sh4->fpul);
	2648	FP_RFS(n) = (float)*((INT32 *)&m_fpul);
2545	2649	}
2546	2650	}
2547	2651
2548	2652	/* FNEG FRn PR=0 1111nnnn01001101 */
2549	2653	/* FNEG DRn PR=1 1111nnn001001101 */
2550		const void FNEG(sh4_state *sh4, const UINT16 opcode)
	2654	void sh34_base_device::FNEG(const UINT16 opcode)
2551	2655	{
2552	2656	UINT32 n = Rn;
2553	2657
2554		if (sh4->fpu_pr) { /* PR = 1 */
	2658	if (m_fpu_pr) { /* PR = 1 */
2555	2659	FP_RFD(n) = -FP_RFD(n);
2556	2660	} else {              /* PR = 0 */
2557	2661	FP_RFS(n) = -FP_RFS(n);
r31221	r31222
2560	2664
2561	2665	/* FABS FRn PR=0 1111nnnn01011101 */
2562	2666	/* FABS DRn PR=1 1111nnn001011101 */
2563		const void FABS(sh4_state *sh4, const UINT16 opcode)
	2667	void sh34_base_device::FABS(const UINT16 opcode)
2564	2668	{
2565	2669	UINT32 n = Rn;
2566	2670
2567		if (sh4->fpu_pr) { /* PR = 1 */
	2671	if (m_fpu_pr) { /* PR = 1 */
2568	2672	#ifdef LSB_FIRST
2569	2673	n = n | 1; // n & 14 + 1
2570		sh4->fr[n] = sh4->fr[n] & 0x7fffffff;
	2674	m_fr[n] = m_fr[n] & 0x7fffffff;
2571	2675	#else
2572	2676	n = n & 14;
2573		sh4->fr[n] = sh4->fr[n] & 0x7fffffff;
	2677	m_fr[n] = m_fr[n] & 0x7fffffff;
2574	2678	#endif
2575	2679	} else {              /* PR = 0 */
2576		sh4->fr[n] = sh4->fr[n] & 0x7fffffff;
	2680	m_fr[n] = m_fr[n] & 0x7fffffff;
2577	2681	}
2578	2682	}
2579	2683
2580	2684	/* FCMP/EQ FRm,FRn PR=0 1111nnnnmmmm0100 */
2581	2685	/* FCMP/EQ DRm,DRn PR=1 1111nnn0mmm00100 */
2582		const void FCMP_EQ(sh4_state *sh4, const UINT16 opcode)
	2686	void sh34_base_device::FCMP_EQ(const UINT16 opcode)
2583	2687	{
2584	2688	UINT32 m = Rm; UINT32 n = Rn;
2585	2689
2586		if (sh4->fpu_pr) { /* PR = 1 */
	2690	if (m_fpu_pr) { /* PR = 1 */
2587	2691	n = n & 14;
2588	2692	m = m & 14;
2589	2693	if (FP_RFD(n) == FP_RFD(m))
2590		sh4->sr |= T;
	2694	m_sr |= T;
2591	2695	else
2592		sh4->sr &= ~T;
	2696	m_sr &= ~T;
2593	2697	} else {              /* PR = 0 */
2594	2698	if (FP_RFS(n) == FP_RFS(m))
2595		sh4->sr |= T;
	2699	m_sr |= T;
2596	2700	else
2597		sh4->sr &= ~T;
	2701	m_sr &= ~T;
2598	2702	}
2599	2703	}
2600	2704
2601	2705	/* FCMP/GT FRm,FRn PR=0 1111nnnnmmmm0101 */
2602	2706	/* FCMP/GT DRm,DRn PR=1 1111nnn0mmm00101 */
2603		const void FCMP_GT(sh4_state *sh4, const UINT16 opcode)
	2707	void sh34_base_device::FCMP_GT(const UINT16 opcode)
2604	2708	{
2605	2709	UINT32 m = Rm; UINT32 n = Rn;
2606	2710
2607		if (sh4->fpu_pr) { /* PR = 1 */
	2711	if (m_fpu_pr) { /* PR = 1 */
2608	2712	n = n & 14;
2609	2713	m = m & 14;
2610	2714	if (FP_RFD(n) > FP_RFD(m))
2611		sh4->sr |= T;
	2715	m_sr |= T;
2612	2716	else
2613		sh4->sr &= ~T;
	2717	m_sr &= ~T;
2614	2718	} else {              /* PR = 0 */
2615	2719	if (FP_RFS(n) > FP_RFS(m))
2616		sh4->sr |= T;
	2720	m_sr |= T;
2617	2721	else
2618		sh4->sr &= ~T;
	2722	m_sr &= ~T;
2619	2723	}
2620	2724	}
2621	2725
2622	2726	/* FCNVDS DRm,FPUL PR=1 1111mmm010111101 */
2623		const void FCNVDS(sh4_state *sh4, const UINT16 opcode)
	2727	void sh34_base_device::FCNVDS(const UINT16 opcode)
2624	2728	{
2625	2729	UINT32 n = Rn;
2626	2730
2627		if (sh4->fpu_pr) { /* PR = 1 */
	2731	if (m_fpu_pr) { /* PR = 1 */
2628	2732	n = n & 14;
2629		if (sh4->fpscr & RM)
2630		sh4->fr[n | NATIVE_ENDIAN_VALUE_LE_BE(0,1)] &= 0xe0000000; /* round toward zero*/
2631		*((float *)&sh4->fpul) = (float)FP_RFD(n);
	2733	if (m_fpscr & RM)
	2734	m_fr[n | NATIVE_ENDIAN_VALUE_LE_BE(0,1)] &= 0xe0000000; /* round toward zero*/
	2735	*((float *)&m_fpul) = (float)FP_RFD(n);
2632	2736	}
2633	2737	}
2634	2738
2635	2739	/* FCNVSD FPUL, DRn PR=1 1111nnn010101101 */
2636		const void FCNVSD(sh4_state *sh4, const UINT16 opcode)
	2740	void sh34_base_device::FCNVSD(const UINT16 opcode)
2637	2741	{
2638	2742	UINT32 n = Rn;
2639	2743
2640		if (sh4->fpu_pr) { /* PR = 1 */
	2744	if (m_fpu_pr) { /* PR = 1 */
2641	2745	n = n & 14;
2642		FP_RFD(n) = (double)*((float *)&sh4->fpul);
	2746	FP_RFD(n) = (double)*((float *)&m_fpul);
2643	2747	}
2644	2748	}
2645	2749
2646	2750	/* FADD FRm,FRn PR=0 1111nnnnmmmm0000 */
2647	2751	/* FADD DRm,DRn PR=1 1111nnn0mmm00000 */
2648		const void FADD(sh4_state *sh4, const UINT16 opcode)
	2752	void sh34_base_device::FADD(const UINT16 opcode)
2649	2753	{
2650	2754	UINT32 m = Rm; UINT32 n = Rn;
2651	2755
2652		if (sh4->fpu_pr) { /* PR = 1 */
	2756	if (m_fpu_pr) { /* PR = 1 */
2653	2757	n = n & 14;
2654	2758	m = m & 14;
2655	2759	FP_RFD(n) = FP_RFD(n) + FP_RFD(m);
r31221	r31222
2660	2764
2661	2765	/* FSUB FRm,FRn PR=0 1111nnnnmmmm0001 */
2662	2766	/* FSUB DRm,DRn PR=1 1111nnn0mmm00001 */
2663		const void FSUB(sh4_state *sh4, const UINT16 opcode)
	2767	void sh34_base_device::FSUB(const UINT16 opcode)
2664	2768	{
2665	2769	UINT32 m = Rm; UINT32 n = Rn;
2666	2770
2667		if (sh4->fpu_pr) { /* PR = 1 */
	2771	if (m_fpu_pr) { /* PR = 1 */
2668	2772	n = n & 14;
2669	2773	m = m & 14;
2670	2774	FP_RFD(n) = FP_RFD(n) - FP_RFD(m);
r31221	r31222
2676	2780
2677	2781	/* FMUL FRm,FRn PR=0 1111nnnnmmmm0010 */
2678	2782	/* FMUL DRm,DRn PR=1 1111nnn0mmm00010 */
2679		const void FMUL(sh4_state *sh4, const UINT16 opcode)
	2783	void sh34_base_device::FMUL(const UINT16 opcode)
2680	2784	{
2681	2785	UINT32 m = Rm; UINT32 n = Rn;
2682	2786
2683		if (sh4->fpu_pr) { /* PR = 1 */
	2787	if (m_fpu_pr) { /* PR = 1 */
2684	2788	n = n & 14;
2685	2789	m = m & 14;
2686	2790	FP_RFD(n) = FP_RFD(n) * FP_RFD(m);
r31221	r31222
2691	2795
2692	2796	/* FDIV FRm,FRn PR=0 1111nnnnmmmm0011 */
2693	2797	/* FDIV DRm,DRn PR=1 1111nnn0mmm00011 */
2694		const void FDIV(sh4_state *sh4, const UINT16 opcode)
	2798	void sh34_base_device::FDIV(const UINT16 opcode)
2695	2799	{
2696	2800	UINT32 m = Rm; UINT32 n = Rn;
2697	2801
2698		if (sh4->fpu_pr) { /* PR = 1 */
	2802	if (m_fpu_pr) { /* PR = 1 */
2699	2803	n = n & 14;
2700	2804	m = m & 14;
2701	2805	if (FP_RFD(m) == 0)
r31221	r31222
2709	2813	}
2710	2814
2711	2815	/* FMAC FR0,FRm,FRn PR=0 1111nnnnmmmm1110 */
2712		const void FMAC(sh4_state *sh4, const UINT16 opcode)
	2816	void sh34_base_device::FMAC(const UINT16 opcode)
2713	2817	{
2714	2818	UINT32 m = Rm; UINT32 n = Rn;
2715	2819
2716		if (sh4->fpu_pr == 0) { /* PR = 0 */
	2820	if (m_fpu_pr == 0) { /* PR = 0 */
2717	2821	FP_RFS(n) = (FP_RFS(0) * FP_RFS(m)) + FP_RFS(n);
2718	2822	}
2719	2823	}
2720	2824
2721	2825	/* FSQRT FRn PR=0 1111nnnn01101101 */
2722	2826	/* FSQRT DRn PR=1 1111nnnn01101101 */
2723		const void FSQRT(sh4_state *sh4, const UINT16 opcode)
	2827	void sh34_base_device::FSQRT(const UINT16 opcode)
2724	2828	{
2725	2829	UINT32 n = Rn;
2726	2830
2727		if (sh4->fpu_pr) { /* PR = 1 */
	2831	if (m_fpu_pr) { /* PR = 1 */
2728	2832	n = n & 14;
2729	2833	if (FP_RFD(n) < 0)
2730	2834	return;
r31221	r31222
2737	2841	}
2738	2842
2739	2843	/* FSRRA FRn PR=0 1111nnnn01111101 */
2740		const void FSRRA(sh4_state *sh4, const UINT16 opcode)
	2844	void sh34_base_device::FSRRA(const UINT16 opcode)
2741	2845	{
2742	2846	UINT32 n = Rn;
2743	2847
r31221	r31222
2747	2851	}
2748	2852
2749	2853	/*  FSSCA FPUL,FRn PR=0 1111nnn011111101 */
2750		const void FSSCA(sh4_state *sh4, const UINT16 opcode)
	2854	void sh34_base_device::FSSCA(const UINT16 opcode)
2751	2855	{
2752	2856	UINT32 n = Rn;
2753	2857
2754	2858	float angle;
2755	2859
2756		angle = (((float)(sh4->fpul & 0xFFFF)) / 65536.0) * 2.0 * M_PI;
	2860	angle = (((float)(m_fpul & 0xFFFF)) / 65536.0) * 2.0 * M_PI;
2757	2861	FP_RFS(n) = sinf(angle);
2758	2862	FP_RFS(n+1) = cosf(angle);
2759	2863	}
2760	2864
2761	2865	/* FIPR FVm,FVn PR=0 1111nnmm11101101 */
2762		const void FIPR(sh4_state *sh4, const UINT16 opcode)
	2866	void sh34_base_device::FIPR(const UINT16 opcode)
2763	2867	{
2764	2868	UINT32 n = Rn;
2765	2869
r31221	r31222
2775	2879	}
2776	2880
2777	2881	/* FTRV XMTRX,FVn PR=0 1111nn0111111101 */
2778		const void FTRV(sh4_state *sh4, const UINT16 opcode)
	2882	void sh34_base_device::FTRV(const UINT16 opcode)
2779	2883	{
2780	2884	UINT32 n = Rn;
2781	2885
r31221	r31222
2792	2896	FP_RFS(n + i) = sum[i];
2793	2897	}
2794	2898
2795		const void op1111_0xf13(sh4_state *sh4, const UINT16 opcode)
	2899	void sh34_base_device::op1111_0xf13(const UINT16 opcode)
2796	2900	{
2797	2901	if (opcode & 0x100) {
2798	2902	if (opcode & 0x200) {
2799	2903	switch (opcode & 0xC00)
2800	2904	{
2801	2905	case 0x000:
2802		FSCHG(sh4);
	2906	FSCHG();
2803	2907	break;
2804	2908	case 0x800:
2805		FRCHG(sh4);
	2909	FRCHG();
2806	2910	break;
2807	2911	default:
2808		debugger_break(sh4->device->machine());
	2912	debugger_break(machine());
2809	2913	break;
2810	2914	}
2811	2915	} else {
2812		FTRV(sh4, opcode);
	2916	FTRV(opcode);
2813	2917	}
2814	2918	} else {
2815		FSSCA(sh4, opcode);
	2919	FSSCA(opcode);
2816	2920	}
2817	2921	}
2818	2922
2819		const void dbreak(sh4_state *sh4, const UINT16 opcode)
	2923	void sh34_base_device::dbreak(const UINT16 opcode)
2820	2924	{
2821		debugger_break(sh4->device->machine());
	2925	debugger_break(machine());
2822	2926	}
2823	2927
2824	2928
2825		sh4ophandler op1111_0x13_handlers[] =
	2929	sh34_base_device::sh4ophandler sh34_base_device::s_master_ophandler_table[0x10000];
	2930
	2931	const sh34_base_device::sh4ophandler sh34_base_device::s_op1111_0x13_handlers[16] =
2826	2932	{
2827		FSTS,       FLDS,       FLOAT,      FTRC,       FNEG,       FABS,       FSQRT,      FSRRA,      FLDI0,      FLDI1,      FCNVSD,     FCNVDS,     dbreak, dbreak, FIPR,   op1111_0xf13
	2933	&sh34_base_device::FSTS,       &sh34_base_device::FLDS,       &sh34_base_device::FLOAT,      &sh34_base_device::FTRC,
	2934	&sh34_base_device::FNEG,       &sh34_base_device::FABS,       &sh34_base_device::FSQRT,      &sh34_base_device::FSRRA,
	2935	&sh34_base_device::FLDI0,      &sh34_base_device::FLDI1,      &sh34_base_device::FCNVSD,     &sh34_base_device::FCNVDS,
	2936	&sh34_base_device::dbreak,     &sh34_base_device::dbreak,     &sh34_base_device::FIPR,       &sh34_base_device::op1111_0xf13
2828	2937	};
2829	2938
2830		const void op1111_0x13(sh4_state *sh4, UINT16 opcode)
	2939	void sh34_base_device::op1111_0x13(UINT16 opcode)
2831	2940	{
2832		op1111_0x13_handlers[(opcode&0xf0)>>4](sh4, opcode);
	2941	(this->*s_op1111_0x13_handlers[(opcode&0xf0)>>4])(opcode);
2833	2942	}
2834	2943
2835	2944
r31221	r31222
2837	2946	*  MAME CPU INTERFACE
2838	2947	*****************************************************************************/
2839	2948
2840		static CPU_RESET( common_sh4_reset )
	2949	void sh34_base_device::device_reset()
2841	2950	{
2842		sh4_state *sh4 = get_safe_token(device);
2843		emu_timer *tsaved[4];
2844		emu_timer *tsave[5];
2845		int save_is_slave;
2846		int savecpu_clock, savebus_clock, savepm_clock;
	2951	m_ppc = 0;
	2952	m_spc = 0;
	2953	m_pr = 0;
	2954	m_sr = 0;
	2955	m_ssr = 0;
	2956	m_gbr = 0;
	2957	m_vbr = 0;
	2958	m_mach = 0;
	2959	m_macl = 0;
	2960	memset(m_r, 0, sizeof(m_r));
	2961	memset(m_rbnk, 0, sizeof(m_rbnk));
	2962	m_sgr = 0;
	2963	memset(m_fr, 0, sizeof(m_fr));
	2964	memset(m_xf, 0, sizeof(m_xf));
	2965	m_ea = 0;
	2966	m_delay = 0;
	2967	m_cpu_off = 0;
	2968	m_pending_irq = 0;
	2969	m_test_irq = 0;
	2970	memset(m_exception_priority, 0, sizeof(m_exception_priority));
	2971	memset(m_exception_requesting, 0, sizeof(m_exception_requesting));
	2972	memset(m_m, 0, sizeof(m_m));
	2973	memset(m_sh3internal_upper, 0, sizeof(m_sh3internal_upper));
	2974	memset(m_sh3internal_lower, 0, sizeof(m_sh3internal_lower));
	2975	memset(m_irq_line_state, 0, sizeof(m_irq_line_state));
	2976	m_SH4_TSTR = 0;
	2977	m_SH4_TCNT0 = 0;
	2978	m_SH4_TCNT1 = 0;
	2979	m_SH4_TCNT2 = 0;
	2980	m_SH4_TCR0 = 0;
	2981	m_SH4_TCR1 = 0;
	2982	m_SH4_TCR2 = 0;
	2983	m_SH4_TCOR0 = 0;
	2984	m_SH4_TCOR1 = 0;
	2985	m_SH4_TCOR2 = 0;
	2986	m_SH4_TOCR = 0;
	2987	m_SH4_TCPR2 = 0;
	2988	m_SH4_IPRA = 0;
	2989	m_SH4_IPRC = 0;
	2990	m_SH4_SAR0 = 0;
	2991	m_SH4_SAR1 = 0;
	2992	m_SH4_SAR2 = 0;
	2993	m_SH4_SAR3 = 0;
	2994	m_SH4_DAR0 = 0;
	2995	m_SH4_DAR1 = 0;
	2996	m_SH4_DAR2 = 0;
	2997	m_SH4_DAR3 = 0;
	2998	m_SH4_CHCR0 = 0;
	2999	m_SH4_CHCR1 = 0;
	3000	m_SH4_CHCR2 = 0;
	3001	m_SH4_CHCR3 = 0;
	3002	m_SH4_DMATCR0 = 0;
	3003	m_SH4_DMATCR1 = 0;
	3004	m_SH4_DMATCR2 = 0;
	3005	m_SH4_DMATCR3 = 0;
	3006	m_SH4_DMAOR = 0;
	3007	m_nmi_line_state = 0;
	3008	m_frt_input = 0;
	3009	m_internal_irq_vector = 0;
	3010	m_refresh_timer_base = 0;
	3011	memset(m_dma_timer_active, 0, sizeof(m_dma_timer_active));
	3012	memset(m_dma_source, 0, sizeof(m_dma_source));
	3013	memset(m_dma_destination, 0, sizeof(m_dma_destination));
	3014	memset(m_dma_count, 0, sizeof(m_dma_count));
	3015	memset(m_dma_wordsize, 0, sizeof(m_dma_wordsize));
	3016	memset(m_dma_source_increment, 0, sizeof(m_dma_source_increment));
	3017	memset(m_dma_destination_increment, 0, sizeof(m_dma_destination_increment));
	3018	memset(m_dma_mode, 0, sizeof(m_dma_mode));
	3019	m_ioport16_pullup = 0;
	3020	m_ioport16_direction = 0;
	3021	m_ioport4_pullup = 0;
	3022	m_ioport4_direction = 0;
2847	3023
2848		void (*f)(UINT32 data);
2849		device_irq_acknowledge_delegate save_irqcallback;
	3024	sh4_default_exception_priorities();
2850	3025
2851		tsaved[0] = sh4->dma_timer[0];
2852		tsaved[1] = sh4->dma_timer[1];
2853		tsaved[2] = sh4->dma_timer[2];
2854		tsaved[3] = sh4->dma_timer[3];
2855		tsave[0] = sh4->refresh_timer;
2856		tsave[1] = sh4->rtc_timer;
2857		tsave[2] = sh4->timer[0];
2858		tsave[3] = sh4->timer[1];
2859		tsave[4] = sh4->timer[2];
	3026	m_rtc_timer->adjust(attotime::from_hz(128));
2860	3027
2861		f = sh4->ftcsr_read_callback;
2862		save_irqcallback = sh4->irq_callback;
2863		save_is_slave = sh4->is_slave;
2864		savecpu_clock = sh4->cpu_clock;
2865		savebus_clock = sh4->bus_clock;
2866		savepm_clock = sh4->pm_clock;
2867		memset(sh4, 0, sizeof(*sh4));
2868		sh4->is_slave = save_is_slave;
2869		sh4->cpu_clock = savecpu_clock;
2870		sh4->bus_clock = savebus_clock;
2871		sh4->pm_clock = savepm_clock;
2872		sh4->ftcsr_read_callback = f;
2873		sh4->irq_callback = save_irqcallback;
2874		sh4->device = device;
2875		sh4->internal = &device->space(AS_PROGRAM);
2876		sh4->program = &device->space(AS_PROGRAM);
2877		sh4->direct = &sh4->program->direct();
2878		sh4->io = &device->space(AS_IO);
	3028	m_pc = 0xa0000000;
	3029	m_r[15] = RL(4);
	3030	m_sr = 0x700000f0;
	3031	m_fpscr = 0x00040001;
	3032	m_fpu_sz = (m_fpscr & SZ) ? 1 : 0;
	3033	m_fpu_pr = (m_fpscr & PR) ? 1 : 0;
	3034	m_fpul = 0;
	3035	m_dbr = 0;
2879	3036
2880		sh4->dma_timer[0] = tsaved[0];
2881		sh4->dma_timer[1] = tsaved[1];
2882		sh4->dma_timer[2] = tsaved[2];
2883		sh4->dma_timer[3] = tsaved[3];
2884		sh4->refresh_timer = tsave[0];
2885		sh4->rtc_timer = tsave[1];
2886		sh4->timer[0] = tsave[2];
2887		sh4->timer[1] = tsave[3];
2888		sh4->timer[2] = tsave[4];
2889		memset(sh4->m, 0, 16384*4);
2890		sh4_default_exception_priorities(sh4);
2891		memset(sh4->exception_requesting, 0, sizeof(sh4->exception_requesting));
	3037	m_internal_irq_level = -1;
	3038	m_irln = 15;
	3039	m_sleep_mode = 0;
2892	3040
2893		sh4->rtc_timer->adjust(attotime::from_hz(128));
	3041	m_sh4_mmu_enabled = 0;
2894	3042
2895
2896		sh4->pc = 0xa0000000;
2897		sh4->r[15] = RL(sh4,4);
2898		sh4->sr = 0x700000f0;
2899		sh4->fpscr = 0x00040001;
2900		sh4->fpu_sz = (sh4->fpscr & SZ) ? 1 : 0;
2901		sh4->fpu_pr = (sh4->fpscr & PR) ? 1 : 0;
2902		sh4->fpul = 0;
2903		sh4->dbr = 0;
2904
2905		sh4->internal_irq_level = -1;
2906		sh4->irln = 15;
2907		sh4->sleep_mode = 0;
2908
2909		sh4->sh4_mmu_enabled = 0;
2910
2911		sh4_build_optable(sh4);
	3043	sh4_build_optable();
2912	3044	}
2913	3045
2914	3046	/*-------------------------------------------------
2915	3047	sh3_reset - reset the processor
2916	3048	-------------------------------------------------*/
2917	3049
2918		static CPU_RESET( sh3 )
	3050	void sh3_base_device::device_reset()
2919	3051	{
2920		sh4_state *sh4 = get_safe_token(device);
	3052	sh34_base_device::device_reset();
2921	3053
2922		CPU_RESET_CALL(common_sh4_reset);
2923
2924		sh4->cpu_type = CPU_TYPE_SH3;
2925
2926		sh4->SH4_TCOR0 = 0xffffffff;
2927		sh4->SH4_TCNT0 = 0xffffffff;
2928		sh4->SH4_TCOR1 = 0xffffffff;
2929		sh4->SH4_TCNT1 = 0xffffffff;
2930		sh4->SH4_TCOR2 = 0xffffffff;
2931		sh4->SH4_TCNT2 = 0xffffffff;
2932
	3054	m_SH4_TCOR0 = 0xffffffff;
	3055	m_SH4_TCNT0 = 0xffffffff;
	3056	m_SH4_TCOR1 = 0xffffffff;
	3057	m_SH4_TCNT1 = 0xffffffff;
	3058	m_SH4_TCOR2 = 0xffffffff;
	3059	m_SH4_TCNT2 = 0xffffffff;
2933	3060	}
2934	3061
2935		static CPU_RESET( sh4 )
	3062	void sh4_base_device::device_reset()
2936	3063	{
2937		sh4_state *sh4 = get_safe_token(device);
	3064	sh34_base_device::device_reset();
2938	3065
2939		CPU_RESET_CALL(common_sh4_reset);
2940
2941		sh4->cpu_type = CPU_TYPE_SH4;
2942
2943		sh4->m[RCR2] = 0x09;
2944		sh4->SH4_TCOR0 = 0xffffffff;
2945		sh4->SH4_TCNT0 = 0xffffffff;
2946		sh4->SH4_TCOR1 = 0xffffffff;
2947		sh4->SH4_TCNT1 = 0xffffffff;
2948		sh4->SH4_TCOR2 = 0xffffffff;
2949		sh4->SH4_TCNT2 = 0xffffffff;
	3066	m_m[RCR2] = 0x09;
	3067	m_SH4_TCOR0 = 0xffffffff;
	3068	m_SH4_TCNT0 = 0xffffffff;
	3069	m_SH4_TCOR1 = 0xffffffff;
	3070	m_SH4_TCNT1 = 0xffffffff;
	3071	m_SH4_TCOR2 = 0xffffffff;
	3072	m_SH4_TCNT2 = 0xffffffff;
2950	3073	}
2951	3074
2952	3075	/* These tables are combined into our main opcode jump table, master_ophandler_table in the RESET function */
2953	3076
2954		sh4ophandler op1000_handler[] =
	3077	#define SH4OP(x)  &sh34_base_device::x
	3078
	3079	const sh34_base_device::sh4ophandler sh34_base_device::s_op1000_handler[16] =
2955	3080	{
2956		MOVBS4,     MOVWS4,     NOP,        NOP,        MOVBL4,     MOVWL4,     NOP,        NOP,        CMPIM,      BT,         NOP,        BF,         NOP,        BTS,        NOP,        BFS
	3081	SH4OP(MOVBS4),     SH4OP(MOVWS4),     SH4OP(NOP),        SH4OP(NOP),        SH4OP(MOVBL4),     SH4OP(MOVWL4),     SH4OP(NOP),        SH4OP(NOP),
	3082	SH4OP(CMPIM),      SH4OP(BT),         SH4OP(NOP),        SH4OP(BF),         SH4OP(NOP),        SH4OP(BTS),        SH4OP(NOP),        SH4OP(BFS)
2957	3083	};
2958	3084
2959		sh4ophandler op1100_handler[] =
	3085	const sh34_base_device::sh4ophandler sh34_base_device::s_op1100_handler[16] =
2960	3086	{
2961		MOVBSG,     MOVWSG,     MOVLSG,     TRAPA,      MOVBLG,     MOVWLG,     MOVLLG,     MOVA,       TSTI,       ANDI,       XORI,       ORI,        TSTM,       ANDM,       XORM,       ORM
	3087	SH4OP(MOVBSG),     SH4OP(MOVWSG),     SH4OP(MOVLSG),     SH4OP(TRAPA),      SH4OP(MOVBLG),     SH4OP(MOVWLG),     SH4OP(MOVLLG),     SH4OP(MOVA),
	3088	SH4OP(TSTI),       SH4OP(ANDI),       SH4OP(XORI),       SH4OP(ORI),        SH4OP(TSTM),       SH4OP(ANDM),       SH4OP(XORM),       SH4OP(ORM)
2962	3089	};
2963	3090
2964		sh4ophandler op0000_handlers[] =
	3091	const sh34_base_device::sh4ophandler sh34_base_device::s_op0000_handlers[256] =
2965	3092	{
2966		NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,
2967		NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,
2968		STCSR,      STCGBR,     STCVBR,     STCSSR,     STCSPC,     NOP,        NOP,        NOP,        STCRBANK,   STCRBANK,   STCRBANK,   STCRBANK,   STCRBANK,   STCRBANK,   STCRBANK,   STCRBANK,
2969		BSRF,       NOP,        BRAF,       NOP,        NOP,        NOP,        NOP,        NOP,        PREFM,      TODO,       TODO,       TODO,       MOVCAL,     NOP,        NOP,        NOP,
2970		MOVBS0,     MOVBS0,     MOVBS0,     MOVBS0,     MOVBS0,     MOVBS0,     MOVBS0,     MOVBS0,     MOVBS0,     MOVBS0,     MOVBS0,     MOVBS0,     MOVBS0,     MOVBS0,     MOVBS0,     MOVBS0,
2971		MOVWS0,     MOVWS0,     MOVWS0,     MOVWS0,     MOVWS0,     MOVWS0,     MOVWS0,     MOVWS0,     MOVWS0,     MOVWS0,     MOVWS0,     MOVWS0,     MOVWS0,     MOVWS0,     MOVWS0,     MOVWS0,
2972		MOVLS0,     MOVLS0,     MOVLS0,     MOVLS0,     MOVLS0,     MOVLS0,     MOVLS0,     MOVLS0,     MOVLS0,     MOVLS0,     MOVLS0,     MOVLS0,     MOVLS0,     MOVLS0,     MOVLS0,     MOVLS0,
2973		MULL,       MULL,       MULL,       MULL,       MULL,       MULL,       MULL,       MULL,       MULL,       MULL,       MULL,       MULL,       MULL,       MULL,       MULL,       MULL,
2974		CLRT,       SETT,       CLRMAC,     TODO,       CLRS,       SETS,       NOP,        NOP,        CLRT,       SETT,       CLRMAC,     TODO,       CLRS,       SETS,       NOP,        NOP,
2975		NOP,        DIV0U,      MOVT,       NOP,        NOP,        DIV0U,      MOVT,       NOP,        NOP,        DIV0U,      MOVT,       NOP,        NOP,        DIV0U,      MOVT,       NOP,
2976		STSMACH,    STSMACL,    STSPR,      STCSGR,     NOP,        STSFPUL,    STSFPSCR,   STCDBR,     STSMACH,    STSMACL,    STSPR,      STCSGR,     NOP,        STSFPUL,    STSFPSCR,   STCDBR,
2977		RTS,        SLEEP,      RTE,        NOP,        RTS,        SLEEP,      RTE,        NOP,        RTS,        SLEEP,      RTE,        NOP,        RTS,        SLEEP,      RTE,        NOP,
2978		MOVBL0,     MOVBL0,     MOVBL0,     MOVBL0,     MOVBL0,     MOVBL0,     MOVBL0,     MOVBL0,     MOVBL0,     MOVBL0,     MOVBL0,     MOVBL0,     MOVBL0,     MOVBL0,     MOVBL0,     MOVBL0,
2979		MOVWL0,     MOVWL0,     MOVWL0,     MOVWL0,     MOVWL0,     MOVWL0,     MOVWL0,     MOVWL0,     MOVWL0,     MOVWL0,     MOVWL0,     MOVWL0,     MOVWL0,     MOVWL0,     MOVWL0,     MOVWL0,
2980		MOVLL0,     MOVLL0,     MOVLL0,     MOVLL0,     MOVLL0,     MOVLL0,     MOVLL0,     MOVLL0,     MOVLL0,     MOVLL0,     MOVLL0,     MOVLL0,     MOVLL0,     MOVLL0,     MOVLL0,     MOVLL0,
2981		MAC_L,      MAC_L,      MAC_L,      MAC_L,      MAC_L,      MAC_L,      MAC_L,      MAC_L,      MAC_L,      MAC_L,      MAC_L,      MAC_L,      MAC_L,      MAC_L,      MAC_L,      MAC_L,
	3093	SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),
	3094	SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),
	3095	SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),
	3096	SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),
	3097	SH4OP(STCSR),      SH4OP(STCGBR),     SH4OP(STCVBR),     SH4OP(STCSSR),     SH4OP(STCSPC),     SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),
	3098	SH4OP(STCRBANK),   SH4OP(STCRBANK),   SH4OP(STCRBANK),   SH4OP(STCRBANK),   SH4OP(STCRBANK),   SH4OP(STCRBANK),   SH4OP(STCRBANK),   SH4OP(STCRBANK),
	3099	SH4OP(BSRF),       SH4OP(NOP),        SH4OP(BRAF),       SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),
	3100	SH4OP(PREFM),      SH4OP(TODO),       SH4OP(TODO),       SH4OP(TODO),       SH4OP(MOVCAL),     SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),
	3101	SH4OP(MOVBS0),     SH4OP(MOVBS0),     SH4OP(MOVBS0),     SH4OP(MOVBS0),     SH4OP(MOVBS0),     SH4OP(MOVBS0),     SH4OP(MOVBS0),     SH4OP(MOVBS0),
	3102	SH4OP(MOVBS0),     SH4OP(MOVBS0),     SH4OP(MOVBS0),     SH4OP(MOVBS0),     SH4OP(MOVBS0),     SH4OP(MOVBS0),     SH4OP(MOVBS0),     SH4OP(MOVBS0),
	3103	SH4OP(MOVWS0),     SH4OP(MOVWS0),     SH4OP(MOVWS0),     SH4OP(MOVWS0),     SH4OP(MOVWS0),     SH4OP(MOVWS0),     SH4OP(MOVWS0),     SH4OP(MOVWS0),
	3104	SH4OP(MOVWS0),     SH4OP(MOVWS0),     SH4OP(MOVWS0),     SH4OP(MOVWS0),     SH4OP(MOVWS0),     SH4OP(MOVWS0),     SH4OP(MOVWS0),     SH4OP(MOVWS0),
	3105	SH4OP(MOVLS0),     SH4OP(MOVLS0),     SH4OP(MOVLS0),     SH4OP(MOVLS0),     SH4OP(MOVLS0),     SH4OP(MOVLS0),     SH4OP(MOVLS0),     SH4OP(MOVLS0),
	3106	SH4OP(MOVLS0),     SH4OP(MOVLS0),     SH4OP(MOVLS0),     SH4OP(MOVLS0),     SH4OP(MOVLS0),     SH4OP(MOVLS0),     SH4OP(MOVLS0),     SH4OP(MOVLS0),
	3107	SH4OP(MULL),       SH4OP(MULL),       SH4OP(MULL),       SH4OP(MULL),       SH4OP(MULL),       SH4OP(MULL),       SH4OP(MULL),       SH4OP(MULL),
	3108	SH4OP(MULL),       SH4OP(MULL),       SH4OP(MULL),       SH4OP(MULL),       SH4OP(MULL),       SH4OP(MULL),       SH4OP(MULL),       SH4OP(MULL),
	3109	SH4OP(CLRT),       SH4OP(SETT),       SH4OP(CLRMAC),     SH4OP(TODO),       SH4OP(CLRS),       SH4OP(SETS),       SH4OP(NOP),        SH4OP(NOP),
	3110	SH4OP(CLRT),       SH4OP(SETT),       SH4OP(CLRMAC),     SH4OP(TODO),       SH4OP(CLRS),       SH4OP(SETS),       SH4OP(NOP),        SH4OP(NOP),
	3111	SH4OP(NOP),        SH4OP(DIV0U),      SH4OP(MOVT),       SH4OP(NOP),        SH4OP(NOP),        SH4OP(DIV0U),      SH4OP(MOVT),       SH4OP(NOP),
	3112	SH4OP(NOP),        SH4OP(DIV0U),      SH4OP(MOVT),       SH4OP(NOP),        SH4OP(NOP),        SH4OP(DIV0U),      SH4OP(MOVT),       SH4OP(NOP),
	3113	SH4OP(STSMACH),    SH4OP(STSMACL),    SH4OP(STSPR),      SH4OP(STCSGR),     SH4OP(NOP),        SH4OP(STSFPUL),    SH4OP(STSFPSCR),   SH4OP(STCDBR),
	3114	SH4OP(STSMACH),    SH4OP(STSMACL),    SH4OP(STSPR),      SH4OP(STCSGR),     SH4OP(NOP),        SH4OP(STSFPUL),    SH4OP(STSFPSCR),   SH4OP(STCDBR),
	3115	SH4OP(RTS),        SH4OP(SLEEP),      SH4OP(RTE),        SH4OP(NOP),        SH4OP(RTS),        SH4OP(SLEEP),      SH4OP(RTE),        SH4OP(NOP),
	3116	SH4OP(RTS),        SH4OP(SLEEP),      SH4OP(RTE),        SH4OP(NOP),        SH4OP(RTS),        SH4OP(SLEEP),      SH4OP(RTE),        SH4OP(NOP),
	3117	SH4OP(MOVBL0),     SH4OP(MOVBL0),     SH4OP(MOVBL0),     SH4OP(MOVBL0),     SH4OP(MOVBL0),     SH4OP(MOVBL0),     SH4OP(MOVBL0),     SH4OP(MOVBL0),
	3118	SH4OP(MOVBL0),     SH4OP(MOVBL0),     SH4OP(MOVBL0),     SH4OP(MOVBL0),     SH4OP(MOVBL0),     SH4OP(MOVBL0),     SH4OP(MOVBL0),     SH4OP(MOVBL0),
	3119	SH4OP(MOVWL0),     SH4OP(MOVWL0),     SH4OP(MOVWL0),     SH4OP(MOVWL0),     SH4OP(MOVWL0),     SH4OP(MOVWL0),     SH4OP(MOVWL0),     SH4OP(MOVWL0),
	3120	SH4OP(MOVWL0),     SH4OP(MOVWL0),     SH4OP(MOVWL0),     SH4OP(MOVWL0),     SH4OP(MOVWL0),     SH4OP(MOVWL0),     SH4OP(MOVWL0),     SH4OP(MOVWL0),
	3121	SH4OP(MOVLL0),     SH4OP(MOVLL0),     SH4OP(MOVLL0),     SH4OP(MOVLL0),     SH4OP(MOVLL0),     SH4OP(MOVLL0),     SH4OP(MOVLL0),     SH4OP(MOVLL0),
	3122	SH4OP(MOVLL0),     SH4OP(MOVLL0),     SH4OP(MOVLL0),     SH4OP(MOVLL0),     SH4OP(MOVLL0),     SH4OP(MOVLL0),     SH4OP(MOVLL0),     SH4OP(MOVLL0),
	3123	SH4OP(MAC_L),      SH4OP(MAC_L),      SH4OP(MAC_L),      SH4OP(MAC_L),      SH4OP(MAC_L),      SH4OP(MAC_L),      SH4OP(MAC_L),      SH4OP(MAC_L),
	3124	SH4OP(MAC_L),      SH4OP(MAC_L),      SH4OP(MAC_L),      SH4OP(MAC_L),      SH4OP(MAC_L),      SH4OP(MAC_L),      SH4OP(MAC_L),      SH4OP(MAC_L)
2982	3125	};
2983	3126
2984		sh4ophandler op0100_handlers[] =
	3127	const sh34_base_device::sh4ophandler sh34_base_device::s_op0100_handlers[256] =
2985	3128	{
2986		SHLL,       DT,         SHAL,       NOP,        SHLL,       DT,         SHAL,       NOP,        SHLL,       DT,         SHAL,       NOP,        SHLL,       DT,         SHAL,       NOP,
2987		SHLR,       CMPPZ,      SHAR,       NOP,        SHLR,       CMPPZ,      SHAR,       NOP,        SHLR,       CMPPZ,      SHAR,       NOP,        SHLR,       CMPPZ,      SHAR,       NOP,
2988		STSMMACH,   STSMMACL,   STSMPR,     STCMSGR,    NOP,        STSMFPUL,   STSMFPSCR,  NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        STCMDBR,
2989		STCMSR,     STCMGBR,    STCMVBR,    STCMSSR,    STCMSPC,    NOP,        NOP,        NOP,        STCMRBANK,  STCMRBANK,  STCMRBANK,  STCMRBANK,  STCMRBANK,  STCMRBANK,  STCMRBANK,  STCMRBANK,
2990		ROTL,       NOP,        ROTCL,      NOP,        ROTL,       NOP,        ROTCL,      NOP,        ROTL,       NOP,        ROTCL,      NOP,        ROTL,       NOP,        ROTCL,      NOP,
2991		ROTR,       CMPPL,      ROTCR,      NOP,        ROTR,       CMPPL,      ROTCR,      NOP,        ROTR,       CMPPL,      ROTCR,      NOP,        ROTR,       CMPPL,      ROTCR,      NOP,
2992		LDSMMACH,   LDSMMACL,   LDSMPR,     NOP,        NOP,        LDSMFPUL,   LDSMFPSCR,  NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        LDCMDBR,
2993		LDCMSR,     LDCMGBR,    LDCMVBR,    LDCMSSR,    LDCMSPC,    NOP,        NOP,        NOP,        LDCMRBANK,  LDCMRBANK,  LDCMRBANK,  LDCMRBANK,  LDCMRBANK,  LDCMRBANK,  LDCMRBANK,  LDCMRBANK,
2994		SHLL2,      SHLL8,      SHLL16,     NOP,        SHLL2,      SHLL8,      SHLL16,     NOP,        SHLL2,      SHLL8,      SHLL16,     NOP,        SHLL2,      SHLL8,      SHLL16,     NOP,
2995		SHLR2,      SHLR8,      SHLR16,     NOP,        SHLR2,      SHLR8,      SHLR16,     NOP,        SHLR2,      SHLR8,      SHLR16,     NOP,        SHLR2,      SHLR8,      SHLR16,     NOP,
2996		LDSMACH,    LDSMACL,    LDSPR,      NOP,        NOP,        LDSFPUL,    LDSFPSCR,   NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        NOP,        LDCDBR,
2997		JSR,        TAS,        JMP,        NOP,        JSR,        TAS,        JMP,        NOP,        JSR,        TAS,        JMP,        NOP,        JSR,        TAS,        JMP,        NOP,
2998		SHAD,       SHAD,       SHAD,       SHAD,       SHAD,       SHAD,       SHAD,       SHAD,       SHAD,       SHAD,       SHAD,       SHAD,       SHAD,       SHAD,       SHAD,       SHAD,
2999		SHLD,       SHLD,       SHLD,       SHLD,       SHLD,       SHLD,       SHLD,       SHLD,       SHLD,       SHLD,       SHLD,       SHLD,       SHLD,       SHLD,       SHLD,       SHLD,
3000		LDCSR,      LDCGBR,     LDCVBR,     LDCSSR,     LDCSPC,     NOP,        NOP,        NOP,        LDCRBANK,   LDCRBANK,   LDCRBANK,   LDCRBANK,   LDCRBANK,   LDCRBANK,   LDCRBANK,   LDCRBANK,
3001		MAC_W,      MAC_W,      MAC_W,      MAC_W,      MAC_W,      MAC_W,      MAC_W,      MAC_W,      MAC_W,      MAC_W,      MAC_W,      MAC_W,      MAC_W,      MAC_W,      MAC_W,      MAC_W,
	3129	SH4OP(SHLL),       SH4OP(DT),         SH4OP(SHAL),       SH4OP(NOP),        SH4OP(SHLL),       SH4OP(DT),         SH4OP(SHAL),       SH4OP(NOP),
	3130	SH4OP(SHLL),       SH4OP(DT),         SH4OP(SHAL),       SH4OP(NOP),        SH4OP(SHLL),       SH4OP(DT),         SH4OP(SHAL),       SH4OP(NOP),
	3131	SH4OP(SHLR),       SH4OP(CMPPZ),      SH4OP(SHAR),       SH4OP(NOP),        SH4OP(SHLR),       SH4OP(CMPPZ),      SH4OP(SHAR),       SH4OP(NOP),
	3132	SH4OP(SHLR),       SH4OP(CMPPZ),      SH4OP(SHAR),       SH4OP(NOP),        SH4OP(SHLR),       SH4OP(CMPPZ),      SH4OP(SHAR),       SH4OP(NOP),
	3133	SH4OP(STSMMACH),   SH4OP(STSMMACL),   SH4OP(STSMPR),     SH4OP(STCMSGR),    SH4OP(NOP),        SH4OP(STSMFPUL),   SH4OP(STSMFPSCR),  SH4OP(NOP),
	3134	SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(STCMDBR),
	3135	SH4OP(STCMSR),     SH4OP(STCMGBR),    SH4OP(STCMVBR),    SH4OP(STCMSSR),    SH4OP(STCMSPC),    SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),
	3136	SH4OP(STCMRBANK),  SH4OP(STCMRBANK),  SH4OP(STCMRBANK),  SH4OP(STCMRBANK),  SH4OP(STCMRBANK),  SH4OP(STCMRBANK),  SH4OP(STCMRBANK),  SH4OP(STCMRBANK),
	3137	SH4OP(ROTL),       SH4OP(NOP),        SH4OP(ROTCL),      SH4OP(NOP),        SH4OP(ROTL),       SH4OP(NOP),        SH4OP(ROTCL),      SH4OP(NOP),
	3138	SH4OP(ROTL),       SH4OP(NOP),        SH4OP(ROTCL),      SH4OP(NOP),        SH4OP(ROTL),       SH4OP(NOP),        SH4OP(ROTCL),      SH4OP(NOP),
	3139	SH4OP(ROTR),       SH4OP(CMPPL),      SH4OP(ROTCR),      SH4OP(NOP),        SH4OP(ROTR),       SH4OP(CMPPL),      SH4OP(ROTCR),      SH4OP(NOP),
	3140	SH4OP(ROTR),       SH4OP(CMPPL),      SH4OP(ROTCR),      SH4OP(NOP),        SH4OP(ROTR),       SH4OP(CMPPL),      SH4OP(ROTCR),      SH4OP(NOP),
	3141	SH4OP(LDSMMACH),   SH4OP(LDSMMACL),   SH4OP(LDSMPR),     SH4OP(NOP),        SH4OP(NOP),        SH4OP(LDSMFPUL),   SH4OP(LDSMFPSCR),  SH4OP(NOP),
	3142	SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(LDCMDBR),
	3143	SH4OP(LDCMSR),     SH4OP(LDCMGBR),    SH4OP(LDCMVBR),    SH4OP(LDCMSSR),    SH4OP(LDCMSPC),    SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),
	3144	SH4OP(LDCMRBANK),  SH4OP(LDCMRBANK),  SH4OP(LDCMRBANK),  SH4OP(LDCMRBANK),  SH4OP(LDCMRBANK),  SH4OP(LDCMRBANK),  SH4OP(LDCMRBANK),  SH4OP(LDCMRBANK),
	3145	SH4OP(SHLL2),      SH4OP(SHLL8),      SH4OP(SHLL16),     SH4OP(NOP),        SH4OP(SHLL2),      SH4OP(SHLL8),      SH4OP(SHLL16),     SH4OP(NOP),
	3146	SH4OP(SHLL2),      SH4OP(SHLL8),      SH4OP(SHLL16),     SH4OP(NOP),        SH4OP(SHLL2),      SH4OP(SHLL8),      SH4OP(SHLL16),     SH4OP(NOP),
	3147	SH4OP(SHLR2),      SH4OP(SHLR8),      SH4OP(SHLR16),     SH4OP(NOP),        SH4OP(SHLR2),      SH4OP(SHLR8),      SH4OP(SHLR16),     SH4OP(NOP),
	3148	SH4OP(SHLR2),      SH4OP(SHLR8),      SH4OP(SHLR16),     SH4OP(NOP),        SH4OP(SHLR2),      SH4OP(SHLR8),      SH4OP(SHLR16),     SH4OP(NOP),
	3149	SH4OP(LDSMACH),    SH4OP(LDSMACL),    SH4OP(LDSPR),      SH4OP(NOP),        SH4OP(NOP),        SH4OP(LDSFPUL),    SH4OP(LDSFPSCR),   SH4OP(NOP),
	3150	SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),        SH4OP(LDCDBR),
	3151	SH4OP(JSR),        SH4OP(TAS),        SH4OP(JMP),        SH4OP(NOP),        SH4OP(JSR),        SH4OP(TAS),        SH4OP(JMP),        SH4OP(NOP),
	3152	SH4OP(JSR),        SH4OP(TAS),        SH4OP(JMP),        SH4OP(NOP),        SH4OP(JSR),        SH4OP(TAS),        SH4OP(JMP),        SH4OP(NOP),
	3153	SH4OP(SHAD),       SH4OP(SHAD),       SH4OP(SHAD),       SH4OP(SHAD),       SH4OP(SHAD),       SH4OP(SHAD),       SH4OP(SHAD),       SH4OP(SHAD),
	3154	SH4OP(SHAD),       SH4OP(SHAD),       SH4OP(SHAD),       SH4OP(SHAD),       SH4OP(SHAD),       SH4OP(SHAD),       SH4OP(SHAD),       SH4OP(SHAD),
	3155	SH4OP(SHLD),       SH4OP(SHLD),       SH4OP(SHLD),       SH4OP(SHLD),       SH4OP(SHLD),       SH4OP(SHLD),       SH4OP(SHLD),       SH4OP(SHLD),
	3156	SH4OP(SHLD),       SH4OP(SHLD),       SH4OP(SHLD),       SH4OP(SHLD),       SH4OP(SHLD),       SH4OP(SHLD),       SH4OP(SHLD),       SH4OP(SHLD),
	3157	SH4OP(LDCSR),      SH4OP(LDCGBR),     SH4OP(LDCVBR),     SH4OP(LDCSSR),     SH4OP(LDCSPC),     SH4OP(NOP),        SH4OP(NOP),        SH4OP(NOP),
	3158	SH4OP(LDCRBANK),   SH4OP(LDCRBANK),   SH4OP(LDCRBANK),   SH4OP(LDCRBANK),   SH4OP(LDCRBANK),   SH4OP(LDCRBANK),   SH4OP(LDCRBANK),   SH4OP(LDCRBANK),
	3159	SH4OP(MAC_W),      SH4OP(MAC_W),      SH4OP(MAC_W),      SH4OP(MAC_W),      SH4OP(MAC_W),      SH4OP(MAC_W),      SH4OP(MAC_W),      SH4OP(MAC_W),
	3160	SH4OP(MAC_W),      SH4OP(MAC_W),      SH4OP(MAC_W),      SH4OP(MAC_W),      SH4OP(MAC_W),      SH4OP(MAC_W),      SH4OP(MAC_W),      SH4OP(MAC_W)
3002	3161	};
3003	3162
3004	3163
3005		sh4ophandler upper4bits[] =
	3164	const sh34_base_device::sh4ophandler sh34_base_device::s_upper4bits[256] =
3006	3165	{
3007		0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,      /* j = 0x0000 - uses op0000_handlers*/
3008		MOVLS4,     MOVLS4,     MOVLS4,     MOVLS4,     MOVLS4,     MOVLS4,     MOVLS4,     MOVLS4,     MOVLS4,     MOVLS4,     MOVLS4,     MOVLS4,     MOVLS4,     MOVLS4,     MOVLS4,     MOVLS4, /* j = 0x1000 */
3009		MOVBS,      MOVWS,      MOVLS,      NOP,        MOVBM,      MOVWM,      MOVLM,      DIV0S,      TST,        AND,        XOR,        OR,         CMPSTR,     XTRCT,      MULU,       MULS,   /* j = 0x2000 */
3010		CMPEQ,      NOP,        CMPHS,      CMPGE,      DIV1,       DMULU,      CMPHI,      CMPGT,      SUB,        NOP,        SUBC,       SUBV,       ADD,        DMULS,      ADDC,       ADDV,   /* j = 0x3000 */
3011		0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,      /* j = 0x4000 - uses op0100_handlers*/
3012		MOVLL4,     MOVLL4,     MOVLL4,     MOVLL4,     MOVLL4,     MOVLL4,     MOVLL4,     MOVLL4,     MOVLL4,     MOVLL4,     MOVLL4,     MOVLL4,     MOVLL4,     MOVLL4,     MOVLL4,     MOVLL4, /* j = 0x5000 */
3013		MOVBL,      MOVWL,      MOVLL,      MOV,        MOVBP,      MOVWP,      MOVLP,      NOT,        SWAPB,      SWAPW,      NEGC,       NEG,        EXTUB,      EXTUW,      EXTSB,      EXTSW,  /* j = 0x6000 */
3014		ADDI,       ADDI,       ADDI,       ADDI,       ADDI,       ADDI,       ADDI,       ADDI,       ADDI,       ADDI,       ADDI,       ADDI,       ADDI,       ADDI,       ADDI,       ADDI,   /* j = 0x7000 */
3015		0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,      /* j = 0x8000 - uses op1000_handlers */
3016		MOVWI,      MOVWI,      MOVWI,      MOVWI,      MOVWI,      MOVWI,      MOVWI,      MOVWI,      MOVWI,      MOVWI,      MOVWI,      MOVWI,      MOVWI,      MOVWI,      MOVWI,      MOVWI,  /* j = 0x9000 */
3017		BRA,        BRA,        BRA,        BRA,        BRA,        BRA,        BRA,        BRA,        BRA,        BRA,        BRA,        BRA,        BRA,        BRA,        BRA,        BRA,    /* j = 0xa000 */
3018		BSR,        BSR,        BSR,        BSR,        BSR,        BSR,        BSR,        BSR,        BSR,        BSR,        BSR,        BSR,        BSR,        BSR,        BSR,        BSR,    /* j = 0xb000 */
3019		0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,          0,      /* j = 0xc000 - uses op1100_handlers */
3020		MOVLI,      MOVLI,      MOVLI,      MOVLI,      MOVLI,      MOVLI,      MOVLI,      MOVLI,      MOVLI,      MOVLI,      MOVLI,      MOVLI,      MOVLI,      MOVLI,      MOVLI,      MOVLI,  /* j = 0xd000 */
3021		MOVI,       MOVI,       MOVI,       MOVI,       MOVI,       MOVI,       MOVI,       MOVI,       MOVI,       MOVI,       MOVI,       MOVI,       MOVI,       MOVI,       MOVI,       MOVI,   /* j = 0xe000 */
3022		FADD,       FSUB,       FMUL,       FDIV,       FCMP_EQ,    FCMP_GT,    FMOVS0FR,   FMOVFRS0,   FMOVMRFR,   FMOVMRIFR,  FMOVFRMR,   FMOVFRMDR,  FMOVFR,     op1111_0x13,FMAC,       dbreak  /* j = 0xf000 */
	3166	/* j = 0x0000 - uses op0000_handlers*/
	3167	NULL,          NULL,          NULL,          NULL,          NULL,          NULL,          NULL,          NULL,
	3168	NULL,          NULL,          NULL,          NULL,          NULL,          NULL,          NULL,          NULL,
	3169	/* j = 0x1000 */
	3170	SH4OP(MOVLS4),     SH4OP(MOVLS4),     SH4OP(MOVLS4),     SH4OP(MOVLS4),     SH4OP(MOVLS4),     SH4OP(MOVLS4),     SH4OP(MOVLS4),     SH4OP(MOVLS4),
	3171	SH4OP(MOVLS4),     SH4OP(MOVLS4),     SH4OP(MOVLS4),     SH4OP(MOVLS4),     SH4OP(MOVLS4),     SH4OP(MOVLS4),     SH4OP(MOVLS4),     SH4OP(MOVLS4),
	3172	/* j = 0x2000 */
	3173	SH4OP(MOVBS),      SH4OP(MOVWS),      SH4OP(MOVLS),      SH4OP(NOP),        SH4OP(MOVBM),      SH4OP(MOVWM),      SH4OP(MOVLM),      SH4OP(DIV0S),
	3174	SH4OP(TST),        SH4OP(AND),        SH4OP(XOR),        SH4OP(OR),         SH4OP(CMPSTR),     SH4OP(XTRCT),      SH4OP(MULU),       SH4OP(MULS),
	3175	/* j = 0x3000 */
	3176	SH4OP(CMPEQ),      SH4OP(NOP),        SH4OP(CMPHS),      SH4OP(CMPGE),      SH4OP(DIV1),       SH4OP(DMULU),      SH4OP(CMPHI),      SH4OP(CMPGT),
	3177	SH4OP(SUB),        SH4OP(NOP),        SH4OP(SUBC),       SH4OP(SUBV),       SH4OP(ADD),        SH4OP(DMULS),      SH4OP(ADDC),       SH4OP(ADDV),
	3178	/* j = 0x4000 - uses op0100_handlers*/
	3179	NULL,          NULL,          NULL,          NULL,          NULL,          NULL,          NULL,          NULL,
	3180	NULL,          NULL,          NULL,          NULL,          NULL,          NULL,          NULL,          NULL,
	3181	/* j = 0x5000 */
	3182	SH4OP(MOVLL4),     SH4OP(MOVLL4),     SH4OP(MOVLL4),     SH4OP(MOVLL4),     SH4OP(MOVLL4),     SH4OP(MOVLL4),     SH4OP(MOVLL4),     SH4OP(MOVLL4),
	3183	SH4OP(MOVLL4),     SH4OP(MOVLL4),     SH4OP(MOVLL4),     SH4OP(MOVLL4),     SH4OP(MOVLL4),     SH4OP(MOVLL4),     SH4OP(MOVLL4),     SH4OP(MOVLL4),
	3184	/* j = 0x6000 */
	3185	SH4OP(MOVBL),      SH4OP(MOVWL),      SH4OP(MOVLL),      SH4OP(MOV),        SH4OP(MOVBP),      SH4OP(MOVWP),      SH4OP(MOVLP),      SH4OP(NOT),
	3186	SH4OP(SWAPB),      SH4OP(SWAPW),      SH4OP(NEGC),       SH4OP(NEG),        SH4OP(EXTUB),      SH4OP(EXTUW),      SH4OP(EXTSB),      SH4OP(EXTSW),
	3187	/* j = 0x7000 */
	3188	SH4OP(ADDI),       SH4OP(ADDI),       SH4OP(ADDI),       SH4OP(ADDI),       SH4OP(ADDI),       SH4OP(ADDI),       SH4OP(ADDI),       SH4OP(ADDI),
	3189	SH4OP(ADDI),       SH4OP(ADDI),       SH4OP(ADDI),       SH4OP(ADDI),       SH4OP(ADDI),       SH4OP(ADDI),       SH4OP(ADDI),       SH4OP(ADDI),
	3190	/* j = 0x8000 - uses op1000_handlers */
	3191	NULL,          NULL,          NULL,          NULL,          NULL,          NULL,          NULL,          NULL,
	3192	NULL,          NULL,          NULL,          NULL,          NULL,          NULL,          NULL,          NULL,
	3193	/* j = 0x9000 */
	3194	SH4OP(MOVWI),      SH4OP(MOVWI),      SH4OP(MOVWI),      SH4OP(MOVWI),      SH4OP(MOVWI),      SH4OP(MOVWI),      SH4OP(MOVWI),      SH4OP(MOVWI),
	3195	SH4OP(MOVWI),      SH4OP(MOVWI),      SH4OP(MOVWI),      SH4OP(MOVWI),      SH4OP(MOVWI),      SH4OP(MOVWI),      SH4OP(MOVWI),      SH4OP(MOVWI),
	3196	/* j = 0xa000 */
	3197	SH4OP(BRA),        SH4OP(BRA),        SH4OP(BRA),        SH4OP(BRA),        SH4OP(BRA),        SH4OP(BRA),        SH4OP(BRA),        SH4OP(BRA),
	3198	SH4OP(BRA),        SH4OP(BRA),        SH4OP(BRA),        SH4OP(BRA),        SH4OP(BRA),        SH4OP(BRA),        SH4OP(BRA),        SH4OP(BRA),
	3199	/* j = 0xb000 */
	3200	SH4OP(BSR),        SH4OP(BSR),        SH4OP(BSR),        SH4OP(BSR),        SH4OP(BSR),        SH4OP(BSR),        SH4OP(BSR),        SH4OP(BSR),
	3201	SH4OP(BSR),        SH4OP(BSR),        SH4OP(BSR),        SH4OP(BSR),        SH4OP(BSR),        SH4OP(BSR),        SH4OP(BSR),        SH4OP(BSR),
	3202	/* j = 0xc000 - uses op1100_handlers */
	3203	NULL,          NULL,          NULL,          NULL,          NULL,          NULL,          NULL,          NULL,
	3204	NULL,          NULL,          NULL,          NULL,          NULL,          NULL,          NULL,          NULL,
	3205	/* j = 0xd000 */
	3206	SH4OP(MOVLI),      SH4OP(MOVLI),      SH4OP(MOVLI),      SH4OP(MOVLI),      SH4OP(MOVLI),      SH4OP(MOVLI),      SH4OP(MOVLI),      SH4OP(MOVLI),
	3207	SH4OP(MOVLI),      SH4OP(MOVLI),      SH4OP(MOVLI),      SH4OP(MOVLI),      SH4OP(MOVLI),      SH4OP(MOVLI),      SH4OP(MOVLI),      SH4OP(MOVLI),
	3208	/* j = 0xe000 */
	3209	SH4OP(MOVI),       SH4OP(MOVI),       SH4OP(MOVI),       SH4OP(MOVI),       SH4OP(MOVI),       SH4OP(MOVI),       SH4OP(MOVI),       SH4OP(MOVI),
	3210	SH4OP(MOVI),       SH4OP(MOVI),       SH4OP(MOVI),       SH4OP(MOVI),       SH4OP(MOVI),       SH4OP(MOVI),       SH4OP(MOVI),       SH4OP(MOVI),
	3211	/* j = 0xf000 */
	3212	SH4OP(FADD),       SH4OP(FSUB),       SH4OP(FMUL),       SH4OP(FDIV),       SH4OP(FCMP_EQ),    SH4OP(FCMP_GT),    SH4OP(FMOVS0FR),   SH4OP(FMOVFRS0),
	3213	SH4OP(FMOVMRFR),   SH4OP(FMOVMRIFR),  SH4OP(FMOVFRMR),   SH4OP(FMOVFRMDR),  SH4OP(FMOVFR),     SH4OP(op1111_0x13),SH4OP(FMAC),       SH4OP(dbreak)
3023	3214	};
3024	3215
3025		void sh4_build_optable(sh4_state *sh4)
	3216	void sh34_base_device::sh4_build_optable()
3026	3217	{
3027	3218	int j,y,x,z;
3028	3219
r31221	r31222
3035	3226	{
3036	3227	for (z=0;z<0x10;z++)
3037	3228	{
3038		master_ophandler_table[j+y+x+z] = upper4bits[(((j+z)&0xf000)>>8) + (z & 0xf)];
	3229	s_master_ophandler_table[j+y+x+z] = s_upper4bits[(((j+z)&0xf000)>>8) + (z & 0xf)];
3039	3230	}
3040	3231	}
3041	3232	}
r31221	r31222
3050	3241	{
3051	3242	for (z=0;z<0x10;z++)
3052	3243	{
3053		master_ophandler_table[j+y+x+z] = op0000_handlers[((((j+y+x+z)&0xf0)>>4)) | ((((j+y+x+z)&0xf)<<4))];
	3244	s_master_ophandler_table[j+y+x+z] = s_op0000_handlers[((((j+y+x+z)&0xf0)>>4)) | ((((j+y+x+z)&0xf)<<4))];
3054	3245	}
3055	3246	}
3056	3247	}
r31221	r31222
3065	3256	{
3066	3257	for (z=0;z<0x10;z++)
3067	3258	{
3068		master_ophandler_table[j+y+x+z] = op0100_handlers[((((j+y+x+z)&0xf0)>>4)) | ((((j+y+x+z)&0xf)<<4))];
	3259	s_master_ophandler_table[j+y+x+z] = s_op0100_handlers[((((j+y+x+z)&0xf0)>>4)) | ((((j+y+x+z)&0xf)<<4))];
3069	3260	}
3070	3261	}
3071	3262	}
r31221	r31222
3081	3272	{
3082	3273	for (z=0;z<0x10;z++)
3083	3274	{
3084		master_ophandler_table[j+y+x+z] = op1000_handler[((((j+y+x+z)&0xf00)>>8))];
	3275	s_master_ophandler_table[j+y+x+z] = s_op1000_handler[((((j+y+x+z)&0xf00)>>8))];
3085	3276	}
3086	3277	}
3087	3278	}
r31221	r31222
3096	3287	{
3097	3288	for (z=0;z<0x10;z++)
3098	3289	{
3099		master_ophandler_table[j+y+x+z] = op1100_handler[((((j+y+x+z)&0xf00)>>8))];
	3290	s_master_ophandler_table[j+y+x+z] = s_op1100_handler[((((j+y+x+z)&0xf00)>>8))];
3100	3291	}
3101	3292	}
3102	3293	}
r31221	r31222
3107	3298
3108	3299
3109	3300	/* Execute cycles - returns number of cycles actually run */
3110		static CPU_EXECUTE( sh4 )
	3301	void sh34_base_device::execute_run()
3111	3302	{
3112		sh4_state *sh4 = get_safe_token(device);
3113
3114		if (sh4->cpu_off)
	3303	if (m_cpu_off)
3115	3304	{
3116		sh4->sh4_icount = 0;
	3305	m_sh4_icount = 0;
3117	3306	return;
3118	3307	}
3119	3308
3120	3309	do
3121	3310	{
3122		if (sh4->delay)
	3311	if (m_delay)
3123	3312	{
3124		const UINT16 opcode = sh4->direct->read_decrypted_word((UINT32)(sh4->delay & AM), WORD2_XOR_LE(0));
	3313	const UINT16 opcode = m_direct->read_decrypted_word((UINT32)(m_delay & AM), WORD2_XOR_LE(0));
3125	3314
3126		debugger_instruction_hook(device, (sh4->pc-2) & AM);
	3315	debugger_instruction_hook(this, (m_pc-2) & AM);
3127	3316
3128		sh4->delay = 0;
3129		sh4->ppc = sh4->pc;
	3317	m_delay = 0;
	3318	m_ppc = m_pc;
3130	3319
3131		master_ophandler_table[opcode](sh4, opcode);
	3320	(this->*s_master_ophandler_table[opcode])(opcode);
3132	3321
3133		if (sh4->test_irq && !sh4->delay)
	3322	if (m_test_irq && !m_delay)
3134	3323	{
3135		sh4_check_pending_irq(sh4, "mame_sh4_execute");
	3324	sh4_check_pending_irq("mame_sh4_execute");
3136	3325	}
3137	3326	}
3138	3327	else
3139	3328	{
3140		const UINT16  opcode = sh4->direct->read_decrypted_word((UINT32)(sh4->pc & AM), WORD2_XOR_LE(0));
	3329	const UINT16  opcode = m_direct->read_decrypted_word((UINT32)(m_pc & AM), WORD2_XOR_LE(0));
3141	3330
3142		debugger_instruction_hook(device, sh4->pc & AM);
	3331	debugger_instruction_hook(this, m_pc & AM);
3143	3332
3144		sh4->pc += 2;
3145		sh4->ppc = sh4->pc;
	3333	m_pc += 2;
	3334	m_ppc = m_pc;
3146	3335
3147		master_ophandler_table[opcode](sh4, opcode);
	3336	(this->*s_master_ophandler_table[opcode])(opcode);
3148	3337
3149		if (sh4->test_irq && !sh4->delay)
	3338	if (m_test_irq && !m_delay)
3150	3339	{
3151		sh4_check_pending_irq(sh4, "mame_sh4_execute");
	3340	sh4_check_pending_irq("mame_sh4_execute");
3152	3341	}
3153	3342	}
3154	3343
3155		sh4->sh4_icount--;
3156		} while( sh4->sh4_icount > 0 );
	3344	m_sh4_icount--;
	3345	} while( m_sh4_icount > 0 );
3157	3346	}
3158	3347
3159		static CPU_EXECUTE( sh4be )
	3348	void sh3be_device::execute_run()
3160	3349	{
3161		sh4_state *sh4 = get_safe_token(device);
3162
3163		if (sh4->cpu_off)
	3350	if (m_cpu_off)
3164	3351	{
3165		sh4->sh4_icount = 0;
	3352	m_sh4_icount = 0;
3166	3353	return;
3167	3354	}
3168	3355
3169	3356	do
3170	3357	{
3171		if (sh4->delay)
	3358	if (m_delay)
3172	3359	{
3173		const UINT16 opcode = sh4->direct->read_decrypted_word((UINT32)(sh4->delay & AM), WORD_XOR_LE(6));
	3360	const UINT16 opcode = m_direct->read_decrypted_word((UINT32)(m_delay & AM), WORD_XOR_LE(6));
3174	3361
3175		debugger_instruction_hook(device, sh4->delay & AM);
	3362	debugger_instruction_hook(this, m_delay & AM);
3176	3363
3177		sh4->delay = 0;
3178		sh4->ppc = sh4->pc;
	3364	m_delay = 0;
	3365	m_ppc = m_pc;
3179	3366
3180		master_ophandler_table[opcode](sh4, opcode);
	3367	(this->*s_master_ophandler_table[opcode])(opcode);
3181	3368
3182	3369
3183		if (sh4->test_irq && !sh4->delay)
	3370	if (m_test_irq && !m_delay)
3184	3371	{
3185		sh4_check_pending_irq(sh4, "mame_sh4_execute");
	3372	sh4_check_pending_irq("mame_sh4_execute");
3186	3373	}
3187	3374
3188	3375
3189	3376	}
3190	3377	else
3191	3378	{
3192		const UINT16 opcode = sh4->direct->read_decrypted_word((UINT32)(sh4->pc & AM), WORD_XOR_LE(6));
	3379	const UINT16 opcode = m_direct->read_decrypted_word((UINT32)(m_pc & AM), WORD_XOR_LE(6));
3193	3380
3194		debugger_instruction_hook(device, sh4->pc & AM);
	3381	debugger_instruction_hook(this, m_pc & AM);
3195	3382
3196		sh4->pc += 2;
3197		sh4->ppc = sh4->pc;
	3383	m_pc += 2;
	3384	m_ppc = m_pc;
3198	3385
3199		master_ophandler_table[opcode](sh4, opcode);
	3386	(this->*s_master_ophandler_table[opcode])(opcode);
3200	3387
3201		if (sh4->test_irq && !sh4->delay)
	3388	if (m_test_irq && !m_delay)
3202	3389	{
3203		sh4_check_pending_irq(sh4, "mame_sh4_execute");
	3390	sh4_check_pending_irq("mame_sh4_execute");
3204	3391	}
3205	3392	}
3206	3393
3207		sh4->sh4_icount--;
3208		} while( sh4->sh4_icount > 0 );
	3394	m_sh4_icount--;
	3395	} while( m_sh4_icount > 0 );
3209	3396	}
3210	3397
3211		static CPU_INIT( sh4 )
	3398	void sh4be_device::execute_run()
3212	3399	{
3213		const struct sh4_config *conf = (const struct sh4_config *)device->static_config();
3214		sh4_state *sh4 = get_safe_token(device);
	3400	if (m_cpu_off)
	3401	{
	3402	m_sh4_icount = 0;
	3403	return;
	3404	}
3215	3405
3216		sh4_common_init(device);
	3406	do
	3407	{
	3408	if (m_delay)
	3409	{
	3410	const UINT16 opcode = m_direct->read_decrypted_word((UINT32)(m_delay & AM), WORD_XOR_LE(6));
3217	3411
3218		sh4_parse_configuration(sh4, conf);
	3412	debugger_instruction_hook(this, m_delay & AM);
3219	3413
3220		sh4->irq_callback = irqcallback;
3221		sh4->device = device;
3222		sh4->internal = &device->space(AS_PROGRAM);
3223		sh4->program = &device->space(AS_PROGRAM);
3224		sh4->io = &device->space(AS_IO);
3225		sh4_default_exception_priorities(sh4);
3226		sh4->irln = 15;
3227		sh4->test_irq = 0;
	3414	m_delay = 0;
	3415	m_ppc = m_pc;
3228	3416
3229		device->save_item(NAME(sh4->pc));
3230		device->save_item(NAME(sh4->r[15]));
3231		device->save_item(NAME(sh4->sr));
3232		device->save_item(NAME(sh4->pr));
3233		device->save_item(NAME(sh4->gbr));
3234		device->save_item(NAME(sh4->vbr));
3235		device->save_item(NAME(sh4->mach));
3236		device->save_item(NAME(sh4->macl));
3237		device->save_item(NAME(sh4->spc));
3238		device->save_item(NAME(sh4->ssr));
3239		device->save_item(NAME(sh4->sgr));
3240		device->save_item(NAME(sh4->fpscr));
3241		device->save_item(NAME(sh4->r[ 0]));
3242		device->save_item(NAME(sh4->r[ 1]));
3243		device->save_item(NAME(sh4->r[ 2]));
3244		device->save_item(NAME(sh4->r[ 3]));
3245		device->save_item(NAME(sh4->r[ 4]));
3246		device->save_item(NAME(sh4->r[ 5]));
3247		device->save_item(NAME(sh4->r[ 6]));
3248		device->save_item(NAME(sh4->r[ 7]));
3249		device->save_item(NAME(sh4->r[ 8]));
3250		device->save_item(NAME(sh4->r[ 9]));
3251		device->save_item(NAME(sh4->r[10]));
3252		device->save_item(NAME(sh4->r[11]));
3253		device->save_item(NAME(sh4->r[12]));
3254		device->save_item(NAME(sh4->r[13]));
3255		device->save_item(NAME(sh4->r[14]));
3256		device->save_item(NAME(sh4->fr[ 0]));
3257		device->save_item(NAME(sh4->fr[ 1]));
3258		device->save_item(NAME(sh4->fr[ 2]));
3259		device->save_item(NAME(sh4->fr[ 3]));
3260		device->save_item(NAME(sh4->fr[ 4]));
3261		device->save_item(NAME(sh4->fr[ 5]));
3262		device->save_item(NAME(sh4->fr[ 6]));
3263		device->save_item(NAME(sh4->fr[ 7]));
3264		device->save_item(NAME(sh4->fr[ 8]));
3265		device->save_item(NAME(sh4->fr[ 9]));
3266		device->save_item(NAME(sh4->fr[10]));
3267		device->save_item(NAME(sh4->fr[11]));
3268		device->save_item(NAME(sh4->fr[12]));
3269		device->save_item(NAME(sh4->fr[13]));
3270		device->save_item(NAME(sh4->fr[14]));
3271		device->save_item(NAME(sh4->fr[15]));
3272		device->save_item(NAME(sh4->xf[ 0]));
3273		device->save_item(NAME(sh4->xf[ 1]));
3274		device->save_item(NAME(sh4->xf[ 2]));
3275		device->save_item(NAME(sh4->xf[ 3]));
3276		device->save_item(NAME(sh4->xf[ 4]));
3277		device->save_item(NAME(sh4->xf[ 5]));
3278		device->save_item(NAME(sh4->xf[ 6]));
3279		device->save_item(NAME(sh4->xf[ 7]));
3280		device->save_item(NAME(sh4->xf[ 8]));
3281		device->save_item(NAME(sh4->xf[ 9]));
3282		device->save_item(NAME(sh4->xf[10]));
3283		device->save_item(NAME(sh4->xf[11]));
3284		device->save_item(NAME(sh4->xf[12]));
3285		device->save_item(NAME(sh4->xf[13]));
3286		device->save_item(NAME(sh4->xf[14]));
3287		device->save_item(NAME(sh4->xf[15]));
3288		device->save_item(NAME(sh4->ea));
3289		device->save_item(NAME(sh4->fpul));
3290		device->save_item(NAME(sh4->dbr));
3291		device->save_item(NAME(sh4->exception_priority));
3292		device->save_item(NAME(sh4->exception_requesting));
	3417	(this->*s_master_ophandler_table[opcode])(opcode);
3293	3418
3294		device->save_item(NAME(sh4->SH4_TSTR));
3295		device->save_item(NAME(sh4->SH4_TCNT0));
3296		device->save_item(NAME(sh4->SH4_TCNT1));
3297		device->save_item(NAME(sh4->SH4_TCNT2));
3298		device->save_item(NAME(sh4->SH4_TCR0));
3299		device->save_item(NAME(sh4->SH4_TCR1));
3300		device->save_item(NAME(sh4->SH4_TCR2));
3301		device->save_item(NAME(sh4->SH4_TCOR0));
3302		device->save_item(NAME(sh4->SH4_TCOR1));
3303		device->save_item(NAME(sh4->SH4_TCOR2));
3304		device->save_item(NAME(sh4->SH4_TOCR));
3305		device->save_item(NAME(sh4->SH4_TCPR2));
3306	3419
3307		device->save_item(NAME(sh4->SH4_IPRA));
	3420	if (m_test_irq && !m_delay)
	3421	{
	3422	sh4_check_pending_irq("mame_sh4_execute");
	3423	}
3308	3424
3309		device->save_item(NAME(sh4->SH4_IPRC));
3310	3425
	3426	}
	3427	else
	3428	{
	3429	const UINT16 opcode = m_direct->read_decrypted_word((UINT32)(m_pc & AM), WORD_XOR_LE(6));
3311	3430
	3431	debugger_instruction_hook(this, m_pc & AM);
3312	3432
	3433	m_pc += 2;
	3434	m_ppc = m_pc;
	3435
	3436	(this->*s_master_ophandler_table[opcode])(opcode);
	3437
	3438	if (m_test_irq && !m_delay)
	3439	{
	3440	sh4_check_pending_irq("mame_sh4_execute");
	3441	}
	3442	}
	3443
	3444	m_sh4_icount--;
	3445	} while( m_sh4_icount > 0 );
3313	3446	}
3314	3447
3315		/**************************************************************************
3316		* Generic set_info
3317		**************************************************************************/
3318
3319		static CPU_SET_INFO( sh4 )
	3448	void sh34_base_device::device_start()
3320	3449	{
3321		sh4_state *sh4 = get_safe_token(device);
	3450	for (int i=0; i<3; i++)
	3451	{
	3452	m_timer[i] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh34_base_device::sh4_timer_callback), this));
	3453	m_timer[i]->adjust(attotime::never, i);
	3454	}
3322	3455
3323		switch (state)
	3456	for (int i=0; i<4; i++)
3324	3457	{
3325		/* --- the following bits of info are set as 64-bit signed integers --- */
3326		case CPUINFO_INT_INPUT_STATE + SH4_IRL0:        sh4_set_irq_line(sh4, SH4_IRL0, info->i);       break;
3327		case CPUINFO_INT_INPUT_STATE + SH4_IRL1:        sh4_set_irq_line(sh4, SH4_IRL1, info->i);       break;
3328		case CPUINFO_INT_INPUT_STATE + SH4_IRL2:        sh4_set_irq_line(sh4, SH4_IRL2, info->i);       break;
3329		case CPUINFO_INT_INPUT_STATE + SH4_IRL3:        sh4_set_irq_line(sh4, SH4_IRL3, info->i);       break;
3330		case CPUINFO_INT_INPUT_STATE + SH4_IRLn:        sh4_set_irq_line(sh4, SH4_IRLn, info->i);       break;
3331		case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI:  sh4_set_irq_line(sh4, INPUT_LINE_NMI, info->i); break;
	3458	m_dma_timer[i] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh34_base_device::sh4_dmac_callback), this));
	3459	m_dma_timer[i]->adjust(attotime::never, i);
	3460	}
3332	3461
3333		case CPUINFO_INT_REGISTER + SH4_PC:
3334		case CPUINFO_INT_PC:                            sh4->pc = info->i; sh4->delay = 0;      break;
3335		case CPUINFO_INT_SP:                            sh4->r[15] = info->i;                   break;
3336		case CPUINFO_INT_REGISTER + SH4_PR:             sh4->pr = info->i;                      break;
3337		case CPUINFO_INT_REGISTER + SH4_SR:
3338		sh4->sr = info->i;
3339		sh4_exception_recompute(sh4);
3340		sh4_check_pending_irq(sh4, "sh4_set_info");
3341		break;
3342		case CPUINFO_INT_REGISTER + SH4_GBR:            sh4->gbr = info->i;                     break;
3343		case CPUINFO_INT_REGISTER + SH4_VBR:            sh4->vbr = info->i;                     break;
3344		case CPUINFO_INT_REGISTER + SH4_DBR:            sh4->dbr = info->i;                     break;
3345		case CPUINFO_INT_REGISTER + SH4_MACH:           sh4->mach = info->i;                        break;
3346		case CPUINFO_INT_REGISTER + SH4_MACL:           sh4->macl = info->i;                        break;
3347		case CPUINFO_INT_REGISTER + SH4_R0:             sh4->r[ 0] = info->i;                   break;
3348		case CPUINFO_INT_REGISTER + SH4_R1:             sh4->r[ 1] = info->i;                   break;
3349		case CPUINFO_INT_REGISTER + SH4_R2:             sh4->r[ 2] = info->i;                   break;
3350		case CPUINFO_INT_REGISTER + SH4_R3:             sh4->r[ 3] = info->i;                   break;
3351		case CPUINFO_INT_REGISTER + SH4_R4:             sh4->r[ 4] = info->i;                   break;
3352		case CPUINFO_INT_REGISTER + SH4_R5:             sh4->r[ 5] = info->i;                   break;
3353		case CPUINFO_INT_REGISTER + SH4_R6:             sh4->r[ 6] = info->i;                   break;
3354		case CPUINFO_INT_REGISTER + SH4_R7:             sh4->r[ 7] = info->i;                   break;
3355		case CPUINFO_INT_REGISTER + SH4_R8:             sh4->r[ 8] = info->i;                   break;
3356		case CPUINFO_INT_REGISTER + SH4_R9:             sh4->r[ 9] = info->i;                   break;
3357		case CPUINFO_INT_REGISTER + SH4_R10:            sh4->r[10] = info->i;                   break;
3358		case CPUINFO_INT_REGISTER + SH4_R11:            sh4->r[11] = info->i;                   break;
3359		case CPUINFO_INT_REGISTER + SH4_R12:            sh4->r[12] = info->i;                   break;
3360		case CPUINFO_INT_REGISTER + SH4_R13:            sh4->r[13] = info->i;                   break;
3361		case CPUINFO_INT_REGISTER + SH4_R14:            sh4->r[14] = info->i;                   break;
3362		case CPUINFO_INT_REGISTER + SH4_R15:            sh4->r[15] = info->i;                   break;
3363		case CPUINFO_INT_REGISTER + SH4_EA:             sh4->ea = info->i;                      break;
3364		case CPUINFO_STR_REGISTER + SH4_R0_BK0:         sh4->rbnk[0][0] = info->i; break;
3365		case CPUINFO_STR_REGISTER + SH4_R1_BK0:         sh4->rbnk[0][1] = info->i; break;
3366		case CPUINFO_STR_REGISTER + SH4_R2_BK0:         sh4->rbnk[0][2] = info->i; break;
3367		case CPUINFO_STR_REGISTER + SH4_R3_BK0:         sh4->rbnk[0][3] = info->i; break;
3368		case CPUINFO_STR_REGISTER + SH4_R4_BK0:         sh4->rbnk[0][4] = info->i; break;
3369		case CPUINFO_STR_REGISTER + SH4_R5_BK0:         sh4->rbnk[0][5] = info->i; break;
3370		case CPUINFO_STR_REGISTER + SH4_R6_BK0:         sh4->rbnk[0][6] = info->i; break;
3371		case CPUINFO_STR_REGISTER + SH4_R7_BK0:         sh4->rbnk[0][7] = info->i; break;
3372		case CPUINFO_STR_REGISTER + SH4_R0_BK1:         sh4->rbnk[1][0] = info->i; break;
3373		case CPUINFO_STR_REGISTER + SH4_R1_BK1:         sh4->rbnk[1][1] = info->i; break;
3374		case CPUINFO_STR_REGISTER + SH4_R2_BK1:         sh4->rbnk[1][2] = info->i; break;
3375		case CPUINFO_STR_REGISTER + SH4_R3_BK1:         sh4->rbnk[1][3] = info->i; break;
3376		case CPUINFO_STR_REGISTER + SH4_R4_BK1:         sh4->rbnk[1][4] = info->i; break;
3377		case CPUINFO_STR_REGISTER + SH4_R5_BK1:         sh4->rbnk[1][5] = info->i; break;
3378		case CPUINFO_STR_REGISTER + SH4_R6_BK1:         sh4->rbnk[1][6] = info->i; break;
3379		case CPUINFO_STR_REGISTER + SH4_R7_BK1:         sh4->rbnk[1][7] = info->i; break;
3380		case CPUINFO_STR_REGISTER + SH4_SPC:            sh4->spc = info->i; break;
3381		case CPUINFO_STR_REGISTER + SH4_SSR:            sh4->ssr = info->i; break;
3382		case CPUINFO_STR_REGISTER + SH4_SGR:            sh4->sgr = info->i; break;
3383		case CPUINFO_STR_REGISTER + SH4_FPSCR:          sh4->fpscr = info->i; break;
3384		case CPUINFO_STR_REGISTER + SH4_FPUL:           sh4->fpul = info->i; break;
	3462	m_refresh_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh34_base_device::sh4_refresh_timer_callback), this));
	3463	m_refresh_timer->adjust(attotime::never);
	3464	m_refresh_timer_base = 0;
	3465
	3466	m_rtc_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh34_base_device::sh4_rtc_timer_callback), this));
	3467	m_rtc_timer->adjust(attotime::never);
	3468
	3469	sh4_parse_configuration();
	3470
	3471	m_internal = &space(AS_PROGRAM);
	3472	m_program = &space(AS_PROGRAM);
	3473	m_io = &space(AS_IO);
	3474	m_direct = &m_program->direct();
	3475	sh4_default_exception_priorities();
	3476	m_irln = 15;
	3477	m_test_irq = 0;
	3478
	3479	save_item(NAME(m_pc));
	3480	save_item(NAME(m_r[15]));
	3481	save_item(NAME(m_sr));
	3482	save_item(NAME(m_pr));
	3483	save_item(NAME(m_gbr));
	3484	save_item(NAME(m_vbr));
	3485	save_item(NAME(m_mach));
	3486	save_item(NAME(m_macl));
	3487	save_item(NAME(m_spc));
	3488	save_item(NAME(m_ssr));
	3489	save_item(NAME(m_sgr));
	3490	save_item(NAME(m_fpscr));
	3491	save_item(NAME(m_r[ 0]));
	3492	save_item(NAME(m_r[ 1]));
	3493	save_item(NAME(m_r[ 2]));
	3494	save_item(NAME(m_r[ 3]));
	3495	save_item(NAME(m_r[ 4]));
	3496	save_item(NAME(m_r[ 5]));
	3497	save_item(NAME(m_r[ 6]));
	3498	save_item(NAME(m_r[ 7]));
	3499	save_item(NAME(m_r[ 8]));
	3500	save_item(NAME(m_r[ 9]));
	3501	save_item(NAME(m_r[10]));
	3502	save_item(NAME(m_r[11]));
	3503	save_item(NAME(m_r[12]));
	3504	save_item(NAME(m_r[13]));
	3505	save_item(NAME(m_r[14]));
	3506	save_item(NAME(m_fr[ 0]));
	3507	save_item(NAME(m_fr[ 1]));
	3508	save_item(NAME(m_fr[ 2]));
	3509	save_item(NAME(m_fr[ 3]));
	3510	save_item(NAME(m_fr[ 4]));
	3511	save_item(NAME(m_fr[ 5]));
	3512	save_item(NAME(m_fr[ 6]));
	3513	save_item(NAME(m_fr[ 7]));
	3514	save_item(NAME(m_fr[ 8]));
	3515	save_item(NAME(m_fr[ 9]));
	3516	save_item(NAME(m_fr[10]));
	3517	save_item(NAME(m_fr[11]));
	3518	save_item(NAME(m_fr[12]));
	3519	save_item(NAME(m_fr[13]));
	3520	save_item(NAME(m_fr[14]));
	3521	save_item(NAME(m_fr[15]));
	3522	save_item(NAME(m_xf[ 0]));
	3523	save_item(NAME(m_xf[ 1]));
	3524	save_item(NAME(m_xf[ 2]));
	3525	save_item(NAME(m_xf[ 3]));
	3526	save_item(NAME(m_xf[ 4]));
	3527	save_item(NAME(m_xf[ 5]));
	3528	save_item(NAME(m_xf[ 6]));
	3529	save_item(NAME(m_xf[ 7]));
	3530	save_item(NAME(m_xf[ 8]));
	3531	save_item(NAME(m_xf[ 9]));
	3532	save_item(NAME(m_xf[10]));
	3533	save_item(NAME(m_xf[11]));
	3534	save_item(NAME(m_xf[12]));
	3535	save_item(NAME(m_xf[13]));
	3536	save_item(NAME(m_xf[14]));
	3537	save_item(NAME(m_xf[15]));
	3538	save_item(NAME(m_ea));
	3539	save_item(NAME(m_fpul));
	3540	save_item(NAME(m_dbr));
	3541	save_item(NAME(m_exception_priority));
	3542	save_item(NAME(m_exception_requesting));
	3543
	3544	save_item(NAME(m_SH4_TSTR));
	3545	save_item(NAME(m_SH4_TCNT0));
	3546	save_item(NAME(m_SH4_TCNT1));
	3547	save_item(NAME(m_SH4_TCNT2));
	3548	save_item(NAME(m_SH4_TCR0));
	3549	save_item(NAME(m_SH4_TCR1));
	3550	save_item(NAME(m_SH4_TCR2));
	3551	save_item(NAME(m_SH4_TCOR0));
	3552	save_item(NAME(m_SH4_TCOR1));
	3553	save_item(NAME(m_SH4_TCOR2));
	3554	save_item(NAME(m_SH4_TOCR));
	3555	save_item(NAME(m_SH4_TCPR2));
	3556
	3557	save_item(NAME(m_SH4_IPRA));
	3558
	3559	save_item(NAME(m_SH4_IPRC));
	3560
	3561	// Debugger state
	3562
	3563	state_add(SH4_PC,             "PC", m_pc).formatstr("%08X").callimport();
	3564	state_add(SH4_SR,             "SR", m_sr).formatstr("%08X").callimport();
	3565	state_add(SH4_PR,             "PR", m_pr).formatstr("%08X");
	3566	state_add(SH4_GBR,            "GBR", m_gbr).formatstr("%08X");
	3567	state_add(SH4_VBR,            "VBR", m_vbr).formatstr("%08X");
	3568	state_add(SH4_DBR,            "DBR", m_dbr).formatstr("%08X");
	3569	state_add(SH4_MACH,           "MACH", m_mach).formatstr("%08X");
	3570	state_add(SH4_MACL,           "MACL", m_macl).formatstr("%08X");
	3571	state_add(SH4_R0,             "R0", m_r[ 0]).formatstr("%08X");
	3572	state_add(SH4_R1,             "R1", m_r[ 1]).formatstr("%08X");
	3573	state_add(SH4_R2,             "R2", m_r[ 2]).formatstr("%08X");
	3574	state_add(SH4_R3,             "R3", m_r[ 3]).formatstr("%08X");
	3575	state_add(SH4_R4,             "R4", m_r[ 4]).formatstr("%08X");
	3576	state_add(SH4_R5,             "R5", m_r[ 5]).formatstr("%08X");
	3577	state_add(SH4_R6,             "R6", m_r[ 6]).formatstr("%08X");
	3578	state_add(SH4_R7,             "R7", m_r[ 7]).formatstr("%08X");
	3579	state_add(SH4_R8,             "R8", m_r[ 8]).formatstr("%08X");
	3580	state_add(SH4_R9,             "R9", m_r[ 9]).formatstr("%08X");
	3581	state_add(SH4_R10,            "R10", m_r[10]).formatstr("%08X");
	3582	state_add(SH4_R11,            "R11", m_r[11]).formatstr("%08X");
	3583	state_add(SH4_R12,            "R12", m_r[12]).formatstr("%08X");
	3584	state_add(SH4_R13,            "R13", m_r[13]).formatstr("%08X");
	3585	state_add(SH4_R14,            "R14", m_r[14]).formatstr("%08X");
	3586	state_add(SH4_R15,            "R15", m_r[15]).formatstr("%08X");
	3587	state_add(SH4_EA,             "EA", m_ea).formatstr("%08X");
	3588	state_add(SH4_R0_BK0,         "R0 BK 0", m_rbnk[0][0]).formatstr("%08X");
	3589	state_add(SH4_R1_BK0,         "R1 BK 0", m_rbnk[0][1]).formatstr("%08X");
	3590	state_add(SH4_R2_BK0,         "R2 BK 0", m_rbnk[0][2]).formatstr("%08X");
	3591	state_add(SH4_R3_BK0,         "R3 BK 0", m_rbnk[0][3]).formatstr("%08X");
	3592	state_add(SH4_R4_BK0,         "R4 BK 0", m_rbnk[0][4]).formatstr("%08X");
	3593	state_add(SH4_R5_BK0,         "R5 BK 0", m_rbnk[0][5]).formatstr("%08X");
	3594	state_add(SH4_R6_BK0,         "R6 BK 0", m_rbnk[0][6]).formatstr("%08X");
	3595	state_add(SH4_R7_BK0,         "R7 BK 0", m_rbnk[0][7]).formatstr("%08X");
	3596	state_add(SH4_R0_BK1,         "R0 BK 1", m_rbnk[1][0]).formatstr("%08X");
	3597	state_add(SH4_R1_BK1,         "R1 BK 1", m_rbnk[1][1]).formatstr("%08X");
	3598	state_add(SH4_R2_BK1,         "R2 BK 1", m_rbnk[1][2]).formatstr("%08X");
	3599	state_add(SH4_R3_BK1,         "R3 BK 1", m_rbnk[1][3]).formatstr("%08X");
	3600	state_add(SH4_R4_BK1,         "R4 BK 1", m_rbnk[1][4]).formatstr("%08X");
	3601	state_add(SH4_R5_BK1,         "R5 BK 1", m_rbnk[1][5]).formatstr("%08X");
	3602	state_add(SH4_R6_BK1,         "R6 BK 1", m_rbnk[1][6]).formatstr("%08X");
	3603	state_add(SH4_R7_BK1,         "R7 BK 1", m_rbnk[1][7]).formatstr("%08X");
	3604	state_add(SH4_SPC,            "SPC", m_spc).formatstr("%08X");
	3605	state_add(SH4_SSR,            "SSR", m_ssr).formatstr("%08X");
	3606	state_add(SH4_SGR,            "SGR", m_sgr).formatstr("%08X");
	3607	state_add(SH4_FPSCR,          "FPSCR", m_fpscr).formatstr("%08X");
	3608	state_add(SH4_FPUL,           "FPUL", m_fpul).formatstr("%08X");
	3609
	3610	state_add(SH4_FR0,            "FR0", m_debugger_temp).callimport().formatstr("%25s");
	3611	state_add(SH4_FR1,            "FR1", m_debugger_temp).callimport().formatstr("%25s");
	3612	state_add(SH4_FR2,            "FR2", m_debugger_temp).callimport().formatstr("%25s");
	3613	state_add(SH4_FR3,            "FR3", m_debugger_temp).callimport().formatstr("%25s");
	3614	state_add(SH4_FR4,            "FR4", m_debugger_temp).callimport().formatstr("%25s");
	3615	state_add(SH4_FR5,            "FR5", m_debugger_temp).callimport().formatstr("%25s");
	3616	state_add(SH4_FR6,            "FR6", m_debugger_temp).callimport().formatstr("%25s");
	3617	state_add(SH4_FR7,            "FR7", m_debugger_temp).callimport().formatstr("%25s");
	3618	state_add(SH4_FR8,            "FR8", m_debugger_temp).callimport().formatstr("%25s");
	3619	state_add(SH4_FR9,            "FR9", m_debugger_temp).callimport().formatstr("%25s");
	3620	state_add(SH4_FR10,           "FR10", m_debugger_temp).callimport().formatstr("%25s");
	3621	state_add(SH4_FR11,           "FR11", m_debugger_temp).callimport().formatstr("%25s");
	3622	state_add(SH4_FR12,           "FR12", m_debugger_temp).callimport().formatstr("%25s");
	3623	state_add(SH4_FR13,           "FR13", m_debugger_temp).callimport().formatstr("%25s");
	3624	state_add(SH4_FR14,           "FR14", m_debugger_temp).callimport().formatstr("%25s");
	3625	state_add(SH4_FR15,           "FR15", m_debugger_temp).callimport().formatstr("%25s");
	3626	state_add(SH4_XF0,            "XF0", m_debugger_temp).callimport().formatstr("%25s");
	3627	state_add(SH4_XF1,            "XF1", m_debugger_temp).callimport().formatstr("%25s");
	3628	state_add(SH4_XF2,            "XF2", m_debugger_temp).callimport().formatstr("%25s");
	3629	state_add(SH4_XF3,            "XF3", m_debugger_temp).callimport().formatstr("%25s");
	3630	state_add(SH4_XF4,            "XF4", m_debugger_temp).callimport().formatstr("%25s");
	3631	state_add(SH4_XF5,            "XF5", m_debugger_temp).callimport().formatstr("%25s");
	3632	state_add(SH4_XF6,            "XF6", m_debugger_temp).callimport().formatstr("%25s");
	3633	state_add(SH4_XF7,            "XF7", m_debugger_temp).callimport().formatstr("%25s");
	3634	state_add(SH4_XF8,            "XF8", m_debugger_temp).callimport().formatstr("%25s");
	3635	state_add(SH4_XF9,            "XF9", m_debugger_temp).callimport().formatstr("%25s");
	3636	state_add(SH4_XF10,           "XF10", m_debugger_temp).callimport().formatstr("%25s");
	3637	state_add(SH4_XF11,           "XF11", m_debugger_temp).callimport().formatstr("%25s");
	3638	state_add(SH4_XF12,           "XF12", m_debugger_temp).callimport().formatstr("%25s");
	3639	state_add(SH4_XF13,           "XF13", m_debugger_temp).callimport().formatstr("%25s");
	3640	state_add(SH4_XF14,           "XF14", m_debugger_temp).callimport().formatstr("%25s");
	3641	state_add(SH4_XF15,           "XF15", m_debugger_temp).callimport().formatstr("%25s");
	3642
	3643	state_add(STATE_GENPC, "GENPC", m_debugger_temp).callimport().callexport().noshow();
	3644	state_add(STATE_GENSP, "GENSP", m_r[15]).noshow();
	3645	state_add(STATE_GENPCBASE, "GENPCBASE", m_ppc).noshow();
	3646	state_add(STATE_GENFLAGS, "GENFLAGS", m_sr).formatstr("%20s").noshow();
	3647
	3648	m_icountptr = &m_sh4_icount;
	3649	}
	3650
	3651	void sh34_base_device::state_import(const device_state_entry &entry)
	3652	{
3385	3653	#ifdef LSB_FIRST
3386		case CPUINFO_STR_REGISTER + SH4_FR0:            sh4->fr[ 0 ^ sh4->fpu_pr] = info->i; break;
3387		case CPUINFO_STR_REGISTER + SH4_FR1:            sh4->fr[ 1 ^ sh4->fpu_pr] = info->i; break;
3388		case CPUINFO_STR_REGISTER + SH4_FR2:            sh4->fr[ 2 ^ sh4->fpu_pr] = info->i; break;
3389		case CPUINFO_STR_REGISTER + SH4_FR3:            sh4->fr[ 3 ^ sh4->fpu_pr] = info->i; break;
3390		case CPUINFO_STR_REGISTER + SH4_FR4:            sh4->fr[ 4 ^ sh4->fpu_pr] = info->i; break;
3391		case CPUINFO_STR_REGISTER + SH4_FR5:            sh4->fr[ 5 ^ sh4->fpu_pr] = info->i; break;
3392		case CPUINFO_STR_REGISTER + SH4_FR6:            sh4->fr[ 6 ^ sh4->fpu_pr] = info->i; break;
3393		case CPUINFO_STR_REGISTER + SH4_FR7:            sh4->fr[ 7 ^ sh4->fpu_pr] = info->i; break;
3394		case CPUINFO_STR_REGISTER + SH4_FR8:            sh4->fr[ 8 ^ sh4->fpu_pr] = info->i; break;
3395		case CPUINFO_STR_REGISTER + SH4_FR9:            sh4->fr[ 9 ^ sh4->fpu_pr] = info->i; break;
3396		case CPUINFO_STR_REGISTER + SH4_FR10:           sh4->fr[10 ^ sh4->fpu_pr] = info->i; break;
3397		case CPUINFO_STR_REGISTER + SH4_FR11:           sh4->fr[11 ^ sh4->fpu_pr] = info->i; break;
3398		case CPUINFO_STR_REGISTER + SH4_FR12:           sh4->fr[12 ^ sh4->fpu_pr] = info->i; break;
3399		case CPUINFO_STR_REGISTER + SH4_FR13:           sh4->fr[13 ^ sh4->fpu_pr] = info->i; break;
3400		case CPUINFO_STR_REGISTER + SH4_FR14:           sh4->fr[14 ^ sh4->fpu_pr] = info->i; break;
3401		case CPUINFO_STR_REGISTER + SH4_FR15:           sh4->fr[15 ^ sh4->fpu_pr] = info->i; break;
3402		case CPUINFO_STR_REGISTER + SH4_XF0:            sh4->xf[ 0 ^ sh4->fpu_pr] = info->i; break;
3403		case CPUINFO_STR_REGISTER + SH4_XF1:            sh4->xf[ 1 ^ sh4->fpu_pr] = info->i; break;
3404		case CPUINFO_STR_REGISTER + SH4_XF2:            sh4->xf[ 2 ^ sh4->fpu_pr] = info->i; break;
3405		case CPUINFO_STR_REGISTER + SH4_XF3:            sh4->xf[ 3 ^ sh4->fpu_pr] = info->i; break;
3406		case CPUINFO_STR_REGISTER + SH4_XF4:            sh4->xf[ 4 ^ sh4->fpu_pr] = info->i; break;
3407		case CPUINFO_STR_REGISTER + SH4_XF5:            sh4->xf[ 5 ^ sh4->fpu_pr] = info->i; break;
3408		case CPUINFO_STR_REGISTER + SH4_XF6:            sh4->xf[ 6 ^ sh4->fpu_pr] = info->i; break;
3409		case CPUINFO_STR_REGISTER + SH4_XF7:            sh4->xf[ 7 ^ sh4->fpu_pr] = info->i; break;
3410		case CPUINFO_STR_REGISTER + SH4_XF8:            sh4->xf[ 8 ^ sh4->fpu_pr] = info->i; break;
3411		case CPUINFO_STR_REGISTER + SH4_XF9:            sh4->xf[ 9 ^ sh4->fpu_pr] = info->i; break;
3412		case CPUINFO_STR_REGISTER + SH4_XF10:           sh4->xf[10 ^ sh4->fpu_pr] = info->i; break;
3413		case CPUINFO_STR_REGISTER + SH4_XF11:           sh4->xf[11 ^ sh4->fpu_pr] = info->i; break;
3414		case CPUINFO_STR_REGISTER + SH4_XF12:           sh4->xf[12 ^ sh4->fpu_pr] = info->i; break;
3415		case CPUINFO_STR_REGISTER + SH4_XF13:           sh4->xf[13 ^ sh4->fpu_pr] = info->i; break;
3416		case CPUINFO_STR_REGISTER + SH4_XF14:           sh4->xf[14 ^ sh4->fpu_pr] = info->i; break;
3417		case CPUINFO_STR_REGISTER + SH4_XF15:           sh4->xf[15 ^ sh4->fpu_pr] = info->i; break;
	3654	UINT8 fpu_xor = m_fpu_pr;
3418	3655	#else
3419		case CPUINFO_STR_REGISTER + SH4_FR0:            sh4->fr[ 0] = info->i; break;
3420		case CPUINFO_STR_REGISTER + SH4_FR1:            sh4->fr[ 1] = info->i; break;
3421		case CPUINFO_STR_REGISTER + SH4_FR2:            sh4->fr[ 2] = info->i; break;
3422		case CPUINFO_STR_REGISTER + SH4_FR3:            sh4->fr[ 3] = info->i; break;
3423		case CPUINFO_STR_REGISTER + SH4_FR4:            sh4->fr[ 4] = info->i; break;
3424		case CPUINFO_STR_REGISTER + SH4_FR5:            sh4->fr[ 5] = info->i; break;
3425		case CPUINFO_STR_REGISTER + SH4_FR6:            sh4->fr[ 6] = info->i; break;
3426		case CPUINFO_STR_REGISTER + SH4_FR7:            sh4->fr[ 7] = info->i; break;
3427		case CPUINFO_STR_REGISTER + SH4_FR8:            sh4->fr[ 8] = info->i; break;
3428		case CPUINFO_STR_REGISTER + SH4_FR9:            sh4->fr[ 9] = info->i; break;
3429		case CPUINFO_STR_REGISTER + SH4_FR10:           sh4->fr[10] = info->i; break;
3430		case CPUINFO_STR_REGISTER + SH4_FR11:           sh4->fr[11] = info->i; break;
3431		case CPUINFO_STR_REGISTER + SH4_FR12:           sh4->fr[12] = info->i; break;
3432		case CPUINFO_STR_REGISTER + SH4_FR13:           sh4->fr[13] = info->i; break;
3433		case CPUINFO_STR_REGISTER + SH4_FR14:           sh4->fr[14] = info->i; break;
3434		case CPUINFO_STR_REGISTER + SH4_FR15:           sh4->fr[15] = info->i; break;
3435		case CPUINFO_STR_REGISTER + SH4_XF0:            sh4->xf[ 0] = info->i; break;
3436		case CPUINFO_STR_REGISTER + SH4_XF1:            sh4->xf[ 1] = info->i; break;
3437		case CPUINFO_STR_REGISTER + SH4_XF2:            sh4->xf[ 2] = info->i; break;
3438		case CPUINFO_STR_REGISTER + SH4_XF3:            sh4->xf[ 3] = info->i; break;
3439		case CPUINFO_STR_REGISTER + SH4_XF4:            sh4->xf[ 4] = info->i; break;
3440		case CPUINFO_STR_REGISTER + SH4_XF5:            sh4->xf[ 5] = info->i; break;
3441		case CPUINFO_STR_REGISTER + SH4_XF6:            sh4->xf[ 6] = info->i; break;
3442		case CPUINFO_STR_REGISTER + SH4_XF7:            sh4->xf[ 7] = info->i; break;
3443		case CPUINFO_STR_REGISTER + SH4_XF8:            sh4->xf[ 8] = info->i; break;
3444		case CPUINFO_STR_REGISTER + SH4_XF9:            sh4->xf[ 9] = info->i; break;
3445		case CPUINFO_STR_REGISTER + SH4_XF10:           sh4->xf[10] = info->i; break;
3446		case CPUINFO_STR_REGISTER + SH4_XF11:           sh4->xf[11] = info->i; break;
3447		case CPUINFO_STR_REGISTER + SH4_XF12:           sh4->xf[12] = info->i; break;
3448		case CPUINFO_STR_REGISTER + SH4_XF13:           sh4->xf[13] = info->i; break;
3449		case CPUINFO_STR_REGISTER + SH4_XF14:           sh4->xf[14] = info->i; break;
3450		case CPUINFO_STR_REGISTER + SH4_XF15:           sh4->xf[15] = info->i; break;
	3656	UINT8 fpu_xor = 0;
3451	3657	#endif
3452		}
3453		}
3454	3658
3455		void sh4_set_ftcsr_callback(device_t *device, sh4_ftcsr_callback callback)
3456		{
3457		sh4_state *sh4 = get_safe_token(device);
3458		sh4->ftcsr_read_callback = callback;
3459		}
	3659	switch (entry.index())
	3660	{
	3661	case STATE_GENPC:
	3662	m_pc = m_debugger_temp;
	3663	case SH4_PC:
	3664	m_delay = 0;
	3665	break;
3460	3666
	3667	case SH4_SR:
	3668	sh4_exception_recompute();
	3669	sh4_check_pending_irq("sh4_set_info");
	3670	break;
3461	3671
3462		#if 0
3463		/*When OC index mode is off (CCR.OIX = 0)*/
3464		static ADDRESS_MAP_START( sh4_internal_map, AS_PROGRAM, 64, sh4_device )
3465		AM_RANGE(0x1C000000, 0x1C000FFF) AM_RAM AM_MIRROR(0x03FFD000)
3466		AM_RANGE(0x1C002000, 0x1C002FFF) AM_RAM AM_MIRROR(0x03FFD000)
3467		AM_RANGE(0xE0000000, 0xE000003F) AM_RAM AM_MIRROR(0x03FFFFC0)
3468		ADDRESS_MAP_END
3469		#endif
	3672	case SH4_FR0:
	3673	m_fr[0 ^ fpu_xor] = m_debugger_temp;
	3674	break;
3470	3675
3471		/*When OC index mode is on (CCR.OIX = 1)*/
3472		static ADDRESS_MAP_START( sh4_internal_map, AS_PROGRAM, 64, sh4_device )
3473		AM_RANGE(0x1C000000, 0x1C000FFF) AM_RAM AM_MIRROR(0x01FFF000)
3474		AM_RANGE(0x1E000000, 0x1E000FFF) AM_RAM AM_MIRROR(0x01FFF000)
3475		AM_RANGE(0xE0000000, 0xE000003F) AM_RAM AM_MIRROR(0x03FFFFC0) // todo: store queues should be write only on DC's SH4, executing PREFM shouldn't cause an actual memory read access!
3476		AM_RANGE(0xF6000000, 0xF7FFFFFF) AM_READWRITE(sh4_tlb_r,sh4_tlb_w)
3477		AM_RANGE(0xFE000000, 0xFFFFFFFF) AM_READWRITE32(sh4_internal_r, sh4_internal_w, U64(0xffffffffffffffff))
3478		ADDRESS_MAP_END
	3676	case SH4_FR1:
	3677	m_fr[1 ^ fpu_xor] = m_debugger_temp;
	3678	break;
3479	3679
3480		static ADDRESS_MAP_START( sh3_internal_map, AS_PROGRAM, 64, sh3_device )
3481		AM_RANGE(SH3_LOWER_REGBASE, SH3_LOWER_REGEND) AM_READWRITE32(sh3_internal_r, sh3_internal_w, U64(0xffffffffffffffff))
3482		AM_RANGE(SH3_UPPER_REGBASE, SH3_UPPER_REGEND) AM_READWRITE32(sh3_internal_high_r, sh3_internal_high_w, U64(0xffffffffffffffff))
3483		ADDRESS_MAP_END
	3680	case SH4_FR2:
	3681	m_fr[2 ^ fpu_xor] = m_debugger_temp;
	3682	break;
3484	3683
	3684	case SH4_FR3:
	3685	m_fr[3 ^ fpu_xor] = m_debugger_temp;
	3686	break;
3485	3687
3486		/**************************************************************************
3487		* Generic get_info
3488		**************************************************************************/
	3688	case SH4_FR4:
	3689	m_fr[4 ^ fpu_xor] = m_debugger_temp;
	3690	break;
3489	3691
3490		CPU_GET_INFO( sh4 )
3491		{
3492		sh4_state *sh4 = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
	3692	case SH4_FR5:
	3693	m_fr[5 ^ fpu_xor] = m_debugger_temp;
	3694	break;
3493	3695
3494		switch (state)
3495		{
3496		/* --- the following bits of info are returned as 64-bit signed integers --- */
3497		case CPUINFO_INT_CONTEXT_SIZE:                  info->i = sizeof(sh4_state);        break;
3498		case CPUINFO_INT_INPUT_LINES:                   info->i = 5;                        break;
3499		case CPUINFO_INT_DEFAULT_IRQ_VECTOR:            info->i = 0;                        break;
3500		case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_LITTLE;                break;
3501		case CPUINFO_INT_CLOCK_MULTIPLIER:              info->i = 1;                        break;
3502		case CPUINFO_INT_CLOCK_DIVIDER:                 info->i = 1;                        break;
3503		case CPUINFO_INT_MIN_INSTRUCTION_BYTES:         info->i = 2;                        break;
3504		case CPUINFO_INT_MAX_INSTRUCTION_BYTES:         info->i = 2;                        break;
3505		case CPUINFO_INT_MIN_CYCLES:                    info->i = 1;                        break;
3506		case CPUINFO_INT_MAX_CYCLES:                    info->i = 4;                        break;
	3696	case SH4_FR6:
	3697	m_fr[6 ^ fpu_xor] = m_debugger_temp;
	3698	break;
3507	3699
3508		case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:        info->i = 64;               break;
3509		case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM:    info->i = 32;               break;
3510		case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM:    info->i = 0;                break;
3511		case CPUINFO_INT_DATABUS_WIDTH + AS_DATA:       info->i = 0;                break;
3512		case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA:       info->i = 0;                break;
3513		case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA:       info->i = 0;                break;
3514		case CPUINFO_INT_DATABUS_WIDTH + AS_IO:     info->i = 64;                   break;
3515		case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO:     info->i = 8;                    break;
3516		case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO:     info->i = 0;                    break;
	3700	case SH4_FR7:
	3701	m_fr[7 ^ fpu_xor] = m_debugger_temp;
	3702	break;
3517	3703
3518		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map64 = ADDRESS_MAP_NAME(sh4_internal_map); break;
	3704	case SH4_FR8:
	3705	m_fr[8 ^ fpu_xor] = m_debugger_temp;
	3706	break;
3519	3707
3520		case CPUINFO_INT_INPUT_STATE + SH4_IRL0:        info->i = sh4->irq_line_state[SH4_IRL0]; break;
3521		case CPUINFO_INT_INPUT_STATE + SH4_IRL1:        info->i = sh4->irq_line_state[SH4_IRL1]; break;
3522		case CPUINFO_INT_INPUT_STATE + SH4_IRL2:        info->i = sh4->irq_line_state[SH4_IRL2]; break;
3523		case CPUINFO_INT_INPUT_STATE + SH4_IRL3:        info->i = sh4->irq_line_state[SH4_IRL3]; break;
3524		case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI:  info->i = sh4->nmi_line_state;          break;
	3708	case SH4_FR9:
	3709	m_fr[9 ^ fpu_xor] = m_debugger_temp;
	3710	break;
3525	3711
3526		case CPUINFO_INT_PREVIOUSPC:                    info->i = sh4->ppc;                     break;
	3712	case SH4_FR10:
	3713	m_fr[10 ^ fpu_xor] = m_debugger_temp;
	3714	break;
3527	3715
3528		case CPUINFO_INT_PC:
3529		case CPUINFO_INT_REGISTER + SH4_PC:             info->i = (sh4->delay) ? (sh4->delay & AM) : (sh4->pc & AM); break;
3530		case CPUINFO_INT_SP:                            info->i = sh4->r[15];                   break;
3531		case CPUINFO_INT_REGISTER + SH4_PR:             info->i = sh4->pr;                      break;
3532		case CPUINFO_INT_REGISTER + SH4_SR:             info->i = sh4->sr;                      break;
3533		case CPUINFO_INT_REGISTER + SH4_GBR:            info->i = sh4->gbr;                     break;
3534		case CPUINFO_INT_REGISTER + SH4_VBR:            info->i = sh4->vbr;                     break;
3535		case CPUINFO_INT_REGISTER + SH4_DBR:            info->i = sh4->dbr;                     break;
3536		case CPUINFO_INT_REGISTER + SH4_MACH:           info->i = sh4->mach;                        break;
3537		case CPUINFO_INT_REGISTER + SH4_MACL:           info->i = sh4->macl;                        break;
3538		case CPUINFO_INT_REGISTER + SH4_R0:             info->i = sh4->r[ 0];                   break;
3539		case CPUINFO_INT_REGISTER + SH4_R1:             info->i = sh4->r[ 1];                   break;
3540		case CPUINFO_INT_REGISTER + SH4_R2:             info->i = sh4->r[ 2];                   break;
3541		case CPUINFO_INT_REGISTER + SH4_R3:             info->i = sh4->r[ 3];                   break;
3542		case CPUINFO_INT_REGISTER + SH4_R4:             info->i = sh4->r[ 4];                   break;
3543		case CPUINFO_INT_REGISTER + SH4_R5:             info->i = sh4->r[ 5];                   break;
3544		case CPUINFO_INT_REGISTER + SH4_R6:             info->i = sh4->r[ 6];                   break;
3545		case CPUINFO_INT_REGISTER + SH4_R7:             info->i = sh4->r[ 7];                   break;
3546		case CPUINFO_INT_REGISTER + SH4_R8:             info->i = sh4->r[ 8];                   break;
3547		case CPUINFO_INT_REGISTER + SH4_R9:             info->i = sh4->r[ 9];                   break;
3548		case CPUINFO_INT_REGISTER + SH4_R10:            info->i = sh4->r[10];                   break;
3549		case CPUINFO_INT_REGISTER + SH4_R11:            info->i = sh4->r[11];                   break;
3550		case CPUINFO_INT_REGISTER + SH4_R12:            info->i = sh4->r[12];                   break;
3551		case CPUINFO_INT_REGISTER + SH4_R13:            info->i = sh4->r[13];                   break;
3552		case CPUINFO_INT_REGISTER + SH4_R14:            info->i = sh4->r[14];                   break;
3553		case CPUINFO_INT_REGISTER + SH4_R15:            info->i = sh4->r[15];                   break;
3554		case CPUINFO_INT_REGISTER + SH4_EA:             info->i = sh4->ea;                      break;
	3716	case SH4_FR11:
	3717	m_fr[11 ^ fpu_xor] = m_debugger_temp;
	3718	break;
3555	3719
3556		/* --- the following bits of info are returned as pointers to data or functions --- */
3557		case CPUINFO_FCT_SET_INFO:                      info->setinfo = CPU_SET_INFO_NAME(sh4);         break;
3558		case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(sh4);                    break;
3559		case CPUINFO_FCT_RESET:                         info->reset = CPU_RESET_NAME(sh4);              break;
3560		case CPUINFO_FCT_EXECUTE:                       info->execute = CPU_EXECUTE_NAME(sh4);          break;
3561		case CPUINFO_FCT_BURN:                          info->burn = NULL;                      break;
3562		case CPUINFO_FCT_DISASSEMBLE:                   info->disassemble = CPU_DISASSEMBLE_NAME(sh4);          break;
3563		case CPUINFO_PTR_INSTRUCTION_COUNTER:           info->icount = &sh4->sh4_icount;                break;
	3720	case SH4_FR12:
	3721	m_fr[12 ^ fpu_xor] = m_debugger_temp;
	3722	break;
3564	3723
3565		/* --- the following bits of info are returned as NULL-terminated strings --- */
3566		case CPUINFO_STR_NAME:                      strcpy(info->s, "SH-4 (little)");                break;
3567		case CPUINFO_STR_SHORTNAME:                 strcpy(info->s, "sh4");                break;
3568		case CPUINFO_STR_FAMILY:                    strcpy(info->s, "Hitachi SH7750");      break;
3569		case CPUINFO_STR_VERSION:                   strcpy(info->s, "1.0");             break;
3570		case CPUINFO_STR_SOURCE_FILE:                   strcpy(info->s, __FILE__);              break;
3571		case CPUINFO_STR_CREDITS:                   strcpy(info->s, "Copyright R. Belmont"); break;
	3724	case SH4_FR13:
	3725	m_fr[13 ^ fpu_xor] = m_debugger_temp;
	3726	break;
3572	3727
3573		case CPUINFO_STR_FLAGS:
3574		sprintf(info->s, "%s%s%s%s%c%c%d%c%c",
3575		sh4->sr & MD ? "MD ":"   ",
3576		sh4->sr & sRB ? "RB ":"   ",
3577		sh4->sr & BL ? "BL ":"   ",
3578		sh4->sr & FD ? "FD ":"   ",
3579		sh4->sr & M ? 'M':'.',
3580		sh4->sr & Q ? 'Q':'.',
3581		(sh4->sr & I) >> 4,
3582		sh4->sr & S ? 'S':'.',
3583		sh4->sr & T ? 'T':'.');
	3728	case SH4_FR14:
	3729	m_fr[14 ^ fpu_xor] = m_debugger_temp;
3584	3730	break;
3585	3731
3586		case CPUINFO_STR_REGISTER + SH4_PC:             sprintf(info->s, "PC  :%08X", sh4->pc); break;
3587		case CPUINFO_STR_REGISTER + SH4_SR:             sprintf(info->s, "SR  :%08X", sh4->sr); break;
3588		case CPUINFO_STR_REGISTER + SH4_PR:             sprintf(info->s, "PR  :%08X", sh4->pr); break;
3589		case CPUINFO_STR_REGISTER + SH4_GBR:            sprintf(info->s, "GBR :%08X", sh4->gbr); break;
3590		case CPUINFO_STR_REGISTER + SH4_VBR:            sprintf(info->s, "VBR :%08X", sh4->vbr); break;
3591		case CPUINFO_STR_REGISTER + SH4_DBR:            sprintf(info->s, "DBR :%08X", sh4->dbr); break;
3592		case CPUINFO_STR_REGISTER + SH4_MACH:           sprintf(info->s, "MACH:%08X", sh4->mach); break;
3593		case CPUINFO_STR_REGISTER + SH4_MACL:           sprintf(info->s, "MACL:%08X", sh4->macl); break;
3594		case CPUINFO_STR_REGISTER + SH4_R0:             sprintf(info->s, "R0  :%08X", sh4->r[ 0]); break;
3595		case CPUINFO_STR_REGISTER + SH4_R1:             sprintf(info->s, "R1  :%08X", sh4->r[ 1]); break;
3596		case CPUINFO_STR_REGISTER + SH4_R2:             sprintf(info->s, "R2  :%08X", sh4->r[ 2]); break;
3597		case CPUINFO_STR_REGISTER + SH4_R3:             sprintf(info->s, "R3  :%08X", sh4->r[ 3]); break;
3598		case CPUINFO_STR_REGISTER + SH4_R4:             sprintf(info->s, "R4  :%08X", sh4->r[ 4]); break;
3599		case CPUINFO_STR_REGISTER + SH4_R5:             sprintf(info->s, "R5  :%08X", sh4->r[ 5]); break;
3600		case CPUINFO_STR_REGISTER + SH4_R6:             sprintf(info->s, "R6  :%08X", sh4->r[ 6]); break;
3601		case CPUINFO_STR_REGISTER + SH4_R7:             sprintf(info->s, "R7  :%08X", sh4->r[ 7]); break;
3602		case CPUINFO_STR_REGISTER + SH4_R8:             sprintf(info->s, "R8  :%08X", sh4->r[ 8]); break;
3603		case CPUINFO_STR_REGISTER + SH4_R9:             sprintf(info->s, "R9  :%08X", sh4->r[ 9]); break;
3604		case CPUINFO_STR_REGISTER + SH4_R10:            sprintf(info->s, "R10 :%08X", sh4->r[10]); break;
3605		case CPUINFO_STR_REGISTER + SH4_R11:            sprintf(info->s, "R11 :%08X", sh4->r[11]); break;
3606		case CPUINFO_STR_REGISTER + SH4_R12:            sprintf(info->s, "R12 :%08X", sh4->r[12]); break;
3607		case CPUINFO_STR_REGISTER + SH4_R13:            sprintf(info->s, "R13 :%08X", sh4->r[13]); break;
3608		case CPUINFO_STR_REGISTER + SH4_R14:            sprintf(info->s, "R14 :%08X", sh4->r[14]); break;
3609		case CPUINFO_STR_REGISTER + SH4_R15:            sprintf(info->s, "R15 :%08X", sh4->r[15]); break;
3610		case CPUINFO_STR_REGISTER + SH4_EA:             sprintf(info->s, "EA  :%08X", sh4->ea);    break;
3611		case CPUINFO_STR_REGISTER + SH4_R0_BK0:         sprintf(info->s, "R0 BK 0  :%08X", sh4->rbnk[0][0]); break;
3612		case CPUINFO_STR_REGISTER + SH4_R1_BK0:         sprintf(info->s, "R1 BK 0 :%08X", sh4->rbnk[0][1]); break;
3613		case CPUINFO_STR_REGISTER + SH4_R2_BK0:         sprintf(info->s, "R2 BK 0 :%08X", sh4->rbnk[0][2]); break;
3614		case CPUINFO_STR_REGISTER + SH4_R3_BK0:         sprintf(info->s, "R3 BK 0 :%08X", sh4->rbnk[0][3]); break;
3615		case CPUINFO_STR_REGISTER + SH4_R4_BK0:         sprintf(info->s, "R4 BK 0 :%08X", sh4->rbnk[0][4]); break;
3616		case CPUINFO_STR_REGISTER + SH4_R5_BK0:         sprintf(info->s, "R5 BK 0 :%08X", sh4->rbnk[0][5]); break;
3617		case CPUINFO_STR_REGISTER + SH4_R6_BK0:         sprintf(info->s, "R6 BK 0 :%08X", sh4->rbnk[0][6]); break;
3618		case CPUINFO_STR_REGISTER + SH4_R7_BK0:         sprintf(info->s, "R7 BK 0 :%08X", sh4->rbnk[0][7]); break;
3619		case CPUINFO_STR_REGISTER + SH4_R0_BK1:         sprintf(info->s, "R0 BK 1 :%08X", sh4->rbnk[1][0]); break;
3620		case CPUINFO_STR_REGISTER + SH4_R1_BK1:         sprintf(info->s, "R1 BK 1 :%08X", sh4->rbnk[1][1]); break;
3621		case CPUINFO_STR_REGISTER + SH4_R2_BK1:         sprintf(info->s, "R2 BK 1 :%08X", sh4->rbnk[1][2]); break;
3622		case CPUINFO_STR_REGISTER + SH4_R3_BK1:         sprintf(info->s, "R3 BK 1 :%08X", sh4->rbnk[1][3]); break;
3623		case CPUINFO_STR_REGISTER + SH4_R4_BK1:         sprintf(info->s, "R4 BK 1 :%08X", sh4->rbnk[1][4]); break;
3624		case CPUINFO_STR_REGISTER + SH4_R5_BK1:         sprintf(info->s, "R5 BK 1 :%08X", sh4->rbnk[1][5]); break;
3625		case CPUINFO_STR_REGISTER + SH4_R6_BK1:         sprintf(info->s, "R6 BK 1 :%08X", sh4->rbnk[1][6]); break;
3626		case CPUINFO_STR_REGISTER + SH4_R7_BK1:         sprintf(info->s, "R7 BK 1 :%08X", sh4->rbnk[1][7]); break;
3627		case CPUINFO_STR_REGISTER + SH4_SPC:            sprintf(info->s, "SPC  :%08X", sh4->spc); break;
3628		case CPUINFO_STR_REGISTER + SH4_SSR:            sprintf(info->s, "SSR  :%08X", sh4->ssr); break;
3629		case CPUINFO_STR_REGISTER + SH4_SGR:            sprintf(info->s, "SGR  :%08X", sh4->sgr); break;
3630		case CPUINFO_STR_REGISTER + SH4_FPSCR:          sprintf(info->s, "FPSCR :%08X", sh4->fpscr); break;
3631		case CPUINFO_STR_REGISTER + SH4_FPUL:           sprintf(info->s, "FPUL :%08X", sh4->fpul); break;
3632		#ifdef LSB_FIRST
3633		case CPUINFO_STR_REGISTER + SH4_FR0:            sprintf(info->s, "FR0  :%08X %f", FP_RS2( 0),(double)FP_RFS2( 0)); break;
3634		case CPUINFO_STR_REGISTER + SH4_FR1:            sprintf(info->s, "FR1  :%08X %f", FP_RS2( 1),(double)FP_RFS2( 1)); break;
3635		case CPUINFO_STR_REGISTER + SH4_FR2:            sprintf(info->s, "FR2  :%08X %f", FP_RS2( 2),(double)FP_RFS2( 2)); break;
3636		case CPUINFO_STR_REGISTER + SH4_FR3:            sprintf(info->s, "FR3  :%08X %f", FP_RS2( 3),(double)FP_RFS2( 3)); break;
3637		case CPUINFO_STR_REGISTER + SH4_FR4:            sprintf(info->s, "FR4  :%08X %f", FP_RS2( 4),(double)FP_RFS2( 4)); break;
3638		case CPUINFO_STR_REGISTER + SH4_FR5:            sprintf(info->s, "FR5  :%08X %f", FP_RS2( 5),(double)FP_RFS2( 5)); break;
3639		case CPUINFO_STR_REGISTER + SH4_FR6:            sprintf(info->s, "FR6  :%08X %f", FP_RS2( 6),(double)FP_RFS2( 6)); break;
3640		case CPUINFO_STR_REGISTER + SH4_FR7:            sprintf(info->s, "FR7  :%08X %f", FP_RS2( 7),(double)FP_RFS2( 7)); break;
3641		case CPUINFO_STR_REGISTER + SH4_FR8:            sprintf(info->s, "FR8  :%08X %f", FP_RS2( 8),(double)FP_RFS2( 8)); break;
3642		case CPUINFO_STR_REGISTER + SH4_FR9:            sprintf(info->s, "FR9  :%08X %f", FP_RS2( 9),(double)FP_RFS2( 9)); break;
3643		case CPUINFO_STR_REGISTER + SH4_FR10:           sprintf(info->s, "FR10 :%08X %f", FP_RS2(10),(double)FP_RFS2(10)); break;
3644		case CPUINFO_STR_REGISTER + SH4_FR11:           sprintf(info->s, "FR11 :%08X %f", FP_RS2(11),(double)FP_RFS2(11)); break;
3645		case CPUINFO_STR_REGISTER + SH4_FR12:           sprintf(info->s, "FR12 :%08X %f", FP_RS2(12),(double)FP_RFS2(12)); break;
3646		case CPUINFO_STR_REGISTER + SH4_FR13:           sprintf(info->s, "FR13 :%08X %f", FP_RS2(13),(double)FP_RFS2(13)); break;
3647		case CPUINFO_STR_REGISTER + SH4_FR14:           sprintf(info->s, "FR14 :%08X %f", FP_RS2(14),(double)FP_RFS2(14)); break;
3648		case CPUINFO_STR_REGISTER + SH4_FR15:           sprintf(info->s, "FR15 :%08X %f", FP_RS2(15),(double)FP_RFS2(15)); break;
3649		case CPUINFO_STR_REGISTER + SH4_XF0:            sprintf(info->s, "XF0  :%08X %f", FP_XS2( 0),(double)FP_XFS2( 0)); break;
3650		case CPUINFO_STR_REGISTER + SH4_XF1:            sprintf(info->s, "XF1  :%08X %f", FP_XS2( 1),(double)FP_XFS2( 1)); break;
3651		case CPUINFO_STR_REGISTER + SH4_XF2:            sprintf(info->s, "XF2  :%08X %f", FP_XS2( 2),(double)FP_XFS2( 2)); break;
3652		case CPUINFO_STR_REGISTER + SH4_XF3:            sprintf(info->s, "XF3  :%08X %f", FP_XS2( 3),(double)FP_XFS2( 3)); break;
3653		case CPUINFO_STR_REGISTER + SH4_XF4:            sprintf(info->s, "XF4  :%08X %f", FP_XS2( 4),(double)FP_XFS2( 4)); break;
3654		case CPUINFO_STR_REGISTER + SH4_XF5:            sprintf(info->s, "XF5  :%08X %f", FP_XS2( 5),(double)FP_XFS2( 5)); break;
3655		case CPUINFO_STR_REGISTER + SH4_XF6:            sprintf(info->s, "XF6  :%08X %f", FP_XS2( 6),(double)FP_XFS2( 6)); break;
3656		case CPUINFO_STR_REGISTER + SH4_XF7:            sprintf(info->s, "XF7  :%08X %f", FP_XS2( 7),(double)FP_XFS2( 7)); break;
3657		case CPUINFO_STR_REGISTER + SH4_XF8:            sprintf(info->s, "XF8  :%08X %f", FP_XS2( 8),(double)FP_XFS2( 8)); break;
3658		case CPUINFO_STR_REGISTER + SH4_XF9:            sprintf(info->s, "XF9  :%08X %f", FP_XS2( 9),(double)FP_XFS2( 9)); break;
3659		case CPUINFO_STR_REGISTER + SH4_XF10:           sprintf(info->s, "XF10 :%08X %f", FP_XS2(10),(double)FP_XFS2(10)); break;
3660		case CPUINFO_STR_REGISTER + SH4_XF11:           sprintf(info->s, "XF11 :%08X %f", FP_XS2(11),(double)FP_XFS2(11)); break;
3661		case CPUINFO_STR_REGISTER + SH4_XF12:           sprintf(info->s, "XF12 :%08X %f", FP_XS2(12),(double)FP_XFS2(12)); break;
3662		case CPUINFO_STR_REGISTER + SH4_XF13:           sprintf(info->s, "XF13 :%08X %f", FP_XS2(13),(double)FP_XFS2(13)); break;
3663		case CPUINFO_STR_REGISTER + SH4_XF14:           sprintf(info->s, "XF14 :%08X %f", FP_XS2(14),(double)FP_XFS2(14)); break;
3664		case CPUINFO_STR_REGISTER + SH4_XF15:           sprintf(info->s, "XF15 :%08X %f", FP_XS2(15),(double)FP_XFS2(15)); break;
3665		#else
3666		case CPUINFO_STR_REGISTER + SH4_FR0:            sprintf(info->s, "FR0  :%08X %f", FP_RS( 0),(double)FP_RFS( 0)); break;
3667		case CPUINFO_STR_REGISTER + SH4_FR1:            sprintf(info->s, "FR1  :%08X %f", FP_RS( 1),(double)FP_RFS( 1)); break;
3668		case CPUINFO_STR_REGISTER + SH4_FR2:            sprintf(info->s, "FR2  :%08X %f", FP_RS( 2),(double)FP_RFS( 2)); break;
3669		case CPUINFO_STR_REGISTER + SH4_FR3:            sprintf(info->s, "FR3  :%08X %f", FP_RS( 3),(double)FP_RFS( 3)); break;
3670		case CPUINFO_STR_REGISTER + SH4_FR4:            sprintf(info->s, "FR4  :%08X %f", FP_RS( 4),(double)FP_RFS( 4)); break;
3671		case CPUINFO_STR_REGISTER + SH4_FR5:            sprintf(info->s, "FR5  :%08X %f", FP_RS( 5),(double)FP_RFS( 5)); break;
3672		case CPUINFO_STR_REGISTER + SH4_FR6:            sprintf(info->s, "FR6  :%08X %f", FP_RS( 6),(double)FP_RFS( 6)); break;
3673		case CPUINFO_STR_REGISTER + SH4_FR7:            sprintf(info->s, "FR7  :%08X %f", FP_RS( 7),(double)FP_RFS( 7)); break;
3674		case CPUINFO_STR_REGISTER + SH4_FR8:            sprintf(info->s, "FR8  :%08X %f", FP_RS( 8),(double)FP_RFS( 8)); break;
3675		case CPUINFO_STR_REGISTER + SH4_FR9:            sprintf(info->s, "FR9  :%08X %f", FP_RS( 9),(double)FP_RFS( 9)); break;
3676		case CPUINFO_STR_REGISTER + SH4_FR10:           sprintf(info->s, "FR10 :%08X %f", FP_RS(10),(double)FP_RFS(10)); break;
3677		case CPUINFO_STR_REGISTER + SH4_FR11:           sprintf(info->s, "FR11 :%08X %f", FP_RS(11),(double)FP_RFS(11)); break;
3678		case CPUINFO_STR_REGISTER + SH4_FR12:           sprintf(info->s, "FR12 :%08X %f", FP_RS(12),(double)FP_RFS(12)); break;
3679		case CPUINFO_STR_REGISTER + SH4_FR13:           sprintf(info->s, "FR13 :%08X %f", FP_RS(13),(double)FP_RFS(13)); break;
3680		case CPUINFO_STR_REGISTER + SH4_FR14:           sprintf(info->s, "FR14 :%08X %f", FP_RS(14),(double)FP_RFS(14)); break;
3681		case CPUINFO_STR_REGISTER + SH4_FR15:           sprintf(info->s, "FR15 :%08X %f", FP_RS(15),(double)FP_RFS(15)); break;
3682		case CPUINFO_STR_REGISTER + SH4_XF0:            sprintf(info->s, "XF0  :%08X %f", FP_XS( 0),(double)FP_XFS( 0)); break;
3683		case CPUINFO_STR_REGISTER + SH4_XF1:            sprintf(info->s, "XF1  :%08X %f", FP_XS( 1),(double)FP_XFS( 1)); break;
3684		case CPUINFO_STR_REGISTER + SH4_XF2:            sprintf(info->s, "XF2  :%08X %f", FP_XS( 2),(double)FP_XFS( 2)); break;
3685		case CPUINFO_STR_REGISTER + SH4_XF3:            sprintf(info->s, "XF3  :%08X %f", FP_XS( 3),(double)FP_XFS( 3)); break;
3686		case CPUINFO_STR_REGISTER + SH4_XF4:            sprintf(info->s, "XF4  :%08X %f", FP_XS( 4),(double)FP_XFS( 4)); break;
3687		case CPUINFO_STR_REGISTER + SH4_XF5:            sprintf(info->s, "XF5  :%08X %f", FP_XS( 5),(double)FP_XFS( 5)); break;
3688		case CPUINFO_STR_REGISTER + SH4_XF6:            sprintf(info->s, "XF6  :%08X %f", FP_XS( 6),(double)FP_XFS( 6)); break;
3689		case CPUINFO_STR_REGISTER + SH4_XF7:            sprintf(info->s, "XF7  :%08X %f", FP_XS( 7),(double)FP_XFS( 7)); break;
3690		case CPUINFO_STR_REGISTER + SH4_XF8:            sprintf(info->s, "XF8  :%08X %f", FP_XS( 8),(double)FP_XFS( 8)); break;
3691		case CPUINFO_STR_REGISTER + SH4_XF9:            sprintf(info->s, "XF9  :%08X %f", FP_XS( 9),(double)FP_XFS( 9)); break;
3692		case CPUINFO_STR_REGISTER + SH4_XF10:           sprintf(info->s, "XF10 :%08X %f", FP_XS(10),(double)FP_XFS(10)); break;
3693		case CPUINFO_STR_REGISTER + SH4_XF11:           sprintf(info->s, "XF11 :%08X %f", FP_XS(11),(double)FP_XFS(11)); break;
3694		case CPUINFO_STR_REGISTER + SH4_XF12:           sprintf(info->s, "XF12 :%08X %f", FP_XS(12),(double)FP_XFS(12)); break;
3695		case CPUINFO_STR_REGISTER + SH4_XF13:           sprintf(info->s, "XF13 :%08X %f", FP_XS(13),(double)FP_XFS(13)); break;
3696		case CPUINFO_STR_REGISTER + SH4_XF14:           sprintf(info->s, "XF14 :%08X %f", FP_XS(14),(double)FP_XFS(14)); break;
3697		case CPUINFO_STR_REGISTER + SH4_XF15:           sprintf(info->s, "XF15 :%08X %f", FP_XS(15),(double)FP_XFS(15)); break; //%01.2e
3698		#endif
3699		}
3700		}
	3732	case SH4_FR15:
	3733	m_fr[15 ^ fpu_xor] = m_debugger_temp;
	3734	break;
3701	3735
3702		CPU_GET_INFO( sh3 )
3703		{
3704		switch (state)
3705		{
3706		/* --- the following bits of info are returned as pointers to data or functions --- */
3707		case CPUINFO_FCT_RESET:                     info->reset = CPU_RESET_NAME(sh3);              break;
	3736	case SH4_XF0:
	3737	m_xf[0 ^ fpu_xor] = m_debugger_temp;
	3738	break;
3708	3739
3709		/* --- the following bits of info are returned as NULL-terminated strings --- */
3710		case CPUINFO_STR_NAME:                      strcpy(info->s, "SH-3 (little)");                break;
3711		case CPUINFO_STR_FAMILY:                    strcpy(info->s, "Hitachi SH7700");      break;
3712		case CPUINFO_STR_SHORTNAME:                 strcpy(info->s, "sh3");                break;
3713		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map64 = ADDRESS_MAP_NAME(sh3_internal_map); break;
	3740	case SH4_XF1:
	3741	m_xf[1 ^ fpu_xor] = m_debugger_temp;
	3742	break;
3714	3743
3715		default:                                    CPU_GET_INFO_CALL(sh4);                 break;
3716		}
3717		}
	3744	case SH4_XF2:
	3745	m_xf[2 ^ fpu_xor] = m_debugger_temp;
	3746	break;
3718	3747
3719		CPU_GET_INFO( sh3be )
3720		{
3721		switch (state)
3722		{
3723		/* --- the following bits of info are returned as pointers to data or functions --- */
3724		case CPUINFO_FCT_RESET:                     info->reset = CPU_RESET_NAME(sh3);              break;
3725		case CPUINFO_FCT_EXECUTE:                   info->execute = CPU_EXECUTE_NAME(sh4be);            break;
3726		case CPUINFO_FCT_DISASSEMBLE:               info->disassemble = CPU_DISASSEMBLE_NAME(sh4be);            break;
	3748	case SH4_XF3:
	3749	m_xf[3 ^ fpu_xor] = m_debugger_temp;
	3750	break;
3727	3751
3728		/* --- the following bits of info are returned as NULL-terminated strings --- */
3729		case CPUINFO_STR_NAME:                      strcpy(info->s, "SH-3 (big)");                break;
3730		case CPUINFO_STR_FAMILY:                    strcpy(info->s, "Hitachi SH7700");      break;
3731		case CPUINFO_STR_SHORTNAME:                 strcpy(info->s, "sh3be");                break;
3732		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map64 = ADDRESS_MAP_NAME(sh3_internal_map); break;
	3752	case SH4_XF4:
	3753	m_xf[4 ^ fpu_xor] = m_debugger_temp;
	3754	break;
3733	3755
3734		case CPUINFO_INT_ENDIANNESS:                info->i = ENDIANNESS_BIG;               break;
	3756	case SH4_XF5:
	3757	m_xf[5 ^ fpu_xor] = m_debugger_temp;
	3758	break;
3735	3759
3736		default:                                    CPU_GET_INFO_CALL(sh4);                 break;
	3760	case SH4_XF6:
	3761	m_xf[6 ^ fpu_xor] = m_debugger_temp;
	3762	break;
	3763
	3764	case SH4_XF7:
	3765	m_xf[7 ^ fpu_xor] = m_debugger_temp;
	3766	break;
	3767
	3768	case SH4_XF8:
	3769	m_xf[8 ^ fpu_xor] = m_debugger_temp;
	3770	break;
	3771
	3772	case SH4_XF9:
	3773	m_xf[9 ^ fpu_xor] = m_debugger_temp;
	3774	break;
	3775
	3776	case SH4_XF10:
	3777	m_xf[10 ^ fpu_xor] = m_debugger_temp;
	3778	break;
	3779
	3780	case SH4_XF11:
	3781	m_xf[11 ^ fpu_xor] = m_debugger_temp;
	3782	break;
	3783
	3784	case SH4_XF12:
	3785	m_xf[12 ^ fpu_xor] = m_debugger_temp;
	3786	break;
	3787
	3788	case SH4_XF13:
	3789	m_xf[13 ^ fpu_xor] = m_debugger_temp;
	3790	break;
	3791
	3792	case SH4_XF14:
	3793	m_xf[14 ^ fpu_xor] = m_debugger_temp;
	3794	break;
	3795
	3796	case SH4_XF15:
	3797	m_xf[15 ^ fpu_xor] = m_debugger_temp;
	3798	break;
3737	3799	}
3738	3800	}
3739	3801
3740		CPU_GET_INFO( sh4be )
	3802	void sh34_base_device::state_export(const device_state_entry &entry)
3741	3803	{
3742		switch (state)
	3804	switch (entry.index())
3743	3805	{
3744		case CPUINFO_STR_NAME:                      strcpy(info->s, "SH-4 (big)");                break;
3745		case CPUINFO_STR_SHORTNAME:                 strcpy(info->s, "sh4be");                break;
3746		case CPUINFO_FCT_EXECUTE:                   info->execute = CPU_EXECUTE_NAME(sh4be);            break;
3747		case CPUINFO_FCT_DISASSEMBLE:               info->disassemble = CPU_DISASSEMBLE_NAME(sh4be);            break;
3748		case CPUINFO_INT_ENDIANNESS:                info->i = ENDIANNESS_BIG;               break;
3749		default:                                    CPU_GET_INFO_CALL(sh4);                 break;
	3806	case STATE_GENPC:
	3807	m_debugger_temp = (m_delay) ? (m_delay & AM) : (m_pc & AM);
	3808	break;
3750	3809	}
3751	3810	}
3752	3811
3753		sh3_device::sh3_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock)
3754		: legacy_cpu_device(mconfig, type, tag, owner, clock, CPU_GET_INFO_NAME(sh3))
	3812	void sh34_base_device::state_string_export(const device_state_entry &entry, astring &string)
3755	3813	{
3756		}
	3814	#ifdef LSB_FIRST
	3815	UINT8 fpu_xor = m_fpu_pr;
	3816	#else
	3817	UINT8 fpu_xor = 0;
	3818	#endif
3757	3819
3758		sh3_device::sh3_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock, cpu_get_info_func info)
3759		: legacy_cpu_device(mconfig, type, tag, owner, clock, info)
3760		{
3761		}
	3820	switch (entry.index())
	3821	{
	3822	case STATE_GENFLAGS:
	3823	string.printf("%s%s%s%s%c%c%d%c%c",
	3824	m_sr & MD ? "MD ":"   ",
	3825	m_sr & sRB ? "RB ":"   ",
	3826	m_sr & BL ? "BL ":"   ",
	3827	m_sr & FD ? "FD ":"   ",
	3828	m_sr & M ? 'M':'.',
	3829	m_sr & Q ? 'Q':'.',
	3830	(m_sr & I) >> 4,
	3831	m_sr & S ? 'S':'.',
	3832	m_sr & T ? 'T':'.');
	3833	break;
3762	3834
3763		const device_type SH3LE = &legacy_device_creator<sh3_device>;
	3835	case SH4_FR0:
	3836	string.printf("%08X %f", m_fr[0 ^ fpu_xor], (double)FP_RFS(0 ^ fpu_xor));
	3837	break;
3764	3838
3765		sh3be_device::sh3be_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock)
3766		: sh3_device(mconfig, type, tag, owner, clock, CPU_GET_INFO_NAME(sh3be))
3767		{
3768		}
	3839	case SH4_FR1:
	3840	string.printf("%08X %f", m_fr[1 ^ fpu_xor], (double)FP_RFS(1 ^ fpu_xor));
	3841	break;
3769	3842
3770		const device_type SH3BE = &legacy_device_creator<sh3be_device>;
	3843	case SH4_FR2:
	3844	string.printf("%08X %f", m_fr[2 ^ fpu_xor], (double)FP_RFS(2 ^ fpu_xor));
	3845	break;
3771	3846
3772		sh4_device::sh4_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock)
3773		: legacy_cpu_device(mconfig, type, tag, owner, clock, CPU_GET_INFO_NAME(sh4))
3774		{
3775		}
	3847	case SH4_FR3:
	3848	string.printf("%08X %f", m_fr[3 ^ fpu_xor], (double)FP_RFS(3 ^ fpu_xor));
	3849	break;
3776	3850
3777		sh4_device::sh4_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock, cpu_get_info_func info)
3778		: legacy_cpu_device(mconfig, type, tag, owner, clock, info)
3779		{
	3851	case SH4_FR4:
	3852	string.printf("%08X %f", m_fr[4 ^ fpu_xor], (double)FP_RFS(4 ^ fpu_xor));
	3853	break;
	3854
	3855	case SH4_FR5:
	3856	string.printf("%08X %f", m_fr[5 ^ fpu_xor], (double)FP_RFS(5 ^ fpu_xor));
	3857	break;
	3858
	3859	case SH4_FR6:
	3860	string.printf("%08X %f", m_fr[6 ^ fpu_xor], (double)FP_RFS(6 ^ fpu_xor));
	3861	break;
	3862
	3863	case SH4_FR7:
	3864	string.printf("%08X %f", m_fr[7 ^ fpu_xor], (double)FP_RFS(7 ^ fpu_xor));
	3865	break;
	3866
	3867	case SH4_FR8:
	3868	string.printf("%08X %f", m_fr[8 ^ fpu_xor], (double)FP_RFS(8 ^ fpu_xor));
	3869	break;
	3870
	3871	case SH4_FR9:
	3872	string.printf("%08X %f", m_fr[9 ^ fpu_xor], (double)FP_RFS(9 ^ fpu_xor));
	3873	break;
	3874
	3875	case SH4_FR10:
	3876	string.printf("%08X %f", m_fr[10 ^ fpu_xor], (double)FP_RFS(10 ^ fpu_xor));
	3877	break;
	3878
	3879	case SH4_FR11:
	3880	string.printf("%08X %f", m_fr[11 ^ fpu_xor], (double)FP_RFS(11 ^ fpu_xor));
	3881	break;
	3882
	3883	case SH4_FR12:
	3884	string.printf("%08X %f", m_fr[12 ^ fpu_xor], (double)FP_RFS(12 ^ fpu_xor));
	3885	break;
	3886
	3887	case SH4_FR13:
	3888	string.printf("%08X %f", m_fr[13 ^ fpu_xor], (double)FP_RFS(13 ^ fpu_xor));
	3889	break;
	3890
	3891	case SH4_FR14:
	3892	string.printf("%08X %f", m_fr[14 ^ fpu_xor], (double)FP_RFS(14 ^ fpu_xor));
	3893	break;
	3894
	3895	case SH4_FR15:
	3896	string.printf("%08X %f", m_fr[15 ^ fpu_xor], (double)FP_RFS(15 ^ fpu_xor));
	3897	break;
	3898
	3899	case SH4_XF0:
	3900	string.printf("%08X %f", m_xf[0 ^ fpu_xor], (double)FP_XFS(0 ^ fpu_xor));
	3901	break;
	3902
	3903	case SH4_XF1:
	3904	string.printf("%08X %f", m_xf[1 ^ fpu_xor], (double)FP_XFS(1 ^ fpu_xor));
	3905	break;
	3906
	3907	case SH4_XF2:
	3908	string.printf("%08X %f", m_xf[2 ^ fpu_xor], (double)FP_XFS(2 ^ fpu_xor));
	3909	break;
	3910
	3911	case SH4_XF3:
	3912	string.printf("%08X %f", m_xf[3 ^ fpu_xor], (double)FP_XFS(3 ^ fpu_xor));
	3913	break;
	3914
	3915	case SH4_XF4:
	3916	string.printf("%08X %f", m_xf[4 ^ fpu_xor], (double)FP_XFS(4 ^ fpu_xor));
	3917	break;
	3918
	3919	case SH4_XF5:
	3920	string.printf("%08X %f", m_xf[5 ^ fpu_xor], (double)FP_XFS(5 ^ fpu_xor));
	3921	break;
	3922
	3923	case SH4_XF6:
	3924	string.printf("%08X %f", m_xf[6 ^ fpu_xor], (double)FP_XFS(6 ^ fpu_xor));
	3925	break;
	3926
	3927	case SH4_XF7:
	3928	string.printf("%08X %f", m_xf[7 ^ fpu_xor], (double)FP_XFS(7 ^ fpu_xor));
	3929	break;
	3930
	3931	case SH4_XF8:
	3932	string.printf("%08X %f", m_xf[8 ^ fpu_xor], (double)FP_XFS(8 ^ fpu_xor));
	3933	break;
	3934
	3935	case SH4_XF9:
	3936	string.printf("%08X %f", m_xf[9 ^ fpu_xor], (double)FP_XFS(9 ^ fpu_xor));
	3937	break;
	3938
	3939	case SH4_XF10:
	3940	string.printf("%08X %f", m_xf[10 ^ fpu_xor], (double)FP_XFS(10 ^ fpu_xor));
	3941	break;
	3942
	3943	case SH4_XF11:
	3944	string.printf("%08X %f", m_xf[11 ^ fpu_xor], (double)FP_XFS(11 ^ fpu_xor));
	3945	break;
	3946
	3947	case SH4_XF12:
	3948	string.printf("%08X %f", m_xf[12 ^ fpu_xor], (double)FP_XFS(12 ^ fpu_xor));
	3949	break;
	3950
	3951	case SH4_XF13:
	3952	string.printf("%08X %f", m_xf[13 ^ fpu_xor], (double)FP_XFS(13 ^ fpu_xor));
	3953	break;
	3954
	3955	case SH4_XF14:
	3956	string.printf("%08X %f", m_xf[14 ^ fpu_xor], (double)FP_XFS(14 ^ fpu_xor));
	3957	break;
	3958
	3959	case SH4_XF15:
	3960	string.printf("%08X %f", m_xf[15 ^ fpu_xor], (double)FP_XFS(15 ^ fpu_xor));
	3961	break;
	3962
	3963	}
3780	3964	}
3781	3965
3782		const device_type SH4LE = &legacy_device_creator<sh4_device>;
3783	3966
3784		sh4be_device::sh4be_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock)
3785		: sh4_device(mconfig, type, tag, owner, clock, CPU_GET_INFO_NAME(sh4be))
	3967	void sh34_base_device::sh4_set_ftcsr_callback(sh4_ftcsr_callback callback)
3786	3968	{
	3969	m_ftcsr_read_callback = callback;
3787	3970	}
3788	3971
3789		const device_type SH4BE = &legacy_device_creator<sh4be_device>;
3790
3791		#endif  // USE_SH4DRC

trunk/src/emu/cpu/sh4/sh4comn.h

r31221	r31222
35	35	#define NMIPRI()            EXPPRI(3,0,16,SH4_INTC_NMI)
36	36	#define INTPRI(p,n)         EXPPRI(4,2,p,n)
37	37
38		#define FP_RS(r) sh4->fr[(r)] // binary representation of single precision floating point register r
39		#define FP_RFS(r) *( (float  *)(sh4->fr+(r)) ) // single precision floating point register r
40		#define FP_RFD(r) *( (double *)(sh4->fr+(r)) ) // double precision floating point register r
41		#define FP_XS(r) sh4->xf[(r)] // binary representation of extended single precision floating point register r
42		#define FP_XFS(r) *( (float  *)(sh4->xf+(r)) ) // single precision extended floating point register r
43		#define FP_XFD(r) *( (double *)(sh4->xf+(r)) ) // double precision extended floating point register r
	38	#define FP_RS(r) m_fr[(r)] // binary representation of single precision floating point register r
	39	#define FP_RFS(r) *( (float  *)(m_fr+(r)) ) // single precision floating point register r
	40	#define FP_RFD(r) *( (double *)(m_fr+(r)) ) // double precision floating point register r
	41	#define FP_XS(r) m_xf[(r)] // binary representation of extended single precision floating point register r
	42	#define FP_XFS(r) *( (float  *)(m_xf+(r)) ) // single precision extended floating point register r
	43	#define FP_XFD(r) *( (double *)(m_xf+(r)) ) // double precision extended floating point register r
44	44	#ifdef LSB_FIRST
45		#define FP_RS2(r) sh4->fr[(r) ^ sh4->fpu_pr]
46		#define FP_RFS2(r) *( (float  *)(sh4->fr+((r) ^ sh4->fpu_pr)) )
47		#define FP_XS2(r) sh4->xf[(r) ^ sh4->fpu_pr]
48		#define FP_XFS2(r) *( (float  *)(sh4->xf+((r) ^ sh4->fpu_pr)) )
	45	#define FP_RS2(r) m_fr[(r) ^ m_fpu_pr]
	46	#define FP_RFS2(r) *( (float  *)(m_fr+((r) ^ m_fpu_pr)) )
	47	#define FP_XS2(r) m_xf[(r) ^ m_fpu_pr]
	48	#define FP_XFS2(r) *( (float  *)(m_xf+((r) ^ m_fpu_pr)) )
49	49	#endif
50	50
51	51
	52	#ifdef USE_SH4DRC
52	53	struct sh4_state
53	54	{
54		UINT32  ppc;
55		UINT32  pc, spc;
56		UINT32  pr;
57		UINT32  sr, ssr;
58		UINT32  gbr, vbr;
59		UINT32  mach, macl;
60		UINT32  r[16], rbnk[2][8], sgr;
61		UINT32  fr[16], xf[16];
62		UINT32  ea;
63		UINT32  delay;
64		UINT32  cpu_off;
65		UINT32  pending_irq;
66		UINT32  test_irq;
67		UINT32  fpscr;
68		UINT32  fpul;
69		UINT32  dbr;
70
71		UINT32  exception_priority[128];
72		int     exception_requesting[128];
73
74		INT8    irq_line_state[17];
75		device_irq_acknowledge_delegate irq_callback;
76		legacy_cpu_device *device;
77		address_space *internal;
78		address_space *program;
79		direct_read_data *direct;
80		address_space *io;
81
82		// sh4 internal
83		UINT32 m[16384];
84
85		// timer regs handled manually for reuse
86		UINT32 SH4_TSTR;
87		UINT32 SH4_TCNT0;
88		UINT32 SH4_TCNT1;
89		UINT32 SH4_TCNT2;
90		UINT32 SH4_TCR0;
91		UINT32 SH4_TCR1;
92		UINT32 SH4_TCR2;
93		UINT32 SH4_TCOR0;
94		UINT32 SH4_TCOR1;
95		UINT32 SH4_TCOR2;
96		UINT32 SH4_TOCR;
97		UINT32 SH4_TCPR2;
98
99		// INTC regs
100		UINT32 SH4_IPRA;
101
102		UINT32 SH4_IPRC;
103
104		// DMAC regs
105		UINT32 SH4_SAR0;
106		UINT32 SH4_SAR1;
107		UINT32 SH4_SAR2;
108		UINT32 SH4_SAR3;
109
110		UINT32 SH4_DAR0;
111		UINT32 SH4_DAR1;
112		UINT32 SH4_DAR2;
113		UINT32 SH4_DAR3;
114
115		UINT32 SH4_CHCR0;
116		UINT32 SH4_CHCR1;
117		UINT32 SH4_CHCR2;
118		UINT32 SH4_CHCR3;
119
120		UINT32 SH4_DMATCR0;
121		UINT32 SH4_DMATCR1;
122		UINT32 SH4_DMATCR2;
123		UINT32 SH4_DMATCR3;
124
125		UINT32 SH4_DMAOR;
126
127
128		INT8    nmi_line_state;
129
130		UINT8 sleep_mode;
131
132		int     frt_input;
133		int     irln;
134		int     internal_irq_level;
135		int     internal_irq_vector;
136
137		emu_timer *dma_timer[4];
138		emu_timer *refresh_timer;
139		emu_timer *rtc_timer;
140		emu_timer *timer[3];
141		UINT32  refresh_timer_base;
142		int     dma_timer_active[4];
143		UINT32  dma_source[4];
144		UINT32  dma_destination[4];
145		UINT32  dma_count[4];
146		int     dma_wordsize[4];
147		int     dma_source_increment[4];
148		int     dma_destination_increment[4];
149		int     dma_mode[4];
150
151		int     sh4_icount;
152		int     is_slave;
153		int     cpu_clock, bus_clock, pm_clock;
154		int     fpu_sz, fpu_pr;
155		int     ioport16_pullup, ioport16_direction;
156		int     ioport4_pullup, ioport4_direction;
157
158		void    (*ftcsr_read_callback)(UINT32 data);
159
160
161		/* This MMU simulation is good for the simple remap used on Naomi GD-ROM SQ access *ONLY* */
162		UINT32 sh4_tlb_address[64];
163		UINT32 sh4_tlb_data[64];
164		UINT8 sh4_mmu_enabled;
165
166		int cpu_type;
167
168		// sh3 internal
169		UINT32  m_sh3internal_upper[0x3000/4];
170		UINT32  m_sh3internal_lower[0x1000];
171
172		#ifdef USE_SH4DRC
173	55	int icount;
174	56
175	57	int pcfsel;                 // last pcflush entry set
r31221	r31222
207	89
208	90	UINT32 prefadr;
209	91	UINT32 target;
210		#endif
211	92	};
	93	#endif
212	94
213	95	#ifdef USE_SH4DRC
214	96	class sh4_frontend : public drc_frontend
r31221	r31222
231	113
232	114	sh4_state &m_context;
233	115	};
234
235		INLINE sh4_state *get_safe_token(device_t *device)
236		{
237		assert(device != NULL);
238		assert(device->type() == SH3LE || device->type() == SH3BE ||
239		device->type() == SH4LE || device->type() == SH4BE );
240		return *(sh4_state **)downcast<legacy_cpu_device *>(device)->token();
241		}
242		#else
243		INLINE sh4_state *get_safe_token(device_t *device)
244		{
245		assert(device != NULL);
246		assert(device->type() == SH3LE || device->type() == SH3BE ||
247		device->type() == SH4LE || device->type() == SH4BE );
248		return (sh4_state *)downcast<legacy_cpu_device *>(device)->token();
249		}
250	116	#endif
251	117
252	118
r31221	r31222
302	168	#define REGFLAG_SSR                     (1 << 10)
303	169	#define REGFLAG_SPC                     (1 << 11)
304	170
305		void sh4_exception_recompute(sh4_state *sh4); // checks if there is any interrupt with high enough priority
306		void sh4_exception_request(sh4_state *sh4, int exception); // start requesting an exception
307		void sh4_exception_unrequest(sh4_state *sh4, int exception); // stop requesting an exception
308		void sh4_exception_checkunrequest(sh4_state *sh4, int exception);
309		void sh4_exception(sh4_state *sh4, const char *message, int exception); // handle exception
310		void sh4_change_register_bank(sh4_state *sh4, int to);
311		void sh4_syncronize_register_bank(sh4_state *sh4, int to);
312		void sh4_swap_fp_registers(sh4_state *sh4);
313		void sh4_default_exception_priorities(sh4_state *sh4); // setup default priorities for exceptions
314		void sh4_parse_configuration(sh4_state *sh4, const struct sh4_config *conf);
315		void sh4_set_irq_line(sh4_state *sh4, int irqline, int state); // set state of external interrupt line
316		#ifdef LSB_FIRST
317		void sh4_swap_fp_couples(sh4_state *sh4);
318		#endif
319		void sh4_common_init(device_t *device);
320		UINT32 sh4_getsqremap(sh4_state *sh4, UINT32 address);
321		void sh4_handler_ipra_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
322	171
323		INLINE void sh4_check_pending_irq(sh4_state *sh4, const char *message) // look for highest priority active exception and handle it
324		{
325		int a,irq,z;
326
327		irq = 0;
328		z = -1;
329		for (a=0;a <= SH4_INTC_ROVI;a++)
330		{
331		if (sh4->exception_requesting[a])
332		{
333		if ((int)sh4->exception_priority[a] > z)
334		{
335		z = sh4->exception_priority[a];
336		irq = a;
337		}
338		}
339		}
340		if (z >= 0)
341		{
342		sh4_exception(sh4, message, irq);
343		}
344		}
345
346	172	#endif /* __SH4COMN_H__ */

trunk/src/emu/cpu/sh4/sh4.h

r31221	r31222
111	111	SH4_IOPORT_SCIF=8*4
112	112	};
113	113
114		struct sh4_config
115		{
116		int md2;
117		int md1;
118		int md0;
119		int md6;
120		int md4;
121		int md3;
122		int md5;
123		int md7;
124		int md8;
125		int clock;
126		};
127
128	114	struct sh4_device_dma
129	115	{
130	116	UINT32 length;
r31221	r31222
147	133
148	134	typedef void (*sh4_ftcsr_callback)(UINT32);
149	135
150		CPU_GET_INFO( sh3 );
151	136
152		class sh3_device : public legacy_cpu_device
	137	#define MCFG_SH4_MD0(_md0) \
	138	sh34_base_device::set_md0(*device, _md0);
	139
	140	#define MCFG_SH4_MD1(_md1) \
	141	sh34_base_device::set_md1(*device, _md1);
	142
	143	#define MCFG_SH4_MD2(_md2) \
	144	sh34_base_device::set_md2(*device, _md2);
	145
	146	#define MCFG_SH4_MD3(_md3) \
	147	sh34_base_device::set_md3(*device, _md3);
	148
	149	#define MCFG_SH4_MD4(_md4) \
	150	sh34_base_device::set_md4(*device, _md4);
	151
	152	#define MCFG_SH4_MD5(_md5) \
	153	sh34_base_device::set_md5(*device, _md5);
	154
	155	#define MCFG_SH4_MD6(_md6) \
	156	sh34_base_device::set_md6(*device, _md6);
	157
	158	#define MCFG_SH4_MD7(_md7) \
	159	sh34_base_device::set_md7(*device, _md7);
	160
	161	#define MCFG_SH4_MD8(_md8) \
	162	sh34_base_device::set_md8(*device, _md8);
	163
	164	#define MCFG_SH4_CLOCK(_clock) \
	165	sh34_base_device::set_sh4_clock(*device, _clock);
	166
	167
	168	class sh34_base_device : public cpu_device
153	169	{
154	170	public:
155		sh3_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock);
156		sh3_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock, cpu_get_info_func info);
	171	// construction/destruction
	172	sh34_base_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, endianness_t endianness, address_map_constructor internal);
157	173
	174	static void set_md0(device_t &device, int md0) { downcast<sh34_base_device &>(device).c_md0 = md0; }
	175	static void set_md1(device_t &device, int md0) { downcast<sh34_base_device &>(device).c_md1 = md0; }
	176	static void set_md2(device_t &device, int md0) { downcast<sh34_base_device &>(device).c_md2 = md0; }
	177	static void set_md3(device_t &device, int md0) { downcast<sh34_base_device &>(device).c_md3 = md0; }
	178	static void set_md4(device_t &device, int md0) { downcast<sh34_base_device &>(device).c_md4 = md0; }
	179	static void set_md5(device_t &device, int md0) { downcast<sh34_base_device &>(device).c_md5 = md0; }
	180	static void set_md6(device_t &device, int md0) { downcast<sh34_base_device &>(device).c_md6 = md0; }
	181	static void set_md7(device_t &device, int md0) { downcast<sh34_base_device &>(device).c_md7 = md0; }
	182	static void set_md8(device_t &device, int md0) { downcast<sh34_base_device &>(device).c_md8 = md0; }
	183	static void set_sh4_clock(device_t &device, int clock) { downcast<sh34_base_device &>(device).c_clock = clock; }
	184
	185	TIMER_CALLBACK_MEMBER( sh4_refresh_timer_callback );
	186	TIMER_CALLBACK_MEMBER( sh4_rtc_timer_callback );
	187	TIMER_CALLBACK_MEMBER( sh4_timer_callback );
	188	TIMER_CALLBACK_MEMBER( sh4_dmac_callback );
	189
	190	void sh4_set_frt_input(int state);
	191	void sh4_set_irln_input(int value);
	192	void sh4_set_ftcsr_callback(sh4_ftcsr_callback callback);
	193	int sh4_dma_data(struct sh4_device_dma *s);
	194	void sh4_dma_ddt(struct sh4_ddt_dma *s);
	195
	196	protected:
	197	// device-level overrides
	198	virtual void device_start();
	199	virtual void device_reset();
	200
	201	// device_execute_interface overrides
	202	virtual UINT32 execute_min_cycles() const { return 1; }
	203	virtual UINT32 execute_max_cycles() const { return 4; }
	204	virtual UINT32 execute_input_lines() const { return 5; }
	205	virtual void execute_run();
	206	virtual void execute_set_input(int inputnum, int state);
	207
	208	// device_memory_interface overrides
	209	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ((spacenum == AS_IO) ? &m_io_config : NULL); }
	210
	211	// device_state_interface overrides
	212	virtual void state_import(const device_state_entry &entry);
	213	virtual void state_export(const device_state_entry &entry);
	214	virtual void state_string_export(const device_state_entry &entry, astring &string);
	215
	216	// device_disasm_interface overrides
	217	virtual UINT32 disasm_min_opcode_bytes() const { return 2; }
	218	virtual UINT32 disasm_max_opcode_bytes() const { return 2; }
	219	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
	220
	221	protected:
	222	address_space_config m_program_config;
	223	address_space_config m_io_config;
	224
	225	int c_md2;
	226	int c_md1;
	227	int c_md0;
	228	int c_md6;
	229	int c_md4;
	230	int c_md3;
	231	int c_md5;
	232	int c_md7;
	233	int c_md8;
	234	int c_clock;
	235
	236	UINT32  m_ppc;
	237	UINT32  m_pc;
	238	UINT32  m_spc;
	239	UINT32  m_pr;
	240	UINT32  m_sr;
	241	UINT32  m_ssr;
	242	UINT32  m_gbr;
	243	UINT32  m_vbr;
	244	UINT32  m_mach;
	245	UINT32  m_macl;
	246	UINT32  m_r[16];
	247	UINT32  m_rbnk[2][8];
	248	UINT32  m_sgr;
	249	UINT32  m_fr[16];
	250	UINT32  m_xf[16];
	251	UINT32  m_ea;
	252	UINT32  m_delay;
	253	UINT32  m_cpu_off;
	254	UINT32  m_pending_irq;
	255	UINT32  m_test_irq;
	256	UINT32  m_fpscr;
	257	UINT32  m_fpul;
	258	UINT32  m_dbr;
	259
	260	UINT32  m_exception_priority[128];
	261	int     m_exception_requesting[128];
	262
	263	INT8    m_irq_line_state[17];
	264	address_space *m_internal;
	265	address_space *m_program;
	266	direct_read_data *m_direct;
	267	address_space *m_io;
	268
	269	// sh4 internal
	270	UINT32 m_m[16384];
	271
	272	// timer regs handled manually for reuse
	273	UINT32 m_SH4_TSTR;
	274	UINT32 m_SH4_TCNT0;
	275	UINT32 m_SH4_TCNT1;
	276	UINT32 m_SH4_TCNT2;
	277	UINT32 m_SH4_TCR0;
	278	UINT32 m_SH4_TCR1;
	279	UINT32 m_SH4_TCR2;
	280	UINT32 m_SH4_TCOR0;
	281	UINT32 m_SH4_TCOR1;
	282	UINT32 m_SH4_TCOR2;
	283	UINT32 m_SH4_TOCR;
	284	UINT32 m_SH4_TCPR2;
	285
	286	// INTC regs
	287	UINT32 m_SH4_IPRA;
	288
	289	UINT32 m_SH4_IPRC;
	290
	291	// DMAC regs
	292	UINT32 m_SH4_SAR0;
	293	UINT32 m_SH4_SAR1;
	294	UINT32 m_SH4_SAR2;
	295	UINT32 m_SH4_SAR3;
	296
	297	UINT32 m_SH4_DAR0;
	298	UINT32 m_SH4_DAR1;
	299	UINT32 m_SH4_DAR2;
	300	UINT32 m_SH4_DAR3;
	301
	302	UINT32 m_SH4_CHCR0;
	303	UINT32 m_SH4_CHCR1;
	304	UINT32 m_SH4_CHCR2;
	305	UINT32 m_SH4_CHCR3;
	306
	307	UINT32 m_SH4_DMATCR0;
	308	UINT32 m_SH4_DMATCR1;
	309	UINT32 m_SH4_DMATCR2;
	310	UINT32 m_SH4_DMATCR3;
	311
	312	UINT32 m_SH4_DMAOR;
	313
	314	INT8    m_nmi_line_state;
	315
	316	UINT8 m_sleep_mode;
	317
	318	int     m_frt_input;
	319	int     m_irln;
	320	int     m_internal_irq_level;
	321	int     m_internal_irq_vector;
	322
	323	emu_timer *m_dma_timer[4];
	324	emu_timer *m_refresh_timer;
	325	emu_timer *m_rtc_timer;
	326	emu_timer *m_timer[3];
	327	UINT32  m_refresh_timer_base;
	328	int     m_dma_timer_active[4];
	329	UINT32  m_dma_source[4];
	330	UINT32  m_dma_destination[4];
	331	UINT32  m_dma_count[4];
	332	int     m_dma_wordsize[4];
	333	int     m_dma_source_increment[4];
	334	int     m_dma_destination_increment[4];
	335	int     m_dma_mode[4];
	336
	337	int     m_sh4_icount;
	338	int     m_is_slave;
	339	int     m_cpu_clock;
	340	int     m_bus_clock;
	341	int     m_pm_clock;
	342	int     m_fpu_sz;
	343	int     m_fpu_pr;
	344	int     m_ioport16_pullup;
	345	int     m_ioport16_direction;
	346	int     m_ioport4_pullup;
	347	int     m_ioport4_direction;
	348
	349	void    (*m_ftcsr_read_callback)(UINT32 data);
	350
	351	/* This MMU simulation is good for the simple remap used on Naomi GD-ROM SQ access *ONLY* */
	352	UINT32 m_sh4_tlb_address[64];
	353	UINT32 m_sh4_tlb_data[64];
	354	UINT8 m_sh4_mmu_enabled;
	355
	356	int m_cpu_type;
	357
	358	// sh3 internal
	359	UINT32  m_sh3internal_upper[0x3000/4];
	360	UINT32  m_sh3internal_lower[0x1000];
	361
	362	UINT64 m_debugger_temp;
	363
	364
	365	typedef void (sh34_base_device::*sh4ophandler)(const UINT16);
	366
	367	static sh4ophandler s_master_ophandler_table[0x10000];
	368	static const sh4ophandler s_op1111_0x13_handlers[16];
	369	static const sh4ophandler s_op1000_handler[16];
	370	static const sh4ophandler s_op1100_handler[16];
	371	static const sh4ophandler s_op0000_handlers[256];
	372	static const sh4ophandler s_op0100_handlers[256];
	373	static const sh4ophandler s_upper4bits[256];
	374
	375
	376	inline void sh4_check_pending_irq(const char *message) // look for highest priority active exception and handle it
	377	{
	378	int a,irq,z;
	379
	380	irq = 0;
	381	z = -1;
	382	for (a=0;a <= SH4_INTC_ROVI;a++)
	383	{
	384	if (m_exception_requesting[a])
	385	{
	386	if ((int)m_exception_priority[a] > z)
	387	{
	388	z = m_exception_priority[a];
	389	irq = a;
	390	}
	391	}
	392	}
	393	if (z >= 0)
	394	{
	395	sh4_exception(message, irq);
	396	}
	397	}
	398
	399	void TODO(const UINT16 opcode);
	400	void WB(offs_t A, UINT8 V);
	401	void WW(offs_t A, UINT16 V);
	402	void WL(offs_t A, UINT32 V);
	403	void ADD(const UINT16 opcode);
	404	void ADDI(const UINT16 opcode);
	405	void ADDC(const UINT16 opcode);
	406	void ADDV(const UINT16 opcode);
	407	void AND(const UINT16 opcode);
	408	void ANDI(const UINT16 opcode);
	409	void ANDM(const UINT16 opcode);
	410	void BF(const UINT16 opcode);
	411	void BFS(const UINT16 opcode);
	412	void BRA(const UINT16 opcode);
	413	void BRAF(const UINT16 opcode);
	414	void BSR(const UINT16 opcode);
	415	void BSRF(const UINT16 opcode);
	416	void BT(const UINT16 opcode);
	417	void BTS(const UINT16 opcode);
	418	void CLRMAC(const UINT16 opcode);
	419	void CLRT(const UINT16 opcode);
	420	void CMPEQ(const UINT16 opcode);
	421	void CMPGE(const UINT16 opcode);
	422	void CMPGT(const UINT16 opcode);
	423	void CMPHI(const UINT16 opcode);
	424	void CMPHS(const UINT16 opcode);
	425	void CMPPL(const UINT16 opcode);
	426	void CMPPZ(const UINT16 opcode);
	427	void CMPSTR(const UINT16 opcode);
	428	void CMPIM(const UINT16 opcode);
	429	void DIV0S(const UINT16 opcode);
	430	void DIV0U(const UINT16 opcode);
	431	void DIV1(const UINT16 opcode);
	432	void DMULS(const UINT16 opcode);
	433	void DMULU(const UINT16 opcode);
	434	void DT(const UINT16 opcode);
	435	void EXTSB(const UINT16 opcode);
	436	void EXTSW(const UINT16 opcode);
	437	void EXTUB(const UINT16 opcode);
	438	void EXTUW(const UINT16 opcode);
	439	void JMP(const UINT16 opcode);
	440	void JSR(const UINT16 opcode);
	441	void LDCSR(const UINT16 opcode);
	442	void LDCGBR(const UINT16 opcode);
	443	void LDCVBR(const UINT16 opcode);
	444	void LDCMSR(const UINT16 opcode);
	445	void LDCMGBR(const UINT16 opcode);
	446	void LDCMVBR(const UINT16 opcode);
	447	void LDSMACH(const UINT16 opcode);
	448	void LDSMACL(const UINT16 opcode);
	449	void LDSPR(const UINT16 opcode);
	450	void LDSMMACH(const UINT16 opcode);
	451	void LDSMMACL(const UINT16 opcode);
	452	void LDSMPR(const UINT16 opcode);
	453	void MAC_L(const UINT16 opcode);
	454	void MAC_W(const UINT16 opcode);
	455	void MOV(const UINT16 opcode);
	456	void MOVBS(const UINT16 opcode);
	457	void MOVWS(const UINT16 opcode);
	458	void MOVLS(const UINT16 opcode);
	459	void MOVBL(const UINT16 opcode);
	460	void MOVWL(const UINT16 opcode);
	461	void MOVLL(const UINT16 opcode);
	462	void MOVBM(const UINT16 opcode);
	463	void MOVWM(const UINT16 opcode);
	464	void MOVLM(const UINT16 opcode);
	465	void MOVBP(const UINT16 opcode);
	466	void MOVWP(const UINT16 opcode);
	467	void MOVLP(const UINT16 opcode);
	468	void MOVBS0(const UINT16 opcode);
	469	void MOVWS0(const UINT16 opcode);
	470	void MOVLS0(const UINT16 opcode);
	471	void MOVBL0(const UINT16 opcode);
	472	void MOVWL0(const UINT16 opcode);
	473	void MOVLL0(const UINT16 opcode);
	474	void MOVI(const UINT16 opcode);
	475	void MOVWI(const UINT16 opcode);
	476	void MOVLI(const UINT16 opcode);
	477	void MOVBLG(const UINT16 opcode);
	478	void MOVWLG(const UINT16 opcode);
	479	void MOVLLG(const UINT16 opcode);
	480	void MOVBSG(const UINT16 opcode);
	481	void MOVWSG(const UINT16 opcode);
	482	void MOVLSG(const UINT16 opcode);
	483	void MOVBS4(const UINT16 opcode);
	484	void MOVWS4(const UINT16 opcode);
	485	void MOVLS4(const UINT16 opcode);
	486	void MOVBL4(const UINT16 opcode);
	487	void MOVWL4(const UINT16 opcode);
	488	void MOVLL4(const UINT16 opcode);
	489	void MOVA(const UINT16 opcode);
	490	void MOVT(const UINT16 opcode);
	491	void MULL(const UINT16 opcode);
	492	void MULS(const UINT16 opcode);
	493	void MULU(const UINT16 opcode);
	494	void NEG(const UINT16 opcode);
	495	void NEGC(const UINT16 opcode);
	496	void NOP(const UINT16 opcode);
	497	void NOT(const UINT16 opcode);
	498	void OR(const UINT16 opcode);
	499	void ORI(const UINT16 opcode);
	500	void ORM(const UINT16 opcode);
	501	void ROTCL(const UINT16 opcode);
	502	void ROTCR(const UINT16 opcode);
	503	void ROTL(const UINT16 opcode);
	504	void ROTR(const UINT16 opcode);
	505	void RTE(const UINT16 opcode);
	506	void RTS(const UINT16 opcode);
	507	void SETT(const UINT16 opcode);
	508	void SHAL(const UINT16 opcode);
	509	void SHAR(const UINT16 opcode);
	510	void SHLL(const UINT16 opcode);
	511	void SHLL2(const UINT16 opcode);
	512	void SHLL8(const UINT16 opcode);
	513	void SHLL16(const UINT16 opcode);
	514	void SHLR(const UINT16 opcode);
	515	void SHLR2(const UINT16 opcode);
	516	void SHLR8(const UINT16 opcode);
	517	void SHLR16(const UINT16 opcode);
	518	void SLEEP(const UINT16 opcode);
	519	void STCSR(const UINT16 opcode);
	520	void STCGBR(const UINT16 opcode);
	521	void STCVBR(const UINT16 opcode);
	522	void STCMSR(const UINT16 opcode);
	523	void STCMGBR(const UINT16 opcode);
	524	void STCMVBR(const UINT16 opcode);
	525	void STSMACH(const UINT16 opcode);
	526	void STSMACL(const UINT16 opcode);
	527	void STSPR(const UINT16 opcode);
	528	void STSMMACH(const UINT16 opcode);
	529	void STSMMACL(const UINT16 opcode);
	530	void STSMPR(const UINT16 opcode);
	531	void SUB(const UINT16 opcode);
	532	void SUBC(const UINT16 opcode);
	533	void SUBV(const UINT16 opcode);
	534	void SWAPB(const UINT16 opcode);
	535	void SWAPW(const UINT16 opcode);
	536	void TAS(const UINT16 opcode);
	537	void TRAPA(const UINT16 opcode);
	538	void TST(const UINT16 opcode);
	539	void TSTI(const UINT16 opcode);
	540	void TSTM(const UINT16 opcode);
	541	void XOR(const UINT16 opcode);
	542	void XORI(const UINT16 opcode);
	543	void XORM(const UINT16 opcode);
	544	void XTRCT(const UINT16 opcode);
	545	void STCSSR(const UINT16 opcode);
	546	void STCSPC(const UINT16 opcode);
	547	void STCSGR(const UINT16 opcode);
	548	void STSFPUL(const UINT16 opcode);
	549	void STSFPSCR(const UINT16 opcode);
	550	void STCDBR(const UINT16 opcode);
	551	void STCRBANK(const UINT16 opcode);
	552	void STCMRBANK(const UINT16 opcode);
	553	void MOVCAL(const UINT16 opcode);
	554	void CLRS(const UINT16 opcode);
	555	void SETS(const UINT16 opcode);
	556	void STCMSGR(const UINT16 opcode);
	557	void STSMFPUL(const UINT16 opcode);
	558	void STSMFPSCR(const UINT16 opcode);
	559	void STCMDBR(const UINT16 opcode);
	560	void STCMSSR(const UINT16 opcode);
	561	void STCMSPC(const UINT16 opcode);
	562	void LDSMFPUL(const UINT16 opcode);
	563	void LDSMFPSCR(const UINT16 opcode);
	564	void LDCMDBR(const UINT16 opcode);
	565	void LDCMRBANK(const UINT16 opcode);
	566	void LDCMSSR(const UINT16 opcode);
	567	void LDCMSPC(const UINT16 opcode);
	568	void LDSFPUL(const UINT16 opcode);
	569	void LDSFPSCR(const UINT16 opcode);
	570	void LDCDBR(const UINT16 opcode);
	571	void SHAD(const UINT16 opcode);
	572	void SHLD(const UINT16 opcode);
	573	void LDCRBANK(const UINT16 opcode);
	574	void LDCSSR(const UINT16 opcode);
	575	void LDCSPC(const UINT16 opcode);
	576	void PREFM(const UINT16 opcode);
	577	void FMOVMRIFR(const UINT16 opcode);
	578	void FMOVFRMR(const UINT16 opcode);
	579	void FMOVFRMDR(const UINT16 opcode);
	580	void FMOVFRS0(const UINT16 opcode);
	581	void FMOVS0FR(const UINT16 opcode);
	582	void FMOVMRFR(const UINT16 opcode);
	583	void FMOVFR(const UINT16 opcode);
	584	void FLDI1(const UINT16 opcode);
	585	void FLDI0(const UINT16 opcode);
	586	void FLDS(const UINT16 opcode);
	587	void FSTS(const UINT16 opcode);
	588	void FRCHG();
	589	void FSCHG();
	590	void FTRC(const UINT16 opcode);
	591	void FLOAT(const UINT16 opcode);
	592	void FNEG(const UINT16 opcode);
	593	void FABS(const UINT16 opcode);
	594	void FCMP_EQ(const UINT16 opcode);
	595	void FCMP_GT(const UINT16 opcode);
	596	void FCNVDS(const UINT16 opcode);
	597	void FCNVSD(const UINT16 opcode);
	598	void FADD(const UINT16 opcode);
	599	void FSUB(const UINT16 opcode);
	600	void FMUL(const UINT16 opcode);
	601	void FDIV(const UINT16 opcode);
	602	void FMAC(const UINT16 opcode);
	603	void FSQRT(const UINT16 opcode);
	604	void FSRRA(const UINT16 opcode);
	605	void FSSCA(const UINT16 opcode);
	606	void FIPR(const UINT16 opcode);
	607	void FTRV(const UINT16 opcode);
	608	void op1111_0xf13(const UINT16 opcode);
	609	void dbreak(const UINT16 opcode);
	610	void op1111_0x13(UINT16 opcode);
	611	UINT8 RB(offs_t A);
	612	UINT16 RW(offs_t A);
	613	UINT32 RL(offs_t A);
	614	void sh4_change_register_bank(int to);
	615	void sh4_swap_fp_registers();
	616	void sh4_swap_fp_couples();
	617	void sh4_syncronize_register_bank(int to);
	618	void sh4_default_exception_priorities();
	619	void sh4_exception_recompute();
	620	void sh4_exception_request(int exception);
	621	void sh4_exception_unrequest(int exception);
	622	void sh4_exception_checkunrequest(int exception);
	623	void sh4_exception(const char *message, int exception);
	624	UINT32 compute_ticks_refresh_timer(emu_timer *timer, int hertz, int base, int divisor);
	625	void sh4_refresh_timer_recompute();
	626	void increment_rtc_time(int mode);
	627	void sh4_dmac_nmi();
	628	void sh4_handler_ipra_w(UINT32 data, UINT32 mem_mask);
	629	UINT32 sh4_getsqremap(UINT32 address);
	630	void sh4_build_optable();
	631	void sh4_parse_configuration();
	632	void sh4_timer_recompute(int which);
	633	UINT32 sh4_handle_tcnt0_addr_r(UINT32 mem_mask);
	634	UINT32 sh4_handle_tcnt1_addr_r(UINT32 mem_mask);
	635	UINT32 sh4_handle_tcnt2_addr_r(UINT32 mem_mask);
	636	UINT32 sh4_handle_tcor0_addr_r(UINT32 mem_mask);
	637	UINT32 sh4_handle_tcor1_addr_r(UINT32 mem_mask);
	638	UINT32 sh4_handle_tcor2_addr_r(UINT32 mem_mask);
	639	UINT32 sh4_handle_tcr0_addr_r(UINT32 mem_mask);
	640	UINT32 sh4_handle_tcr1_addr_r(UINT32 mem_mask);
	641	UINT32 sh4_handle_tcr2_addr_r(UINT32 mem_mask);
	642	UINT32 sh4_handle_tstr_addr_r(UINT32 mem_mask);
	643	UINT32 sh4_handle_tocr_addr_r(UINT32 mem_mask);
	644	UINT32 sh4_handle_tcpr2_addr_r(UINT32 mem_mask);
	645	void sh4_handle_tstr_addr_w(UINT32 data, UINT32 mem_mask);
	646	void sh4_handle_tcr0_addr_w(UINT32 data, UINT32 mem_mask);
	647	void sh4_handle_tcr1_addr_w(UINT32 data, UINT32 mem_mask);
	648	void sh4_handle_tcr2_addr_w(UINT32 data, UINT32 mem_mask);
	649	void sh4_handle_tcor0_addr_w(UINT32 data, UINT32 mem_mask);
	650	void sh4_handle_tcor1_addr_w(UINT32 data, UINT32 mem_mask);
	651	void sh4_handle_tcor2_addr_w(UINT32 data, UINT32 mem_mask);
	652	void sh4_handle_tcnt0_addr_w(UINT32 data, UINT32 mem_mask);
	653	void sh4_handle_tcnt1_addr_w(UINT32 data, UINT32 mem_mask);
	654	void sh4_handle_tcnt2_addr_w(UINT32 data, UINT32 mem_mask);
	655	void sh4_handle_tocr_addr_w(UINT32 data, UINT32 mem_mask);
	656	void sh4_handle_tcpr2_addr_w(UINT32 data, UINT32 mem_mask);
	657	int sh4_dma_transfer(int channel, int timermode, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr);
	658	int sh4_dma_transfer_device(int channel, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr);
	659	void sh4_dmac_check(int channel);
	660	void sh4_handle_sar0_addr_w(UINT32 data, UINT32 mem_mask);
	661	void sh4_handle_sar1_addr_w(UINT32 data, UINT32 mem_mask);
	662	void sh4_handle_sar2_addr_w(UINT32 data, UINT32 mem_mask);
	663	void sh4_handle_sar3_addr_w(UINT32 data, UINT32 mem_mask);
	664	void sh4_handle_dar0_addr_w(UINT32 data, UINT32 mem_mask);
	665	void sh4_handle_dar1_addr_w(UINT32 data, UINT32 mem_mask);
	666	void sh4_handle_dar2_addr_w(UINT32 data, UINT32 mem_mask);
	667	void sh4_handle_dar3_addr_w(UINT32 data, UINT32 mem_mask);
	668	void sh4_handle_dmatcr0_addr_w(UINT32 data, UINT32 mem_mask);
	669	void sh4_handle_dmatcr1_addr_w(UINT32 data, UINT32 mem_mask);
	670	void sh4_handle_dmatcr2_addr_w(UINT32 data, UINT32 mem_mask);
	671	void sh4_handle_dmatcr3_addr_w(UINT32 data, UINT32 mem_mask);
	672	void sh4_handle_chcr0_addr_w(UINT32 data, UINT32 mem_mask);
	673	void sh4_handle_chcr1_addr_w(UINT32 data, UINT32 mem_mask);
	674	void sh4_handle_chcr2_addr_w(UINT32 data, UINT32 mem_mask);
	675	void sh4_handle_chcr3_addr_w(UINT32 data, UINT32 mem_mask);
	676	void sh4_handle_dmaor_addr_w(UINT32 data, UINT32 mem_mask);
	677	UINT32 sh4_handle_sar0_addr_r(UINT32 mem_mask) { return m_SH4_SAR0; }
	678	UINT32 sh4_handle_sar1_addr_r(UINT32 mem_mask) { return m_SH4_SAR1; }
	679	UINT32 sh4_handle_sar2_addr_r(UINT32 mem_mask) { return m_SH4_SAR2; }
	680	UINT32 sh4_handle_sar3_addr_r(UINT32 mem_mask) { return m_SH4_SAR3; }
	681	UINT32 sh4_handle_dar0_addr_r(UINT32 mem_mask) { return m_SH4_DAR0; }
	682	UINT32 sh4_handle_dar1_addr_r(UINT32 mem_mask) { return m_SH4_DAR1; }
	683	UINT32 sh4_handle_dar2_addr_r(UINT32 mem_mask) { return m_SH4_DAR2; }
	684	UINT32 sh4_handle_dar3_addr_r(UINT32 mem_mask) { return m_SH4_DAR3; }
	685	UINT32 sh4_handle_dmatcr0_addr_r(UINT32 mem_mask) { return m_SH4_DMATCR0; }
	686	UINT32 sh4_handle_dmatcr1_addr_r(UINT32 mem_mask) { return m_SH4_DMATCR1; }
	687	UINT32 sh4_handle_dmatcr2_addr_r(UINT32 mem_mask) { return m_SH4_DMATCR2; }
	688	UINT32 sh4_handle_dmatcr3_addr_r(UINT32 mem_mask) { return m_SH4_DMATCR3; }
	689	UINT32 sh4_handle_chcr0_addr_r(UINT32 mem_mask) { return m_SH4_CHCR0; }
	690	UINT32 sh4_handle_chcr1_addr_r(UINT32 mem_mask) { return m_SH4_CHCR1; }
	691	UINT32 sh4_handle_chcr2_addr_r(UINT32 mem_mask) { return m_SH4_CHCR2; }
	692	UINT32 sh4_handle_chcr3_addr_r(UINT32 mem_mask) { return m_SH4_CHCR3; }
	693	UINT32 sh4_handle_dmaor_addr_r(UINT32 mem_mask) { return m_SH4_DMAOR; }
	694
	695	};
	696
	697
	698	class sh3_base_device : public sh34_base_device
	699	{
	700	public:
	701	// construction/destruction
	702	sh3_base_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, endianness_t endianness);
	703
158	704	DECLARE_WRITE32_MEMBER( sh3_internal_w );
159	705	DECLARE_READ32_MEMBER( sh3_internal_r );
160	706
161	707	DECLARE_WRITE32_MEMBER( sh3_internal_high_w );
162	708	DECLARE_READ32_MEMBER( sh3_internal_high_r );
163
	709
	710	protected:
	711	virtual void device_reset();
164	712	};
165	713
166		extern const device_type SH3LE;
167	714
168		CPU_GET_INFO( sh3be );
	715	class sh4_base_device : public sh34_base_device
	716	{
	717	public:
	718	// construction/destruction
	719	sh4_base_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, endianness_t endianness);
169	720
170		class sh3be_device : public sh3_device
	721	DECLARE_WRITE32_MEMBER( sh4_internal_w );
	722	DECLARE_READ32_MEMBER( sh4_internal_r );
	723
	724	DECLARE_READ64_MEMBER( sh4_tlb_r );
	725	DECLARE_WRITE64_MEMBER( sh4_tlb_w );
	726
	727	protected:
	728	virtual void device_reset();
	729	};
	730
	731
	732	class sh3_device : public sh3_base_device
171	733	{
172	734	public:
173		sh3be_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock);
	735	sh3_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
174	736	};
175	737
176		extern const device_type SH3BE;
177	738
178		CPU_GET_INFO( sh4 );
	739	class sh3be_device : public sh3_base_device
	740	{
	741	public:
	742	sh3be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
179	743
180		class sh4_device : public legacy_cpu_device
	744	protected:
	745	virtual void execute_run();
	746	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
	747	};
	748
	749
	750	class sh4_device : public sh4_base_device
181	751	{
182	752	public:
183		sh4_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock);
184		sh4_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock, cpu_get_info_func info);
185
186		DECLARE_WRITE32_MEMBER( sh4_internal_w );
187		DECLARE_READ32_MEMBER( sh4_internal_r );
188
189		DECLARE_READ64_MEMBER( sh4_tlb_r );
190		DECLARE_WRITE64_MEMBER( sh4_tlb_w );
	753	sh4_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
191	754	};
192	755
193		extern const device_type SH4LE;
194	756
195		CPU_GET_INFO( sh4be );
196
197		class sh4be_device : public sh4_device
	757	class sh4be_device : public sh4_base_device
198	758	{
199	759	public:
200		sh4be_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock);
	760	sh4be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	761
	762	protected:
	763	virtual void execute_run();
	764	virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
201	765	};
202	766
	767
	768	extern const device_type SH3LE;
	769	extern const device_type SH3BE;
	770	extern const device_type SH4LE;
203	771	extern const device_type SH4BE;
204	772
205	773
206
207		void sh4_set_frt_input(device_t *device, int state);
208		void sh4_set_irln_input(device_t *device, int value);
209		void sh4_set_ftcsr_callback(device_t *device, sh4_ftcsr_callback callback);
210		int sh4_dma_data(device_t *device, struct sh4_device_dma *s);
211		void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s);
212
213	774	/***************************************************************************
214	775	COMPILER-SPECIFIC OPTIONS
215	776	***************************************************************************/

trunk/src/emu/cpu/sh4/sh4dmac.c

r31221	r31222
11	11
12	12	static const int sh3_dmasize[4] = { 1, 2, 4, 16 };
13	13
14		TIMER_CALLBACK( sh4_dmac_callback )
	14	TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_dmac_callback )
15	15	{
16		sh4_state *sh4 = (sh4_state *)ptr;
17	16	int channel = param;
18	17
19		LOG(("SH4 '%s': DMA %d complete\n", sh4->device->tag(), channel));
20		sh4->dma_timer_active[channel] = 0;
	18	LOG(("SH4 '%s': DMA %d complete\n", tag(), channel));
	19	m_dma_timer_active[channel] = 0;
21	20	switch (channel)
22	21	{
23	22	case 0:
24		sh4->SH4_DMATCR0 = 0;
25		sh4->SH4_CHCR0 |= CHCR_TE;
26		if (sh4->SH4_CHCR0 & CHCR_IE)
27		sh4_exception_request(sh4, SH4_INTC_DMTE0);
	23	m_SH4_DMATCR0 = 0;
	24	m_SH4_CHCR0 |= CHCR_TE;
	25	if (m_SH4_CHCR0 & CHCR_IE)
	26	sh4_exception_request(SH4_INTC_DMTE0);
28	27	break;
29	28	case 1:
30		sh4->SH4_DMATCR1 = 0;
31		sh4->SH4_CHCR1 |= CHCR_TE;
32		if (sh4->SH4_CHCR1 & CHCR_IE)
33		sh4_exception_request(sh4, SH4_INTC_DMTE1);
	29	m_SH4_DMATCR1 = 0;
	30	m_SH4_CHCR1 |= CHCR_TE;
	31	if (m_SH4_CHCR1 & CHCR_IE)
	32	sh4_exception_request(SH4_INTC_DMTE1);
34	33	break;
35	34	case 2:
36		sh4->SH4_DMATCR2 = 0;
37		sh4->SH4_CHCR2 |= CHCR_TE;
38		if (sh4->SH4_CHCR2 & CHCR_IE)
39		sh4_exception_request(sh4, SH4_INTC_DMTE2);
	35	m_SH4_DMATCR2 = 0;
	36	m_SH4_CHCR2 |= CHCR_TE;
	37	if (m_SH4_CHCR2 & CHCR_IE)
	38	sh4_exception_request(SH4_INTC_DMTE2);
40	39	break;
41	40	case 3:
42		sh4->SH4_DMATCR3 = 0;
43		sh4->SH4_CHCR3 |= CHCR_TE;
44		if (sh4->SH4_CHCR3 & CHCR_IE)
45		sh4_exception_request(sh4, SH4_INTC_DMTE3);
	41	m_SH4_DMATCR3 = 0;
	42	m_SH4_CHCR3 |= CHCR_TE;
	43	if (m_SH4_CHCR3 & CHCR_IE)
	44	sh4_exception_request(SH4_INTC_DMTE3);
46	45	break;
47	46	}
48	47	}
49	48
50		static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr)
	49	int sh34_base_device::sh4_dma_transfer(int channel, int timermode, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr)
51	50	{
52	51	int incs, incd, size;
53	52	UINT32 src, dst, count;
r31221	r31222
55	54	incd = (chcr & CHCR_DM) >> 14;
56	55	incs = (chcr & CHCR_SM) >> 12;
57	56
58		if (sh4->cpu_type == CPU_TYPE_SH4)
	57	if (m_cpu_type == CPU_TYPE_SH4)
59	58	{
60	59	size = dmasize[(chcr & CHCR_TS) >> 4];
61	60	}
r31221	r31222
79	78
80	79	if (timermode == 1) // timer actvated after a time based on the number of words to transfer
81	80	{
82		sh4->dma_timer_active[channel] = 1;
83		sh4->dma_timer[channel]->adjust(sh4->device->cycles_to_attotime(2*count+1), channel);
	81	m_dma_timer_active[channel] = 1;
	82	m_dma_timer[channel]->adjust(cycles_to_attotime(2*count+1), channel);
84	83	}
85	84	else if (timermode == 2) // timer activated immediately
86	85	{
87		sh4->dma_timer_active[channel] = 1;
88		sh4->dma_timer[channel]->adjust(attotime::zero, channel);
	86	m_dma_timer_active[channel] = 1;
	87	m_dma_timer[channel]->adjust(attotime::zero, channel);
89	88	}
90	89
91	90	src &= AM;
r31221	r31222
100	99	src --;
101	100	if(incd == 2)
102	101	dst --;
103		sh4->program->write_byte(dst, sh4->program->read_byte(src));
	102	m_program->write_byte(dst, m_program->read_byte(src));
104	103	if(incs == 1)
105	104	src ++;
106	105	if(incd == 1)
r31221	r31222
116	115	src -= 2;
117	116	if(incd == 2)
118	117	dst -= 2;
119		sh4->program->write_word(dst, sh4->program->read_word(src));
	118	m_program->write_word(dst, m_program->read_word(src));
120	119	if(incs == 1)
121	120	src += 2;
122	121	if(incd == 1)
r31221	r31222
132	131	src -= 8;
133	132	if(incd == 2)
134	133	dst -= 8;
135		sh4->program->write_qword(dst, sh4->program->read_qword(src));
	134	m_program->write_qword(dst, m_program->read_qword(src));
136	135	if(incs == 1)
137	136	src += 8;
138	137	if(incd == 1)
r31221	r31222
149	148	src -= 4;
150	149	if(incd == 2)
151	150	dst -= 4;
152		sh4->program->write_dword(dst, sh4->program->read_dword(src));
	151	m_program->write_dword(dst, m_program->read_dword(src));
153	152	if(incs == 1)
154	153	src += 4;
155	154	if(incd == 1)
r31221	r31222
166	165	src -= 32;
167	166	if(incd == 2)
168	167	dst -= 32;
169		sh4->program->write_qword(dst, sh4->program->read_qword(src));
170		sh4->program->write_qword(dst+8, sh4->program->read_qword(src+8));
171		sh4->program->write_qword(dst+16, sh4->program->read_qword(src+16));
172		sh4->program->write_qword(dst+24, sh4->program->read_qword(src+24));
	168	m_program->write_qword(dst, m_program->read_qword(src));
	169	m_program->write_qword(dst+8, m_program->read_qword(src+8));
	170	m_program->write_qword(dst+16, m_program->read_qword(src+16));
	171	m_program->write_qword(dst+24, m_program->read_qword(src+24));
173	172	if(incs == 1)
174	173	src += 32;
175	174	if(incd == 1)
r31221	r31222
183	182	return 1;
184	183	}
185	184
186		static int sh4_dma_transfer_device(sh4_state *sh4, int channel, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr)
	185	int sh34_base_device::sh4_dma_transfer_device(int channel, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr)
187	186	{
188	187	int incs, incd, size, mod;
189	188	UINT32 src, dst, count;
r31221	r31222
192	191	incs = (chcr & CHCR_SM) >> 12;
193	192
194	193
195		if (sh4->cpu_type == CPU_TYPE_SH4)
	194	if (m_cpu_type == CPU_TYPE_SH4)
196	195	{
197	196	size = dmasize[(chcr & CHCR_TS) >> 4];
198	197	}
r31221	r31222
215	214
216	215	LOG(("SH4: DMA %d start device<->memory %x, %x, %x, %04x, %d, %d, %d\n", channel, src, dst, count, chcr, incs, incd, size));
217	216
218		sh4->dma_timer_active[channel] = 1;
	217	m_dma_timer_active[channel] = 1;
219	218
220	219	src &= AM;
221	220	dst &= AM;
222	221
223	222	// remember parameters
224		sh4->dma_source[channel]=src;
225		sh4->dma_destination[channel]=dst;
226		sh4->dma_count[channel]=count;
227		sh4->dma_wordsize[channel]=size;
228		sh4->dma_source_increment[channel]=incs;
229		sh4->dma_destination_increment[channel]=incd;
230		sh4->dma_mode[channel]=mod;
	223	m_dma_source[channel]=src;
	224	m_dma_destination[channel]=dst;
	225	m_dma_count[channel]=count;
	226	m_dma_wordsize[channel]=size;
	227	m_dma_source_increment[channel]=incs;
	228	m_dma_destination_increment[channel]=incd;
	229	m_dma_mode[channel]=mod;
231	230
232	231	// inform device its ready to transfer
233		sh4->io->write_dword(SH4_IOPORT_DMA, channel | (mod << 16));
	232	m_io->write_dword(SH4_IOPORT_DMA, channel | (mod << 16));
234	233	return 1;
235	234	}
236	235
237		static void sh4_dmac_check(sh4_state *sh4, int channel)
	236	void sh34_base_device::sh4_dmac_check(int channel)
238	237	{
239	238	UINT32 dmatcr, chcr, sar, dar;
240	239
241	240	switch (channel)
242	241	{
243	242	case 0:
244		sar = sh4->SH4_SAR0;
245		dar = sh4->SH4_DAR0;
246		chcr = sh4->SH4_CHCR0;
247		dmatcr = sh4->SH4_DMATCR0;
	243	sar = m_SH4_SAR0;
	244	dar = m_SH4_DAR0;
	245	chcr = m_SH4_CHCR0;
	246	dmatcr = m_SH4_DMATCR0;
248	247	break;
249	248	case 1:
250		sar = sh4->SH4_SAR1;
251		dar = sh4->SH4_DAR1;
252		chcr = sh4->SH4_CHCR1;
253		dmatcr = sh4->SH4_DMATCR1;
	249	sar = m_SH4_SAR1;
	250	dar = m_SH4_DAR1;
	251	chcr = m_SH4_CHCR1;
	252	dmatcr = m_SH4_DMATCR1;
254	253	break;
255	254	case 2:
256		sar = sh4->SH4_SAR2;
257		dar = sh4->SH4_DAR2;
258		chcr = sh4->SH4_CHCR2;
259		dmatcr = sh4->SH4_DMATCR2;
	255	sar = m_SH4_SAR2;
	256	dar = m_SH4_DAR2;
	257	chcr = m_SH4_CHCR2;
	258	dmatcr = m_SH4_DMATCR2;
260	259	break;
261	260	case 3:
262		sar = sh4->SH4_SAR3;
263		dar = sh4->SH4_DAR3;
264		chcr = sh4->SH4_CHCR3;
265		dmatcr = sh4->SH4_DMATCR3;
	261	sar = m_SH4_SAR3;
	262	dar = m_SH4_DAR3;
	263	chcr = m_SH4_CHCR3;
	264	dmatcr = m_SH4_DMATCR3;
266	265	break;
267	266	default:
268	267	return;
269	268	}
270		if (chcr & sh4->SH4_DMAOR & DMAOR_DME)
	269	if (chcr & m_SH4_DMAOR & DMAOR_DME)
271	270	{
272	271	if ((((chcr & CHCR_RS) >> 8) < 2) || (((chcr & CHCR_RS) >> 8) > 6))
273	272	return;
274		if (!sh4->dma_timer_active[channel] && !(chcr & CHCR_TE) && !(sh4->SH4_DMAOR & (DMAOR_AE | DMAOR_NMIF)))
	273	if (!m_dma_timer_active[channel] && !(chcr & CHCR_TE) && !(m_SH4_DMAOR & (DMAOR_AE | DMAOR_NMIF)))
275	274	{
276	275	if (((chcr & CHCR_RS) >> 8) > 3)
277		sh4_dma_transfer(sh4, channel, 1, chcr, &sar, &dar, &dmatcr);
278		else if ((sh4->SH4_DMAOR & DMAOR_DDT) == 0)
279		sh4_dma_transfer_device(sh4, channel, chcr, &sar, &dar, &dmatcr); // tell device we are ready to transfer
	276	sh4_dma_transfer(channel, 1, chcr, &sar, &dar, &dmatcr);
	277	else if ((m_SH4_DMAOR & DMAOR_DDT) == 0)
	278	sh4_dma_transfer_device(channel, chcr, &sar, &dar, &dmatcr); // tell device we are ready to transfer
280	279	}
281	280	}
282	281	else
283	282	{
284		if (sh4->dma_timer_active[channel])
	283	if (m_dma_timer_active[channel])
285	284	{
286	285	logerror("SH4: DMA %d cancelled in-flight but all data transferred", channel);
287		sh4->dma_timer[channel]->adjust(attotime::never, channel);
288		sh4->dma_timer_active[channel] = 0;
	286	m_dma_timer[channel]->adjust(attotime::never, channel);
	287	m_dma_timer_active[channel] = 0;
289	288	}
290	289	}
291	290	}
292	291
293	292
294	293	// called by drivers to transfer data in a cpu<->device dma. 'device' must be a SH4 cpu
295		int sh4_dma_data(device_t *device, struct sh4_device_dma *s)
	294	int sh34_base_device::sh4_dma_data(struct sh4_device_dma *s)
296	295	{
297	296	UINT32 pos, len, siz;
298	297	int channel = s->channel;
299	298	void *data = s->buffer;
300	299
301		sh4_state *sh4 = get_safe_token(device);
302
303		if (!sh4->dma_timer_active[channel])
	300	if (!m_dma_timer_active[channel])
304	301	return 0;
305	302
306		if (sh4->dma_mode[channel] == 2)
	303	if (m_dma_mode[channel] == 2)
307	304	{
308	305	// device receives data
309		len = sh4->dma_count[channel];
	306	len = m_dma_count[channel];
310	307	if (s->length < len)
311	308	len = s->length;
312		siz = sh4->dma_wordsize[channel];
	309	siz = m_dma_wordsize[channel];
313	310	for (pos = 0;pos < len;pos++) {
314	311	switch (siz)
315	312	{
316	313	case 8:
317		if (sh4->dma_source_increment[channel] == 2)
318		sh4->dma_source[channel] -= 8;
319		*(UINT64 *)data = sh4->program->read_qword(sh4->dma_source[channel] & ~7);
320		if (sh4->dma_source_increment[channel] == 1)
321		sh4->dma_source[channel] += 8;
	314	if (m_dma_source_increment[channel] == 2)
	315	m_dma_source[channel] -= 8;
	316	*(UINT64 *)data = m_program->read_qword(m_dma_source[channel] & ~7);
	317	if (m_dma_source_increment[channel] == 1)
	318	m_dma_source[channel] += 8;
322	319	break;
323	320	case 1:
324		if (sh4->dma_source_increment[channel] == 2)
325		sh4->dma_source[channel]--;
326		*(UINT8 *)data = sh4->program->read_byte(sh4->dma_source[channel]);
327		if (sh4->dma_source_increment[channel] == 1)
328		sh4->dma_source[channel]++;
	321	if (m_dma_source_increment[channel] == 2)
	322	m_dma_source[channel]--;
	323	*(UINT8 *)data = m_program->read_byte(m_dma_source[channel]);
	324	if (m_dma_source_increment[channel] == 1)
	325	m_dma_source[channel]++;
329	326	break;
330	327	case 2:
331		if (sh4->dma_source_increment[channel] == 2)
332		sh4->dma_source[channel] -= 2;
333		*(UINT16 *)data = sh4->program->read_word(sh4->dma_source[channel] & ~1);
334		if (sh4->dma_source_increment[channel] == 1)
335		sh4->dma_source[channel] += 2;
	328	if (m_dma_source_increment[channel] == 2)
	329	m_dma_source[channel] -= 2;
	330	*(UINT16 *)data = m_program->read_word(m_dma_source[channel] & ~1);
	331	if (m_dma_source_increment[channel] == 1)
	332	m_dma_source[channel] += 2;
336	333	break;
337	334	case 4:
338		if (sh4->dma_source_increment[channel] == 2)
339		sh4->dma_source[channel] -= 4;
340		*(UINT32 *)data = sh4->program->read_dword(sh4->dma_source[channel] & ~3);
341		if (sh4->dma_source_increment[channel] == 1)
342		sh4->dma_source[channel] += 4;
	335	if (m_dma_source_increment[channel] == 2)
	336	m_dma_source[channel] -= 4;
	337	*(UINT32 *)data = m_program->read_dword(m_dma_source[channel] & ~3);
	338	if (m_dma_source_increment[channel] == 1)
	339	m_dma_source[channel] += 4;
343	340	break;
344	341	case 32:
345		if (sh4->dma_source_increment[channel] == 2)
346		sh4->dma_source[channel] -= 32;
347		*(UINT64 *)data = sh4->program->read_qword(sh4->dma_source[channel] & ~31);
348		*((UINT64 *)data+1) = sh4->program->read_qword((sh4->dma_source[channel] & ~31)+8);
349		*((UINT64 *)data+2) = sh4->program->read_qword((sh4->dma_source[channel] & ~31)+16);
350		*((UINT64 *)data+3) = sh4->program->read_qword((sh4->dma_source[channel] & ~31)+24);
351		if (sh4->dma_source_increment[channel] == 1)
352		sh4->dma_source[channel] += 32;
	342	if (m_dma_source_increment[channel] == 2)
	343	m_dma_source[channel] -= 32;
	344	*(UINT64 *)data = m_program->read_qword(m_dma_source[channel] & ~31);
	345	*((UINT64 *)data+1) = m_program->read_qword((m_dma_source[channel] & ~31)+8);
	346	*((UINT64 *)data+2) = m_program->read_qword((m_dma_source[channel] & ~31)+16);
	347	*((UINT64 *)data+3) = m_program->read_qword((m_dma_source[channel] & ~31)+24);
	348	if (m_dma_source_increment[channel] == 1)
	349	m_dma_source[channel] += 32;
353	350	break;
354	351	}
355		sh4->dma_count[channel]--;
	352	m_dma_count[channel]--;
356	353	}
357		if (sh4->dma_count[channel] == 0) // all data transferred ?
	354	if (m_dma_count[channel] == 0) // all data transferred ?
358	355	{
359		sh4->dma_timer[channel]->adjust(attotime::zero, channel);
	356	m_dma_timer[channel]->adjust(attotime::zero, channel);
360	357	return 2;
361	358	}
362	359	return 1;
363	360	}
364		else if (sh4->dma_mode[channel] == 3)
	361	else if (m_dma_mode[channel] == 3)
365	362	{
366	363	// device sends data
367		len = sh4->dma_count[channel];
	364	len = m_dma_count[channel];
368	365	if (s->length < len)
369	366	len = s->length;
370		siz = sh4->dma_wordsize[channel];
	367	siz = m_dma_wordsize[channel];
371	368	for (pos = 0;pos < len;pos++) {
372	369	switch (siz)
373	370	{
374	371	case 8:
375		if (sh4->dma_destination_increment[channel] == 2)
376		sh4->dma_destination[channel]-=8;
377		sh4->program->write_qword(sh4->dma_destination[channel] & ~7, *(UINT64 *)data);
378		if (sh4->dma_destination_increment[channel] == 1)
379		sh4->dma_destination[channel]+=8;
	372	if (m_dma_destination_increment[channel] == 2)
	373	m_dma_destination[channel]-=8;
	374	m_program->write_qword(m_dma_destination[channel] & ~7, *(UINT64 *)data);
	375	if (m_dma_destination_increment[channel] == 1)
	376	m_dma_destination[channel]+=8;
380	377	break;
381	378	case 1:
382		if (sh4->dma_destination_increment[channel] == 2)
383		sh4->dma_destination[channel]--;
384		sh4->program->write_byte(sh4->dma_destination[channel], *(UINT8 *)data);
385		if (sh4->dma_destination_increment[channel] == 1)
386		sh4->dma_destination[channel]++;
	379	if (m_dma_destination_increment[channel] == 2)
	380	m_dma_destination[channel]--;
	381	m_program->write_byte(m_dma_destination[channel], *(UINT8 *)data);
	382	if (m_dma_destination_increment[channel] == 1)
	383	m_dma_destination[channel]++;
387	384	break;
388	385	case 2:
389		if (sh4->dma_destination_increment[channel] == 2)
390		sh4->dma_destination[channel]-=2;
391		sh4->program->write_word(sh4->dma_destination[channel] & ~1, *(UINT16 *)data);
392		if (sh4->dma_destination_increment[channel] == 1)
393		sh4->dma_destination[channel]+=2;
	386	if (m_dma_destination_increment[channel] == 2)
	387	m_dma_destination[channel]-=2;
	388	m_program->write_word(m_dma_destination[channel] & ~1, *(UINT16 *)data);
	389	if (m_dma_destination_increment[channel] == 1)
	390	m_dma_destination[channel]+=2;
394	391	break;
395	392	case 4:
396		if (sh4->dma_destination_increment[channel] == 2)
397		sh4->dma_destination[channel]-=4;
398		sh4->program->write_dword(sh4->dma_destination[channel] & ~3, *(UINT32 *)data);
399		if (sh4->dma_destination_increment[channel] == 1)
400		sh4->dma_destination[channel]+=4;
	393	if (m_dma_destination_increment[channel] == 2)
	394	m_dma_destination[channel]-=4;
	395	m_program->write_dword(m_dma_destination[channel] & ~3, *(UINT32 *)data);
	396	if (m_dma_destination_increment[channel] == 1)
	397	m_dma_destination[channel]+=4;
401	398	break;
402	399	case 32:
403		if (sh4->dma_destination_increment[channel] == 2)
404		sh4->dma_destination[channel]-=32;
405		sh4->program->write_qword(sh4->dma_destination[channel] & ~31, *(UINT64 *)data);
406		sh4->program->write_qword((sh4->dma_destination[channel] & ~31)+8, *((UINT64 *)data+1));
407		sh4->program->write_qword((sh4->dma_destination[channel] & ~31)+16, *((UINT64 *)data+2));
408		sh4->program->write_qword((sh4->dma_destination[channel] & ~31)+24, *((UINT64 *)data+3));
409		if (sh4->dma_destination_increment[channel] == 1)
410		sh4->dma_destination[channel]+=32;
	400	if (m_dma_destination_increment[channel] == 2)
	401	m_dma_destination[channel]-=32;
	402	m_program->write_qword(m_dma_destination[channel] & ~31, *(UINT64 *)data);
	403	m_program->write_qword((m_dma_destination[channel] & ~31)+8, *((UINT64 *)data+1));
	404	m_program->write_qword((m_dma_destination[channel] & ~31)+16, *((UINT64 *)data+2));
	405	m_program->write_qword((m_dma_destination[channel] & ~31)+24, *((UINT64 *)data+3));
	406	if (m_dma_destination_increment[channel] == 1)
	407	m_dma_destination[channel]+=32;
411	408	break;
412	409	}
413		sh4->dma_count[channel]--;
	410	m_dma_count[channel]--;
414	411	}
415	412
416		if (sh4->dma_count[channel] == 0) // all data transferred ?
	413	if (m_dma_count[channel] == 0) // all data transferred ?
417	414	{
418		sh4->dma_timer[channel]->adjust(attotime::zero, channel);
	415	m_dma_timer[channel]->adjust(attotime::zero, channel);
419	416	return 2;
420	417	}
421	418	return 1;
r31221	r31222
424	421	return 0;
425	422	}
426	423
427		// called by drivers to transfer data in a DDT dma. 'device' must be a SH4 cpu
428		void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s)
	424	// called by drivers to transfer data in a DDT dma.
	425	void sh34_base_device::sh4_dma_ddt(struct sh4_ddt_dma *s)
429	426	{
430		sh4_state *sh4 = get_safe_token(device);
431	427	UINT32 chcr;
432	428	UINT32 *p32bits;
433	429	UINT64 *p32bytes;
434	430	UINT32 pos,len,siz;
435	431
436		if (sh4->cpu_type != CPU_TYPE_SH4)
437		fatalerror("sh4_dma_ddt uses sh4->m[] with SH3\n");
	432	if (m_cpu_type != CPU_TYPE_SH4)
	433	fatalerror("sh4_dma_ddt uses m_m[] with SH3\n");
438	434
439		if (sh4->dma_timer_active[s->channel])
	435	if (m_dma_timer_active[s->channel])
440	436	return;
441	437	if (s->mode >= 0) {
442	438	switch (s->channel)
443	439	{
444	440	case 0:
445	441	if (s->mode & 1)
446		s->source = sh4->SH4_SAR0;
	442	s->source = m_SH4_SAR0;
447	443	if (s->mode & 2)
448		sh4->SH4_SAR0 = s->source;
	444	m_SH4_SAR0 = s->source;
449	445	if (s->mode & 4)
450		s->destination = sh4->SH4_DAR0;
	446	s->destination = m_SH4_DAR0;
451	447	if (s->mode & 8)
452		sh4->SH4_DAR0 = s->destination;
	448	m_SH4_DAR0 = s->destination;
453	449	break;
454	450	case 1:
455	451	if (s->mode & 1)
456		s->source = sh4->SH4_SAR1;
	452	s->source = m_SH4_SAR1;
457	453	if (s->mode & 2)
458		sh4->SH4_SAR1 = s->source;
	454	m_SH4_SAR1 = s->source;
459	455	if (s->mode & 4)
460		s->destination = sh4->SH4_DAR1;
	456	s->destination = m_SH4_DAR1;
461	457	if (s->mode & 8)
462		sh4->SH4_DAR1 = s->destination;
	458	m_SH4_DAR1 = s->destination;
463	459	break;
464	460	case 2:
465	461	if (s->mode & 1)
466		s->source = sh4->SH4_SAR2;
	462	s->source = m_SH4_SAR2;
467	463	if (s->mode & 2)
468		sh4->SH4_SAR2 = s->source;
	464	m_SH4_SAR2 = s->source;
469	465	if (s->mode & 4)
470		s->destination = sh4->SH4_DAR2;
	466	s->destination = m_SH4_DAR2;
471	467	if (s->mode & 8)
472		sh4->SH4_DAR2 = s->destination;
	468	m_SH4_DAR2 = s->destination;
473	469	break;
474	470	case 3:
475	471	default:
476	472	if (s->mode & 1)
477		s->source = sh4->SH4_SAR3;
	473	s->source = m_SH4_SAR3;
478	474	if (s->mode & 2)
479		sh4->SH4_SAR3 = s->source;
	475	m_SH4_SAR3 = s->source;
480	476	if (s->mode & 4)
481		s->destination = sh4->SH4_DAR3;
	477	s->destination = m_SH4_DAR3;
482	478	if (s->mode & 8)
483		sh4->SH4_DAR3 = s->destination;
	479	m_SH4_DAR3 = s->destination;
484	480	break;
485	481	}
486	482	switch (s->channel)
487	483	{
488	484	case 0:
489		chcr = sh4->SH4_CHCR0;
490		len = sh4->SH4_DMATCR0;
	485	chcr = m_SH4_CHCR0;
	486	len = m_SH4_DMATCR0;
491	487	break;
492	488	case 1:
493		chcr = sh4->SH4_CHCR1;
494		len = sh4->SH4_DMATCR1;
	489	chcr = m_SH4_CHCR1;
	490	len = m_SH4_DMATCR1;
495	491	break;
496	492	case 2:
497		chcr = sh4->SH4_CHCR2;
498		len = sh4->SH4_DMATCR2;
	493	chcr = m_SH4_CHCR2;
	494	len = m_SH4_DMATCR2;
499	495	break;
500	496	case 3:
501	497	default:
502		chcr = sh4->SH4_CHCR3;
503		len = sh4->SH4_DMATCR3;
	498	chcr = m_SH4_CHCR3;
	499	len = m_SH4_DMATCR3;
504	500	break;
505	501	}
506	502	if ((s->direction) == 0) {
r31221	r31222
510	506	}
511	507
512	508
513		if (sh4->cpu_type == CPU_TYPE_SH4)
	509	if (m_cpu_type == CPU_TYPE_SH4)
514	510	{
515	511	//siz = dmasize[(chcr & CHCR_TS) >> 4];
516	512	siz = dmasize[(chcr >> 4) & 7];
r31221	r31222
524	520	if (siz && (s->size))
525	521	if ((len * siz) != (s->length * s->size))
526	522	return;
527		sh4_dma_transfer(sh4, s->channel, 0, chcr, &s->source, &s->destination, &len);
	523	sh4_dma_transfer(s->channel, 0, chcr, &s->source, &s->destination, &len);
528	524	} else {
529	525	if (s->size == 4) {
530	526	if ((s->direction) == 0) {
531	527	len = s->length;
532	528	p32bits = (UINT32 *)(s->buffer);
533	529	for (pos = 0;pos < len;pos++) {
534		*p32bits = sh4->program->read_dword(s->source);
	530	*p32bits = m_program->read_dword(s->source);
535	531	p32bits++;
536	532	s->source = s->source + 4;
537	533	}
r31221	r31222
539	535	len = s->length;
540	536	p32bits = (UINT32 *)(s->buffer);
541	537	for (pos = 0;pos < len;pos++) {
542		sh4->program->write_dword(s->destination, *p32bits);
	538	m_program->write_dword(s->destination, *p32bits);
543	539	p32bits++;
544	540	s->destination = s->destination + 4;
545	541	}
r31221	r31222
550	546	len = s->length * 4;
551	547	p32bytes = (UINT64 *)(s->buffer);
552	548	for (pos = 0;pos < len;pos++) {
553		*p32bytes = sh4->program->read_qword(s->source);
	549	*p32bytes = m_program->read_qword(s->source);
554	550	p32bytes++;
555	551	s->destination = s->destination + 8;
556	552	}
r31221	r31222
558	554	len = s->length * 4;
559	555	p32bytes = (UINT64 *)(s->buffer);
560	556	for (pos = 0;pos < len;pos++) {
561		sh4->program->write_qword(s->destination, *p32bytes);
	557	m_program->write_qword(s->destination, *p32bytes);
562	558	p32bytes++;
563	559	s->destination = s->destination + 8;
564	560	}
r31221	r31222
568	564	}
569	565
570	566
571		void sh4_handle_sar0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	567	void sh34_base_device::sh4_handle_sar0_addr_w(UINT32 data, UINT32 mem_mask)
572	568	{
573		COMBINE_DATA(&sh4->SH4_SAR0);
	569	COMBINE_DATA(&m_SH4_SAR0);
574	570	}
575	571
576		void sh4_handle_sar1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	572	void sh34_base_device::sh4_handle_sar1_addr_w(UINT32 data, UINT32 mem_mask)
577	573	{
578		COMBINE_DATA(&sh4->SH4_SAR1);
	574	COMBINE_DATA(&m_SH4_SAR1);
579	575	}
580	576
581		void sh4_handle_sar2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	577	void sh34_base_device::sh4_handle_sar2_addr_w(UINT32 data, UINT32 mem_mask)
582	578	{
583		COMBINE_DATA(&sh4->SH4_SAR2);
	579	COMBINE_DATA(&m_SH4_SAR2);
584	580	}
585	581
586		void sh4_handle_sar3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	582	void sh34_base_device::sh4_handle_sar3_addr_w(UINT32 data, UINT32 mem_mask)
587	583	{
588		COMBINE_DATA(&sh4->SH4_SAR3);
	584	COMBINE_DATA(&m_SH4_SAR3);
589	585	}
590	586
591		void sh4_handle_dar0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	587	void sh34_base_device::sh4_handle_dar0_addr_w(UINT32 data, UINT32 mem_mask)
592	588	{
593		COMBINE_DATA(&sh4->SH4_DAR0);
	589	COMBINE_DATA(&m_SH4_DAR0);
594	590	}
595	591
596		void sh4_handle_dar1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	592	void sh34_base_device::sh4_handle_dar1_addr_w(UINT32 data, UINT32 mem_mask)
597	593	{
598		COMBINE_DATA(&sh4->SH4_DAR1);
	594	COMBINE_DATA(&m_SH4_DAR1);
599	595	}
600	596
601		void sh4_handle_dar2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	597	void sh34_base_device::sh4_handle_dar2_addr_w(UINT32 data, UINT32 mem_mask)
602	598	{
603		COMBINE_DATA(&sh4->SH4_DAR2);
	599	COMBINE_DATA(&m_SH4_DAR2);
604	600	}
605	601
606		void sh4_handle_dar3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	602	void sh34_base_device::sh4_handle_dar3_addr_w(UINT32 data, UINT32 mem_mask)
607	603	{
608		COMBINE_DATA(&sh4->SH4_DAR3);
	604	COMBINE_DATA(&m_SH4_DAR3);
609	605	}
610	606
611		void sh4_handle_dmatcr0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	607	void sh34_base_device::sh4_handle_dmatcr0_addr_w(UINT32 data, UINT32 mem_mask)
612	608	{
613		COMBINE_DATA(&sh4->SH4_DMATCR0);
	609	COMBINE_DATA(&m_SH4_DMATCR0);
614	610	}
615	611
616		void sh4_handle_dmatcr1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	612	void sh34_base_device::sh4_handle_dmatcr1_addr_w(UINT32 data, UINT32 mem_mask)
617	613	{
618		COMBINE_DATA(&sh4->SH4_DMATCR1);
	614	COMBINE_DATA(&m_SH4_DMATCR1);
619	615	}
620	616
621		void sh4_handle_dmatcr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	617	void sh34_base_device::sh4_handle_dmatcr2_addr_w(UINT32 data, UINT32 mem_mask)
622	618	{
623		COMBINE_DATA(&sh4->SH4_DMATCR2);
	619	COMBINE_DATA(&m_SH4_DMATCR2);
624	620	}
625	621
626		void sh4_handle_dmatcr3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	622	void sh34_base_device::sh4_handle_dmatcr3_addr_w(UINT32 data, UINT32 mem_mask)
627	623	{
628		COMBINE_DATA(&sh4->SH4_DMATCR3);
	624	COMBINE_DATA(&m_SH4_DMATCR3);
629	625	}
630	626
631		void sh4_handle_chcr0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	627	void sh34_base_device::sh4_handle_chcr0_addr_w(UINT32 data, UINT32 mem_mask)
632	628	{
633		COMBINE_DATA(&sh4->SH4_CHCR0);
634		sh4_dmac_check(sh4, 0);
	629	COMBINE_DATA(&m_SH4_CHCR0);
	630	sh4_dmac_check(0);
635	631	}
636	632
637		void sh4_handle_chcr1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	633	void sh34_base_device::sh4_handle_chcr1_addr_w(UINT32 data, UINT32 mem_mask)
638	634	{
639		COMBINE_DATA(&sh4->SH4_CHCR1);
640		sh4_dmac_check(sh4, 1);
	635	COMBINE_DATA(&m_SH4_CHCR1);
	636	sh4_dmac_check(1);
641	637	}
642	638
643		void sh4_handle_chcr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	639	void sh34_base_device::sh4_handle_chcr2_addr_w(UINT32 data, UINT32 mem_mask)
644	640	{
645		COMBINE_DATA(&sh4->SH4_CHCR2);
646		sh4_dmac_check(sh4, 2);
	641	COMBINE_DATA(&m_SH4_CHCR2);
	642	sh4_dmac_check(2);
647	643	}
648	644
649		void sh4_handle_chcr3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	645	void sh34_base_device::sh4_handle_chcr3_addr_w(UINT32 data, UINT32 mem_mask)
650	646	{
651		COMBINE_DATA(&sh4->SH4_CHCR3);
652		sh4_dmac_check(sh4, 3);
	647	COMBINE_DATA(&m_SH4_CHCR3);
	648	sh4_dmac_check(3);
653	649	}
654	650
655		void sh4_handle_dmaor_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	651	void sh34_base_device::sh4_handle_dmaor_addr_w(UINT32 data, UINT32 mem_mask)
656	652	{
657		UINT32 old = sh4->SH4_DMAOR;
658		COMBINE_DATA(&sh4->SH4_DMAOR);
	653	UINT32 old = m_SH4_DMAOR;
	654	COMBINE_DATA(&m_SH4_DMAOR);
659	655
660		if ((sh4->SH4_DMAOR & DMAOR_AE) && (~old & DMAOR_AE))
661		sh4->SH4_DMAOR &= ~DMAOR_AE;
662		if ((sh4->SH4_DMAOR & DMAOR_NMIF) && (~old & DMAOR_NMIF))
663		sh4->SH4_DMAOR &= ~DMAOR_NMIF;
664		sh4_dmac_check(sh4, 0);
665		sh4_dmac_check(sh4, 1);
666		sh4_dmac_check(sh4, 2);
667		sh4_dmac_check(sh4, 3);
	656	if ((m_SH4_DMAOR & DMAOR_AE) && (~old & DMAOR_AE))
	657	m_SH4_DMAOR &= ~DMAOR_AE;
	658	if ((m_SH4_DMAOR & DMAOR_NMIF) && (~old & DMAOR_NMIF))
	659	m_SH4_DMAOR &= ~DMAOR_NMIF;
	660	sh4_dmac_check(0);
	661	sh4_dmac_check(1);
	662	sh4_dmac_check(2);
	663	sh4_dmac_check(3);
668	664	}
669	665
670		UINT32 sh4_handle_sar0_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_SAR0; }
671		UINT32 sh4_handle_sar1_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_SAR1; }
672		UINT32 sh4_handle_sar2_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_SAR2; }
673		UINT32 sh4_handle_sar3_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_SAR3; }
674		UINT32 sh4_handle_dar0_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DAR0; }
675		UINT32 sh4_handle_dar1_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DAR1; }
676		UINT32 sh4_handle_dar2_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DAR2; }
677		UINT32 sh4_handle_dar3_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DAR3; }
678		UINT32 sh4_handle_dmatcr0_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DMATCR0; }
679		UINT32 sh4_handle_dmatcr1_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DMATCR1; }
680		UINT32 sh4_handle_dmatcr2_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DMATCR2; }
681		UINT32 sh4_handle_dmatcr3_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DMATCR3; }
682		UINT32 sh4_handle_chcr0_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_CHCR0; }
683		UINT32 sh4_handle_chcr1_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_CHCR1; }
684		UINT32 sh4_handle_chcr2_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_CHCR2; }
685		UINT32 sh4_handle_chcr3_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_CHCR3; }
686		UINT32 sh4_handle_dmaor_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DMAOR; }

trunk/src/emu/cpu/sh4/sh4tmu.c

r31221	r31222
27	27	return (UINT32)ret;
28	28	}
29	29
30		static void sh4_timer_recompute(sh4_state *sh4, int which)
	30	void sh34_base_device::sh4_timer_recompute(int which)
31	31	{
32	32	double ticks;
33	33
r31221	r31222
36	36	switch (which)
37	37	{
38	38	case 0:
39		tcr = sh4->SH4_TCR0;
40		tcnt = sh4->SH4_TCNT0;
	39	tcr = m_SH4_TCR0;
	40	tcnt = m_SH4_TCNT0;
41	41	break;
42	42
43	43	case 1:
44		tcr = sh4->SH4_TCR1;
45		tcnt = sh4->SH4_TCNT1;
	44	tcr = m_SH4_TCR1;
	45	tcnt = m_SH4_TCNT1;
46	46	break;
47	47
48	48	case 2:
49		tcr = sh4->SH4_TCR2;
50		tcnt = sh4->SH4_TCNT2;
	49	tcr = m_SH4_TCR2;
	50	tcnt = m_SH4_TCNT2;
51	51	break;
52	52	}
53	53
54	54	ticks = tcnt;
55		sh4->timer[which]->adjust(sh4_scale_up_mame_time(attotime::from_hz(sh4->pm_clock) * tcnt_div[tcr & 7], ticks), which);
	55	m_timer[which]->adjust(sh4_scale_up_mame_time(attotime::from_hz(m_pm_clock) * tcnt_div[tcr & 7], ticks), which);
56	56	}
57	57
58	58
59		TIMER_CALLBACK( sh4_timer_callback )
	59	TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_timer_callback )
60	60	{
61		sh4_state *sh4 = (sh4_state *)ptr;
62	61	int which = param;
63	62
64	63	switch (which)
65	64	{
66	65	case 0:
67		sh4->SH4_TCNT0 = sh4->SH4_TCOR0;
	66	m_SH4_TCNT0 = m_SH4_TCOR0;
68	67	break;
69	68
70	69	case 1:
71		sh4->SH4_TCNT1 = sh4->SH4_TCOR1;
	70	m_SH4_TCNT1 = m_SH4_TCOR1;
72	71	break;
73	72
74	73	case 2:
75		sh4->SH4_TCNT2 = sh4->SH4_TCOR2;
	74	m_SH4_TCNT2 = m_SH4_TCOR2;
76	75	break;
77	76
78	77	}
79	78
80		sh4_timer_recompute(sh4, which);
	79	sh4_timer_recompute(which);
81	80
82	81	switch (which)
83	82	{
84	83	case 0:
85		sh4->SH4_TCR0 |= 0x100;
	84	m_SH4_TCR0 |= 0x100;
86	85	break;
87	86
88	87	case 1:
89		sh4->SH4_TCR1 |= 0x100;
	88	m_SH4_TCR1 |= 0x100;
90	89	break;
91	90
92	91	case 2:
93		sh4->SH4_TCR2 |= 0x100;
	92	m_SH4_TCR2 |= 0x100;
94	93	break;
95	94
96	95	}
r31221	r31222
98	97	switch (which)
99	98	{
100	99	case 0:
101		if (sh4->SH4_TCR0 & 0x20)
	100	if (m_SH4_TCR0 & 0x20)
102	101	{
103		sh4_exception_request(sh4, SH4_INTC_TUNI0);
	102	sh4_exception_request(SH4_INTC_TUNI0);
104	103	//  logerror("SH4_INTC_TUNI0 requested\n");
105	104	}
106	105	break;
107	106
108	107	case 1:
109		if (sh4->SH4_TCR1 & 0x20)
	108	if (m_SH4_TCR1 & 0x20)
110	109	{
111		sh4_exception_request(sh4, SH4_INTC_TUNI1);
	110	sh4_exception_request(SH4_INTC_TUNI1);
112	111	//  logerror("SH4_INTC_TUNI1 requested\n");
113	112	}
114	113	break;
115	114
116	115	case 2:
117		if (sh4->SH4_TCR2 & 0x20)
	116	if (m_SH4_TCR2 & 0x20)
118	117	{
119		sh4_exception_request(sh4, SH4_INTC_TUNI2);
	118	sh4_exception_request(SH4_INTC_TUNI2);
120	119	//  logerror("SH4_INTC_TUNI2 requested\n");
121	120	}
122	121	break;
r31221	r31222
125	124	}
126	125
127	126
128		UINT32 sh4_handle_tcnt0_addr_r(sh4_state *sh4, UINT32 mem_mask)
	127	UINT32 sh34_base_device::sh4_handle_tcnt0_addr_r(UINT32 mem_mask)
129	128	{
130		if (sh4->SH4_TSTR & 1)
131		return compute_ticks_timer(sh4->timer[0], sh4->pm_clock, tcnt_div[sh4->SH4_TCR0 & 7]);
	129	if (m_SH4_TSTR & 1)
	130	return compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[m_SH4_TCR0 & 7]);
132	131	else
133		return sh4->SH4_TCNT0;
	132	return m_SH4_TCNT0;
134	133	}
135	134
136		UINT32 sh4_handle_tcnt1_addr_r(sh4_state *sh4, UINT32 mem_mask)
	135	UINT32 sh34_base_device::sh4_handle_tcnt1_addr_r(UINT32 mem_mask)
137	136	{
138		if (sh4->SH4_TSTR & 2)
139		return compute_ticks_timer(sh4->timer[1], sh4->pm_clock, tcnt_div[sh4->SH4_TCR1 & 7]);
	137	if (m_SH4_TSTR & 2)
	138	return compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[m_SH4_TCR1 & 7]);
140	139	else
141		return sh4->SH4_TCNT1;
	140	return m_SH4_TCNT1;
142	141	}
143	142
144		UINT32 sh4_handle_tcnt2_addr_r(sh4_state *sh4, UINT32 mem_mask)
	143	UINT32 sh34_base_device::sh4_handle_tcnt2_addr_r(UINT32 mem_mask)
145	144	{
146		if (sh4->SH4_TSTR & 4)
147		return compute_ticks_timer(sh4->timer[2], sh4->pm_clock, tcnt_div[sh4->SH4_TCR2 & 7]);
	145	if (m_SH4_TSTR & 4)
	146	return compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[m_SH4_TCR2 & 7]);
148	147	else
149		return sh4->SH4_TCNT2;
	148	return m_SH4_TCNT2;
150	149	}
151	150
152		UINT32 sh4_handle_tcor0_addr_r(sh4_state *sh4, UINT32 mem_mask)
	151	UINT32 sh34_base_device::sh4_handle_tcor0_addr_r(UINT32 mem_mask)
153	152	{
154		return sh4->SH4_TCOR0;
	153	return m_SH4_TCOR0;
155	154	}
156	155
157		UINT32 sh4_handle_tcor1_addr_r(sh4_state *sh4, UINT32 mem_mask)
	156	UINT32 sh34_base_device::sh4_handle_tcor1_addr_r(UINT32 mem_mask)
158	157	{
159		return sh4->SH4_TCOR1;
	158	return m_SH4_TCOR1;
160	159	}
161	160
162		UINT32 sh4_handle_tcor2_addr_r(sh4_state *sh4, UINT32 mem_mask)
	161	UINT32 sh34_base_device::sh4_handle_tcor2_addr_r(UINT32 mem_mask)
163	162	{
164		return sh4->SH4_TCOR2;
	163	return m_SH4_TCOR2;
165	164	}
166	165
167		UINT32 sh4_handle_tcr0_addr_r(sh4_state *sh4, UINT32 mem_mask)
	166	UINT32 sh34_base_device::sh4_handle_tcr0_addr_r(UINT32 mem_mask)
168	167	{
169		return sh4->SH4_TCR0;
	168	return m_SH4_TCR0;
170	169	}
171	170
172		UINT32 sh4_handle_tcr1_addr_r(sh4_state *sh4, UINT32 mem_mask)
	171	UINT32 sh34_base_device::sh4_handle_tcr1_addr_r(UINT32 mem_mask)
173	172	{
174		return sh4->SH4_TCR1;
	173	return m_SH4_TCR1;
175	174	}
176	175
177		UINT32 sh4_handle_tcr2_addr_r(sh4_state *sh4, UINT32 mem_mask)
	176	UINT32 sh34_base_device::sh4_handle_tcr2_addr_r(UINT32 mem_mask)
178	177	{
179		return sh4->SH4_TCR2;
	178	return m_SH4_TCR2;
180	179	}
181	180
182		UINT32 sh4_handle_tstr_addr_r(sh4_state *sh4, UINT32 mem_mask)
	181	UINT32 sh34_base_device::sh4_handle_tstr_addr_r(UINT32 mem_mask)
183	182	{
184		return sh4->SH4_TSTR;
	183	return m_SH4_TSTR;
185	184	}
186	185
187		UINT32 sh4_handle_tocr_addr_r(sh4_state *sh4, UINT32 mem_mask)
	186	UINT32 sh34_base_device::sh4_handle_tocr_addr_r(UINT32 mem_mask)
188	187	{
189		return sh4->SH4_TOCR;
	188	return m_SH4_TOCR;
190	189	}
191	190
192		UINT32 sh4_handle_tcpr2_addr_r(sh4_state *sh4, UINT32 mem_mask)
	191	UINT32 sh34_base_device::sh4_handle_tcpr2_addr_r(UINT32 mem_mask)
193	192	{
194		return sh4->SH4_TCPR2;
	193	return m_SH4_TCPR2;
195	194	}
196	195
197	196
198		void sh4_handle_tstr_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	197	void sh34_base_device::sh4_handle_tstr_addr_w(UINT32 data, UINT32 mem_mask)
199	198	{
200		UINT32 old2 = sh4->SH4_TSTR;
201		COMBINE_DATA(&sh4->SH4_TSTR);
	199	UINT32 old2 = m_SH4_TSTR;
	200	COMBINE_DATA(&m_SH4_TSTR);
202	201
203	202	if (old2 & 1)
204		sh4->SH4_TCNT0 = compute_ticks_timer(sh4->timer[0], sh4->pm_clock, tcnt_div[sh4->SH4_TCR0 & 7]);
205		if ((sh4->SH4_TSTR & 1) == 0) {
206		sh4->timer[0]->adjust(attotime::never);
	203	m_SH4_TCNT0 = compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[m_SH4_TCR0 & 7]);
	204	if ((m_SH4_TSTR & 1) == 0) {
	205	m_timer[0]->adjust(attotime::never);
207	206	} else
208		sh4_timer_recompute(sh4, 0);
	207	sh4_timer_recompute(0);
209	208
210	209	if (old2 & 2)
211		sh4->SH4_TCNT1 = compute_ticks_timer(sh4->timer[1], sh4->pm_clock, tcnt_div[sh4->SH4_TCR1 & 7]);
212		if ((sh4->SH4_TSTR & 2) == 0) {
213		sh4->timer[1]->adjust(attotime::never);
	210	m_SH4_TCNT1 = compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[m_SH4_TCR1 & 7]);
	211	if ((m_SH4_TSTR & 2) == 0) {
	212	m_timer[1]->adjust(attotime::never);
214	213	} else
215		sh4_timer_recompute(sh4, 1);
	214	sh4_timer_recompute(1);
216	215
217	216	if (old2 & 4)
218		sh4->SH4_TCNT2 = compute_ticks_timer(sh4->timer[2], sh4->pm_clock, tcnt_div[sh4->SH4_TCR2 & 7]);
219		if ((sh4->SH4_TSTR & 4) == 0) {
220		sh4->timer[2]->adjust(attotime::never);
	217	m_SH4_TCNT2 = compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[m_SH4_TCR2 & 7]);
	218	if ((m_SH4_TSTR & 4) == 0) {
	219	m_timer[2]->adjust(attotime::never);
221	220	} else
222		sh4_timer_recompute(sh4, 2);
	221	sh4_timer_recompute(2);
223	222	}
224	223
225		void sh4_handle_tcr0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	224	void sh34_base_device::sh4_handle_tcr0_addr_w(UINT32 data, UINT32 mem_mask)
226	225	{
227		UINT32 old2 = sh4->SH4_TCR0;
228		COMBINE_DATA(&sh4->SH4_TCR0);
229		if (sh4->SH4_TSTR & 1)
	226	UINT32 old2 = m_SH4_TCR0;
	227	COMBINE_DATA(&m_SH4_TCR0);
	228	if (m_SH4_TSTR & 1)
230	229	{
231		sh4->SH4_TCNT0 = compute_ticks_timer(sh4->timer[0], sh4->pm_clock, tcnt_div[old2 & 7]);
232		sh4_timer_recompute(sh4, 0);
	230	m_SH4_TCNT0 = compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[old2 & 7]);
	231	sh4_timer_recompute(0);
233	232	}
234		if (!(sh4->SH4_TCR0 & 0x20) || !(sh4->SH4_TCR0 & 0x100))
235		sh4_exception_unrequest(sh4, SH4_INTC_TUNI0);
	233	if (!(m_SH4_TCR0 & 0x20) || !(m_SH4_TCR0 & 0x100))
	234	sh4_exception_unrequest(SH4_INTC_TUNI0);
236	235	}
237	236
238		void sh4_handle_tcr1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	237	void sh34_base_device::sh4_handle_tcr1_addr_w(UINT32 data, UINT32 mem_mask)
239	238	{
240		UINT32 old2 = sh4->SH4_TCR1;
241		COMBINE_DATA(&sh4->SH4_TCR1);
242		if (sh4->SH4_TSTR & 2)
	239	UINT32 old2 = m_SH4_TCR1;
	240	COMBINE_DATA(&m_SH4_TCR1);
	241	if (m_SH4_TSTR & 2)
243	242	{
244		sh4->SH4_TCNT1 = compute_ticks_timer(sh4->timer[1], sh4->pm_clock, tcnt_div[old2 & 7]);
245		sh4_timer_recompute(sh4, 1);
	243	m_SH4_TCNT1 = compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[old2 & 7]);
	244	sh4_timer_recompute(1);
246	245	}
247		if (!(sh4->SH4_TCR1 & 0x20) || !(sh4->SH4_TCR1 & 0x100))
248		sh4_exception_unrequest(sh4, SH4_INTC_TUNI1);
	246	if (!(m_SH4_TCR1 & 0x20) || !(m_SH4_TCR1 & 0x100))
	247	sh4_exception_unrequest(SH4_INTC_TUNI1);
249	248	}
250	249
251		void sh4_handle_tcr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	250	void sh34_base_device::sh4_handle_tcr2_addr_w(UINT32 data, UINT32 mem_mask)
252	251	{
253		UINT32 old2 = sh4->SH4_TCR2;
254		COMBINE_DATA(&sh4->SH4_TCR2);
255		if (sh4->SH4_TSTR & 4)
	252	UINT32 old2 = m_SH4_TCR2;
	253	COMBINE_DATA(&m_SH4_TCR2);
	254	if (m_SH4_TSTR & 4)
256	255	{
257		sh4->SH4_TCNT2 = compute_ticks_timer(sh4->timer[2], sh4->pm_clock, tcnt_div[old2 & 7]);
258		sh4_timer_recompute(sh4, 2);
	256	m_SH4_TCNT2 = compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[old2 & 7]);
	257	sh4_timer_recompute(2);
259	258	}
260		if (!(sh4->SH4_TCR2 & 0x20) || !(sh4->SH4_TCR2 & 0x100))
261		sh4_exception_unrequest(sh4, SH4_INTC_TUNI2);
	259	if (!(m_SH4_TCR2 & 0x20) || !(m_SH4_TCR2 & 0x100))
	260	sh4_exception_unrequest(SH4_INTC_TUNI2);
262	261	}
263	262
264		void sh4_handle_tcor0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	263	void sh34_base_device::sh4_handle_tcor0_addr_w(UINT32 data, UINT32 mem_mask)
265	264	{
266		COMBINE_DATA(&sh4->SH4_TCOR0);
267		if (sh4->SH4_TSTR & 1)
	265	COMBINE_DATA(&m_SH4_TCOR0);
	266	if (m_SH4_TSTR & 1)
268	267	{
269		sh4->SH4_TCNT0 = compute_ticks_timer(sh4->timer[0], sh4->pm_clock, tcnt_div[sh4->SH4_TCR0 & 7]);
270		sh4_timer_recompute(sh4, 0);
	268	m_SH4_TCNT0 = compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[m_SH4_TCR0 & 7]);
	269	sh4_timer_recompute(0);
271	270	}
272	271	}
273	272
274		void sh4_handle_tcor1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	273	void sh34_base_device::sh4_handle_tcor1_addr_w(UINT32 data, UINT32 mem_mask)
275	274	{
276		COMBINE_DATA(&sh4->SH4_TCOR1);
277		if (sh4->SH4_TSTR & 2)
	275	COMBINE_DATA(&m_SH4_TCOR1);
	276	if (m_SH4_TSTR & 2)
278	277	{
279		sh4->SH4_TCNT1 = compute_ticks_timer(sh4->timer[1], sh4->pm_clock, tcnt_div[sh4->SH4_TCR1 & 7]);
280		sh4_timer_recompute(sh4, 1);
	278	m_SH4_TCNT1 = compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[m_SH4_TCR1 & 7]);
	279	sh4_timer_recompute(1);
281	280	}
282	281	}
283	282
284		void sh4_handle_tcor2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	283	void sh34_base_device::sh4_handle_tcor2_addr_w(UINT32 data, UINT32 mem_mask)
285	284	{
286		COMBINE_DATA(&sh4->SH4_TCOR2);
287		if (sh4->SH4_TSTR & 4)
	285	COMBINE_DATA(&m_SH4_TCOR2);
	286	if (m_SH4_TSTR & 4)
288	287	{
289		sh4->SH4_TCNT2 = compute_ticks_timer(sh4->timer[2], sh4->pm_clock, tcnt_div[sh4->SH4_TCR2 & 7]);
290		sh4_timer_recompute(sh4, 2);
	288	m_SH4_TCNT2 = compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[m_SH4_TCR2 & 7]);
	289	sh4_timer_recompute(2);
291	290	}
292	291	}
293	292
294		void sh4_handle_tcnt0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	293	void sh34_base_device::sh4_handle_tcnt0_addr_w(UINT32 data, UINT32 mem_mask)
295	294	{
296		COMBINE_DATA(&sh4->SH4_TCNT0);
297		if (sh4->SH4_TSTR & 1)
298		sh4_timer_recompute(sh4, 0);
	295	COMBINE_DATA(&m_SH4_TCNT0);
	296	if (m_SH4_TSTR & 1)
	297	sh4_timer_recompute(0);
299	298	}
300	299
301		void sh4_handle_tcnt1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	300	void sh34_base_device::sh4_handle_tcnt1_addr_w(UINT32 data, UINT32 mem_mask)
302	301	{
303		COMBINE_DATA(&sh4->SH4_TCNT1);
304		if (sh4->SH4_TSTR & 2)
305		sh4_timer_recompute(sh4, 1);
	302	COMBINE_DATA(&m_SH4_TCNT1);
	303	if (m_SH4_TSTR & 2)
	304	sh4_timer_recompute(1);
306	305	}
307	306
308		void sh4_handle_tcnt2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	307	void sh34_base_device::sh4_handle_tcnt2_addr_w(UINT32 data, UINT32 mem_mask)
309	308	{
310		COMBINE_DATA(&sh4->SH4_TCNT2);
311		if (sh4->SH4_TSTR & 4)
312		sh4_timer_recompute(sh4, 2);
	309	COMBINE_DATA(&m_SH4_TCNT2);
	310	if (m_SH4_TSTR & 4)
	311	sh4_timer_recompute(2);
313	312	}
314	313
315		void sh4_handle_tocr_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	314	void sh34_base_device::sh4_handle_tocr_addr_w(UINT32 data, UINT32 mem_mask)
316	315	{
317		COMBINE_DATA(&sh4->SH4_TOCR);
	316	COMBINE_DATA(&m_SH4_TOCR);
318	317	}
319	318
320		void sh4_handle_tcpr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
	319	void sh34_base_device::sh4_handle_tcpr2_addr_w(UINT32 data, UINT32 mem_mask)
321	320	{
322		COMBINE_DATA(&sh4->SH4_TCPR2);
	321	COMBINE_DATA(&m_SH4_TCPR2);
323	322	}

trunk/src/mess/drivers/sh4robot.c

r31221	r31222
54	54
55	55	static INPUT_PORTS_START( sh4robot )
56	56	INPUT_PORTS_END
57		static const struct sh4_config sh4cpu_config = {  1,  0,  1,  0,  0,  0,  1,  1,  0, 200000000 };
58	57
59	58	static MACHINE_CONFIG_START( sh4robot, sh4robot_state )
60	59	/* basic machine hardware */
61	60	MCFG_CPU_ADD("maincpu", SH4LE, 200000000) // SH7750
62		MCFG_CPU_CONFIG(sh4cpu_config)
	61	MCFG_SH4_MD0(1)
	62	MCFG_SH4_MD1(0)
	63	MCFG_SH4_MD2(1)
	64	MCFG_SH4_MD3(0)
	65	MCFG_SH4_MD4(0)
	66	MCFG_SH4_MD5(1)
	67	MCFG_SH4_MD6(0)
	68	MCFG_SH4_MD7(1)
	69	MCFG_SH4_MD8(0)
	70	MCFG_SH4_CLOCK(200000000)
63	71	MCFG_CPU_PROGRAM_MAP(sh4robot_mem)
64	72	MCFG_CPU_IO_MAP(sh4robot_io)
65	73

trunk/src/mess/drivers/dccons.c

r31221	r31222
595	595	dc_update_interrupt_status();
596	596	}
597	597
598		static const struct sh4_config sh4cpu_config = {  1,  0,  1,  0,  0,  0,  1,  1,  0, CPU_CLOCK };
599
600	598	static MACHINE_CONFIG_FRAGMENT( gdrom_config )
601	599	MCFG_DEVICE_MODIFY("cdda")
602	600	MCFG_SOUND_ROUTE(0, "^^^^lspeaker", 1.0)
r31221	r31222
606	604	static MACHINE_CONFIG_START( dc, dc_cons_state )
607	605	/* basic machine hardware */
608	606	MCFG_CPU_ADD("maincpu", SH4LE, CPU_CLOCK)
609		MCFG_CPU_CONFIG(sh4cpu_config)
	607	MCFG_SH4_MD0(1)
	608	MCFG_SH4_MD1(0)
	609	MCFG_SH4_MD2(1)
	610	MCFG_SH4_MD3(0)
	611	MCFG_SH4_MD4(0)
	612	MCFG_SH4_MD5(1)
	613	MCFG_SH4_MD6(0)
	614	MCFG_SH4_MD7(1)
	615	MCFG_SH4_MD8(0)
	616	MCFG_SH4_CLOCK(CPU_CLOCK)
610	617	MCFG_CPU_PROGRAM_MAP(dc_map)
611	618	MCFG_CPU_IO_MAP(dc_port)
612	619	MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", dc_state, dc_scanline, "screen", 0, 1)

trunk/src/mess/machine/dccons.c

r31221	r31222
71	71	ddtdata.channel= 0;
72	72	ddtdata.mode= -1;       // copy from/to buffer
73	73	printf("ATAPI: DMA one sector to %x, %x remaining\n", atapi_xferbase, atapi_xferlen);
74		sh4_dma_ddt(m_maincpu, &ddtdata);
	74	m_maincpu->sh4_dma_ddt(&ddtdata);
75	75
76	76	atapi_xferbase += 2048;
77	77	}

trunk/src/mame/machine/dc.c

r31221	r31222
88	88	ddt.direction = to_mainram;
89	89	ddt.channel = 0;
90	90	ddt.mode = -1;
91		sh4_dma_ddt(m_maincpu, &ddt);
	91	m_maincpu->sh4_dma_ddt(&ddt);
92	92	}
93	93
94	94	TIMER_CALLBACK_MEMBER(dc_state::aica_dma_irq)
r31221	r31222
332	332	}
333	333
334	334	level=dc_compute_interrupt_level();
335		sh4_set_irln_input(m_maincpu, 15-level);
	335	m_maincpu->sh4_set_irln_input(15-level);
336	336
337	337	/* Wave DMA HW trigger */
338	338	if(m_wave_dma.flag && ((m_wave_dma.sel & 2) == 2))
r31221	r31222
407	407	ddtdata.direction=0;
408	408	ddtdata.channel=2;
409	409	ddtdata.mode=25; //011001
410		sh4_dma_ddt(m_maincpu,&ddtdata);
	410	m_maincpu->sh4_dma_ddt(&ddtdata);
411	411	#if DEBUG_SYSCTRL
412	412	if ((address >= 0x11000000) && (address <= 0x11FFFFFF))
413	413	if (dc_sysctrl_regs[SB_LMMODE0])

trunk/src/mame/machine/maple-dc.c

r31221	r31222
120	120	ddtdata.direction = 0;       // 0 source to buffer, 1 buffer to source
121	121	ddtdata.channel   = 0;
122	122	ddtdata.mode      = -1;      // copy from/to buffer
123		sh4_dma_ddt(cpu, &ddtdata);
	123	cpu->sh4_dma_ddt(&ddtdata);
124	124	dma_adr += 8;
125	125
126	126	dma_endflag    = header[0] & 0x80000000;
r31221	r31222
136	136	ddtdata.direction = 0;       // 0 source to buffer, 1 buffer to source
137	137	ddtdata.channel   = 0;
138	138	ddtdata.mode      = -1;      // copy from/to buffer
139		sh4_dma_ddt(cpu, &ddtdata);
	139	cpu->sh4_dma_ddt(&ddtdata);
140	140	dma_adr += length*4;
141	141
142	142	switch(pattern) {
r31221	r31222
191	191	ddtdata.direction   = 1;        // 0 source to buffer, 1 buffer to source
192	192	ddtdata.channel     = 0;
193	193	ddtdata.mode        = -1;       // copy from/to buffer
194		sh4_dma_ddt(cpu, &ddtdata);
	194	cpu->sh4_dma_ddt(&ddtdata);
195	195	dma_state = dma_endflag ? DMA_DONE : DMA_SEND;
196	196	break;
197	197	}
r31221	r31222
216	216	ddtdata.direction   = 1;        // 0 source to buffer, 1 buffer to source
217	217	ddtdata.channel     = 0;
218	218	ddtdata.mode        = -1;       // copy from/to buffer
219		sh4_dma_ddt(cpu, &ddtdata);
	219	cpu->sh4_dma_ddt(&ddtdata);
220	220	dma_dest += length*4;
221	221	}
222	222

trunk/src/mame/includes/dc.h

r31221	r31222
77	77	DECLARE_WRITE8_MEMBER( g1_irq );
78	78	DECLARE_WRITE8_MEMBER( pvr_irq );
79	79
80		required_device<cpu_device> m_maincpu;
	80	required_device<sh4_base_device> m_maincpu;
81	81	required_device<cpu_device> m_soundcpu;
82	82	required_device<powervr2_device> m_powervr2;
83	83	required_device<maple_dc_device> m_maple;

trunk/src/mame/drivers/naomi.c

r31221	r31222
1491	1491	#include "includes/naomi.h"
1492	1492
1493	1493	#define CPU_CLOCK (200000000)
1494		/* MD2 MD1 MD0 MD6 MD4 MD3 MD5 MD7 MD8 */
1495		static const struct sh4_config sh4cpu_config = {  1,  0,  1,  0,  0,  0,  1,  1,  0, CPU_CLOCK };
1496	1494
1497	1495	READ64_MEMBER(naomi_state::naomi_arm_r )
1498	1496	{
r31221	r31222
2547	2545	static MACHINE_CONFIG_START( naomi_aw_base, naomi_state )
2548	2546	/* basic machine hardware */
2549	2547	MCFG_CPU_ADD("maincpu", SH4LE, CPU_CLOCK) // SH4!!!
2550		MCFG_CPU_CONFIG(sh4cpu_config)
	2548	MCFG_SH4_MD0(1)
	2549	MCFG_SH4_MD1(0)
	2550	MCFG_SH4_MD2(1)
	2551	MCFG_SH4_MD3(0)
	2552	MCFG_SH4_MD4(0)
	2553	MCFG_SH4_MD5(1)
	2554	MCFG_SH4_MD6(0)
	2555	MCFG_SH4_MD7(1)
	2556	MCFG_SH4_MD8(0)
	2557	MCFG_SH4_CLOCK(CPU_CLOCK)
2551	2558	MCFG_CPU_PROGRAM_MAP(naomi_map)
2552	2559	MCFG_CPU_IO_MAP(naomi_port)
2553	2560	MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", dc_state, dc_scanline, "screen", 0, 1)

trunk/src/mame/drivers/atvtrack.c

r31221	r31222
387	387	// ?
388	388	#define ATV_CPU_CLOCK 200000000
389	389	// ?
390		static const struct sh4_config sh4cpu_config = {  1,  0,  1,  0,  0,  0,  1,  1,  0, ATV_CPU_CLOCK };
391	390
392	391	static MACHINE_CONFIG_START( atvtrack, atvtrack_state )
393	392	/* basic machine hardware */
394	393	MCFG_CPU_ADD("maincpu", SH4LE, ATV_CPU_CLOCK)
395		MCFG_CPU_CONFIG(sh4cpu_config)
	394	MCFG_SH4_MD0(1)
	395	MCFG_SH4_MD1(0)
	396	MCFG_SH4_MD2(1)
	397	MCFG_SH4_MD3(0)
	398	MCFG_SH4_MD4(0)
	399	MCFG_SH4_MD5(1)
	400	MCFG_SH4_MD6(0)
	401	MCFG_SH4_MD7(1)
	402	MCFG_SH4_MD8(0)
	403	MCFG_SH4_CLOCK(ATV_CPU_CLOCK)
396	404	MCFG_CPU_PROGRAM_MAP(atvtrack_main_map)
397	405	MCFG_CPU_IO_MAP(atvtrack_main_port)
398	406
399	407	MCFG_CPU_ADD("subcpu", SH4LE, ATV_CPU_CLOCK)
400		MCFG_CPU_CONFIG(sh4cpu_config)
	408	MCFG_SH4_MD0(1)
	409	MCFG_SH4_MD1(0)
	410	MCFG_SH4_MD2(1)
	411	MCFG_SH4_MD3(0)
	412	MCFG_SH4_MD4(0)
	413	MCFG_SH4_MD5(1)
	414	MCFG_SH4_MD6(0)
	415	MCFG_SH4_MD7(1)
	416	MCFG_SH4_MD8(0)
	417	MCFG_SH4_CLOCK(ATV_CPU_CLOCK)
401	418	MCFG_CPU_PROGRAM_MAP(atvtrack_sub_map)
402	419	MCFG_CPU_IO_MAP(atvtrack_sub_port)
403	420

trunk/src/mame/drivers/cv1k.c

r31221	r31222
404	404	INPUT_PORTS_END
405	405
406	406
407
408		// none of this is verified
409		// (the sh3 is different to the sh4 anyway, should be changed)
410		static const struct sh4_config sh4cpu_config = {
411		0, // md2 (clock divders)
412		0, // md1 (clock divders)
413		0, // md0 (clock divders)
414		0,
415		0,
416		0,
417		1,
418		1, // md7 (master?)
419		0,
420		CPU_CLOCK // influences music sequencing in ddpdfk at least
421		};
422
423
424
425	407	INTERRUPT_GEN_MEMBER(cv1k_state::cv1k_interrupt)
426	408	{
427	409	m_maincpu->set_input_line(2, HOLD_LINE);
r31221	r31222
439	421	static MACHINE_CONFIG_START( cv1k, cv1k_state )
440	422	/* basic machine hardware */
441	423	MCFG_CPU_ADD("maincpu", SH3BE, CPU_CLOCK)
442		MCFG_CPU_CONFIG(sh4cpu_config)
	424	MCFG_SH4_MD0(0)  // none of this is verified
	425	MCFG_SH4_MD1(0)  // (the sh3 is different to the sh4 anyway, should be changed)
	426	MCFG_SH4_MD2(0)
	427	MCFG_SH4_MD3(0)
	428	MCFG_SH4_MD4(0)
	429	MCFG_SH4_MD5(1)
	430	MCFG_SH4_MD6(0)
	431	MCFG_SH4_MD7(1)
	432	MCFG_SH4_MD8(0)
	433	MCFG_SH4_CLOCK(CPU_CLOCK)
443	434	MCFG_CPU_PROGRAM_MAP(cv1k_map)
444	435	MCFG_CPU_IO_MAP(cv1k_port)
445	436	MCFG_DEVICE_VBLANK_INT_DRIVER("screen", cv1k_state, cv1k_interrupt)
r31221	r31222
473	464	MCFG_DEVICE_REMOVE("maincpu")
474	465
475	466	MCFG_CPU_ADD("maincpu", SH3BE, CPU_CLOCK)
476		MCFG_CPU_CONFIG(sh4cpu_config)
	467	MCFG_SH4_MD0(0)  // none of this is verified
	468	MCFG_SH4_MD1(0)  // (the sh3 is different to the sh4 anyway, should be changed)
	469	MCFG_SH4_MD2(0)
	470	MCFG_SH4_MD3(0)
	471	MCFG_SH4_MD4(0)
	472	MCFG_SH4_MD5(1)
	473	MCFG_SH4_MD6(0)
	474	MCFG_SH4_MD7(1)
	475	MCFG_SH4_MD8(0)
	476	MCFG_SH4_CLOCK(CPU_CLOCK)
477	477	MCFG_CPU_PROGRAM_MAP(cv1k_d_map)
478	478	MCFG_CPU_IO_MAP(cv1k_port)
479	479	MCFG_DEVICE_VBLANK_INT_DRIVER("screen", cv1k_state, cv1k_interrupt)

trunk/src/mame/drivers/aristmk6.c

r31221	r31222
130	130	// ?
131	131	#define ARISTMK6_CPU_CLOCK XTAL_200MHz
132	132	// ?
133		static const struct sh4_config sh4cpu_config = {  1,  0,  1,  0,  0,  0,  1,  1,  0, ARISTMK6_CPU_CLOCK };
134	133
135	134	static MACHINE_CONFIG_START( aristmk6, aristmk6_state )
136	135	/* basic machine hardware */
137	136	MCFG_CPU_ADD("maincpu", SH4LE, ARISTMK6_CPU_CLOCK)
138		MCFG_CPU_CONFIG(sh4cpu_config)
	137	MCFG_SH4_MD0(1)
	138	MCFG_SH4_MD1(0)
	139	MCFG_SH4_MD2(1)
	140	MCFG_SH4_MD3(0)
	141	MCFG_SH4_MD4(0)
	142	MCFG_SH4_MD5(1)
	143	MCFG_SH4_MD6(0)
	144	MCFG_SH4_MD7(1)
	145	MCFG_SH4_MD8(0)
	146	MCFG_SH4_CLOCK(ARISTMK6_CPU_CLOCK)
139	147	MCFG_CPU_PROGRAM_MAP(aristmk6_map)
140	148	MCFG_CPU_IO_MAP(aristmk6_port)
141	149	//  MCFG_DEVICE_DISABLE()

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