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r31217 Monday 7th July, 2014 at 15:01:52 UTC by Carl
(mess) rmnimbus: fix and simplify more drawing code (nw)

[src/emu/bus/isa]	dectalk.c
[src/emu/cpu/i86]	i186.c i186.h
[src/mess/drivers]	rmnimbus.c
[src/mess/includes]	rmnimbus.h
[src/mess/machine]	rmnimbus.c
[src/mess/video]	rmnimbus.c

trunk/src/emu/cpu/i86/i186.h

r31216	r31217
88	88
89	89	struct dma_state
90	90	{
91		bool        drq_delay;
92	91	bool        drq_state;
93	92	UINT32      source;
94	93	UINT32      dest;
r31216	r31217
117	116	static const device_timer_id TIMER_TIME0 = 3;
118	117	static const device_timer_id TIMER_TIME1 = 4;
119	118	static const device_timer_id TIMER_TIME2 = 5;
120		static const device_timer_id TIMER_DMA0 = 6;
121		static const device_timer_id TIMER_DMA1 = 7;
122	119
123	120	struct timer_state  m_timer[3];
124	121	struct dma_state    m_dma[2];

trunk/src/emu/cpu/i86/i186.c

r31216	r31217
10	10	#define LOG_INTERRUPTS      0
11	11	#define LOG_INTERRUPTS_EXT  0
12	12	#define LOG_TIMER           0
13		#define LOG_OPTIMIZATION    0
14	13	#define LOG_DMA             0
15		#define CPU_RESUME_TRIGGER  7123
16	14
17	15	/* external int priority masks */
18	16
r31216	r31217
608	606	m_timer[0].time_timer = timer_alloc(TIMER_TIME0);
609	607	m_timer[1].time_timer = timer_alloc(TIMER_TIME1);
610	608	m_timer[2].time_timer = timer_alloc(TIMER_TIME2);
611		m_dma[0].finish_timer = timer_alloc(TIMER_DMA0);
612		m_dma[1].finish_timer = timer_alloc(TIMER_DMA1);
613	609
614	610	m_out_tmrout0_func.resolve_safe();
615	611	m_out_tmrout1_func.resolve_safe();
r31216	r31217
637	633	m_intr.status            = 0x0000;
638	634	m_intr.poll_status       = 0x0000;
639	635	m_reloc = 0x20ff;
640		m_dma[0].drq_delay = false;
641		m_dma[1].drq_delay = false;
642	636	m_dma[0].drq_state = false;
643	637	m_dma[1].drq_state = false;
644	638	for(int i = 0; i < ARRAY_LENGTH(m_timer); ++i)
r31216	r31217
647	641	m_timer[i].time_timer_active = 0;
648	642	m_timer[i].maxA = 0;
649	643	m_timer[i].maxB = 0;
	644	m_timer[i].count = 0;
650	645	}
651	646	}
652	647
r31216	r31217
826	821
827	822	/* check external interrupts */
828	823	for (IntNo = 0; IntNo < 4; IntNo++)
	824	{
829	825	if ((m_intr.ext[IntNo] & 0x0F) == Priority)
830	826	{
831	827	if (LOG_INTERRUPTS)
r31216	r31217
838	834	/* if there's something pending, generate an interrupt */
839	835	if (m_intr.request & (0x10 << IntNo))
840	836	{
	837	if((IntNo >= 2) && (m_intr.ext[IntNo - 2] & EXTINT_CTRL_CASCADE))
	838	{
	839	logerror("i186: %06x: irq %d use when set for cascade mode\n", pc(), IntNo);
	840	m_intr.request &= ~(0x10 << IntNo);
	841	continue;
	842	}
841	843	/* otherwise, generate an interrupt for this request */
842	844	new_vector = 0x0c + IntNo;
843	845
r31216	r31217
845	847	m_intr.ack_mask = 0x0010 << IntNo;
846	848	goto generate_int;
847	849	}
	850	else if ((m_intr.in_service & (0x10 << IntNo)) && (m_intr.ext[IntNo] & EXTINT_CTRL_SFNM))
	851	return; // if an irq is in service and sfnm is enabled, stop here
848	852	}
	853	}
849	854	}
850	855	return;
851	856
r31216	r31217
855	860	if (!m_intr.pending)
856	861	set_input_line(0, ASSERT_LINE);
857	862	m_intr.pending = 1;
858		machine().scheduler().trigger(CPU_RESUME_TRIGGER);
859		if (LOG_OPTIMIZATION) logerror("  - trigger due to interrupt pending\n");
860	863	if (LOG_INTERRUPTS) logerror("(%f) **** Requesting interrupt vector %02X\n", machine().time().as_double(), new_vector);
861	864	}
862	865
r31216	r31217
920	923	}
921	924	}
922	925	}
	926	update_interrupt_state();
923	927	}
924	928
925	929	/* Trigger an external interrupt, optionally supplying the vector to take */
r31216	r31217
928	932	if (LOG_INTERRUPTS_EXT) logerror("generating external int %02X, vector %02X\n",intno,vector);
929	933
930	934	if(!state)
931		return;
	935	{
	936	m_intr.request &= ~(0x010 << intno);
	937	m_intr.ack_mask &= ~(0x0010 << intno);
	938	}
	939	else // Turn on the requested request bit and handle interrupt
	940	m_intr.request |= (0x010 << intno);
932	941
933		// Turn on the requested request bit and handle interrupt
934		m_intr.request |= (0x010 << intno);
935	942	update_interrupt_state();
936	943	}
937	944
r31216	r31217
1015	1022	t->int_timer->adjust(attotime::never, which);
1016	1023	break;
1017	1024	}
1018		case TIMER_DMA0:
1019		case TIMER_DMA1:
1020		{
1021		int which = param;
1022		struct dma_state *d = &m_dma[which];
1023
1024		d->drq_delay = false;
1025		if(d->drq_state)
1026		drq_callback(which);
1027		break;
1028		}
1029	1025	case TIMER_TIME0:
1030	1026	case TIMER_TIME1:
1031	1027	case TIMER_TIME2:
r31216	r31217
1227	1223	UINT8   dma_byte;
1228	1224	UINT8   incdec_size;
1229	1225
1230		if(dma->drq_delay)
1231		return;
1232
1233	1226	if (LOG_DMA>1)
1234	1227	logerror("Control=%04X, src=%05X, dest=%05X, count=%04X\n",dma->control,dma->source,dma->dest,dma->count);
1235	1228
r31216	r31217
1282	1275	dma->count -= 1;
1283	1276
1284	1277	// Terminate if count is zero, and terminate flag set
1285		if((dma->control & TERMINATE_ON_ZERO) && (dma->count==0))
	1278	if(((dma->control & TERMINATE_ON_ZERO) || !(dma->control & SYNC_MASK)) && (dma->count==0))
1286	1279	{
1287	1280	dma->control &= ~ST_STOP;
1288	1281	if (LOG_DMA) logerror("DMA terminated\n");
r31216	r31217
1295	1288	m_intr.request |= 0x04 << which;
1296	1289	update_interrupt_state();
1297	1290	}
1298
1299		//  dma->finish_timer->adjust(attotime::from_hz(clock()/8), 0);
1300		//  dma->drq_delay = true;
1301	1291	}
1302	1292
1303	1293	READ16_MEMBER(i80186_cpu_device::internal_port_r)

trunk/src/emu/bus/isa/dectalk.c

r31216	r31217
39	39
40	40	READ8_MEMBER(dectalk_isa_device::dma_r)
41	41	{
	42	m_cpu->drq1_w(0);
42	43	return m_dma;
43	44	}
44	45
45	46	WRITE8_MEMBER(dectalk_isa_device::dma_w)
46	47	{
	48	m_cpu->drq1_w(0);
47	49	m_dma = data;
48	50	}
49	51
r31216	r31217
71	73	READ16_MEMBER(dectalk_isa_device::dsp_dma_r)
72	74	{
73	75	m_bio = ASSERT_LINE;
	76	m_cpu->drq1_w(0);
74	77	return m_dsp_dma;
75	78	}
76	79

trunk/src/mess/includes/rmnimbus.h

r31216	r31217
20	20	#define MAINCPU_TAG "maincpu"
21	21	#define IOCPU_TAG   "iocpu"
22	22
23		#define SCREEN_WIDTH_PIXELS     640
24		#define SCREEN_HEIGHT_LINES     250
25		#define SCREEN_NO_COLOURS       16
26
27		#define NO_VIDREGS              (0x30/2)
28
29
30	23	/* Nimbus specific */
31	24
32	25	/* External int vectors for chained interupts */
r31216	r31217
191	184	UINT8 m_last_playmode;
192	185	UINT8 m_ay8910_a;
193	186	UINT8 m_sio_int_state;
194		UINT16 m_vidregs[NO_VIDREGS];
195		UINT8 m_bpp;
196		UINT16 m_pixel_mask;
197		UINT8 m_hs_count;
	187	UINT16 m_vidregs[24];
	188	UINT16 m_x, m_y;
198	189	UINT32 m_debug_video;
199	190	UINT8 m_vector;
200	191	UINT8 m_eeprom_bits;
r31216	r31217
202	193
203	194	DECLARE_READ8_MEMBER(nimbus_mcu_r);
204	195	DECLARE_WRITE8_MEMBER(nimbus_mcu_w);
205		DECLARE_READ16_MEMBER(nimbus_io_r);
206		DECLARE_WRITE16_MEMBER(nimbus_io_w);
207	196	DECLARE_READ8_MEMBER(scsi_r);
208	197	DECLARE_WRITE8_MEMBER(scsi_w);
209	198	DECLARE_WRITE8_MEMBER(fdc_ctl_w);
r31216	r31217
225	214	virtual void machine_reset();
226	215	virtual void video_start();
227	216	virtual void video_reset();
228		DECLARE_PALETTE_INIT(rmnimbus);
229	217	UINT32 screen_update_nimbus(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
230	218	DECLARE_WRITE_LINE_MEMBER(sio_interrupt);
231	219	DECLARE_WRITE_LINE_MEMBER(nimbus_fdc_intrq_w);
r31216	r31217
241	229	DECLARE_WRITE_LINE_MEMBER(write_scsi_iena);
242	230
243	231	UINT8 get_pixel(UINT16 x, UINT16 y);
244		UINT16 read_pixel_line(UINT16 x, UINT16 y, UINT8 width);
	232	UINT16 read_pixel_line(UINT16 x, UINT16 y, UINT8 pixels, UINT8 bpp);
245	233	UINT16 read_pixel_data(UINT16 x, UINT16 y);
246	234	void set_pixel(UINT16 x, UINT16 y, UINT8 colour);
247	235	void set_pixel40(UINT16 x, UINT16 y, UINT8 colour);
248		void write_pixel_line(UINT16 x, UINT16 y, UINT16    data, UINT8 width);
249		void move_pixel_line(UINT16 x, UINT16 y, UINT16    data, UINT8 width);
	236	void write_pixel_line(UINT16 x, UINT16 y, UINT16, UINT8 pixels, UINT8 bpp);
	237	void move_pixel_line(UINT16 x, UINT16 y, UINT8 width);
250	238	void write_pixel_data(UINT16 x, UINT16 y, UINT16    data);
251	239	void write_reg_004();
252	240	void write_reg_006();
	241	void write_reg_00A();
	242	void write_reg_00E();
253	243	void write_reg_010();
254	244	void write_reg_012();
255	245	void write_reg_014();
r31216	r31217
258	248	void write_reg_01C();
259	249	void write_reg_01E();
260	250	void write_reg_026();
261		void change_palette(UINT8 bank, UINT16 colours, UINT8 regno);
	251	void change_palette(UINT8 bank, UINT16 colours);
262	252	void external_int(UINT16 intno, UINT8 vector);
263	253	DECLARE_READ8_MEMBER(cascade_callback);
264	254	void *get_dssi_ptr(address_space &space, UINT16   ds, UINT16 si);
r31216	r31217
271	261	void hdc_post_rw();
272	262	void hdc_drq();
273	263	void pc8031_reset();
274		void ipc_dumpregs();
	264	//void ipc_dumpregs();
275	265	void iou_reset();
276	266	void rmni_sound_reset();
277	267	void mouse_js_reset();

trunk/src/mess/video/rmnimbus.c

r31216	r31217
28	28
29	29
30	30	#define WIDTH_MASK      0x07
31		#define XOR_MASK        0x08
32		#define MASK_4080       0x10
33	31
34	32	// Offsets of nimbus video registers within register array
35	33
r31216	r31217
60	58
61	59	#define FG_COLOUR       (m_vidregs[reg024]&0x0F)
62	60	#define BG_COLOUR       ((m_vidregs[reg024]&0xF0)>>4)
	61	#define SELECT_COL(x,c)   (IS_80COL ? ((((x) & 1) ? ((c) << 2) : (c)) & 0xC) : (c))
	62	#define FILL_WORD(c)   (((c) << 12) | ((c) << 8) | ((c) << 4) | (c))
63	63
64		#define IS_80COL        (m_vidregs[reg026]&MASK_4080)
65		#define IS_XOR          (m_vidregs[reg022]&XOR_MASK)
	64	#define IS_80COL        (m_vidregs[reg026]&0x10)
	65	#define IS_XOR          (m_vidregs[reg022]&8)
66	66
67	67	#define DEBUG_TEXT  0x01
68	68	#define DEBUG_DB    0x02
r31216	r31217
71	71	#define DEBUG_SET(flags)    ((m_debug_video & (flags))==(flags))
72	72
73	73	static void video_debug(running_machine &machine, int ref, int params, const char *param[]);
74		static void video_regdump(running_machine &machine, int ref, int params, const char *param[]);
75	74
76	75	/*
77	76	I'm not sure which of thes return values on a real machine, so for the time being I'm going
r31216	r31217
85	84
86	85	switch (offset)
87	86	{
88		case    reg000  : result=m_vidregs[reg000]; break;
	87	case    reg000  : result=read_pixel_data(m_vidregs[reg002],m_vidregs[reg00C]); break;
89	88	case    reg002  : result=m_vidregs[reg002]; break;
90	89	case    reg004  : result=read_pixel_data(m_vidregs[reg002],++m_vidregs[reg00C]); break;
91	90	case    reg006  : result=m_vidregs[reg006]; break;
r31216	r31217
94	93	case    reg00C  : result=m_vidregs[reg00C]; break;
95	94	case    reg00E  : result=m_vidregs[reg00E]; break;
96	95
97		case    reg010  : result=m_vidregs[reg010]; break;
	96	case    reg010  : result=read_pixel_data(m_vidregs[reg002],m_vidregs[reg00C]); break;
98	97	case    reg012  : result=m_vidregs[reg012]; break;
99	98	case    reg014  : result=m_vidregs[reg014]; break;
100	99	case    reg016  : result=m_vidregs[reg016]; break;
101	100	case    reg018  : result=m_vidregs[reg018]; break;
102		case    reg01A  : result=m_vidregs[reg01A]; break;
	101	case    reg01A  : result=read_pixel_data(++m_vidregs[reg002],m_vidregs[reg00C]); break;
103	102	case    reg01C  : result=m_vidregs[reg01C]; break;
104	103	case    reg01E  : result=m_vidregs[reg01E]; break;
105	104
r31216	r31217
108	107	case    reg024  : result=m_vidregs[reg024]; break;
109	108	case    reg026  : result=m_vidregs[reg026]; break;
110	109	case    reg028  : result=m_screen->vpos() % 0xb; break; //result=m_vidregs[reg028]; break;
111		case    reg02A  : result=m_vidregs[reg02A]; break;
112		case    reg02C  : result=m_vidregs[reg02C]; break;
	110	case    reg02A  : result=m_vidregs[reg002]; break;
	111	case    reg02C  : result=m_vidregs[reg00C]; break;
113	112	case    reg02E  : result=m_vidregs[reg02E]; break;
114	113	default         : result=0; break;
115	114	}
r31216	r31217
124	123	{
125	124	UINT8   result = 0;
126	125
127		if((x<SCREEN_WIDTH_PIXELS) && (y<SCREEN_HEIGHT_LINES))
	126	if((x<640) && (y<250))
128	127	{
129	128	if(IS_80COL)
130		result=m_video_mem.pix16(y, x);
	129	result=m_video_mem.pix16(y, x) >> 2;
131	130	else
132	131	result=m_video_mem.pix16(y, x*2);
133	132	}
r31216	r31217
135	134	return result;
136	135	}
137	136
138		UINT16 rmnimbus_state::read_pixel_line(UINT16 x, UINT16 y, UINT8 width)
	137	UINT16 rmnimbus_state::read_pixel_line(UINT16 x, UINT16 y, UINT8 pixels, UINT8 bpp)
139	138	{
140		UINT16  result = 0;
141		UINT16  mask;
142		UINT16  pixel_x;
143		UINT16  colour;
144		UINT8   shifts;
	139	UINT16 colour = 0;
	140	int i;
	141	x *= pixels;
145	142
146	143	if(DEBUG_SET(DEBUG_TEXT | DEBUG_PIXEL))
147		logerror("read_pixel_line(x=%04X, y=%04X, width=%02X, bpp=%02X, pixel_mask=%02X)\n",x,y,width,m_bpp,m_pixel_mask);
	144	logerror("read_pixel_line(x=%d, y=%d, width=%d, bpp=%d)\n",x,y,pixels,bpp);
148	145
149		shifts=width-m_bpp;
150
151		for(mask=m_pixel_mask, pixel_x=(x*(width/m_bpp)); mask>0; mask=(mask>>m_bpp), pixel_x++)
	146	for(i = 0; i < pixels - 1; i++)
152	147	{
153		colour=get_pixel(pixel_x,y);
	148	colour |= get_pixel(i + x, y);
154	149
155		if(m_bpp==1)
156		colour=((colour==FG_COLOUR) ? 1 : 0) << shifts;
	150	if(bpp==1)
	151	colour=((colour==SELECT_COL(x + i, FG_COLOUR)) ? 1 : 0) << 1;
157	152	else
158		colour=colour << shifts;
159
160		result=(result & ~mask)  | colour;
161
162		shifts-=m_bpp;
	153	colour <<= bpp;
163	154	}
164
165		return result;
	155	return colour | get_pixel(x + i, y);
166	156	}
167	157
168	158	UINT16 rmnimbus_state::read_pixel_data(UINT16 x, UINT16 y)
r31216	r31217
170	160	UINT16  result=0;
171	161
172	162	if(DEBUG_SET(DEBUG_TEXT | DEBUG_PIXEL))
173		logerror("read_pixel_data(x=%04X, y=%04X), reg022=%04X\n",x,y,m_vidregs[reg022]);
	163	logerror("read_pixel_data(x=%d, y=%d), reg022=%04X\n",x,y,m_vidregs[reg022]);
174	164
175	165	if(IS_80COL)
176	166	{
r31216	r31217
184	174
185	175	case 0x03   : break;
186	176
187		case 0x04   : m_bpp=2; m_pixel_mask=0xC0;
188		result=read_pixel_line(x,y,8);
189		break;
	177	case 0x04   :
	178	result=read_pixel_line(x,y,4,2);
	179	break;
190	180
191	181	case 0x05   : break;
192	182
193		case 0x06   : m_bpp=2; m_pixel_mask=0xC000;
194		result=read_pixel_line(x,y,16);
195		break;
	183	case 0x06   :
	184	result=read_pixel_line(x,y,8,2);
	185	break;
196	186
197	187	case 0x07   : break;
198	188	}
r31216	r31217
213	203
214	204	case 0x05   : break;
215	205
216		case 0x06   : m_bpp=4; m_pixel_mask=0xF000;
217		result=read_pixel_line(x,y,16);
218		break;
	206	case 0x06   :
	207	result=read_pixel_line(x,y,4,4);
	208	break;
219	209
220	210	case 0x07   : break;
221	211	}
r31216	r31217
254	244	case    reg004  : m_vidregs[reg004]=data; write_reg_004(); break;
255	245	case    reg006  : m_vidregs[reg006]=data; write_reg_006(); break;
256	246	case    reg008  : m_vidregs[reg008]=data; break;
257		case    reg00A  : m_vidregs[reg00A]=data; break;
	247	case    reg00A  : m_vidregs[reg00A]=data; write_reg_00A(); break;
258	248	case    reg00C  : m_vidregs[reg00C]=data; break;
259		case    reg00E  : m_vidregs[reg00E]=data; break;
	249	case    reg00E  : m_vidregs[reg00E]=data; write_reg_00E(); break;
260	250
261	251	case    reg010  : m_vidregs[reg010]=data; write_reg_010(); break;
262	252	case    reg012  : m_vidregs[reg012]=data; write_reg_012(); break;
r31216	r31217
271	261	case    reg022  : m_vidregs[reg022]=data; break;
272	262	case    reg024  : m_vidregs[reg024]=data; break;
273	263	case    reg026  : m_vidregs[reg026]=data; write_reg_026(); break;
274		case    reg028  : change_palette(0,data,reg028); break;
275		case    reg02A  : change_palette(1,data,reg02A); break;
276		case    reg02C  : change_palette(2,data,reg02C); break;
277		case    reg02E  : change_palette(3,data,reg02E); break;
	264	case    reg028  : change_palette(0,data); break;
	265	case    reg02A  : change_palette(1,data); break;
	266	case    reg02C  : change_palette(2,data); break;
	267	case    reg02E  : change_palette(3,data); break;
278	268
279	269	default         : break;
280	270	}
r31216	r31217
283	273	void rmnimbus_state::set_pixel(UINT16 x, UINT16 y, UINT8 colour)
284	274	{
285	275	if(DEBUG_SET(DEBUG_TEXT | DEBUG_PIXEL))
286		logerror("set_pixel(x=%04X, y=%04X, colour=%04X), IS_XOR=%02X\n",x,y,colour,IS_XOR);
	276	logerror("set_pixel(x=%d, y=%d, colour=%04X), IS_XOR=%02X\n",x,y,colour,IS_XOR);
287	277
288		if(IS_80COL)
289		colour&=0x03;
290
291		if((x<SCREEN_WIDTH_PIXELS) && (y<SCREEN_HEIGHT_LINES))
	278	if((x<640) && (y<250))
292	279	{
293	280	if(IS_XOR)
294	281	m_video_mem.pix16(y, x)^=colour;
r31216	r31217
303	290	set_pixel((x*2)+1,y,colour);
304	291	}
305	292
306		void rmnimbus_state::write_pixel_line(UINT16 x, UINT16 y, UINT16    data, UINT8 width)
	293	void rmnimbus_state::write_pixel_line(UINT16 x, UINT16 y, UINT16 data, UINT8 pixels, UINT8 bpp)
307	294	{
308		UINT16  mask;
309		UINT16  pixel_x;
310		UINT16  colour;
311		UINT8   shifts;
	295	UINT8 colour;
	296	UINT8 mask = (1 << bpp) - 1;
	297	x *= pixels;
312	298
313	299	if(DEBUG_SET(DEBUG_TEXT | DEBUG_PIXEL))
314		logerror("write_pixel_line(x=%04X, y=%04X, data=%04X, width=%02X, bpp=%02X, pixel_mask=%02X)\n",x,y,data,width,m_bpp,m_pixel_mask);
	300	logerror("write_pixel_line(x=%d, y=%d, data=%04X, width=%d, bpp=%d)\n",x,y,data,pixels,bpp);
315	301
316		shifts=width-m_bpp;
317
318		for(mask=m_pixel_mask, pixel_x=(x*(width/m_bpp)); mask>0; mask=(mask>>m_bpp), pixel_x++)
	302	for(int i = (pixels - 1); i >= 0; i--)
319	303	{
320		if(m_bpp==1)
321		colour=(data & mask) ? FG_COLOUR : BG_COLOUR;
	304	if(bpp==1)
	305	colour = SELECT_COL(x + i, (data & 1) ? FG_COLOUR : BG_COLOUR);
	306	else if(IS_80COL)
	307	colour = (data & mask) << 2;
322	308	else
323		colour=(data & mask) >> shifts;
	309	colour = (data & mask);
324	310
325		//logerror("write_pixel_line: data=%04X, mask=%04X, shifts=%02X, bpp=%02X colour=%02X\n",data,mask,shifts,m_bpp,colour);
326
327	311	if(IS_80COL)
328		set_pixel(pixel_x,y,colour);
	312	set_pixel(x + i,y,colour);
329	313	else
330		set_pixel40(pixel_x,y,colour);
	314	set_pixel40(x + i,y,colour);
331	315
332		shifts-=m_bpp;
	316	data >>= bpp;
333	317	}
334	318	}
335	319
336		void rmnimbus_state::move_pixel_line(UINT16 x, UINT16 y, UINT16    data, UINT8 width)
	320	void rmnimbus_state::move_pixel_line(UINT16 x, UINT16 y, UINT8 pixels)
337	321	{
338		UINT16  pixelno;
339		UINT16  pixelx;
340
	322	x *= pixels;
341	323	if(DEBUG_SET(DEBUG_TEXT | DEBUG_PIXEL))
342		logerror("move_pixel_line(x=%04X, y=%04X, data=%04X, width=%02X)\n",x,y,data,width);
	324	logerror("move_pixel_line(x=%d, y=%d, width=%d)\n",x,y,pixels);
343	325
344		for(pixelno=0;pixelno<width;pixelno++)
	326	for(int i = 0; i < pixels; i++)
345	327	{
346		pixelx=(x*width)+pixelno;
347	328	if(DEBUG_SET(DEBUG_TEXT | DEBUG_PIXEL))
348		logerror("pixelx=%04X\n",pixelx);
349		m_video_mem.pix16(m_vidregs[reg020], pixelx)=m_video_mem.pix16(y, pixelx);
	329	logerror("x=%d\n",x + i);
	330	m_video_mem.pix16(m_vidregs[reg020], x + i) = m_video_mem.pix16(y, x + i);
350	331	}
351	332	}
352	333
r31216	r31217
380	361	void rmnimbus_state::write_pixel_data(UINT16 x, UINT16 y, UINT16    data)
381	362	{
382	363	if(DEBUG_SET(DEBUG_TEXT | DEBUG_PIXEL))
383		logerror("write_pixel_data(x=%04X, y=%04X, data=%04X), reg022=%04X\n",x,y,data,m_vidregs[reg022]);
	364	logerror("write_pixel_data(x=%d, y=%d, data=%04X), reg022=%04X\n",x,y,data,m_vidregs[reg022]);
384	365
385	366	if(IS_80COL)
386	367	{
387	368	switch (m_vidregs[reg022] & WIDTH_MASK)
388	369	{
389		case 0x00   : m_bpp=1; m_pixel_mask=0x8000;
390		write_pixel_line(x,y,data,16);
391		break;
	370	case 0x00:
	371	write_pixel_line(x,y,data,16,1);
	372	break;
392	373
393		case 0x01   : m_bpp=1; m_pixel_mask=0x80;
394		write_pixel_line(x,y,data,8);
395		break;
	374	case 0x01:
	375	write_pixel_line(x,y,data,8,1);
	376	break;
396	377
397		case 0x02   : m_bpp=1; m_pixel_mask=0x0080;
398		write_pixel_line(x,y,data,8);
399		break;
	378	case 0x02:
	379	write_pixel_line(x,y,data,8,1);
	380	break;
400	381
401		case 0x03   : m_bpp=1;
402		set_pixel(x,y,FG_COLOUR);
403		break;
	382	case 0x03:
	383	set_pixel(x,y,SELECT_COL(x, FG_COLOUR));
	384	break;
404	385
405		case 0x04   : m_bpp=2; m_pixel_mask=0xC0;
406		write_pixel_line(x,y,(((data & 0xFF00)>>8) & (data & 0xFF)) | (~((data & 0xFF00)>>8) & read_pixel_line(x,y,8)),8);
407		break;
	386	case 0x04:
	387	write_pixel_line(x,y,(((data & 0xFF00)>>8) & (data & 0xFF)) | (~((data & 0xFF00)>>8) & read_pixel_line(x,y,4,2)),4,2);
	388	break;
408	389
409		case 0x05   : move_pixel_line(x,y,data,16);
410		break;
	390	case 0x05:
	391	move_pixel_line(x,y,16);
	392	break;
411	393
412		case 0x06   : m_bpp=2; m_pixel_mask=0xC000;
413		write_pixel_line(x,y,data,16);
414		break;
	394	case 0x06:
	395	write_pixel_line(x,y,data,8,2);
	396	break;
415	397
416		case 0x07   : m_bpp=1;
417		set_pixel(x,y,FG_COLOUR);
418		break;
	398	case 0x07:
	399	set_pixel(x,y,SELECT_COL(x, FG_COLOUR));
	400	break;
419	401	}
420	402	}
421	403	else /* 40 Col */
422	404	{
423	405	switch (m_vidregs[reg022] & WIDTH_MASK)
424	406	{
425		case 0x00   : m_bpp=1; m_pixel_mask=0x0080;
426		write_pixel_line(x,y,data,8);
427		break;
	407	case 0x00:
	408	write_pixel_line(x,y,data,8,1);
	409	break;
428	410
429		case 0x01   : m_bpp=2; m_pixel_mask=0xC0;
430		write_pixel_line(x,y,data,8);
431		break;
	411	case 0x01:
	412	write_pixel_line(x,y,data,4,2);
	413	break;
432	414
433		case 0x02   : m_bpp=1; m_pixel_mask=0x0080;
434		set_pixel40(x,y,FG_COLOUR);
435		break;
	415	case 0x02:
	416	set_pixel40(x,y,FG_COLOUR);
	417	break;
436	418
437		case 0x03   : m_bpp=1;
438		set_pixel(x,y,FG_COLOUR);
439		break;
	419	case 0x03:
	420	set_pixel(x,y,FG_COLOUR);
	421	break;
440	422
441		case 0x04   : m_bpp=4; m_pixel_mask=0xF0;
442		write_pixel_line(x,y,(((data & 0xFF00)>>8) & (data & 0xFF)) | (~((data & 0xFF00)>>8) & read_pixel_line(x,y,8)),8);
443		break;
	423	case 0x04:
	424	write_pixel_line(x,y,(((data & 0xFF00)>>8) & (data & 0xFF)) | (~((data & 0xFF00)>>8) & read_pixel_line(x,y,2,4)),2,4);
	425	break;
444	426
445		case 0x05   : move_pixel_line(x,y,data,16);
446		break;
	427	case 0x05:
	428	move_pixel_line(x,y,16);
	429	break;
447	430
448		case 0x06   : m_bpp=4; m_pixel_mask=0xF000;
449		write_pixel_line(x,y,data,16);
450		break;
	431	case 0x06:
	432	write_pixel_line(x,y,data,4,4);
	433	break;
451	434
452		case 0x07   : m_bpp=1;
453		set_pixel(x,y,FG_COLOUR);
454		break;
	435	case 0x07:
	436	set_pixel(x,y,FG_COLOUR);
	437	break;
455	438	}
456	439	}
457	440	}
458	441
459	442	void rmnimbus_state::write_reg_004()
460	443	{
461		m_vidregs[reg002]=0;
	444	//m_vidregs[reg002]=0;
462	445	m_vidregs[reg00C]++;
463	446	}
464	447
r31216	r31217
468	451	m_vidregs[reg002]=m_vidregs[reg006];
469	452	}
470	453
	454	void rmnimbus_state::write_reg_00A()
	455	{
	456	m_vidregs[reg002]++;
	457	}
	458
	459	void rmnimbus_state::write_reg_00E()
	460	{
	461	m_vidregs[reg002]++;
	462	m_vidregs[reg00C]=m_vidregs[reg00E];
	463	}
	464
471	465	void rmnimbus_state::write_reg_010()
472	466	{
473	467	write_pixel_data(m_vidregs[reg002],m_vidregs[reg00C],m_vidregs[reg010]);
r31216	r31217
480	474	// work correctly.
481	475	m_vidregs[reg002]=m_vidregs[reg012];
482	476
483		write_pixel_data(m_vidregs[reg012],m_vidregs[reg00C],FG_COLOUR);
	477	write_pixel_data(m_vidregs[reg012],m_vidregs[reg00C],FILL_WORD(FG_COLOUR));
484	478	}
485	479
486	480	void rmnimbus_state::write_reg_014()
r31216	r31217
492	486	{
493	487	m_vidregs[reg002]=m_vidregs[reg016];
494	488
495		write_pixel_data(m_vidregs[reg002],++m_vidregs[reg00C],FG_COLOUR);
	489	write_pixel_data(m_vidregs[reg002],++m_vidregs[reg00C],FILL_WORD(FG_COLOUR));
496	490	}
497	491
498	492
r31216	r31217
508	502	// and others using the standard RM box menus) work correctly.
509	503	m_vidregs[reg00C]=m_vidregs[reg01C];
510	504
511		write_pixel_data(m_vidregs[reg002],m_vidregs[reg01C],FG_COLOUR);
	505	write_pixel_data(m_vidregs[reg002],m_vidregs[reg01C],FILL_WORD(FG_COLOUR));
512	506	}
513	507
514	508	void rmnimbus_state::write_reg_01E()
515	509	{
516	510	m_vidregs[reg00C]=m_vidregs[reg01E];
517	511
518		write_pixel_data(++m_vidregs[reg002],m_vidregs[reg00C],FG_COLOUR);
	512	write_pixel_data(++m_vidregs[reg002],m_vidregs[reg00C],FILL_WORD(FG_COLOUR));
519	513	}
520	514
521	515	/*
r31216	r31217
529	523	logerror("reg 026 write, border_colour=%02X\n",m_vidregs[reg026] & 0x0F);
530	524	}
531	525
532		void rmnimbus_state::change_palette(UINT8 bank, UINT16 colours, UINT8 regno)
	526	void rmnimbus_state::change_palette(UINT8 bank, UINT16 colours)
533	527	{
534		UINT8   colourno;
535		UINT16  mask;
536		UINT8   shifts;
537		UINT8   colourmax;
538		UINT8   first;
539
540		// for the register's data has changed update it, and then update the pallette, else do nothing.
541		if(m_vidregs[regno]!=colours)
542		m_vidregs[regno]=colours;
543		else
544		return;
545
546		// Setup parameters for pallette change
547		colourmax=IS_80COL ? 1 : 4;
548		first=IS_80COL ? bank : bank*4;
549
550		shifts=0;
551		mask=0x000F;
552
553	528	// loop over changing colours
554		for(colourno=first; colourno<(first+colourmax); colourno++)
	529	for(int colourno = (bank * 4); colourno < ((bank + 1) * 4); colourno++)
555	530	{
556		int paletteidx=(colours & mask) >> shifts;
557		int i = (paletteidx & 8) >> 3;
558		m_palette->set_pen_color(colourno, pal2bit((paletteidx & 2) | i), pal2bit(((paletteidx & 4) >> 1) | i), pal2bit(((paletteidx & 1) << 1) | i));
	531	int i = (colours & 8) >> 3;
	532	m_palette->set_pen_color(colourno, pal2bit((colours & 2) | i), pal2bit(((colours & 4) >> 1) | i), pal2bit(((colours & 1) << 1) | i));
559	533
560	534	if(DEBUG_SET(DEBUG_TEXT))
561		logerror("set colourno[%02X], paletteidx=%02X\n",colourno, paletteidx);
562		mask=mask<<4;
563		shifts+=4;
	535	logerror("set colourno[%02X], colour=%02X\n",colourno, colours);
	536	colours >>= 4;
564	537	}
565	538	}
566	539
r31216	r31217
578	551	}
579	552	}
580	553
581		static void video_regdump(running_machine &machine, int ref, int params, const char *param[])
582		{
583		rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
584		int regno;
585
586		for(regno=0;regno<0x08;regno++)
587		{
588		debug_console_printf(machine,"reg%03X=%04X reg%03X=%04X reg%03X=%04X\n",
589		regno*2,state->m_vidregs[regno],
590		(regno+0x08)*2,state->m_vidregs[regno+0x08],
591		(regno+0x10)*2,state->m_vidregs[regno+0x10]);
592
593		logerror("reg%03X=%04X reg%03X=%04X reg%03X=%04X\n",
594		regno*2,state->m_vidregs[regno],
595		(regno+0x08)*2,state->m_vidregs[regno+0x08],
596		(regno+0x10)*2,state->m_vidregs[regno+0x10]);
597		}
598		}
599
600	554	void rmnimbus_state::video_start()
601	555	{
602	556	m_debug_video=0;
603	557
604		logerror("video_start\n");
605
606	558	m_screen->register_screen_bitmap(m_video_mem);
607	559
608	560	save_item(NAME(m_vidregs));
r31216	r31217
610	562	if (machine().debug_flags & DEBUG_FLAG_ENABLED)
611	563	{
612	564	debug_console_register_command(machine(), "nimbus_vid_debug", CMDFLAG_NONE, 0, 0, 1, video_debug);
613		debug_console_register_command(machine(), "nimbus_vid_regdump", CMDFLAG_NONE, 0, 0, 1, video_regdump);
614	565	}
615	566	}
616	567
617		PALETTE_INIT_MEMBER(rmnimbus_state, rmnimbus)
618		{
619		int colourno;
620
621		for ( colourno = 0; colourno < SCREEN_NO_COLOURS; colourno++ )
622		{
623		int i = (colourno & 8) >> 3;
624		palette.set_pen_color(colourno, pal2bit((colourno & 2) | i), pal2bit(((colourno & 4) >> 1) | i), pal2bit(((colourno & 1) << 1) | i));
625		}
626		}
627
628	568	void rmnimbus_state::video_reset()
629	569	{
630	570	// When we reset clear the video registers and video memory.
631	571	memset(&m_vidregs,0x00,sizeof(m_vidregs));
632
633		m_bpp=4;          // bits per pixel
634		logerror("Video reset\n");
635	572	}
636	573
637	574	UINT32 rmnimbus_state::screen_update_nimbus(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)

trunk/src/mess/drivers/rmnimbus.c

r31216	r31217
120	120	//MCFG_SCREEN_VIDEO_ATTRIBUTES(VIDEO_UPDATE_SCANLINE)
121	121	MCFG_SCREEN_PALETTE("palette")
122	122
123		MCFG_PALETTE_ADD("palette", SCREEN_NO_COLOURS)
124		MCFG_PALETTE_INIT_OWNER(rmnimbus_state, rmnimbus)
	123	MCFG_PALETTE_ADD("palette", 16)
125	124
126	125	/* Backing storage */
127	126	MCFG_WD2793x_ADD(FDC_TAG, 1000000)

trunk/src/mess/machine/rmnimbus.c

r31216	r31217
1026	1026	if(LOG_DISK)
1027	1027	logerror("nimbus_drives_drq_w(%d)\n", state);
1028	1028
1029		if(state && FDC_DRQ_ENABLED())
1030		m_maincpu->drq1_w(state);
	1029	m_maincpu->drq1_w(state && FDC_DRQ_ENABLED());
1031	1030	}
1032	1031
1033	1032	UINT8 rmnimbus_state::fdc_driveno(UINT8 drivesel)

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