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r31203 Sunday 6th July, 2014 at 10:24:17 UTC by Alex Jackson
(MESS) c64: some optimizations [Alex Jackson]
* read_pla() leaves the PLA outputs packed, instead of using eight output parameters to return them
* flatten nested switch statements in read_memory() and write_memory()
* mos6566: inline bus_r() and various READ_LINE_MEMBERs

(nw)
from 285% to 300% idling at basic prompt with default slot devices (c1541, no cartridge)
About half the speedup comes from read_pla() refactoring, the other half comes from flattening the switch()es.
[src/emu/video]mos6566.c mos6566.h
[src/mess/drivers]c64.c
[src/mess/includes]c64.h

trunk/src/emu/video/mos6566.c
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28382838
28392839   m_lp = state;
28402840}
2841
2842
2843//-------------------------------------------------
2844//  phi0_r - phi 0
2845//-------------------------------------------------
2846
2847READ_LINE_MEMBER( mos6566_device::phi0_r )
2848{
2849   return m_phi0;
2850}
2851
2852
2853//-------------------------------------------------
2854//  ba_r - bus available
2855//-------------------------------------------------
2856
2857READ_LINE_MEMBER( mos6566_device::ba_r )
2858{
2859   return m_ba;
2860}
2861
2862
2863//-------------------------------------------------
2864//  aec_r - address enable control
2865//-------------------------------------------------
2866
2867READ_LINE_MEMBER( mos6566_device::aec_r )
2868{
2869   return m_aec;
2870}
2871
2872
2873//-------------------------------------------------
2874//  bus_r - data bus read
2875//-------------------------------------------------
2876
2877UINT8 mos6566_device::bus_r()
2878{
2879   return m_last_data;
2880}
trunk/src/emu/video/mos6566.h
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228228
229229   DECLARE_WRITE_LINE_MEMBER( lp_w );
230230
231   DECLARE_READ_LINE_MEMBER( phi0_r );
232   DECLARE_READ_LINE_MEMBER( ba_r );
233   DECLARE_READ_LINE_MEMBER( aec_r );
231   DECLARE_READ_LINE_MEMBER( phi0_r ) { return m_phi0; } // phi 0
232   DECLARE_READ_LINE_MEMBER( ba_r )   { return m_ba; }   // bus available
233   DECLARE_READ_LINE_MEMBER( aec_r )  { return m_aec; }  // address enable control
234234
235   UINT8 bus_r();
235   UINT8 bus_r() { return m_last_data; }
236236
237237   UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
238238
trunk/src/mess/includes/c64.h
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106106   virtual void machine_reset();
107107
108108   void check_interrupts();
109   void read_pla(offs_t offset, offs_t va, int rw, int aec, int ba, int *casram, int *basic, int *kernal, int *charom, int *grw, int *io, int *roml, int *romh);
109   int read_pla(offs_t offset, offs_t va, int rw, int aec, int ba);
110110   UINT8 read_memory(address_space &space, offs_t offset, offs_t va, int aec, int ba);
111111   void write_memory(address_space &space, offs_t offset, UINT8 data, int aec, int ba);
112112
trunk/src/mess/drivers/c64.c
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3232#define VA13 BIT(va, 13)
3333#define VA12 BIT(va, 12)
3434
35enum
36{
37   PLA_OUT_CASRAM = 0,
38   PLA_OUT_BASIC  = 1,
39   PLA_OUT_KERNAL = 2,
40   PLA_OUT_CHAROM = 3,
41   PLA_OUT_GRW    = 4,
42   PLA_OUT_IO     = 5,
43   PLA_OUT_ROML   = 6,
44   PLA_OUT_ROMH   = 7
45};
46
47
3548QUICKLOAD_LOAD_MEMBER( c64_state, cbm_c64 )
3649{
3750   return general_cbm_loadsnap(image, file_type, quickload_size, m_maincpu->space(AS_PROGRAM), 0, cbm_quick_sethiaddress);
r31202r31203
6679//  read_pla -
6780//-------------------------------------------------
6881
69void c64_state::read_pla(offs_t offset, offs_t va, int rw, int aec, int ba, int *casram, int *basic, int *kernal, int *charom, int *grw, int *io, int *roml, int *romh)
82int c64_state::read_pla(offs_t offset, offs_t va, int rw, int aec, int ba)
7083{
7184   //int ba = m_vic->ba_r();
7285   //int aec = !m_vic->aec_r();
r31202r31203
7891   UINT32 input = VA12 << 15 | VA13 << 14 | game << 13 | exrom << 12 | rw << 11 | aec << 10 | ba << 9 | A12 << 8 |
7992      A13 << 7 | A14 << 6 | A15 << 5 | m_va14 << 4 | m_charen << 3 | m_hiram << 2 | m_loram << 1 | cas;
8093
81   UINT32 data = m_pla->read(input);
82
83   *casram = BIT(data, 0);
84   *basic = BIT(data, 1);
85   *kernal = BIT(data, 2);
86   *charom = BIT(data, 3);
87   *grw = BIT(data, 4);
88   *io = BIT(data, 5);
89   *roml = BIT(data, 6);
90   *romh = BIT(data, 7);
94   return m_pla->read(input);
9195}
9296
9397
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98102UINT8 c64_state::read_memory(address_space &space, offs_t offset, offs_t va, int aec, int ba)
99103{
100104   int rw = 1;
101   int casram, basic, kernal, charom, grw, io, roml, romh;
102105   int io1 = 1, io2 = 1;
103106   int sphi2 = m_vic->phi0_r();
104107
105   read_pla(offset, va, rw, !aec, ba, &casram, &basic, &kernal, &charom, &grw, &io, &roml, &romh);
108   int plaout = read_pla(offset, va, rw, !aec, ba);
106109
107110   UINT8 data = 0xff;
108111
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111114      data = m_vic->bus_r();
112115   }
113116
114   if (!casram)
117   if (!BIT(plaout, PLA_OUT_CASRAM))
115118   {
116119      if (aec)
117120      {
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122125         data = m_ram->pointer()[(!m_va15 << 15) | (!m_va14 << 14) | va];
123126      }
124127   }
125   if (!basic)
128   if (!BIT(plaout, PLA_OUT_BASIC))
126129   {
127130      if (m_basic != NULL)
128131      {
r31202r31203
133136         data = m_kernal->base()[offset & 0x1fff];
134137      }
135138   }
136   if (!kernal)
139   if (!BIT(plaout, PLA_OUT_KERNAL))
137140   {
138141      if (m_basic != NULL)
139142      {
r31202r31203
144147         data = m_kernal->base()[0x2000 | (offset & 0x1fff)];
145148      }
146149   }
147   if (!charom)
150   if (!BIT(plaout, PLA_OUT_CHAROM))
148151   {
149152      data = m_charom->base()[offset & 0xfff];
150153   }
151   if (!io)
154   if (!BIT(plaout, PLA_OUT_IO))
152155   {
153      switch ((offset >> 10) & 0x03)
156      switch ((offset >> 8) & 0x0f)
154157      {
155      case 0: // VIC
158      case 0:
159      case 1:
160      case 2:
161      case 3: // VIC
156162         data = m_vic->read(space, offset & 0x3f);
157163         break;
158164
159      case 1: // SID
165      case 4:
166      case 5:
167      case 6:
168      case 7: // SID
160169         data = m_sid->read(space, offset & 0x1f);
161170         break;
162171
163      case 2: // COLOR
172      case 0x8:
173      case 0x9:
174      case 0xa:
175      case 0xb: // COLOR
164176         data = m_color_ram[offset & 0x3ff] & 0x0f;
165177         break;
166178
167      case 3: // CIAS
168         switch ((offset >> 8) & 0x03)
169         {
170         case 0: // CIA1
171            data = m_cia1->read(space, offset & 0x0f);
172            break;
179      case 0xc: // CIA1
180         data = m_cia1->read(space, offset & 0x0f);
181         break;
173182
174         case 1: // CIA2
175            data = m_cia2->read(space, offset & 0x0f);
176            break;
183      case 0xd: // CIA2
184         data = m_cia2->read(space, offset & 0x0f);
185         break;
177186
178         case 2: // I/O1
179            io1 = 0;
180            break;
187      case 0xe: // I/O1
188         io1 = 0;
189         break;
181190
182         case 3: // I/O2
183            io2 = 0;
184            break;
185         }
191      case 0xf: // I/O2
192         io2 = 0;
186193         break;
187194      }
188195   }
189196
197   int roml = BIT(plaout, PLA_OUT_ROML);
198   int romh = BIT(plaout, PLA_OUT_ROMH);
190199   return m_exp->cd_r(space, offset, data, sphi2, ba, roml, romh, io1, io2);
191200}
192201
r31202r31203
198207void c64_state::write_memory(address_space &space, offs_t offset, UINT8 data, int aec, int ba)
199208{
200209   int rw = 0;
201   int casram, basic, kernal, charom, grw, io, roml, romh;
202210   offs_t va = 0;
203211   int io1 = 1, io2 = 1;
204212   int sphi2 = m_vic->phi0_r();
205213
206   read_pla(offset, va, rw, !aec, ba, &casram, &basic, &kernal, &charom, &grw, &io, &roml, &romh);
214   int plaout = read_pla(offset, va, rw, !aec, ba);
207215
208216   if (offset < 0x0002)
209217   {
r31202r31203
211219      data = m_vic->bus_r();
212220   }
213221
214   if (!casram)
222   if (!BIT(plaout, PLA_OUT_CASRAM))
215223   {
216224      m_ram->pointer()[offset] = data;
217225   }
218   if (!io)
226   if (!BIT(plaout, PLA_OUT_IO))
219227   {
220      switch ((offset >> 10) & 0x03)
228      switch ((offset >> 8) & 0x0f)
221229      {
222      case 0: // VIC
230      case 0:
231      case 1:
232      case 2:
233      case 3: // VIC
223234         m_vic->write(space, offset & 0x3f, data);
224235         break;
225236
226      case 1: // SID
237      case 4:
238      case 5:
239      case 6:
240      case 7: // SID
227241         m_sid->write(space, offset & 0x1f, data);
228242         break;
229243
230      case 2: // COLOR
231         if (!grw) m_color_ram[offset & 0x3ff] = data & 0x0f;
244      case 0x8:
245      case 0x9:
246      case 0xa:
247      case 0xb: // COLOR
248         if (!BIT(plaout, PLA_OUT_GRW)) m_color_ram[offset & 0x3ff] = data & 0x0f;
232249         break;
233250
234      case 3: // CIAS
235         switch ((offset >> 8) & 0x03)
236         {
237         case 0: // CIA1
238            m_cia1->write(space, offset & 0x0f, data);
239            break;
251      case 0xc: // CIA1
252         m_cia1->write(space, offset & 0x0f, data);
253         break;
240254
241         case 1: // CIA2
242            m_cia2->write(space, offset & 0x0f, data);
243            break;
255      case 0xd: // CIA2
256         m_cia2->write(space, offset & 0x0f, data);
257         break;
244258
245         case 2: // I/O1
246            io1 = 0;
247            break;
259      case 0xe: // I/O1
260         io1 = 0;
261         break;
248262
249         case 3: // I/O2
250            io2 = 0;
251            break;
252         }
263      case 0xf: // I/O2
264         io2 = 0;
253265         break;
254266      }
255267   }
256268
269   int roml = BIT(plaout, PLA_OUT_ROML);
270   int romh = BIT(plaout, PLA_OUT_ROMH);
257271   m_exp->cd_w(space, offset, data, sphi2, ba, roml, romh, io1, io2);
258272}
259273

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