trunk/src/mess/drivers/gimix.c
| r31079 | r31080 | |
| 19 | 19 | #include "cpu/m6809/m6809.h" |
| 20 | 20 | #include "machine/mm58167.h" |
| 21 | 21 | #include "machine/6840ptm.h" |
| 22 | #include "machine/6821pia.h" |
| 23 | #include "machine/6850acia.h" |
| 24 | #include "bus/rs232/rs232.h" |
| 25 | #include "machine/clock.h" |
| 22 | 26 | #include "machine/wd_fdc.h" |
| 23 | 27 | #include "machine/terminal.h" |
| 24 | 28 | #include "machine/bankdev.h" |
| 29 | #include "machine/ram.h" |
| 30 | #include "formats/pc_dsk.h" |
| 25 | 31 | |
| 26 | 32 | #define DMA_DRQ (m_dma_status & 0x80) |
| 27 | 33 | #define DMA_INTRQ (m_dma_status & 0x40) |
| r31079 | r31080 | |
| 45 | 51 | #define DMA_ENABLE (m_dma_ctrl & 0x10) |
| 46 | 52 | #define DMA_BANK (m_dma_ctrl & 0x0f) |
| 47 | 53 | |
| 48 | | #define DMA_START_ADDR ((m_dma_ctrl & 0x0f) << 16) | m_dma_start_addr) |
| 54 | #define DMA_START_ADDR (((m_dma_ctrl & 0x0f) << 16) | m_dma_start_addr) |
| 49 | 55 | |
| 50 | 56 | class gimix_state : public driver_device |
| 51 | 57 | { |
| r31079 | r31080 | |
| 53 | 59 | gimix_state(const machine_config &mconfig, device_type type, const char *tag) |
| 54 | 60 | : driver_device(mconfig, type, tag) |
| 55 | 61 | , m_maincpu(*this, "maincpu") |
| 56 | | , m_terminal(*this, "terminal") |
| 62 | , m_fdc(*this, "fdc") |
| 63 | , m_ram(*this, RAM_TAG) |
| 57 | 64 | , m_rom(*this, "roms") |
| 65 | , m_acia1(*this, "acia1") |
| 66 | , m_acia2(*this, "acia2") |
| 67 | , m_acia3(*this, "acia3") |
| 68 | , m_acia4(*this, "acia4") |
| 58 | 69 | , m_bank1(*this, "bank1") |
| 59 | 70 | , m_bank2(*this, "bank2") |
| 60 | 71 | , m_bank3(*this, "bank3") |
| r31079 | r31080 | |
| 86 | 97 | DECLARE_WRITE_LINE_MEMBER(fdc_drq_w); |
| 87 | 98 | DECLARE_READ8_MEMBER(dma_r); |
| 88 | 99 | DECLARE_WRITE8_MEMBER(dma_w); |
| 100 | DECLARE_READ8_MEMBER(fdc_r); |
| 101 | DECLARE_WRITE8_MEMBER(fdc_w); |
| 102 | DECLARE_WRITE_LINE_MEMBER(write_acia_clock); |
| 103 | DECLARE_READ8_MEMBER(pia_pa_r); |
| 104 | DECLARE_WRITE8_MEMBER(pia_pa_w); |
| 105 | DECLARE_READ8_MEMBER(pia_pb_r); |
| 106 | DECLARE_WRITE8_MEMBER(pia_pb_w); |
| 89 | 107 | |
| 108 | DECLARE_FLOPPY_FORMATS(floppy_formats); |
| 109 | |
| 90 | 110 | private: |
| 91 | 111 | UINT8 m_term_data; |
| 92 | 112 | UINT8 m_dma_status; |
| 93 | 113 | UINT8 m_dma_ctrl; |
| 94 | 114 | UINT8 m_dma_drive_select; |
| 95 | 115 | UINT16 m_dma_start_addr; |
| 116 | UINT32 m_dma_current_addr; |
| 96 | 117 | UINT8 m_task; |
| 97 | 118 | UINT8 m_task_banks[16][16]; |
| 98 | 119 | |
| 120 | UINT8 m_pia1_pa; |
| 121 | UINT8 m_pia1_pb; |
| 122 | |
| 99 | 123 | virtual void machine_reset(); |
| 100 | 124 | virtual void machine_start(); |
| 125 | virtual void driver_start(); |
| 101 | 126 | |
| 102 | 127 | void refresh_memory(); |
| 103 | 128 | |
| 104 | 129 | required_device<cpu_device> m_maincpu; |
| 105 | | required_device<generic_terminal_device> m_terminal; |
| 130 | required_device<fd1797_t> m_fdc; |
| 131 | required_device<ram_device> m_ram; |
| 106 | 132 | required_memory_region m_rom; |
| 133 | required_device<acia6850_device> m_acia1; |
| 134 | required_device<acia6850_device> m_acia2; |
| 135 | required_device<acia6850_device> m_acia3; |
| 136 | required_device<acia6850_device> m_acia4; |
| 107 | 137 | |
| 108 | 138 | required_device<address_map_bank_device> m_bank1; |
| 109 | 139 | required_device<address_map_bank_device> m_bank2; |
| r31079 | r31080 | |
| 129 | 159 | }; |
| 130 | 160 | |
| 131 | 161 | static ADDRESS_MAP_START( gimix_banked_mem, AS_PROGRAM, 8, gimix_state) |
| 132 | | AM_RANGE(0x00000, 0x0dfff) AM_RAM |
| 133 | | AM_RANGE(0x0e004, 0x0e004) AM_READ(status_r) |
| 134 | | AM_RANGE(0x0e005, 0x0e005) AM_READ(keyin_r) AM_DEVWRITE("terminal", generic_terminal_device, write) |
| 162 | //AM_RANGE(0x00000, 0x0dfff) AM_RAM |
| 163 | AM_RANGE(0x0e000, 0x0e000) AM_DEVREADWRITE("acia1",acia6850_device,status_r,control_w) |
| 164 | AM_RANGE(0x0e001, 0x0e001) AM_DEVREADWRITE("acia1",acia6850_device,data_r,data_w) |
| 165 | AM_RANGE(0x0e004, 0x0e004) AM_DEVREADWRITE("acia2",acia6850_device,status_r,control_w) |
| 166 | AM_RANGE(0x0e005, 0x0e005) AM_DEVREADWRITE("acia2",acia6850_device,data_r,data_w) |
| 167 | AM_RANGE(0x0e018, 0x0e01b) AM_RAM // this area is used for "PROGRAMMED I/O BOOTSTRAP" |
| 135 | 168 | AM_RANGE(0x0e100, 0x0e1ff) AM_RAM |
| 136 | 169 | //AM_RANGE(0x0e200, 0x0e20f) // 9511A / 9512 Arithmetic Processor |
| 137 | 170 | AM_RANGE(0x0e210, 0x0e21f) AM_DEVREADWRITE("timer",ptm6840_device,read,write) |
| 138 | 171 | AM_RANGE(0x0e220, 0x0e23f) AM_DEVREADWRITE("rtc",mm58167_device,read,write) |
| 139 | 172 | AM_RANGE(0x0e240, 0x0e3af) AM_RAM |
| 140 | | AM_RANGE(0x0e3b0, 0x0e3b3) AM_READWRITE(dma_r, dma_w)// DMA controller (custom?) |
| 141 | | AM_RANGE(0x0e3b4, 0x0e3b7) AM_DEVREADWRITE("fdc", fd1797_t,read,write) // FD1797 FDC |
| 173 | AM_RANGE(0x0e3b0, 0x0e3b3) AM_READWRITE(dma_r, dma_w) // DMA controller (custom?) |
| 174 | AM_RANGE(0x0e3b4, 0x0e3b7) AM_READWRITE(fdc_r, fdc_w) // FD1797 FDC |
| 142 | 175 | AM_RANGE(0x0e400, 0x0e7ff) AM_RAM |
| 143 | 176 | AM_RANGE(0x0e800, 0x0efff) AM_ROMBANK("rombank3") |
| 144 | 177 | AM_RANGE(0x0f000, 0x0f7ff) AM_ROMBANK("rombank2") |
| 145 | 178 | AM_RANGE(0x0f800, 0x0ffff) AM_ROMBANK("rombank1") |
| 146 | | AM_RANGE(0x10000, 0x1ffff) AM_RAM |
| 179 | //AM_RANGE(0x10000, 0x1ffff) AM_RAM |
| 147 | 180 | ADDRESS_MAP_END |
| 148 | 181 | |
| 149 | 182 | static ADDRESS_MAP_START( gimix_mem, AS_PROGRAM, 8, gimix_state ) |
| r31079 | r31080 | |
| 242 | 275 | { |
| 243 | 276 | case 0: |
| 244 | 277 | return m_dma_status; |
| 278 | case 1: |
| 279 | return m_dma_ctrl; |
| 245 | 280 | case 2: |
| 246 | 281 | return (m_dma_start_addr & 0xff00) >> 8; |
| 247 | 282 | case 3: |
| r31079 | r31080 | |
| 259 | 294 | case 0: |
| 260 | 295 | logerror("DMA: Drive select %02x\n",data); |
| 261 | 296 | m_dma_drive_select = data; |
| 297 | m_fdc->dden_w(DMA_DENSITY); |
| 298 | if(data & 0x40) // 8" / 5.25" connector select |
| 299 | m_dma_status |= 0x04; |
| 300 | else |
| 301 | m_dma_status &= ~0x04; |
| 302 | if(data & 0x01) |
| 303 | m_fdc->set_floppy(m_fdc->subdevice<floppy_connector>("0")->get_device()); |
| 304 | if(data & 0x02) |
| 305 | m_fdc->set_floppy(m_fdc->subdevice<floppy_connector>("1")->get_device()); |
| 262 | 306 | break; |
| 263 | 307 | case 1: |
| 264 | 308 | logerror("DMA: DMA control %02x\n",data); |
| 265 | 309 | m_dma_ctrl = data; |
| 310 | if(data & 0x10) |
| 311 | m_dma_status |= 0x12; |
| 312 | else |
| 313 | m_dma_status &= ~0x12; |
| 266 | 314 | break; |
| 267 | 315 | case 2: |
| 268 | 316 | logerror("DMA: DMA start address MSB %02x\n",data); |
| 269 | 317 | m_dma_start_addr = (m_dma_start_addr & 0x00ff) | (data << 8); |
| 318 | m_dma_current_addr = DMA_START_ADDR; |
| 270 | 319 | break; |
| 271 | 320 | case 3: |
| 272 | 321 | logerror("DMA: DMA start address LSB %02x\n",data); |
| 273 | 322 | m_dma_start_addr = (m_dma_start_addr & 0xff00) | data; |
| 323 | m_dma_current_addr = DMA_START_ADDR; |
| 274 | 324 | break; |
| 275 | 325 | default: |
| 276 | 326 | logerror("DMA: Unknown or invalid DMA register %02x write %02x\n",offset,data); |
| 277 | 327 | } |
| 278 | 328 | } |
| 279 | 329 | |
| 330 | READ8_MEMBER(gimix_state::fdc_r) |
| 331 | { |
| 332 | // motors are switched on on FDC access |
| 333 | m_fdc->subdevice<floppy_connector>("0")->get_device()->mon_w(0); |
| 334 | m_fdc->subdevice<floppy_connector>("1")->get_device()->mon_w(0); |
| 335 | return m_fdc->read(space,offset); |
| 336 | } |
| 337 | |
| 338 | WRITE8_MEMBER(gimix_state::fdc_w) |
| 339 | { |
| 340 | // motors are switched on on FDC access |
| 341 | m_fdc->subdevice<floppy_connector>("0")->get_device()->mon_w(0); |
| 342 | m_fdc->subdevice<floppy_connector>("1")->get_device()->mon_w(0); |
| 343 | m_fdc->write(space,offset,data); |
| 344 | } |
| 345 | |
| 346 | READ8_MEMBER(gimix_state::pia_pa_r) |
| 347 | { |
| 348 | return m_pia1_pa; |
| 349 | } |
| 350 | |
| 351 | WRITE8_MEMBER(gimix_state::pia_pa_w) |
| 352 | { |
| 353 | m_pia1_pa = data; |
| 354 | logerror("PIA: Port A write %02x\n",data); |
| 355 | } |
| 356 | |
| 357 | READ8_MEMBER(gimix_state::pia_pb_r) |
| 358 | { |
| 359 | return m_pia1_pb; |
| 360 | } |
| 361 | |
| 362 | WRITE8_MEMBER(gimix_state::pia_pb_w) |
| 363 | { |
| 364 | m_pia1_pb = data; |
| 365 | logerror("PIA: Port B write %02x\n",data); |
| 366 | } |
| 367 | |
| 368 | |
| 280 | 369 | WRITE_LINE_MEMBER(gimix_state::irq_w) |
| 281 | 370 | { |
| 282 | 371 | m_maincpu->set_input_line(M6809_IRQ_LINE,state ? ASSERT_LINE : CLEAR_LINE); |
| r31079 | r31080 | |
| 293 | 382 | WRITE_LINE_MEMBER(gimix_state::fdc_drq_w) |
| 294 | 383 | { |
| 295 | 384 | if(state) |
| 385 | { |
| 296 | 386 | m_dma_status |= 0x80; |
| 387 | // do a DMA transfer |
| 388 | if(DMA_DIRECTION) |
| 389 | { |
| 390 | // write to disk |
| 391 | m_fdc->data_w(m_ram->read(m_dma_current_addr)); |
| 392 | logerror("DMA: read from RAM %05x\n",m_dma_current_addr); |
| 393 | } |
| 394 | else |
| 395 | { |
| 396 | // read from disk |
| 397 | m_ram->write(m_dma_current_addr,m_fdc->data_r()); |
| 398 | logerror("DMA: write to RAM %05x\n",m_dma_current_addr); |
| 399 | } |
| 400 | m_dma_current_addr++; |
| 401 | } |
| 297 | 402 | else |
| 298 | 403 | m_dma_status &= ~0x80; |
| 299 | | // TODO: actually do DMA transfers |
| 404 | logerror("DMA: DRQ set to %i\n",state); |
| 300 | 405 | } |
| 301 | 406 | |
| 302 | 407 | void gimix_state::machine_reset() |
| r31079 | r31080 | |
| 322 | 427 | m_rombank2->set_entry(1); |
| 323 | 428 | m_rombank3->set_entry(2); |
| 324 | 429 | m_fixedrombank->set_entry(0); |
| 430 | // install first 56k RAM |
| 431 | m_bank1->space(AS_PROGRAM).install_ram(0x0000,0xe000,0xffff,0,NULL); |
| 432 | m_bank2->space(AS_PROGRAM).install_ram(0x0000,0xe000,0xffff,0,NULL); |
| 433 | m_bank3->space(AS_PROGRAM).install_ram(0x0000,0xe000,0xffff,0,NULL); |
| 434 | m_bank4->space(AS_PROGRAM).install_ram(0x0000,0xe000,0xffff,0,NULL); |
| 435 | m_bank5->space(AS_PROGRAM).install_ram(0x0000,0xe000,0xffff,0,NULL); |
| 436 | m_bank6->space(AS_PROGRAM).install_ram(0x0000,0xe000,0xffff,0,NULL); |
| 437 | m_bank7->space(AS_PROGRAM).install_ram(0x0000,0xe000,0xffff,0,NULL); |
| 438 | m_bank8->space(AS_PROGRAM).install_ram(0x0000,0xe000,0xffff,0,NULL); |
| 439 | m_bank9->space(AS_PROGRAM).install_ram(0x0000,0xe000,0xffff,0,NULL); |
| 440 | m_bank10->space(AS_PROGRAM).install_ram(0x0000,0xe000,0xffff,0,NULL); |
| 441 | m_bank11->space(AS_PROGRAM).install_ram(0x0000,0xe000,0xffff,0,NULL); |
| 442 | m_bank12->space(AS_PROGRAM).install_ram(0x0000,0xe000,0xffff,0,NULL); |
| 443 | m_bank13->space(AS_PROGRAM).install_ram(0x0000,0xe000,0xffff,0,NULL); |
| 444 | m_bank14->space(AS_PROGRAM).install_ram(0x0000,0xe000,0xffff,0,NULL); |
| 445 | m_bank15->space(AS_PROGRAM).install_ram(0x0000,0xe000,0xffff,0,NULL); |
| 446 | m_bank16->space(AS_PROGRAM).install_ram(0x0000,0xe000,0xffff,0,NULL); |
| 447 | // install any extra RAM |
| 448 | if(m_ram->size() > 65536) |
| 449 | { |
| 450 | m_bank1->space(AS_PROGRAM).install_ram(0x10000,m_ram->size()-1,0xffff,0,NULL); |
| 451 | m_bank2->space(AS_PROGRAM).install_ram(0x10000,m_ram->size()-1,0xffff,0,NULL); |
| 452 | m_bank3->space(AS_PROGRAM).install_ram(0x10000,m_ram->size()-1,0xffff,0,NULL); |
| 453 | m_bank4->space(AS_PROGRAM).install_ram(0x10000,m_ram->size()-1,0xffff,0,NULL); |
| 454 | m_bank5->space(AS_PROGRAM).install_ram(0x10000,m_ram->size()-1,0xffff,0,NULL); |
| 455 | m_bank6->space(AS_PROGRAM).install_ram(0x10000,m_ram->size()-1,0xffff,0,NULL); |
| 456 | m_bank7->space(AS_PROGRAM).install_ram(0x10000,m_ram->size()-1,0xffff,0,NULL); |
| 457 | m_bank8->space(AS_PROGRAM).install_ram(0x10000,m_ram->size()-1,0xffff,0,NULL); |
| 458 | m_bank9->space(AS_PROGRAM).install_ram(0x10000,m_ram->size()-1,0xffff,0,NULL); |
| 459 | m_bank10->space(AS_PROGRAM).install_ram(0x10000,m_ram->size()-1,0xffff,0,NULL); |
| 460 | m_bank11->space(AS_PROGRAM).install_ram(0x10000,m_ram->size()-1,0xffff,0,NULL); |
| 461 | m_bank12->space(AS_PROGRAM).install_ram(0x10000,m_ram->size()-1,0xffff,0,NULL); |
| 462 | m_bank13->space(AS_PROGRAM).install_ram(0x10000,m_ram->size()-1,0xffff,0,NULL); |
| 463 | m_bank14->space(AS_PROGRAM).install_ram(0x10000,m_ram->size()-1,0xffff,0,NULL); |
| 464 | m_bank15->space(AS_PROGRAM).install_ram(0x10000,m_ram->size()-1,0xffff,0,NULL); |
| 465 | m_bank16->space(AS_PROGRAM).install_ram(0x10000,m_ram->size()-1,0xffff,0,NULL); |
| 466 | } |
| 325 | 467 | } |
| 326 | 468 | |
| 469 | void gimix_state::driver_start() |
| 470 | { |
| 471 | } |
| 472 | |
| 473 | WRITE_LINE_MEMBER(gimix_state::write_acia_clock) |
| 474 | { |
| 475 | m_acia1->write_txc(state); |
| 476 | m_acia1->write_rxc(state); |
| 477 | m_acia2->write_txc(state); |
| 478 | m_acia2->write_rxc(state); |
| 479 | } |
| 480 | |
| 481 | FLOPPY_FORMATS_MEMBER( gimix_state::floppy_formats ) |
| 482 | FLOPPY_PC_FORMAT |
| 483 | FLOPPY_FORMATS_END |
| 484 | |
| 327 | 485 | static SLOT_INTERFACE_START( gimix_floppies ) |
| 328 | 486 | SLOT_INTERFACE( "525dd", FLOPPY_525_DD ) |
| 329 | 487 | SLOT_INTERFACE_END |
| r31079 | r31080 | |
| 341 | 499 | MCFG_CPU_PROGRAM_MAP(gimix_mem) |
| 342 | 500 | MCFG_CPU_IO_MAP(gimix_io) |
| 343 | 501 | |
| 344 | | /* video hardware */ |
| 345 | | MCFG_DEVICE_ADD("terminal", GENERIC_TERMINAL, 0) |
| 346 | | MCFG_GENERIC_TERMINAL_KEYBOARD_CB(WRITE8(gimix_state, kbd_put)) |
| 347 | | |
| 348 | 502 | /* rtc */ |
| 349 | 503 | MCFG_DEVICE_ADD("rtc", MM58167, XTAL_32_768kHz) |
| 350 | 504 | MCFG_MM58167_IRQ_CALLBACK(WRITELINE(gimix_state,irq_w)) |
| r31079 | r31080 | |
| 357 | 511 | MCFG_FD1797x_ADD("fdc",XTAL_2MHz) |
| 358 | 512 | MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(gimix_state,fdc_irq_w)) |
| 359 | 513 | MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(gimix_state,fdc_drq_w)) |
| 360 | | MCFG_FLOPPY_DRIVE_ADD("fdc:0", gimix_floppies, "525dd", floppy_image_device::default_floppy_formats) |
| 361 | | MCFG_FLOPPY_DRIVE_ADD("fdc:1", gimix_floppies, "525dd", floppy_image_device::default_floppy_formats) |
| 514 | MCFG_FLOPPY_DRIVE_ADD("fdc:0", gimix_floppies, "525dd", gimix_state::floppy_formats) |
| 515 | MCFG_FLOPPY_DRIVE_ADD("fdc:1", gimix_floppies, "525dd", gimix_state::floppy_formats) |
| 362 | 516 | |
| 517 | /* parallel ports */ |
| 518 | MCFG_DEVICE_ADD("pia1",PIA6821,XTAL_2MHz) |
| 519 | MCFG_PIA_WRITEPA_HANDLER(WRITE8(gimix_state,pia_pa_w)) |
| 520 | MCFG_PIA_WRITEPB_HANDLER(WRITE8(gimix_state,pia_pb_w)) |
| 521 | MCFG_PIA_READPA_HANDLER(READ8(gimix_state,pia_pa_r)) |
| 522 | MCFG_PIA_READPB_HANDLER(READ8(gimix_state,pia_pb_r)) |
| 523 | MCFG_DEVICE_ADD("pia2",PIA6821,XTAL_2MHz) |
| 524 | |
| 525 | /* serial ports */ |
| 526 | MCFG_DEVICE_ADD("acia1",ACIA6850,XTAL_2MHz) |
| 527 | MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("serial1",rs232_port_device,write_txd)) |
| 528 | MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE("serial1",rs232_port_device,write_rts)) |
| 529 | MCFG_DEVICE_ADD("acia2",ACIA6850,XTAL_2MHz) |
| 530 | MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("serial2",rs232_port_device,write_txd)) |
| 531 | MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE("serial2",rs232_port_device,write_rts)) |
| 532 | MCFG_DEVICE_ADD("acia3",ACIA6850,XTAL_2MHz) |
| 533 | MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("serial3",rs232_port_device,write_txd)) |
| 534 | MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE("serial3",rs232_port_device,write_rts)) |
| 535 | MCFG_DEVICE_ADD("acia4",ACIA6850,XTAL_2MHz) |
| 536 | MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("serial4",rs232_port_device,write_txd)) |
| 537 | MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE("serial4",rs232_port_device,write_rts)) |
| 538 | |
| 539 | MCFG_RS232_PORT_ADD("serial1",default_rs232_devices,NULL) |
| 540 | MCFG_RS232_RXD_HANDLER(DEVWRITELINE("acia1",acia6850_device,write_rxd)) |
| 541 | MCFG_RS232_CTS_HANDLER(DEVWRITELINE("acia1",acia6850_device,write_cts)) |
| 542 | |
| 543 | MCFG_RS232_PORT_ADD("serial2",default_rs232_devices,"terminal") |
| 544 | MCFG_RS232_RXD_HANDLER(DEVWRITELINE("acia2",acia6850_device,write_rxd)) |
| 545 | MCFG_RS232_CTS_HANDLER(DEVWRITELINE("acia2",acia6850_device,write_cts)) |
| 546 | |
| 547 | MCFG_RS232_PORT_ADD("serial3",default_rs232_devices,NULL) |
| 548 | MCFG_RS232_RXD_HANDLER(DEVWRITELINE("acia3",acia6850_device,write_rxd)) |
| 549 | MCFG_RS232_CTS_HANDLER(DEVWRITELINE("acia3",acia6850_device,write_cts)) |
| 550 | |
| 551 | MCFG_RS232_PORT_ADD("serial4",default_rs232_devices,NULL) |
| 552 | MCFG_RS232_RXD_HANDLER(DEVWRITELINE("acia4",acia6850_device,write_rxd)) |
| 553 | MCFG_RS232_CTS_HANDLER(DEVWRITELINE("acia4",acia6850_device,write_cts)) |
| 554 | |
| 555 | MCFG_DEVICE_ADD("acia_clock", CLOCK, 153600) |
| 556 | MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(gimix_state, write_acia_clock)) |
| 557 | |
| 363 | 558 | /* banking */ |
| 364 | 559 | MCFG_ADDRESS_BANK("bank1") |
| 365 | 560 | MCFG_ADDRESS_BANK("bank2") |
| r31079 | r31080 | |
| 378 | 573 | MCFG_ADDRESS_BANK("bank15") |
| 379 | 574 | MCFG_ADDRESS_BANK("bank16") |
| 380 | 575 | |
| 576 | /* internal ram */ |
| 577 | MCFG_RAM_ADD(RAM_TAG) |
| 578 | MCFG_RAM_DEFAULT_SIZE("128K") |
| 579 | MCFG_RAM_EXTRA_OPTIONS("56K,256K,512K") |
| 580 | |
| 381 | 581 | MACHINE_CONFIG_END |
| 382 | 582 | |
| 383 | 583 | ROM_START( gimix ) |