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r31057 Saturday 21st June, 2014 at 13:09:12 UTC by Barry Rodewald
gimix: added banking, RTC, timer, FDC...

[src/mess/drivers]

gimix.c

trunk/src/mess/drivers/gimix.c

r31056	r31057
17	17
18	18	#include "emu.h"
19	19	#include "cpu/m6809/m6809.h"
	20	#include "machine/mm58167.h"
	21	#include "machine/6840ptm.h"
	22	#include "machine/wd_fdc.h"
20	23	#include "machine/terminal.h"
	24	#include "machine/bankdev.h"
21	25
	26	#define DMA_DRQ         (m_dma_status & 0x80)
	27	#define DMA_INTRQ       (m_dma_status & 0x40)
	28	#define DMA_MOTOR_DELAY (m_dma_status & 0x20)
	29	#define DMA_ENABLED     (m_dma_status & 0x10)
	30	#define DMA_FAULT       (m_dma_status & 0x08)
	31	#define DMA_DRIVE_SIZE  (m_dma_status & 0x04)
	32	#define DMA_DIP_SENSE   (m_dma_status & 0x01)
22	33
	34	#define DMA_CONNECT_SEL (m_dma_drive_select & 0x40)
	35	#define DMA_DENSITY     (m_dma_drive_select & 0x20)
	36	#define DMA_WR_PROTECT  (m_dma_drive_select & 0x10)
	37	#define DMA_SEL_DRV3    (m_dma_drive_select & 0x08)
	38	#define DMA_SEL_DRV2    (m_dma_drive_select & 0x04)
	39	#define DMA_SEL_DRV1    (m_dma_drive_select & 0x02)
	40	#define DMA_SEL_DRV0    (m_dma_drive_select & 0x01)
	41
	42	#define DMA_IRQ_ENABLE  (m_dma_ctrl & 0x80)
	43	#define DMA_SIDE_SEL    (m_dma_ctrl & 0x40)
	44	#define DMA_DIRECTION   (m_dma_ctrl & 0x20)
	45	#define DMA_ENABLE      (m_dma_ctrl & 0x10)
	46	#define DMA_BANK        (m_dma_ctrl & 0x0f)
	47
	48	#define DMA_START_ADDR  ((m_dma_ctrl & 0x0f) << 16) | m_dma_start_addr)
	49
23	50	class gimix_state : public driver_device
24	51	{
25	52	public:
r31056	r31057
27	54	: driver_device(mconfig, type, tag)
28	55	, m_maincpu(*this, "maincpu")
29	56	, m_terminal(*this, "terminal")
	57	, m_rom(*this, "roms")
	58	, m_bank1(*this, "bank1")
	59	, m_bank2(*this, "bank2")
	60	, m_bank3(*this, "bank3")
	61	, m_bank4(*this, "bank4")
	62	, m_bank5(*this, "bank5")
	63	, m_bank6(*this, "bank6")
	64	, m_bank7(*this, "bank7")
	65	, m_bank8(*this, "bank8")
	66	, m_bank9(*this, "bank9")
	67	, m_bank10(*this, "bank10")
	68	, m_bank11(*this, "bank11")
	69	, m_bank12(*this, "bank12")
	70	, m_bank13(*this, "bank13")
	71	, m_bank14(*this, "bank14")
	72	, m_bank15(*this, "bank15")
	73	, m_bank16(*this, "bank16")
	74	, m_rombank1(*this, "rombank1")
	75	, m_rombank2(*this, "rombank2")
	76	, m_rombank3(*this, "rombank3")
	77	, m_fixedrombank(*this, "fixedrombank")
30	78	{}
31	79
32	80	DECLARE_WRITE8_MEMBER(kbd_put);
33	81	DECLARE_READ8_MEMBER(keyin_r);
34	82	DECLARE_READ8_MEMBER(status_r);
	83	DECLARE_WRITE8_MEMBER(system_w);
	84	DECLARE_WRITE_LINE_MEMBER(irq_w);
	85	DECLARE_WRITE_LINE_MEMBER(fdc_irq_w);
	86	DECLARE_WRITE_LINE_MEMBER(fdc_drq_w);
	87	DECLARE_READ8_MEMBER(dma_r);
	88	DECLARE_WRITE8_MEMBER(dma_w);
35	89
36	90	private:
37	91	UINT8 m_term_data;
	92	UINT8 m_dma_status;
	93	UINT8 m_dma_ctrl;
	94	UINT8 m_dma_drive_select;
	95	UINT16 m_dma_start_addr;
	96	UINT8 m_task;
	97	UINT8 m_task_banks[16][16];
	98
38	99	virtual void machine_reset();
	100	virtual void machine_start();
	101
	102	void refresh_memory();
	103
39	104	required_device<cpu_device> m_maincpu;
40	105	required_device<generic_terminal_device> m_terminal;
	106	required_memory_region m_rom;
	107
	108	required_device<address_map_bank_device> m_bank1;
	109	required_device<address_map_bank_device> m_bank2;
	110	required_device<address_map_bank_device> m_bank3;
	111	required_device<address_map_bank_device> m_bank4;
	112	required_device<address_map_bank_device> m_bank5;
	113	required_device<address_map_bank_device> m_bank6;
	114	required_device<address_map_bank_device> m_bank7;
	115	required_device<address_map_bank_device> m_bank8;
	116	required_device<address_map_bank_device> m_bank9;
	117	required_device<address_map_bank_device> m_bank10;
	118	required_device<address_map_bank_device> m_bank11;
	119	required_device<address_map_bank_device> m_bank12;
	120	required_device<address_map_bank_device> m_bank13;
	121	required_device<address_map_bank_device> m_bank14;
	122	required_device<address_map_bank_device> m_bank15;
	123	required_device<address_map_bank_device> m_bank16;
	124	required_memory_bank m_rombank1;
	125	required_memory_bank m_rombank2;
	126	required_memory_bank m_rombank3;
	127	required_memory_bank m_fixedrombank;
	128
41	129	};
42	130
	131	static ADDRESS_MAP_START( gimix_banked_mem, AS_PROGRAM, 8, gimix_state)
	132	AM_RANGE(0x00000, 0x0dfff) AM_RAM
	133	AM_RANGE(0x0e004, 0x0e004) AM_READ(status_r)
	134	AM_RANGE(0x0e005, 0x0e005) AM_READ(keyin_r) AM_DEVWRITE("terminal", generic_terminal_device, write)
	135	AM_RANGE(0x0e100, 0x0e1ff) AM_RAM
	136	//AM_RANGE(0x0e200, 0x0e20f) // 9511A / 9512 Arithmetic Processor
	137	AM_RANGE(0x0e210, 0x0e21f) AM_DEVREADWRITE("timer",ptm6840_device,read,write)
	138	AM_RANGE(0x0e220, 0x0e23f) AM_DEVREADWRITE("rtc",mm58167_device,read,write)
	139	AM_RANGE(0x0e240, 0x0e3af) AM_RAM
	140	AM_RANGE(0x0e3b0, 0x0e3b3) AM_READWRITE(dma_r, dma_w)// DMA controller (custom?)
	141	AM_RANGE(0x0e3b4, 0x0e3b7) AM_DEVREADWRITE("fdc", fd1797_t,read,write)  // FD1797 FDC
	142	AM_RANGE(0x0e400, 0x0e7ff) AM_RAM
	143	AM_RANGE(0x0e800, 0x0efff) AM_ROMBANK("rombank3")
	144	AM_RANGE(0x0f000, 0x0f7ff) AM_ROMBANK("rombank2")
	145	AM_RANGE(0x0f800, 0x0ffff) AM_ROMBANK("rombank1")
	146	AM_RANGE(0x10000, 0x1ffff) AM_RAM
	147	ADDRESS_MAP_END
	148
43	149	static ADDRESS_MAP_START( gimix_mem, AS_PROGRAM, 8, gimix_state )
44		AM_RANGE(0x0000, 0xdfff) AM_RAM
45		AM_RANGE(0xe004, 0xe004) AM_READ(status_r)
46		AM_RANGE(0xe005, 0xe005) AM_READ(keyin_r) AM_DEVWRITE("terminal", generic_terminal_device, write)
47		AM_RANGE(0xe400, 0xf7ff) AM_RAM
48		AM_RANGE(0xf800, 0xffff) AM_ROM AM_REGION("maincpu", 0xf800)
	150	AM_RANGE(0x0000, 0x0fff) AM_DEVREADWRITE("bank1", address_map_bank_device, read8, write8)
	151	AM_RANGE(0x1000, 0x1fff) AM_DEVREADWRITE("bank2", address_map_bank_device, read8, write8)
	152	AM_RANGE(0x2000, 0x2fff) AM_DEVREADWRITE("bank3", address_map_bank_device, read8, write8)
	153	AM_RANGE(0x3000, 0x3fff) AM_DEVREADWRITE("bank4", address_map_bank_device, read8, write8)
	154	AM_RANGE(0x4000, 0x4fff) AM_DEVREADWRITE("bank5", address_map_bank_device, read8, write8)
	155	AM_RANGE(0x5000, 0x5fff) AM_DEVREADWRITE("bank6", address_map_bank_device, read8, write8)
	156	AM_RANGE(0x6000, 0x6fff) AM_DEVREADWRITE("bank7", address_map_bank_device, read8, write8)
	157	AM_RANGE(0x7000, 0x7fff) AM_DEVREADWRITE("bank8", address_map_bank_device, read8, write8)
	158	AM_RANGE(0x8000, 0x8fff) AM_DEVREADWRITE("bank9", address_map_bank_device, read8, write8)
	159	AM_RANGE(0x9000, 0x9fff) AM_DEVREADWRITE("bank10", address_map_bank_device, read8, write8)
	160	AM_RANGE(0xa000, 0xafff) AM_DEVREADWRITE("bank11", address_map_bank_device, read8, write8)
	161	AM_RANGE(0xb000, 0xbfff) AM_DEVREADWRITE("bank12", address_map_bank_device, read8, write8)
	162	AM_RANGE(0xc000, 0xcfff) AM_DEVREADWRITE("bank13", address_map_bank_device, read8, write8)
	163	AM_RANGE(0xd000, 0xdfff) AM_DEVREADWRITE("bank14", address_map_bank_device, read8, write8)
	164	AM_RANGE(0xe000, 0xefff) AM_DEVREADWRITE("bank15", address_map_bank_device, read8, write8)
	165	AM_RANGE(0xf000, 0xfeff) AM_DEVREADWRITE("bank16", address_map_bank_device, read8, write8)
	166	AM_RANGE(0xff00, 0xffff) AM_ROMBANK("fixedrombank") AM_WRITE(system_w)
49	167	ADDRESS_MAP_END
50	168
51	169	static ADDRESS_MAP_START( gimix_io, AS_IO, 8, gimix_state )
r31056	r31057
71	189	m_term_data = data;
72	190	}
73	191
	192	void gimix_state::refresh_memory()
	193	{
	194	int x;
	195	address_map_bank_device* banknum[16] = { m_bank1, m_bank2, m_bank3, m_bank4, m_bank5, m_bank6, m_bank7, m_bank8,
	196	m_bank9, m_bank10, m_bank11, m_bank12, m_bank13, m_bank14, m_bank15, m_bank16};
	197
	198	for(x=0;x<16;x++) // for each bank
	199	{
	200	banknum[x]->set_bank(m_task_banks[m_task][x]);
	201	}
	202	}
	203
	204	WRITE8_MEMBER( gimix_state::system_w )
	205	{
	206	if(offset == 0x7f)  // task register
	207	{
	208	if(data & 0x20)  // FPLA software latch
	209	{
	210	m_rombank1->set_entry(2);
	211	m_rombank2->set_entry(3);
	212	m_rombank3->set_entry(1);
	213	m_fixedrombank->set_entry(2);
	214	logerror("SYS: FPLA software latch set\n");
	215	}
	216	else
	217	{
	218	m_rombank1->set_entry(0);
	219	m_rombank2->set_entry(1);
	220	m_rombank3->set_entry(2);
	221	m_fixedrombank->set_entry(0);
	222	logerror("SYS: FPLA software latch reset\n");
	223	}
	224	m_task = data & 0x0f;
	225	refresh_memory();
	226	logerror("SYS: Task set to %02x\n",data & 0x0f);
	227	}
	228	if(offset >= 0xf0)  // Dynamic Address Translation RAM (write only)
	229	{
	230	address_map_bank_device* banknum[16] = { m_bank1, m_bank2, m_bank3, m_bank4, m_bank5, m_bank6, m_bank7, m_bank8,
	231	m_bank9, m_bank10, m_bank11, m_bank12, m_bank13, m_bank14, m_bank15, m_bank16};
	232
	233	banknum[offset-0xf0]->set_bank(data & 0x0f);
	234	m_task_banks[m_task][offset-0xf0] = data & 0x0f;
	235	logerror("SYS: Bank %i set to physical bank %02x\n",offset-0xf0,data);
	236	}
	237	}
	238
	239	READ8_MEMBER(gimix_state::dma_r)
	240	{
	241	switch(offset)
	242	{
	243	case 0:
	244	return m_dma_status;
	245	case 2:
	246	return (m_dma_start_addr & 0xff00) >> 8;
	247	case 3:
	248	return (m_dma_start_addr & 0x00ff);
	249	default:
	250	logerror("DMA: Unknown or invalid DMA register %02x read\n",offset);
	251	}
	252	return 0xff;
	253	}
	254
	255	WRITE8_MEMBER(gimix_state::dma_w)
	256	{
	257	switch(offset)
	258	{
	259	case 0:
	260	logerror("DMA: Drive select %02x\n",data);
	261	m_dma_drive_select = data;
	262	break;
	263	case 1:
	264	logerror("DMA: DMA control %02x\n",data);
	265	m_dma_ctrl = data;
	266	break;
	267	case 2:
	268	logerror("DMA: DMA start address MSB %02x\n",data);
	269	m_dma_start_addr = (m_dma_start_addr & 0x00ff) | (data << 8);
	270	break;
	271	case 3:
	272	logerror("DMA: DMA start address LSB %02x\n",data);
	273	m_dma_start_addr = (m_dma_start_addr & 0xff00) | data;
	274	break;
	275	default:
	276	logerror("DMA: Unknown or invalid DMA register %02x write %02x\n",offset,data);
	277	}
	278	}
	279
	280	WRITE_LINE_MEMBER(gimix_state::irq_w)
	281	{
	282	m_maincpu->set_input_line(M6809_IRQ_LINE,state ? ASSERT_LINE : CLEAR_LINE);
	283	}
	284
	285	WRITE_LINE_MEMBER(gimix_state::fdc_irq_w)
	286	{
	287	if(state)
	288	m_dma_status |= 0x40;
	289	else
	290	m_dma_status &= ~0x40;
	291	}
	292
	293	WRITE_LINE_MEMBER(gimix_state::fdc_drq_w)
	294	{
	295	if(state)
	296	m_dma_status |= 0x80;
	297	else
	298	m_dma_status &= ~0x80;
	299	// TODO: actually do DMA transfers
	300	}
	301
74	302	void gimix_state::machine_reset()
75	303	{
76	304	m_term_data = 0;
	305	m_rombank1->set_entry(0);  // RAM banks are undefined on startup
	306	m_rombank2->set_entry(1);
	307	m_rombank3->set_entry(2);
	308	m_fixedrombank->set_entry(0);
	309	m_dma_status = 0x00;
	310	m_dma_ctrl = 0x00;
	311	m_task = 0x00;
77	312	}
78	313
	314	void gimix_state::machine_start()
	315	{
	316	UINT8* ROM = m_rom->base();
	317	m_rombank1->configure_entries(0,4,ROM,0x800);
	318	m_rombank2->configure_entries(0,4,ROM,0x800);
	319	m_rombank3->configure_entries(0,4,ROM,0x800);
	320	m_fixedrombank->configure_entries(0,4,ROM+0x700,0x800);
	321	m_rombank1->set_entry(0);  // RAM banks are undefined on startup
	322	m_rombank2->set_entry(1);
	323	m_rombank3->set_entry(2);
	324	m_fixedrombank->set_entry(0);
	325	}
	326
	327	static SLOT_INTERFACE_START( gimix_floppies )
	328	SLOT_INTERFACE( "525dd", FLOPPY_525_DD )
	329	SLOT_INTERFACE_END
	330
	331	#define MCFG_ADDRESS_BANK(tag) \
	332	MCFG_DEVICE_ADD(tag, ADDRESS_MAP_BANK, 0) \
	333	MCFG_DEVICE_PROGRAM_MAP(gimix_banked_mem) \
	334	MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE) \
	335	MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8) \
	336	MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
	337
79	338	static MACHINE_CONFIG_START( gimix, gimix_state )
80	339	// basic machine hardware
81		MCFG_CPU_ADD("maincpu", M6809, 2000000)
	340	MCFG_CPU_ADD("maincpu", M6809E, XTAL_8MHz)
82	341	MCFG_CPU_PROGRAM_MAP(gimix_mem)
83	342	MCFG_CPU_IO_MAP(gimix_io)
84	343
85	344	/* video hardware */
86	345	MCFG_DEVICE_ADD("terminal", GENERIC_TERMINAL, 0)
87	346	MCFG_GENERIC_TERMINAL_KEYBOARD_CB(WRITE8(gimix_state, kbd_put))
	347
	348	/* rtc */
	349	MCFG_DEVICE_ADD("rtc", MM58167, XTAL_32_768kHz)
	350	MCFG_MM58167_IRQ_CALLBACK(WRITELINE(gimix_state,irq_w))
	351
	352	/* timer */
	353	MCFG_DEVICE_ADD("timer", PTM6840, XTAL_2MHz)  // clock is a guess
	354	MCFG_PTM6840_IRQ_CB(WRITELINE(gimix_state,irq_w))  // PCB pictures show both the RTC and timer set to generate IRQs (are jumper configurable)
	355
	356	/* floppy disks */
	357	MCFG_FD1797x_ADD("fdc",XTAL_2MHz)
	358	MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(gimix_state,fdc_irq_w))
	359	MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(gimix_state,fdc_drq_w))
	360	MCFG_FLOPPY_DRIVE_ADD("fdc:0", gimix_floppies, "525dd", floppy_image_device::default_floppy_formats)
	361	MCFG_FLOPPY_DRIVE_ADD("fdc:1", gimix_floppies, "525dd", floppy_image_device::default_floppy_formats)
	362
	363	/* banking */
	364	MCFG_ADDRESS_BANK("bank1")
	365	MCFG_ADDRESS_BANK("bank2")
	366	MCFG_ADDRESS_BANK("bank3")
	367	MCFG_ADDRESS_BANK("bank4")
	368	MCFG_ADDRESS_BANK("bank5")
	369	MCFG_ADDRESS_BANK("bank6")
	370	MCFG_ADDRESS_BANK("bank7")
	371	MCFG_ADDRESS_BANK("bank8")
	372	MCFG_ADDRESS_BANK("bank9")
	373	MCFG_ADDRESS_BANK("bank10")
	374	MCFG_ADDRESS_BANK("bank11")
	375	MCFG_ADDRESS_BANK("bank12")
	376	MCFG_ADDRESS_BANK("bank13")
	377	MCFG_ADDRESS_BANK("bank14")
	378	MCFG_ADDRESS_BANK("bank15")
	379	MCFG_ADDRESS_BANK("bank16")
	380
88	381	MACHINE_CONFIG_END
89	382
90	383	ROM_START( gimix )
91		ROM_REGION( 0x10000, "maincpu", 0)
	384	ROM_REGION( 0x10000, "roms", 0)
92	385
	386	/* CPU board U4: gimixf8.bin  - checksum 68DB - 2716 - GMXBUG09 V2.1 | (c)1981 GIMIX | $F800 I2716 */
	387	ROM_LOAD( "gimixf8.u4",  0x000000, 0x000800, CRC(7d60f838) SHA1(eb7546e8bbf50d33e181f3e86c3e4c5c9032cab2) )
93	388	/* CPU board U5: gimixv14.bin - checksum 97E2 - 2716 - GIMIX 6809 | AUTOBOOT | V1.4 I2716 */
94		ROM_LOAD( "gimixv14.u5", 0x000000, 0x000800, CRC(f795b8b9) SHA1(eda2de51cc298d94b36605437d900ce971b3b276) )
95
96		/* CPU board U4: gimixf8.bin  - checksum 68DB - 2716 - GMXBUG09 V2.1 | (c)1981 GIMIX | $F800 I2716 */
97		ROM_LOAD( "gimixf8.u4",  0x00f800, 0x000800, CRC(7d60f838) SHA1(eb7546e8bbf50d33e181f3e86c3e4c5c9032cab2) )
98
	389	ROM_LOAD( "gimixv14.u5", 0x000800, 0x000800, CRC(f795b8b9) SHA1(eda2de51cc298d94b36605437d900ce971b3b276) )
99	390	/* CPU board U6: os9l1v11.bin - checksum 2C84 - 2716 - OS-9tmL1 V1 | GIMIX P1 " (c)1982 MSC
100	391	CPU board U7: os9l1v12.bin - checksum 7694 - 2716 - OS-9tmL1 V1 | GIMIX P2-68 | (c)1982 MSC */
	392	ROM_LOAD( "os9l1v11.u6", 0x001000, 0x000800, CRC(0d6527a0) SHA1(1435a22581c6e9e0ae338071a72eed646f429530) )
	393	ROM_LOAD( "os9l1v12.u7", 0x001800, 0x000800, CRC(b3c65feb) SHA1(19d1ea1e84473b25c95cbb8449e6b9828567e998) )
101	394
102		ROM_LOAD( "os9l1v11.u6", 0x002000, 0x000800, CRC(0d6527a0) SHA1(1435a22581c6e9e0ae338071a72eed646f429530) )
103		ROM_LOAD( "os9l1v12.u7", 0x003000, 0x000800, CRC(b3c65feb) SHA1(19d1ea1e84473b25c95cbb8449e6b9828567e998) )
104
105	395	/* Hard drive controller board 2 (XEBEC board) 11H: gimixhd.bin - checksum 2436 - 2732 - 104521D */
106
107		ROM_LOAD( "gimixhd.h11",  0x004000, 0x001000, CRC(35c12201) SHA1(51ac9052f9757d79c7f5bd3aa5d8421e98cfcc37) )
	396	ROM_REGION( 0x10000, "xebec", 0)
	397	ROM_LOAD( "gimixhd.h11",  0x000000, 0x001000, CRC(35c12201) SHA1(51ac9052f9757d79c7f5bd3aa5d8421e98cfcc37) )
108	398	ROM_END
109	399
110	400	COMP( 1980, gimix,    0,      0,      gimix,        gimix, driver_device, 0,      "Gimix",  "Gimix 6809 System",  GAME_IS_SKELETON | GAME_NOT_WORKING | GAME_NO_SOUND )

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