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r31053 Friday 20th June, 2014 at 23:41:14 UTC by hap
tmpz84c011c small cleanup.
note: if you want a handler for logging unmapped read/write, put it in the driver machine config, like we do with 8255, for example:
MCFG_I8255_OUT_PORTB_CB(LOGGER("PPI8255 - unmapped write port B", 0))
[src/emu/cpu/z80]tmpz84c011.c tmpz84c011.h

trunk/src/emu/cpu/z80/tmpz84c011.c
r31052r31053
1/***************************************************************************
12
3    Toshiba TMPZ84C011, TLCS-Z80 ASSP Family
4    Z80 CPU, CTC, CGC(6/8MHz), I/O8x5
5   
6    TODO:
7    - CGC (clock generator/controller)
8
9***************************************************************************/
10
211#include "tmpz84c011.h"
312
4// how do we actually install default handlers for logging?
5/*
6READ8_MEMBER(tmpz84c011_device::porta_default_r) { logerror("%s read port A but no handler assigned\n", machine().describe_context()); return 0xff; }
7READ8_MEMBER(tmpz84c011_device::portb_default_r) { logerror("%s read port B but no handler assigned\n", machine().describe_context()); return 0xff; }
8READ8_MEMBER(tmpz84c011_device::portc_default_r) { logerror("%s read port C but no handler assigned\n", machine().describe_context()); return 0xff; }
9READ8_MEMBER(tmpz84c011_device::portd_default_r) { logerror("%s read port D but no handler assigned\n", machine().describe_context()); return 0xff; }
10READ8_MEMBER(tmpz84c011_device::porte_default_r) { logerror("%s read port E but no handler assigned\n", machine().describe_context()); return 0xff; }
13const device_type TMPZ84C011 = &device_creator<tmpz84c011_device>;
1114
12WRITE8_MEMBER(tmpz84c011_device::porta_default_w) { logerror("%s write %02x to port A but no handler assigned\n", machine().describe_context(), data); }
13WRITE8_MEMBER(tmpz84c011_device::portb_default_w) { logerror("%s write %02x to port B but no handler assigned\n", machine().describe_context(), data); }
14WRITE8_MEMBER(tmpz84c011_device::portc_default_w) { logerror("%s write %02x to port C but no handler assigned\n", machine().describe_context(), data); }
15WRITE8_MEMBER(tmpz84c011_device::portd_default_w) { logerror("%s write %02x to port D but no handler assigned\n", machine().describe_context(), data); }
16WRITE8_MEMBER(tmpz84c011_device::porte_default_w) { logerror("%s write %02x to port E but no handler assigned\n", machine().describe_context(), data); }
17*/
15static ADDRESS_MAP_START( tmpz84c011_internal_io_map, AS_IO, 8, tmpz84c011_device )
16   AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("ctc", z80ctc_device, read, write) AM_MIRROR(0xff00)
1817
19READ8_MEMBER(tmpz84c011_device::tmpz84c011_pio_r)
18   AM_RANGE(0x50, 0x50) AM_READWRITE(tmpz84c011_pa_r, tmpz84c011_pa_w) AM_MIRROR(0xff00)
19   AM_RANGE(0x51, 0x51) AM_READWRITE(tmpz84c011_pb_r, tmpz84c011_pb_w) AM_MIRROR(0xff00)
20   AM_RANGE(0x52, 0x52) AM_READWRITE(tmpz84c011_pc_r, tmpz84c011_pc_w) AM_MIRROR(0xff00)
21   AM_RANGE(0x30, 0x30) AM_READWRITE(tmpz84c011_pd_r, tmpz84c011_pd_w) AM_MIRROR(0xff00)
22   AM_RANGE(0x40, 0x40) AM_READWRITE(tmpz84c011_pe_r, tmpz84c011_pe_w) AM_MIRROR(0xff00)
23   AM_RANGE(0x54, 0x54) AM_READWRITE(tmpz84c011_dir_pa_r, tmpz84c011_dir_pa_w) AM_MIRROR(0xff00)
24   AM_RANGE(0x55, 0x55) AM_READWRITE(tmpz84c011_dir_pb_r, tmpz84c011_dir_pb_w) AM_MIRROR(0xff00)
25   AM_RANGE(0x56, 0x56) AM_READWRITE(tmpz84c011_dir_pc_r, tmpz84c011_dir_pc_w) AM_MIRROR(0xff00)
26   AM_RANGE(0x34, 0x34) AM_READWRITE(tmpz84c011_dir_pd_r, tmpz84c011_dir_pd_w) AM_MIRROR(0xff00)
27   AM_RANGE(0x44, 0x44) AM_READWRITE(tmpz84c011_dir_pe_r, tmpz84c011_dir_pe_w) AM_MIRROR(0xff00)
28ADDRESS_MAP_END
29
30
31tmpz84c011_device::tmpz84c011_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
32   : z80_device(mconfig, TMPZ84C011, "TMPZ84C011", tag, owner, clock, "tmpz84c011", __FILE__),
33   m_io_space_config( "io", ENDIANNESS_LITTLE, 8, 16, 0, ADDRESS_MAP_NAME( tmpz84c011_internal_io_map ) ),
34   m_outportsa(*this),
35   m_outportsb(*this),
36   m_outportsc(*this),
37   m_outportsd(*this),
38   m_outportse(*this),
39   m_inportsa(*this),
40   m_inportsb(*this),
41   m_inportsc(*this),
42   m_inportsd(*this),
43   m_inportse(*this),
44   m_intr_cb(*this),
45   m_zc0_cb(*this),
46   m_zc1_cb(*this),
47   m_zc2_cb(*this)
2048{
21   int portdata = 0xff;
49   memset(m_pio_dir, 0, 5);
50   memset(m_pio_latch, 0, 5);
51}
2252
23   switch (offset)
24   {
25      case 0:         /* PA_0 */
26         portdata = m_inports0();
27         break;
28      case 1:         /* PB_0 */
29         portdata = m_inports1();
30         break;
31      case 2:         /* PC_0 */
32         portdata = m_inports2();
33         break;
34      case 3:         /* PD_0 */
35         portdata = m_inports3();
36         break;
37      case 4:         /* PE_0 */
38         portdata = m_inports4();
39         break;
40   }
4153
42   return portdata;
54//-------------------------------------------------
55//  device_start - device-specific startup
56//-------------------------------------------------
57
58void tmpz84c011_device::device_start()
59{
60   z80_device::device_start();
61
62   // resolve callbacks
63   m_outportsa.resolve_safe();
64   m_outportsb.resolve_safe();
65   m_outportsc.resolve_safe();
66   m_outportsd.resolve_safe();
67   m_outportse.resolve_safe();
68
69   m_inportsa.resolve_safe(0);
70   m_inportsb.resolve_safe(0);
71   m_inportsc.resolve_safe(0);
72   m_inportsd.resolve_safe(0);
73   m_inportse.resolve_safe(0);
74
75   m_intr_cb.resolve_safe();
76   m_zc0_cb.resolve_safe();
77   m_zc1_cb.resolve_safe();
78   m_zc2_cb.resolve_safe();
79
80   // register for save states
81   save_item(NAME(m_pio_dir[0]));
82   save_item(NAME(m_pio_latch[0]));
83   save_item(NAME(m_pio_dir[1]));
84   save_item(NAME(m_pio_latch[1]));
85   save_item(NAME(m_pio_dir[2]));
86   save_item(NAME(m_pio_latch[2]));
87   save_item(NAME(m_pio_dir[3]));
88   save_item(NAME(m_pio_latch[3]));
89   save_item(NAME(m_pio_dir[4]));
90   save_item(NAME(m_pio_latch[4]));
4391}
4492
45WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_pio_w)
93
94//-------------------------------------------------
95//  device_reset - device-specific reset
96//-------------------------------------------------
97
98void tmpz84c011_device::device_reset()
4699{
47   switch (offset)
48   {
49      case 0:         /* PA_0 */
50         m_outports0(data);
51         break;
52      case 1:         /* PB_0 */
53         m_outports1(data);
54         break;
55      case 2:         /* PC_0 */
56         m_outports2(data);
57         break;
58      case 3:         /* PD_0 */
59         m_outports3(data);
60         break;
61      case 4:         /* PE_0 */
62         m_outports4(data);
63         break;
64   }
100   z80_device::device_reset();
101
102   // initialize TMPZ84C011 PIO
103   tmpz84c011_dir_pa_w(*m_io, 0, 0); tmpz84c011_pa_w(*m_io, 0, 0xff);
104   tmpz84c011_dir_pb_w(*m_io, 0, 0); tmpz84c011_pb_w(*m_io, 0, 0xff);
105   tmpz84c011_dir_pc_w(*m_io, 0, 0); tmpz84c011_pc_w(*m_io, 0, 0xff);
106   tmpz84c011_dir_pd_w(*m_io, 0, 0); tmpz84c011_pd_w(*m_io, 0, 0xff);
107   tmpz84c011_dir_pe_w(*m_io, 0, 0); tmpz84c011_pe_w(*m_io, 0, 0xff);
65108}
66109
110
67111/* CPU interface */
68READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pa_r)
112READ8_MEMBER(tmpz84c011_device::tmpz84c011_pa_r)
69113{
70   return (tmpz84c011_pio_r(space,0) & ~m_pio_dir[0]) | (m_pio_latch[0] & m_pio_dir[0]);
114   return (m_inportsa() & ~m_pio_dir[0]) | (m_pio_latch[0] & m_pio_dir[0]);
71115}
72116
73READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pb_r)
117READ8_MEMBER(tmpz84c011_device::tmpz84c011_pb_r)
74118{
75   return (tmpz84c011_pio_r(space,1) & ~m_pio_dir[1]) | (m_pio_latch[1] & m_pio_dir[1]);
119   return (m_inportsb() & ~m_pio_dir[1]) | (m_pio_latch[1] & m_pio_dir[1]);
76120}
77121
78READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pc_r)
122READ8_MEMBER(tmpz84c011_device::tmpz84c011_pc_r)
79123{
80   return (tmpz84c011_pio_r(space,2) & ~m_pio_dir[2]) | (m_pio_latch[2] & m_pio_dir[2]);
124   return (m_inportsc() & ~m_pio_dir[2]) | (m_pio_latch[2] & m_pio_dir[2]);
81125}
82126
83READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pd_r)
127READ8_MEMBER(tmpz84c011_device::tmpz84c011_pd_r)
84128{
85   return (tmpz84c011_pio_r(space,3) & ~m_pio_dir[3]) | (m_pio_latch[3] & m_pio_dir[3]);
129   return (m_inportsd() & ~m_pio_dir[3]) | (m_pio_latch[3] & m_pio_dir[3]);
86130}
87131
88READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pe_r)
132READ8_MEMBER(tmpz84c011_device::tmpz84c011_pe_r)
89133{
90   return (tmpz84c011_pio_r(space,4) & ~m_pio_dir[4]) | (m_pio_latch[4] & m_pio_dir[4]);
134   return (m_inportse() & ~m_pio_dir[4]) | (m_pio_latch[4] & m_pio_dir[4]);
91135}
92136
93WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pa_w)
137WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_pa_w)
94138{
95139   m_pio_latch[0] = data;
96   tmpz84c011_pio_w(space, 0, data);
140   m_outportsa(data | ~m_pio_dir[0]);
97141}
98142
99WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pb_w)
143WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_pb_w)
100144{
101145   m_pio_latch[1] = data;
102   tmpz84c011_pio_w(space, 1, data);
146   m_outportsb(data | ~m_pio_dir[1]);
103147}
104WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pc_w)
148WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_pc_w)
105149{
106150   m_pio_latch[2] = data;
107   tmpz84c011_pio_w(space, 2, data);
151   m_outportsc(data | ~m_pio_dir[2]);
108152}
109153
110WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pd_w)
154WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_pd_w)
111155{
112156   m_pio_latch[3] = data;
113   tmpz84c011_pio_w(space, 3, data);
157   m_outportsd(data | ~m_pio_dir[3]);
114158}
115159
116WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pe_w)
160WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_pe_w)
117161{
118162   m_pio_latch[4] = data;
119   tmpz84c011_pio_w(space, 4, data);
163   m_outportse(data | ~m_pio_dir[4]);
120164}
121165
122READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pa_r)
166READ8_MEMBER(tmpz84c011_device::tmpz84c011_dir_pa_r)
123167{
124168   return m_pio_dir[0];
125169}
126170
127READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pb_r)
171READ8_MEMBER(tmpz84c011_device::tmpz84c011_dir_pb_r)
128172{
129173   return m_pio_dir[1];
130174}
131175
132READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pc_r)
176READ8_MEMBER(tmpz84c011_device::tmpz84c011_dir_pc_r)
133177{
134178   return m_pio_dir[2];
135179}
136180
137READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pd_r)
181READ8_MEMBER(tmpz84c011_device::tmpz84c011_dir_pd_r)
138182{
139183   return m_pio_dir[3];
140184}
141185
142READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pe_r)
186READ8_MEMBER(tmpz84c011_device::tmpz84c011_dir_pe_r)
143187{
144188   return m_pio_dir[4];
145189}
146190
147WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pa_w)
191WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_dir_pa_w)
148192{
149193   m_pio_dir[0] = data;
150194}
151195
152WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pb_w)
196WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_dir_pb_w)
153197{
154198   m_pio_dir[1] = data;
155199}
156200
157WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pc_w)
201WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_dir_pc_w)
158202{
159203   m_pio_dir[2] = data;
160204}
161205
162WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pd_w)
206WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_dir_pd_w)
163207{
164208   m_pio_dir[3] = data;
165209}
166210
167WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pe_w)
211WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_dir_pe_w)
168212{
169213   m_pio_dir[4] = data;
170214}
171215
172216
173
174static ADDRESS_MAP_START( tmpz84c011_internal_io_map, AS_IO, 8, tmpz84c011_device )
175   AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("ctc", z80ctc_device, read, write) AM_MIRROR(0xff00)
176
177   AM_RANGE(0x50, 0x50) AM_READWRITE(tmpz84c011_0_pa_r, tmpz84c011_0_pa_w) AM_MIRROR(0xff00)
178   AM_RANGE(0x51, 0x51) AM_READWRITE(tmpz84c011_0_pb_r, tmpz84c011_0_pb_w) AM_MIRROR(0xff00)
179   AM_RANGE(0x52, 0x52) AM_READWRITE(tmpz84c011_0_pc_r, tmpz84c011_0_pc_w) AM_MIRROR(0xff00)
180   AM_RANGE(0x30, 0x30) AM_READWRITE(tmpz84c011_0_pd_r, tmpz84c011_0_pd_w) AM_MIRROR(0xff00)
181   AM_RANGE(0x40, 0x40) AM_READWRITE(tmpz84c011_0_pe_r, tmpz84c011_0_pe_w) AM_MIRROR(0xff00)
182   AM_RANGE(0x54, 0x54) AM_READWRITE(tmpz84c011_0_dir_pa_r, tmpz84c011_0_dir_pa_w) AM_MIRROR(0xff00)
183   AM_RANGE(0x55, 0x55) AM_READWRITE(tmpz84c011_0_dir_pb_r, tmpz84c011_0_dir_pb_w) AM_MIRROR(0xff00)
184   AM_RANGE(0x56, 0x56) AM_READWRITE(tmpz84c011_0_dir_pc_r, tmpz84c011_0_dir_pc_w) AM_MIRROR(0xff00)
185   AM_RANGE(0x34, 0x34) AM_READWRITE(tmpz84c011_0_dir_pd_r, tmpz84c011_0_dir_pd_w) AM_MIRROR(0xff00)
186   AM_RANGE(0x44, 0x44) AM_READWRITE(tmpz84c011_0_dir_pe_r, tmpz84c011_0_dir_pe_w) AM_MIRROR(0xff00)
187ADDRESS_MAP_END
188
189
190tmpz84c011_device::tmpz84c011_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
191   : z80_device(mconfig, TMPZ84C011, "TMPZ84C011", tag, owner, clock, "tmpz84c011", __FILE__),
192   m_io_space_config( "io", ENDIANNESS_LITTLE, 8, 16, 0, ADDRESS_MAP_NAME( tmpz84c011_internal_io_map ) ),
193   m_outports0(*this),
194   m_outports1(*this),
195   m_outports2(*this),
196   m_outports3(*this),
197   m_outports4(*this),
198   m_inports0(*this),
199   m_inports1(*this),
200   m_inports2(*this),
201   m_inports3(*this),
202   m_inports4(*this),
203   m_intr_cb(*this),
204   m_zc0_cb(*this),
205   m_zc1_cb(*this),
206   m_zc2_cb(*this)
207{
208}
209
210217WRITE_LINE_MEMBER( tmpz84c011_device::intr_cb_trampoline_w ) { m_intr_cb(state); }
211218WRITE_LINE_MEMBER( tmpz84c011_device::zc0_cb_trampoline_w ) { m_zc0_cb(state); }
212219WRITE_LINE_MEMBER( tmpz84c011_device::zc1_cb_trampoline_w ) { m_zc1_cb(state); }
213220WRITE_LINE_MEMBER( tmpz84c011_device::zc2_cb_trampoline_w ) { m_zc2_cb(state); }
214221
215222
216
217const device_type TMPZ84C011 = &device_creator<tmpz84c011_device>;
218
219223static MACHINE_CONFIG_FRAGMENT( tmpz84c011 )
220224   MCFG_DEVICE_ADD("ctc", Z80CTC, DERIVED_CLOCK(1,1) )
221225   MCFG_Z80CTC_INTR_CB(WRITELINE(tmpz84c011_device, intr_cb_trampoline_w))
222226   MCFG_Z80CTC_ZC0_CB(WRITELINE(tmpz84c011_device, zc0_cb_trampoline_w))
223227   MCFG_Z80CTC_ZC1_CB(WRITELINE(tmpz84c011_device, zc1_cb_trampoline_w))
224228   MCFG_Z80CTC_ZC2_CB(WRITELINE(tmpz84c011_device, zc2_cb_trampoline_w))
225
226
227229MACHINE_CONFIG_END
228230
229231machine_config_constructor tmpz84c011_device::device_mconfig_additions() const
230232{
231233   return MACHINE_CONFIG_NAME( tmpz84c011 );
232234}
233
234
235void tmpz84c011_device::device_start()
236{
237   z80_device::device_start();
238
239   m_outports0.resolve_safe();
240   m_outports1.resolve_safe();
241   m_outports2.resolve_safe();
242   m_outports3.resolve_safe();
243   m_outports4.resolve_safe();
244
245   m_inports0.resolve_safe(0);
246   m_inports1.resolve_safe(0);
247   m_inports2.resolve_safe(0);
248   m_inports3.resolve_safe(0);
249   m_inports4.resolve_safe(0);
250
251   m_intr_cb.resolve_safe();
252   m_zc0_cb.resolve_safe();
253   m_zc1_cb.resolve_safe();
254   m_zc2_cb.resolve_safe();
255
256   save_item(NAME(m_pio_dir[0]));
257   save_item(NAME(m_pio_latch[0]));
258   save_item(NAME(m_pio_dir[1]));
259   save_item(NAME(m_pio_latch[1]));
260   save_item(NAME(m_pio_dir[2]));
261   save_item(NAME(m_pio_latch[2]));
262   save_item(NAME(m_pio_dir[3]));
263   save_item(NAME(m_pio_latch[3]));
264   save_item(NAME(m_pio_dir[4]));
265   save_item(NAME(m_pio_latch[4]));
266
267
268}
269
270void tmpz84c011_device::device_reset()
271{
272   z80_device::device_reset();
273
274   // initialize TMPZ84C011 PIO
275   for (int i = 0; i < 5; i++)
276   {
277      m_pio_dir[i] = m_pio_latch[i] = 0;
278      tmpz84c011_pio_w(*m_io, i, 0);
279   }
280}
281
282
trunk/src/emu/cpu/z80/tmpz84c011.h
r31052r31053
1/***************************************************************************
12
3    Toshiba TMPZ84C011, TLCS-Z80 ASSP Family
4    Z80 CPU, CTC, CGC(6/8MHz), I/O8x5
5
6***************************************************************************/
7
28#include "emu.h"
39#include "z80.h"
410
11
12// TMPZ84C011 PIO callbacks
513#define MCFG_TMPZ84C011_PORTA_READ_CB(_devcb) \
6   devcb = &tmpz84c011_device::set_inports0_cb(*device, DEVCB_##_devcb);
14   devcb = &tmpz84c011_device::set_inportsa_cb(*device, DEVCB_##_devcb);
715
816#define MCFG_TMPZ84C011_PORTB_READ_CB(_devcb) \
9   devcb = &tmpz84c011_device::set_inports1_cb(*device, DEVCB_##_devcb);
17   devcb = &tmpz84c011_device::set_inportsb_cb(*device, DEVCB_##_devcb);
1018
1119#define MCFG_TMPZ84C011_PORTC_READ_CB(_devcb) \
12   devcb = &tmpz84c011_device::set_inports2_cb(*device, DEVCB_##_devcb);
20   devcb = &tmpz84c011_device::set_inportsc_cb(*device, DEVCB_##_devcb);
1321
1422#define MCFG_TMPZ84C011_PORTD_READ_CB(_devcb) \
15   devcb = &tmpz84c011_device::set_inports3_cb(*device, DEVCB_##_devcb);
23   devcb = &tmpz84c011_device::set_inportsd_cb(*device, DEVCB_##_devcb);
1624
1725#define MCFG_TMPZ84C011_PORTE_READ_CB(_devcb) \
18   devcb = &tmpz84c011_device::set_inports4_cb(*device, DEVCB_##_devcb);
26   devcb = &tmpz84c011_device::set_inportse_cb(*device, DEVCB_##_devcb);
1927
2028
2129#define MCFG_TMPZ84C011_PORTA_WRITE_CB(_devcb) \
22   devcb = &tmpz84c011_device::set_outports0_cb(*device, DEVCB_##_devcb);
30   devcb = &tmpz84c011_device::set_outportsa_cb(*device, DEVCB_##_devcb);
2331
2432#define MCFG_TMPZ84C011_PORTB_WRITE_CB(_devcb) \
25   devcb = &tmpz84c011_device::set_outports1_cb(*device, DEVCB_##_devcb);
33   devcb = &tmpz84c011_device::set_outportsb_cb(*device, DEVCB_##_devcb);
2634
2735#define MCFG_TMPZ84C011_PORTC_WRITE_CB(_devcb) \
28   devcb = &tmpz84c011_device::set_outports2_cb(*device, DEVCB_##_devcb);
36   devcb = &tmpz84c011_device::set_outportsc_cb(*device, DEVCB_##_devcb);
2937
3038#define MCFG_TMPZ84C011_PORTD_WRITE_CB(_devcb) \
31   devcb = &tmpz84c011_device::set_outports3_cb(*device, DEVCB_##_devcb);
39   devcb = &tmpz84c011_device::set_outportsd_cb(*device, DEVCB_##_devcb);
3240
3341#define MCFG_TMPZ84C011_PORTE_WRITE_CB(_devcb) \
34   devcb = &tmpz84c011_device::set_outports4_cb(*device, DEVCB_##_devcb);
42   devcb = &tmpz84c011_device::set_outportse_cb(*device, DEVCB_##_devcb);
3543
3644
45// CTC callbacks
3746#define MCFG_TMPZ84C011_Z80CTC_INTR_CB(_devcb) \
3847   devcb = &tmpz84c011_device::set_intr_callback(*device, DEVCB_##_devcb);
3948
r31052r31053
5261public:
5362   tmpz84c011_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32);
5463
55   template<class _Object> static devcb_base & set_outports0_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports0.set_callback(object); }
56   template<class _Object> static devcb_base & set_outports1_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports1.set_callback(object); }
57   template<class _Object> static devcb_base & set_outports2_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports2.set_callback(object); }
58   template<class _Object> static devcb_base & set_outports3_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports3.set_callback(object); }
59   template<class _Object> static devcb_base & set_outports4_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports4.set_callback(object); }
64   template<class _Object> static devcb_base & set_outportsa_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outportsa.set_callback(object); }
65   template<class _Object> static devcb_base & set_outportsb_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outportsb.set_callback(object); }
66   template<class _Object> static devcb_base & set_outportsc_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outportsc.set_callback(object); }
67   template<class _Object> static devcb_base & set_outportsd_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outportsd.set_callback(object); }
68   template<class _Object> static devcb_base & set_outportse_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outportse.set_callback(object); }
6069
61   template<class _Object> static devcb_base & set_inports0_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports0.set_callback(object); }
62   template<class _Object> static devcb_base & set_inports1_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports1.set_callback(object); }
63   template<class _Object> static devcb_base & set_inports2_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports2.set_callback(object); }
64   template<class _Object> static devcb_base & set_inports3_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports3.set_callback(object); }
65   template<class _Object> static devcb_base & set_inports4_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports4.set_callback(object); }
70   template<class _Object> static devcb_base & set_inportsa_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inportsa.set_callback(object); }
71   template<class _Object> static devcb_base & set_inportsb_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inportsb.set_callback(object); }
72   template<class _Object> static devcb_base & set_inportsc_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inportsc.set_callback(object); }
73   template<class _Object> static devcb_base & set_inportsd_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inportsd.set_callback(object); }
74   template<class _Object> static devcb_base & set_inportse_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inportse.set_callback(object); }
6675
6776   template<class _Object> static devcb_base &set_intr_callback(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_intr_cb.set_callback(object); }
6877   template<class _Object> static devcb_base &set_zc0_callback(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_zc0_cb.set_callback(object); }
6978   template<class _Object> static devcb_base &set_zc1_callback(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_zc1_cb.set_callback(object); }
7079   template<class _Object> static devcb_base &set_zc2_callback(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_zc2_cb.set_callback(object); }
7180
81   DECLARE_READ8_MEMBER(tmpz84c011_pa_r);
82   DECLARE_READ8_MEMBER(tmpz84c011_pb_r);
83   DECLARE_READ8_MEMBER(tmpz84c011_pc_r);
84   DECLARE_READ8_MEMBER(tmpz84c011_pd_r);
85   DECLARE_READ8_MEMBER(tmpz84c011_pe_r);
86   DECLARE_WRITE8_MEMBER(tmpz84c011_pa_w);
87   DECLARE_WRITE8_MEMBER(tmpz84c011_pb_w);
88   DECLARE_WRITE8_MEMBER(tmpz84c011_pc_w);
89   DECLARE_WRITE8_MEMBER(tmpz84c011_pd_w);
90   DECLARE_WRITE8_MEMBER(tmpz84c011_pe_w);
91   DECLARE_READ8_MEMBER(tmpz84c011_dir_pa_r);
92   DECLARE_READ8_MEMBER(tmpz84c011_dir_pb_r);
93   DECLARE_READ8_MEMBER(tmpz84c011_dir_pc_r);
94   DECLARE_READ8_MEMBER(tmpz84c011_dir_pd_r);
95   DECLARE_READ8_MEMBER(tmpz84c011_dir_pe_r);
96   DECLARE_WRITE8_MEMBER(tmpz84c011_dir_pa_w);
97   DECLARE_WRITE8_MEMBER(tmpz84c011_dir_pb_w);
98   DECLARE_WRITE8_MEMBER(tmpz84c011_dir_pc_w);
99   DECLARE_WRITE8_MEMBER(tmpz84c011_dir_pd_w);
100   DECLARE_WRITE8_MEMBER(tmpz84c011_dir_pe_w);
72101
73   DECLARE_READ8_MEMBER(tmpz84c011_pio_r);
74   DECLARE_WRITE8_MEMBER(tmpz84c011_pio_w);
75   DECLARE_READ8_MEMBER(tmpz84c011_0_pa_r);
76   DECLARE_READ8_MEMBER(tmpz84c011_0_pb_r);
77   DECLARE_READ8_MEMBER(tmpz84c011_0_pc_r);
78   DECLARE_READ8_MEMBER(tmpz84c011_0_pd_r);
79   DECLARE_READ8_MEMBER(tmpz84c011_0_pe_r);
80   DECLARE_WRITE8_MEMBER(tmpz84c011_0_pa_w);
81   DECLARE_WRITE8_MEMBER(tmpz84c011_0_pb_w);
82   DECLARE_WRITE8_MEMBER(tmpz84c011_0_pc_w);
83   DECLARE_WRITE8_MEMBER(tmpz84c011_0_pd_w);
84   DECLARE_WRITE8_MEMBER(tmpz84c011_0_pe_w);
85   DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pa_r);
86   DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pb_r);
87   DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pc_r);
88   DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pd_r);
89   DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pe_r);
90   DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pa_w);
91   DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pb_w);
92   DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pc_w);
93   DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pd_w);
94   DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pe_w);
95
96   DECLARE_READ8_MEMBER(porta_default_r);
97   DECLARE_READ8_MEMBER(portb_default_r);
98   DECLARE_READ8_MEMBER(portc_default_r);
99   DECLARE_READ8_MEMBER(portd_default_r);
100   DECLARE_READ8_MEMBER(porte_default_r);
101
102   DECLARE_WRITE8_MEMBER(porta_default_w);
103   DECLARE_WRITE8_MEMBER(portb_default_w);
104   DECLARE_WRITE8_MEMBER(portc_default_w);
105   DECLARE_WRITE8_MEMBER(portd_default_w);
106   DECLARE_WRITE8_MEMBER(porte_default_w);
107
108102   DECLARE_WRITE_LINE_MEMBER(intr_cb_trampoline_w);
109103   DECLARE_WRITE_LINE_MEMBER(zc0_cb_trampoline_w);
110104   DECLARE_WRITE_LINE_MEMBER(zc1_cb_trampoline_w);
r31052r31053
127121      }
128122   }
129123
130
124private:
131125   UINT8 m_pio_dir[5];
132126   UINT8 m_pio_latch[5];
133127
134private:
135   devcb_write8      m_outports0;
136   devcb_write8      m_outports1;
137   devcb_write8      m_outports2;
138   devcb_write8      m_outports3;
139   devcb_write8      m_outports4;
128   devcb_write8      m_outportsa;
129   devcb_write8      m_outportsb;
130   devcb_write8      m_outportsc;
131   devcb_write8      m_outportsd;
132   devcb_write8      m_outportse;
140133
141   devcb_read8       m_inports0;
142   devcb_read8       m_inports1;
143   devcb_read8       m_inports2;
144   devcb_read8       m_inports3;
145   devcb_read8       m_inports4;
134   devcb_read8       m_inportsa;
135   devcb_read8       m_inportsb;
136   devcb_read8       m_inportsc;
137   devcb_read8       m_inportsd;
138   devcb_read8       m_inportse;
146139
147140   devcb_write_line   m_intr_cb;              // interrupt callback
148141   devcb_write_line   m_zc0_cb;               // channel 0 zero crossing callbacks
149142   devcb_write_line   m_zc1_cb;               // channel 1 zero crossing callbacks
150143   devcb_write_line   m_zc2_cb;               // channel 2 zero crossing callbacks
151
152144};
153145
154146extern const device_type TMPZ84C011;

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