trunk/src/emu/cpu/lr35902/lr35902.c
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| 304 | 304 | |
| 305 | 305 | |
| 306 | 306 | /************************************************************/ |
| 307 | | /*** Execute lr35902 code for cycles cycles, return nr of ***/ |
| 308 | | /*** cycles actually executed. ***/ |
| 307 | /*** Execute lr35902 code for m_icount cycles. ***/ |
| 309 | 308 | /************************************************************/ |
| 310 | 309 | void lr35902_cpu_device::execute_run() |
| 311 | 310 | { |
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| 316 | 315 | /* Execute instruction */ |
| 317 | 316 | switch( m_op ) { |
| 318 | 317 | #include "opc_main.inc" |
| 318 | default: |
| 319 | // actually this should lock up the cpu! |
| 320 | logerror("LR35902: Illegal opcode $%02X @ %04X\n", m_op, m_PC); |
| 321 | break; |
| 319 | 322 | } |
| 320 | 323 | } else { |
| 321 | 324 | /* Fetch and count cycles */ |
trunk/src/emu/cpu/lr35902/opc_main.inc
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| 62 | 62 | m_F=f; \ |
| 63 | 63 | } |
| 64 | 64 | |
| 65 | | /* |
| 66 | | #define CP_A_X(x) \ |
| 67 | | { \ |
| 68 | | register UINT16 r; \ |
| 69 | | register UINT8 f; \ |
| 70 | | r=(UINT16)(m_A-(x)); \ |
| 71 | | if( ((UINT8)r)==0 ) \ |
| 72 | | f=FLAG_N|FLAG_Z; \ |
| 73 | | else \ |
| 74 | | f=FLAG_N; \ |
| 75 | | f|=(UINT8)((r>>8)&FLAG_C); \ |
| 76 | | if( (r^m_A^(x))&0x10 ) \ |
| 77 | | f|=FLAG_H; \ |
| 78 | | m_F=f; \ |
| 79 | | } |
| 80 | | */ |
| 81 | | |
| 82 | 65 | #define CP_A_X(x) \ |
| 83 | 66 | { \ |
| 84 | 67 | register UINT16 r1,r2; \ |
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| 147 | 130 | m_SP--; \ |
| 148 | 131 | mem_write_byte( m_SP, y ); |
| 149 | 132 | |
| 133 | /**********************************************************/ |
| 134 | |
| 150 | 135 | case 0x00: /* NOP */ |
| 151 | 136 | break; |
| 152 | 137 | |
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| 1280 | 1265 | } |
| 1281 | 1266 | } |
| 1282 | 1267 | break; |
| 1283 | | case 0xD3: /* EH? */ |
| 1284 | | break; |
| 1285 | 1268 | case 0xD4: /* CALL NC,n16 */ |
| 1286 | 1269 | { |
| 1287 | 1270 | UINT16 addr = mem_read_word( m_PC ); |
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| 1338 | 1321 | } |
| 1339 | 1322 | } |
| 1340 | 1323 | break; |
| 1341 | | case 0xDB: /* EH? */ |
| 1342 | | break; |
| 1343 | 1324 | case 0xDC: /* CALL C,n16 */ |
| 1344 | 1325 | { |
| 1345 | 1326 | UINT16 addr = mem_read_word( m_PC ); |
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| 1354 | 1335 | } |
| 1355 | 1336 | } |
| 1356 | 1337 | break; |
| 1357 | | case 0xDD: /* EH? */ |
| 1358 | | break; |
| 1359 | 1338 | case 0xDE: /* SBC A,n8 */ |
| 1360 | 1339 | |
| 1361 | 1340 | x = mem_read_byte( m_PC++ ); |
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| 1380 | 1359 | |
| 1381 | 1360 | mem_write_byte( 0xFF00 + m_C, m_A ); |
| 1382 | 1361 | break; |
| 1383 | | case 0xE3: /* EH? */ |
| 1384 | | break; |
| 1385 | | case 0xE4: /* EH? */ |
| 1386 | | break; |
| 1387 | 1362 | case 0xE5: /* PUSH HL */ |
| 1388 | 1363 | PUSH( m_H, m_L ); |
| 1389 | 1364 | cycles_passed( 4 ); |
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| 1438 | 1413 | mem_write_byte( mem_read_word( m_PC ), m_A ); |
| 1439 | 1414 | m_PC += 2; |
| 1440 | 1415 | break; |
| 1441 | | case 0xEB: /* EH? */ |
| 1442 | | break; |
| 1443 | | case 0xEC: /* EH? */ |
| 1444 | | break; |
| 1445 | | case 0xED: /* EH? */ |
| 1446 | | break; |
| 1447 | 1416 | case 0xEE: /* XOR A,n8 */ |
| 1448 | 1417 | |
| 1449 | 1418 | x = mem_read_byte( m_PC++ ); |
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| 1473 | 1442 | m_ei_delay = 0; |
| 1474 | 1443 | m_enable &= ~IME; |
| 1475 | 1444 | break; |
| 1476 | | case 0xF4: /* EH? */ |
| 1477 | | break; |
| 1478 | 1445 | case 0xF5: /* PUSH AF */ |
| 1479 | 1446 | m_F &= 0xF0; |
| 1480 | 1447 | PUSH( m_A, m_F ); |
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| 1540 | 1507 | m_enable |= IME; |
| 1541 | 1508 | m_ei_delay = 1; |
| 1542 | 1509 | break; |
| 1543 | | case 0xFC: /* EH? */ |
| 1544 | | break; |
| 1545 | | case 0xFD: /* EH? */ |
| 1546 | | break; |
| 1547 | 1510 | case 0xFE: /* CP A,n8 */ |
| 1548 | 1511 | x = mem_read_byte( m_PC++ ); |
| 1549 | 1512 | CP_A_X (x) |