Previous

199869 Revisions

Next

r30942 Wednesday 11th June, 2014 at 13:50:26 UTC by David Haywood
move tmpz84c011 specifics to its own files, make z80ctc a subdevice rather than adding it separately it in each driver using a tmpz84c011. (nw)

[src/emu/cpu]	cpu.mak
[src/emu/cpu/z80]	tmpz84c011.c* tmpz84c011.h* z80.c z80.h
[src/mame/drivers]	csplayh5.c kenseim.c nbmj9195.c niyanpai.c

trunk/src/emu/cpu/cpu.mak

r30941	r30942
2229	2229	ifneq ($(filter Z80,$(CPUS)),)
2230	2230	OBJDIRS += $(CPUOBJ)/z80
2231	2231	CPUOBJS += $(CPUOBJ)/z80/z80.o $(CPUOBJ)/z80/tlcs_z80.o $(CPUOBJ)/z80/z80daisy.o
	2232	CPUOBJS += $(CPUOBJ)/z80/tmpz84c011.o
2232	2233	DASMOBJS += $(CPUOBJ)/z80/z80dasm.o
2233	2234	endif
2234	2235

trunk/src/emu/cpu/z80/tmpz84c011.h

r0	r30942
	1
	2	#include "emu.h"
	3	#include "z80.h"
	4
	5	#define MCFG_TMPZ84C011_PORTA_READ_CB(_devcb) \
	6	devcb = &tmpz84c011_device::set_inports0_cb(*device, DEVCB_##_devcb);
	7
	8	#define MCFG_TMPZ84C011_PORTB_READ_CB(_devcb) \
	9	devcb = &tmpz84c011_device::set_inports1_cb(*device, DEVCB_##_devcb);
	10
	11	#define MCFG_TMPZ84C011_PORTC_READ_CB(_devcb) \
	12	devcb = &tmpz84c011_device::set_inports2_cb(*device, DEVCB_##_devcb);
	13
	14	#define MCFG_TMPZ84C011_PORTD_READ_CB(_devcb) \
	15	devcb = &tmpz84c011_device::set_inports3_cb(*device, DEVCB_##_devcb);
	16
	17	#define MCFG_TMPZ84C011_PORTE_READ_CB(_devcb) \
	18	devcb = &tmpz84c011_device::set_inports4_cb(*device, DEVCB_##_devcb);
	19
	20
	21	#define MCFG_TMPZ84C011_PORTA_WRITE_CB(_devcb) \
	22	devcb = &tmpz84c011_device::set_outports0_cb(*device, DEVCB_##_devcb);
	23
	24	#define MCFG_TMPZ84C011_PORTB_WRITE_CB(_devcb) \
	25	devcb = &tmpz84c011_device::set_outports1_cb(*device, DEVCB_##_devcb);
	26
	27	#define MCFG_TMPZ84C011_PORTC_WRITE_CB(_devcb) \
	28	devcb = &tmpz84c011_device::set_outports2_cb(*device, DEVCB_##_devcb);
	29
	30	#define MCFG_TMPZ84C011_PORTD_WRITE_CB(_devcb) \
	31	devcb = &tmpz84c011_device::set_outports3_cb(*device, DEVCB_##_devcb);
	32
	33	#define MCFG_TMPZ84C011_PORTE_WRITE_CB(_devcb) \
	34	devcb = &tmpz84c011_device::set_outports4_cb(*device, DEVCB_##_devcb);
	35
	36
	37	#define MCFG_TMPZ84C011_Z80CTC_INTR_CB(_devcb) \
	38	devcb = &tmpz84c011_device::set_intr_callback(*device, DEVCB_##_devcb);
	39
	40
	41	#define MCFG_TMPZ84C011_Z80CTC_ZC0_CB(_devcb) \
	42	devcb = &tmpz84c011_device::set_zc0_callback(*device, DEVCB_##_devcb);
	43
	44	#define MCFG_TMPZ84C011_Z80CTC_ZC1_CB(_devcb) \
	45	devcb = &tmpz84c011_device::set_zc1_callback(*device, DEVCB_##_devcb);
	46
	47	#define MCFG_TMPZ84C011_Z80CTC_ZC2_CB(_devcb) \
	48	devcb = &tmpz84c011_device::set_zc2_callback(*device, DEVCB_##_devcb);
	49
	50	class tmpz84c011_device : public z80_device
	51	{
	52	public:
	53	tmpz84c011_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32);
	54
	55	template<class _Object> static devcb_base & set_outports0_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports0.set_callback(object); }
	56	template<class _Object> static devcb_base & set_outports1_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports1.set_callback(object); }
	57	template<class _Object> static devcb_base & set_outports2_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports2.set_callback(object); }
	58	template<class _Object> static devcb_base & set_outports3_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports3.set_callback(object); }
	59	template<class _Object> static devcb_base & set_outports4_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports4.set_callback(object); }
	60
	61	template<class _Object> static devcb_base & set_inports0_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports0.set_callback(object); }
	62	template<class _Object> static devcb_base & set_inports1_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports1.set_callback(object); }
	63	template<class _Object> static devcb_base & set_inports2_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports2.set_callback(object); }
	64	template<class _Object> static devcb_base & set_inports3_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports3.set_callback(object); }
	65	template<class _Object> static devcb_base & set_inports4_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports4.set_callback(object); }
	66
	67	template<class _Object> static devcb_base &set_intr_callback(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_intr_cb.set_callback(object); }
	68	template<class _Object> static devcb_base &set_zc0_callback(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_zc0_cb.set_callback(object); }
	69	template<class _Object> static devcb_base &set_zc1_callback(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_zc1_cb.set_callback(object); }
	70	template<class _Object> static devcb_base &set_zc2_callback(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_zc2_cb.set_callback(object); }
	71
	72
	73	DECLARE_READ8_MEMBER(tmpz84c011_pio_r);
	74	DECLARE_WRITE8_MEMBER(tmpz84c011_pio_w);
	75	DECLARE_READ8_MEMBER(tmpz84c011_0_pa_r);
	76	DECLARE_READ8_MEMBER(tmpz84c011_0_pb_r);
	77	DECLARE_READ8_MEMBER(tmpz84c011_0_pc_r);
	78	DECLARE_READ8_MEMBER(tmpz84c011_0_pd_r);
	79	DECLARE_READ8_MEMBER(tmpz84c011_0_pe_r);
	80	DECLARE_WRITE8_MEMBER(tmpz84c011_0_pa_w);
	81	DECLARE_WRITE8_MEMBER(tmpz84c011_0_pb_w);
	82	DECLARE_WRITE8_MEMBER(tmpz84c011_0_pc_w);
	83	DECLARE_WRITE8_MEMBER(tmpz84c011_0_pd_w);
	84	DECLARE_WRITE8_MEMBER(tmpz84c011_0_pe_w);
	85	DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pa_r);
	86	DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pb_r);
	87	DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pc_r);
	88	DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pd_r);
	89	DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pe_r);
	90	DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pa_w);
	91	DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pb_w);
	92	DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pc_w);
	93	DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pd_w);
	94	DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pe_w);
	95
	96	DECLARE_READ8_MEMBER(porta_default_r);
	97	DECLARE_READ8_MEMBER(portb_default_r);
	98	DECLARE_READ8_MEMBER(portc_default_r);
	99	DECLARE_READ8_MEMBER(portd_default_r);
	100	DECLARE_READ8_MEMBER(porte_default_r);
	101
	102	DECLARE_WRITE8_MEMBER(porta_default_w);
	103	DECLARE_WRITE8_MEMBER(portb_default_w);
	104	DECLARE_WRITE8_MEMBER(portc_default_w);
	105	DECLARE_WRITE8_MEMBER(portd_default_w);
	106	DECLARE_WRITE8_MEMBER(porte_default_w);
	107
	108	DECLARE_WRITE_LINE_MEMBER(intr_cb_trampoline_w);
	109	DECLARE_WRITE_LINE_MEMBER(zc0_cb_trampoline_w);
	110	DECLARE_WRITE_LINE_MEMBER(zc1_cb_trampoline_w);
	111	DECLARE_WRITE_LINE_MEMBER(zc2_cb_trampoline_w);
	112
	113	protected:
	114	// device-level overrides
	115	virtual machine_config_constructor device_mconfig_additions() const;
	116	virtual void device_start();
	117	virtual void device_reset();
	118
	119	const address_space_config m_io_space_config;
	120
	121	const address_space_config *memory_space_config(address_spacenum spacenum) const
	122	{
	123	switch (spacenum)
	124	{
	125	case AS_IO: return &m_io_space_config;
	126	default: return z80_device::memory_space_config(spacenum);
	127	}
	128	}
	129
	130
	131	UINT8 m_pio_dir[5];
	132	UINT8 m_pio_latch[5];
	133
	134	private:
	135	devcb_write8      m_outports0;
	136	devcb_write8      m_outports1;
	137	devcb_write8      m_outports2;
	138	devcb_write8      m_outports3;
	139	devcb_write8      m_outports4;
	140
	141	devcb_read8       m_inports0;
	142	devcb_read8       m_inports1;
	143	devcb_read8       m_inports2;
	144	devcb_read8       m_inports3;
	145	devcb_read8       m_inports4;
	146
	147	devcb_write_line   m_intr_cb;              // interrupt callback
	148	devcb_write_line   m_zc0_cb;               // channel 0 zero crossing callbacks
	149	devcb_write_line   m_zc1_cb;               // channel 1 zero crossing callbacks
	150	devcb_write_line   m_zc2_cb;               // channel 2 zero crossing callbacks
	151
	152	};
	153
	154	extern const device_type TMPZ84C011;

Property changes on: trunk/src/emu/cpu/z80/tmpz84c011.h

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/emu/cpu/z80/z80.c

r30941	r30942
3737	3737	const device_type NSC800 = &device_creator<nsc800_device>;
3738	3738
3739	3739
3740		// how do we actually install default handlers for logging?
3741		/*
3742		READ8_MEMBER(tmpz84c011_device::porta_default_r) { logerror("%s read port A but no handler assigned\n", machine().describe_context()); return 0xff; }
3743		READ8_MEMBER(tmpz84c011_device::portb_default_r) { logerror("%s read port B but no handler assigned\n", machine().describe_context()); return 0xff; }
3744		READ8_MEMBER(tmpz84c011_device::portc_default_r) { logerror("%s read port C but no handler assigned\n", machine().describe_context()); return 0xff; }
3745		READ8_MEMBER(tmpz84c011_device::portd_default_r) { logerror("%s read port D but no handler assigned\n", machine().describe_context()); return 0xff; }
3746		READ8_MEMBER(tmpz84c011_device::porte_default_r) { logerror("%s read port E but no handler assigned\n", machine().describe_context()); return 0xff; }
3747	3740
3748		WRITE8_MEMBER(tmpz84c011_device::porta_default_w) { logerror("%s write %02x to port A but no handler assigned\n", machine().describe_context(), data); }
3749		WRITE8_MEMBER(tmpz84c011_device::portb_default_w) { logerror("%s write %02x to port B but no handler assigned\n", machine().describe_context(), data); }
3750		WRITE8_MEMBER(tmpz84c011_device::portc_default_w) { logerror("%s write %02x to port C but no handler assigned\n", machine().describe_context(), data); }
3751		WRITE8_MEMBER(tmpz84c011_device::portd_default_w) { logerror("%s write %02x to port D but no handler assigned\n", machine().describe_context(), data); }
3752		WRITE8_MEMBER(tmpz84c011_device::porte_default_w) { logerror("%s write %02x to port E but no handler assigned\n", machine().describe_context(), data); }
3753		*/
3754
3755		READ8_MEMBER(tmpz84c011_device::tmpz84c011_pio_r)
3756		{
3757		int portdata = 0xff;
3758
3759		switch (offset)
3760		{
3761		case 0:         /* PA_0 */
3762		portdata = m_inports0();
3763		break;
3764		case 1:         /* PB_0 */
3765		portdata = m_inports1();
3766		break;
3767		case 2:         /* PC_0 */
3768		portdata = m_inports2();
3769		break;
3770		case 3:         /* PD_0 */
3771		portdata = m_inports3();
3772		break;
3773		case 4:         /* PE_0 */
3774		portdata = m_inports4();
3775		break;
3776		}
3777
3778		return portdata;
3779		}
3780
3781		WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_pio_w)
3782		{
3783		switch (offset)
3784		{
3785		case 0:         /* PA_0 */
3786		m_outports0(data);
3787		break;
3788		case 1:         /* PB_0 */
3789		m_outports1(data);
3790		break;
3791		case 2:         /* PC_0 */
3792		m_outports2(data);
3793		break;
3794		case 3:         /* PD_0 */
3795		m_outports3(data);
3796		break;
3797		case 4:         /* PE_0 */
3798		m_outports4(data);
3799		break;
3800		}
3801		}
3802
3803		/* CPU interface */
3804		READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pa_r)
3805		{
3806		return (tmpz84c011_pio_r(space,0) & ~m_pio_dir[0]) | (m_pio_latch[0] & m_pio_dir[0]);
3807		}
3808
3809		READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pb_r)
3810		{
3811		return (tmpz84c011_pio_r(space,1) & ~m_pio_dir[1]) | (m_pio_latch[1] & m_pio_dir[1]);
3812		}
3813
3814		READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pc_r)
3815		{
3816		return (tmpz84c011_pio_r(space,2) & ~m_pio_dir[2]) | (m_pio_latch[2] & m_pio_dir[2]);
3817		}
3818
3819		READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pd_r)
3820		{
3821		return (tmpz84c011_pio_r(space,3) & ~m_pio_dir[3]) | (m_pio_latch[3] & m_pio_dir[3]);
3822		}
3823
3824		READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pe_r)
3825		{
3826		return (tmpz84c011_pio_r(space,4) & ~m_pio_dir[4]) | (m_pio_latch[4] & m_pio_dir[4]);
3827		}
3828
3829		WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pa_w)
3830		{
3831		m_pio_latch[0] = data;
3832		tmpz84c011_pio_w(space, 0, data);
3833		}
3834
3835		WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pb_w)
3836		{
3837		m_pio_latch[1] = data;
3838		tmpz84c011_pio_w(space, 1, data);
3839		}
3840		WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pc_w)
3841		{
3842		m_pio_latch[2] = data;
3843		tmpz84c011_pio_w(space, 2, data);
3844		}
3845
3846		WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pd_w)
3847		{
3848		m_pio_latch[3] = data;
3849		tmpz84c011_pio_w(space, 3, data);
3850		}
3851
3852		WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pe_w)
3853		{
3854		m_pio_latch[4] = data;
3855		tmpz84c011_pio_w(space, 4, data);
3856		}
3857
3858		READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pa_r)
3859		{
3860		return m_pio_dir[0];
3861		}
3862
3863		READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pb_r)
3864		{
3865		return m_pio_dir[1];
3866		}
3867
3868		READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pc_r)
3869		{
3870		return m_pio_dir[2];
3871		}
3872
3873		READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pd_r)
3874		{
3875		return m_pio_dir[3];
3876		}
3877
3878		READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pe_r)
3879		{
3880		return m_pio_dir[4];
3881		}
3882
3883		WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pa_w)
3884		{
3885		m_pio_dir[0] = data;
3886		}
3887
3888		WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pb_w)
3889		{
3890		m_pio_dir[1] = data;
3891		}
3892
3893		WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pc_w)
3894		{
3895		m_pio_dir[2] = data;
3896		}
3897
3898		WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pd_w)
3899		{
3900		m_pio_dir[3] = data;
3901		}
3902
3903		WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pe_w)
3904		{
3905		m_pio_dir[4] = data;
3906		}
3907
3908
3909
3910		static ADDRESS_MAP_START( tmpz84c011_internal_io_map, AS_IO, 8, tmpz84c011_device )
3911		AM_RANGE(0x50, 0x50) AM_READWRITE(tmpz84c011_0_pa_r, tmpz84c011_0_pa_w) AM_MIRROR(0xff00)
3912		AM_RANGE(0x51, 0x51) AM_READWRITE(tmpz84c011_0_pb_r, tmpz84c011_0_pb_w) AM_MIRROR(0xff00)
3913		AM_RANGE(0x52, 0x52) AM_READWRITE(tmpz84c011_0_pc_r, tmpz84c011_0_pc_w) AM_MIRROR(0xff00)
3914		AM_RANGE(0x30, 0x30) AM_READWRITE(tmpz84c011_0_pd_r, tmpz84c011_0_pd_w) AM_MIRROR(0xff00)
3915		AM_RANGE(0x40, 0x40) AM_READWRITE(tmpz84c011_0_pe_r, tmpz84c011_0_pe_w) AM_MIRROR(0xff00)
3916		AM_RANGE(0x54, 0x54) AM_READWRITE(tmpz84c011_0_dir_pa_r, tmpz84c011_0_dir_pa_w) AM_MIRROR(0xff00)
3917		AM_RANGE(0x55, 0x55) AM_READWRITE(tmpz84c011_0_dir_pb_r, tmpz84c011_0_dir_pb_w) AM_MIRROR(0xff00)
3918		AM_RANGE(0x56, 0x56) AM_READWRITE(tmpz84c011_0_dir_pc_r, tmpz84c011_0_dir_pc_w) AM_MIRROR(0xff00)
3919		AM_RANGE(0x34, 0x34) AM_READWRITE(tmpz84c011_0_dir_pd_r, tmpz84c011_0_dir_pd_w) AM_MIRROR(0xff00)
3920		AM_RANGE(0x44, 0x44) AM_READWRITE(tmpz84c011_0_dir_pe_r, tmpz84c011_0_dir_pe_w) AM_MIRROR(0xff00)
3921		ADDRESS_MAP_END
3922
3923
3924		tmpz84c011_device::tmpz84c011_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
3925		: z80_device(mconfig, TMPZ84C011, "TMPZ84C011", tag, owner, clock, "tmpz84c011", __FILE__),
3926		m_io_space_config( "io", ENDIANNESS_LITTLE, 8, 16, 0, ADDRESS_MAP_NAME( tmpz84c011_internal_io_map ) ),
3927		m_outports0(*this),
3928		m_outports1(*this),
3929		m_outports2(*this),
3930		m_outports3(*this),
3931		m_outports4(*this),
3932		m_inports0(*this),
3933		m_inports1(*this),
3934		m_inports2(*this),
3935		m_inports3(*this),
3936		m_inports4(*this)
3937		{
3938		}
3939
3940		const device_type TMPZ84C011 = &device_creator<tmpz84c011_device>;
3941
3942
3943		void tmpz84c011_device::device_start()
3944		{
3945		z80_device::device_start();
3946
3947		m_outports0.resolve_safe();
3948		m_outports1.resolve_safe();
3949		m_outports2.resolve_safe();
3950		m_outports3.resolve_safe();
3951		m_outports4.resolve_safe();
3952
3953		m_inports0.resolve_safe(0);
3954		m_inports1.resolve_safe(0);
3955		m_inports2.resolve_safe(0);
3956		m_inports3.resolve_safe(0);
3957		m_inports4.resolve_safe(0);
3958
3959		save_item(NAME(m_pio_dir[0]));
3960		save_item(NAME(m_pio_latch[0]));
3961		save_item(NAME(m_pio_dir[1]));
3962		save_item(NAME(m_pio_latch[1]));
3963		save_item(NAME(m_pio_dir[2]));
3964		save_item(NAME(m_pio_latch[2]));
3965		save_item(NAME(m_pio_dir[3]));
3966		save_item(NAME(m_pio_latch[3]));
3967		save_item(NAME(m_pio_dir[4]));
3968		save_item(NAME(m_pio_latch[4]));
3969
3970
3971		}
3972
3973		void tmpz84c011_device::device_reset()
3974		{
3975		z80_device::device_reset();
3976
3977		// initialize TMPZ84C011 PIO
3978		for (int i = 0; i < 5; i++)
3979		{
3980		m_pio_dir[i] = m_pio_latch[i] = 0;
3981		tmpz84c011_pio_w(*m_io, i, 0);
3982		}
3983		}
3984
3985
3986	3741	WRITE_LINE_MEMBER( z80_device::irq_line )
3987	3742	{
3988	3743	set_input_line( INPUT_LINE_IRQ0, state );

trunk/src/emu/cpu/z80/z80.h

r30941	r30942
340	340
341	341
342	342
343		#define MCFG_TMPZ84C011_PORTA_READ_CB(_devcb) \
344		devcb = &tmpz84c011_device::set_inports0_cb(*device, DEVCB_##_devcb);
345
346		#define MCFG_TMPZ84C011_PORTB_READ_CB(_devcb) \
347		devcb = &tmpz84c011_device::set_inports1_cb(*device, DEVCB_##_devcb);
348
349		#define MCFG_TMPZ84C011_PORTC_READ_CB(_devcb) \
350		devcb = &tmpz84c011_device::set_inports2_cb(*device, DEVCB_##_devcb);
351
352		#define MCFG_TMPZ84C011_PORTD_READ_CB(_devcb) \
353		devcb = &tmpz84c011_device::set_inports3_cb(*device, DEVCB_##_devcb);
354
355		#define MCFG_TMPZ84C011_PORTE_READ_CB(_devcb) \
356		devcb = &tmpz84c011_device::set_inports4_cb(*device, DEVCB_##_devcb);
357
358
359		#define MCFG_TMPZ84C011_PORTA_WRITE_CB(_devcb) \
360		devcb = &tmpz84c011_device::set_outports0_cb(*device, DEVCB_##_devcb);
361
362		#define MCFG_TMPZ84C011_PORTB_WRITE_CB(_devcb) \
363		devcb = &tmpz84c011_device::set_outports1_cb(*device, DEVCB_##_devcb);
364
365		#define MCFG_TMPZ84C011_PORTC_WRITE_CB(_devcb) \
366		devcb = &tmpz84c011_device::set_outports2_cb(*device, DEVCB_##_devcb);
367
368		#define MCFG_TMPZ84C011_PORTD_WRITE_CB(_devcb) \
369		devcb = &tmpz84c011_device::set_outports3_cb(*device, DEVCB_##_devcb);
370
371		#define MCFG_TMPZ84C011_PORTE_WRITE_CB(_devcb) \
372		devcb = &tmpz84c011_device::set_outports4_cb(*device, DEVCB_##_devcb);
373
374
375
376
377
378		class tmpz84c011_device : public z80_device
379		{
380		public:
381		tmpz84c011_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32);
382
383		template<class _Object> static devcb_base & set_outports0_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports0.set_callback(object); }
384		template<class _Object> static devcb_base & set_outports1_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports1.set_callback(object); }
385		template<class _Object> static devcb_base & set_outports2_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports2.set_callback(object); }
386		template<class _Object> static devcb_base & set_outports3_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports3.set_callback(object); }
387		template<class _Object> static devcb_base & set_outports4_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports4.set_callback(object); }
388
389		template<class _Object> static devcb_base & set_inports0_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports0.set_callback(object); }
390		template<class _Object> static devcb_base & set_inports1_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports1.set_callback(object); }
391		template<class _Object> static devcb_base & set_inports2_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports2.set_callback(object); }
392		template<class _Object> static devcb_base & set_inports3_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports3.set_callback(object); }
393		template<class _Object> static devcb_base & set_inports4_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports4.set_callback(object); }
394
395
396		DECLARE_READ8_MEMBER(tmpz84c011_pio_r);
397		DECLARE_WRITE8_MEMBER(tmpz84c011_pio_w);
398		DECLARE_READ8_MEMBER(tmpz84c011_0_pa_r);
399		DECLARE_READ8_MEMBER(tmpz84c011_0_pb_r);
400		DECLARE_READ8_MEMBER(tmpz84c011_0_pc_r);
401		DECLARE_READ8_MEMBER(tmpz84c011_0_pd_r);
402		DECLARE_READ8_MEMBER(tmpz84c011_0_pe_r);
403		DECLARE_WRITE8_MEMBER(tmpz84c011_0_pa_w);
404		DECLARE_WRITE8_MEMBER(tmpz84c011_0_pb_w);
405		DECLARE_WRITE8_MEMBER(tmpz84c011_0_pc_w);
406		DECLARE_WRITE8_MEMBER(tmpz84c011_0_pd_w);
407		DECLARE_WRITE8_MEMBER(tmpz84c011_0_pe_w);
408		DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pa_r);
409		DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pb_r);
410		DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pc_r);
411		DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pd_r);
412		DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pe_r);
413		DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pa_w);
414		DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pb_w);
415		DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pc_w);
416		DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pd_w);
417		DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pe_w);
418
419		DECLARE_READ8_MEMBER(porta_default_r);
420		DECLARE_READ8_MEMBER(portb_default_r);
421		DECLARE_READ8_MEMBER(portc_default_r);
422		DECLARE_READ8_MEMBER(portd_default_r);
423		DECLARE_READ8_MEMBER(porte_default_r);
424
425		DECLARE_WRITE8_MEMBER(porta_default_w);
426		DECLARE_WRITE8_MEMBER(portb_default_w);
427		DECLARE_WRITE8_MEMBER(portc_default_w);
428		DECLARE_WRITE8_MEMBER(portd_default_w);
429		DECLARE_WRITE8_MEMBER(porte_default_w);
430
431
432
433		protected:
434		// device-level overrides
435		virtual void device_start();
436		virtual void device_reset();
437
438		const address_space_config m_io_space_config;
439
440		const address_space_config *memory_space_config(address_spacenum spacenum) const
441		{
442		switch (spacenum)
443		{
444		case AS_IO: return &m_io_space_config;
445		default: return z80_device::memory_space_config(spacenum);
446		}
447		}
448
449
450		UINT8 m_pio_dir[5];
451		UINT8 m_pio_latch[5];
452
453		private:
454		devcb_write8      m_outports0;
455		devcb_write8      m_outports1;
456		devcb_write8      m_outports2;
457		devcb_write8      m_outports3;
458		devcb_write8      m_outports4;
459
460		devcb_read8       m_inports0;
461		devcb_read8       m_inports1;
462		devcb_read8       m_inports2;
463		devcb_read8       m_inports3;
464		devcb_read8       m_inports4;
465
466		};
467
468		extern const device_type TMPZ84C011;
469
470	343	#endif /* __Z80_H__ */

trunk/src/emu/cpu/z80/tmpz84c011.c

r0	r30942
	1
	2	#include "tmpz84c011.h"
	3
	4	// how do we actually install default handlers for logging?
	5	/*
	6	READ8_MEMBER(tmpz84c011_device::porta_default_r) { logerror("%s read port A but no handler assigned\n", machine().describe_context()); return 0xff; }
	7	READ8_MEMBER(tmpz84c011_device::portb_default_r) { logerror("%s read port B but no handler assigned\n", machine().describe_context()); return 0xff; }
	8	READ8_MEMBER(tmpz84c011_device::portc_default_r) { logerror("%s read port C but no handler assigned\n", machine().describe_context()); return 0xff; }
	9	READ8_MEMBER(tmpz84c011_device::portd_default_r) { logerror("%s read port D but no handler assigned\n", machine().describe_context()); return 0xff; }
	10	READ8_MEMBER(tmpz84c011_device::porte_default_r) { logerror("%s read port E but no handler assigned\n", machine().describe_context()); return 0xff; }
	11
	12	WRITE8_MEMBER(tmpz84c011_device::porta_default_w) { logerror("%s write %02x to port A but no handler assigned\n", machine().describe_context(), data); }
	13	WRITE8_MEMBER(tmpz84c011_device::portb_default_w) { logerror("%s write %02x to port B but no handler assigned\n", machine().describe_context(), data); }
	14	WRITE8_MEMBER(tmpz84c011_device::portc_default_w) { logerror("%s write %02x to port C but no handler assigned\n", machine().describe_context(), data); }
	15	WRITE8_MEMBER(tmpz84c011_device::portd_default_w) { logerror("%s write %02x to port D but no handler assigned\n", machine().describe_context(), data); }
	16	WRITE8_MEMBER(tmpz84c011_device::porte_default_w) { logerror("%s write %02x to port E but no handler assigned\n", machine().describe_context(), data); }
	17	*/
	18
	19	READ8_MEMBER(tmpz84c011_device::tmpz84c011_pio_r)
	20	{
	21	int portdata = 0xff;
	22
	23	switch (offset)
	24	{
	25	case 0:         /* PA_0 */
	26	portdata = m_inports0();
	27	break;
	28	case 1:         /* PB_0 */
	29	portdata = m_inports1();
	30	break;
	31	case 2:         /* PC_0 */
	32	portdata = m_inports2();
	33	break;
	34	case 3:         /* PD_0 */
	35	portdata = m_inports3();
	36	break;
	37	case 4:         /* PE_0 */
	38	portdata = m_inports4();
	39	break;
	40	}
	41
	42	return portdata;
	43	}
	44
	45	WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_pio_w)
	46	{
	47	switch (offset)
	48	{
	49	case 0:         /* PA_0 */
	50	m_outports0(data);
	51	break;
	52	case 1:         /* PB_0 */
	53	m_outports1(data);
	54	break;
	55	case 2:         /* PC_0 */
	56	m_outports2(data);
	57	break;
	58	case 3:         /* PD_0 */
	59	m_outports3(data);
	60	break;
	61	case 4:         /* PE_0 */
	62	m_outports4(data);
	63	break;
	64	}
	65	}
	66
	67	/* CPU interface */
	68	READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pa_r)
	69	{
	70	return (tmpz84c011_pio_r(space,0) & ~m_pio_dir[0]) | (m_pio_latch[0] & m_pio_dir[0]);
	71	}
	72
	73	READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pb_r)
	74	{
	75	return (tmpz84c011_pio_r(space,1) & ~m_pio_dir[1]) | (m_pio_latch[1] & m_pio_dir[1]);
	76	}
	77
	78	READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pc_r)
	79	{
	80	return (tmpz84c011_pio_r(space,2) & ~m_pio_dir[2]) | (m_pio_latch[2] & m_pio_dir[2]);
	81	}
	82
	83	READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pd_r)
	84	{
	85	return (tmpz84c011_pio_r(space,3) & ~m_pio_dir[3]) | (m_pio_latch[3] & m_pio_dir[3]);
	86	}
	87
	88	READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pe_r)
	89	{
	90	return (tmpz84c011_pio_r(space,4) & ~m_pio_dir[4]) | (m_pio_latch[4] & m_pio_dir[4]);
	91	}
	92
	93	WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pa_w)
	94	{
	95	m_pio_latch[0] = data;
	96	tmpz84c011_pio_w(space, 0, data);
	97	}
	98
	99	WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pb_w)
	100	{
	101	m_pio_latch[1] = data;
	102	tmpz84c011_pio_w(space, 1, data);
	103	}
	104	WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pc_w)
	105	{
	106	m_pio_latch[2] = data;
	107	tmpz84c011_pio_w(space, 2, data);
	108	}
	109
	110	WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pd_w)
	111	{
	112	m_pio_latch[3] = data;
	113	tmpz84c011_pio_w(space, 3, data);
	114	}
	115
	116	WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pe_w)
	117	{
	118	m_pio_latch[4] = data;
	119	tmpz84c011_pio_w(space, 4, data);
	120	}
	121
	122	READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pa_r)
	123	{
	124	return m_pio_dir[0];
	125	}
	126
	127	READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pb_r)
	128	{
	129	return m_pio_dir[1];
	130	}
	131
	132	READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pc_r)
	133	{
	134	return m_pio_dir[2];
	135	}
	136
	137	READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pd_r)
	138	{
	139	return m_pio_dir[3];
	140	}
	141
	142	READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pe_r)
	143	{
	144	return m_pio_dir[4];
	145	}
	146
	147	WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pa_w)
	148	{
	149	m_pio_dir[0] = data;
	150	}
	151
	152	WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pb_w)
	153	{
	154	m_pio_dir[1] = data;
	155	}
	156
	157	WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pc_w)
	158	{
	159	m_pio_dir[2] = data;
	160	}
	161
	162	WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pd_w)
	163	{
	164	m_pio_dir[3] = data;
	165	}
	166
	167	WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pe_w)
	168	{
	169	m_pio_dir[4] = data;
	170	}
	171
	172
	173
	174	static ADDRESS_MAP_START( tmpz84c011_internal_io_map, AS_IO, 8, tmpz84c011_device )
	175	AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("ctc", z80ctc_device, read, write) AM_MIRROR(0xff00)
	176
	177	AM_RANGE(0x50, 0x50) AM_READWRITE(tmpz84c011_0_pa_r, tmpz84c011_0_pa_w) AM_MIRROR(0xff00)
	178	AM_RANGE(0x51, 0x51) AM_READWRITE(tmpz84c011_0_pb_r, tmpz84c011_0_pb_w) AM_MIRROR(0xff00)
	179	AM_RANGE(0x52, 0x52) AM_READWRITE(tmpz84c011_0_pc_r, tmpz84c011_0_pc_w) AM_MIRROR(0xff00)
	180	AM_RANGE(0x30, 0x30) AM_READWRITE(tmpz84c011_0_pd_r, tmpz84c011_0_pd_w) AM_MIRROR(0xff00)
	181	AM_RANGE(0x40, 0x40) AM_READWRITE(tmpz84c011_0_pe_r, tmpz84c011_0_pe_w) AM_MIRROR(0xff00)
	182	AM_RANGE(0x54, 0x54) AM_READWRITE(tmpz84c011_0_dir_pa_r, tmpz84c011_0_dir_pa_w) AM_MIRROR(0xff00)
	183	AM_RANGE(0x55, 0x55) AM_READWRITE(tmpz84c011_0_dir_pb_r, tmpz84c011_0_dir_pb_w) AM_MIRROR(0xff00)
	184	AM_RANGE(0x56, 0x56) AM_READWRITE(tmpz84c011_0_dir_pc_r, tmpz84c011_0_dir_pc_w) AM_MIRROR(0xff00)
	185	AM_RANGE(0x34, 0x34) AM_READWRITE(tmpz84c011_0_dir_pd_r, tmpz84c011_0_dir_pd_w) AM_MIRROR(0xff00)
	186	AM_RANGE(0x44, 0x44) AM_READWRITE(tmpz84c011_0_dir_pe_r, tmpz84c011_0_dir_pe_w) AM_MIRROR(0xff00)
	187	ADDRESS_MAP_END
	188
	189
	190	tmpz84c011_device::tmpz84c011_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	191	: z80_device(mconfig, TMPZ84C011, "TMPZ84C011", tag, owner, clock, "tmpz84c011", __FILE__),
	192	m_io_space_config( "io", ENDIANNESS_LITTLE, 8, 16, 0, ADDRESS_MAP_NAME( tmpz84c011_internal_io_map ) ),
	193	m_outports0(*this),
	194	m_outports1(*this),
	195	m_outports2(*this),
	196	m_outports3(*this),
	197	m_outports4(*this),
	198	m_inports0(*this),
	199	m_inports1(*this),
	200	m_inports2(*this),
	201	m_inports3(*this),
	202	m_inports4(*this),
	203	m_intr_cb(*this),
	204	m_zc0_cb(*this),
	205	m_zc1_cb(*this),
	206	m_zc2_cb(*this)
	207	{
	208	}
	209
	210	WRITE_LINE_MEMBER( tmpz84c011_device::intr_cb_trampoline_w ) { m_intr_cb(state); }
	211	WRITE_LINE_MEMBER( tmpz84c011_device::zc0_cb_trampoline_w ) { m_zc0_cb(state); }
	212	WRITE_LINE_MEMBER( tmpz84c011_device::zc1_cb_trampoline_w ) { m_zc1_cb(state); }
	213	WRITE_LINE_MEMBER( tmpz84c011_device::zc2_cb_trampoline_w ) { m_zc2_cb(state); }
	214
	215
	216
	217	const device_type TMPZ84C011 = &device_creator<tmpz84c011_device>;
	218
	219	static MACHINE_CONFIG_FRAGMENT( tmpz84c011 )
	220	MCFG_DEVICE_ADD("ctc", Z80CTC, DERIVED_CLOCK(1,1) )
	221	MCFG_Z80CTC_INTR_CB(WRITELINE(tmpz84c011_device, intr_cb_trampoline_w))
	222	MCFG_Z80CTC_ZC0_CB(WRITELINE(tmpz84c011_device, zc0_cb_trampoline_w))
	223	MCFG_Z80CTC_ZC1_CB(WRITELINE(tmpz84c011_device, zc1_cb_trampoline_w))
	224	MCFG_Z80CTC_ZC2_CB(WRITELINE(tmpz84c011_device, zc2_cb_trampoline_w))
	225
	226
	227	MACHINE_CONFIG_END
	228
	229	machine_config_constructor tmpz84c011_device::device_mconfig_additions() const
	230	{
	231	return MACHINE_CONFIG_NAME( tmpz84c011 );
	232	}
	233
	234
	235	void tmpz84c011_device::device_start()
	236	{
	237	z80_device::device_start();
	238
	239	m_outports0.resolve_safe();
	240	m_outports1.resolve_safe();
	241	m_outports2.resolve_safe();
	242	m_outports3.resolve_safe();
	243	m_outports4.resolve_safe();
	244
	245	m_inports0.resolve_safe(0);
	246	m_inports1.resolve_safe(0);
	247	m_inports2.resolve_safe(0);
	248	m_inports3.resolve_safe(0);
	249	m_inports4.resolve_safe(0);
	250
	251	m_intr_cb.resolve_safe();
	252	m_zc0_cb.resolve_safe();
	253	m_zc1_cb.resolve_safe();
	254	m_zc2_cb.resolve_safe();
	255
	256	save_item(NAME(m_pio_dir[0]));
	257	save_item(NAME(m_pio_latch[0]));
	258	save_item(NAME(m_pio_dir[1]));
	259	save_item(NAME(m_pio_latch[1]));
	260	save_item(NAME(m_pio_dir[2]));
	261	save_item(NAME(m_pio_latch[2]));
	262	save_item(NAME(m_pio_dir[3]));
	263	save_item(NAME(m_pio_latch[3]));
	264	save_item(NAME(m_pio_dir[4]));
	265	save_item(NAME(m_pio_latch[4]));
	266
	267
	268	}
	269
	270	void tmpz84c011_device::device_reset()
	271	{
	272	z80_device::device_reset();
	273
	274	// initialize TMPZ84C011 PIO
	275	for (int i = 0; i < 5; i++)
	276	{
	277	m_pio_dir[i] = m_pio_latch[i] = 0;
	278	tmpz84c011_pio_w(*m_io, i, 0);
	279	}
	280	}
	281
	282

Property changes on: trunk/src/emu/cpu/z80/tmpz84c011.c

Added: svn:mime-type    + text/plain Added: svn:eol-style    + native

trunk/src/mame/drivers/nbmj9195.c

r30941	r30942
20	20	******************************************************************************/
21	21
22	22	#include "emu.h"
23		#include "cpu/z80/z80.h"
24		#include "machine/z80ctc.h"
	23	#include "cpu/z80/tmpz84c011.h"
25	24	#include "machine/nvram.h"
26	25	#include "includes/nb1413m3.h"      // needed for mahjong input controller
27	26	#include "sound/3812intf.h"
r30941	r30942
323	322	/* CTC of main cpu, ch0 trigger is vblank */
324	323	INTERRUPT_GEN_MEMBER(nbmj9195_state::ctc0_trg1)
325	324	{
326		z80ctc_device *ctc = machine().device<z80ctc_device>("main_ctc");
	325	z80ctc_device *ctc = machine().device<z80ctc_device>("maincpu:ctc");
327	326	ctc->trg1(1);
328	327	ctc->trg1(0);
329	328	}
r30941	r30942
345	344	logerror("DRIVER_INIT( nbmj9195 )\n");
346	345	}
347	346
348		static ADDRESS_MAP_START( tmpz84c011_regs, AS_IO, 8, nbmj9195_state )
349		AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("main_ctc", z80ctc_device, read, write)
350		ADDRESS_MAP_END
351	347
352	348	static ADDRESS_MAP_START( sailorws_map, AS_PROGRAM, 8, nbmj9195_state )
353	349	AM_RANGE(0x0000, 0xefff) AM_ROM
r30941	r30942
391	387
392	388	static ADDRESS_MAP_START( mjuraden_io_map, AS_IO, 8, nbmj9195_state )
393	389	ADDRESS_MAP_GLOBAL_MASK(0xff)
394		AM_IMPORT_FROM( tmpz84c011_regs )
395	390
396	391	AM_RANGE(0x80, 0x81) AM_READ(nbmj9195_blitter_0_r)
397	392	AM_RANGE(0x80, 0x8f) AM_WRITE(nbmj9195_blitter_0_w)
r30941	r30942
405	400
406	401	static ADDRESS_MAP_START( koinomp_io_map, AS_IO, 8, nbmj9195_state )
407	402	ADDRESS_MAP_GLOBAL_MASK(0xff)
408		AM_IMPORT_FROM( tmpz84c011_regs )
409	403
410	404	AM_RANGE(0x80, 0x81) AM_READ(nbmj9195_blitter_0_r)
411	405	AM_RANGE(0x80, 0x8f) AM_WRITE(nbmj9195_blitter_0_w)
r30941	r30942
424	418
425	419	static ADDRESS_MAP_START( patimono_io_map, AS_IO, 8, nbmj9195_state )
426	420	ADDRESS_MAP_GLOBAL_MASK(0xff)
427		AM_IMPORT_FROM( tmpz84c011_regs )
428	421
429	422	AM_RANGE(0x80, 0x81) AM_READ(nbmj9195_blitter_1_r)
430	423	AM_RANGE(0x80, 0x8f) AM_WRITE(nbmj9195_blitter_1_w)
r30941	r30942
442	435
443	436	static ADDRESS_MAP_START( mmehyou_io_map, AS_IO, 8, nbmj9195_state )
444	437	ADDRESS_MAP_GLOBAL_MASK(0xff)
445		AM_IMPORT_FROM( tmpz84c011_regs )
446	438
447	439	AM_RANGE(0x80, 0x81) AM_READ(nbmj9195_blitter_0_r)
448	440	AM_RANGE(0x80, 0x8f) AM_WRITE(nbmj9195_blitter_0_w)
r30941	r30942
456	448
457	449	static ADDRESS_MAP_START( gal10ren_io_map, AS_IO, 8, nbmj9195_state )
458	450	ADDRESS_MAP_GLOBAL_MASK(0xff)
459		AM_IMPORT_FROM( tmpz84c011_regs )
460	451
461	452	AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r)
462	453	AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w)
r30941	r30942
474	465
475	466	static ADDRESS_MAP_START( renaiclb_io_map, AS_IO, 8, nbmj9195_state )
476	467	ADDRESS_MAP_GLOBAL_MASK(0xff)
477		AM_IMPORT_FROM( tmpz84c011_regs )
478	468
479	469	AM_RANGE(0x20, 0x20) AM_WRITE(nbmj9195_sound_w)
480	470	AM_RANGE(0x24, 0x24) AM_WRITENOP
r30941	r30942
492	482
493	483	static ADDRESS_MAP_START( mjlaman_io_map, AS_IO, 8, nbmj9195_state )
494	484	ADDRESS_MAP_GLOBAL_MASK(0xff)
495		AM_IMPORT_FROM( tmpz84c011_regs )
496	485
497	486	AM_RANGE(0x20, 0x20) AM_WRITE(nbmj9195_sound_w)
498	487	AM_RANGE(0x22, 0x22) AM_WRITENOP
r30941	r30942
510	499
511	500	static ADDRESS_MAP_START( mkeibaou_io_map, AS_IO, 8, nbmj9195_state )
512	501	ADDRESS_MAP_GLOBAL_MASK(0xff)
513		AM_IMPORT_FROM( tmpz84c011_regs )
514	502
515	503	AM_RANGE(0x80, 0x81) AM_READ(nbmj9195_blitter_0_r)
516	504	AM_RANGE(0x80, 0x8f) AM_WRITE(nbmj9195_blitter_0_w)
r30941	r30942
528	516
529	517	static ADDRESS_MAP_START( pachiten_io_map, AS_IO, 8, nbmj9195_state )
530	518	ADDRESS_MAP_GLOBAL_MASK(0xff)
531		AM_IMPORT_FROM( tmpz84c011_regs )
532	519
533	520	AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r)
534	521	AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w)
r30941	r30942
546	533
547	534	static ADDRESS_MAP_START( sailorws_io_map, AS_IO, 8, nbmj9195_state )
548	535	ADDRESS_MAP_GLOBAL_MASK(0xff)
549		AM_IMPORT_FROM( tmpz84c011_regs )
550	536
551	537	AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r)
552	538	AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w)
r30941	r30942
564	550
565	551	static ADDRESS_MAP_START( sailorwr_io_map, AS_IO, 8, nbmj9195_state )
566	552	ADDRESS_MAP_GLOBAL_MASK(0xff)
567		AM_IMPORT_FROM( tmpz84c011_regs )
568	553
569	554	AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r)
570	555	AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w)
r30941	r30942
582	567
583	568	static ADDRESS_MAP_START( psailor1_io_map, AS_IO, 8, nbmj9195_state )
584	569	ADDRESS_MAP_GLOBAL_MASK(0xff)
585		AM_IMPORT_FROM( tmpz84c011_regs )
586	570
587	571	AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r)
588	572	AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w)
r30941	r30942
600	584
601	585	static ADDRESS_MAP_START( psailor2_io_map, AS_IO, 8, nbmj9195_state )
602	586	ADDRESS_MAP_GLOBAL_MASK(0xff)
603		AM_IMPORT_FROM( tmpz84c011_regs )
604	587
605	588	AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r)
606	589	AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w)
r30941	r30942
618	601
619	602	static ADDRESS_MAP_START( otatidai_io_map, AS_IO, 8, nbmj9195_state )
620	603	ADDRESS_MAP_GLOBAL_MASK(0xff)
621		AM_IMPORT_FROM( tmpz84c011_regs )
622	604
623	605	AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r)
624	606	AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w)
r30941	r30942
636	618
637	619	static ADDRESS_MAP_START( yosimoto_io_map, AS_IO, 8, nbmj9195_state )
638	620	ADDRESS_MAP_GLOBAL_MASK(0xff)
639		AM_IMPORT_FROM( tmpz84c011_regs )
640	621
641	622	AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r)
642	623	AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w)
r30941	r30942
654	635
655	636	static ADDRESS_MAP_START( yosimotm_io_map, AS_IO, 8, nbmj9195_state )
656	637	ADDRESS_MAP_GLOBAL_MASK(0xff)
657		AM_IMPORT_FROM( tmpz84c011_regs )
658	638
659	639	AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r)
660	640	AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w)
r30941	r30942
672	652
673	653	static ADDRESS_MAP_START( jituroku_io_map, AS_IO, 8, nbmj9195_state )
674	654	ADDRESS_MAP_GLOBAL_MASK(0xff)
675		AM_IMPORT_FROM( tmpz84c011_regs )
676	655
677	656	AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r)
678	657	AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w)
r30941	r30942
690	669
691	670	static ADDRESS_MAP_START( ngpgal_io_map, AS_IO, 8, nbmj9195_state )
692	671	ADDRESS_MAP_GLOBAL_MASK(0xff)
693		AM_IMPORT_FROM( tmpz84c011_regs )
694	672
695	673	AM_RANGE(0xa0, 0xa0) AM_WRITE(nbmj9195_sound_w)
696	674	AM_RANGE(0xa4, 0xa4) AM_WRITENOP
r30941	r30942
704	682
705	683	static ADDRESS_MAP_START( mjgottsu_io_map, AS_IO, 8, nbmj9195_state )
706	684	ADDRESS_MAP_GLOBAL_MASK(0xff)
707		AM_IMPORT_FROM( tmpz84c011_regs )
708	685
709	686	AM_RANGE(0x80, 0x81) AM_READ(nbmj9195_blitter_0_r)
710	687	AM_RANGE(0x80, 0x8f) AM_WRITE(nbmj9195_blitter_0_w)
r30941	r30942
718	695
719	696	static ADDRESS_MAP_START( cmehyou_io_map, AS_IO, 8, nbmj9195_state )
720	697	ADDRESS_MAP_GLOBAL_MASK(0xff)
721		AM_IMPORT_FROM( tmpz84c011_regs )
722	698
723	699	AM_RANGE(0xa0, 0xa0) AM_WRITE(nbmj9195_sound_w)
724	700	AM_RANGE(0xa8, 0xa8) AM_WRITENOP
r30941	r30942
732	708
733	709	static ADDRESS_MAP_START( mjkoiura_io_map, AS_IO, 8, nbmj9195_state )
734	710	ADDRESS_MAP_GLOBAL_MASK(0xff)
735		AM_IMPORT_FROM( tmpz84c011_regs )
736	711
737	712	AM_RANGE(0x80, 0x81) AM_READ(nbmj9195_blitter_0_r)
738	713	AM_RANGE(0x80, 0x8f) AM_WRITE(nbmj9195_blitter_0_w)
r30941	r30942
746	721
747	722	static ADDRESS_MAP_START( mkoiuraa_io_map, AS_IO, 8, nbmj9195_state )
748	723	ADDRESS_MAP_GLOBAL_MASK(0xff)
749		AM_IMPORT_FROM( tmpz84c011_regs )
750	724
751	725	AM_RANGE(0xa0, 0xa0) AM_WRITE(nbmj9195_sound_w)
752	726	AM_RANGE(0xa4, 0xa4) AM_WRITENOP
r30941	r30942
760	734
761	735	static ADDRESS_MAP_START( mscoutm_io_map, AS_IO, 8, nbmj9195_state )
762	736	ADDRESS_MAP_GLOBAL_MASK(0xff)
763		AM_IMPORT_FROM( tmpz84c011_regs )
764	737
765	738	AM_RANGE(0x80, 0x80) AM_READ(mscoutm_dipsw_1_r)
766	739	AM_RANGE(0x82, 0x82) AM_READ(mscoutm_dipsw_0_r)
r30941	r30942
780	753
781	754	static ADDRESS_MAP_START( imekura_io_map, AS_IO, 8, nbmj9195_state )
782	755	ADDRESS_MAP_GLOBAL_MASK(0xff)
783		AM_IMPORT_FROM( tmpz84c011_regs )
784	756
785	757	AM_RANGE(0x80, 0x80) AM_READ(mscoutm_dipsw_1_r)
786	758	AM_RANGE(0x82, 0x82) AM_READ(mscoutm_dipsw_0_r)
r30941	r30942
800	772
801	773	static ADDRESS_MAP_START( mjegolf_io_map, AS_IO, 8, nbmj9195_state )
802	774	ADDRESS_MAP_GLOBAL_MASK(0xff)
803		AM_IMPORT_FROM( tmpz84c011_regs )
804	775
805	776	AM_RANGE(0x80, 0x86) AM_WRITENOP            // nb22090 param ?
806	777
r30941	r30942
828	799
829	800	static ADDRESS_MAP_START( sailorws_sound_io_map, AS_IO, 8, nbmj9195_state )
830	801	ADDRESS_MAP_GLOBAL_MASK(0xff)
831		AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("audio_ctc", z80ctc_device, read, write)
832	802	AM_RANGE(0x80, 0x81) AM_DEVWRITE("ymsnd", ym3812_device, write)
833	803	ADDRESS_MAP_END
834	804
r30941	r30942
849	819	static ADDRESS_MAP_START( shabdama_io_map, AS_IO, 8, nbmj9195_state )
850	820	//  ADDRESS_MAP_UNMAP_HIGH
851	821	ADDRESS_MAP_GLOBAL_MASK(0xff)
852		AM_IMPORT_FROM( tmpz84c011_regs )
853	822
854	823	//  AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r)
855	824	//  AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w)
r30941	r30942
2812	2781
2813	2782	static const z80_daisy_config daisy_chain_main[] =
2814	2783	{
2815		{ "main_ctc" },
	2784	{ "maincpu:ctc" },
2816	2785	{ NULL }
2817	2786	};
2818	2787
2819	2788	static const z80_daisy_config daisy_chain_sound[] =
2820	2789	{
2821		{ "audio_ctc" },
	2790	{ "audiocpu:ctc" },
2822	2791	{ NULL }
2823	2792	};
2824	2793
r30941	r30942
2865	2834	MCFG_CPU_PROGRAM_MAP(sailorws_map)
2866	2835	MCFG_CPU_IO_MAP(sailorws_io_map)
2867	2836	MCFG_CPU_VBLANK_INT_DRIVER("screen", nbmj9195_state,  ctc0_trg1)                /* vblank is connect to ctc triggfer */
	2837	MCFG_TMPZ84C011_Z80CTC_INTR_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
2868	2838
2869	2839	MCFG_CPU_ADD("audiocpu", TMPZ84C011, 8000000)                  /* TMPZ84C011, 8.00 MHz */
2870	2840	MCFG_CPU_CONFIG(daisy_chain_sound)
2871	2841	MCFG_CPU_PROGRAM_MAP(sailorws_sound_map)
2872	2842	MCFG_CPU_IO_MAP(sailorws_sound_io_map)
	2843	MCFG_TMPZ84C011_Z80CTC_INTR_CB(INPUTLINE("audiocpu", INPUT_LINE_IRQ0))
	2844	MCFG_TMPZ84C011_Z80CTC_ZC0_CB(DEVWRITELINE("audiocpu:ctc", z80ctc_device, trg3))
2873	2845
2874		MCFG_DEVICE_ADD("main_ctc", Z80CTC, 12000000/2 /* same as "maincpu" */)
2875		MCFG_Z80CTC_INTR_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
2876	2846
2877		MCFG_DEVICE_ADD("audio_ctc", Z80CTC, 8000000 /* same as "audiocpu" */)
2878		MCFG_Z80CTC_INTR_CB(INPUTLINE("audiocpu", INPUT_LINE_IRQ0))
2879		MCFG_Z80CTC_ZC0_CB(DEVWRITELINE("audio_ctc", z80ctc_device, trg3))
2880
2881	2847	/* video hardware */
2882	2848	MCFG_SCREEN_ADD("screen", RASTER)
2883	2849	MCFG_SCREEN_VIDEO_ATTRIBUTES(VIDEO_UPDATE_AFTER_VBLANK)

trunk/src/mame/drivers/csplayh5.c

r30941	r30942
27	27	#include "cpu/m68000/m68000.h"
28	28	#include "machine/tmp68301.h"
29	29	#include "video/v9938.h"
30		#include "cpu/z80/z80.h"
31		#include "machine/z80ctc.h"
	30	#include "cpu/z80/tmpz84c011.h"
32	31	#include "sound/dac.h"
33	32	#include "sound/3812intf.h"
34	33	#include "cpu/z80/z80daisy.h"
r30941	r30942
235	234
236	235	static ADDRESS_MAP_START( csplayh5_sound_io_map, AS_IO, 8, csplayh5_state )
237	236	ADDRESS_MAP_GLOBAL_MASK(0xff)
238		AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("ctc", z80ctc_device, read, write)
239	237	AM_RANGE(0x80, 0x81) AM_DEVWRITE("ymsnd", ym3812_device, write)
240	238	ADDRESS_MAP_END
241	239
r30941	r30942
453	451
454	452	static const z80_daisy_config daisy_chain_sound[] =
455	453	{
456		{ "ctc" },
	454	{ "audiocpu:ctc" },
457	455	{ NULL }
458	456	};
459	457
r30941	r30942
483	481	MCFG_TMPZ84C011_PORTC_WRITE_CB(WRITE8(csplayh5_state, soundcpu_dac1_w))
484	482	MCFG_TMPZ84C011_PORTD_READ_CB(READ8(csplayh5_state, soundcpu_portd_r))
485	483	MCFG_TMPZ84C011_PORTE_WRITE_CB(WRITE8(csplayh5_state, soundcpu_porte_w))
	484	MCFG_TMPZ84C011_Z80CTC_INTR_CB(INPUTLINE("audiocpu", INPUT_LINE_IRQ0))
	485	MCFG_TMPZ84C011_Z80CTC_ZC0_CB(DEVWRITELINE("audiocpu:ctc", z80ctc_device, trg3))
486	486
487		MCFG_DEVICE_ADD("ctc", Z80CTC, 8000000)
488		MCFG_Z80CTC_INTR_CB(INPUTLINE("audiocpu", INPUT_LINE_IRQ0))
489		MCFG_Z80CTC_ZC0_CB(DEVWRITELINE("ctc", z80ctc_device, trg3))
490
491	487	MCFG_NVRAM_ADD_0FILL("nvram")
492	488
493	489	/* video hardware */

trunk/src/mame/drivers/niyanpai.c

r30941	r30942
34	34	******************************************************************************/
35	35
36	36	#include "emu.h"
37		#include "cpu/z80/z80.h"
	37	#include "cpu/z80/tmpz84c011.h"
38	38	#include "cpu/m68000/m68000.h"
39	39	#include "machine/tmp68301.h"
40		#include "machine/z80ctc.h"
41	40	#include "includes/nb1413m3.h"
42	41	#include "sound/dac.h"
43	42	#include "sound/3812intf.h"
r30941	r30942
336	335
337	336	static ADDRESS_MAP_START( niyanpai_sound_io_map, AS_IO, 8, niyanpai_state )
338	337	ADDRESS_MAP_GLOBAL_MASK(0xff)
339		AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("ctc", z80ctc_device, read, write)
340	338	AM_RANGE(0x80, 0x81) AM_DEVWRITE("ymsnd", ym3812_device, write)
341	339	ADDRESS_MAP_END
342	340
r30941	r30942
765	763
766	764	static const z80_daisy_config daisy_chain_sound[] =
767	765	{
768		{ "ctc" },
	766	{ "audiocpu:ctc" },
769	767	{ NULL }
770	768	};
771	769
r30941	r30942
791	789	MCFG_TMPZ84C011_PORTB_WRITE_CB(WRITE8(niyanpai_state, cpu_portb_w))
792	790	MCFG_TMPZ84C011_PORTC_WRITE_CB(WRITE8(niyanpai_state, cpu_portc_w))
793	791	MCFG_TMPZ84C011_PORTE_WRITE_CB(WRITE8(niyanpai_state, cpu_porte_w))
	792	MCFG_TMPZ84C011_Z80CTC_INTR_CB(INPUTLINE("audiocpu", INPUT_LINE_IRQ0))
	793	MCFG_TMPZ84C011_Z80CTC_ZC0_CB(DEVWRITELINE("audiocpu:ctc", z80ctc_device, trg3))
794	794
795		MCFG_DEVICE_ADD("ctc", Z80CTC, 8000000 /* same as "audiocpu" */)
796		MCFG_Z80CTC_INTR_CB(INPUTLINE("audiocpu", INPUT_LINE_IRQ0))
797		MCFG_Z80CTC_ZC0_CB(DEVWRITELINE("ctc", z80ctc_device, trg3))
798	795
799	796	MCFG_NVRAM_ADD_0FILL("nvram")
800	797

trunk/src/mame/drivers/kenseim.c

r30941	r30942
139	139	// note: I've kept this code out of cps1.c as there is likely to be a substantial amount of game specific code here ones all the extra hardware is emulated
140	140
141	141	#include "emu.h"
142		#include "cpu/z80/z80.h"
143		#include "machine/z80ctc.h"
	142	#include "cpu/z80/tmpz84c011.h"
144	143	#include "includes/cps1.h"
145	144	#include "kenseim.lh"
146	145	#include "machine/mb89363b.h"
r30941	r30942
460	459
461	460	static ADDRESS_MAP_START( kenseim_io_map, AS_IO, 8, kenseim_state )
462	461	ADDRESS_MAP_GLOBAL_MASK(0xff)
463		AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("gamecpu_ctc", z80ctc_device, read, write)
464		AM_RANGE(0x20, 0x27) AM_DEVREADWRITE("mb89363b", mb89363b_device, read, write)
	462	AM_RANGE(0x20, 0x27) AM_DEVREADWRITE("mb89363b",   mb89363b_device, read, write)
465	463	ADDRESS_MAP_END
466	464
467	465
468	466	static const z80_daisy_config daisy_chain_gamecpu[] =
469	467	{
470		{ "gamecpu_ctc" },
	468	{ "gamecpu:ctc" },
471	469	{ NULL }
472	470	};
473	471
r30941	r30942
486	484	MCFG_TMPZ84C011_PORTC_READ_CB(IOPORT("CAB-IN"))
487	485	MCFG_TMPZ84C011_PORTD_READ_CB(READ8(kenseim_state, cpu_portd_r))
488	486	MCFG_CPU_CONFIG(daisy_chain_gamecpu)
	487	MCFG_TMPZ84C011_Z80CTC_INTR_CB(INPUTLINE("gamecpu", INPUT_LINE_IRQ0))
489	488
490		MCFG_DEVICE_ADD("gamecpu_ctc", Z80CTC, XTAL_16MHz/2) // part of the tmpz84
491		MCFG_Z80CTC_INTR_CB(INPUTLINE("gamecpu", INPUT_LINE_IRQ0))
492	489
493	490	MCFG_MB89363B_ADD("mb89363b")
494	491	// a,b,c always $80: all ports set as output

Previous

199869 Revisions

Next

---

© 1997-2024 The MAME Team