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r30897 Sunday 8th June, 2014 at 23:47:35 UTC by Angelo Salese
Hooked up RAMDAC device to following drivers [Angelo Salese]: * adp.c * bmcbowl.c * coinmvga.c * highvdeo.c * magicard.c * segajw.c

[src/emu/video]	ramdac.c
[src/mame/drivers]	adp.c bmcbowl.c coinmvga.c highvdeo.c magicard.c segajw.c

trunk/src/emu/video/ramdac.c

r30896	r30897
7	7	Written by Angelo Salese
8	8
9	9	TODO:
10		- masking register
	10	- masking register, almost likely it controls rollback on incrementing
	11	r/w palette access;
11	12	- needs information about different models and what exactly they does
12	13
13	14	***************************************************************************/

trunk/src/mame/drivers/magicard.c

r30896	r30897
168	168	#include "emu.h"
169	169	#include "cpu/m68000/m68000.h"
170	170	#include "sound/2413intf.h"
	171	#include "video/ramdac.h"
171	172
172	173
173	174	class magicard_state : public driver_device
r30896	r30897
198	199	required_shared_ptr<UINT16> m_scc68070_dma_ch1_regs;
199	200	required_shared_ptr<UINT16> m_scc68070_dma_ch2_regs;
200	201	required_shared_ptr<UINT16> m_scc68070_mmu_regs;
201		struct { int r,g,b,offs,offs_internal; } m_pal;
202	202	DECLARE_READ16_MEMBER(test_r);
203		DECLARE_WRITE16_MEMBER(paletteram_io_w);
204	203	DECLARE_READ16_MEMBER(philips_66470_r);
205	204	DECLARE_WRITE16_MEMBER(philips_66470_w);
206	205	DECLARE_READ16_MEMBER(scc68070_ext_irqc_r);
r30896	r30897
500	499	return machine().rand();
501	500	}
502	501
503		// should use ramdac device
504		WRITE16_MEMBER(magicard_state::paletteram_io_w)
505		{
506		data &= mem_mask;
507
508		switch(offset*2)
509		{
510		case 0:
511		m_pal.offs = data;
512		m_pal.offs_internal = 0;
513		break;
514		case 4:
515		break;
516		case 2:
517		switch(m_pal.offs_internal)
518		{
519		case 0:
520		m_pal.r = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
521		m_pal.offs_internal++;
522		break;
523		case 1:
524		m_pal.g = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
525		m_pal.offs_internal++;
526		break;
527		case 2:
528		m_pal.b = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
529		m_palette->set_pen_color(m_pal.offs, rgb_t(m_pal.r, m_pal.g, m_pal.b));
530		m_pal.offs_internal = 0;
531		m_pal.offs++;
532		break;
533		}
534
535		break;
536		}
537		}
538
539	502	READ16_MEMBER(magicard_state::philips_66470_r)
540	503	{
541	504	switch(offset)
r30896	r30897
693	656	/* 001ffc00-001ffdff System I/O */
694	657	AM_RANGE(0x001ffc00, 0x001ffc01) AM_MIRROR(0x7fe00000) AM_READ(test_r)
695	658	AM_RANGE(0x001ffc40, 0x001ffc41) AM_MIRROR(0x7fe00000) AM_READ(test_r)
696		AM_RANGE(0x001ffd00, 0x001ffd05) AM_MIRROR(0x7fe00000) AM_WRITE(paletteram_io_w) //RAMDAC
	659	AM_RANGE(0x001ffd00, 0x001ffd01) AM_MIRROR(0x7fe00000) AM_DEVWRITE8("ramdac", ramdac_device, index_w, 0x00ff)
	660	AM_RANGE(0x001ffd02, 0x001ffd03) AM_MIRROR(0x7fe00000) AM_DEVWRITE8("ramdac", ramdac_device, pal_w, 0x00ff)
	661	AM_RANGE(0x001ffd04, 0x001ffd05) AM_MIRROR(0x7fe00000) AM_DEVWRITE8("ramdac", ramdac_device, mask_w, 0x00ff)
697	662	/*not the right sound chip,unknown type,it should be an ADPCM with 8 channels.*/
698	663	AM_RANGE(0x001ffd40, 0x001ffd43) AM_MIRROR(0x7fe00000) AM_DEVWRITE8("ymsnd", ym2413_device, write, 0x00ff)
699	664	AM_RANGE(0x001ffd80, 0x001ffd81) AM_MIRROR(0x7fe00000) AM_READ(test_r)
r30896	r30897
741	706	device.execute().set_input_line_and_vector(1, HOLD_LINE,0xf0/4);
742	707	}
743	708
	709	static ADDRESS_MAP_START( ramdac_map, AS_0, 8, magicard_state )
	710	AM_RANGE(0x000, 0x3ff) AM_DEVREADWRITE("ramdac",ramdac_device,ramdac_pal_r,ramdac_rgb666_w)
	711	ADDRESS_MAP_END
	712
	713
744	714	static MACHINE_CONFIG_START( magicard, magicard_state )
745	715	MCFG_CPU_ADD("maincpu", SCC68070, CLOCK_A/2)    /* SCC-68070 CCA84 datasheet */
746	716	MCFG_CPU_PROGRAM_MAP(magicard_mem)
r30896	r30897
754	724	MCFG_SCREEN_UPDATE_DRIVER(magicard_state, screen_update_magicard)
755	725
756	726	MCFG_PALETTE_ADD("palette", 0x100)
	727	MCFG_RAMDAC_ADD("ramdac", ramdac_map, "palette")
757	728
758
759
760	729	MCFG_SPEAKER_STANDARD_MONO("mono")
761	730	MCFG_SOUND_ADD("ymsnd", YM2413, CLOCK_A/12)
762	731	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)

trunk/src/mame/drivers/bmcbowl.c

r30896	r30897
106	106	#include "sound/ay8910.h"
107	107	#include "sound/okim6295.h"
108	108	#include "sound/2413intf.h"
	109	#include "video/ramdac.h"
109	110
110	111	#define NVRAM_HACK
111	112
r30896	r30897
119	120	m_stats_ram(*this, "nvram", 16),
120	121	m_vid1(*this, "vid1"),
121	122	m_vid2(*this, "vid2"),
122		m_colorram(*this, "colorram", 16),
123	123	m_palette(*this, "palette") { }
124	124
125	125	required_device<cpu_device> m_maincpu;
126	126	optional_shared_ptr<UINT8> m_stats_ram;
127	127	required_shared_ptr<UINT16> m_vid1;
128	128	required_shared_ptr<UINT16> m_vid2;
129		required_shared_ptr<UINT8> m_colorram;
130	129	required_device<palette_device> m_palette;
131	130	int m_clr_offset;
132	131	int m_bmc_input;
133	132	DECLARE_READ16_MEMBER(bmc_random_read);
134	133	DECLARE_READ16_MEMBER(bmc_protection_r);
135		DECLARE_WRITE16_MEMBER(bmc_RAMDAC_offset_w);
136		DECLARE_WRITE16_MEMBER(bmc_RAMDAC_color_w);
137	134	DECLARE_WRITE16_MEMBER(scroll_w);
138	135	DECLARE_READ8_MEMBER(via_b_in);
139	136	DECLARE_WRITE8_MEMBER(via_a_out);
r30896	r30897
225	222	return machine().rand();
226	223	}
227	224
228		WRITE16_MEMBER(bmcbowl_state::bmc_RAMDAC_offset_w)
229		{
230		m_clr_offset=data*3;
231		}
232
233		WRITE16_MEMBER(bmcbowl_state::bmc_RAMDAC_color_w)
234		{
235		m_colorram[m_clr_offset]=data;
236		m_palette->set_pen_color(m_clr_offset/3,pal6bit(m_colorram[(m_clr_offset/3)*3]),pal6bit(m_colorram[(m_clr_offset/3)*3+1]),pal6bit(m_colorram[(m_clr_offset/3)*3+2]));
237		m_clr_offset=(m_clr_offset+1)%768;
238		}
239
240	225	WRITE16_MEMBER(bmcbowl_state::scroll_w)
241	226	{
242	227	//TODO - scroll
r30896	r30897
325	310	static ADDRESS_MAP_START( bmcbowl_mem, AS_PROGRAM, 16, bmcbowl_state )
326	311	AM_RANGE(0x000000, 0x01ffff) AM_ROM
327	312
328		AM_RANGE(0x090000, 0x090001) AM_WRITE(bmc_RAMDAC_offset_w) AM_SHARE("colorram")
329		AM_RANGE(0x090002, 0x090003) AM_WRITE(bmc_RAMDAC_color_w)
330		AM_RANGE(0x090004, 0x090005) AM_WRITENOP//RAMDAC
	313	AM_RANGE(0x090000, 0x090001) AM_DEVWRITE8("ramdac", ramdac_device, index_w, 0x00ff)
	314	AM_RANGE(0x090002, 0x090003) AM_DEVWRITE8("ramdac", ramdac_device, pal_w, 0x00ff)
	315	AM_RANGE(0x090004, 0x090005) AM_DEVWRITE8("ramdac", ramdac_device, mask_w, 0x00ff)
331	316
332	317	AM_RANGE(0x090800, 0x090803) AM_WRITENOP
333	318	AM_RANGE(0x091000, 0x091001) AM_WRITENOP
r30896	r30897
459	444	m_bmc_input=data;
460	445	}
461	446
	447	static ADDRESS_MAP_START( ramdac_map, AS_0, 8, bmcbowl_state )
	448	AM_RANGE(0x000, 0x3ff) AM_DEVREADWRITE("ramdac",ramdac_device,ramdac_pal_r,ramdac_rgb666_w)
	449	ADDRESS_MAP_END
	450
462	451	static MACHINE_CONFIG_START( bmcbowl, bmcbowl_state )
463	452	MCFG_CPU_ADD("maincpu", M68000, XTAL_21_4772MHz / 2 )
464	453	MCFG_CPU_PROGRAM_MAP(bmcbowl_mem)
r30896	r30897
473	462	MCFG_SCREEN_PALETTE("palette")
474	463
475	464	MCFG_PALETTE_ADD("palette", 256)
	465	MCFG_RAMDAC_ADD("ramdac", ramdac_map, "palette")
476	466
477	467	MCFG_NVRAM_ADD_1FILL("nvram")
478	468

trunk/src/mame/drivers/coinmvga.c

r30896	r30897
203	203	- Interrupts generation is unknown.
204	204	- Touch screen hook-up.
205	205	- Fully understand why it trigger some RTEs that should be RTS at POST.
	206	- Rewrite palette system, use two RAMDAC devices
206	207
207	208
208	209	*******************************************************************************/
r30896	r30897
217	218	#include "cpu/h8/h83006.h"
218	219	#include "sound/ymz280b.h"
219	220	#include "machine/nvram.h"
	221	#include "video/ramdac.h"
220	222
221	223
222	224	class coinmvga_state : public driver_device
r30896	r30897
227	229	m_vram(*this, "vram"),
228	230	m_maincpu(*this, "maincpu"),
229	231	m_gfxdecode(*this, "gfxdecode"),
230		m_palette(*this, "palette")  { }
	232	m_palette(*this, "palette"),
	233	m_palette2(*this, "palette2") { }
231	234
232	235	required_shared_ptr<UINT16> m_vram;
233		struct { int r,g,b,offs,offs_internal; } m_bgpal, m_fgpal;
234	236	DECLARE_WRITE8_MEMBER(debug_w);
235		DECLARE_WRITE16_MEMBER(ramdac_bg_w);
236		DECLARE_WRITE16_MEMBER(ramdac_fg_w);
237	237	DECLARE_READ16_MEMBER(test_r);
238	238	DECLARE_DRIVER_INIT(colorama);
239	239	DECLARE_DRIVER_INIT(cmrltv75);
r30896	r30897
244	244	required_device<cpu_device> m_maincpu;
245	245	required_device<gfxdecode_device> m_gfxdecode;
246	246	required_device<palette_device> m_palette;
	247	required_device<palette_device> m_palette2;
	248
247	249	};
248	250
249	251
r30896	r30897
296	298	//  popmessage("written : %02X", data);
297	299	//}
298	300
299		WRITE16_MEMBER(coinmvga_state::ramdac_bg_w)
300		{
301		if(ACCESSING_BITS_8_15)
302		{
303		m_bgpal.offs = data >> 8;
304		m_bgpal.offs_internal = 0;
305		}
306		else //if(mem_mask == 0x00ff)
307		{
308		switch(m_bgpal.offs_internal)
309		{
310		case 0:
311		m_bgpal.r = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
312		m_bgpal.offs_internal++;
313		break;
314		case 1:
315		m_bgpal.g = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
316		m_bgpal.offs_internal++;
317		break;
318		case 2:
319		m_bgpal.b = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
320		m_palette->set_pen_color(m_bgpal.offs, rgb_t(m_bgpal.r, m_bgpal.g, m_bgpal.b));
321		m_bgpal.offs_internal = 0;
322		m_bgpal.offs++;
323		break;
324		}
325		}
326		}
327
328
329		WRITE16_MEMBER(coinmvga_state::ramdac_fg_w)
330		{
331		if(ACCESSING_BITS_8_15)
332		{
333		m_fgpal.offs = data >> 8;
334		m_fgpal.offs_internal = 0;
335		}
336		else
337		{
338		switch(m_fgpal.offs_internal)
339		{
340		case 0:
341		m_fgpal.r = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
342		m_fgpal.offs_internal++;
343		break;
344		case 1:
345		m_fgpal.g = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
346		m_fgpal.offs_internal++;
347		break;
348		case 2:
349		m_fgpal.b = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
350		m_palette->set_pen_color(0x100+m_fgpal.offs, rgb_t(m_fgpal.r, m_fgpal.g, m_fgpal.b));
351		m_fgpal.offs_internal = 0;
352		m_fgpal.offs++;
353		break;
354		}
355		}
356		}
357
358	301	/*
359	302	READ16_MEMBER(coinmvga_state::test_r)
360	303	{
r30896	r30897
376	319	//  AM_RANGE(0x403afa, 0x403afb) AM_READ(test_r) AM_WRITENOP //touch screen related, cmrltv75
377	320	AM_RANGE(0x400000, 0x40ffff) AM_RAM
378	321
379		AM_RANGE(0x600000, 0x600001) AM_WRITE(ramdac_bg_w)
380		AM_RANGE(0x600004, 0x600005) AM_WRITE(ramdac_fg_w)
	322	AM_RANGE(0x600000, 0x600001) AM_DEVWRITE8("ramdac", ramdac_device, index_w, 0xff00)
	323	AM_RANGE(0x600000, 0x600001) AM_DEVWRITE8("ramdac", ramdac_device, pal_w, 0x00ff)
	324	AM_RANGE(0x600002, 0x600003) AM_DEVWRITE8("ramdac", ramdac_device, mask_w, 0xff00)
	325	AM_RANGE(0x600004, 0x600005) AM_DEVWRITE8("ramdac2", ramdac_device, index_w, 0xff00)
	326	AM_RANGE(0x600004, 0x600005) AM_DEVWRITE8("ramdac2", ramdac_device, pal_w, 0x00ff)
	327	AM_RANGE(0x600006, 0x600007) AM_DEVWRITE8("ramdac2", ramdac_device, mask_w, 0xff00)
381	328	AM_RANGE(0x600008, 0x600009) AM_DEVREADWRITE8("ymz", ymz280b_device, read, write, 0xffff)
382	329	AM_RANGE(0x610000, 0x61000f) AM_RAM //touch screen i/o
383	330
r30896	r30897
645	592	******************************/
646	593
647	594	static GFXDECODE_START( coinmvga )
648		GFXDECODE_ENTRY( "gfx1", 0, tiles8x8_layout,   0x100, 16 )  /* Foreground GFX */
649		GFXDECODE_ENTRY( "gfx2", 0, tiles16x16_layout, 0x000, 16 )  /* Background GFX */
	595	GFXDECODE_ENTRY( "gfx1", 0, tiles8x8_layout,   0x000, 16 )  /* Foreground GFX */
650	596	GFXDECODE_END
651	597
	598	static GFXDECODE_START( coinmvga2 )
	599	GFXDECODE_ENTRY( "gfx2", 0, tiles16x16_layout, 0x000, 1 )  /* Background GFX */
	600	GFXDECODE_END
652	601
	602
653	603	/*************************
654	604	*    Sound Interface     *
655	605	*************************/
r30896	r30897
665	615	*    Machine Drivers     *
666	616	*************************/
667	617
	618	static ADDRESS_MAP_START( ramdac_map, AS_0, 8, coinmvga_state )
	619	AM_RANGE(0x000, 0x3ff) AM_DEVREADWRITE("ramdac",ramdac_device,ramdac_pal_r,ramdac_rgb666_w)
	620	ADDRESS_MAP_END
	621
	622	static ADDRESS_MAP_START( ramdac2_map, AS_0, 8, coinmvga_state )
	623	AM_RANGE(0x000, 0x3ff) AM_DEVREADWRITE("ramdac2",ramdac_device,ramdac_pal_r,ramdac_rgb666_w)
	624	ADDRESS_MAP_END
	625
	626
668	627	static MACHINE_CONFIG_START( coinmvga, coinmvga_state )
669	628
670	629	/* basic machine hardware */
r30896	r30897
685	644	MCFG_SCREEN_PALETTE("palette")
686	645
687	646	MCFG_GFXDECODE_ADD("gfxdecode", "palette", coinmvga)
	647	MCFG_GFXDECODE_ADD("gfxdecode2", "palette2", coinmvga2)
688	648
689		MCFG_PALETTE_ADD("palette", 512)
	649	MCFG_PALETTE_ADD("palette", 256)
	650	MCFG_RAMDAC_ADD("ramdac", ramdac_map, "palette")
	651
	652	MCFG_PALETTE_ADD("palette2", 16)
	653	MCFG_RAMDAC_ADD("ramdac2", ramdac2_map, "palette2")
	654
690	655	MCFG_PALETTE_INIT_OWNER(coinmvga_state, coinmvga)
691	656
692	657	/* sound hardware */

trunk/src/mame/drivers/adp.c

r30896	r30897
160	160	#include "machine/mc68681.h"
161	161	#include "machine/msm6242.h"
162	162	#include "machine/nvram.h"
	163	#include "video/ramdac.h"
163	164
	165
164	166	class adp_state : public driver_device
165	167	{
166	168	public:
r30896	r30897
181	183
182	184	/* misc */
183	185	UINT8 m_mux_data;
184		struct { int r,g,b,offs,offs_internal; } m_pal;
185	186
186	187	/* devices */
187	188	DECLARE_READ16_MEMBER(input_r);
188	189	DECLARE_WRITE16_MEMBER(input_w);
189		DECLARE_WRITE8_MEMBER(ramdac_io_w);
190	190	DECLARE_MACHINE_START(skattv);
191	191	DECLARE_MACHINE_RESET(skattv);
192	192	DECLARE_PALETTE_INIT(adp);
r30896	r30897
297	297	AM_RANGE(0x600006, 0x600007) AM_NOP //(r) is discarded (watchdog?)
298	298	ADDRESS_MAP_END
299	299
300		WRITE8_MEMBER(adp_state::ramdac_io_w)
301		{
302		switch(offset)
303		{
304		case 0:
305		m_pal.offs = data;
306		m_pal.offs_internal = 0;
307		break;
308		case 2:
309		//mask pen reg
310		break;
311		case 1:
312		switch(m_pal.offs_internal)
313		{
314		case 0:
315		m_pal.r = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
316		m_pal.offs_internal++;
317		break;
318		case 1:
319		m_pal.g = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
320		m_pal.offs_internal++;
321		break;
322		case 2:
323		m_pal.b = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
324		m_palette->set_pen_color(m_pal.offs, rgb_t(m_pal.r, m_pal.g, m_pal.b));
325		m_pal.offs_internal = 0;
326		m_pal.offs++;
327		m_pal.offs&=0xff;
328		break;
329		}
330
331		break;
332		}
333		}
334
335	300	static ADDRESS_MAP_START( funland_mem, AS_PROGRAM, 16, adp_state )
336	301	AM_RANGE(0x000000, 0x0fffff) AM_ROM
337	302	AM_RANGE(0x400000, 0x40001f) AM_DEVREADWRITE8("rtc",msm6242_device, read, write, 0x00ff)
338	303	AM_RANGE(0x800080, 0x800081) AM_DEVREADWRITE("h63484", h63484_device, status_r, address_w)
339	304	AM_RANGE(0x800082, 0x800083) AM_DEVREADWRITE("h63484", h63484_device, data_r, data_w)
340		AM_RANGE(0x800088, 0x80008d) AM_WRITE8(ramdac_io_w, 0x00ff)
	305	AM_RANGE(0x800088, 0x800089) AM_DEVWRITE8("ramdac", ramdac_device, index_w, 0x00ff)
	306	AM_RANGE(0x80008a, 0x80008b) AM_DEVWRITE8("ramdac", ramdac_device, pal_w, 0x00ff)
	307	AM_RANGE(0x80008c, 0x80008d) AM_DEVWRITE8("ramdac", ramdac_device, mask_w, 0x00ff)
341	308	AM_RANGE(0x800100, 0x800101) AM_READ_PORT("IN0")
342	309	AM_RANGE(0x800140, 0x800143) AM_DEVREADWRITE8("aysnd", ay8910_device, data_r, address_data_w, 0x00ff) //18b too
343	310	AM_RANGE(0x800180, 0x80019f) AM_DEVREADWRITE8("duart68681", mc68681_device, read, write, 0xff )
r30896	r30897
574	541	MCFG_H63484_ADDRESS_MAP(fashiong_h63484_map)
575	542	MACHINE_CONFIG_END
576	543
	544	static ADDRESS_MAP_START( ramdac_map, AS_0, 8, adp_state )
	545	AM_RANGE(0x000, 0x3ff) AM_DEVREADWRITE("ramdac",ramdac_device,ramdac_pal_r,ramdac_rgb666_w)
	546	ADDRESS_MAP_END
	547
577	548	static MACHINE_CONFIG_DERIVED( funland, quickjac )
578	549	MCFG_CPU_MODIFY("maincpu")
579	550	MCFG_CPU_PROGRAM_MAP(funland_mem)
580	551
581	552	MCFG_DEVICE_REMOVE("palette")
582	553	MCFG_PALETTE_ADD_INIT_BLACK("palette", 0x100)
	554	MCFG_RAMDAC_ADD("ramdac", ramdac_map, "palette")
583	555
584	556	MCFG_DEVICE_MODIFY("h63484")
585	557	MCFG_H63484_ADDRESS_MAP(fstation_h63484_map)

trunk/src/mame/drivers/highvdeo.c

r30896	r30897
102	102	#include "sound/okim6376.h"
103	103	#include "machine/nvram.h"
104	104	#include "fashion.lh"
	105	#include "video/ramdac.h"
105	106
106	107
107	108	class highvdeo_state : public driver_device
r30896	r30897
122	123	DECLARE_READ16_MEMBER(read0_r);
123	124	DECLARE_READ16_MEMBER(read1_r);
124	125	DECLARE_READ16_MEMBER(read2_r);
125		DECLARE_WRITE16_MEMBER(tv_vcf_paletteram_w);
126	126	DECLARE_WRITE16_MEMBER(tv_vcf_bankselect_w);
127	127	DECLARE_WRITE16_MEMBER(write1_w);
128	128	DECLARE_READ16_MEMBER(tv_ncf_read1_r);
r30896	r30897
241	241	return ioport("IN2")->read();
242	242	}
243	243
244		WRITE16_MEMBER(highvdeo_state::tv_vcf_paletteram_w)
245		{
246		switch(offset*2)
247		{
248		case 0:
249		m_pal.offs = data;
250		break;
251		case 2:
252		m_pal.offs_internal = 0;
253		break;
254		case 4:
255		switch(m_pal.offs_internal)
256		{
257		case 0:
258		m_pal.r = pal6bit(data);
259		m_pal.offs_internal++;
260		break;
261		case 1:
262		m_pal.g = pal6bit(data);
263		m_pal.offs_internal++;
264		break;
265		case 2:
266		m_pal.b = pal6bit(data);
267		m_palette->set_pen_color(m_pal.offs, m_pal.r, m_pal.g, m_pal.b);
268		m_pal.offs_internal = 0;
269		m_pal.offs++;
270		break;
271		}
272	244
273		break;
274		}
275		}
276
277	245	WRITE16_MEMBER(highvdeo_state::tv_vcf_bankselect_w)
278	246	{
279	247	UINT32 bankaddress;
r30896	r30897
343	311	AM_RANGE(0x0008, 0x0009) AM_READ(read0_r )
344	312	AM_RANGE(0x000a, 0x000b) AM_READ(read1_r )
345	313	AM_RANGE(0x000c, 0x000d) AM_READ(read2_r )
346		AM_RANGE(0x0010, 0x0015) AM_WRITE(tv_vcf_paletteram_w )
	314	AM_RANGE(0x0010, 0x0011) AM_DEVWRITE8("ramdac", ramdac_device, index_w, 0x00ff)
	315	AM_RANGE(0x0012, 0x0013) AM_DEVWRITE8("ramdac", ramdac_device, mask_w, 0x00ff)
	316	AM_RANGE(0x0014, 0x0015) AM_DEVWRITE8("ramdac", ramdac_device, pal_w, 0x00ff)
347	317	AM_RANGE(0x0030, 0x0031) AM_WRITE(tv_vcf_bankselect_w ) AM_READ(tv_oki6376_r )
348	318	ADDRESS_MAP_END
349	319
r30896	r30897
391	361	AM_RANGE(0x000c, 0x000d) AM_READ(read0_r )
392	362	AM_RANGE(0x0010, 0x0011) AM_READ(tv_ncf_read1_r )
393	363	AM_RANGE(0x0012, 0x0013) AM_READ(read2_r )
394		AM_RANGE(0x0030, 0x0035) AM_WRITE(tv_vcf_paletteram_w )
	364	AM_RANGE(0x0030, 0x0031) AM_DEVWRITE8("ramdac", ramdac_device, index_w, 0x00ff)
	365	AM_RANGE(0x0032, 0x0033) AM_DEVWRITE8("ramdac", ramdac_device, mask_w, 0x00ff)
	366	AM_RANGE(0x0034, 0x0035) AM_DEVWRITE8("ramdac", ramdac_device, pal_w, 0x00ff)
395	367	ADDRESS_MAP_END
396	368
397	369
r30896	r30897
416	388	AM_RANGE(0x0012, 0x0013) AM_READ_PORT("IN3")
417	389	AM_RANGE(0x0014, 0x0015) AM_READ(tv_ncf_read1_r )
418	390	AM_RANGE(0x0020, 0x0021) AM_WRITENOP
419		AM_RANGE(0x0030, 0x0035) AM_WRITE(tv_vcf_paletteram_w )
	391	AM_RANGE(0x0030, 0x0031) AM_DEVWRITE8("ramdac", ramdac_device, index_w, 0x00ff)
	392	AM_RANGE(0x0032, 0x0033) AM_DEVWRITE8("ramdac", ramdac_device, mask_w, 0x00ff)
	393	AM_RANGE(0x0034, 0x0035) AM_DEVWRITE8("ramdac", ramdac_device, pal_w, 0x00ff)
420	394	ADDRESS_MAP_END
421	395
422	396
r30896	r30897
521	495	AM_RANGE(0x000a, 0x000b) AM_READ(read1_r )
522	496	AM_RANGE(0x000c, 0x000d) AM_READ(newmcard_vblank_r )
523	497	AM_RANGE(0x000e, 0x000f) AM_READ(read2_r )
524		AM_RANGE(0x0010, 0x0015) AM_WRITE(tv_vcf_paletteram_w )
	498	AM_RANGE(0x0010, 0x0011) AM_DEVWRITE8("ramdac", ramdac_device, index_w, 0x00ff)
	499	AM_RANGE(0x0012, 0x0013) AM_DEVWRITE8("ramdac", ramdac_device, pal_w, 0x00ff)
	500	AM_RANGE(0x0014, 0x0015) AM_DEVWRITE8("ramdac", ramdac_device, mask_w, 0x00ff)
525	501	ADDRESS_MAP_END
526	502
527	503	/****************************
r30896	r30897
1139	1115	device.execute().set_input_line(INPUT_LINE_NMI, PULSE_LINE);
1140	1116	}
1141	1117
	1118	static ADDRESS_MAP_START( ramdac_map, AS_0, 8, highvdeo_state )
	1119	AM_RANGE(0x000, 0x3ff) AM_DEVREADWRITE("ramdac",ramdac_device,ramdac_pal_r,ramdac_rgb666_w)
	1120	ADDRESS_MAP_END
	1121
	1122
1142	1123	static MACHINE_CONFIG_START( tv_vcf, highvdeo_state )
1143	1124	MCFG_CPU_ADD("maincpu", V30, XTAL_12MHz/2 ) // ?
1144	1125	MCFG_CPU_PROGRAM_MAP(tv_vcf_map)
r30896	r30897
1155	1136	MCFG_SCREEN_UPDATE_DRIVER(highvdeo_state, screen_update_tourvisn)
1156	1137
1157	1138	MCFG_PALETTE_ADD("palette", 0x100)
	1139	MCFG_RAMDAC_ADD("ramdac", ramdac_map, "palette")
1158	1140
1159	1141	MCFG_VIDEO_START_OVERRIDE(highvdeo_state,tourvisn)
1160	1142

trunk/src/mame/drivers/segajw.c

r30896	r30897
24	24	#include "cpu/z80/z80.h"
25	25	#include "machine/nvram.h"
26	26	#include "video/h63484.h"
	27	#include "video/ramdac.h"
27	28
28	29	class segajw_state : public driver_device
29	30	{
r30896	r30897
41	42	DECLARE_READ16_MEMBER(coinlockout_r);
42	43	DECLARE_WRITE16_MEMBER(coinlockout_w);
43	44	DECLARE_READ16_MEMBER(soundboard_r);
44		DECLARE_WRITE8_MEMBER(ramdac_io_w);
45	45	DECLARE_INPUT_CHANGED_MEMBER(coin_drop_start);
46	46	DECLARE_CUSTOM_INPUT_MEMBER(coin_sensors_r);
47	47	DECLARE_CUSTOM_INPUT_MEMBER(hopper_sensors_r);
r30896	r30897
55	55	// driver_device overrides
56	56	virtual void machine_start();
57	57	virtual void machine_reset();
58		struct { int r,g,b,offs,offs_internal; } m_pal;
59	58	UINT64      m_coin_start_cycles;
60	59	UINT64      m_hopper_start_cycles;
61	60	UINT8       m_coin_counter;
r30896	r30897
107	106	return 0xfff0;  // value expected for pass the sound board test
108	107	}
109	108
110		WRITE8_MEMBER(segajw_state::ramdac_io_w)
111		{
112		// copied from adp.c
113		switch(offset)
114		{
115		case 0:
116		m_pal.offs = data;
117		m_pal.offs_internal = 0;
118		break;
119		case 2:
120		//mask pen reg
121		break;
122		case 1:
123		switch(m_pal.offs_internal)
124		{
125		case 0:
126		m_pal.r = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
127		m_pal.offs_internal++;
128		break;
129		case 1:
130		m_pal.g = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
131		m_pal.offs_internal++;
132		break;
133		case 2:
134		m_pal.b = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
135		m_palette->set_pen_color(m_pal.offs, rgb_t(m_pal.r, m_pal.g, m_pal.b));
136		m_pal.offs_internal = 0;
137		m_pal.offs++;
138		m_pal.offs&=0xff;
139		break;
140		}
141
142		break;
143		}
144		}
145
146	109	INPUT_CHANGED_MEMBER( segajw_state::coin_drop_start )
147	110	{
148	111	if (newval && !m_coin_start_cycles)
r30896	r30897
215	178	AM_RANGE(0x1c0006, 0x1c0007) AM_READ_PORT("IN3")
216	179	AM_RANGE(0x1c000c, 0x1c000d) AM_READWRITE(coinlockout_r, coinlockout_w)
217	180
218		AM_RANGE(0x280000, 0x280007) AM_WRITE8(ramdac_io_w, 0x00ff)
	181	AM_RANGE(0x280000, 0x280001) AM_DEVWRITE8("ramdac", ramdac_device, index_w, 0x00ff)
	182	AM_RANGE(0x280002, 0x280003) AM_DEVWRITE8("ramdac", ramdac_device, pal_w, 0x00ff)
	183	AM_RANGE(0x280004, 0x280005) AM_DEVWRITE8("ramdac", ramdac_device, mask_w, 0x00ff)
219	184
220	185	AM_RANGE(0xff0000, 0xffffff) AM_RAM AM_SHARE("nvram")
221	186	ADDRESS_MAP_END
r30896	r30897
391	356	m_hopper_ctrl = 0;
392	357	}
393	358
	359	static ADDRESS_MAP_START( ramdac_map, AS_0, 8, segajw_state )
	360	AM_RANGE(0x000, 0x3ff) AM_DEVREADWRITE("ramdac",ramdac_device,ramdac_pal_r,ramdac_rgb666_w)
	361	ADDRESS_MAP_END
	362
394	363	static MACHINE_CONFIG_START( segajw, segajw_state )
395	364	/* basic machine hardware */
396	365	MCFG_CPU_ADD("maincpu",M68000,8000000) // unknown clock
r30896	r30897
415	384	MCFG_SCREEN_PALETTE("palette")
416	385
417	386	MCFG_PALETTE_ADD("palette", 16)
	387	MCFG_RAMDAC_ADD("ramdac", ramdac_map, "palette")
418	388
419	389	MCFG_H63484_ADD("hd63484", 8000000, segajw_hd63484_map) // unknown clock
420	390

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