trunk/src/mame/drivers/toaplan2.c
| r30852 | r30853 | |
|---|
| 676 | 676 | { |
| 677 | 677 | if (ACCESSING_BITS_0_7) |
| 678 | 678 | { |
| 679 | | UINT16 *toaplan2_shared_ram16 = m_shared_ram16; |
| 680 | | |
| 679 | data &= 0xff; |
| 681 | 680 | m_mcu_data = data; |
| 682 | 681 | if ((data >= 0xd0) && (data < 0xe0)) |
| 683 | 682 | { |
| 684 | 683 | offset = ((data & 0x0f) * 2) + (0x38 / 2); |
| 685 | | toaplan2_shared_ram16[offset ] = 0x0005; // Return address for |
| 686 | | toaplan2_shared_ram16[offset-1] = 0x0056; // RTS instruction |
| 684 | m_shared_ram16[offset ] = 0x0005; // Return address for |
| 685 | m_shared_ram16[offset-1] = 0x0056; // RTS instruction |
| 687 | 686 | } |
| 688 | 687 | else |
| 689 | 688 | { |
| 690 | 689 | logerror("PC:%08x Writing %08x to HD647180 cpu shared ram status port\n", space.device().safe_pcbase(), m_mcu_data); |
| 691 | 690 | } |
| 692 | | toaplan2_shared_ram16[0x56 / 2] = 0x004e; // Return a RTS instruction |
| 693 | | toaplan2_shared_ram16[0x58 / 2] = 0x0075; |
| 691 | m_shared_ram16[0x56 / 2] = 0x004e; // Return a RTS instruction |
| 692 | m_shared_ram16[0x58 / 2] = 0x0075; |
| 694 | 693 | |
| 695 | 694 | if (data == 0xd3) |
| 696 | 695 | { |
| 697 | | toaplan2_shared_ram16[0x56 / 2] = 0x003a; // move.w d1,d5 |
| 698 | | toaplan2_shared_ram16[0x58 / 2] = 0x0001; |
| 699 | | toaplan2_shared_ram16[0x5a / 2] = 0x0008; // bclr.b #0,d5 |
| 700 | | toaplan2_shared_ram16[0x5c / 2] = 0x0085; |
| 701 | | toaplan2_shared_ram16[0x5e / 2] = 0x0000; |
| 702 | | toaplan2_shared_ram16[0x60 / 2] = 0x0000; |
| 703 | | toaplan2_shared_ram16[0x62 / 2] = 0x00cb; // muls.w #3,d5 |
| 704 | | toaplan2_shared_ram16[0x64 / 2] = 0x00fc; |
| 705 | | toaplan2_shared_ram16[0x66 / 2] = 0x0000; |
| 706 | | toaplan2_shared_ram16[0x68 / 2] = 0x0003; |
| 707 | | toaplan2_shared_ram16[0x6a / 2] = 0x0090; // sub.w d5,d0 |
| 708 | | toaplan2_shared_ram16[0x6c / 2] = 0x0045; |
| 709 | | toaplan2_shared_ram16[0x6e / 2] = 0x00e5; // lsl.b #2,d1 |
| 710 | | toaplan2_shared_ram16[0x70 / 2] = 0x0009; |
| 711 | | toaplan2_shared_ram16[0x72 / 2] = 0x004e; // rts |
| 712 | | toaplan2_shared_ram16[0x74 / 2] = 0x0075; |
| 696 | m_shared_ram16[0x56 / 2] = 0x003a; // move.w d1,d5 |
| 697 | m_shared_ram16[0x58 / 2] = 0x0001; |
| 698 | m_shared_ram16[0x5a / 2] = 0x0008; // bclr.b #0,d5 |
| 699 | m_shared_ram16[0x5c / 2] = 0x0085; |
| 700 | m_shared_ram16[0x5e / 2] = 0x0000; |
| 701 | m_shared_ram16[0x60 / 2] = 0x0000; |
| 702 | m_shared_ram16[0x62 / 2] = 0x00cb; // muls.w #3,d5 |
| 703 | m_shared_ram16[0x64 / 2] = 0x00fc; |
| 704 | m_shared_ram16[0x66 / 2] = 0x0000; |
| 705 | m_shared_ram16[0x68 / 2] = 0x0003; |
| 706 | m_shared_ram16[0x6a / 2] = 0x0090; // sub.w d5,d0 |
| 707 | m_shared_ram16[0x6c / 2] = 0x0045; |
| 708 | m_shared_ram16[0x6e / 2] = 0x00e5; // lsl.b #2,d1 |
| 709 | m_shared_ram16[0x70 / 2] = 0x0009; |
| 710 | m_shared_ram16[0x72 / 2] = 0x004e; // rts |
| 711 | m_shared_ram16[0x74 / 2] = 0x0075; |
| 713 | 712 | } |
| 714 | 713 | } |
| 715 | 714 | } |