trunk/src/mame/machine/namcos1.c
| r30780 | r30781 | |
| 500 | 500 | if (op == m_key_rng) return machine().rand(); |
| 501 | 501 | if (op == m_key_swap4) return (m_key[m_key_swap4_arg] << 4) | (m_key[m_key_swap4_arg] >> 4); |
| 502 | 502 | if (op == m_key_bottom4) return (offset << 4) | (m_key[m_key_swap4_arg] & 0x0f); |
| 503 | | if (op == m_key_top4) return (offset << 4) | (m_key[m_key_swap4_arg] >> 4); |
| 503 | if (op == m_key_top4) return (offset << 4) | (m_key[m_key_swap4_arg] >> 4); |
| 504 | 504 | |
| 505 | 505 | popmessage("CPU %s PC %08x: keychip read %04x", space.device().tag(), space.device().safe_pc(), offset); |
| 506 | 506 | |
| r30780 | r30781 | |
| 746 | 746 | * * |
| 747 | 747 | *******************************************************************************/ |
| 748 | 748 | |
| 749 | | void namcos1_state::namcos1_install_bank(int start,int end,read8_delegate hr,write8_delegate hw, int offset,UINT8 *pointer) |
| 749 | void namcos1_state::namcos1_install_bank(int start, int end,read8_delegate hr, write8_delegate hw, int offset, UINT8 *pointer) |
| 750 | 750 | { |
| 751 | | int i; |
| 752 | | for(i=start;i<=end;i++) |
| 751 | for (int i = start; i <= end; i++) |
| 753 | 752 | { |
| 754 | 753 | m_bank_element[i].bank_handler_r = hr; |
| 755 | 754 | m_bank_element[i].bank_handler_w = hw; |
| 756 | 755 | m_bank_element[i].bank_offset = offset; |
| 757 | 756 | m_bank_element[i].bank_pointer = pointer; |
| 758 | | offset += 0x2000; |
| 759 | | if(pointer) pointer += 0x2000; |
| 757 | |
| 758 | offset += 0x2000; |
| 759 | |
| 760 | if (pointer) |
| 761 | pointer += 0x2000; |
| 760 | 762 | } |
| 761 | 763 | } |
| 762 | 764 | |
| 763 | 765 | |
| 764 | 766 | |
| 765 | | void namcos1_state::namcos1_build_banks(read8_delegate key_r,write8_delegate key_w) |
| 767 | void namcos1_state::namcos1_build_banks(read8_delegate key_r, write8_delegate key_w) |
| 766 | 768 | { |
| 767 | 769 | int i; |
| 768 | 770 | |
| 769 | 771 | /**** kludge alert ****/ |
| 770 | | UINT8 *dummyrom = auto_alloc_array(machine(), UINT8, 0x2000); |
| 772 | m_dummyrom = auto_alloc_array(machine(), UINT8, 0x2000); |
| 771 | 773 | |
| 772 | 774 | /* when the games want to reset because the test switch has been flipped (or |
| 773 | 775 | because the protection checks failed!) they just set the top bits of bank #7 |
| r30780 | r30781 | |
| 778 | 780 | so misaligned entry points get immediatly corrected. */ |
| 779 | 781 | for (i = 0;i < 0x2000;i+=2) |
| 780 | 782 | { |
| 781 | | dummyrom[i] = 0x20; |
| 782 | | dummyrom[i+1] = 0xfe; |
| 783 | m_dummyrom[i] = 0x20; |
| 784 | m_dummyrom[i+1] = 0xfe; |
| 783 | 785 | } |
| 784 | 786 | /* also provide a valid IRQ vector */ |
| 785 | | dummyrom[0x1ff8] = 0xff; |
| 786 | | dummyrom[0x1ff9] = 0x00; |
| 787 | m_dummyrom[0x1ff8] = 0xff; |
| 788 | m_dummyrom[0x1ff9] = 0x00; |
| 787 | 789 | |
| 788 | 790 | /* clear all banks to unknown area */ |
| 789 | 791 | for(i = 0;i < NAMCOS1_MAX_BANK;i++) |
| 790 | | namcos1_install_bank(i,i,read8_delegate(),write8_delegate(FUNC(namcos1_state::unknown_w),this),0,dummyrom); |
| 792 | namcos1_install_bank(i,i,read8_delegate(),write8_delegate(FUNC(namcos1_state::unknown_w),this),0,m_dummyrom); |
| 791 | 793 | /**** end of kludge alert ****/ |
| 792 | 794 | |
| 793 | 795 | |
| r30780 | r30781 | |
| 807 | 809 | namcos1_install_bank(0x180,0x183,read8_delegate(),write8_delegate(),0,m_s1ram); |
| 808 | 810 | |
| 809 | 811 | /* PRG0-PRG7 */ |
| 810 | | { |
| 811 | | UINT8 *rom = machine().root_device().memregion("user1")->base(); |
| 812 | UINT8 *rom = machine().root_device().memregion("user1")->base(); |
| 812 | 813 | |
| 813 | | namcos1_install_bank(0x200,0x3ff,read8_delegate(),write8_delegate(FUNC(namcos1_state::rom_w),this),0,rom); |
| 814 | namcos1_install_bank(0x200,0x3ff,read8_delegate(),write8_delegate(FUNC(namcos1_state::rom_w),this),0,rom); |
| 814 | 815 | |
| 815 | | /* bit 16 of the address is inverted for PRG7 (and bits 17,18 just not connected) */ |
| 816 | | for (i = 0x380000;i < 0x400000;i++) |
| 816 | /* bit 16 of the address is inverted for PRG7 (and bits 17,18 just not connected) */ |
| 817 | for (i = 0x380000;i < 0x400000;i++) |
| 818 | { |
| 819 | if ((i & 0x010000) == 0) |
| 817 | 820 | { |
| 818 | | if ((i & 0x010000) == 0) |
| 819 | | { |
| 820 | | UINT8 t = rom[i]; |
| 821 | | rom[i] = rom[i + 0x010000]; |
| 822 | | rom[i + 0x010000] = t; |
| 823 | | } |
| 821 | UINT8 t = rom[i]; |
| 822 | rom[i] = rom[i + 0x010000]; |
| 823 | rom[i + 0x010000] = t; |
| 824 | 824 | } |
| 825 | 825 | } |
| 826 | 826 | } |
| 827 | 827 | |
| 828 | 828 | void namcos1_state::machine_reset() |
| 829 | 829 | { |
| 830 | memset(m_chip, 0, sizeof(m_chip)); |
| 831 | |
| 832 | /* Point all of our bankhandlers to the error handlers */ |
| 830 | 833 | static const bankhandler unknown_handler = { read8_delegate(FUNC(namcos1_state::unknown_r),this), write8_delegate(FUNC(namcos1_state::unknown_w),this), 0, NULL }; |
| 831 | | int bank; |
| 832 | 834 | |
| 833 | | /* Point all of our bankhandlers to the error handlers */ |
| 834 | | for (bank = 0; bank < 2*8 ; bank++) |
| 835 | for (int bank = 0; bank < 2*8 ; bank++) |
| 835 | 836 | set_bank(bank, &unknown_handler); |
| 836 | 837 | |
| 837 | | memset(m_chip, 0, sizeof(m_chip)); |
| 838 | | |
| 839 | 838 | /* Default MMU setup for Cpu 0 */ |
| 840 | 839 | namcos1_bankswitch(0, 0x0000, 0x01 ); /* bank0 = 0x180(RAM) - evidence: wldcourt */ |
| 841 | 840 | namcos1_bankswitch(0, 0x0001, 0x80 ); |
| r30780 | r30781 | |
| 864 | 863 | |
| 865 | 864 | namcos1_init_DACs(); |
| 866 | 865 | memset(m_key, 0, sizeof(m_key)); |
| 866 | m_key_quotient = 0; |
| 867 | m_key_reminder = 0; |
| 868 | m_key_numerator_high_word = 0; |
| 867 | 869 | m_wdog = 0; |
| 868 | 870 | } |
| 869 | 871 | |
| r30780 | r30781 | |
| 953 | 955 | m_key_top4 = specific->key_reg6; |
| 954 | 956 | |
| 955 | 957 | /* S1 RAM pointer set */ |
| 956 | | m_s1ram = auto_alloc_array(machine(), UINT8, 0x8000); |
| 957 | | m_triram = auto_alloc_array(machine(), UINT8, 0x800); |
| 958 | | m_paletteram = auto_alloc_array(machine(), UINT8, 0x8000); |
| 958 | m_s1ram = auto_alloc_array_clear(machine(), UINT8, 0x8000); |
| 959 | m_triram = auto_alloc_array_clear(machine(), UINT8, 0x800); |
| 960 | m_paletteram = auto_alloc_array_clear(machine(), UINT8, 0x8000); |
| 959 | 961 | |
| 960 | 962 | /* Register volatile user memory for save state */ |
| 961 | 963 | save_pointer(NAME(m_s1ram), 0x8000); |
| r30780 | r30781 | |
| 963 | 965 | save_pointer(NAME(m_paletteram), 0x8000); |
| 964 | 966 | |
| 965 | 967 | /* Point mcu & sound shared RAM to destination */ |
| 966 | | membank("bank18")->set_base(m_triram ); |
| 967 | | membank("bank19")->set_base(m_triram ); |
| 968 | membank("bank18")->set_base(m_triram); |
| 969 | membank("bank19")->set_base(m_triram); |
| 968 | 970 | |
| 969 | 971 | /* build bank elements */ |
| 970 | 972 | namcos1_build_banks(specific->key_r,specific->key_w); |
| 973 | memset(m_active_bank, 0, sizeof(m_active_bank)); |
| 971 | 974 | } |
| 972 | 975 | |
| 973 | 976 | |