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r30758 Sunday 1st June, 2014 at 15:47:35 UTC by Wilbert Pol
mips3.c: Modernised cpu core (nw)
[src/emu/cpu/mips]mips3.c mips3.h mips3com.c mips3com.h mips3drc.c mips3fe.c mips3fe.h
[src/mame/drivers]aleck64.c atlantis.c hng64.c iteagle.c kinst.c namcops2.c namcos23.c pyson.c seattle.c vegas.c vp101.c
[src/mame/includes]hng64.h
[src/mame/machine]n64.c
[src/mess/drivers]ip22.c

trunk/src/mame/drivers/vp101.c
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3434protected:
3535
3636   // devices
37   required_device<cpu_device> m_maincpu;
37   required_device<mips3_device> m_maincpu;
3838
3939   // driver_device overrides
4040   virtual void video_start();
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7474static INPUT_PORTS_START( vp101 )
7575INPUT_PORTS_END
7676
77static const mips3_config r5000_config =
78{
79   32768,              /* code cache size */
80   32768,              /* data cache size */
81   100000000           /* system (bus) clock */
82};
8377
8478static MACHINE_CONFIG_START( vp101, vp10x_state )
8579   MCFG_CPU_ADD("maincpu", R5000LE, 300000000) /* actually VR5500 with added NEC VR-series custom instructions */
86   MCFG_CPU_CONFIG(r5000_config)
80   MCFG_MIPS3_ICACHE_SIZE(32768)
81   MCFG_MIPS3_DCACHE_SIZE(32768)
82   MCFG_MIPS3_SYSTEM_CLOCK(100000000)
8783   MCFG_CPU_PROGRAM_MAP(main_map)
8884
8985   MCFG_SCREEN_ADD("screen", RASTER)
trunk/src/mame/drivers/kinst.c
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177177   virtual void machine_reset();
178178   UINT32 screen_update_kinst(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
179179   INTERRUPT_GEN_MEMBER(irq0_start);
180   required_device<cpu_device> m_maincpu;
180   required_device<mips3_device> m_maincpu;
181181   required_device<ata_interface_device> m_ata;
182182   required_device<dcs_audio_2k_device> m_dcs;
183183
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201201void kinst_state::machine_start()
202202{
203203   /* set the fastest DRC options */
204   mips3drc_set_options(m_maincpu, MIPS3DRC_FASTEST_OPTIONS);
204   m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS);
205205
206206   /* configure fast RAM regions for DRC */
207   mips3drc_add_fastram(m_maincpu, 0x08000000, 0x087fffff, FALSE, m_rambase2);
208   mips3drc_add_fastram(m_maincpu, 0x00000000, 0x0007ffff, FALSE, m_rambase);
209   mips3drc_add_fastram(m_maincpu, 0x1fc00000, 0x1fc7ffff, TRUE,  m_rombase);
207   m_maincpu->mips3drc_add_fastram(0x08000000, 0x087fffff, FALSE, m_rambase2);
208   m_maincpu->mips3drc_add_fastram(0x00000000, 0x0007ffff, FALSE, m_rambase);
209   m_maincpu->mips3drc_add_fastram(0x1fc00000, 0x1fc7ffff, TRUE,  m_rombase);
210210}
211211
212212
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669669 *
670670 *************************************/
671671
672static const mips3_config r4600_config =
673{
674   16384,              /* code cache size */
675   16384               /* data cache size */
676};
677
678672static MACHINE_CONFIG_START( kinst, kinst_state )
679673
680674   /* basic machine hardware */
681675   MCFG_CPU_ADD("maincpu", R4600LE, MASTER_CLOCK*2)
682   MCFG_CPU_CONFIG(r4600_config)
676   MCFG_MIPS3_ICACHE_SIZE(16384)
677   MCFG_MIPS3_DCACHE_SIZE(16384)
683678   MCFG_CPU_PROGRAM_MAP(main_map)
684679   MCFG_CPU_VBLANK_INT_DRIVER("screen", kinst_state,  irq0_start)
685680
trunk/src/mame/drivers/iteagle.c
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102102      m_voodoo(*this, "voodoo")
103103   {}
104104
105   required_device<cpu_device> m_maincpu;
105   required_device<mips3_device> m_maincpu;
106106   required_device<device_t>   m_voodoo;
107107
108108   DECLARE_DRIVER_INIT(iteagle);
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122122void iteagle_state::machine_start()
123123{
124124   /* set the fastest DRC options */
125   mips3drc_set_options(m_maincpu, MIPS3DRC_FASTEST_OPTIONS);
125   m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS);
126126}
127127
128128
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181181 *
182182 *************************************/
183183
184static const mips3_config r4310_config =
185{
186   16384,              /* code cache size */
187   16384               /* data cache size */
188};
189
190184static MACHINE_CONFIG_START( gtfore, iteagle_state )
191185
192186   /* basic machine hardware */
193187   MCFG_CPU_ADD("maincpu", VR4310LE, 166666666)
194   MCFG_CPU_CONFIG(r4310_config)
188   MCFG_MIPS3_ICACHE_SIZE(16384)
189   MCFG_MIPS3_DCACHE_SIZE(16384)
195190   MCFG_CPU_PROGRAM_MAP(main_map)
196191
197192   MCFG_ATA_INTERFACE_ADD("ata", ata_devices, "hdd", NULL, true)
trunk/src/mame/drivers/seattle.c
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446446   required_shared_ptr<UINT32> m_interrupt_config;
447447   required_shared_ptr<UINT32> m_asic_reset;
448448   required_shared_ptr<UINT32> m_rombase;
449   required_device<cpu_device> m_maincpu;
449   required_device<mips3_device> m_maincpu;
450450   required_device<bus_master_ide_controller_device> m_ide;
451451   optional_device<smc91c94_device> m_ethernet;
452452   optional_device<atari_cage_seattle_device> m_cage;
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564564   m_galileo.timer[3].timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(seattle_state::galileo_timer_callback),this));
565565
566566   /* set the fastest DRC options, but strict verification */
567   mips3drc_set_options(m_maincpu, MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY);
567   m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY);
568568
569569   /* configure fast RAM regions for DRC */
570   mips3drc_add_fastram(m_maincpu, 0x00000000, 0x007fffff, FALSE, m_rambase);
571   mips3drc_add_fastram(m_maincpu, 0x1fc00000, 0x1fc7ffff, TRUE,  m_rombase);
570   m_maincpu->mips3drc_add_fastram(0x00000000, 0x007fffff, FALSE, m_rambase);
571   m_maincpu->mips3drc_add_fastram(0x1fc00000, 0x1fc7ffff, TRUE,  m_rombase);
572572
573573   /* register for save states */
574574   save_item(NAME(m_galileo.reg));
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25062506 *
25072507 *************************************/
25082508
2509static const mips3_config r5000_config =
2510{
2511   16384,      /* code cache size */
2512   16384,      /* data cache size */
2513   SYSTEM_CLOCK    /* system clock rate */
2514};
2515
25162509static MACHINE_CONFIG_START( seattle_common, seattle_state )
25172510
25182511   /* basic machine hardware */
25192512   MCFG_CPU_ADD("maincpu", R5000LE, SYSTEM_CLOCK*3)
2520   MCFG_CPU_CONFIG(r5000_config)
2513   MCFG_MIPS3_ICACHE_SIZE(16384)
2514   MCFG_MIPS3_DCACHE_SIZE(16384)
2515   MCFG_MIPS3_SYSTEM_CLOCK(SYSTEM_CLOCK)
25212516   MCFG_CPU_PROGRAM_MAP(seattle_map)
25222517
25232518   MCFG_NVRAM_ADD_1FILL("nvram")
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25462541
25472542static MACHINE_CONFIG_DERIVED( phoenixsa, seattle_common )
25482543   MCFG_CPU_REPLACE("maincpu", R4700LE, SYSTEM_CLOCK*2)
2549   MCFG_CPU_CONFIG(r5000_config)
2544   MCFG_MIPS3_ICACHE_SIZE(16384)
2545   MCFG_MIPS3_DCACHE_SIZE(16384)
2546   MCFG_MIPS3_SYSTEM_CLOCK(SYSTEM_CLOCK)
25502547   MCFG_CPU_PROGRAM_MAP(seattle_map)
25512548MACHINE_CONFIG_END
25522549
25532550
25542551static MACHINE_CONFIG_DERIVED( seattle150, seattle_common )
25552552   MCFG_CPU_REPLACE("maincpu", R5000LE, SYSTEM_CLOCK*3)
2556   MCFG_CPU_CONFIG(r5000_config)
2553   MCFG_MIPS3_ICACHE_SIZE(16384)
2554   MCFG_MIPS3_DCACHE_SIZE(16384)
2555   MCFG_MIPS3_SYSTEM_CLOCK(SYSTEM_CLOCK)
25572556   MCFG_CPU_PROGRAM_MAP(seattle_map)
25582557MACHINE_CONFIG_END
25592558
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25662565
25672566static MACHINE_CONFIG_DERIVED( seattle200, seattle_common )
25682567   MCFG_CPU_REPLACE("maincpu", R5000LE, SYSTEM_CLOCK*4)
2569   MCFG_CPU_CONFIG(r5000_config)
2568   MCFG_MIPS3_ICACHE_SIZE(16384)
2569   MCFG_MIPS3_DCACHE_SIZE(16384)
2570   MCFG_MIPS3_SYSTEM_CLOCK(SYSTEM_CLOCK)
25702571   MCFG_CPU_PROGRAM_MAP(seattle_map)
25712572MACHINE_CONFIG_END
25722573
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25782579
25792580static MACHINE_CONFIG_DERIVED( flagstaff, seattle_common )
25802581   MCFG_CPU_REPLACE("maincpu", R5000LE, SYSTEM_CLOCK*4)
2581   MCFG_CPU_CONFIG(r5000_config)
2582   MCFG_MIPS3_ICACHE_SIZE(16384)
2583   MCFG_MIPS3_DCACHE_SIZE(16384)
2584   MCFG_MIPS3_SYSTEM_CLOCK(SYSTEM_CLOCK)
25822585   MCFG_CPU_PROGRAM_MAP(seattle_map)
25832586
25842587   MCFG_SMC91C94_ADD("ethernet")
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30033006   init_common(PHOENIX_CONFIG);
30043007
30053008   /* speedups */
3006   mips3drc_add_hotspot(m_maincpu, 0x8004413C, 0x0C0054B4, 250);     /* confirmed */
3007   mips3drc_add_hotspot(m_maincpu, 0x80094930, 0x00A2102B, 250);     /* confirmed */
3008   mips3drc_add_hotspot(m_maincpu, 0x80092984, 0x3C028011, 250);     /* confirmed */
3009   m_maincpu->mips3drc_add_hotspot(0x8004413C, 0x0C0054B4, 250);     /* confirmed */
3010   m_maincpu->mips3drc_add_hotspot(0x80094930, 0x00A2102B, 250);     /* confirmed */
3011   m_maincpu->mips3drc_add_hotspot(0x80092984, 0x3C028011, 250);     /* confirmed */
30093012}
30103013
30113014
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30143017   init_common(SEATTLE_CONFIG);
30153018
30163019   /* speedups */
3017   mips3drc_add_hotspot(m_maincpu, 0x800108F8, 0x8C420000, 250);     /* confirmed */
3020   m_maincpu->mips3drc_add_hotspot(0x800108F8, 0x8C420000, 250);     /* confirmed */
30183021}
30193022
30203023
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30233026   init_common(FLAGSTAFF_CONFIG);
30243027
30253028   /* speedups */
3026   mips3drc_add_hotspot(m_maincpu, 0x80059F34, 0x3C028012, 250);     /* confirmed */
3027   mips3drc_add_hotspot(m_maincpu, 0x800A5AF4, 0x8E300010, 250);     /* confirmed */
3028   mips3drc_add_hotspot(m_maincpu, 0x8004C260, 0x3C028012, 250);     /* confirmed */
3029   m_maincpu->mips3drc_add_hotspot(0x80059F34, 0x3C028012, 250);     /* confirmed */
3030   m_maincpu->mips3drc_add_hotspot(0x800A5AF4, 0x8E300010, 250);     /* confirmed */
3031   m_maincpu->mips3drc_add_hotspot(0x8004C260, 0x3C028012, 250);     /* confirmed */
30293032}
30303033
30313034
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30343037   init_common(FLAGSTAFF_CONFIG);
30353038
30363039   /* speedups */
3037   mips3drc_add_hotspot(m_maincpu, 0x800343E8, 0x3C028012, 250);     /* confirmed */
3038   mips3drc_add_hotspot(m_maincpu, 0x8008F4F0, 0x3C028012, 250);     /* confirmed */
3039   mips3drc_add_hotspot(m_maincpu, 0x800A365C, 0x8E300014, 250);     /* confirmed */
3040   mips3drc_add_hotspot(m_maincpu, 0x80051DAC, 0x3C028012, 250);     /* confirmed */
3040   m_maincpu->mips3drc_add_hotspot(0x800343E8, 0x3C028012, 250);     /* confirmed */
3041   m_maincpu->mips3drc_add_hotspot(0x8008F4F0, 0x3C028012, 250);     /* confirmed */
3042   m_maincpu->mips3drc_add_hotspot(0x800A365C, 0x8E300014, 250);     /* confirmed */
3043   m_maincpu->mips3drc_add_hotspot(0x80051DAC, 0x3C028012, 250);     /* confirmed */
30413044}
30423045
30433046
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30463049   init_common(SEATTLE_WIDGET_CONFIG);
30473050
30483051   /* speedups */
3049   mips3drc_add_hotspot(m_maincpu, 0x80032534, 0x02221024, 250);     /* confirmed */
3050   mips3drc_add_hotspot(m_maincpu, 0x800B1BE4, 0x8E110014, 250);     /* confirmed */
3052   m_maincpu->mips3drc_add_hotspot(0x80032534, 0x02221024, 250);     /* confirmed */
3053   m_maincpu->mips3drc_add_hotspot(0x800B1BE4, 0x8E110014, 250);     /* confirmed */
30513054}
30523055
30533056
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30563059   init_common(SEATTLE_WIDGET_CONFIG);
30573060
30583061   /* speedups */
3059   mips3drc_add_hotspot(m_maincpu, 0x80049F14, 0x3C028020, 250);     /* confirmed */
3060   mips3drc_add_hotspot(m_maincpu, 0x8004859C, 0x3C028020, 250);     /* confirmed */
3061   mips3drc_add_hotspot(m_maincpu, 0x8005922C, 0x8E020014, 250);     /* confirmed */
3062   m_maincpu->mips3drc_add_hotspot(0x80049F14, 0x3C028020, 250);     /* confirmed */
3063   m_maincpu->mips3drc_add_hotspot(0x8004859C, 0x3C028020, 250);     /* confirmed */
3064   m_maincpu->mips3drc_add_hotspot(0x8005922C, 0x8E020014, 250);     /* confirmed */
30623065}
30633066
30643067
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30763079   m_rombase[0x934/4] += 4;
30773080
30783081   /* main CPU speedups */
3079   mips3drc_add_hotspot(m_maincpu, 0x80135510, 0x3C028024, 250);     /* confirmed */
3080   mips3drc_add_hotspot(m_maincpu, 0x800087DC, 0x8E820010, 250);     /* confirmed */
3082   m_maincpu->mips3drc_add_hotspot(0x80135510, 0x3C028024, 250);     /* confirmed */
3083   m_maincpu->mips3drc_add_hotspot(0x800087DC, 0x8E820010, 250);     /* confirmed */
30813084}
30823085
30833086
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30863089   init_common(SEATTLE_CONFIG);
30873090
30883091   /* speedups */
3089   mips3drc_add_hotspot(m_maincpu, 0x8014E41C, 0x3C038025, 250);     /* confirmed */
3090   mips3drc_add_hotspot(m_maincpu, 0x80011F10, 0x8E020018, 250);     /* confirmed */
3092   m_maincpu->mips3drc_add_hotspot(0x8014E41C, 0x3C038025, 250);     /* confirmed */
3093   m_maincpu->mips3drc_add_hotspot(0x80011F10, 0x8E020018, 250);     /* confirmed */
30913094}
30923095
30933096
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30963099   init_common(SEATTLE_CONFIG);
30973100
30983101   /* speedups */
3099   mips3drc_add_hotspot(m_maincpu, 0x8015773C, 0x3C038025, 250);     /* confirmed */
3100   mips3drc_add_hotspot(m_maincpu, 0x80012CA8, 0x8E020018, 250);     /* confirmed */
3102   m_maincpu->mips3drc_add_hotspot(0x8015773C, 0x3C038025, 250);     /* confirmed */
3103   m_maincpu->mips3drc_add_hotspot(0x80012CA8, 0x8E020018, 250);     /* confirmed */
31013104}
31023105
31033106
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31093112   m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x16800000, 0x1680001f, read32_delegate(FUNC(seattle_state::carnevil_gun_r),this), write32_delegate(FUNC(seattle_state::carnevil_gun_w),this));
31103113
31113114   /* speedups */
3112   mips3drc_add_hotspot(m_maincpu, 0x8015176C, 0x3C03801A, 250);     /* confirmed */
3113   mips3drc_add_hotspot(m_maincpu, 0x80011FBC, 0x8E020018, 250);     /* confirmed */
3115   m_maincpu->mips3drc_add_hotspot(0x8015176C, 0x3C03801A, 250);     /* confirmed */
3116   m_maincpu->mips3drc_add_hotspot(0x80011FBC, 0x8E020018, 250);     /* confirmed */
31143117}
31153118
31163119
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31193122   init_common(SEATTLE_WIDGET_CONFIG);
31203123
31213124   /* speedups */
3122   mips3drc_add_hotspot(m_maincpu, 0x801643BC, 0x3C03801B, 250);     /* confirmed */
3123   mips3drc_add_hotspot(m_maincpu, 0x80011FB8, 0x8E020018, 250);     /* confirmed */
3124   //mips3drc_add_hotspot(m_maincpu, 0x80136A80, 0x3C02801D, 250);      /* potential */
3125   m_maincpu->mips3drc_add_hotspot(0x801643BC, 0x3C03801B, 250);     /* confirmed */
3126   m_maincpu->mips3drc_add_hotspot(0x80011FB8, 0x8E020018, 250);     /* confirmed */
3127   //m_maincpu->mips3drc_add_hotspot(0x80136A80, 0x3C02801D, 250);      /* potential */
31253128}
31263129
31273130
trunk/src/mame/drivers/pyson.c
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190190static INPUT_PORTS_START( pyson )
191191INPUT_PORTS_END
192192
193static const mips3_config r5000_config =
194{
195   16384,              /* code cache size - probably wrong */
196   16384               /* data cache size */
197};
198
199193static MACHINE_CONFIG_START( pyson, pyson_state )
200194   MCFG_CPU_ADD("maincpu", R5000LE, 294000000) // imported from namcops2.c driver
195   MCFG_MIPS3_ICACHE_SIZE(16384)
196   MCFG_MIPS3_DCACHE_SIZE(16384)
201197   MCFG_CPU_PROGRAM_MAP(ps2_map)
202   MCFG_CPU_CONFIG(r5000_config)
203198
204199   /* video hardware */
205200   MCFG_SCREEN_ADD("screen", RASTER)
trunk/src/mame/drivers/vegas.c
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466466      m_dcs(*this, "dcs"),
467467      m_ioasic(*this, "ioasic") { }
468468
469   required_device<cpu_device> m_maincpu;
469   required_device<mips3_device> m_maincpu;
470470   required_device<m48t37_device> m_timekeeper;
471471   required_device<bus_master_ide_controller_device> m_ide;
472472   required_device<smc91c94_device> m_ethernet;
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593593      m_dcs_idma_cs = 0;
594594
595595   /* set the fastest DRC options, but strict verification */
596   mips3drc_set_options(m_maincpu, MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY + MIPS3DRC_FLUSH_PC);
596   m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY + MIPS3DRC_FLUSH_PC);
597597
598598   /* configure fast RAM regions for DRC */
599   mips3drc_add_fastram(m_maincpu, 0x00000000, m_rambase.bytes() - 1, FALSE, m_rambase);
600   mips3drc_add_fastram(m_maincpu, 0x1fc00000, 0x1fc7ffff, TRUE, m_rombase);
599   m_maincpu->mips3drc_add_fastram(0x00000000, m_rambase.bytes() - 1, FALSE, m_rambase);
600   m_maincpu->mips3drc_add_fastram(0x1fc00000, 0x1fc7ffff, TRUE, m_rombase);
601601
602602   /* register for save states */
603603   save_item(NAME(m_nile_irq_state));
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22062206 *
22072207 *************************************/
22082208
2209static const mips3_config r5000_config =
2210{
2211   16384,          /* code cache size */
2212   16384,          /* data cache size */
2213   SYSTEM_CLOCK    /* system clock rate */
2214};
2215
22162209static MACHINE_CONFIG_START( vegascore, vegas_state )
22172210
22182211   /* basic machine hardware */
22192212   MCFG_CPU_ADD("maincpu", R5000LE, SYSTEM_CLOCK*2)
2220   MCFG_CPU_CONFIG(r5000_config)
2213   MCFG_MIPS3_ICACHE_SIZE(16384)
2214   MCFG_MIPS3_DCACHE_SIZE(16384)
2215   MCFG_MIPS3_SYSTEM_CLOCK(SYSTEM_CLOCK)
22212216   MCFG_CPU_PROGRAM_MAP(vegas_map_8mb)
22222217
22232218   MCFG_M48T37_ADD("timekeeper")
r30757r30758
22762271
22772272static MACHINE_CONFIG_DERIVED( vegasv3, vegas32m )
22782273   MCFG_CPU_REPLACE("maincpu", RM7000LE, SYSTEM_CLOCK*2.5)
2279   MCFG_CPU_CONFIG(r5000_config)
2274   MCFG_MIPS3_ICACHE_SIZE(16384)
2275   MCFG_MIPS3_DCACHE_SIZE(16384)
2276   MCFG_MIPS3_SYSTEM_CLOCK(SYSTEM_CLOCK)
22802277   MCFG_CPU_PROGRAM_MAP(vegas_map_8mb)
22812278
22822279   MCFG_DEVICE_REMOVE("voodoo")
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22902287
22912288static MACHINE_CONFIG_DERIVED( denver, vegascore )
22922289   MCFG_CPU_REPLACE("maincpu", RM7000LE, SYSTEM_CLOCK*2.5)
2293   MCFG_CPU_CONFIG(r5000_config)
2290   MCFG_MIPS3_ICACHE_SIZE(16384)
2291   MCFG_MIPS3_DCACHE_SIZE(16384)
2292   MCFG_MIPS3_SYSTEM_CLOCK(SYSTEM_CLOCK)
22942293   MCFG_CPU_PROGRAM_MAP(vegas_map_32mb)
22952294
22962295   MCFG_DEVICE_REMOVE("voodoo")
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26022601DRIVER_INIT_MEMBER(vegas_state,gauntleg)
26032602{
26042603   /* speedups */
2605   mips3drc_add_hotspot(m_maincpu, 0x80015430, 0x8CC38060, 250);     /* confirmed */
2606   mips3drc_add_hotspot(m_maincpu, 0x80015464, 0x3C09801E, 250);     /* confirmed */
2607   mips3drc_add_hotspot(m_maincpu, 0x800C8918, 0x8FA2004C, 250);     /* confirmed */
2608   mips3drc_add_hotspot(m_maincpu, 0x800C8890, 0x8FA20024, 250);     /* confirmed */
2604   m_maincpu->mips3drc_add_hotspot(0x80015430, 0x8CC38060, 250);     /* confirmed */
2605   m_maincpu->mips3drc_add_hotspot(0x80015464, 0x3C09801E, 250);     /* confirmed */
2606   m_maincpu->mips3drc_add_hotspot(0x800C8918, 0x8FA2004C, 250);     /* confirmed */
2607   m_maincpu->mips3drc_add_hotspot(0x800C8890, 0x8FA20024, 250);     /* confirmed */
26092608}
26102609
26112610
26122611DRIVER_INIT_MEMBER(vegas_state,gauntdl)
26132612{
26142613   /* speedups */
2615   mips3drc_add_hotspot(m_maincpu, 0x800158B8, 0x8CC3CC40, 250);     /* confirmed */
2616   mips3drc_add_hotspot(m_maincpu, 0x800158EC, 0x3C0C8022, 250);     /* confirmed */
2617   mips3drc_add_hotspot(m_maincpu, 0x800D40C0, 0x8FA2004C, 250);     /* confirmed */
2618   mips3drc_add_hotspot(m_maincpu, 0x800D4038, 0x8FA20024, 250);     /* confirmed */
2614   m_maincpu->mips3drc_add_hotspot(0x800158B8, 0x8CC3CC40, 250);     /* confirmed */
2615   m_maincpu->mips3drc_add_hotspot(0x800158EC, 0x3C0C8022, 250);     /* confirmed */
2616   m_maincpu->mips3drc_add_hotspot(0x800D40C0, 0x8FA2004C, 250);     /* confirmed */
2617   m_maincpu->mips3drc_add_hotspot(0x800D4038, 0x8FA20024, 250);     /* confirmed */
26192618}
26202619
26212620
26222621DRIVER_INIT_MEMBER(vegas_state,warfa)
26232622{
26242623   /* speedups */
2625   mips3drc_add_hotspot(m_maincpu, 0x8009436C, 0x0C031663, 250);     /* confirmed */
2624   m_maincpu->mips3drc_add_hotspot(0x8009436C, 0x0C031663, 250);     /* confirmed */
26262625}
26272626
26282627
26292628DRIVER_INIT_MEMBER(vegas_state,tenthdeg)
26302629{
26312630   /* speedups */
2632   mips3drc_add_hotspot(m_maincpu, 0x80051CD8, 0x0C023C15, 250);     /* confirmed */
2633   mips3drc_add_hotspot(m_maincpu, 0x8005E674, 0x3C028017, 250);     /* confirmed */
2634   mips3drc_add_hotspot(m_maincpu, 0x8002DBCC, 0x8FA2002C, 250);     /* confirmed */
2635   mips3drc_add_hotspot(m_maincpu, 0x80015930, 0x8FC20244, 250);     /* confirmed */
2631   m_maincpu->mips3drc_add_hotspot(0x80051CD8, 0x0C023C15, 250);     /* confirmed */
2632   m_maincpu->mips3drc_add_hotspot(0x8005E674, 0x3C028017, 250);     /* confirmed */
2633   m_maincpu->mips3drc_add_hotspot(0x8002DBCC, 0x8FA2002C, 250);     /* confirmed */
2634   m_maincpu->mips3drc_add_hotspot(0x80015930, 0x8FC20244, 250);     /* confirmed */
26362635}
26372636
26382637
trunk/src/mame/drivers/namcops2.c
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128128static INPUT_PORTS_START( system246 )
129129INPUT_PORTS_END
130130
131static const mips3_config r5000_config =
132{
133   16384,              /* code cache size - probably wrong */
134   16384               /* data cache size */
135};
136
137131static MACHINE_CONFIG_START( system246, namcops2_state )
138132   MCFG_CPU_ADD("maincpu", R5000LE, 294000000) // actually R5900 @ 294 MHz
133   MCFG_MIPS3_ICACHE_SIZE(16384)
134   MCFG_MIPS3_DCACHE_SIZE(16384)
139135   MCFG_CPU_PROGRAM_MAP(ps2_map)
140   MCFG_CPU_CONFIG(r5000_config)
141136
142137   /* video hardware */
143138   MCFG_SCREEN_ADD("screen", RASTER)
trunk/src/mame/drivers/atlantis.c
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5151   virtual void machine_start();
5252   virtual void machine_reset();
5353   UINT32 screen_update_mwskins(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
54   required_device<cpu_device> m_maincpu;
54   required_device<mips3_device> m_maincpu;
5555   required_device<dcs2_audio_denver_device> m_dcs;
5656};
5757
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6565void atlantis_state::machine_start()
6666{
6767   /* set the fastest DRC options */
68   mips3drc_set_options(m_maincpu, MIPS3DRC_FASTEST_OPTIONS);
68   m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS);
6969}
7070
7171
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130130 *
131131 *************************************/
132132
133static const mips3_config r4310_config =
134{
135   16384,              /* code cache size */
136   16384               /* data cache size */
137};
138
139133static MACHINE_CONFIG_START( mwskins, atlantis_state )
140134
141135   /* basic machine hardware */
142136   MCFG_CPU_ADD("maincpu", VR4310LE, 166666666)    // clock is TRUSTED
143   MCFG_CPU_CONFIG(r4310_config)
137   MCFG_MIPS3_ICACHE_SIZE(16384)
138   MCFG_MIPS3_DCACHE_SIZE(16384)
144139   MCFG_CPU_PROGRAM_MAP(main_map)
145140
146141
trunk/src/mame/drivers/namcos23.c
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13791379      m_generic_paletteram_32(*this, "paletteram")
13801380   { }
13811381
1382   required_device<cpu_device> m_maincpu;
1382   required_device<mips3_device> m_maincpu;
13831383   required_device<h83002_device> m_subcpu;
13841384   required_device<h8_adc_device> m_adc;
13851385   optional_device<h83334_device> m_iocpu;
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32223222   m_c361.timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(namcos23_state::c361_timer_cb),this));
32233223   m_c361.timer->adjust(attotime::never);
32243224
3225   mips3drc_add_fastram(m_maincpu, 0, m_mainram.bytes()-1, FALSE, reinterpret_cast<UINT32 *>(memshare("mainram")->ptr()));
3225   m_maincpu->mips3drc_add_fastram(0, m_mainram.bytes()-1, FALSE, reinterpret_cast<UINT32 *>(memshare("mainram")->ptr()));
32263226}
32273227
32283228
r30757r30758
33153315GFXDECODE_END
33163316
33173317
3318static const mips3_config r4650_config =
3319{
3320   8192,               /* code cache size - VERIFIED */
3321   8192                /* data cache size - VERIFIED */
3322};
3323
3324
3325
33263318static MACHINE_CONFIG_START( gorgon, namcos23_state )
33273319
33283320   /* basic machine hardware */
33293321   MCFG_CPU_ADD("maincpu", R4650BE, BUSCLOCK*4)
3330   MCFG_CPU_CONFIG(r4650_config)
3322   MCFG_MIPS3_ICACHE_SIZE(8192)   // VERIFIED
3323   MCFG_MIPS3_DCACHE_SIZE(8192)   // VERIFIED
33313324   MCFG_CPU_PROGRAM_MAP(gorgon_map)
33323325   MCFG_CPU_VBLANK_INT_DRIVER("screen", namcos23_state, interrupt)
33333326
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33953388
33963389   /* basic machine hardware */
33973390   MCFG_CPU_ADD("maincpu", R4650BE, BUSCLOCK*4)
3398   MCFG_CPU_CONFIG(r4650_config)
3391   MCFG_MIPS3_ICACHE_SIZE(8192)   // VERIFIED
3392   MCFG_MIPS3_DCACHE_SIZE(8192)   // VERIFIED
33993393   MCFG_CPU_PROGRAM_MAP(s23_map)
34003394   MCFG_CPU_VBLANK_INT_DRIVER("screen", namcos23_state, interrupt)
34013395
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34833477
34843478   /* basic machine hardware */
34853479   MCFG_CPU_ADD("maincpu", R4650BE, BUSCLOCK*5)
3486   MCFG_CPU_CONFIG(r4650_config)
3480   MCFG_MIPS3_ICACHE_SIZE(8192)   // VERIFIED
3481   MCFG_MIPS3_DCACHE_SIZE(8192)   // VERIFIED
34873482   MCFG_CPU_PROGRAM_MAP(s23_map)
34883483   MCFG_CPU_VBLANK_INT_DRIVER("screen", namcos23_state, interrupt)
34893484
trunk/src/mame/drivers/hng64.c
r30757r30758
18331833}
18341834
18351835
1836/* ?? */
1837static const mips3_config vr4300_config =
1838{
1839   16384,              /* code cache size */
1840   16384               /* data cache size */
1841};
1842
18431836void hng64_state::m_set_irq(UINT32 irq_vector)
18441837{
18451838   /*
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19021895void hng64_state::machine_start()
19031896{
19041897   /* set the fastest DRC options */
1905   mips3drc_set_options(m_maincpu, MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY);
1898   m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY);
19061899
19071900   /* configure fast RAM regions for DRC */
1908   mips3drc_add_fastram(m_maincpu, 0x00000000, 0x00ffffff, FALSE, m_mainram);
1909   mips3drc_add_fastram(m_maincpu, 0x04000000, 0x05ffffff, TRUE,  m_cart);
1910   mips3drc_add_fastram(m_maincpu, 0x1fc00000, 0x1fc7ffff, TRUE,  m_rombase);
1901   m_maincpu->mips3drc_add_fastram(0x00000000, 0x00ffffff, FALSE, m_mainram);
1902   m_maincpu->mips3drc_add_fastram(0x04000000, 0x05ffffff, TRUE,  m_cart);
1903   m_maincpu->mips3drc_add_fastram(0x1fc00000, 0x1fc7ffff, TRUE,  m_rombase);
19111904
19121905   m_comm_rom = memregion("user2")->base();
19131906   m_comm_ram = auto_alloc_array(machine(),UINT8,0x10000);
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19421935
19431936   /* basic machine hardware */
19441937   MCFG_CPU_ADD("maincpu", VR4300BE, MASTER_CLOCK)     // actually R4300
1945   MCFG_CPU_CONFIG(vr4300_config)
1938   MCFG_MIPS3_ICACHE_SIZE(16384)
1939   MCFG_MIPS3_DCACHE_SIZE(16384)
19461940   MCFG_CPU_PROGRAM_MAP(hng_map)
19471941   MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", hng64_state, hng64_irq, "screen", 0, 1)
19481942
trunk/src/mame/drivers/aleck64.c
r30757r30758
810810   PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
811811INPUT_PORTS_END
812812
813/* ?? */
814static const mips3_config vr4300_config =
815{
816   16384,              /* code cache size */
817   8192,               /* data cache size */
818   62500000            /* system clock */
819};
820813
821814static MACHINE_CONFIG_START( aleck64, aleck64_state )
822815
823816   /* basic machine hardware */
824817   MCFG_CPU_ADD("maincpu", VR4300BE, 93750000)
825   MCFG_CPU_CONFIG(vr4300_config)
818   MCFG_MIPS3_ICACHE_SIZE(16384)
819   MCFG_MIPS3_DCACHE_SIZE(8192)
820   MCFG_MIPS3_SYSTEM_CLOCK(62500000)
826821   MCFG_CPU_PROGRAM_MAP(n64_map)
827822
828823   MCFG_CPU_ADD("rsp", RSP, 62500000)
trunk/src/mame/machine/n64.c
r30757r30758
24122412   rsp_imem = reinterpret_cast<UINT32 *>(memshare("rsp_imem")->ptr());
24132413   rsp_dmem = reinterpret_cast<UINT32 *>(memshare("rsp_dmem")->ptr());
24142414
2415   mips3drc_set_options(machine().device("maincpu"), MIPS3DRC_COMPATIBLE_OPTIONS);
2415   dynamic_cast<mips3_device *>(machine().device("maincpu"))->mips3drc_set_options(MIPS3DRC_COMPATIBLE_OPTIONS);
24162416
24172417   /* configure fast RAM regions for DRC */
2418   mips3drc_add_fastram(machine().device("maincpu"), 0x00000000, 0x007fffff, FALSE, rdram);
2418   dynamic_cast<mips3_device *>(machine().device("maincpu"))->mips3drc_add_fastram(0x00000000, 0x007fffff, FALSE, rdram);
24192419
24202420   rspdrc_set_options(machine().device("rsp"), RSPDRC_STRICT_VERIFY);
24212421   rspdrc_flush_drc_cache(machine().device("rsp"));
trunk/src/mame/includes/hng64.h
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11#include "machine/msm6242.h"
2#include "cpu/mips/mips3.h"
23
34enum
45{
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4142      m_generic_paletteram_32(*this, "paletteram")
4243      { }
4344
44   required_device<cpu_device> m_maincpu;
45   required_device<mips3_device> m_maincpu;
4546   required_device<cpu_device> m_audiocpu;
4647   required_device<cpu_device> m_comm;
4748   required_device<msm6242_device> m_rtc;
trunk/src/emu/cpu/mips/mips3com.c
r30757r30758
1313
1414
1515/***************************************************************************
16    DEBUGGING
17***************************************************************************/
18
19#define PRINTF_TLB              (0)
20#define USE_ABI_REG_NAMES       (1)
21
22
23/***************************************************************************
2416    FUNCTION PROTOTYPES
2517***************************************************************************/
2618
27static TIMER_CALLBACK( compare_int_callback );
28
29static UINT32 compute_config_register(const mips3_state *mips);
30static UINT32 compute_prid_register(const mips3_state *mips);
31
32static void tlb_map_entry(mips3_state *mips, int tlbindex);
33static void tlb_write_common(mips3_state *mips, int tlbindex);
3419static void tlb_entry_log_half(mips3_tlb_entry *entry, int tlbindex, int which);
3520
3621
r30757r30758
6146}
6247
6348
64
65/***************************************************************************
66    INITIALIZATION AND SHUTDOWN
67***************************************************************************/
68
69/*-------------------------------------------------
70    mips3com_init - initialize the mips3_state
71    structure based on the configured type
72-------------------------------------------------*/
73
74void mips3com_init(mips3_state *mips, mips3_flavor flavor, int bigendian, legacy_cpu_device *device, device_irq_acknowledge_delegate irqcallback)
49void mips3_device::execute_set_input(int inputnum, int state)
7550{
76   const mips3_config *config = (const mips3_config *)device->static_config();
77   int tlbindex;
78
79   /* initialize based on the config */
80   memset(mips, 0, sizeof(*mips));
81   mips->flavor = flavor;
82   mips->bigendian = bigendian;
83   mips->cpu_clock = device->clock();
84   mips->irq_callback = irqcallback;
85   mips->device = device;
86   mips->program = &device->space(AS_PROGRAM);
87   mips->direct = &mips->program->direct();
88   mips->icache_size = config->icache;
89   mips->dcache_size = config->dcache;
90   mips->system_clock = config->system_clock;
91
92   /* configure flavor-specific parameters */
93   mips->pfnmask = 0x00ffffff;
94   mips->tlbentries = MIPS3_MAX_TLB_ENTRIES;
95
96   /* VR4300 and VR5432 have 4 fewer PFN bits, and only 32 TLB entries */
97   if (flavor == MIPS3_TYPE_VR4300)
51   if (inputnum >= MIPS3_IRQ0 && inputnum <= MIPS3_IRQ5)
9852   {
99      mips->pfnmask = 0x000fffff;
100      mips->tlbentries = 32;
53      if (state != CLEAR_LINE)
54         m_core->cpr[0][COP0_Cause] |= 0x400 << inputnum;
55      else
56         m_core->cpr[0][COP0_Cause] &= ~(0x400 << inputnum);
10157   }
102
103   /* set up the endianness */
104   mips->program->accessors(mips->memory);
105
106   /* allocate the virtual TLB */
107   mips->vtlb = vtlb_alloc(device, AS_PROGRAM, 2 * mips->tlbentries + 2, 0);
108
109   /* allocate a timer for the compare interrupt */
110   mips->compare_int_timer = device->machine().scheduler().timer_alloc(FUNC(compare_int_callback), (void *)device);
111
112   /* reset the state */
113   mips3com_reset(mips);
114
115   /* register for save states */
116   device->save_item(NAME(mips->pc));
117   device->save_item(NAME(mips->r));
118   device->save_item(NAME(mips->cpr));
119   device->save_item(NAME(mips->ccr));
120   device->save_item(NAME(mips->llbit));
121   device->save_item(NAME(mips->count_zero_time));
122   for (tlbindex = 0; tlbindex < mips->tlbentries; tlbindex++)
123   {
124      device->save_item(NAME(mips->tlb[tlbindex].page_mask), tlbindex);
125      device->save_item(NAME(mips->tlb[tlbindex].entry_hi), tlbindex);
126      device->save_item(NAME(mips->tlb[tlbindex].entry_lo), tlbindex);
127   }
12858}
12959
13060
131/*-------------------------------------------------
132    mips3com_exit - common cleanup/exit
133-------------------------------------------------*/
61/***************************************************************************
62    INITIALIZATION AND SHUTDOWN
63***************************************************************************/
13464
135void mips3com_exit(mips3_state *mips)
136{
137   if (mips->vtlb != NULL)
138      vtlb_free(mips->vtlb);
139}
140
141
14265/*-------------------------------------------------
143    mips3com_reset - reset the state of all the
144    registers
145-------------------------------------------------*/
146
147void mips3com_reset(mips3_state *mips)
148{
149   int tlbindex;
150
151   /* initialize the state */
152   mips->pc = 0xbfc00000;
153   mips->cpr[0][COP0_Status] = SR_BEV | SR_ERL;
154   mips->cpr[0][COP0_Wired] = 0;
155   mips->cpr[0][COP0_Compare] = 0xffffffff;
156   mips->cpr[0][COP0_Count] = 0;
157   mips->cpr[0][COP0_Config] = compute_config_register(mips);
158   mips->cpr[0][COP0_PRId] = compute_prid_register(mips);
159   mips->count_zero_time = mips->device->total_cycles();
160
161   /* initialize the TLB state */
162   for (tlbindex = 0; tlbindex < mips->tlbentries; tlbindex++)
163   {
164      mips3_tlb_entry *entry = &mips->tlb[tlbindex];
165      entry->page_mask = 0;
166      entry->entry_hi = 0xffffffff;
167      entry->entry_lo[0] = 0xfffffff8;
168      entry->entry_lo[1] = 0xfffffff8;
169      vtlb_load(mips->vtlb, 2 * tlbindex + 0, 0, 0, 0);
170      vtlb_load(mips->vtlb, 2 * tlbindex + 1, 0, 0, 0);
171   }
172
173   /* load the fixed TLB range */
174   vtlb_load(mips->vtlb, 2 * mips->tlbentries + 0, (0xa0000000 - 0x80000000) >> MIPS3_MIN_PAGE_SHIFT, 0x80000000, 0x00000000 | VTLB_READ_ALLOWED | VTLB_WRITE_ALLOWED | VTLB_FETCH_ALLOWED | VTLB_FLAG_VALID);
175   vtlb_load(mips->vtlb, 2 * mips->tlbentries + 1, (0xc0000000 - 0xa0000000) >> MIPS3_MIN_PAGE_SHIFT, 0xa0000000, 0x00000000 | VTLB_READ_ALLOWED | VTLB_WRITE_ALLOWED | VTLB_FETCH_ALLOWED | VTLB_FLAG_VALID);
176}
177
178
179/*-------------------------------------------------
180    mips3com_dasm - handle disassembly for a
181    CPU
182-------------------------------------------------*/
183
184offs_t mips3com_dasm(mips3_state *mips, char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram)
185{
186   extern unsigned dasmmips3(char *, unsigned, UINT32);
187   UINT32 op = *(UINT32 *)oprom;
188   if (mips->bigendian)
189      op = BIG_ENDIANIZE_INT32(op);
190   else
191      op = LITTLE_ENDIANIZE_INT32(op);
192   return dasmmips3(buffer, pc, op);
193}
194
195
196/*-------------------------------------------------
19766    mips3com_update_cycle_counting - update cycle
19867    counts and the timers
19968-------------------------------------------------*/
20069
201void mips3com_update_cycle_counting(mips3_state *mips)
70void mips3_device::mips3com_update_cycle_counting()
20271{
20372   /* modify the timer to go off */
204   if (mips->compare_armed && (mips->cpr[0][COP0_Status] & SR_IMEX5))
73   if (m_core->compare_armed && (m_core->cpr[0][COP0_Status] & SR_IMEX5))
20574   {
206      UINT32 count = (mips->device->total_cycles() - mips->count_zero_time) / 2;
207      UINT32 compare = mips->cpr[0][COP0_Compare];
75      UINT32 count = (total_cycles() - m_core->count_zero_time) / 2;
76      UINT32 compare = m_core->cpr[0][COP0_Compare];
20877      UINT32 delta = compare - count;
209      attotime newtime = mips->device->cycles_to_attotime((UINT64)delta * 2);
210      mips->compare_int_timer->adjust(newtime);
78      attotime newtime = cycles_to_attotime((UINT64)delta * 2);
79      m_compare_int_timer->adjust(newtime);
21180      return;
21281   }
213   mips->compare_int_timer->adjust(attotime::never);
82   m_compare_int_timer->adjust(attotime::never);
21483}
21584
21685
r30757r30758
22493    TLB entries
22594-------------------------------------------------*/
22695
227void mips3com_asid_changed(mips3_state *mips)
96void mips3_device::mips3com_asid_changed()
22897{
22998   int tlbindex;
23099
231100   /* iterate over all non-global TLB entries and remap them */
232   for (tlbindex = 0; tlbindex < mips->tlbentries; tlbindex++)
233      if (!tlb_entry_is_global(&mips->tlb[tlbindex]))
234         tlb_map_entry(mips, tlbindex);
101   for (tlbindex = 0; tlbindex < m_tlbentries; tlbindex++)
102      if (!tlb_entry_is_global(&m_tlb[tlbindex]))
103         tlb_map_entry(tlbindex);
235104}
236105
237106
238107/*-------------------------------------------------
239    mips3com_translate_address - translate an address
240    from logical to physical
241-------------------------------------------------*/
242
243int mips3com_translate_address(mips3_state *mips, address_spacenum space, int intention, offs_t *address)
244{
245   /* only applies to the program address space */
246   if (space == AS_PROGRAM)
247   {
248      const vtlb_entry *table = vtlb_table(mips->vtlb);
249      vtlb_entry entry = table[*address >> MIPS3_MIN_PAGE_SHIFT];
250      if ((entry & (1 << (intention & (TRANSLATE_TYPE_MASK | TRANSLATE_USER_MASK)))) == 0)
251         return FALSE;
252      *address = (entry & ~MIPS3_MIN_PAGE_MASK) | (*address & MIPS3_MIN_PAGE_MASK);
253   }
254   return TRUE;
255}
256
257
258/*-------------------------------------------------
259108    mips3com_tlbr - execute the tlbr instruction
260109-------------------------------------------------*/
261110
262void mips3com_tlbr(mips3_state *mips)
111void mips3_device::mips3com_tlbr()
263112{
264   UINT32 tlbindex = mips->cpr[0][COP0_Index] & 0x3f;
113   UINT32 tlbindex = m_core->cpr[0][COP0_Index] & 0x3f;
265114
266115   /* only handle entries within the TLB */
267   if (tlbindex < mips->tlbentries)
116   if (tlbindex < m_tlbentries)
268117   {
269      mips3_tlb_entry *entry = &mips->tlb[tlbindex];
118      mips3_tlb_entry *entry = &m_tlb[tlbindex];
270119
271120      /* copy data from the TLB entry into the COP0 registers */
272      mips->cpr[0][COP0_PageMask] = entry->page_mask;
273      mips->cpr[0][COP0_EntryHi] = entry->entry_hi;
274      mips->cpr[0][COP0_EntryLo0] = entry->entry_lo[0];
275      mips->cpr[0][COP0_EntryLo1] = entry->entry_lo[1];
121      m_core->cpr[0][COP0_PageMask] = entry->page_mask;
122      m_core->cpr[0][COP0_EntryHi] = entry->entry_hi;
123      m_core->cpr[0][COP0_EntryLo0] = entry->entry_lo[0];
124      m_core->cpr[0][COP0_EntryLo1] = entry->entry_lo[1];
276125   }
277126}
278127
r30757r30758
281130    mips3com_tlbwi - execute the tlbwi instruction
282131-------------------------------------------------*/
283132
284void mips3com_tlbwi(mips3_state *mips)
133void mips3_device::mips3com_tlbwi()
285134{
286135   /* use the common handler and write based off the COP0 Index register */
287   tlb_write_common(mips, mips->cpr[0][COP0_Index] & 0x3f);
136   tlb_write_common(m_core->cpr[0][COP0_Index] & 0x3f);
288137}
289138
290139
r30757r30758
292141    mips3com_tlbwr - execute the tlbwr instruction
293142-------------------------------------------------*/
294143
295void mips3com_tlbwr(mips3_state *mips)
144void mips3_device::mips3com_tlbwr()
296145{
297   UINT32 wired = mips->cpr[0][COP0_Wired] & 0x3f;
298   UINT32 unwired = mips->tlbentries - wired;
299   UINT32 tlbindex = mips->tlbentries - 1;
146   UINT32 wired = m_core->cpr[0][COP0_Wired] & 0x3f;
147   UINT32 unwired = m_tlbentries - wired;
148   UINT32 tlbindex = m_tlbentries - 1;
300149
301150   /* "random" is based off of the current cycle counting through the non-wired pages */
302151   if (unwired > 0)
303      tlbindex = ((mips->device->total_cycles() - mips->count_zero_time) % unwired + wired) & 0x3f;
152      tlbindex = ((total_cycles() - m_core->count_zero_time) % unwired + wired) & 0x3f;
304153
305154   /* use the common handler to write to this tlbindex */
306   tlb_write_common(mips, tlbindex);
155   tlb_write_common(tlbindex);
307156}
308157
309158
r30757r30758
311160    mips3com_tlbp - execute the tlbp instruction
312161-------------------------------------------------*/
313162
314void mips3com_tlbp(mips3_state *mips)
163void mips3_device::mips3com_tlbp()
315164{
316165   UINT32 tlbindex;
317//  UINT64 vpn;
318166
319167   /* iterate over TLB entries */
320   for (tlbindex = 0; tlbindex < mips->tlbentries; tlbindex++)
168   for (tlbindex = 0; tlbindex < m_tlbentries; tlbindex++)
321169   {
322      mips3_tlb_entry *entry = &mips->tlb[tlbindex];
170      mips3_tlb_entry *entry = &m_tlb[tlbindex];
323171      UINT64 mask = ~((entry->page_mask >> 13) & 0xfff) << 13;
324172
325173      /* if the relevant bits of EntryHi match the relevant bits of the TLB */
326      if ((entry->entry_hi & mask) == (mips->cpr[0][COP0_EntryHi] & mask))
174      if ((entry->entry_hi & mask) == (m_core->cpr[0][COP0_EntryHi] & mask))
327175
328176         /* and if we are either global or matching the current ASID, then stop */
329         if ((entry->entry_hi & 0xff) == (mips->cpr[0][COP0_EntryHi] & 0xff) || ((entry->entry_lo[0] & entry->entry_lo[1]) & TLB_GLOBAL))
177         if ((entry->entry_hi & 0xff) == (m_core->cpr[0][COP0_EntryHi] & 0xff) || ((entry->entry_lo[0] & entry->entry_lo[1]) & TLB_GLOBAL))
330178            break;
331179   }
332180
333181   /* validate that our tlb_table was in sync */
334//  vpn = ((mips->cpr[0][COP0_EntryHi] >> 13) & 0x07ffffff) << 1;
335   if (tlbindex != mips->tlbentries)
336      mips->cpr[0][COP0_Index] = tlbindex;
182//  vpn = ((m_cores->cpr[0][COP0_EntryHi] >> 13) & 0x07ffffff) << 1;
183   if (tlbindex != m_tlbentries)
184      m_core->cpr[0][COP0_Index] = tlbindex;
337185   else
338      mips->cpr[0][COP0_Index] = 0x80000000;
186      m_core->cpr[0][COP0_Index] = 0x80000000;
339187}
340188
341189
342190
343191/***************************************************************************
344    COMMON GET/SET INFO
345***************************************************************************/
346
347/*-------------------------------------------------
348    mips3com_set_info - set information about
349    a MIPS 3 CPU
350-------------------------------------------------*/
351
352void mips3com_set_info(mips3_state *mips, UINT32 state, cpuinfo *info)
353{
354   switch (state)
355   {
356      /* --- the following bits of info are set as 64-bit signed integers --- */
357      case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ0:      mips3com_set_irq_line(mips, MIPS3_IRQ0, info->i);   break;
358      case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ1:      mips3com_set_irq_line(mips, MIPS3_IRQ1, info->i);   break;
359      case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ2:      mips3com_set_irq_line(mips, MIPS3_IRQ2, info->i);   break;
360      case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ3:      mips3com_set_irq_line(mips, MIPS3_IRQ3, info->i);   break;
361      case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ4:      mips3com_set_irq_line(mips, MIPS3_IRQ4, info->i);   break;
362      case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ5:      mips3com_set_irq_line(mips, MIPS3_IRQ5, info->i);   break;
363
364      case CPUINFO_INT_PC:
365      case CPUINFO_INT_REGISTER + MIPS3_PC:           mips->pc = info->i;                     break;
366      case CPUINFO_INT_REGISTER + MIPS3_SR:           mips->cpr[0][COP0_Status] = info->i;    break;
367      case CPUINFO_INT_REGISTER + MIPS3_EPC:          mips->cpr[0][COP0_EPC] = info->i;       break;
368      case CPUINFO_INT_REGISTER + MIPS3_CAUSE:        mips->cpr[0][COP0_Cause] = info->i;     break;
369      case CPUINFO_INT_REGISTER + MIPS3_COUNT:        mips->cpr[0][COP0_Count] = info->i;     break;
370      case CPUINFO_INT_REGISTER + MIPS3_COMPARE:      mips->cpr[0][COP0_Compare] = info->i;   break;
371      case CPUINFO_INT_REGISTER + MIPS3_INDEX:        mips->cpr[0][COP0_Index] = info->i;     break;
372      case CPUINFO_INT_REGISTER + MIPS3_RANDOM:       mips->cpr[0][COP0_Random] = info->i;    break;
373      case CPUINFO_INT_REGISTER + MIPS3_ENTRYHI:      mips->cpr[0][COP0_EntryHi] = info->i;   break;
374      case CPUINFO_INT_REGISTER + MIPS3_ENTRYLO0:     mips->cpr[0][COP0_EntryLo0] = info->i;  break;
375      case CPUINFO_INT_REGISTER + MIPS3_ENTRYLO1:     mips->cpr[0][COP0_EntryLo1] = info->i;  break;
376      case CPUINFO_INT_REGISTER + MIPS3_PAGEMASK:     mips->cpr[0][COP0_PageMask] = info->i;  break;
377      case CPUINFO_INT_REGISTER + MIPS3_WIRED:        mips->cpr[0][COP0_Wired] = info->i;     break;
378      case CPUINFO_INT_REGISTER + MIPS3_BADVADDR:     mips->cpr[0][COP0_BadVAddr] = info->i;  break;
379
380      case CPUINFO_INT_REGISTER + MIPS3_R0:           /* can't change R0 */                   break;
381      case CPUINFO_INT_REGISTER + MIPS3_R1:           mips->r[1] = info->i;                   break;
382      case CPUINFO_INT_REGISTER + MIPS3_R2:           mips->r[2] = info->i;                   break;
383      case CPUINFO_INT_REGISTER + MIPS3_R3:           mips->r[3] = info->i;                   break;
384      case CPUINFO_INT_REGISTER + MIPS3_R4:           mips->r[4] = info->i;                   break;
385      case CPUINFO_INT_REGISTER + MIPS3_R5:           mips->r[5] = info->i;                   break;
386      case CPUINFO_INT_REGISTER + MIPS3_R6:           mips->r[6] = info->i;                   break;
387      case CPUINFO_INT_REGISTER + MIPS3_R7:           mips->r[7] = info->i;                   break;
388      case CPUINFO_INT_REGISTER + MIPS3_R8:           mips->r[8] = info->i;                   break;
389      case CPUINFO_INT_REGISTER + MIPS3_R9:           mips->r[9] = info->i;                   break;
390      case CPUINFO_INT_REGISTER + MIPS3_R10:          mips->r[10] = info->i;                  break;
391      case CPUINFO_INT_REGISTER + MIPS3_R11:          mips->r[11] = info->i;                  break;
392      case CPUINFO_INT_REGISTER + MIPS3_R12:          mips->r[12] = info->i;                  break;
393      case CPUINFO_INT_REGISTER + MIPS3_R13:          mips->r[13] = info->i;                  break;
394      case CPUINFO_INT_REGISTER + MIPS3_R14:          mips->r[14] = info->i;                  break;
395      case CPUINFO_INT_REGISTER + MIPS3_R15:          mips->r[15] = info->i;                  break;
396      case CPUINFO_INT_REGISTER + MIPS3_R16:          mips->r[16] = info->i;                  break;
397      case CPUINFO_INT_REGISTER + MIPS3_R17:          mips->r[17] = info->i;                  break;
398      case CPUINFO_INT_REGISTER + MIPS3_R18:          mips->r[18] = info->i;                  break;
399      case CPUINFO_INT_REGISTER + MIPS3_R19:          mips->r[19] = info->i;                  break;
400      case CPUINFO_INT_REGISTER + MIPS3_R20:          mips->r[20] = info->i;                  break;
401      case CPUINFO_INT_REGISTER + MIPS3_R21:          mips->r[21] = info->i;                  break;
402      case CPUINFO_INT_REGISTER + MIPS3_R22:          mips->r[22] = info->i;                  break;
403      case CPUINFO_INT_REGISTER + MIPS3_R23:          mips->r[23] = info->i;                  break;
404      case CPUINFO_INT_REGISTER + MIPS3_R24:          mips->r[24] = info->i;                  break;
405      case CPUINFO_INT_REGISTER + MIPS3_R25:          mips->r[25] = info->i;                  break;
406      case CPUINFO_INT_REGISTER + MIPS3_R26:          mips->r[26] = info->i;                  break;
407      case CPUINFO_INT_REGISTER + MIPS3_R27:          mips->r[27] = info->i;                  break;
408      case CPUINFO_INT_REGISTER + MIPS3_R28:          mips->r[28] = info->i;                  break;
409      case CPUINFO_INT_REGISTER + MIPS3_R29:          mips->r[29] = info->i;                  break;
410      case CPUINFO_INT_REGISTER + MIPS3_R30:          mips->r[30] = info->i;                  break;
411      case CPUINFO_INT_SP:
412      case CPUINFO_INT_REGISTER + MIPS3_R31:          mips->r[31] = info->i;                  break;
413      case CPUINFO_INT_REGISTER + MIPS3_HI:           mips->r[REG_HI] = info->i;              break;
414      case CPUINFO_INT_REGISTER + MIPS3_LO:           mips->r[REG_LO] = info->i;              break;
415
416      case CPUINFO_INT_REGISTER + MIPS3_FPR0:         mips->cpr[1][0] = info->i;              break;
417      case CPUINFO_INT_REGISTER + MIPS3_FPR1:         mips->cpr[1][1] = info->i;              break;
418      case CPUINFO_INT_REGISTER + MIPS3_FPR2:         mips->cpr[1][2] = info->i;              break;
419      case CPUINFO_INT_REGISTER + MIPS3_FPR3:         mips->cpr[1][3] = info->i;              break;
420      case CPUINFO_INT_REGISTER + MIPS3_FPR4:         mips->cpr[1][4] = info->i;              break;
421      case CPUINFO_INT_REGISTER + MIPS3_FPR5:         mips->cpr[1][5] = info->i;              break;
422      case CPUINFO_INT_REGISTER + MIPS3_FPR6:         mips->cpr[1][6] = info->i;              break;
423      case CPUINFO_INT_REGISTER + MIPS3_FPR7:         mips->cpr[1][7] = info->i;              break;
424      case CPUINFO_INT_REGISTER + MIPS3_FPR8:         mips->cpr[1][8] = info->i;              break;
425      case CPUINFO_INT_REGISTER + MIPS3_FPR9:         mips->cpr[1][9] = info->i;              break;
426      case CPUINFO_INT_REGISTER + MIPS3_FPR10:        mips->cpr[1][10] = info->i;             break;
427      case CPUINFO_INT_REGISTER + MIPS3_FPR11:        mips->cpr[1][11] = info->i;             break;
428      case CPUINFO_INT_REGISTER + MIPS3_FPR12:        mips->cpr[1][12] = info->i;             break;
429      case CPUINFO_INT_REGISTER + MIPS3_FPR13:        mips->cpr[1][13] = info->i;             break;
430      case CPUINFO_INT_REGISTER + MIPS3_FPR14:        mips->cpr[1][14] = info->i;             break;
431      case CPUINFO_INT_REGISTER + MIPS3_FPR15:        mips->cpr[1][15] = info->i;             break;
432      case CPUINFO_INT_REGISTER + MIPS3_FPR16:        mips->cpr[1][16] = info->i;             break;
433      case CPUINFO_INT_REGISTER + MIPS3_FPR17:        mips->cpr[1][17] = info->i;             break;
434      case CPUINFO_INT_REGISTER + MIPS3_FPR18:        mips->cpr[1][18] = info->i;             break;
435      case CPUINFO_INT_REGISTER + MIPS3_FPR19:        mips->cpr[1][19] = info->i;             break;
436      case CPUINFO_INT_REGISTER + MIPS3_FPR20:        mips->cpr[1][20] = info->i;             break;
437      case CPUINFO_INT_REGISTER + MIPS3_FPR21:        mips->cpr[1][21] = info->i;             break;
438      case CPUINFO_INT_REGISTER + MIPS3_FPR22:        mips->cpr[1][22] = info->i;             break;
439      case CPUINFO_INT_REGISTER + MIPS3_FPR23:        mips->cpr[1][23] = info->i;             break;
440      case CPUINFO_INT_REGISTER + MIPS3_FPR24:        mips->cpr[1][24] = info->i;             break;
441      case CPUINFO_INT_REGISTER + MIPS3_FPR25:        mips->cpr[1][25] = info->i;             break;
442      case CPUINFO_INT_REGISTER + MIPS3_FPR26:        mips->cpr[1][26] = info->i;             break;
443      case CPUINFO_INT_REGISTER + MIPS3_FPR27:        mips->cpr[1][27] = info->i;             break;
444      case CPUINFO_INT_REGISTER + MIPS3_FPR28:        mips->cpr[1][28] = info->i;             break;
445      case CPUINFO_INT_REGISTER + MIPS3_FPR29:        mips->cpr[1][29] = info->i;             break;
446      case CPUINFO_INT_REGISTER + MIPS3_FPR30:        mips->cpr[1][30] = info->i;             break;
447      case CPUINFO_INT_REGISTER + MIPS3_FPR31:        mips->cpr[1][31] = info->i;             break;
448   }
449}
450
451
452/*-------------------------------------------------
453    mips3com_get_info - get information about
454    a MIPS 3 CPU
455-------------------------------------------------*/
456
457void mips3com_get_info(mips3_state *mips, UINT32 state, cpuinfo *info)
458{
459   switch (state)
460   {
461      /* --- the following bits of info are returned as 64-bit signed integers --- */
462      case CPUINFO_INT_CONTEXT_SIZE:                  /* provided by core */                  break;
463      case CPUINFO_INT_INPUT_LINES:                   info->i = 6;                            break;
464      case CPUINFO_INT_DEFAULT_IRQ_VECTOR:            info->i = 0;                            break;
465      case CPUINFO_INT_ENDIANNESS:                    info->i = mips->bigendian ? ENDIANNESS_BIG : ENDIANNESS_LITTLE; break;
466      case CPUINFO_INT_CLOCK_MULTIPLIER:              info->i = 1;                            break;
467      case CPUINFO_INT_CLOCK_DIVIDER:                 info->i = 1;                            break;
468      case CPUINFO_INT_MIN_INSTRUCTION_BYTES:         info->i = 4;                            break;
469      case CPUINFO_INT_MAX_INSTRUCTION_BYTES:         info->i = 4;                            break;
470      case CPUINFO_INT_MIN_CYCLES:                    info->i = 1;                            break;
471      case CPUINFO_INT_MAX_CYCLES:                    info->i = 40;                           break;
472
473      case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM:    info->i = MIPS3_MAX_PADDR_SHIFT;break;
474      case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32;                  break;
475      case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0;                   break;
476      case CPUINFO_INT_LOGADDR_WIDTH_PROGRAM: info->i = 32;                   break;
477      case CPUINFO_INT_PAGE_SHIFT_PROGRAM:    info->i = MIPS3_MIN_PAGE_SHIFT; break;
478
479      case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ0:      info->i = (mips->cpr[0][COP0_Cause] & 0x400) ? ASSERT_LINE : CLEAR_LINE;    break;
480      case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ1:      info->i = (mips->cpr[0][COP0_Cause] & 0x800) ? ASSERT_LINE : CLEAR_LINE;    break;
481      case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ2:      info->i = (mips->cpr[0][COP0_Cause] & 0x1000) ? ASSERT_LINE : CLEAR_LINE;   break;
482      case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ3:      info->i = (mips->cpr[0][COP0_Cause] & 0x2000) ? ASSERT_LINE : CLEAR_LINE;   break;
483      case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ4:      info->i = (mips->cpr[0][COP0_Cause] & 0x4000) ? ASSERT_LINE : CLEAR_LINE;   break;
484      case CPUINFO_INT_INPUT_STATE + MIPS3_IRQ5:      info->i = (mips->cpr[0][COP0_Cause] & 0x8000) ? ASSERT_LINE : CLEAR_LINE;   break;
485
486      case CPUINFO_INT_PREVIOUSPC:                    /* optionally implemented */            break;
487
488      case CPUINFO_INT_PC:
489      case CPUINFO_INT_REGISTER + MIPS3_PC:           info->i = mips->pc;                     break;
490      case CPUINFO_INT_REGISTER + MIPS3_SR:           info->i = mips->cpr[0][COP0_Status];    break;
491      case CPUINFO_INT_REGISTER + MIPS3_EPC:          info->i = mips->cpr[0][COP0_EPC];       break;
492      case CPUINFO_INT_REGISTER + MIPS3_CAUSE:        info->i = mips->cpr[0][COP0_Cause];     break;
493      case CPUINFO_INT_REGISTER + MIPS3_COUNT:        info->i = ((mips->device->total_cycles() - mips->count_zero_time) / 2); break;
494      case CPUINFO_INT_REGISTER + MIPS3_COMPARE:      info->i = mips->cpr[0][COP0_Compare];   break;
495      case CPUINFO_INT_REGISTER + MIPS3_INDEX:        info->i = mips->cpr[0][COP0_Index];     break;
496      case CPUINFO_INT_REGISTER + MIPS3_RANDOM:       info->i = mips->cpr[0][COP0_Random];    break;
497      case CPUINFO_INT_REGISTER + MIPS3_ENTRYHI:      info->i = mips->cpr[0][COP0_EntryHi];   break;
498      case CPUINFO_INT_REGISTER + MIPS3_ENTRYLO0:     info->i = mips->cpr[0][COP0_EntryLo0];  break;
499      case CPUINFO_INT_REGISTER + MIPS3_ENTRYLO1:     info->i = mips->cpr[0][COP0_EntryLo1];  break;
500      case CPUINFO_INT_REGISTER + MIPS3_PAGEMASK:     info->i = mips->cpr[0][COP0_PageMask];  break;
501      case CPUINFO_INT_REGISTER + MIPS3_WIRED:        info->i = mips->cpr[0][COP0_Wired];     break;
502      case CPUINFO_INT_REGISTER + MIPS3_BADVADDR:     info->i = mips->cpr[0][COP0_BadVAddr];  break;
503
504      case CPUINFO_INT_REGISTER + MIPS3_R0:           info->i = mips->r[0];                   break;
505      case CPUINFO_INT_REGISTER + MIPS3_R1:           info->i = mips->r[1];                   break;
506      case CPUINFO_INT_REGISTER + MIPS3_R2:           info->i = mips->r[2];                   break;
507      case CPUINFO_INT_REGISTER + MIPS3_R3:           info->i = mips->r[3];                   break;
508      case CPUINFO_INT_REGISTER + MIPS3_R4:           info->i = mips->r[4];                   break;
509      case CPUINFO_INT_REGISTER + MIPS3_R5:           info->i = mips->r[5];                   break;
510      case CPUINFO_INT_REGISTER + MIPS3_R6:           info->i = mips->r[6];                   break;
511      case CPUINFO_INT_REGISTER + MIPS3_R7:           info->i = mips->r[7];                   break;
512      case CPUINFO_INT_REGISTER + MIPS3_R8:           info->i = mips->r[8];                   break;
513      case CPUINFO_INT_REGISTER + MIPS3_R9:           info->i = mips->r[9];                   break;
514      case CPUINFO_INT_REGISTER + MIPS3_R10:          info->i = mips->r[10];                  break;
515      case CPUINFO_INT_REGISTER + MIPS3_R11:          info->i = mips->r[11];                  break;
516      case CPUINFO_INT_REGISTER + MIPS3_R12:          info->i = mips->r[12];                  break;
517      case CPUINFO_INT_REGISTER + MIPS3_R13:          info->i = mips->r[13];                  break;
518      case CPUINFO_INT_REGISTER + MIPS3_R14:          info->i = mips->r[14];                  break;
519      case CPUINFO_INT_REGISTER + MIPS3_R15:          info->i = mips->r[15];                  break;
520      case CPUINFO_INT_REGISTER + MIPS3_R16:          info->i = mips->r[16];                  break;
521      case CPUINFO_INT_REGISTER + MIPS3_R17:          info->i = mips->r[17];                  break;
522      case CPUINFO_INT_REGISTER + MIPS3_R18:          info->i = mips->r[18];                  break;
523      case CPUINFO_INT_REGISTER + MIPS3_R19:          info->i = mips->r[19];                  break;
524      case CPUINFO_INT_REGISTER + MIPS3_R20:          info->i = mips->r[20];                  break;
525      case CPUINFO_INT_REGISTER + MIPS3_R21:          info->i = mips->r[21];                  break;
526      case CPUINFO_INT_REGISTER + MIPS3_R22:          info->i = mips->r[22];                  break;
527      case CPUINFO_INT_REGISTER + MIPS3_R23:          info->i = mips->r[23];                  break;
528      case CPUINFO_INT_REGISTER + MIPS3_R24:          info->i = mips->r[24];                  break;
529      case CPUINFO_INT_REGISTER + MIPS3_R25:          info->i = mips->r[25];                  break;
530      case CPUINFO_INT_REGISTER + MIPS3_R26:          info->i = mips->r[26];                  break;
531      case CPUINFO_INT_REGISTER + MIPS3_R27:          info->i = mips->r[27];                  break;
532      case CPUINFO_INT_REGISTER + MIPS3_R28:          info->i = mips->r[28];                  break;
533      case CPUINFO_INT_REGISTER + MIPS3_R29:          info->i = mips->r[29];                  break;
534      case CPUINFO_INT_REGISTER + MIPS3_R30:          info->i = mips->r[30];                  break;
535      case CPUINFO_INT_SP:
536      case CPUINFO_INT_REGISTER + MIPS3_R31:          info->i = mips->r[31];                  break;
537      case CPUINFO_INT_REGISTER + MIPS3_HI:           info->i = mips->r[REG_HI];              break;
538      case CPUINFO_INT_REGISTER + MIPS3_LO:           info->i = mips->r[REG_LO];              break;
539
540      /* --- the following bits of info are returned as pointers to data or functions --- */
541      case CPUINFO_FCT_SET_INFO:                      /* provided by core */                  break;
542      case CPUINFO_FCT_INIT:                          /* provided by core */                  break;
543      case CPUINFO_FCT_RESET:                         /* provided by core */                  break;
544      case CPUINFO_FCT_EXIT:                          /* provided by core */                  break;
545      case CPUINFO_FCT_EXECUTE:                       /* provided by core */                  break;
546      case CPUINFO_FCT_TRANSLATE:                     /* provided by core */                  break;
547      case CPUINFO_FCT_DISASSEMBLE:                   /* provided by core */                  break;
548      case CPUINFO_PTR_INSTRUCTION_COUNTER:           info->icount = &mips->icount;           break;
549
550      /* --- the following bits of info are returned as NULL-terminated strings --- */
551      case CPUINFO_STR_NAME:                          strcpy(info->s, "MIPS III");            break;
552      case CPUINFO_STR_FAMILY:                    strcpy(info->s, "MIPS III");            break;
553      case CPUINFO_STR_VERSION:                   strcpy(info->s, "3.0");                 break;
554      case CPUINFO_STR_SOURCE_FILE:                       /* provided by core */                  break;
555      case CPUINFO_STR_CREDITS:                   strcpy(info->s, "Copyright Aaron Giles"); break;
556
557      case CPUINFO_STR_FLAGS:                         strcpy(info->s, " ");                   break;
558
559      case CPUINFO_STR_REGISTER + MIPS3_PC:           sprintf(info->s, "PC:%08X", mips->pc); break;
560      case CPUINFO_STR_REGISTER + MIPS3_SR:           sprintf(info->s, "SR:%08X", (UINT32)mips->cpr[0][COP0_Status]); break;
561      case CPUINFO_STR_REGISTER + MIPS3_EPC:          sprintf(info->s, "EPC:%08X", (UINT32)mips->cpr[0][COP0_EPC]); break;
562      case CPUINFO_STR_REGISTER + MIPS3_CAUSE:        sprintf(info->s, "Cause:%08X", (UINT32)mips->cpr[0][COP0_Cause]); break;
563      case CPUINFO_STR_REGISTER + MIPS3_COUNT:        sprintf(info->s, "Count:%08X", (UINT32)((mips->device->total_cycles() - mips->count_zero_time) / 2)); break;
564      case CPUINFO_STR_REGISTER + MIPS3_COMPARE:      sprintf(info->s, "Compare:%08X", (UINT32)mips->cpr[0][COP0_Compare]); break;
565      case CPUINFO_STR_REGISTER + MIPS3_INDEX:        sprintf(info->s, "Index:%08X", (UINT32)mips->cpr[0][COP0_Index]); break;
566      case CPUINFO_STR_REGISTER + MIPS3_RANDOM:       sprintf(info->s, "Random:%08X", (UINT32)mips->cpr[0][COP0_Random]); break;
567      case CPUINFO_STR_REGISTER + MIPS3_ENTRYHI:      sprintf(info->s, "EntryHi:%08X%08X", (UINT32)(mips->cpr[0][COP0_EntryHi] >> 32), (UINT32)mips->cpr[0][COP0_EntryHi]); break;
568      case CPUINFO_STR_REGISTER + MIPS3_ENTRYLO0:     sprintf(info->s, "EntryLo0:%08X%08X", (UINT32)(mips->cpr[0][COP0_EntryLo0] >> 32), (UINT32)mips->cpr[0][COP0_EntryLo0]); break;
569      case CPUINFO_STR_REGISTER + MIPS3_ENTRYLO1:     sprintf(info->s, "EntryLo1:%08X%08X", (UINT32)(mips->cpr[0][COP0_EntryLo1] >> 32), (UINT32)mips->cpr[0][COP0_EntryLo1]); break;
570      case CPUINFO_STR_REGISTER + MIPS3_PAGEMASK:     sprintf(info->s, "PageMask:%08X%08X", (UINT32)(mips->cpr[0][COP0_PageMask] >> 32), (UINT32)mips->cpr[0][COP0_PageMask]); break;
571      case CPUINFO_STR_REGISTER + MIPS3_WIRED:        sprintf(info->s, "Wired:%08X", (UINT32)mips->cpr[0][COP0_Wired]); break;
572      case CPUINFO_STR_REGISTER + MIPS3_BADVADDR:     sprintf(info->s, "BadVAddr:%08X", (UINT32)mips->cpr[0][COP0_BadVAddr]); break;
573
574#if USE_ABI_REG_NAMES
575      case CPUINFO_STR_REGISTER + MIPS3_R0:           sprintf(info->s, "zero:%08X%08X", (UINT32)(mips->r[0] >> 32), (UINT32)mips->r[0]); break;
576      case CPUINFO_STR_REGISTER + MIPS3_R1:           sprintf(info->s, "at:%08X%08X", (UINT32)(mips->r[1] >> 32), (UINT32)mips->r[1]); break;
577      case CPUINFO_STR_REGISTER + MIPS3_R2:           sprintf(info->s, "v0:%08X%08X", (UINT32)(mips->r[2] >> 32), (UINT32)mips->r[2]); break;
578      case CPUINFO_STR_REGISTER + MIPS3_R3:           sprintf(info->s, "v1:%08X%08X", (UINT32)(mips->r[3] >> 32), (UINT32)mips->r[3]); break;
579      case CPUINFO_STR_REGISTER + MIPS3_R4:           sprintf(info->s, "a0:%08X%08X", (UINT32)(mips->r[4] >> 32), (UINT32)mips->r[4]); break;
580      case CPUINFO_STR_REGISTER + MIPS3_R5:           sprintf(info->s, "a1:%08X%08X", (UINT32)(mips->r[5] >> 32), (UINT32)mips->r[5]); break;
581      case CPUINFO_STR_REGISTER + MIPS3_R6:           sprintf(info->s, "a2:%08X%08X", (UINT32)(mips->r[6] >> 32), (UINT32)mips->r[6]); break;
582      case CPUINFO_STR_REGISTER + MIPS3_R7:           sprintf(info->s, "a3:%08X%08X", (UINT32)(mips->r[7] >> 32), (UINT32)mips->r[7]); break;
583      case CPUINFO_STR_REGISTER + MIPS3_R8:           sprintf(info->s, "t0:%08X%08X", (UINT32)(mips->r[8] >> 32), (UINT32)mips->r[8]); break;
584      case CPUINFO_STR_REGISTER + MIPS3_R9:           sprintf(info->s, "t1:%08X%08X", (UINT32)(mips->r[9] >> 32), (UINT32)mips->r[9]); break;
585      case CPUINFO_STR_REGISTER + MIPS3_R10:          sprintf(info->s, "t2:%08X%08X", (UINT32)(mips->r[10] >> 32), (UINT32)mips->r[10]); break;
586      case CPUINFO_STR_REGISTER + MIPS3_R11:          sprintf(info->s, "t3:%08X%08X", (UINT32)(mips->r[11] >> 32), (UINT32)mips->r[11]); break;
587      case CPUINFO_STR_REGISTER + MIPS3_R12:          sprintf(info->s, "t4:%08X%08X", (UINT32)(mips->r[12] >> 32), (UINT32)mips->r[12]); break;
588      case CPUINFO_STR_REGISTER + MIPS3_R13:          sprintf(info->s, "t5:%08X%08X", (UINT32)(mips->r[13] >> 32), (UINT32)mips->r[13]); break;
589      case CPUINFO_STR_REGISTER + MIPS3_R14:          sprintf(info->s, "t6:%08X%08X", (UINT32)(mips->r[14] >> 32), (UINT32)mips->r[14]); break;
590      case CPUINFO_STR_REGISTER + MIPS3_R15:          sprintf(info->s, "t7:%08X%08X", (UINT32)(mips->r[15] >> 32), (UINT32)mips->r[15]); break;
591      case CPUINFO_STR_REGISTER + MIPS3_R16:          sprintf(info->s, "s0:%08X%08X", (UINT32)(mips->r[16] >> 32), (UINT32)mips->r[16]); break;
592      case CPUINFO_STR_REGISTER + MIPS3_R17:          sprintf(info->s, "s1:%08X%08X", (UINT32)(mips->r[17] >> 32), (UINT32)mips->r[17]); break;
593      case CPUINFO_STR_REGISTER + MIPS3_R18:          sprintf(info->s, "s2:%08X%08X", (UINT32)(mips->r[18] >> 32), (UINT32)mips->r[18]); break;
594      case CPUINFO_STR_REGISTER + MIPS3_R19:          sprintf(info->s, "s3:%08X%08X", (UINT32)(mips->r[19] >> 32), (UINT32)mips->r[19]); break;
595      case CPUINFO_STR_REGISTER + MIPS3_R20:          sprintf(info->s, "s4:%08X%08X", (UINT32)(mips->r[20] >> 32), (UINT32)mips->r[20]); break;
596      case CPUINFO_STR_REGISTER + MIPS3_R21:          sprintf(info->s, "s5:%08X%08X", (UINT32)(mips->r[21] >> 32), (UINT32)mips->r[21]); break;
597      case CPUINFO_STR_REGISTER + MIPS3_R22:          sprintf(info->s, "s6:%08X%08X", (UINT32)(mips->r[22] >> 32), (UINT32)mips->r[22]); break;
598      case CPUINFO_STR_REGISTER + MIPS3_R23:          sprintf(info->s, "s7:%08X%08X", (UINT32)(mips->r[23] >> 32), (UINT32)mips->r[23]); break;
599      case CPUINFO_STR_REGISTER + MIPS3_R24:          sprintf(info->s, "t8:%08X%08X", (UINT32)(mips->r[24] >> 32), (UINT32)mips->r[24]); break;
600      case CPUINFO_STR_REGISTER + MIPS3_R25:          sprintf(info->s, "t9:%08X%08X", (UINT32)(mips->r[25] >> 32), (UINT32)mips->r[25]); break;
601      case CPUINFO_STR_REGISTER + MIPS3_R26:          sprintf(info->s, "k0:%08X%08X", (UINT32)(mips->r[26] >> 32), (UINT32)mips->r[26]); break;
602      case CPUINFO_STR_REGISTER + MIPS3_R27:          sprintf(info->s, "k1:%08X%08X", (UINT32)(mips->r[27] >> 32), (UINT32)mips->r[27]); break;
603      case CPUINFO_STR_REGISTER + MIPS3_R28:          sprintf(info->s, "gp:%08X%08X", (UINT32)(mips->r[28] >> 32), (UINT32)mips->r[28]); break;
604      case CPUINFO_STR_REGISTER + MIPS3_R29:          sprintf(info->s, "sp:%08X%08X", (UINT32)(mips->r[29] >> 32), (UINT32)mips->r[29]); break;
605      case CPUINFO_STR_REGISTER + MIPS3_R30:          sprintf(info->s, "fp:%08X%08X", (UINT32)(mips->r[30] >> 32), (UINT32)mips->r[30]); break;
606      case CPUINFO_STR_REGISTER + MIPS3_R31:          sprintf(info->s, "ra:%08X%08X", (UINT32)(mips->r[31] >> 32), (UINT32)mips->r[31]); break;
607#else
608      case CPUINFO_STR_REGISTER + MIPS3_R0:           sprintf(info->s, "R0:%08X%08X", (UINT32)(mips->r[0] >> 32), (UINT32)mips->r[0]); break;
609      case CPUINFO_STR_REGISTER + MIPS3_R1:           sprintf(info->s, "R1:%08X%08X", (UINT32)(mips->r[1] >> 32), (UINT32)mips->r[1]); break;
610      case CPUINFO_STR_REGISTER + MIPS3_R2:           sprintf(info->s, "R2:%08X%08X", (UINT32)(mips->r[2] >> 32), (UINT32)mips->r[2]); break;
611      case CPUINFO_STR_REGISTER + MIPS3_R3:           sprintf(info->s, "R3:%08X%08X", (UINT32)(mips->r[3] >> 32), (UINT32)mips->r[3]); break;
612      case CPUINFO_STR_REGISTER + MIPS3_R4:           sprintf(info->s, "R4:%08X%08X", (UINT32)(mips->r[4] >> 32), (UINT32)mips->r[4]); break;
613      case CPUINFO_STR_REGISTER + MIPS3_R5:           sprintf(info->s, "R5:%08X%08X", (UINT32)(mips->r[5] >> 32), (UINT32)mips->r[5]); break;
614      case CPUINFO_STR_REGISTER + MIPS3_R6:           sprintf(info->s, "R6:%08X%08X", (UINT32)(mips->r[6] >> 32), (UINT32)mips->r[6]); break;
615      case CPUINFO_STR_REGISTER + MIPS3_R7:           sprintf(info->s, "R7:%08X%08X", (UINT32)(mips->r[7] >> 32), (UINT32)mips->r[7]); break;
616      case CPUINFO_STR_REGISTER + MIPS3_R8:           sprintf(info->s, "R8:%08X%08X", (UINT32)(mips->r[8] >> 32), (UINT32)mips->r[8]); break;
617      case CPUINFO_STR_REGISTER + MIPS3_R9:           sprintf(info->s, "R9:%08X%08X", (UINT32)(mips->r[9] >> 32), (UINT32)mips->r[9]); break;
618      case CPUINFO_STR_REGISTER + MIPS3_R10:          sprintf(info->s, "R10:%08X%08X", (UINT32)(mips->r[10] >> 32), (UINT32)mips->r[10]); break;
619      case CPUINFO_STR_REGISTER + MIPS3_R11:          sprintf(info->s, "R11:%08X%08X", (UINT32)(mips->r[11] >> 32), (UINT32)mips->r[11]); break;
620      case CPUINFO_STR_REGISTER + MIPS3_R12:          sprintf(info->s, "R12:%08X%08X", (UINT32)(mips->r[12] >> 32), (UINT32)mips->r[12]); break;
621      case CPUINFO_STR_REGISTER + MIPS3_R13:          sprintf(info->s, "R13:%08X%08X", (UINT32)(mips->r[13] >> 32), (UINT32)mips->r[13]); break;
622      case CPUINFO_STR_REGISTER + MIPS3_R14:          sprintf(info->s, "R14:%08X%08X", (UINT32)(mips->r[14] >> 32), (UINT32)mips->r[14]); break;
623      case CPUINFO_STR_REGISTER + MIPS3_R15:          sprintf(info->s, "R15:%08X%08X", (UINT32)(mips->r[15] >> 32), (UINT32)mips->r[15]); break;
624      case CPUINFO_STR_REGISTER + MIPS3_R16:          sprintf(info->s, "R16:%08X%08X", (UINT32)(mips->r[16] >> 32), (UINT32)mips->r[16]); break;
625      case CPUINFO_STR_REGISTER + MIPS3_R17:          sprintf(info->s, "R17:%08X%08X", (UINT32)(mips->r[17] >> 32), (UINT32)mips->r[17]); break;
626      case CPUINFO_STR_REGISTER + MIPS3_R18:          sprintf(info->s, "R18:%08X%08X", (UINT32)(mips->r[18] >> 32), (UINT32)mips->r[18]); break;
627      case CPUINFO_STR_REGISTER + MIPS3_R19:          sprintf(info->s, "R19:%08X%08X", (UINT32)(mips->r[19] >> 32), (UINT32)mips->r[19]); break;
628      case CPUINFO_STR_REGISTER + MIPS3_R20:          sprintf(info->s, "R20:%08X%08X", (UINT32)(mips->r[20] >> 32), (UINT32)mips->r[20]); break;
629      case CPUINFO_STR_REGISTER + MIPS3_R21:          sprintf(info->s, "R21:%08X%08X", (UINT32)(mips->r[21] >> 32), (UINT32)mips->r[21]); break;
630      case CPUINFO_STR_REGISTER + MIPS3_R22:          sprintf(info->s, "R22:%08X%08X", (UINT32)(mips->r[22] >> 32), (UINT32)mips->r[22]); break;
631      case CPUINFO_STR_REGISTER + MIPS3_R23:          sprintf(info->s, "R23:%08X%08X", (UINT32)(mips->r[23] >> 32), (UINT32)mips->r[23]); break;
632      case CPUINFO_STR_REGISTER + MIPS3_R24:          sprintf(info->s, "R24:%08X%08X", (UINT32)(mips->r[24] >> 32), (UINT32)mips->r[24]); break;
633      case CPUINFO_STR_REGISTER + MIPS3_R25:          sprintf(info->s, "R25:%08X%08X", (UINT32)(mips->r[25] >> 32), (UINT32)mips->r[25]); break;
634      case CPUINFO_STR_REGISTER + MIPS3_R26:          sprintf(info->s, "R26:%08X%08X", (UINT32)(mips->r[26] >> 32), (UINT32)mips->r[26]); break;
635      case CPUINFO_STR_REGISTER + MIPS3_R27:          sprintf(info->s, "R27:%08X%08X", (UINT32)(mips->r[27] >> 32), (UINT32)mips->r[27]); break;
636      case CPUINFO_STR_REGISTER + MIPS3_R28:          sprintf(info->s, "R28:%08X%08X", (UINT32)(mips->r[28] >> 32), (UINT32)mips->r[28]); break;
637      case CPUINFO_STR_REGISTER + MIPS3_R29:          sprintf(info->s, "R29:%08X%08X", (UINT32)(mips->r[29] >> 32), (UINT32)mips->r[29]); break;
638      case CPUINFO_STR_REGISTER + MIPS3_R30:          sprintf(info->s, "R30:%08X%08X", (UINT32)(mips->r[30] >> 32), (UINT32)mips->r[30]); break;
639      case CPUINFO_STR_REGISTER + MIPS3_R31:          sprintf(info->s, "R31:%08X%08X", (UINT32)(mips->r[31] >> 32), (UINT32)mips->r[31]); break;
640#endif
641      case CPUINFO_STR_REGISTER + MIPS3_HI:           sprintf(info->s, "HI:%08X%08X", (UINT32)(mips->r[REG_HI] >> 32), (UINT32)mips->r[REG_HI]); break;
642      case CPUINFO_STR_REGISTER + MIPS3_LO:           sprintf(info->s, "LO:%08X%08X", (UINT32)(mips->r[REG_LO] >> 32), (UINT32)mips->r[REG_LO]); break;
643
644      case CPUINFO_STR_REGISTER + MIPS3_CCR1_31:      sprintf(info->s, "CCR31:%08X", (UINT32)mips->ccr[1][31]); break;
645
646      case CPUINFO_STR_REGISTER + MIPS3_FPR0:         sprintf(info->s, "FPR0:%08X%08X", (UINT32)(mips->cpr[1][0] >> 32), (UINT32)mips->cpr[1][0]); break;
647      case CPUINFO_STR_REGISTER + MIPS3_FPS0:         sprintf(info->s, "FPS0:!%16g", *(float *)&mips->cpr[1][0]); break;
648      case CPUINFO_STR_REGISTER + MIPS3_FPD0:         sprintf(info->s, "FPD0:!%16g", *(double *)&mips->cpr[1][0]); break;
649      case CPUINFO_STR_REGISTER + MIPS3_FPR1:         sprintf(info->s, "FPR1:%08X%08X", (UINT32)(mips->cpr[1][1] >> 32), (UINT32)mips->cpr[1][1]); break;
650      case CPUINFO_STR_REGISTER + MIPS3_FPS1:         sprintf(info->s, "FPS1:!%16g", *(float *)&mips->cpr[1][1]); break;
651      case CPUINFO_STR_REGISTER + MIPS3_FPD1:         sprintf(info->s, "FPD1:!%16g", *(double *)&mips->cpr[1][1]); break;
652      case CPUINFO_STR_REGISTER + MIPS3_FPR2:         sprintf(info->s, "FPR2:%08X%08X", (UINT32)(mips->cpr[1][2] >> 32), (UINT32)mips->cpr[1][2]); break;
653      case CPUINFO_STR_REGISTER + MIPS3_FPS2:         sprintf(info->s, "FPS2:!%16g", *(float *)&mips->cpr[1][2]); break;
654      case CPUINFO_STR_REGISTER + MIPS3_FPD2:         sprintf(info->s, "FPD2:!%16g", *(double *)&mips->cpr[1][2]); break;
655      case CPUINFO_STR_REGISTER + MIPS3_FPR3:         sprintf(info->s, "FPR3:%08X%08X", (UINT32)(mips->cpr[1][3] >> 32), (UINT32)mips->cpr[1][3]); break;
656      case CPUINFO_STR_REGISTER + MIPS3_FPS3:         sprintf(info->s, "FPS3:!%16g", *(float *)&mips->cpr[1][3]); break;
657      case CPUINFO_STR_REGISTER + MIPS3_FPD3:         sprintf(info->s, "FPD3:!%16g", *(double *)&mips->cpr[1][3]); break;
658      case CPUINFO_STR_REGISTER + MIPS3_FPR4:         sprintf(info->s, "FPR4:%08X%08X", (UINT32)(mips->cpr[1][4] >> 32), (UINT32)mips->cpr[1][4]); break;
659      case CPUINFO_STR_REGISTER + MIPS3_FPS4:         sprintf(info->s, "FPS4:!%16g", *(float *)&mips->cpr[1][4]); break;
660      case CPUINFO_STR_REGISTER + MIPS3_FPD4:         sprintf(info->s, "FPD4:!%16g", *(double *)&mips->cpr[1][4]); break;
661      case CPUINFO_STR_REGISTER + MIPS3_FPR5:         sprintf(info->s, "FPR5:%08X%08X", (UINT32)(mips->cpr[1][5] >> 32), (UINT32)mips->cpr[1][5]); break;
662      case CPUINFO_STR_REGISTER + MIPS3_FPS5:         sprintf(info->s, "FPS5:!%16g", *(float *)&mips->cpr[1][5]); break;
663      case CPUINFO_STR_REGISTER + MIPS3_FPD5:         sprintf(info->s, "FPD5:!%16g", *(double *)&mips->cpr[1][5]); break;
664      case CPUINFO_STR_REGISTER + MIPS3_FPR6:         sprintf(info->s, "FPR6:%08X%08X", (UINT32)(mips->cpr[1][6] >> 32), (UINT32)mips->cpr[1][6]); break;
665      case CPUINFO_STR_REGISTER + MIPS3_FPS6:         sprintf(info->s, "FPS6:!%16g", *(float *)&mips->cpr[1][6]); break;
666      case CPUINFO_STR_REGISTER + MIPS3_FPD6:         sprintf(info->s, "FPD6:!%16g", *(double *)&mips->cpr[1][6]); break;
667      case CPUINFO_STR_REGISTER + MIPS3_FPR7:         sprintf(info->s, "FPR7:%08X%08X", (UINT32)(mips->cpr[1][7] >> 32), (UINT32)mips->cpr[1][7]); break;
668      case CPUINFO_STR_REGISTER + MIPS3_FPS7:         sprintf(info->s, "FPS7:!%16g", *(float *)&mips->cpr[1][7]); break;
669      case CPUINFO_STR_REGISTER + MIPS3_FPD7:         sprintf(info->s, "FPD7:!%16g", *(double *)&mips->cpr[1][7]); break;
670      case CPUINFO_STR_REGISTER + MIPS3_FPR8:         sprintf(info->s, "FPR8:%08X%08X", (UINT32)(mips->cpr[1][8] >> 32), (UINT32)mips->cpr[1][8]); break;
671      case CPUINFO_STR_REGISTER + MIPS3_FPS8:         sprintf(info->s, "FPS8:!%16g", *(float *)&mips->cpr[1][8]); break;
672      case CPUINFO_STR_REGISTER + MIPS3_FPD8:         sprintf(info->s, "FPD8:!%16g", *(double *)&mips->cpr[1][8]); break;
673      case CPUINFO_STR_REGISTER + MIPS3_FPR9:         sprintf(info->s, "FPR9:%08X%08X", (UINT32)(mips->cpr[1][9] >> 32), (UINT32)mips->cpr[1][9]); break;
674      case CPUINFO_STR_REGISTER + MIPS3_FPS9:         sprintf(info->s, "FPS9:!%16g", *(float *)&mips->cpr[1][9]); break;
675      case CPUINFO_STR_REGISTER + MIPS3_FPD9:         sprintf(info->s, "FPD9:!%16g", *(double *)&mips->cpr[1][9]); break;
676      case CPUINFO_STR_REGISTER + MIPS3_FPR10:        sprintf(info->s, "FPR10:%08X%08X", (UINT32)(mips->cpr[1][10] >> 32), (UINT32)mips->cpr[1][10]); break;
677      case CPUINFO_STR_REGISTER + MIPS3_FPS10:        sprintf(info->s, "FPS10:!%16g", *(float *)&mips->cpr[1][10]); break;
678      case CPUINFO_STR_REGISTER + MIPS3_FPD10:        sprintf(info->s, "FPD10:!%16g", *(double *)&mips->cpr[1][10]); break;
679      case CPUINFO_STR_REGISTER + MIPS3_FPR11:        sprintf(info->s, "FPR11:%08X%08X", (UINT32)(mips->cpr[1][11] >> 32), (UINT32)mips->cpr[1][11]); break;
680      case CPUINFO_STR_REGISTER + MIPS3_FPS11:        sprintf(info->s, "FPS11:!%16g", *(float *)&mips->cpr[1][11]); break;
681      case CPUINFO_STR_REGISTER + MIPS3_FPD11:        sprintf(info->s, "FPD11:!%16g", *(double *)&mips->cpr[1][11]); break;
682      case CPUINFO_STR_REGISTER + MIPS3_FPR12:        sprintf(info->s, "FPR12:%08X%08X", (UINT32)(mips->cpr[1][12] >> 32), (UINT32)mips->cpr[1][12]); break;
683      case CPUINFO_STR_REGISTER + MIPS3_FPS12:        sprintf(info->s, "FPS12:!%16g", *(float *)&mips->cpr[1][12]); break;
684      case CPUINFO_STR_REGISTER + MIPS3_FPD12:        sprintf(info->s, "FPD12:!%16g", *(double *)&mips->cpr[1][12]); break;
685      case CPUINFO_STR_REGISTER + MIPS3_FPR13:        sprintf(info->s, "FPR13:%08X%08X", (UINT32)(mips->cpr[1][13] >> 32), (UINT32)mips->cpr[1][13]); break;
686      case CPUINFO_STR_REGISTER + MIPS3_FPS13:        sprintf(info->s, "FPS13:!%16g", *(float *)&mips->cpr[1][13]); break;
687      case CPUINFO_STR_REGISTER + MIPS3_FPD13:        sprintf(info->s, "FPD13:!%16g", *(double *)&mips->cpr[1][13]); break;
688      case CPUINFO_STR_REGISTER + MIPS3_FPR14:        sprintf(info->s, "FPR14:%08X%08X", (UINT32)(mips->cpr[1][14] >> 32), (UINT32)mips->cpr[1][14]); break;
689      case CPUINFO_STR_REGISTER + MIPS3_FPS14:        sprintf(info->s, "FPS14:!%16g", *(float *)&mips->cpr[1][14]); break;
690      case CPUINFO_STR_REGISTER + MIPS3_FPD14:        sprintf(info->s, "FPD14:!%16g", *(double *)&mips->cpr[1][14]); break;
691      case CPUINFO_STR_REGISTER + MIPS3_FPR15:        sprintf(info->s, "FPR15:%08X%08X", (UINT32)(mips->cpr[1][15] >> 32), (UINT32)mips->cpr[1][15]); break;
692      case CPUINFO_STR_REGISTER + MIPS3_FPS15:        sprintf(info->s, "FPS15:!%16g", *(float *)&mips->cpr[1][15]); break;
693      case CPUINFO_STR_REGISTER + MIPS3_FPD15:        sprintf(info->s, "FPD15:!%16g", *(double *)&mips->cpr[1][15]); break;
694      case CPUINFO_STR_REGISTER + MIPS3_FPR16:        sprintf(info->s, "FPR16:%08X%08X", (UINT32)(mips->cpr[1][16] >> 32), (UINT32)mips->cpr[1][16]); break;
695      case CPUINFO_STR_REGISTER + MIPS3_FPS16:        sprintf(info->s, "FPS16:!%16g", *(float *)&mips->cpr[1][16]); break;
696      case CPUINFO_STR_REGISTER + MIPS3_FPD16:        sprintf(info->s, "FPD16:!%16g", *(double *)&mips->cpr[1][16]); break;
697      case CPUINFO_STR_REGISTER + MIPS3_FPR17:        sprintf(info->s, "FPR17:%08X%08X", (UINT32)(mips->cpr[1][17] >> 32), (UINT32)mips->cpr[1][17]); break;
698      case CPUINFO_STR_REGISTER + MIPS3_FPS17:        sprintf(info->s, "FPS17:!%16g", *(float *)&mips->cpr[1][17]); break;
699      case CPUINFO_STR_REGISTER + MIPS3_FPD17:        sprintf(info->s, "FPD17:!%16g", *(double *)&mips->cpr[1][17]); break;
700      case CPUINFO_STR_REGISTER + MIPS3_FPR18:        sprintf(info->s, "FPR18:%08X%08X", (UINT32)(mips->cpr[1][18] >> 32), (UINT32)mips->cpr[1][18]); break;
701      case CPUINFO_STR_REGISTER + MIPS3_FPS18:        sprintf(info->s, "FPS18:!%16g", *(float *)&mips->cpr[1][18]); break;
702      case CPUINFO_STR_REGISTER + MIPS3_FPD18:        sprintf(info->s, "FPD18:!%16g", *(double *)&mips->cpr[1][18]); break;
703      case CPUINFO_STR_REGISTER + MIPS3_FPR19:        sprintf(info->s, "FPR19:%08X%08X", (UINT32)(mips->cpr[1][19] >> 32), (UINT32)mips->cpr[1][19]); break;
704      case CPUINFO_STR_REGISTER + MIPS3_FPS19:        sprintf(info->s, "FPS19:!%16g", *(float *)&mips->cpr[1][19]); break;
705      case CPUINFO_STR_REGISTER + MIPS3_FPD19:        sprintf(info->s, "FPD19:!%16g", *(double *)&mips->cpr[1][19]); break;
706      case CPUINFO_STR_REGISTER + MIPS3_FPR20:        sprintf(info->s, "FPR20:%08X%08X", (UINT32)(mips->cpr[1][20] >> 32), (UINT32)mips->cpr[1][20]); break;
707      case CPUINFO_STR_REGISTER + MIPS3_FPS20:        sprintf(info->s, "FPS20:!%16g", *(float *)&mips->cpr[1][20]); break;
708      case CPUINFO_STR_REGISTER + MIPS3_FPD20:        sprintf(info->s, "FPD20:!%16g", *(double *)&mips->cpr[1][20]); break;
709      case CPUINFO_STR_REGISTER + MIPS3_FPR21:        sprintf(info->s, "FPR21:%08X%08X", (UINT32)(mips->cpr[1][21] >> 32), (UINT32)mips->cpr[1][21]); break;
710      case CPUINFO_STR_REGISTER + MIPS3_FPS21:        sprintf(info->s, "FPS21:!%16g", *(float *)&mips->cpr[1][21]); break;
711      case CPUINFO_STR_REGISTER + MIPS3_FPD21:        sprintf(info->s, "FPD21:!%16g", *(double *)&mips->cpr[1][21]); break;
712      case CPUINFO_STR_REGISTER + MIPS3_FPR22:        sprintf(info->s, "FPR22:%08X%08X", (UINT32)(mips->cpr[1][22] >> 32), (UINT32)mips->cpr[1][22]); break;
713      case CPUINFO_STR_REGISTER + MIPS3_FPS22:        sprintf(info->s, "FPS22:!%16g", *(float *)&mips->cpr[1][22]); break;
714      case CPUINFO_STR_REGISTER + MIPS3_FPD22:        sprintf(info->s, "FPD22:!%16g", *(double *)&mips->cpr[1][22]); break;
715      case CPUINFO_STR_REGISTER + MIPS3_FPR23:        sprintf(info->s, "FPR23:%08X%08X", (UINT32)(mips->cpr[1][23] >> 32), (UINT32)mips->cpr[1][23]); break;
716      case CPUINFO_STR_REGISTER + MIPS3_FPS23:        sprintf(info->s, "FPS23:!%16g", *(float *)&mips->cpr[1][23]); break;
717      case CPUINFO_STR_REGISTER + MIPS3_FPD23:        sprintf(info->s, "FPD23:!%16g", *(double *)&mips->cpr[1][23]); break;
718      case CPUINFO_STR_REGISTER + MIPS3_FPR24:        sprintf(info->s, "FPR24:%08X%08X", (UINT32)(mips->cpr[1][24] >> 32), (UINT32)mips->cpr[1][24]); break;
719      case CPUINFO_STR_REGISTER + MIPS3_FPS24:        sprintf(info->s, "FPS24:!%16g", *(float *)&mips->cpr[1][24]); break;
720      case CPUINFO_STR_REGISTER + MIPS3_FPD24:        sprintf(info->s, "FPD24:!%16g", *(double *)&mips->cpr[1][24]); break;
721      case CPUINFO_STR_REGISTER + MIPS3_FPR25:        sprintf(info->s, "FPR25:%08X%08X", (UINT32)(mips->cpr[1][25] >> 32), (UINT32)mips->cpr[1][25]); break;
722      case CPUINFO_STR_REGISTER + MIPS3_FPS25:        sprintf(info->s, "FPS25:!%16g", *(float *)&mips->cpr[1][25]); break;
723      case CPUINFO_STR_REGISTER + MIPS3_FPD25:        sprintf(info->s, "FPD25:!%16g", *(double *)&mips->cpr[1][25]); break;
724      case CPUINFO_STR_REGISTER + MIPS3_FPR26:        sprintf(info->s, "FPR26:%08X%08X", (UINT32)(mips->cpr[1][26] >> 32), (UINT32)mips->cpr[1][26]); break;
725      case CPUINFO_STR_REGISTER + MIPS3_FPS26:        sprintf(info->s, "FPS26:!%16g", *(float *)&mips->cpr[1][26]); break;
726      case CPUINFO_STR_REGISTER + MIPS3_FPD26:        sprintf(info->s, "FPD26:!%16g", *(double *)&mips->cpr[1][26]); break;
727      case CPUINFO_STR_REGISTER + MIPS3_FPR27:        sprintf(info->s, "FPR27:%08X%08X", (UINT32)(mips->cpr[1][27] >> 32), (UINT32)mips->cpr[1][27]); break;
728      case CPUINFO_STR_REGISTER + MIPS3_FPS27:        sprintf(info->s, "FPS27:!%16g", *(float *)&mips->cpr[1][27]); break;
729      case CPUINFO_STR_REGISTER + MIPS3_FPD27:        sprintf(info->s, "FPD27:!%16g", *(double *)&mips->cpr[1][27]); break;
730      case CPUINFO_STR_REGISTER + MIPS3_FPR28:        sprintf(info->s, "FPR28:%08X%08X", (UINT32)(mips->cpr[1][28] >> 32), (UINT32)mips->cpr[1][28]); break;
731      case CPUINFO_STR_REGISTER + MIPS3_FPS28:        sprintf(info->s, "FPS28:!%16g", *(float *)&mips->cpr[1][28]); break;
732      case CPUINFO_STR_REGISTER + MIPS3_FPD28:        sprintf(info->s, "FPD28:!%16g", *(double *)&mips->cpr[1][28]); break;
733      case CPUINFO_STR_REGISTER + MIPS3_FPR29:        sprintf(info->s, "FPR29:%08X%08X", (UINT32)(mips->cpr[1][29] >> 32), (UINT32)mips->cpr[1][29]); break;
734      case CPUINFO_STR_REGISTER + MIPS3_FPS29:        sprintf(info->s, "FPS29:!%16g", *(float *)&mips->cpr[1][29]); break;
735      case CPUINFO_STR_REGISTER + MIPS3_FPD29:        sprintf(info->s, "FPD29:!%16g", *(double *)&mips->cpr[1][29]); break;
736      case CPUINFO_STR_REGISTER + MIPS3_FPR30:        sprintf(info->s, "FPR30:%08X%08X", (UINT32)(mips->cpr[1][30] >> 32), (UINT32)mips->cpr[1][30]); break;
737      case CPUINFO_STR_REGISTER + MIPS3_FPS30:        sprintf(info->s, "FPS30:!%16g", *(float *)&mips->cpr[1][30]); break;
738      case CPUINFO_STR_REGISTER + MIPS3_FPD30:        sprintf(info->s, "FPD30:!%16g", *(double *)&mips->cpr[1][30]); break;
739      case CPUINFO_STR_REGISTER + MIPS3_FPR31:        sprintf(info->s, "FPR31:%08X%08X", (UINT32)(mips->cpr[1][31] >> 32), (UINT32)mips->cpr[1][31]); break;
740      case CPUINFO_STR_REGISTER + MIPS3_FPS31:        sprintf(info->s, "FPS31:!%16g", *(float *)&mips->cpr[1][31]); break;
741      case CPUINFO_STR_REGISTER + MIPS3_FPD31:        sprintf(info->s, "FPD31:!%16g", *(double *)&mips->cpr[1][31]); break;
742   }
743}
744
745
746/***************************************************************************
747192    INTERNAL HELPERS
748193***************************************************************************/
749194
r30757r30758
752197    whenever a compare interrupt is generated
753198-------------------------------------------------*/
754199
755static TIMER_CALLBACK( compare_int_callback )
200TIMER_CALLBACK_MEMBER( mips3_device::compare_int_callback )
756201{
757   legacy_cpu_device *device = (legacy_cpu_device *)ptr;
758   device->set_input_line(MIPS3_IRQ5, ASSERT_LINE);
202   set_input_line(MIPS3_IRQ5, ASSERT_LINE);
759203}
760204
761205
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764208    of the config register
765209-------------------------------------------------*/
766210
767static UINT32 compute_config_register(const mips3_state *mips)
211UINT32 mips3_device::compute_config_register()
768212{
769213   /* set the cache line size to 32 bytes */
770214   UINT32 configreg = 0x00026030;
771215   int divisor;
772216
773217   // NEC VR series does not use a 100% compatible COP0/TLB implementation
774   if (mips->flavor == MIPS3_TYPE_VR4300)
218   if (m_flavor == MIPS3_TYPE_VR4300)
775219   {
776220      /*
777221          For VR43xx, Config is as follows:
r30757r30758
790234   else
791235   {
792236      /* set the data cache size */
793            if (mips->icache_size <= 0x01000) configreg |= 0 << 6;
794      else if (mips->icache_size <= 0x02000) configreg |= 1 << 6;
795      else if (mips->icache_size <= 0x04000) configreg |= 2 << 6;
796      else if (mips->icache_size <= 0x08000) configreg |= 3 << 6;
797      else if (mips->icache_size <= 0x10000) configreg |= 4 << 6;
798      else if (mips->icache_size <= 0x20000) configreg |= 5 << 6;
799      else if (mips->icache_size <= 0x40000) configreg |= 6 << 6;
237            if (c_icache_size <= 0x01000) configreg |= 0 << 6;
238      else if (c_icache_size <= 0x02000) configreg |= 1 << 6;
239      else if (c_icache_size <= 0x04000) configreg |= 2 << 6;
240      else if (c_icache_size <= 0x08000) configreg |= 3 << 6;
241      else if (c_icache_size <= 0x10000) configreg |= 4 << 6;
242      else if (c_icache_size <= 0x20000) configreg |= 5 << 6;
243      else if (c_icache_size <= 0x40000) configreg |= 6 << 6;
800244      else                                   configreg |= 7 << 6;
801245
802246      /* set the instruction cache size */
803            if (mips->icache_size <= 0x01000) configreg |= 0 << 9;
804      else if (mips->icache_size <= 0x02000) configreg |= 1 << 9;
805      else if (mips->icache_size <= 0x04000) configreg |= 2 << 9;
806      else if (mips->icache_size <= 0x08000) configreg |= 3 << 9;
807      else if (mips->icache_size <= 0x10000) configreg |= 4 << 9;
808      else if (mips->icache_size <= 0x20000) configreg |= 5 << 9;
809      else if (mips->icache_size <= 0x40000) configreg |= 6 << 9;
247            if (c_icache_size <= 0x01000) configreg |= 0 << 9;
248      else if (c_icache_size <= 0x02000) configreg |= 1 << 9;
249      else if (c_icache_size <= 0x04000) configreg |= 2 << 9;
250      else if (c_icache_size <= 0x08000) configreg |= 3 << 9;
251      else if (c_icache_size <= 0x10000) configreg |= 4 << 9;
252      else if (c_icache_size <= 0x20000) configreg |= 5 << 9;
253      else if (c_icache_size <= 0x40000) configreg |= 6 << 9;
810254      else                                   configreg |= 7 << 9;
811255
812256
813257      /* set the system clock divider */
814258      divisor = 2;
815      if (mips->system_clock != 0)
259      if (c_system_clock != 0)
816260      {
817         divisor = mips->cpu_clock / mips->system_clock;
818         if (mips->system_clock * divisor != mips->cpu_clock)
261         divisor = m_cpu_clock / c_system_clock;
262         if (c_system_clock * divisor != m_cpu_clock)
819263         {
820264            configreg |= 0x80000000;
821            divisor = mips->cpu_clock * 2 / mips->system_clock;
265            divisor = m_cpu_clock * 2 / c_system_clock;
822266         }
823267      }
824268      configreg |= (((divisor < 2) ? 2 : (divisor > 8) ? 8 : divisor) - 2) << 28;
825269   }
826270
827271   /* set the endianness bit */
828   if (mips->bigendian)
272   if (m_bigendian)
829273      configreg |= 0x00008000;
830274
831275   return configreg;
r30757r30758
837281    of the PRId register
838282-------------------------------------------------*/
839283
840static UINT32 compute_prid_register(const mips3_state *mips)
284UINT32 mips3_device::compute_prid_register()
841285{
842   switch (mips->flavor)
286   switch (m_flavor)
843287   {
844288      case MIPS3_TYPE_VR4300:
845289         return 0x0b00;
r30757r30758
870314    entry
871315-------------------------------------------------*/
872316
873static void tlb_map_entry(mips3_state *mips, int tlbindex)
317void mips3_device::tlb_map_entry(int tlbindex)
874318{
875   int current_asid = mips->cpr[0][COP0_EntryHi] & 0xff;
876   mips3_tlb_entry *entry = &mips->tlb[tlbindex];
319   int current_asid = m_core->cpr[0][COP0_EntryHi] & 0xff;
320   mips3_tlb_entry *entry = &m_tlb[tlbindex];
877321   UINT32 count, vpn;
878322   int which;
879323
880324   /* the ASID doesn't match the current ASID, and if the page isn't global, unmap it from the TLB */
881325   if (!tlb_entry_matches_asid(entry, current_asid) && !tlb_entry_is_global(entry))
882326   {
883      vtlb_load(mips->vtlb, 2 * tlbindex + 0, 0, 0, 0);
884      vtlb_load(mips->vtlb, 2 * tlbindex + 1, 0, 0, 0);
327      vtlb_load(m_vtlb, 2 * tlbindex + 0, 0, 0, 0);
328      vtlb_load(m_vtlb, 2 * tlbindex + 1, 0, 0, 0);
885329      return;
886330   }
887331
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889333   vpn = ((entry->entry_hi >> 13) & 0x07ffffff) << 1;
890334   if (vpn >= (1 << (MIPS3_MAX_PADDR_SHIFT - MIPS3_MIN_PAGE_SHIFT)))
891335   {
892      vtlb_load(mips->vtlb, 2 * tlbindex + 0, 0, 0, 0);
893      vtlb_load(mips->vtlb, 2 * tlbindex + 1, 0, 0, 0);
336      vtlb_load(m_vtlb, 2 * tlbindex + 0, 0, 0, 0);
337      vtlb_load(m_vtlb, 2 * tlbindex + 1, 0, 0, 0);
894338      return;
895339   }
896340
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906350      UINT32 flags = 0;
907351
908352      /* compute physical page index */
909      pfn = (lo >> 6) & mips->pfnmask;
353      pfn = (lo >> 6) & m_pfnmask;
910354
911355      /* valid? */
912356      if ((lo & 2) != 0)
r30757r30758
924368
925369      /* load the virtual TLB with the corresponding entries */
926370      if ((effvpn + count) <= (0x80000000 >> MIPS3_MIN_PAGE_SHIFT) || effvpn >= (0xc0000000 >> MIPS3_MIN_PAGE_SHIFT))
927         vtlb_load(mips->vtlb, 2 * tlbindex + which, count, effvpn << MIPS3_MIN_PAGE_SHIFT, (pfn << MIPS3_MIN_PAGE_SHIFT) | flags);
371         vtlb_load(m_vtlb, 2 * tlbindex + which, count, effvpn << MIPS3_MIN_PAGE_SHIFT, (pfn << MIPS3_MIN_PAGE_SHIFT) | flags);
928372      else
929         vtlb_load(mips->vtlb, 2 * tlbindex + which, 0, 0, 0);
373         vtlb_load(m_vtlb, 2 * tlbindex + which, 0, 0, 0);
930374   }
931375}
932376
r30757r30758
936380    a TLB entry
937381-------------------------------------------------*/
938382
939static void tlb_write_common(mips3_state *mips, int tlbindex)
383void mips3_device::tlb_write_common(int tlbindex)
940384{
941385   /* only handle entries within the TLB */
942   if (tlbindex < mips->tlbentries)
386   if (tlbindex < m_tlbentries)
943387   {
944      mips3_tlb_entry *entry = &mips->tlb[tlbindex];
388      mips3_tlb_entry *entry = &m_tlb[tlbindex];
945389
946390      /* fill in the new TLB entry from the COP0 registers */
947      entry->page_mask = mips->cpr[0][COP0_PageMask];
948      entry->entry_hi = mips->cpr[0][COP0_EntryHi] & ~(entry->page_mask & U64(0x0000000001ffe000));
949      entry->entry_lo[0] = mips->cpr[0][COP0_EntryLo0];
950      entry->entry_lo[1] = mips->cpr[0][COP0_EntryLo1];
391      entry->page_mask = m_core->cpr[0][COP0_PageMask];
392      entry->entry_hi = m_core->cpr[0][COP0_EntryHi] & ~(entry->page_mask & U64(0x0000000001ffe000));
393      entry->entry_lo[0] = m_core->cpr[0][COP0_EntryLo0];
394      entry->entry_lo[1] = m_core->cpr[0][COP0_EntryLo1];
951395
952396      /* remap this TLB entry */
953      tlb_map_entry(mips, tlbindex);
397      tlb_map_entry(tlbindex);
954398
955399      /* log the two halves once they are in */
956400      tlb_entry_log_half(entry, tlbindex, 0);
trunk/src/emu/cpu/mips/mips3.c
r30757r30758
2323    HELPER MACROS
2424***************************************************************************/
2525
26#define RSVAL32     ((UINT32)mips3.core.r[RSREG])
27#define RTVAL32     ((UINT32)mips3.core.r[RTREG])
28#define RDVAL32     ((UINT32)mips3.core.r[RDREG])
26#define RSVAL32     ((UINT32)m_core->r[RSREG])
27#define RTVAL32     ((UINT32)m_core->r[RTREG])
28#define RDVAL32     ((UINT32)m_core->r[RDREG])
2929
30#define RSVAL64     (mips3.core.r[RSREG])
31#define RTVAL64     (mips3.core.r[RTREG])
32#define RDVAL64     (mips3.core.r[RDREG])
30#define RSVAL64     (m_core->r[RSREG])
31#define RTVAL64     (m_core->r[RTREG])
32#define RDVAL64     (m_core->r[RDREG])
3333
34#define FRVALS_FR0  (((float *)&mips3.core.cpr[1][0])[FRREG])
35#define FTVALS_FR0  (((float *)&mips3.core.cpr[1][0])[FTREG])
36#define FSVALS_FR0  (((float *)&mips3.core.cpr[1][0])[FSREG])
37#define FDVALS_FR0  (((float *)&mips3.core.cpr[1][0])[FDREG])
38#define FSVALW_FR0  (((UINT32 *)&mips3.core.cpr[1][0])[FSREG])
39#define FDVALW_FR0  (((UINT32 *)&mips3.core.cpr[1][0])[FDREG])
34#define FRVALS_FR0  (((float *)&m_core->cpr[1][0])[FRREG])
35#define FTVALS_FR0  (((float *)&m_core->cpr[1][0])[FTREG])
36#define FSVALS_FR0  (((float *)&m_core->cpr[1][0])[FSREG])
37#define FDVALS_FR0  (((float *)&m_core->cpr[1][0])[FDREG])
38#define FSVALW_FR0  (((UINT32 *)&m_core->cpr[1][0])[FSREG])
39#define FDVALW_FR0  (((UINT32 *)&m_core->cpr[1][0])[FDREG])
4040
41#define FRVALD_FR0  (*(double *)&mips3.core.cpr[1][FRREG/2])
42#define FTVALD_FR0  (*(double *)&mips3.core.cpr[1][FTREG/2])
43#define FSVALD_FR0  (*(double *)&mips3.core.cpr[1][FSREG/2])
44#define FDVALD_FR0  (*(double *)&mips3.core.cpr[1][FDREG/2])
45#define FSVALL_FR0  (((UINT64 *)&mips3.core.cpr[1][0])[FSREG/2])
46#define FDVALL_FR0  (((UINT64 *)&mips3.core.cpr[1][0])[FDREG/2])
41#define FRVALD_FR0  (*(double *)&m_core->cpr[1][FRREG/2])
42#define FTVALD_FR0  (*(double *)&m_core->cpr[1][FTREG/2])
43#define FSVALD_FR0  (*(double *)&m_core->cpr[1][FSREG/2])
44#define FDVALD_FR0  (*(double *)&m_core->cpr[1][FDREG/2])
45#define FSVALL_FR0  (((UINT64 *)&m_core->cpr[1][0])[FSREG/2])
46#define FDVALL_FR0  (((UINT64 *)&m_core->cpr[1][0])[FDREG/2])
4747
48#define FRVALS_FR1  (((float *)&mips3.core.cpr[1][FRREG])[BYTE_XOR_LE(0)])
49#define FTVALS_FR1  (((float *)&mips3.core.cpr[1][FTREG])[BYTE_XOR_LE(0)])
50#define FSVALS_FR1  (((float *)&mips3.core.cpr[1][FSREG])[BYTE_XOR_LE(0)])
51#define FDVALS_FR1  (((float *)&mips3.core.cpr[1][FDREG])[BYTE_XOR_LE(0)])
52#define FSVALW_FR1  (((UINT32 *)&mips3.core.cpr[1][FSREG])[BYTE_XOR_LE(0)])
53#define FDVALW_FR1  (((UINT32 *)&mips3.core.cpr[1][FDREG])[BYTE_XOR_LE(0)])
48#define FRVALS_FR1  (((float *)&m_core->cpr[1][FRREG])[BYTE_XOR_LE(0)])
49#define FTVALS_FR1  (((float *)&m_core->cpr[1][FTREG])[BYTE_XOR_LE(0)])
50#define FSVALS_FR1  (((float *)&m_core->cpr[1][FSREG])[BYTE_XOR_LE(0)])
51#define FDVALS_FR1  (((float *)&m_core->cpr[1][FDREG])[BYTE_XOR_LE(0)])
52#define FSVALW_FR1  (((UINT32 *)&m_core->cpr[1][FSREG])[BYTE_XOR_LE(0)])
53#define FDVALW_FR1  (((UINT32 *)&m_core->cpr[1][FDREG])[BYTE_XOR_LE(0)])
5454
55#define FRVALD_FR1  (*(double *)&mips3.core.cpr[1][FRREG])
56#define FTVALD_FR1  (*(double *)&mips3.core.cpr[1][FTREG])
57#define FSVALD_FR1  (*(double *)&mips3.core.cpr[1][FSREG])
58#define FDVALD_FR1  (*(double *)&mips3.core.cpr[1][FDREG])
59#define FSVALL_FR1  (*(UINT64 *)&mips3.core.cpr[1][FSREG])
60#define FDVALL_FR1  (*(UINT64 *)&mips3.core.cpr[1][FDREG])
55#define FRVALD_FR1  (*(double *)&m_core->cpr[1][FRREG])
56#define FTVALD_FR1  (*(double *)&m_core->cpr[1][FTREG])
57#define FSVALD_FR1  (*(double *)&m_core->cpr[1][FSREG])
58#define FDVALD_FR1  (*(double *)&m_core->cpr[1][FDREG])
59#define FSVALL_FR1  (*(UINT64 *)&m_core->cpr[1][FSREG])
60#define FDVALL_FR1  (*(UINT64 *)&m_core->cpr[1][FDREG])
6161
62#define ADDPC(x)    mips3.nextpc = mips3.core.pc + ((x) << 2)
63#define ADDPCL(x,l) { mips3.nextpc = mips3.core.pc + ((x) << 2); mips3.core.r[l] = (INT32)(mips3.core.pc + 4); }
64#define ABSPC(x)    mips3.nextpc = (mips3.core.pc & 0xf0000000) | ((x) << 2)
65#define ABSPCL(x,l) { mips3.nextpc = (mips3.core.pc & 0xf0000000) | ((x) << 2); mips3.core.r[l] = (INT32)(mips3.core.pc + 4); }
66#define SETPC(x)    mips3.nextpc = (x)
67#define SETPCL(x,l) { mips3.nextpc = (x); mips3.core.r[l] = (INT32)(mips3.core.pc + 4); }
62#define ADDPC(x)    m_nextpc = m_core->pc + ((x) << 2)
63#define ADDPCL(x,l) { m_nextpc = m_core->pc + ((x) << 2); m_core->r[l] = (INT32)(m_core->pc + 4); }
64#define ABSPC(x)    m_nextpc = (m_core->pc & 0xf0000000) | ((x) << 2)
65#define ABSPCL(x,l) { m_nextpc = (m_core->pc & 0xf0000000) | ((x) << 2); m_core->r[l] = (INT32)(m_core->pc + 4); }
66#define SETPC(x)    m_nextpc = (x)
67#define SETPCL(x,l) { m_nextpc = (x); m_core->r[l] = (INT32)(m_core->pc + 4); }
6868
69#define HIVAL       (UINT32)mips3.core.r[REG_HI]
70#define LOVAL       (UINT32)mips3.core.r[REG_LO]
71#define HIVAL64     mips3.core.r[REG_HI]
72#define LOVAL64     mips3.core.r[REG_LO]
73#define SR          mips3.core.cpr[0][COP0_Status]
74#define CAUSE       mips3.core.cpr[0][COP0_Cause]
69#define HIVAL       (UINT32)m_core->r[REG_HI]
70#define LOVAL       (UINT32)m_core->r[REG_LO]
71#define HIVAL64     m_core->r[REG_HI]
72#define LOVAL64     m_core->r[REG_LO]
73#define SR          m_core->cpr[0][COP0_Status]
74#define CAUSE       m_core->cpr[0][COP0_Cause]
7575
76#define GET_FCC(n)  (mips3.cf[1][n])
77#define SET_FCC(n,v) (mips3.cf[1][n] = (v))
76#define GET_FCC(n)  (m_cf[1][n])
77#define SET_FCC(n,v) (m_cf[1][n] = (v))
7878
7979#define IS_FR0      (!(SR & SR_FR))
8080#define IS_FR1      (SR & SR_FR)
8181
82/* size of the execution code cache */
83#define CACHE_SIZE                      (32 * 1024 * 1024)
8284
8385
84/***************************************************************************
85    STRUCTURES & TYPEDEFS
86***************************************************************************/
8786
88/* MIPS3 Registers */
89struct mips3_regs
87static const UINT8 fcc_shift[8] = { 23, 25, 26, 27, 28, 29, 30, 31 };
88
89/* lookup table for FP modes */
90static const UINT8 fpmode_source[4] =
9091{
91   /* core state */
92   mips3_state core;
93
94   /* internal stuff */
95   UINT32      ppc;
96   UINT32      nextpc;
97   UINT32      pcbase;
98   UINT8       cf[4][8];
99   int         op;
100   int         interrupt_cycles;
101   UINT32      ll_value;
102   UINT64      lld_value;
103   UINT32      badcop_value;
104   const vtlb_entry *tlb_table;
105
106   /* endian-dependent load/store */
107   void        (*lwl)(UINT32 op);
108   void        (*lwr)(UINT32 op);
109   void        (*swl)(UINT32 op);
110   void        (*swr)(UINT32 op);
111   void        (*ldl)(UINT32 op);
112   void        (*ldr)(UINT32 op);
113   void        (*sdl)(UINT32 op);
114   void        (*sdr)(UINT32 op);
92   uml::ROUND_ROUND,
93   uml::ROUND_TRUNC,
94   uml::ROUND_CEIL,
95   uml::ROUND_FLOOR
11596};
11697
11798
11899
119100/***************************************************************************
120    FUNCTION PROTOTYPES
101    MEMORY ACCESSORS
121102***************************************************************************/
122103
123static void lwl_be(UINT32 op);
124static void lwr_be(UINT32 op);
125static void swl_be(UINT32 op);
126static void swr_be(UINT32 op);
104#define ROPCODE(pc)     direct->read_decrypted_dword(pc)
127105
128static void lwl_le(UINT32 op);
129static void lwr_le(UINT32 op);
130static void swl_le(UINT32 op);
131static void swr_le(UINT32 op);
132106
133static void ldl_be(UINT32 op);
134static void ldr_be(UINT32 op);
135static void sdl_be(UINT32 op);
136static void sdr_be(UINT32 op);
107const device_type VR4300BE = &device_creator<vr4300be_device>;
108const device_type VR4300LE = &device_creator<vr4300le_device>;
109const device_type VR4310BE = &device_creator<vr4310be_device>;
110const device_type VR4310LE = &device_creator<vr4310le_device>;
111const device_type R4600BE = &device_creator<r4600be_device>;
112const device_type R4600LE = &device_creator<r4600le_device>;
113const device_type R4650BE = &device_creator<r4650be_device>;
114const device_type R4650LE = &device_creator<r4650le_device>;
115const device_type R4700BE = &device_creator<r4700be_device>;
116const device_type R4700LE = &device_creator<r4700le_device>;
117const device_type R5000BE = &device_creator<r5000be_device>;
118const device_type R5000LE = &device_creator<r5000le_device>;
119const device_type QED5271BE = &device_creator<qed5271be_device>;
120const device_type QED5271LE = &device_creator<qed5271le_device>;
121const device_type RM7000BE = &device_creator<rm7000be_device>;
122const device_type RM7000LE = &device_creator<rm7000le_device>;
137123
138static void ldl_le(UINT32 op);
139static void ldr_le(UINT32 op);
140static void sdl_le(UINT32 op);
141static void sdr_le(UINT32 op);
142124
143static const UINT8 fcc_shift[8] = { 23, 25, 26, 27, 28, 29, 30, 31 };
125mips3_device::mips3_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, mips3_flavor flavor, endianness_t endianness)
126   : cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__)
127   , m_program_config("program", endianness, 32, 32, 0, 32, MIPS3_MIN_PAGE_SHIFT)
128   , m_flavor(flavor)
129   , m_core(NULL)
130   , m_ppc(0)
131   , m_nextpc(0)
132   , m_pcbase(0)
133   , m_op(0)
134   , m_interrupt_cycles(0)
135   , m_ll_value(0)
136   , m_lld_value(0)
137   , m_badcop_value(0)
138   , m_tlb_table(NULL)
139   , m_lwl(endianness == ENDIANNESS_BIG ? &mips3_device::lwl_be : &mips3_device::lwl_le)
140   , m_lwr(endianness == ENDIANNESS_BIG ? &mips3_device::lwr_be : &mips3_device::lwr_le)
141   , m_swl(endianness == ENDIANNESS_BIG ? &mips3_device::swl_be : &mips3_device::swl_le)
142   , m_swr(endianness == ENDIANNESS_BIG ? &mips3_device::swr_be : &mips3_device::swr_le)
143   , m_ldl(endianness == ENDIANNESS_BIG ? &mips3_device::ldl_be : &mips3_device::ldl_le)
144   , m_ldr(endianness == ENDIANNESS_BIG ? &mips3_device::ldr_be : &mips3_device::ldr_le)
145   , m_sdl(endianness == ENDIANNESS_BIG ? &mips3_device::sdl_be : &mips3_device::sdl_le)
146   , m_sdr(endianness == ENDIANNESS_BIG ? &mips3_device::sdr_be : &mips3_device::sdr_le)
147   , c_system_clock(0)
148   , m_pfnmask(0)
149   , m_tlbentries(0)
150   , m_bigendian(endianness == ENDIANNESS_BIG)
151   , c_icache_size(0)
152   , c_dcache_size(0)
153   , m_vtlb(NULL)
154   , m_debugger_temp(0)
155   , m_cache(CACHE_SIZE + sizeof(internal_mips3_state))
156   , m_drcuml(NULL)
157   , m_drcfe(NULL)
158   , m_drcoptions(0)
159   , m_cache_dirty(0)
160   , m_entry(NULL)
161   , m_nocode(NULL)
162   , m_out_of_cycles(NULL)
163   , m_tlb_mismatch(NULL)
164   , m_fastram_select(0)
165   , m_hotspot_select(0)
166{
167   memset(m_fpmode, 0, sizeof(m_fpmode));
144168
169   for (int i = 0; i < 3; i++)
170   {
171      m_read8[i] = NULL;
172      m_write8[i] = NULL;
173      m_read16[i] = NULL;
174      m_write16[i] = NULL;
175      m_read32[i] = NULL;
176      m_read32mask[i] = NULL;
177      m_write32[i] = NULL;
178      m_write32mask[i] = NULL;
179      m_read64[i] = NULL;
180      m_read64mask[i] = NULL;
181      m_write64[i] = NULL;
182      m_write64mask[i] = NULL;
183   }
145184
185   for (int i = 0; i < 18; i++)
186   {
187      m_exception[i] = NULL;
188      m_exception_norecover[i] = NULL;
189   }
190   memset(m_fastram, 0, sizeof(m_fastram));
191   memset(m_hotspot, 0, sizeof(m_hotspot));
146192
147/***************************************************************************
148    PRIVATE GLOBAL VARIABLES
149***************************************************************************/
193   m_isdrc = mconfig.options().drc() ? true : false;
194}
150195
151static mips3_regs mips3;
152196
197void mips3_device::device_stop()
198{
199   if (m_vtlb != NULL)
200   {
201      vtlb_free(m_vtlb);
202      m_vtlb = NULL;
203   }
153204
205   if (m_drcfe != NULL)
206   {
207      auto_free(machine(), m_drcfe);
208      m_drcfe = NULL;
209   }
210   if (m_drcuml != NULL)
211   {
212      auto_free(machine(), m_drcuml);
213      m_drcuml = NULL;
214   }
215}
154216
155217/***************************************************************************
156    MEMORY ACCESSORS
157***************************************************************************/
158
159#define ROPCODE(pc)     mips3.core.direct->read_decrypted_dword(pc)
160
161
162/***************************************************************************
163218    EXECEPTION HANDLING
164219***************************************************************************/
165220
166INLINE void generate_exception(int exception, int backup)
221void mips3_device::generate_exception(int exception, int backup)
167222{
168223   UINT32 offset = 0x180;
169224/*
r30757r30758
171226
172227    if (exception != 0)
173228    {
174        fprintf(stderr, "Exception: PC=%08X, PPC=%08X\n", mips3.core.pc, mips3.ppc);
175        debugger_break(Machine);
229        fprintf(stderr, "Exception: PC=%08X, PPC=%08X\n", m_core->pc, m_ppc);
230        debugger_break(machine());
176231    }
177232*/
178233
179234   /* back up if necessary */
180235   if (backup)
181      mips3.core.pc = mips3.ppc;
236      m_core->pc = m_ppc;
182237
183238   /* translate our fake fill exceptions into real exceptions */
184239   if (exception == EXCEPTION_TLBLOAD_FILL || exception == EXCEPTION_TLBSTORE_FILL)
r30757r30758
188243   }
189244
190245   /* set the exception PC */
191   mips3.core.cpr[0][COP0_EPC] = mips3.core.pc;
246   m_core->cpr[0][COP0_EPC] = m_core->pc;
192247
193248   /* put the cause in the low 8 bits and clear the branch delay flag */
194249   CAUSE = (CAUSE & ~0x800000ff) | (exception << 2);
r30757r30758
196251   /* set the appropriate bits for coprocessor exceptions */
197252   if(exception == EXCEPTION_BADCOP)
198253   {
199      CAUSE |= mips3.badcop_value << 28;
254      CAUSE |= m_badcop_value << 28;
200255   }
201256
202257   /* if we were in a branch delay slot, adjust */
203   if (mips3.nextpc != ~0)
258   if (m_nextpc != ~0)
204259   {
205      mips3.nextpc = ~0;
206      mips3.core.cpr[0][COP0_EPC] -= 4;
260      m_nextpc = ~0;
261      m_core->cpr[0][COP0_EPC] -= 4;
207262      CAUSE |= 0x80000000;
208263   }
209264
r30757r30758
211266   SR |= SR_EXL;
212267
213268   /* based on the BEV bit, we either go to ROM or RAM */
214   mips3.core.pc = (SR & SR_BEV) ? 0xbfc00200 : 0x80000000;
269   m_core->pc = (SR & SR_BEV) ? 0xbfc00200 : 0x80000000;
215270
216271   /* most exceptions go to offset 0x180, except for TLB stuff */
217272   if (exception >= EXCEPTION_TLBMOD && exception <= EXCEPTION_TLBSTORE)
218273   {
219      osd_printf_debug("TLB miss @ %08X\n", (UINT32)mips3.core.cpr[0][COP0_BadVAddr]);
274      osd_printf_debug("TLB miss @ %08X\n", (UINT32)m_core->cpr[0][COP0_BadVAddr]);
220275   }
221   mips3.core.pc += offset;
276   m_core->pc += offset;
222277
223278/*
224279    useful for tracking interrupts
225280
226281    if ((CAUSE & 0x7f) == 0)
227        logerror("Took interrupt -- Cause = %08X, PC =  %08X\n", (UINT32)CAUSE, mips3.core.pc);
282        logerror("Took interrupt -- Cause = %08X, PC =  %08X\n", (UINT32)CAUSE, m_core->pc);
228283*/
229284}
230285
231286
232static void generate_tlb_exception(int exception, offs_t address)
287void mips3_device::generate_tlb_exception(int exception, offs_t address)
233288{
234   mips3.core.cpr[0][COP0_BadVAddr] = address;
289   m_core->cpr[0][COP0_BadVAddr] = address;
235290   if(exception == EXCEPTION_TLBLOAD || exception == EXCEPTION_TLBSTORE || exception == EXCEPTION_TLBLOAD_FILL || exception == EXCEPTION_TLBSTORE_FILL)
236291   {
237      mips3.core.cpr[0][COP0_Context] = (mips3.core.cpr[0][COP0_Context] & 0xff800000) | ((address >> 9) & 0x007ffff0);
238      mips3.core.cpr[0][COP0_EntryHi] = (address & 0xffffe000) | (mips3.core.cpr[0][COP0_EntryHi] & 0xff);
292      m_core->cpr[0][COP0_Context] = (m_core->cpr[0][COP0_Context] & 0xff800000) | ((address >> 9) & 0x007ffff0);
293      m_core->cpr[0][COP0_EntryHi] = (address & 0xffffe000) | (m_core->cpr[0][COP0_EntryHi] & 0xff);
239294   }
240295   generate_exception(exception, 1);
241296}
242297
243298
244INLINE void invalid_instruction(UINT32 op)
299void mips3_device::invalid_instruction(UINT32 op)
245300{
246301   generate_exception(EXCEPTION_INVALIDOP, 1);
247302}
r30757r30758
252307    IRQ HANDLING
253308***************************************************************************/
254309
255static void check_irqs(void)
310void mips3_device::check_irqs()
256311{
257312   if ((CAUSE & SR & 0xfc00) && (SR & SR_IE) && !(SR & SR_EXL) && !(SR & SR_ERL))
258313      generate_exception(EXCEPTION_INTERRUPT, 0);
r30757r30758
264319    CORE CALLBACKS
265320***************************************************************************/
266321
267static CPU_RESET( mips3 )
322void mips3_device::device_start()
268323{
269   /* common reset */
270   mips3com_reset(&mips3.core);
271   mips3.nextpc = ~0;
272   memset(mips3.cf, 0, sizeof(mips3.cf));
324   /* allocate the implementation-specific state from the full cache */
325   m_core = (internal_mips3_state *)m_cache.alloc_near(sizeof(internal_mips3_state));
273326
327   /* initialize based on the config */
328   memset(m_core, 0, sizeof(internal_mips3_state));
329
330   m_cpu_clock = clock();
331   m_program = &space(AS_PROGRAM);
332   m_direct = &m_program->direct();
333
334   /* configure flavor-specific parameters */
335   m_pfnmask = 0x00ffffff;
336   m_tlbentries = MIPS3_MAX_TLB_ENTRIES;
337
338   /* VR4300 and VR5432 have 4 fewer PFN bits, and only 32 TLB entries */
339   if (m_flavor == MIPS3_TYPE_VR4300)
340   {
341      m_pfnmask = 0x000fffff;
342      m_tlbentries = 32;
343   }
344
274345   /* set up the endianness */
275   if (mips3.core.bigendian)
346   m_program->accessors(m_memory);
347
348   /* allocate the virtual TLB */
349   m_vtlb = vtlb_alloc(this, AS_PROGRAM, 2 * m_tlbentries + 2, 0);
350
351   /* allocate a timer for the compare interrupt */
352   m_compare_int_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(mips3_device::compare_int_callback), this));
353
354   m_tlb_table = vtlb_table(m_vtlb);
355
356   UINT32 flags = 0;
357   /* initialize the UML generator */
358   if (LOG_UML)
359      flags |= DRCUML_OPTION_LOG_UML;
360   if (LOG_NATIVE)
361      flags |= DRCUML_OPTION_LOG_NATIVE;
362   m_drcuml = auto_alloc(machine(), drcuml_state(*this, m_cache, flags, 8, 32, 2));
363
364   /* add symbols for our stuff */
365   m_drcuml->symbol_add(&m_core->pc, sizeof(m_core->pc), "pc");
366   m_drcuml->symbol_add(&m_core->icount, sizeof(m_core->icount), "icount");
367   for (int regnum = 0; regnum < 32; regnum++)
276368   {
277      mips3.lwl = lwl_be;
278      mips3.lwr = lwr_be;
279      mips3.swl = swl_be;
280      mips3.swr = swr_be;
281      mips3.ldl = ldl_be;
282      mips3.ldr = ldr_be;
283      mips3.sdl = sdl_be;
284      mips3.sdr = sdr_be;
369      char buf[10];
370      sprintf(buf, "r%d", regnum);
371      m_drcuml->symbol_add(&m_core->r[regnum], sizeof(m_core->r[regnum]), buf);
372      sprintf(buf, "f%d", regnum);
373      m_drcuml->symbol_add(&m_core->cpr[1][regnum], sizeof(m_core->cpr[1][regnum]), buf);
285374   }
286   else
375   m_drcuml->symbol_add(&m_core->r[REG_LO], sizeof(m_core->r[REG_LO]), "lo");
376   m_drcuml->symbol_add(&m_core->r[REG_HI], sizeof(m_core->r[REG_LO]), "hi");
377   m_drcuml->symbol_add(&m_core->cpr[0][COP0_Index], sizeof(m_core->cpr[0][COP0_Index]), "Index");
378   m_drcuml->symbol_add(&m_core->cpr[0][COP0_Random], sizeof(m_core->cpr[0][COP0_Random]), "Random");
379   m_drcuml->symbol_add(&m_core->cpr[0][COP0_EntryLo0], sizeof(m_core->cpr[0][COP0_EntryLo0]), "EntryLo0");
380   m_drcuml->symbol_add(&m_core->cpr[0][COP0_EntryLo1], sizeof(m_core->cpr[0][COP0_EntryLo1]), "EntryLo1");
381   m_drcuml->symbol_add(&m_core->cpr[0][COP0_Context], sizeof(m_core->cpr[0][COP0_Context]), "Context");
382   m_drcuml->symbol_add(&m_core->cpr[0][COP0_PageMask], sizeof(m_core->cpr[0][COP0_PageMask]), "PageMask");
383   m_drcuml->symbol_add(&m_core->cpr[0][COP0_Wired], sizeof(m_core->cpr[0][COP0_Wired]), "Wired");
384   m_drcuml->symbol_add(&m_core->cpr[0][COP0_BadVAddr], sizeof(m_core->cpr[0][COP0_BadVAddr]), "BadVAddr");
385   m_drcuml->symbol_add(&m_core->cpr[0][COP0_Count], sizeof(m_core->cpr[0][COP0_Count]), "Count");
386   m_drcuml->symbol_add(&m_core->cpr[0][COP0_EntryHi], sizeof(m_core->cpr[0][COP0_EntryHi]), "EntryHi");
387   m_drcuml->symbol_add(&m_core->cpr[0][COP0_Compare], sizeof(m_core->cpr[0][COP0_Compare]), "Compare");
388   m_drcuml->symbol_add(&m_core->cpr[0][COP0_Status], sizeof(m_core->cpr[0][COP0_Status]), "Status");
389   m_drcuml->symbol_add(&m_core->cpr[0][COP0_Cause], sizeof(m_core->cpr[0][COP0_Cause]), "Cause");
390   m_drcuml->symbol_add(&m_core->cpr[0][COP0_EPC], sizeof(m_core->cpr[0][COP0_EPC]), "EPC");
391   m_drcuml->symbol_add(&m_core->cpr[0][COP0_PRId], sizeof(m_core->cpr[0][COP0_PRId]), "PRId");
392   m_drcuml->symbol_add(&m_core->cpr[0][COP0_Config], sizeof(m_core->cpr[0][COP0_Config]), "Config");
393   m_drcuml->symbol_add(&m_core->cpr[0][COP0_LLAddr], sizeof(m_core->cpr[0][COP0_LLAddr]), "LLAddr");
394   m_drcuml->symbol_add(&m_core->cpr[0][COP0_XContext], sizeof(m_core->cpr[0][COP0_XContext]), "XContext");
395   m_drcuml->symbol_add(&m_core->cpr[0][COP0_ECC], sizeof(m_core->cpr[0][COP0_ECC]), "ECC");
396   m_drcuml->symbol_add(&m_core->cpr[0][COP0_CacheErr], sizeof(m_core->cpr[0][COP0_CacheErr]), "CacheErr");
397   m_drcuml->symbol_add(&m_core->cpr[0][COP0_TagLo], sizeof(m_core->cpr[0][COP0_TagLo]), "TagLo");
398   m_drcuml->symbol_add(&m_core->cpr[0][COP0_TagHi], sizeof(m_core->cpr[0][COP0_TagHi]), "TagHi");
399   m_drcuml->symbol_add(&m_core->cpr[0][COP0_ErrorPC], sizeof(m_core->cpr[0][COP0_ErrorPC]), "ErrorPC");
400   m_drcuml->symbol_add(&m_core->ccr[1][31], sizeof(m_core->cpr[1][31]), "fcr31");
401   m_drcuml->symbol_add(&m_core->mode, sizeof(m_core->mode), "mode");
402   m_drcuml->symbol_add(&m_core->arg0, sizeof(m_core->arg0), "arg0");
403   m_drcuml->symbol_add(&m_core->arg1, sizeof(m_core->arg1), "arg1");
404   m_drcuml->symbol_add(&m_core->numcycles, sizeof(m_core->numcycles), "numcycles");
405   m_drcuml->symbol_add(&m_fpmode, sizeof(m_fpmode), "fpmode");
406
407   /* initialize the front-end helper */
408   m_drcfe = auto_alloc(machine(), mips3_frontend(this, COMPILE_BACKWARDS_BYTES, COMPILE_FORWARDS_BYTES, SINGLE_INSTRUCTION_MODE ? 1 : COMPILE_MAX_SEQUENCE));
409
410   /* allocate memory for cache-local state and initialize it */
411   memcpy(m_fpmode, fpmode_source, sizeof(fpmode_source));
412
413   /* compute the register parameters */
414   for (int regnum = 0; regnum < 34; regnum++)
287415   {
288      mips3.lwl = lwl_le;
289      mips3.lwr = lwr_le;
290      mips3.swl = swl_le;
291      mips3.swr = swr_le;
292      mips3.ldl = ldl_le;
293      mips3.ldr = ldr_le;
294      mips3.sdl = sdl_le;
295      mips3.sdr = sdr_le;
416      m_regmap[regnum] = (regnum == 0) ? uml::parameter(0) : uml::parameter::make_memory(&m_core->r[regnum]);
417      m_regmaplo[regnum] = (regnum == 0) ? uml::parameter(0) : uml::parameter::make_memory(LOPTR(&m_core->r[regnum]));
296418   }
419
420   /* if we have registers to spare, assign r2, r3, r4 to leftovers */
421   if (!DISABLE_FAST_REGISTERS)
422   {
423      drcbe_info beinfo;
424
425      m_drcuml->get_backend_info(beinfo);
426      if (beinfo.direct_iregs > 4)
427      {
428         m_regmap[2] = uml::I4;
429         m_regmaplo[2] = uml::I4;
430      }
431      if (beinfo.direct_iregs > 5)
432      {
433         m_regmap[3] = uml::I5;
434         m_regmaplo[3] = uml::I5;
435      }
436      if (beinfo.direct_iregs > 6)
437      {
438         m_regmap[4] = uml::I6;
439         m_regmaplo[4] = uml::I6;
440      }
441   }
442
443   /* mark the cache dirty so it is updated on next execute */
444   m_cache_dirty = TRUE;
445
446
447   /* register for save states */
448   save_item(NAME(m_core->pc));
449   save_item(NAME(m_core->r));
450   save_item(NAME(m_core->cpr));
451   save_item(NAME(m_core->ccr));
452   save_item(NAME(m_core->llbit));
453   save_item(NAME(m_core->count_zero_time));
454   for (int tlbindex = 0; tlbindex < m_tlbentries; tlbindex++)
455   {
456      save_item(NAME(m_tlb[tlbindex].page_mask), tlbindex);
457      save_item(NAME(m_tlb[tlbindex].entry_hi), tlbindex);
458      save_item(NAME(m_tlb[tlbindex].entry_lo), tlbindex);
459   }
460
461   // Register state with debugger
462   state_add( MIPS3_PC,           "PC", m_core->pc).formatstr("%08X");
463
464#if USE_ABI_REG_NAMES
465   state_add( MIPS3_R0,           "zero", m_core->r[0]).callimport().formatstr("%016X");   // Can't change R0
466   state_add( MIPS3_R1,           "at", m_core->r[1]).formatstr("%016X");
467   state_add( MIPS3_R2,           "v0", m_core->r[2]).formatstr("%016X");
468   state_add( MIPS3_R3,           "v1", m_core->r[3]).formatstr("%016X");
469   state_add( MIPS3_R4,           "a0", m_core->r[4]).formatstr("%016X");
470   state_add( MIPS3_R5,           "a1", m_core->r[5]).formatstr("%016X");
471   state_add( MIPS3_R6,           "a2", m_core->r[6]).formatstr("%016X");
472   state_add( MIPS3_R7,           "a3", m_core->r[7]).formatstr("%016X");
473   state_add( MIPS3_R8,           "t0", m_core->r[8]).formatstr("%016X");
474   state_add( MIPS3_R9,           "t1", m_core->r[9]).formatstr("%016X");
475   state_add( MIPS3_R10,          "t2", m_core->r[10]).formatstr("%016X");
476   state_add( MIPS3_R11,          "t3", m_core->r[11]).formatstr("%016X");
477   state_add( MIPS3_R12,          "t4", m_core->r[12]).formatstr("%016X");
478   state_add( MIPS3_R13,          "t5", m_core->r[13]).formatstr("%016X");
479   state_add( MIPS3_R14,          "t6", m_core->r[14]).formatstr("%016X");
480   state_add( MIPS3_R15,          "t7", m_core->r[15]).formatstr("%016X");
481   state_add( MIPS3_R16,          "s0", m_core->r[16]).formatstr("%016X");
482   state_add( MIPS3_R17,          "s1", m_core->r[17]).formatstr("%016X");
483   state_add( MIPS3_R18,          "s2", m_core->r[18]).formatstr("%016X");
484   state_add( MIPS3_R19,          "s3", m_core->r[19]).formatstr("%016X");
485   state_add( MIPS3_R20,          "s4", m_core->r[20]).formatstr("%016X");
486   state_add( MIPS3_R21,          "s5", m_core->r[21]).formatstr("%016X");
487   state_add( MIPS3_R22,          "s6", m_core->r[22]).formatstr("%016X");
488   state_add( MIPS3_R23,          "s7", m_core->r[23]).formatstr("%016X");
489   state_add( MIPS3_R24,          "t8", m_core->r[24]).formatstr("%016X");
490   state_add( MIPS3_R25,          "t9", m_core->r[25]).formatstr("%016X");
491   state_add( MIPS3_R26,          "k0", m_core->r[26]).formatstr("%016X");
492   state_add( MIPS3_R27,          "k1", m_core->r[27]).formatstr("%016X");
493   state_add( MIPS3_R28,          "gp", m_core->r[28]).formatstr("%016X");
494   state_add( MIPS3_R29,          "sp", m_core->r[29]).formatstr("%016X");
495   state_add( MIPS3_R30,          "fp", m_core->r[30]).formatstr("%016X");
496   state_add( MIPS3_R31,          "ra", m_core->r[31]).formatstr("%016X");
497#else
498   state_add( MIPS3_R0,           "R0", m_core->r[0]).callimport().formatstr("%016X");   // Can't change R0
499   state_add( MIPS3_R1,           "R1", m_core->r[1]).formatstr("%016X");
500   state_add( MIPS3_R2,           "R2", m_core->r[2]).formatstr("%016X");
501   state_add( MIPS3_R3,           "R3", m_core->r[3]).formatstr("%016X");
502   state_add( MIPS3_R4,           "R4", m_core->r[4]).formatstr("%016X");
503   state_add( MIPS3_R5,           "R5", m_core->r[5]).formatstr("%016X");
504   state_add( MIPS3_R6,           "R6", m_core->r[6]).formatstr("%016X");
505   state_add( MIPS3_R7,           "R7", m_core->r[7]).formatstr("%016X");
506   state_add( MIPS3_R8,           "R8", m_core->r[8]).formatstr("%016X");
507   state_add( MIPS3_R9,           "R9", m_core->r[9]).formatstr("%016X");
508   state_add( MIPS3_R10,          "R10", m_core->r[10]).formatstr("%016X");
509   state_add( MIPS3_R11,          "R11", m_core->r[11]).formatstr("%016X");
510   state_add( MIPS3_R12,          "R12", m_core->r[12]).formatstr("%016X");
511   state_add( MIPS3_R13,          "R13", m_core->r[13]).formatstr("%016X");
512   state_add( MIPS3_R14,          "R14", m_core->r[14]).formatstr("%016X");
513   state_add( MIPS3_R15,          "R15", m_core->r[15]).formatstr("%016X");
514   state_add( MIPS3_R16,          "R16", m_core->r[16]).formatstr("%016X");
515   state_add( MIPS3_R17,          "R17", m_core->r[17]).formatstr("%016X");
516   state_add( MIPS3_R18,          "R18", m_core->r[18]).formatstr("%016X");
517   state_add( MIPS3_R19,          "R19", m_core->r[19]).formatstr("%016X");
518   state_add( MIPS3_R20,          "R20", m_core->r[20]).formatstr("%016X");
519   state_add( MIPS3_R21,          "R21", m_core->r[21]).formatstr("%016X");
520   state_add( MIPS3_R22,          "R22", m_core->r[22]).formatstr("%016X");
521   state_add( MIPS3_R23,          "R23", m_core->r[23]).formatstr("%016X");
522   state_add( MIPS3_R24,          "R24", m_core->r[24]).formatstr("%016X");
523   state_add( MIPS3_R25,          "R25", m_core->r[25]).formatstr("%016X");
524   state_add( MIPS3_R26,          "R26", m_core->r[26]).formatstr("%016X");
525   state_add( MIPS3_R27,          "R27", m_core->r[27]).formatstr("%016X");
526   state_add( MIPS3_R28,          "R28", m_core->r[28]).formatstr("%016X");
527   state_add( MIPS3_R29,          "R29", m_core->r[29]).formatstr("%016X");
528   state_add( MIPS3_R30,          "R30", m_core->r[30]).formatstr("%016X");
529   state_add( MIPS3_R31,          "R31", m_core->r[31]).formatstr("%016X");
530#endif
531   state_add( MIPS3_HI,           "HI", m_core->r[REG_HI]).formatstr("%016X");
532   state_add( MIPS3_LO,           "LO", m_core->r[REG_LO]).formatstr("%016X");
533
534   state_add( MIPS3_CCR1_31,      "CCR31", m_core->ccr[1][31]).formatstr("%08X");
535
536   state_add( MIPS3_FPR0,         "FPR0", m_core->cpr[1][0]).formatstr("%016X");
537   state_add( MIPS3_FPS0,         "FPS0", m_core->cpr[1][0]).formatstr("%17s");
538   state_add( MIPS3_FPD0,         "FPD0", m_core->cpr[1][0]).formatstr("%17s");
539   state_add( MIPS3_FPR1,         "FPR1", m_core->cpr[1][1]).formatstr("%016X");
540   state_add( MIPS3_FPS1,         "FPS1", m_core->cpr[1][1]).formatstr("%17s");
541   state_add( MIPS3_FPD1,         "FPD1", m_core->cpr[1][1]).formatstr("%17s");
542   state_add( MIPS3_FPR2,         "FPR2", m_core->cpr[1][2]).formatstr("%016X");
543   state_add( MIPS3_FPS2,         "FPS2", m_core->cpr[1][2]).formatstr("%17s");
544   state_add( MIPS3_FPD2,         "FPD2", m_core->cpr[1][2]).formatstr("%17s");
545   state_add( MIPS3_FPR3,         "FPR3", m_core->cpr[1][3]).formatstr("%016X");
546   state_add( MIPS3_FPS3,         "FPS3", m_core->cpr[1][3]).formatstr("%17s");
547   state_add( MIPS3_FPD3,         "FPD3", m_core->cpr[1][3]).formatstr("%17s");
548   state_add( MIPS3_FPR4,         "FPR4", m_core->cpr[1][4]).formatstr("%016X");
549   state_add( MIPS3_FPS4,         "FPS4", m_core->cpr[1][4]).formatstr("%17s");
550   state_add( MIPS3_FPD4,         "FPD4", m_core->cpr[1][4]).formatstr("%17s");
551   state_add( MIPS3_FPR5,         "FPR5", m_core->cpr[1][5]).formatstr("%016X");
552   state_add( MIPS3_FPS5,         "FPS5", m_core->cpr[1][5]).formatstr("%17s");
553   state_add( MIPS3_FPD5,         "FPD5", m_core->cpr[1][5]).formatstr("%17s");
554   state_add( MIPS3_FPR6,         "FPR6", m_core->cpr[1][6]).formatstr("%016X");
555   state_add( MIPS3_FPS6,         "FPS6", m_core->cpr[1][6]).formatstr("%17s");
556   state_add( MIPS3_FPD6,         "FPD6", m_core->cpr[1][6]).formatstr("%17s");
557   state_add( MIPS3_FPR7,         "FPR7", m_core->cpr[1][7]).formatstr("%016X");
558   state_add( MIPS3_FPS7,         "FPS7", m_core->cpr[1][7]).formatstr("%17s");
559   state_add( MIPS3_FPD7,         "FPD7", m_core->cpr[1][7]).formatstr("%17s");
560   state_add( MIPS3_FPR8,         "FPR8", m_core->cpr[1][8]).formatstr("%016X");
561   state_add( MIPS3_FPS8,         "FPS8", m_core->cpr[1][8]).formatstr("%17s");
562   state_add( MIPS3_FPD8,         "FPD8", m_core->cpr[1][8]).formatstr("%17s");
563   state_add( MIPS3_FPR9,         "FPR9", m_core->cpr[1][9]).formatstr("%016X");
564   state_add( MIPS3_FPS9,         "FPS9", m_core->cpr[1][9]).formatstr("%17s");
565   state_add( MIPS3_FPD9,         "FPD9", m_core->cpr[1][9]).formatstr("%17s");
566   state_add( MIPS3_FPR10,        "FPR10", m_core->cpr[1][10]).formatstr("%016X");
567   state_add( MIPS3_FPS10,        "FPS10", m_core->cpr[1][10]).formatstr("%17s");
568   state_add( MIPS3_FPD10,        "FPD10", m_core->cpr[1][10]).formatstr("%17s");
569   state_add( MIPS3_FPR11,        "FPR11", m_core->cpr[1][11]).formatstr("%016X");
570   state_add( MIPS3_FPS11,        "FPS11", m_core->cpr[1][11]).formatstr("%17s");
571   state_add( MIPS3_FPD11,        "FPD11", m_core->cpr[1][11]).formatstr("%17s");
572   state_add( MIPS3_FPR12,        "FPR12", m_core->cpr[1][12]).formatstr("%016X");
573   state_add( MIPS3_FPS12,        "FPS12", m_core->cpr[1][12]).formatstr("%17s");
574   state_add( MIPS3_FPD12,        "FPD12", m_core->cpr[1][12]).formatstr("%17s");
575   state_add( MIPS3_FPR13,        "FPR13", m_core->cpr[1][13]).formatstr("%016X");
576   state_add( MIPS3_FPS13,        "FPS13", m_core->cpr[1][13]).formatstr("%17s");
577   state_add( MIPS3_FPD13,        "FPD13", m_core->cpr[1][13]).formatstr("%17s");
578   state_add( MIPS3_FPR14,        "FPR14", m_core->cpr[1][14]).formatstr("%016X");
579   state_add( MIPS3_FPS14,        "FPS14", m_core->cpr[1][14]).formatstr("%17s");
580   state_add( MIPS3_FPD14,        "FPD14", m_core->cpr[1][14]).formatstr("%17s");
581   state_add( MIPS3_FPR15,        "FPR15", m_core->cpr[1][15]).formatstr("%016X");
582   state_add( MIPS3_FPS15,        "FPS15", m_core->cpr[1][15]).formatstr("%17s");
583   state_add( MIPS3_FPD15,        "FPD15", m_core->cpr[1][15]).formatstr("%17s");
584   state_add( MIPS3_FPR16,        "FPR16", m_core->cpr[1][16]).formatstr("%016X");
585   state_add( MIPS3_FPS16,        "FPS16", m_core->cpr[1][16]).formatstr("%17s");
586   state_add( MIPS3_FPD16,        "FPD16", m_core->cpr[1][16]).formatstr("%17s");
587   state_add( MIPS3_FPR17,        "FPR17", m_core->cpr[1][17]).formatstr("%016X");
588   state_add( MIPS3_FPS17,        "FPS17", m_core->cpr[1][17]).formatstr("%17s");
589   state_add( MIPS3_FPD17,        "FPD17", m_core->cpr[1][17]).formatstr("%17s");
590   state_add( MIPS3_FPR18,        "FPR18", m_core->cpr[1][18]).formatstr("%016X");
591   state_add( MIPS3_FPS18,        "FPS18", m_core->cpr[1][18]).formatstr("%17s");
592   state_add( MIPS3_FPD18,        "FPD18", m_core->cpr[1][18]).formatstr("%17s");
593   state_add( MIPS3_FPR19,        "FPR19", m_core->cpr[1][19]).formatstr("%016X");
594   state_add( MIPS3_FPS19,        "FPS19", m_core->cpr[1][19]).formatstr("%17s");
595   state_add( MIPS3_FPD19,        "FPD19", m_core->cpr[1][19]).formatstr("%17s");
596   state_add( MIPS3_FPR20,        "FPR20", m_core->cpr[1][20]).formatstr("%016X");
597   state_add( MIPS3_FPS20,        "FPS20", m_core->cpr[1][20]).formatstr("%17s");
598   state_add( MIPS3_FPD20,        "FPD20", m_core->cpr[1][20]).formatstr("%17s");
599   state_add( MIPS3_FPR21,        "FPR21", m_core->cpr[1][21]).formatstr("%016X");
600   state_add( MIPS3_FPS21,        "FPS21", m_core->cpr[1][21]).formatstr("%17s");
601   state_add( MIPS3_FPD21,        "FPD21", m_core->cpr[1][21]).formatstr("%17s");
602   state_add( MIPS3_FPR22,        "FPR22", m_core->cpr[1][22]).formatstr("%016X");
603   state_add( MIPS3_FPS22,        "FPS22", m_core->cpr[1][22]).formatstr("%17s");
604   state_add( MIPS3_FPD22,        "FPD22", m_core->cpr[1][22]).formatstr("%17s");
605   state_add( MIPS3_FPR23,        "FPR23", m_core->cpr[1][23]).formatstr("%016X");
606   state_add( MIPS3_FPS23,        "FPS23", m_core->cpr[1][23]).formatstr("%17s");
607   state_add( MIPS3_FPD23,        "FPD23", m_core->cpr[1][23]).formatstr("%17s");
608   state_add( MIPS3_FPR24,        "FPR24", m_core->cpr[1][24]).formatstr("%016X");
609   state_add( MIPS3_FPS24,        "FPS24", m_core->cpr[1][24]).formatstr("%17s");
610   state_add( MIPS3_FPD24,        "FPD24", m_core->cpr[1][24]).formatstr("%17s");
611   state_add( MIPS3_FPR25,        "FPR25", m_core->cpr[1][25]).formatstr("%016X");
612   state_add( MIPS3_FPS25,        "FPS25", m_core->cpr[1][25]).formatstr("%17s");
613   state_add( MIPS3_FPD25,        "FPD25", m_core->cpr[1][25]).formatstr("%17s");
614   state_add( MIPS3_FPR26,        "FPR26", m_core->cpr[1][26]).formatstr("%016X");
615   state_add( MIPS3_FPS26,        "FPS26", m_core->cpr[1][26]).formatstr("%17s");
616   state_add( MIPS3_FPD26,        "FPD26", m_core->cpr[1][26]).formatstr("%17s");
617   state_add( MIPS3_FPR27,        "FPR27", m_core->cpr[1][27]).formatstr("%016X");
618   state_add( MIPS3_FPS27,        "FPS27", m_core->cpr[1][27]).formatstr("%17s");
619   state_add( MIPS3_FPD27,        "FPD27", m_core->cpr[1][27]).formatstr("%17s");
620   state_add( MIPS3_FPR28,        "FPR28", m_core->cpr[1][28]).formatstr("%016X");
621   state_add( MIPS3_FPS28,        "FPS28", m_core->cpr[1][28]).formatstr("%17s");
622   state_add( MIPS3_FPD28,        "FPD28", m_core->cpr[1][28]).formatstr("%17s");
623   state_add( MIPS3_FPR29,        "FPR29", m_core->cpr[1][29]).formatstr("%016X");
624   state_add( MIPS3_FPS29,        "FPS29", m_core->cpr[1][29]).formatstr("%17s");
625   state_add( MIPS3_FPD29,        "FPD29", m_core->cpr[1][29]).formatstr("%17s");
626   state_add( MIPS3_FPR30,        "FPR30", m_core->cpr[1][30]).formatstr("%016X");
627   state_add( MIPS3_FPS30,        "FPS30", m_core->cpr[1][30]).formatstr("%17s");
628   state_add( MIPS3_FPD30,        "FPD30", m_core->cpr[1][30]).formatstr("%17s");
629   state_add( MIPS3_FPR31,        "FPR31", m_core->cpr[1][31]).formatstr("%016X");
630   state_add( MIPS3_FPS31,        "FPS31", m_core->cpr[1][31]).formatstr("%17s");
631   state_add( MIPS3_FPD31,        "FPD31", m_core->cpr[1][31]).formatstr("%17s");
632
633   state_add( MIPS3_SR,           "SR", m_core->cpr[0][COP0_Status]).formatstr("%08X");
634   state_add( MIPS3_EPC,          "EPC", m_core->cpr[0][COP0_EPC]).formatstr("%08X");
635   state_add( MIPS3_CAUSE,        "Cause", m_core->cpr[0][COP0_Cause]).formatstr("%08X");
636   state_add( MIPS3_COUNT,        "Count", m_debugger_temp).callexport().formatstr("%08X");
637   state_add( MIPS3_COMPARE,      "Compare", m_core->cpr[0][COP0_Compare]).formatstr("%08X");
638   state_add( MIPS3_INDEX,        "Index", m_core->cpr[0][COP0_Index]).formatstr("%08X");
639   state_add( MIPS3_RANDOM,       "Random", m_core->cpr[0][COP0_Random]).formatstr("%08X");
640   state_add( MIPS3_ENTRYHI,      "EntryHi", m_core->cpr[0][COP0_EntryHi]).formatstr("%016X");
641   state_add( MIPS3_ENTRYLO0,     "EntryLo0", m_core->cpr[0][COP0_EntryLo0]).formatstr("%016X");
642   state_add( MIPS3_ENTRYLO1,     "EntryLo1", m_core->cpr[0][COP0_EntryLo1]).formatstr("%016X");
643   state_add( MIPS3_PAGEMASK,     "PageMask", m_core->cpr[0][COP0_PageMask]).formatstr("%016X");
644   state_add( MIPS3_WIRED,        "Wired", m_core->cpr[0][COP0_Wired]).formatstr("%08X");
645   state_add( MIPS3_BADVADDR,     "BadVAddr", m_core->cpr[0][COP0_BadVAddr]).formatstr("%08X");
646
647   state_add( STATE_GENPC, "GENPC", m_core->pc).noshow();
648   state_add( STATE_GENSP, "GENSP", m_core->r[31]).noshow();
649   state_add( STATE_GENFLAGS, "GENFLAGS", m_debugger_temp).formatstr("%1s").noshow();
650
651   m_icountptr = &m_core->icount;
297652}
298653
299654
300static CPU_TRANSLATE( mips3 )
655void mips3_device::state_export(const device_state_entry &entry)
301656{
302   /* common translate */
303   return mips3com_translate_address(&mips3.core, space, intention, address);
657   switch (entry.index())
658   {
659      case MIPS3_COUNT:
660         m_debugger_temp = (total_cycles() - m_core->count_zero_time) / 2;
661         break;
662   }
304663}
305664
306665
307CPU_DISASSEMBLE( mips3 )
666void mips3_device::state_string_export(const device_state_entry &entry, astring &string)
308667{
309   /* common disassemble */
310   return mips3com_dasm(&mips3.core, buffer, pc, oprom, opram);
668   switch (entry.index())
669   {
670      case MIPS3_FPS0:
671         string.printf("!%16g", *(float *)&m_core->cpr[1][0]);
672         break;
673
674      case MIPS3_FPD0:
675         string.printf("!%16g", *(double *)&m_core->cpr[1][0]);
676         break;
677
678      case MIPS3_FPS1:
679         string.printf("!%16g", *(float *)&m_core->cpr[1][1]);
680         break;
681
682      case MIPS3_FPD1:
683         string.printf("!%16g", *(double *)&m_core->cpr[1][1]);
684         break;
685
686      case MIPS3_FPS2:
687         string.printf("!%16g", *(float *)&m_core->cpr[1][2]);
688         break;
689
690      case MIPS3_FPD2:
691         string.printf("!%16g", *(double *)&m_core->cpr[1][2]);
692         break;
693
694      case MIPS3_FPS3:
695         string.printf("!%16g", *(float *)&m_core->cpr[1][3]);
696         break;
697
698      case MIPS3_FPD3:
699         string.printf("!%16g", *(double *)&m_core->cpr[1][3]);
700         break;
701
702      case MIPS3_FPS4:
703         string.printf("!%16g", *(float *)&m_core->cpr[1][4]);
704         break;
705
706      case MIPS3_FPD4:
707         string.printf("!%16g", *(double *)&m_core->cpr[1][4]);
708         break;
709
710      case MIPS3_FPS5:
711         string.printf("!%16g", *(float *)&m_core->cpr[1][5]);
712         break;
713
714      case MIPS3_FPD5:
715         string.printf("!%16g", *(double *)&m_core->cpr[1][5]);
716         break;
717
718      case MIPS3_FPS6:
719         string.printf("!%16g", *(float *)&m_core->cpr[1][6]);
720         break;
721
722      case MIPS3_FPD6:
723         string.printf("!%16g", *(double *)&m_core->cpr[1][6]);
724         break;
725
726      case MIPS3_FPS7:
727         string.printf("!%16g", *(float *)&m_core->cpr[1][7]);
728         break;
729
730      case MIPS3_FPD7:
731         string.printf("!%16g", *(double *)&m_core->cpr[1][7]);
732         break;
733
734      case MIPS3_FPS8:
735         string.printf("!%16g", *(float *)&m_core->cpr[1][8]);
736         break;
737
738      case MIPS3_FPD8:
739         string.printf("!%16g", *(double *)&m_core->cpr[1][8]);
740         break;
741
742      case MIPS3_FPS9:
743         string.printf("!%16g", *(float *)&m_core->cpr[1][9]);
744         break;
745
746      case MIPS3_FPD9:
747         string.printf("!%16g", *(double *)&m_core->cpr[1][9]);
748         break;
749
750      case MIPS3_FPS10:
751         string.printf("!%16g", *(float *)&m_core->cpr[1][10]);
752         break;
753
754      case MIPS3_FPD10:
755         string.printf("!%16g", *(double *)&m_core->cpr[1][10]);
756         break;
757
758      case MIPS3_FPS11:
759         string.printf("!%16g", *(float *)&m_core->cpr[1][11]);
760         break;
761
762      case MIPS3_FPD11:
763         string.printf("!%16g", *(double *)&m_core->cpr[1][11]);
764         break;
765
766      case MIPS3_FPS12:
767         string.printf("!%16g", *(float *)&m_core->cpr[1][12]);
768         break;
769
770      case MIPS3_FPD12:
771         string.printf("!%16g", *(double *)&m_core->cpr[1][12]);
772         break;
773
774      case MIPS3_FPS13:
775         string.printf("!%16g", *(float *)&m_core->cpr[1][13]);
776         break;
777
778      case MIPS3_FPD13:
779         string.printf("!%16g", *(double *)&m_core->cpr[1][13]);
780         break;
781
782      case MIPS3_FPS14:
783         string.printf("!%16g", *(float *)&m_core->cpr[1][14]);
784         break;
785
786      case MIPS3_FPD14:
787         string.printf("!%16g", *(double *)&m_core->cpr[1][14]);
788         break;
789
790      case MIPS3_FPS15:
791         string.printf("!%16g", *(float *)&m_core->cpr[1][15]);
792         break;
793
794      case MIPS3_FPD15:
795         string.printf("!%16g", *(double *)&m_core->cpr[1][15]);
796         break;
797
798      case MIPS3_FPS16:
799         string.printf("!%16g", *(float *)&m_core->cpr[1][16]);
800         break;
801
802      case MIPS3_FPD16:
803         string.printf("!%16g", *(double *)&m_core->cpr[1][16]);
804         break;
805
806      case MIPS3_FPS17:
807         string.printf("!%16g", *(float *)&m_core->cpr[1][17]);
808         break;
809
810      case MIPS3_FPD17:
811         string.printf("!%16g", *(double *)&m_core->cpr[1][17]);
812         break;
813
814      case MIPS3_FPS18:
815         string.printf("!%16g", *(float *)&m_core->cpr[1][18]);
816         break;
817
818      case MIPS3_FPD18:
819         string.printf("!%16g", *(double *)&m_core->cpr[1][18]);
820         break;
821
822      case MIPS3_FPS19:
823         string.printf("!%16g", *(float *)&m_core->cpr[1][19]);
824         break;
825
826      case MIPS3_FPD19:
827         string.printf("!%16g", *(double *)&m_core->cpr[1][19]);
828         break;
829
830      case MIPS3_FPS20:
831         string.printf("!%16g", *(float *)&m_core->cpr[1][20]);
832         break;
833
834      case MIPS3_FPD20:
835         string.printf("!%16g", *(double *)&m_core->cpr[1][20]);
836         break;
837
838      case MIPS3_FPS21:
839         string.printf("!%16g", *(float *)&m_core->cpr[1][21]);
840         break;
841
842      case MIPS3_FPD21:
843         string.printf("!%16g", *(double *)&m_core->cpr[1][21]);
844         break;
845
846      case MIPS3_FPS22:
847         string.printf("!%16g", *(float *)&m_core->cpr[1][22]);
848         break;
849
850      case MIPS3_FPD22:
851         string.printf("!%16g", *(double *)&m_core->cpr[1][22]);
852         break;
853
854      case MIPS3_FPS23:
855         string.printf("!%16g", *(float *)&m_core->cpr[1][23]);
856         break;
857
858      case MIPS3_FPD23:
859         string.printf("!%16g", *(double *)&m_core->cpr[1][23]);
860         break;
861
862      case MIPS3_FPS24:
863         string.printf("!%16g", *(float *)&m_core->cpr[1][24]);
864         break;
865
866      case MIPS3_FPD24:
867         string.printf("!%16g", *(double *)&m_core->cpr[1][24]);
868         break;
869
870      case MIPS3_FPS25:
871         string.printf("!%16g", *(float *)&m_core->cpr[1][25]);
872         break;
873
874      case MIPS3_FPD25:
875         string.printf("!%16g", *(double *)&m_core->cpr[1][25]);
876         break;
877
878      case MIPS3_FPS26:
879         string.printf("!%16g", *(float *)&m_core->cpr[1][26]);
880         break;
881
882      case MIPS3_FPD26:
883         string.printf("!%16g", *(double *)&m_core->cpr[1][26]);
884         break;
885
886      case MIPS3_FPS27:
887         string.printf("!%16g", *(float *)&m_core->cpr[1][27]);
888         break;
889
890      case MIPS3_FPD27:
891         string.printf("!%16g", *(double *)&m_core->cpr[1][27]);
892         break;
893
894      case MIPS3_FPS28:
895         string.printf("!%16g", *(float *)&m_core->cpr[1][28]);
896         break;
897
898      case MIPS3_FPD28:
899         string.printf("!%16g", *(double *)&m_core->cpr[1][28]);
900         break;
901
902      case MIPS3_FPS29:
903         string.printf("!%16g", *(float *)&m_core->cpr[1][29]);
904         break;
905
906      case MIPS3_FPD29:
907         string.printf("!%16g", *(double *)&m_core->cpr[1][29]);
908         break;
909
910      case MIPS3_FPS30:
911         string.printf("!%16g", *(float *)&m_core->cpr[1][30]);
912         break;
913
914      case MIPS3_FPD30:
915         string.printf("!%16g", *(double *)&m_core->cpr[1][30]);
916         break;
917
918      case MIPS3_FPS31:
919         string.printf("!%16g", *(float *)&m_core->cpr[1][31]);
920         break;
921
922      case MIPS3_FPD31:
923         string.printf("!%16g", *(double *)&m_core->cpr[1][31]);
924         break;
925
926      case STATE_GENFLAGS:
927         string.printf(" ");
928         break;
929   }
311930}
312931
313932
933void mips3_device::device_reset()
934{
935   /* common reset */
936   m_nextpc = ~0;
937   memset(m_cf, 0, sizeof(m_cf));
314938
939   /* initialize the state */
940   m_core->pc = 0xbfc00000;
941   m_core->cpr[0][COP0_Status] = SR_BEV | SR_ERL;
942   m_core->cpr[0][COP0_Wired] = 0;
943   m_core->cpr[0][COP0_Compare] = 0xffffffff;
944   m_core->cpr[0][COP0_Count] = 0;
945   m_core->cpr[0][COP0_Config] = compute_config_register();
946   m_core->cpr[0][COP0_PRId] = compute_prid_register();
947   m_core->count_zero_time = total_cycles();
948
949   /* initialize the TLB state */
950   for (int tlbindex = 0; tlbindex < m_tlbentries; tlbindex++)
951   {
952      mips3_tlb_entry *entry = &m_tlb[tlbindex];
953      entry->page_mask = 0;
954      entry->entry_hi = 0xffffffff;
955      entry->entry_lo[0] = 0xfffffff8;
956      entry->entry_lo[1] = 0xfffffff8;
957      vtlb_load(m_vtlb, 2 * tlbindex + 0, 0, 0, 0);
958      vtlb_load(m_vtlb, 2 * tlbindex + 1, 0, 0, 0);
959   }
960
961   /* load the fixed TLB range */
962   vtlb_load(m_vtlb, 2 * m_tlbentries + 0, (0xa0000000 - 0x80000000) >> MIPS3_MIN_PAGE_SHIFT, 0x80000000, 0x00000000 | VTLB_READ_ALLOWED | VTLB_WRITE_ALLOWED | VTLB_FETCH_ALLOWED | VTLB_FLAG_VALID);
963   vtlb_load(m_vtlb, 2 * m_tlbentries + 1, (0xc0000000 - 0xa0000000) >> MIPS3_MIN_PAGE_SHIFT, 0xa0000000, 0x00000000 | VTLB_READ_ALLOWED | VTLB_WRITE_ALLOWED | VTLB_FETCH_ALLOWED | VTLB_FLAG_VALID);
964
965   m_core->mode = (MODE_KERNEL << 1) | 0;
966   m_cache_dirty = TRUE;
967   m_interrupt_cycles = 0;
968}
969
970
971bool mips3_device::memory_translate(address_spacenum spacenum, int intention, offs_t &address)
972{
973   /* only applies to the program address space */
974   if (spacenum == AS_PROGRAM)
975   {
976      const vtlb_entry *table = vtlb_table(m_vtlb);
977      vtlb_entry entry = table[address >> MIPS3_MIN_PAGE_SHIFT];
978      if ((entry & (1 << (intention & (TRANSLATE_TYPE_MASK | TRANSLATE_USER_MASK)))) == 0)
979         return false;
980      address = (entry & ~MIPS3_MIN_PAGE_MASK) | (address & MIPS3_MIN_PAGE_MASK);
981   }
982   return true;
983}
984
985
986offs_t mips3_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
987{
988   extern unsigned dasmmips3(char *, unsigned, UINT32);
989   UINT32 op = *(UINT32 *)oprom;
990   if (m_bigendian)
991      op = BIG_ENDIANIZE_INT32(op);
992   else
993      op = LITTLE_ENDIANIZE_INT32(op);
994   return dasmmips3(buffer, pc, op);
995}
996
997
998
315999/***************************************************************************
3161000    TLB HANDLING
3171001***************************************************************************/
3181002
319INLINE int RBYTE(offs_t address, UINT32 *result)
1003inline int mips3_device::RBYTE(offs_t address, UINT32 *result)
3201004{
321   UINT32 tlbval = mips3.tlb_table[address >> 12];
1005   UINT32 tlbval = m_tlb_table[address >> 12];
3221006   if (tlbval & VTLB_READ_ALLOWED)
3231007   {
324      *result = (*mips3.core.memory.read_byte)(*mips3.core.program, (tlbval & ~0xfff) | (address & 0xfff));
1008      *result = (*m_memory.read_byte)(*m_program, (tlbval & ~0xfff) | (address & 0xfff));
3251009   }
3261010   else
3271011   {
r30757r30758
3401024}
3411025
3421026
343INLINE int RHALF(offs_t address, UINT32 *result)
1027inline int mips3_device::RHALF(offs_t address, UINT32 *result)
3441028{
345   UINT32 tlbval = mips3.tlb_table[address >> 12];
1029   UINT32 tlbval = m_tlb_table[address >> 12];
3461030   if (tlbval & VTLB_READ_ALLOWED)
3471031   {
348      *result = (*mips3.core.memory.read_word)(*mips3.core.program, (tlbval & ~0xfff) | (address & 0xfff));
1032      *result = (*m_memory.read_word)(*m_program, (tlbval & ~0xfff) | (address & 0xfff));
3491033   }
3501034   else
3511035   {
r30757r30758
3641048}
3651049
3661050
367INLINE int RWORD(offs_t address, UINT32 *result)
1051inline int mips3_device::RWORD(offs_t address, UINT32 *result)
3681052{
369   UINT32 tlbval = mips3.tlb_table[address >> 12];
1053   UINT32 tlbval = m_tlb_table[address >> 12];
3701054   if (tlbval & VTLB_READ_ALLOWED)
3711055   {
372      *result = (*mips3.core.memory.read_dword)(*mips3.core.program, (tlbval & ~0xfff) | (address & 0xfff));
1056      *result = (*m_memory.read_dword)(*m_program, (tlbval & ~0xfff) | (address & 0xfff));
3731057   }
3741058   else
3751059   {
r30757r30758
3881072}
3891073
3901074
391INLINE int RWORD_MASKED(offs_t address, UINT32 *result, UINT32 mem_mask)
1075inline int mips3_device::RWORD_MASKED(offs_t address, UINT32 *result, UINT32 mem_mask)
3921076{
393   UINT32 tlbval = mips3.tlb_table[address >> 12];
1077   UINT32 tlbval = m_tlb_table[address >> 12];
3941078   if (tlbval & VTLB_READ_ALLOWED)
3951079   {
396      *result = (*mips3.core.memory.read_dword_masked)(*mips3.core.program, (tlbval & ~0xfff) | (address & 0xfff), mem_mask);
1080      *result = (*m_memory.read_dword_masked)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), mem_mask);
3971081   }
3981082   else
3991083   {
r30757r30758
4121096}
4131097
4141098
415INLINE int RDOUBLE(offs_t address, UINT64 *result)
1099inline int mips3_device::RDOUBLE(offs_t address, UINT64 *result)
4161100{
417   UINT32 tlbval = mips3.tlb_table[address >> 12];
1101   UINT32 tlbval = m_tlb_table[address >> 12];
4181102   if (tlbval & VTLB_READ_ALLOWED)
4191103   {
420      *result = (*mips3.core.memory.read_qword)(*mips3.core.program, (tlbval & ~0xfff) | (address & 0xfff));
1104      *result = (*m_memory.read_qword)(*m_program, (tlbval & ~0xfff) | (address & 0xfff));
4211105   }
4221106   else
4231107   {
r30757r30758
4361120}
4371121
4381122
439INLINE int RDOUBLE_MASKED(offs_t address, UINT64 *result, UINT64 mem_mask)
1123inline int mips3_device::RDOUBLE_MASKED(offs_t address, UINT64 *result, UINT64 mem_mask)
4401124{
441   UINT32 tlbval = mips3.tlb_table[address >> 12];
1125   UINT32 tlbval = m_tlb_table[address >> 12];
4421126   if (tlbval & VTLB_READ_ALLOWED)
4431127   {
444      *result = (*mips3.core.memory.read_qword_masked)(*mips3.core.program, (tlbval & ~0xfff) | (address & 0xfff), mem_mask);
1128      *result = (*m_memory.read_qword_masked)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), mem_mask);
4451129   }
4461130   else
4471131   {
r30757r30758
4601144}
4611145
4621146
463INLINE void WBYTE(offs_t address, UINT8 data)
1147inline void mips3_device::WBYTE(offs_t address, UINT8 data)
4641148{
465   UINT32 tlbval = mips3.tlb_table[address >> 12];
1149   UINT32 tlbval = m_tlb_table[address >> 12];
4661150   if (tlbval & VTLB_WRITE_ALLOWED)
4671151   {
468      (*mips3.core.memory.write_byte)(*mips3.core.program, (tlbval & ~0xfff) | (address & 0xfff), data);
1152      (*m_memory.write_byte)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data);
4691153   }
4701154   else
4711155   {
r30757r30758
4851169}
4861170
4871171
488INLINE void WHALF(offs_t address, UINT16 data)
1172inline void mips3_device::WHALF(offs_t address, UINT16 data)
4891173{
490   UINT32 tlbval = mips3.tlb_table[address >> 12];
1174   UINT32 tlbval = m_tlb_table[address >> 12];
4911175   if (tlbval & VTLB_WRITE_ALLOWED)
4921176   {
493      (*mips3.core.memory.write_word)(*mips3.core.program, (tlbval & ~0xfff) | (address & 0xfff), data);
1177      (*m_memory.write_word)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data);
4941178   }
4951179   else
4961180   {
r30757r30758
5101194}
5111195
5121196
513INLINE void WWORD(offs_t address, UINT32 data)
1197inline void mips3_device::WWORD(offs_t address, UINT32 data)
5141198{
515   UINT32 tlbval = mips3.tlb_table[address >> 12];
1199   UINT32 tlbval = m_tlb_table[address >> 12];
5161200   if (tlbval & VTLB_WRITE_ALLOWED)
5171201   {
518      (*mips3.core.memory.write_dword)(*mips3.core.program, (tlbval & ~0xfff) | (address & 0xfff), data);
1202      (*m_memory.write_dword)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data);
5191203   }
5201204   else
5211205   {
r30757r30758
5351219}
5361220
5371221
538INLINE void WWORD_MASKED(offs_t address, UINT32 data, UINT32 mem_mask)
1222inline void mips3_device::WWORD_MASKED(offs_t address, UINT32 data, UINT32 mem_mask)
5391223{
540   UINT32 tlbval = mips3.tlb_table[address >> 12];
1224   UINT32 tlbval = m_tlb_table[address >> 12];
5411225   if (tlbval & VTLB_WRITE_ALLOWED)
5421226   {
543      (*mips3.core.memory.write_dword_masked)(*mips3.core.program, (tlbval & ~0xfff) | (address & 0xfff), data, mem_mask);
1227      (*m_memory.write_dword_masked)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data, mem_mask);
5441228   }
5451229   else
5461230   {
r30757r30758
5601244}
5611245
5621246
563INLINE void WDOUBLE(offs_t address, UINT64 data)
1247inline void mips3_device::WDOUBLE(offs_t address, UINT64 data)
5641248{
565   UINT32 tlbval = mips3.tlb_table[address >> 12];
1249   UINT32 tlbval = m_tlb_table[address >> 12];
5661250   //printf("%08x: %08x\n", (UINT32)address, (UINT32)tlbval);
5671251   if (tlbval & VTLB_WRITE_ALLOWED)
5681252   {
569      (*mips3.core.memory.write_qword)(*mips3.core.program, (tlbval & ~0xfff)  | (address & 0xfff), data);
1253      (*m_memory.write_qword)(*m_program, (tlbval & ~0xfff)  | (address & 0xfff), data);
5701254   }
5711255   else
5721256   {
r30757r30758
5861270}
5871271
5881272
589INLINE void WDOUBLE_MASKED(offs_t address, UINT64 data, UINT64 mem_mask)
1273inline void mips3_device::WDOUBLE_MASKED(offs_t address, UINT64 data, UINT64 mem_mask)
5901274{
591   UINT32 tlbval = mips3.tlb_table[address >> 12];
1275   UINT32 tlbval = m_tlb_table[address >> 12];
5921276   if (tlbval & VTLB_WRITE_ALLOWED)
5931277   {
594      (*mips3.core.memory.write_qword_masked)(*mips3.core.program, (tlbval & ~0xfff)  | (address & 0xfff), data, mem_mask);
1278      (*m_memory.write_qword_masked)(*m_program, (tlbval & ~0xfff)  | (address & 0xfff), data, mem_mask);
5951279   }
5961280   else
5971281   {
r30757r30758
6161300    COP0 (SYSTEM) EXECUTION HANDLING
6171301***************************************************************************/
6181302
619INLINE UINT64 get_cop0_reg(int idx)
1303inline UINT64 mips3_device::get_cop0_reg(int idx)
6201304{
6211305   if (idx == COP0_Count)
6221306   {
6231307      /* it doesn't really take 250 cycles to read this register, but it helps speed */
6241308      /* up loops that hammer on it */
625      if (mips3.core.icount >= MIPS3_COUNT_READ_CYCLES)
626         mips3.core.icount -= MIPS3_COUNT_READ_CYCLES;
1309      if (m_core->icount >= MIPS3_COUNT_READ_CYCLES)
1310         m_core->icount -= MIPS3_COUNT_READ_CYCLES;
6271311      else
628         mips3.core.icount = 0;
629      return (UINT32)((mips3.core.device->total_cycles() - mips3.core.count_zero_time) / 2);
1312         m_core->icount = 0;
1313      return (UINT32)((total_cycles() - m_core->count_zero_time) / 2);
6301314   }
6311315   else if (idx == COP0_Cause)
6321316   {
6331317      /* it doesn't really take 250 cycles to read this register, but it helps speed */
6341318      /* up loops that hammer on it */
635      if (mips3.core.icount >= MIPS3_CAUSE_READ_CYCLES)
636         mips3.core.icount -= MIPS3_CAUSE_READ_CYCLES;
1319      if (m_core->icount >= MIPS3_CAUSE_READ_CYCLES)
1320         m_core->icount -= MIPS3_CAUSE_READ_CYCLES;
6371321      else
638         mips3.core.icount = 0;
1322         m_core->icount = 0;
6391323   }
6401324   else if (idx == COP0_Random)
6411325   {
642      int wired = mips3.core.cpr[0][COP0_Wired] & 0x3f;
1326      int wired = m_core->cpr[0][COP0_Wired] & 0x3f;
6431327      int range = 48 - wired;
6441328      if (range > 0)
645         return ((mips3.core.device->total_cycles() - mips3.core.count_zero_time) % range + wired) & 0x3f;
1329         return ((total_cycles() - m_core->count_zero_time) % range + wired) & 0x3f;
6461330      else
6471331         return 47;
6481332   }
649   return mips3.core.cpr[0][idx];
1333   return m_core->cpr[0][idx];
6501334}
6511335
652INLINE void set_cop0_reg(int idx, UINT64 val)
1336inline void mips3_device::set_cop0_reg(int idx, UINT64 val)
6531337{
6541338   switch (idx)
6551339   {
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6581342         if (CAUSE & 0x300)
6591343         {
6601344            /* if we're in a delay slot, propogate the target PC before generating the exception */
661            if (mips3.nextpc != ~0)
1345            if (m_nextpc != ~0)
6621346            {
663               mips3.core.pc = mips3.nextpc;
664               mips3.nextpc = ~0;
1347               m_core->pc = m_nextpc;
1348               m_nextpc = ~0;
6651349            }
6661350            generate_exception(EXCEPTION_INTERRUPT, 0);
6671351         }
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6701354      case COP0_Status:
6711355      {
6721356         /* update interrupts and cycle counting */
673         UINT32 diff = mips3.core.cpr[0][idx] ^ val;
1357         UINT32 diff = m_core->cpr[0][idx] ^ val;
6741358//          if (val & 0xe0)
6751359//              fatalerror("System set 64-bit addressing mode, SR=%08X\n", val);
676         mips3.core.cpr[0][idx] = val;
1360         m_core->cpr[0][idx] = val;
6771361         if (diff & 0x8000)
678            mips3com_update_cycle_counting(&mips3.core);
1362            mips3com_update_cycle_counting();
6791363         check_irqs();
6801364         break;
6811365      }
6821366
6831367      case COP0_Count:
684         mips3.core.cpr[0][idx] = val;
685         mips3.core.count_zero_time = mips3.core.device->total_cycles() - ((UINT64)(UINT32)val * 2);
686         mips3com_update_cycle_counting(&mips3.core);
1368         m_core->cpr[0][idx] = val;
1369         m_core->count_zero_time = total_cycles() - ((UINT64)(UINT32)val * 2);
1370         mips3com_update_cycle_counting();
6871371         break;
6881372
6891373      case COP0_Compare:
690         mips3.core.compare_armed = 1;
1374         m_core->compare_armed = 1;
6911375         CAUSE &= ~0x8000;
692         mips3.core.cpr[0][idx] = val & 0xffffffff;
693         mips3com_update_cycle_counting(&mips3.core);
1376         m_core->cpr[0][idx] = val & 0xffffffff;
1377         mips3com_update_cycle_counting();
6941378         break;
6951379
6961380      case COP0_PRId:
6971381         break;
6981382
6991383      case COP0_Config:
700         mips3.core.cpr[0][idx] = (mips3.core.cpr[0][idx] & ~7) | (val & 7);
1384         m_core->cpr[0][idx] = (m_core->cpr[0][idx] & ~7) | (val & 7);
7011385         break;
7021386
7031387      case COP0_EntryHi:
7041388         /* if the ASID changes, remap */
705         if ((mips3.core.cpr[0][idx] ^ val) & 0xff)
1389         if ((m_core->cpr[0][idx] ^ val) & 0xff)
7061390         {
707            mips3.core.cpr[0][idx] = val;
708            mips3com_asid_changed(&mips3.core);
1391            m_core->cpr[0][idx] = val;
1392            mips3com_asid_changed();
7091393         }
710         mips3.core.cpr[0][idx] = val;
1394         m_core->cpr[0][idx] = val;
7111395         break;
7121396
7131397      default:
714         mips3.core.cpr[0][idx] = val;
1398         m_core->cpr[0][idx] = val;
7151399         break;
7161400   }
7171401}
7181402
719INLINE UINT64 get_cop0_creg(int idx)
1403inline UINT64 mips3_device::get_cop0_creg(int idx)
7201404{
721   return mips3.core.ccr[0][idx];
1405   return m_core->ccr[0][idx];
7221406}
7231407
724INLINE void set_cop0_creg(int idx, UINT64 val)
1408inline void mips3_device::set_cop0_creg(int idx, UINT64 val)
7251409{
726   mips3.core.ccr[0][idx] = val;
1410   m_core->ccr[0][idx] = val;
7271411}
7281412
729INLINE void handle_cop0(UINT32 op)
1413inline void mips3_device::handle_cop0(UINT32 op)
7301414{
7311415   if ((SR & SR_KSU_MASK) != SR_KSU_KERNEL && !(SR & SR_COP0))
7321416   {
733      mips3.badcop_value = 0;
1417      m_badcop_value = 0;
7341418      generate_exception(EXCEPTION_BADCOP, 1);
7351419   }
7361420
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7451429      case 0x08:  /* BC */
7461430         switch (RTREG)
7471431         {
748            case 0x00:  /* BCzF */  if (!mips3.cf[0]) ADDPC(SIMMVAL);               break;
749            case 0x01:  /* BCzF */  if (mips3.cf[0]) ADDPC(SIMMVAL);                break;
1432            case 0x00:  /* BCzF */  if (!m_cf[0]) ADDPC(SIMMVAL);               break;
1433            case 0x01:  /* BCzF */  if (m_cf[0]) ADDPC(SIMMVAL);                break;
7501434            case 0x02:  /* BCzFL */ invalid_instruction(op);                            break;
7511435            case 0x03:  /* BCzTL */ invalid_instruction(op);                            break;
7521436            default:    invalid_instruction(op);                                        break;
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7711455         switch (op & 0x01ffffff)
7721456         {
7731457            case 0x01:  /* TLBR */
774               mips3com_tlbr(&mips3.core);
1458               mips3com_tlbr();
7751459               break;
7761460
7771461            case 0x02:  /* TLBWI */
778               mips3com_tlbwi(&mips3.core);
1462               mips3com_tlbwi();
7791463               break;
7801464
7811465            case 0x06:  /* TLBWR */
782               mips3com_tlbwr(&mips3.core);
1466               mips3com_tlbwr();
7831467               break;
7841468
7851469            case 0x08:  /* TLBP */
786               mips3com_tlbp(&mips3.core);
1470               mips3com_tlbp();
7871471               break;
7881472
7891473            case 0x10:  /* RFE */   invalid_instruction(op);                            break;
790            case 0x18:  /* ERET */  logerror("ERET\n"); mips3.core.pc = mips3.core.cpr[0][COP0_EPC]; SR &= ~SR_EXL; check_irqs(); mips3.lld_value ^= 0xffffffff; mips3.ll_value ^= 0xffffffff;  break;
1474            case 0x18:  /* ERET */  logerror("ERET\n"); m_core->pc = m_core->cpr[0][COP0_EPC]; SR &= ~SR_EXL; check_irqs(); m_lld_value ^= 0xffffffff; m_ll_value ^= 0xffffffff;  break;
7911475            case 0x20:  /* WAIT */                                                      break;
7921476            default:    invalid_instruction(op);                                        break;
7931477         }
r30757r30758
8021486    COP1 (FPU) EXECUTION HANDLING
8031487***************************************************************************/
8041488
805INLINE UINT32 get_cop1_reg32(int idx)
1489inline UINT32 mips3_device::get_cop1_reg32(int idx)
8061490{
8071491   if (IS_FR0)
808      return ((UINT32 *)&mips3.core.cpr[1][0])[idx];
1492      return ((UINT32 *)&m_core->cpr[1][0])[idx];
8091493   else
810      return mips3.core.cpr[1][idx];
1494      return m_core->cpr[1][idx];
8111495}
8121496
813INLINE UINT64 get_cop1_reg64(int idx)
1497inline UINT64 mips3_device::get_cop1_reg64(int idx)
8141498{
8151499   if (IS_FR0)
816      return ((UINT64 *)&mips3.core.cpr[1][0])[idx/2];
1500      return ((UINT64 *)&m_core->cpr[1][0])[idx/2];
8171501   else
818      return mips3.core.cpr[1][idx];
1502      return m_core->cpr[1][idx];
8191503}
8201504
821INLINE void set_cop1_reg32(int idx, UINT32 val)
1505inline void mips3_device::set_cop1_reg32(int idx, UINT32 val)
8221506{
8231507   if (IS_FR0)
824      ((UINT32 *)&mips3.core.cpr[1][0])[idx] = val;
1508      ((UINT32 *)&m_core->cpr[1][0])[idx] = val;
8251509   else
826      mips3.core.cpr[1][idx] = val;
1510      m_core->cpr[1][idx] = val;
8271511}
8281512
829INLINE void set_cop1_reg64(int idx, UINT64 val)
1513inline void mips3_device::set_cop1_reg64(int idx, UINT64 val)
8301514{
8311515   if (IS_FR0)
832      ((UINT64 *)&mips3.core.cpr[1][0])[idx/2] = val;
1516      ((UINT64 *)&m_core->cpr[1][0])[idx/2] = val;
8331517   else
834      mips3.core.cpr[1][idx] = val;
1518      m_core->cpr[1][idx] = val;
8351519}
8361520
837INLINE UINT64 get_cop1_creg(int idx)
1521inline UINT64 mips3_device::get_cop1_creg(int idx)
8381522{
8391523   if (idx == 31)
8401524   {
841      UINT32 result = mips3.core.ccr[1][31] & ~0xfe800000;
1525      UINT32 result = m_core->ccr[1][31] & ~0xfe800000;
8421526      int i;
8431527
8441528      for (i = 0; i < 8; i++)
845         if (mips3.cf[1][i])
1529         if (m_cf[1][i])
8461530            result |= 1 << fcc_shift[i];
8471531      return result;
8481532   }
849   return mips3.core.ccr[1][idx];
1533   return m_core->ccr[1][idx];
8501534}
8511535
852INLINE void set_cop1_creg(int idx, UINT64 val)
1536inline void mips3_device::set_cop1_creg(int idx, UINT64 val)
8531537{
854   mips3.core.ccr[1][idx] = val;
1538   m_core->ccr[1][idx] = val;
8551539   if (idx == 31)
8561540   {
8571541      int i;
8581542
8591543      for (i = 0; i < 8; i++)
860         mips3.cf[1][i] = (val >> fcc_shift[i]) & 1;
1544         m_cf[1][i] = (val >> fcc_shift[i]) & 1;
8611545   }
8621546}
8631547
864INLINE void handle_cop1_fr0(UINT32 op)
1548inline void mips3_device::handle_cop1_fr0(UINT32 op)
8651549{
8661550   double dtemp;
8671551
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8691553
8701554   if (!(SR & SR_COP1))
8711555   {
872      mips3.badcop_value = 1;
1556      m_badcop_value = 1;
8731557      generate_exception(EXCEPTION_BADCOP, 1);
8741558   }
8751559
r30757r30758
8861570         {
8871571            case 0x00:  /* BCzF */  if (!GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL);   break;
8881572            case 0x01:  /* BCzT */  if (GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL);    break;
889            case 0x02:  /* BCzFL */ if (!GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL); else mips3.core.pc += 4;  break;
890            case 0x03:  /* BCzTL */ if (GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL); else mips3.core.pc += 4;   break;
1573            case 0x02:  /* BCzFL */ if (!GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL); else m_core->pc += 4;  break;
1574            case 0x03:  /* BCzTL */ if (GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL); else m_core->pc += 4;   break;
8911575         }
8921576         break;
8931577      default:
r30757r30758
12201904}
12211905
12221906
1223INLINE void handle_cop1_fr1(UINT32 op)
1907inline void mips3_device::handle_cop1_fr1(UINT32 op)
12241908{
12251909   double dtemp;
12261910
r30757r30758
12281912
12291913   if (!(SR & SR_COP1))
12301914   {
1231      mips3.badcop_value = 1;
1915      m_badcop_value = 1;
12321916      generate_exception(EXCEPTION_BADCOP, 1);
12331917   }
12341918
r30757r30758
12451929         {
12461930            case 0x00:  /* BCzF */  if (!GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL);   break;
12471931            case 0x01:  /* BCzT */  if (GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL);    break;
1248            case 0x02:  /* BCzFL */ if (!GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL); else mips3.core.pc += 4;  break;
1249            case 0x03:  /* BCzTL */ if (GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL); else mips3.core.pc += 4;   break;
1932            case 0x02:  /* BCzFL */ if (!GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL); else m_core->pc += 4;  break;
1933            case 0x03:  /* BCzTL */ if (GET_FCC((op >> 18) & 7)) ADDPC(SIMMVAL); else m_core->pc += 4;   break;
12501934         }
12511935         break;
12521936      default:
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15842268    COP1X (FPU EXTRA) EXECUTION HANDLING
15852269***************************************************************************/
15862270
1587INLINE void handle_cop1x_fr0(UINT32 op)
2271inline void mips3_device::handle_cop1x_fr0(UINT32 op)
15882272{
15892273   UINT64 temp64;
15902274   UINT32 temp;
15912275
15922276   if (!(SR & SR_COP1))
15932277   {
1594      mips3.badcop_value = 1;
2278      m_badcop_value = 1;
15952279      generate_exception(EXCEPTION_BADCOP, 1);
15962280   }
15972281
r30757r30758
16632347}
16642348
16652349
1666INLINE void handle_cop1x_fr1(UINT32 op)
2350inline void mips3_device::handle_cop1x_fr1(UINT32 op)
16672351{
16682352   UINT64 temp64;
16692353   UINT32 temp;
16702354
16712355   if (!(SR & SR_COP1))
16722356   {
1673      mips3.badcop_value = 1;
2357      m_badcop_value = 1;
16742358      generate_exception(EXCEPTION_BADCOP, 1);
16752359   }
16762360
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17472431    COP2 (CUSTOM) EXECUTION HANDLING
17482432***************************************************************************/
17492433
1750INLINE UINT64 get_cop2_reg(int idx)
2434inline UINT64 mips3_device::get_cop2_reg(int idx)
17512435{
1752   return mips3.core.cpr[2][idx];
2436   return m_core->cpr[2][idx];
17532437}
17542438
1755INLINE void set_cop2_reg(int idx, UINT64 val)
2439inline void mips3_device::set_cop2_reg(int idx, UINT64 val)
17562440{
1757   mips3.core.cpr[2][idx] = val;
2441   m_core->cpr[2][idx] = val;
17582442}
17592443
1760INLINE UINT64 get_cop2_creg(int idx)
2444inline UINT64 mips3_device::get_cop2_creg(int idx)
17612445{
1762   return mips3.core.ccr[2][idx];
2446   return m_core->ccr[2][idx];
17632447}
17642448
1765INLINE void set_cop2_creg(int idx, UINT64 val)
2449inline void mips3_device::set_cop2_creg(int idx, UINT64 val)
17662450{
1767   mips3.core.ccr[2][idx] = val;
2451   m_core->ccr[2][idx] = val;
17682452}
17692453
1770INLINE void handle_cop2(UINT32 op)
2454inline void mips3_device::handle_cop2(UINT32 op)
17712455{
17722456   if (!(SR & SR_COP2))
17732457   {
1774      mips3.badcop_value = 2;
2458      m_badcop_value = 2;
17752459      generate_exception(EXCEPTION_BADCOP, 1);
17762460   }
17772461
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17862470      case 0x08:  /* BC */
17872471         switch (RTREG)
17882472         {
1789            case 0x00:  /* BCzF */  if (!mips3.cf[2]) ADDPC(SIMMVAL);               break;
1790            case 0x01:  /* BCzF */  if (mips3.cf[2]) ADDPC(SIMMVAL);                break;
2473            case 0x00:  /* BCzF */  if (!m_cf[2]) ADDPC(SIMMVAL);               break;
2474            case 0x01:  /* BCzF */  if (m_cf[2]) ADDPC(SIMMVAL);                break;
17912475            case 0x02:  /* BCzFL */ invalid_instruction(op);                            break;
17922476            case 0x03:  /* BCzTL */ invalid_instruction(op);                            break;
17932477            default:    invalid_instruction(op);                                        break;
r30757r30758
18192503    CORE EXECUTION LOOP
18202504***************************************************************************/
18212505
1822CPU_EXECUTE( mips3 )
2506void mips3_device::execute_run()
18232507{
2508   if (m_isdrc)
2509   {
2510      int execute_result;
2511
2512      /* reset the cache if dirty */
2513      if (m_cache_dirty)
2514         code_flush_cache();
2515      m_cache_dirty = FALSE;
2516
2517      /* execute */
2518      do
2519      {
2520         /* run as much as we can */
2521         execute_result = m_drcuml->execute(*m_entry);
2522
2523         /* if we need to recompile, do it */
2524         if (execute_result == EXECUTE_MISSING_CODE)
2525         {
2526            code_compile_block(m_core->mode, m_core->pc);
2527         }
2528         else if (execute_result == EXECUTE_UNMAPPED_CODE)
2529         {
2530            fatalerror("Attempted to execute unmapped code at PC=%08X\n", m_core->pc);
2531         }
2532         else if (execute_result == EXECUTE_RESET_CACHE)
2533         {
2534            code_flush_cache();
2535         }
2536
2537      } while (execute_result != EXECUTE_OUT_OF_CYCLES);
2538
2539      return;
2540   }
2541
18242542   /* count cycles and interrupt cycles */
1825   mips3.core.icount -= mips3.interrupt_cycles;
1826   mips3.interrupt_cycles = 0;
2543   m_core->icount -= m_interrupt_cycles;
2544   m_interrupt_cycles = 0;
18272545
18282546   /* update timers & such */
1829   mips3com_update_cycle_counting(&mips3.core);
2547   mips3com_update_cycle_counting();
18302548
18312549   /* check for IRQs */
18322550   check_irqs();
r30757r30758
18392557      UINT32 temp;
18402558
18412559      /* debugging */
1842      mips3.ppc = mips3.core.pc;
1843      debugger_instruction_hook(device, mips3.core.pc);
2560      m_ppc = m_core->pc;
2561      debugger_instruction_hook(this, m_core->pc);
18442562
18452563      /* instruction fetch */
1846      if(!RWORD(mips3.core.pc, &op))
2564      if(!RWORD(m_core->pc, &op))
18472565      {
18482566         continue;
18492567      }
18502568
18512569      /* adjust for next PC */
1852      if (mips3.nextpc != ~0)
2570      if (m_nextpc != ~0)
18532571      {
1854         mips3.core.pc = mips3.nextpc;
1855         mips3.nextpc = ~0;
2572         m_core->pc = m_nextpc;
2573         m_nextpc = ~0;
18562574      }
18572575      else
1858         mips3.core.pc += 4;
2576         m_core->pc += 4;
18592577
18602578      /* parse the instruction */
18612579      switch (op >> 26)
r30757r30758
18882606                  temp64 = (INT64)(INT32)RSVAL32 * (INT64)(INT32)RTVAL32;
18892607                  LOVAL64 = (INT32)temp64;
18902608                  HIVAL64 = (INT32)(temp64 >> 32);
1891                  mips3.core.icount -= 3;
2609                  m_core->icount -= 3;
18922610                  break;
18932611               case 0x19:  /* MULTU */
18942612                  temp64 = (UINT64)RSVAL32 * (UINT64)RTVAL32;
18952613                  LOVAL64 = (INT32)temp64;
18962614                  HIVAL64 = (INT32)(temp64 >> 32);
1897                  mips3.core.icount -= 3;
2615                  m_core->icount -= 3;
18982616                  break;
18992617               case 0x1a:  /* DIV */
19002618                  if (RTVAL32)
r30757r30758
19022620                     LOVAL64 = (INT32)((INT32)RSVAL32 / (INT32)RTVAL32);
19032621                     HIVAL64 = (INT32)((INT32)RSVAL32 % (INT32)RTVAL32);
19042622                  }
1905                  mips3.core.icount -= 35;
2623                  m_core->icount -= 35;
19062624                  break;
19072625               case 0x1b:  /* DIVU */
19082626                  if (RTVAL32)
r30757r30758
19102628                     LOVAL64 = (INT32)(RSVAL32 / RTVAL32);
19112629                     HIVAL64 = (INT32)(RSVAL32 % RTVAL32);
19122630                  }
1913                  mips3.core.icount -= 35;
2631                  m_core->icount -= 35;
19142632                  break;
19152633               case 0x1c:  /* DMULT */
19162634                  temp64 = (INT64)RSVAL64 * (INT64)RTVAL64;
19172635                  LOVAL64 = temp64;
19182636                  HIVAL64 = (INT64)temp64 >> 63;
1919                  mips3.core.icount -= 7;
2637                  m_core->icount -= 7;
19202638                  break;
19212639               case 0x1d:  /* DMULTU */
19222640                  temp64 = (UINT64)RSVAL64 * (UINT64)RTVAL64;
19232641                  LOVAL64 = temp64;
19242642                  HIVAL64 = 0;
1925                  mips3.core.icount -= 7;
2643                  m_core->icount -= 7;
19262644                  break;
19272645               case 0x1e:  /* DDIV */
19282646                  if (RTVAL64)
r30757r30758
19302648                     LOVAL64 = (INT64)RSVAL64 / (INT64)RTVAL64;
19312649                     HIVAL64 = (INT64)RSVAL64 % (INT64)RTVAL64;
19322650                  }
1933                  mips3.core.icount -= 67;
2651                  m_core->icount -= 67;
19342652                  break;
19352653               case 0x1f:  /* DDIVU */
19362654                  if (RTVAL64)
r30757r30758
19382656                     LOVAL64 = RSVAL64 / RTVAL64;
19392657                     HIVAL64 = RSVAL64 % RTVAL64;
19402658                  }
1941                  mips3.core.icount -= 67;
2659                  m_core->icount -= 67;
19422660                  break;
19432661               case 0x20:  /* ADD */
19442662                  if (ENABLE_OVERFLOWS && RSVAL32 > ~RTVAL32) generate_exception(EXCEPTION_OVERFLOW, 1);
r30757r30758
19872705            {
19882706               case 0x00:  /* BLTZ */      if ((INT64)RSVAL64 < 0) ADDPC(SIMMVAL);                         break;
19892707               case 0x01:  /* BGEZ */      if ((INT64)RSVAL64 >= 0) ADDPC(SIMMVAL);                        break;
1990               case 0x02:  /* BLTZL */     if ((INT64)RSVAL64 < 0) ADDPC(SIMMVAL); else mips3.core.pc += 4;        break;
1991               case 0x03:  /* BGEZL */     if ((INT64)RSVAL64 >= 0) ADDPC(SIMMVAL); else mips3.core.pc += 4;   break;
2708               case 0x02:  /* BLTZL */     if ((INT64)RSVAL64 < 0) ADDPC(SIMMVAL); else m_core->pc += 4;        break;
2709               case 0x03:  /* BGEZL */     if ((INT64)RSVAL64 >= 0) ADDPC(SIMMVAL); else m_core->pc += 4;   break;
19922710               case 0x08:  /* TGEI */      if ((INT64)RSVAL64 >= SIMMVAL) generate_exception(EXCEPTION_TRAP, 1);   break;
19932711               case 0x09:  /* TGEIU */     if (RSVAL64 >= UIMMVAL) generate_exception(EXCEPTION_TRAP, 1);  break;
19942712               case 0x0a:  /* TLTI */      if ((INT64)RSVAL64 < SIMMVAL) generate_exception(EXCEPTION_TRAP, 1);    break;
r30757r30758
19972715               case 0x0e:  /* TNEI */      if (RSVAL64 != UIMMVAL) generate_exception(EXCEPTION_TRAP, 1);  break;
19982716               case 0x10:  /* BLTZAL */    if ((INT64)RSVAL64 < 0) ADDPCL(SIMMVAL,31);                     break;
19992717               case 0x11:  /* BGEZAL */    if ((INT64)RSVAL64 >= 0) ADDPCL(SIMMVAL,31);                    break;
2000               case 0x12:  /* BLTZALL */   if ((INT64)RSVAL64 < 0) ADDPCL(SIMMVAL,31) else mips3.core.pc += 4; break;
2001               case 0x13:  /* BGEZALL */   if ((INT64)RSVAL64 >= 0) ADDPCL(SIMMVAL,31) else mips3.core.pc += 4;    break;
2718               case 0x12:  /* BLTZALL */   if ((INT64)RSVAL64 < 0) ADDPCL(SIMMVAL,31) else m_core->pc += 4; break;
2719               case 0x13:  /* BGEZALL */   if ((INT64)RSVAL64 >= 0) ADDPCL(SIMMVAL,31) else m_core->pc += 4;    break;
20022720               default:    /* ??? */       invalid_instruction(op);                                        break;
20032721            }
20042722            break;
r30757r30758
20242742         case 0x11:  /* COP1 */      if (IS_FR0) handle_cop1_fr0(op); else handle_cop1_fr1(op);              break;
20252743         case 0x12:  /* COP2 */      handle_cop2(op);                                                        break;
20262744         case 0x13:  /* COP1X - R5000 */if (IS_FR0) handle_cop1x_fr0(op); else handle_cop1x_fr1(op);         break;
2027         case 0x14:  /* BEQL */      if (RSVAL64 == RTVAL64) ADDPC(SIMMVAL); else mips3.core.pc += 4;                break;
2028         case 0x15:  /* BNEL */      if (RSVAL64 != RTVAL64) ADDPC(SIMMVAL); else mips3.core.pc += 4;                break;
2029         case 0x16:  /* BLEZL */     if ((INT64)RSVAL64 <= 0) ADDPC(SIMMVAL); else mips3.core.pc += 4;           break;
2030         case 0x17:  /* BGTZL */     if ((INT64)RSVAL64 > 0) ADDPC(SIMMVAL); else mips3.core.pc += 4;                break;
2745         case 0x14:  /* BEQL */      if (RSVAL64 == RTVAL64) ADDPC(SIMMVAL); else m_core->pc += 4;                break;
2746         case 0x15:  /* BNEL */      if (RSVAL64 != RTVAL64) ADDPC(SIMMVAL); else m_core->pc += 4;                break;
2747         case 0x16:  /* BLEZL */     if ((INT64)RSVAL64 <= 0) ADDPC(SIMMVAL); else m_core->pc += 4;           break;
2748         case 0x17:  /* BGTZL */     if ((INT64)RSVAL64 > 0) ADDPC(SIMMVAL); else m_core->pc += 4;                break;
20312749         case 0x18:  /* DADDI */
20322750            if (ENABLE_OVERFLOWS && (INT64)RSVAL64 > ~SIMMVAL) generate_exception(EXCEPTION_OVERFLOW, 1);
20332751            else if (RTREG) RTVAL64 = RSVAL64 + (INT64)SIMMVAL;
20342752            break;
20352753         case 0x19:  /* DADDIU */    if (RTREG) RTVAL64 = RSVAL64 + (UINT64)SIMMVAL;                         break;
2036         case 0x1a:  /* LDL */       (*mips3.ldl)(op);                                                       break;
2037         case 0x1b:  /* LDR */       (*mips3.ldr)(op);                                                       break;
2754         case 0x1a:  /* LDL */       (this->*m_ldl)(op);                                                       break;
2755         case 0x1b:  /* LDR */       (this->*m_ldr)(op);                                                       break;
20382756         case 0x1c:  /* IDT-specific opcodes: mad/madu/mul on R4640/4650, msub on RC32364 */
20392757            switch (op & 0x1f)
20402758            {
20412759               case 2: /* MUL */
20422760                  RDVAL64 = (INT32)((INT32)RSVAL32 * (INT32)RTVAL32);
2043                  mips3.core.icount -= 3;
2761                  m_core->icount -= 3;
20442762                  break;
20452763               default: invalid_instruction(op);
20462764            }
20472765            break;
20482766         case 0x20:  /* LB */        if (RBYTE(SIMMVAL+RSVAL32, &temp) && RTREG) RTVAL64 = (INT8)temp;       break;
20492767         case 0x21:  /* LH */        if (RHALF(SIMMVAL+RSVAL32, &temp) && RTREG) RTVAL64 = (INT16)temp;      break;
2050         case 0x22:  /* LWL */       (*mips3.lwl)(op);                                                       break;
2768         case 0x22:  /* LWL */       (this->*m_lwl)(op);                                                       break;
20512769         case 0x23:  /* LW */        if (RWORD(SIMMVAL+RSVAL32, &temp) && RTREG) RTVAL64 = (INT32)temp;      break;
20522770         case 0x24:  /* LBU */       if (RBYTE(SIMMVAL+RSVAL32, &temp) && RTREG) RTVAL64 = (UINT8)temp;      break;
20532771         case 0x25:  /* LHU */       if (RHALF(SIMMVAL+RSVAL32, &temp) && RTREG) RTVAL64 = (UINT16)temp;     break;
2054         case 0x26:  /* LWR */       (*mips3.lwr)(op);                                                       break;
2772         case 0x26:  /* LWR */       (this->*m_lwr)(op);                                                       break;
20552773         case 0x27:  /* LWU */       if (RWORD(SIMMVAL+RSVAL32, &temp) && RTREG) RTVAL64 = (UINT32)temp;     break;
20562774         case 0x28:  /* SB */        WBYTE(SIMMVAL+RSVAL32, RTVAL32);                                        break;
20572775         case 0x29:  /* SH */        WHALF(SIMMVAL+RSVAL32, RTVAL32);                                        break;
2058         case 0x2a:  /* SWL */       (*mips3.swl)(op);                                                       break;
2776         case 0x2a:  /* SWL */       (this->*m_swl)(op);                                                       break;
20592777         case 0x2b:  /* SW */        WWORD(SIMMVAL+RSVAL32, RTVAL32);                                        break;
2060         case 0x2c:  /* SDL */       (*mips3.sdl)(op);                                                       break;
2061         case 0x2d:  /* SDR */       (*mips3.sdr)(op);                                                       break;
2062         case 0x2e:  /* SWR */       (*mips3.swr)(op);                                                       break;
2778         case 0x2c:  /* SDL */       (this->*m_sdl)(op);                                                       break;
2779         case 0x2d:  /* SDR */       (this->*m_sdr)(op);                                                       break;
2780         case 0x2e:  /* SWR */       (this->*m_swr)(op);                                                       break;
20632781         case 0x2f:  /* CACHE */     /* effective no-op */                                                   break;
2064         case 0x30:  /* LL */        if (RWORD(SIMMVAL+RSVAL32, &temp) && RTREG) RTVAL64 = (UINT32)temp; mips3.ll_value = RTVAL32;       break;
2782         case 0x30:  /* LL */        if (RWORD(SIMMVAL+RSVAL32, &temp) && RTREG) RTVAL64 = (UINT32)temp; m_ll_value = RTVAL32;       break;
20652783         case 0x31:  /* LWC1 */      if (RWORD(SIMMVAL+RSVAL32, &temp)) set_cop1_reg32(RTREG, temp);         break;
20662784         case 0x32:  /* LWC2 */      if (RWORD(SIMMVAL+RSVAL32, &temp)) set_cop2_reg(RTREG, temp);           break;
20672785         case 0x33:  /* PREF */      /* effective no-op */                                                   break;
2068         case 0x34:  /* LLD */       if (RDOUBLE(SIMMVAL+RSVAL32, &temp64) && RTREG) RTVAL64 = temp64; mips3.lld_value = temp64;     break;
2786         case 0x34:  /* LLD */       if (RDOUBLE(SIMMVAL+RSVAL32, &temp64) && RTREG) RTVAL64 = temp64; m_lld_value = temp64;     break;
20692787         case 0x35:  /* LDC1 */      if (RDOUBLE(SIMMVAL+RSVAL32, &temp64)) set_cop1_reg64(RTREG, temp64);       break;
20702788         case 0x36:  /* LDC2 */      if (RDOUBLE(SIMMVAL+RSVAL32, &temp64)) set_cop2_reg(RTREG, temp64);     break;
20712789         case 0x37:  /* LD */        if (RDOUBLE(SIMMVAL+RSVAL32, &temp64) && RTREG) RTVAL64 = temp64;       break;
20722790         case 0x38:  /* SC */        if (RWORD(SIMMVAL+RSVAL32, &temp) && RTREG)
20732791                        {
2074                           if (temp == mips3.ll_value)
2792                           if (temp == m_ll_value)
20752793                           {
20762794                              WWORD(SIMMVAL+RSVAL32, RTVAL32);
20772795                              RTVAL64 = (UINT32)1;
r30757r30758
20872805         case 0x3b:  /* SWC3 */      invalid_instruction(op);                                                break;
20882806         case 0x3c:  /* SCD */       if (RDOUBLE(SIMMVAL+RSVAL32, &temp64) && RTREG)
20892807                        {
2090                           if (temp64 == mips3.lld_value)
2808                           if (temp64 == m_lld_value)
20912809                           {
20922810                              WDOUBLE(SIMMVAL+RSVAL32, RTVAL64);
20932811                              RTVAL64 = 1;
r30757r30758
21032821         case 0x3f:  /* SD */        WDOUBLE(SIMMVAL+RSVAL32, RTVAL64);                                      break;
21042822         default:    /* ??? */       invalid_instruction(op);                                                break;
21052823      }
2106      mips3.core.icount--;
2824      m_core->icount--;
21072825
2108   } while (mips3.core.icount > 0 || mips3.nextpc != ~0);
2826   } while (m_core->icount > 0 || m_nextpc != ~0);
21092827
2110   mips3.core.icount -= mips3.interrupt_cycles;
2111   mips3.interrupt_cycles = 0;
2828   m_core->icount -= m_interrupt_cycles;
2829   m_interrupt_cycles = 0;
21122830}
21132831
21142832
r30757r30758
21172835    COMPLEX OPCODE IMPLEMENTATIONS
21182836***************************************************************************/
21192837
2120static void lwl_be(UINT32 op)
2838void mips3_device::lwl_be(UINT32 op)
21212839{
21222840   offs_t offs = SIMMVAL + RSVAL32;
21232841   int shift = 8 * (offs & 3);
r30757r30758
21282846      RTVAL64 = (INT32)((RTVAL32 & ~mask) | (temp << shift));
21292847}
21302848
2131static void lwr_be(UINT32 op)
2849void mips3_device::lwr_be(UINT32 op)
21322850{
21332851   offs_t offs = SIMMVAL + RSVAL32;
21342852   int shift = 8 * (~offs & 3);
r30757r30758
21392857      RTVAL64 = (INT32)((RTVAL32 & ~mask) | (temp >> shift));
21402858}
21412859
2142static void ldl_be(UINT32 op)
2860void mips3_device::ldl_be(UINT32 op)
21432861{
21442862   offs_t offs = SIMMVAL + RSVAL32;
21452863   int shift = 8 * (offs & 7);
r30757r30758
21502868      RTVAL64 = (RTVAL64 & ~mask) | (temp << shift);
21512869}
21522870
2153static void ldr_be(UINT32 op)
2871void mips3_device::ldr_be(UINT32 op)
21542872{
21552873   offs_t offs = SIMMVAL + RSVAL32;
21562874   int shift = 8 * (~offs & 7);
r30757r30758
21612879      RTVAL64 = (RTVAL64 & ~mask) | (temp >> shift);
21622880}
21632881
2164static void swl_be(UINT32 op)
2882void mips3_device::swl_be(UINT32 op)
21652883{
21662884   offs_t offs = SIMMVAL + RSVAL32;
21672885   int shift = 8 * (offs & 3);
r30757r30758
21692887   WWORD_MASKED(offs & ~3, RTVAL32 >> shift, mask);
21702888}
21712889
2172static void swr_be(UINT32 op)
2890void mips3_device::swr_be(UINT32 op)
21732891{
21742892   offs_t offs = SIMMVAL + RSVAL32;
21752893   int shift = 8 * (~offs & 3);
r30757r30758
21772895   WWORD_MASKED(offs & ~3, RTVAL32 << shift, mask);
21782896}
21792897
2180static void sdl_be(UINT32 op)
2898void mips3_device::sdl_be(UINT32 op)
21812899{
21822900   offs_t offs = SIMMVAL + RSVAL32;
21832901   int shift = 8 * (offs & 7);
r30757r30758
21852903   WDOUBLE_MASKED(offs & ~7, RTVAL64 >> shift, mask);
21862904}
21872905
2188static void sdr_be(UINT32 op)
2906void mips3_device::sdr_be(UINT32 op)
21892907{
21902908   offs_t offs = SIMMVAL + RSVAL32;
21912909   int shift = 8 * (~offs & 7);
r30757r30758
21952913
21962914
21972915
2198static void lwl_le(UINT32 op)
2916void mips3_device::lwl_le(UINT32 op)
21992917{
22002918   offs_t offs = SIMMVAL + RSVAL32;
22012919   int shift = 8 * (~offs & 3);
r30757r30758
22062924      RTVAL64 = (INT32)((RTVAL32 & ~mask) | (temp << shift));
22072925}
22082926
2209static void lwr_le(UINT32 op)
2927void mips3_device::lwr_le(UINT32 op)
22102928{
22112929   offs_t offs = SIMMVAL + RSVAL32;
22122930   int shift = 8 * (offs & 3);
r30757r30758
22172935      RTVAL64 = (INT32)((RTVAL32 & ~mask) | (temp >> shift));
22182936}
22192937
2220static void ldl_le(UINT32 op)
2938void mips3_device::ldl_le(UINT32 op)
22212939{
22222940   offs_t offs = SIMMVAL + RSVAL32;
22232941   int shift = 8 * (~offs & 7);
r30757r30758
22282946      RTVAL64 = (RTVAL64 & ~mask) | (temp << shift);
22292947}
22302948
2231static void ldr_le(UINT32 op)
2949void mips3_device::ldr_le(UINT32 op)
22322950{
22332951   offs_t offs = SIMMVAL + RSVAL32;
22342952   int shift = 8 * (offs & 7);
r30757r30758
22392957      RTVAL64 = (RTVAL64 & ~mask) | (temp >> shift);
22402958}
22412959
2242static void swl_le(UINT32 op)
2960void mips3_device::swl_le(UINT32 op)
22432961{
22442962   offs_t offs = SIMMVAL + RSVAL32;
22452963   int shift = 8 * (~offs & 3);
r30757r30758
22472965   WWORD_MASKED(offs & ~3, RTVAL32 >> shift, mask);
22482966}
22492967
2250static void swr_le(UINT32 op)
2968void mips3_device::swr_le(UINT32 op)
22512969{
22522970   offs_t offs = SIMMVAL + RSVAL32;
22532971   int shift = 8 * (offs & 3);
r30757r30758
22552973   WWORD_MASKED(offs & ~3, RTVAL32 << shift, mask);
22562974}
22572975
2258static void sdl_le(UINT32 op)
2976void mips3_device::sdl_le(UINT32 op)
22592977{
22602978   offs_t offs = SIMMVAL + RSVAL32;
22612979   int shift = 8 * (~offs & 7);
r30757r30758
22632981   WDOUBLE_MASKED(offs & ~7, RTVAL64 >> shift, mask);
22642982}
22652983
2266static void sdr_le(UINT32 op)
2984void mips3_device::sdr_le(UINT32 op)
22672985{
22682986   offs_t offs = SIMMVAL + RSVAL32;
22692987   int shift = 8 * (offs & 7);
r30757r30758
22712989   WDOUBLE_MASKED(offs & ~7, RTVAL64 << shift, mask);
22722990}
22732991
2274
2275
2276/***************************************************************************
2277    GENERIC GET/SET INFO
2278***************************************************************************/
2279
2280static CPU_SET_INFO( mips3 )
2281{
2282   /* everything is handled generically here */
2283   mips3com_set_info(&mips3.core, state, info);
2284}
2285
2286
2287static CPU_GET_INFO( mips3 )
2288{
2289   switch (state)
2290   {
2291      /* --- the following bits of info are returned as 64-bit signed integers --- */
2292      case CPUINFO_INT_CONTEXT_SIZE:                  info->i = sizeof(mips3);                break;
2293      case CPUINFO_INT_PREVIOUSPC:                    info->i = mips3.ppc;                    break;
2294
2295      /* --- the following bits of info are returned as pointers to data or functions --- */
2296      case CPUINFO_FCT_SET_INFO:                      info->setinfo = CPU_SET_INFO_NAME(mips3);           break;
2297      case CPUINFO_FCT_INIT:                          /* provided per-CPU */                  break;
2298      case CPUINFO_FCT_RESET:                         info->reset = CPU_RESET_NAME(mips3);                break;
2299      case CPUINFO_FCT_EXECUTE:                       info->execute = CPU_EXECUTE_NAME(mips3);            break;
2300      case CPUINFO_FCT_DISASSEMBLE:                   info->disassemble = CPU_DISASSEMBLE_NAME(mips3);            break;
2301      case CPUINFO_FCT_TRANSLATE:                     info->translate = CPU_TRANSLATE_NAME(mips3);        break;
2302
2303      /* --- the following bits of info are returned as NULL-terminated strings --- */
2304      case CPUINFO_STR_SOURCE_FILE:                       strcpy(info->s, __FILE__);              break;
2305
2306      /* --- everything else is handled generically --- */
2307      default:                                        mips3com_get_info(&mips3.core, state, info); break;
2308   }
2309}
2310
2311
2312
2313/***************************************************************************
2314    NEC VR4300 VARIANTS
2315***************************************************************************/
2316
2317// NEC VR4300 series is MIPS III with 32-bit address bus and slightly custom COP0/TLB
2318static CPU_INIT( vr4300be )
2319{
2320   mips3com_init(&mips3.core, MIPS3_TYPE_VR4300, TRUE, device, irqcallback);
2321   mips3.tlb_table = vtlb_table(mips3.core.vtlb);
2322}
2323
2324static CPU_INIT( vr4300le )
2325{
2326   mips3com_init(&mips3.core, MIPS3_TYPE_VR4300, FALSE, device, irqcallback);
2327   mips3.tlb_table = vtlb_table(mips3.core.vtlb);
2328}
2329
2330CPU_GET_INFO( vr4300be_int )
2331{
2332   switch (state)
2333   {
2334      /* --- the following bits of info are returned as 64-bit signed integers --- */
2335      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_BIG;                   break;
2336
2337      /* --- the following bits of info are returned as pointers to data or functions --- */
2338      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(vr4300be);               break;
2339
2340      /* --- the following bits of info are returned as NULL-terminated strings --- */
2341      case CPUINFO_STR_NAME:                          strcpy(info->s, "VR4300 (big)");            break;
2342      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "vr4300be");            break;
2343
2344      /* --- everything else is handled generically --- */
2345      default:                                        CPU_GET_INFO_CALL(mips3);           break;
2346   }
2347}
2348
2349CPU_GET_INFO( vr4300le_int )
2350{
2351   switch (state)
2352   {
2353      /* --- the following bits of info are returned as 64-bit signed integers --- */
2354      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_LITTLE;                    break;
2355
2356      /* --- the following bits of info are returned as pointers to data or functions --- */
2357      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(vr4300le);               break;
2358
2359      /* --- the following bits of info are returned as NULL-terminated strings --- */
2360      case CPUINFO_STR_NAME:                          strcpy(info->s, "VR4300 (little)");     break;
2361      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "vr4300le");            break;
2362
2363      /* --- everything else is handled generically --- */
2364      default:                                        CPU_GET_INFO_CALL(mips3);           break;
2365   }
2366}
2367
2368// VR4310 = VR4300 with different speed bin
2369CPU_GET_INFO( vr4310be_int )
2370{
2371   switch (state)
2372   {
2373      /* --- the following bits of info are returned as 64-bit signed integers --- */
2374      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_BIG;                   break;
2375
2376      /* --- the following bits of info are returned as pointers to data or functions --- */
2377      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(vr4300be);               break;
2378
2379      /* --- the following bits of info are returned as NULL-terminated strings --- */
2380      case CPUINFO_STR_NAME:                          strcpy(info->s, "VR4310 (big)");            break;
2381      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "vr4310be");            break;
2382
2383      /* --- everything else is handled generically --- */
2384      default:                                        CPU_GET_INFO_CALL(mips3);           break;
2385   }
2386}
2387
2388CPU_GET_INFO( vr4310le_int )
2389{
2390   switch (state)
2391   {
2392      /* --- the following bits of info are returned as 64-bit signed integers --- */
2393      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_LITTLE;                    break;
2394
2395      /* --- the following bits of info are returned as pointers to data or functions --- */
2396      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(vr4300le);               break;
2397
2398      /* --- the following bits of info are returned as NULL-terminated strings --- */
2399      case CPUINFO_STR_NAME:                          strcpy(info->s, "VR4310 (little)");     break;
2400      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "vr4310le");            break;
2401
2402      /* --- everything else is handled generically --- */
2403      default:                                        CPU_GET_INFO_CALL(mips3);           break;
2404   }
2405}
2406
2407
2408/***************************************************************************
2409    R4600 VARIANTS
2410***************************************************************************/
2411
2412static CPU_INIT( r4600be )
2413{
2414   mips3com_init(&mips3.core, MIPS3_TYPE_R4600, TRUE, device, irqcallback);
2415   mips3.tlb_table = vtlb_table(mips3.core.vtlb);
2416}
2417
2418static CPU_INIT( r4600le )
2419{
2420   mips3com_init(&mips3.core, MIPS3_TYPE_R4600, FALSE, device, irqcallback);
2421   mips3.tlb_table = vtlb_table(mips3.core.vtlb);
2422}
2423
2424CPU_GET_INFO( r4600be_int )
2425{
2426   switch (state)
2427   {
2428      /* --- the following bits of info are returned as 64-bit signed integers --- */
2429      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_BIG;                   break;
2430
2431      /* --- the following bits of info are returned as pointers to data or functions --- */
2432      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(r4600be);                break;
2433
2434      /* --- the following bits of info are returned as NULL-terminated strings --- */
2435      case CPUINFO_STR_NAME:                          strcpy(info->s, "R4600 (big)");         break;
2436      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "r4600be");            break;
2437
2438      /* --- everything else is handled generically --- */
2439      default:                                        CPU_GET_INFO_CALL(mips3);           break;
2440   }
2441}
2442
2443CPU_GET_INFO( r4600le_int )
2444{
2445   switch (state)
2446   {
2447      /* --- the following bits of info are returned as 64-bit signed integers --- */
2448      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_LITTLE;                    break;
2449
2450      /* --- the following bits of info are returned as pointers to data or functions --- */
2451      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(r4600le);                break;
2452
2453      /* --- the following bits of info are returned as NULL-terminated strings --- */
2454      case CPUINFO_STR_NAME:                          strcpy(info->s, "R4600 (little)");      break;
2455      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "r4600le");            break;
2456
2457      /* --- everything else is handled generically --- */
2458      default:                                        CPU_GET_INFO_CALL(mips3);           break;
2459   }
2460}
2461
2462
2463
2464/***************************************************************************
2465    R4650 VARIANTS
2466***************************************************************************/
2467
2468static CPU_INIT( r4650be )
2469{
2470   mips3com_init(&mips3.core, MIPS3_TYPE_R4650, TRUE, device, irqcallback);
2471   mips3.tlb_table = vtlb_table(mips3.core.vtlb);
2472}
2473
2474static CPU_INIT( r4650le )
2475{
2476   mips3com_init(&mips3.core, MIPS3_TYPE_R4650, FALSE, device, irqcallback);
2477   mips3.tlb_table = vtlb_table(mips3.core.vtlb);
2478}
2479
2480CPU_GET_INFO( r4650be_int )
2481{
2482   switch (state)
2483   {
2484      /* --- the following bits of info are returned as 64-bit signed integers --- */
2485      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_BIG;                   break;
2486
2487      /* --- the following bits of info are returned as pointers to data or functions --- */
2488      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(r4650be);                break;
2489
2490      /* --- the following bits of info are returned as NULL-terminated strings --- */
2491      case CPUINFO_STR_NAME:                          strcpy(info->s, "IDT R4650 (big)");     break;
2492      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "r4650be");            break;
2493
2494      /* --- everything else is handled generically --- */
2495      default:                                        CPU_GET_INFO_CALL(mips3);           break;
2496   }
2497}
2498
2499CPU_GET_INFO( r4650le_int )
2500{
2501   switch (state)
2502   {
2503      /* --- the following bits of info are returned as 64-bit signed integers --- */
2504      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_LITTLE;                    break;
2505
2506      /* --- the following bits of info are returned as pointers to data or functions --- */
2507      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(r4650le);                break;
2508
2509      /* --- the following bits of info are returned as NULL-terminated strings --- */
2510      case CPUINFO_STR_NAME:                          strcpy(info->s, "IDT R4650 (little)");  break;
2511      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "r4650le");            break;
2512
2513      /* --- everything else is handled generically --- */
2514      default:                                        CPU_GET_INFO_CALL(mips3);           break;
2515   }
2516}
2517
2518
2519
2520/***************************************************************************
2521    R4700 VARIANTS
2522***************************************************************************/
2523
2524static CPU_INIT( r4700be )
2525{
2526   mips3com_init(&mips3.core, MIPS3_TYPE_R4700, TRUE, device, irqcallback);
2527   mips3.tlb_table = vtlb_table(mips3.core.vtlb);
2528}
2529
2530static CPU_INIT( r4700le )
2531{
2532   mips3com_init(&mips3.core, MIPS3_TYPE_R4700, FALSE, device, irqcallback);
2533   mips3.tlb_table = vtlb_table(mips3.core.vtlb);
2534}
2535
2536CPU_GET_INFO( r4700be_int )
2537{
2538   switch (state)
2539   {
2540      /* --- the following bits of info are returned as 64-bit signed integers --- */
2541      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_BIG;                   break;
2542
2543      /* --- the following bits of info are returned as pointers to data or functions --- */
2544      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(r4700be);                break;
2545
2546      /* --- the following bits of info are returned as NULL-terminated strings --- */
2547      case CPUINFO_STR_NAME:                          strcpy(info->s, "R4700 (big)");         break;
2548      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "r4700be");            break;
2549
2550      /* --- everything else is handled generically --- */
2551      default:                                        CPU_GET_INFO_CALL(mips3);           break;
2552   }
2553}
2554
2555
2556CPU_GET_INFO( r4700le_int )
2557{
2558   switch (state)
2559   {
2560      /* --- the following bits of info are returned as 64-bit signed integers --- */
2561      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_LITTLE;                    break;
2562
2563      /* --- the following bits of info are returned as pointers to data or functions --- */
2564      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(r4700le);                break;
2565
2566      /* --- the following bits of info are returned as NULL-terminated strings --- */
2567      case CPUINFO_STR_NAME:                          strcpy(info->s, "R4700 (little)");      break;
2568      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "r4700le");            break;
2569
2570      /* --- everything else is handled generically --- */
2571      default:                                        CPU_GET_INFO_CALL(mips3);           break;
2572   }
2573}
2574
2575
2576
2577/***************************************************************************
2578    R5000 VARIANTS
2579***************************************************************************/
2580
2581static CPU_INIT( r5000be )
2582{
2583   mips3com_init(&mips3.core, MIPS3_TYPE_R5000, TRUE, device, irqcallback);
2584   mips3.tlb_table = vtlb_table(mips3.core.vtlb);
2585}
2586
2587static CPU_INIT( r5000le )
2588{
2589   mips3com_init(&mips3.core, MIPS3_TYPE_R5000, FALSE, device, irqcallback);
2590   mips3.tlb_table = vtlb_table(mips3.core.vtlb);
2591}
2592
2593CPU_GET_INFO( r5000be_int )
2594{
2595   switch (state)
2596   {
2597      /* --- the following bits of info are returned as 64-bit signed integers --- */
2598      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_BIG;                   break;
2599
2600      /* --- the following bits of info are returned as pointers to data or functions --- */
2601      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(r5000be);                break;
2602
2603      /* --- the following bits of info are returned as NULL-terminated strings --- */
2604      case CPUINFO_STR_NAME:                          strcpy(info->s, "R5000 (big)");         break;
2605      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "r5000be");            break;
2606
2607      /* --- everything else is handled generically --- */
2608      default:                                        CPU_GET_INFO_CALL(mips3);           break;
2609   }
2610}
2611
2612CPU_GET_INFO( r5000le_int )
2613{
2614   switch (state)
2615   {
2616      /* --- the following bits of info are returned as 64-bit signed integers --- */
2617      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_LITTLE;                    break;
2618
2619      /* --- the following bits of info are returned as pointers to data or functions --- */
2620      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(r5000le);                break;
2621
2622      /* --- the following bits of info are returned as NULL-terminated strings --- */
2623      case CPUINFO_STR_NAME:                          strcpy(info->s, "R5000 (little)");      break;
2624      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "r5000le");            break;
2625
2626      /* --- everything else is handled generically --- */
2627      default:                                        CPU_GET_INFO_CALL(mips3);           break;
2628   }
2629}
2630
2631
2632
2633/***************************************************************************
2634    QED5271 VARIANTS
2635***************************************************************************/
2636
2637static CPU_INIT( qed5271be )
2638{
2639   mips3com_init(&mips3.core, MIPS3_TYPE_QED5271, TRUE, device, irqcallback);
2640   mips3.tlb_table = vtlb_table(mips3.core.vtlb);
2641}
2642
2643static CPU_INIT( qed5271le )
2644{
2645   mips3com_init(&mips3.core, MIPS3_TYPE_QED5271, FALSE, device, irqcallback);
2646   mips3.tlb_table = vtlb_table(mips3.core.vtlb);
2647}
2648
2649CPU_GET_INFO( qed5271be_int )
2650{
2651   switch (state)
2652   {
2653      /* --- the following bits of info are returned as 64-bit signed integers --- */
2654      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_BIG;                   break;
2655
2656      /* --- the following bits of info are returned as pointers to data or functions --- */
2657      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(qed5271be);          break;
2658
2659      /* --- the following bits of info are returned as NULL-terminated strings --- */
2660      case CPUINFO_STR_NAME:                          strcpy(info->s, "QED5271 (big)");       break;
2661      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "qed5271be");            break;
2662
2663      /* --- everything else is handled generically --- */
2664      default:                                        CPU_GET_INFO_CALL(mips3);           break;
2665   }
2666}
2667
2668CPU_GET_INFO( qed5271le_int )
2669{
2670   switch (state)
2671   {
2672      /* --- the following bits of info are returned as 64-bit signed integers --- */
2673      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_LITTLE;                    break;
2674
2675      /* --- the following bits of info are returned as pointers to data or functions --- */
2676      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(qed5271le);          break;
2677
2678      /* --- the following bits of info are returned as NULL-terminated strings --- */
2679      case CPUINFO_STR_NAME:                          strcpy(info->s, "QED5271 (little)");    break;
2680      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "qed5271le");            break;
2681
2682      /* --- everything else is handled generically --- */
2683      default:                                        CPU_GET_INFO_CALL(mips3);           break;
2684   }
2685}
2686
2687
2688
2689/***************************************************************************
2690    RM7000 VARIANTS
2691***************************************************************************/
2692
2693static CPU_INIT( rm7000be )
2694{
2695   mips3com_init(&mips3.core, MIPS3_TYPE_RM7000, TRUE, device, irqcallback);
2696   mips3.tlb_table = vtlb_table(mips3.core.vtlb);
2697}
2698
2699static CPU_INIT( rm7000le )
2700{
2701   mips3com_init(&mips3.core, MIPS3_TYPE_RM7000, FALSE, device, irqcallback);
2702   mips3.tlb_table = vtlb_table(mips3.core.vtlb);
2703}
2704
2705CPU_GET_INFO( rm7000be_int )
2706{
2707   switch (state)
2708   {
2709      /* --- the following bits of info are returned as 64-bit signed integers --- */
2710      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_BIG;                   break;
2711
2712      /* --- the following bits of info are returned as pointers to data or functions --- */
2713      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(rm7000be);               break;
2714
2715      /* --- the following bits of info are returned as NULL-terminated strings --- */
2716      case CPUINFO_STR_NAME:                          strcpy(info->s, "RM7000 (big)");        break;
2717      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "rm7000be");            break;
2718
2719      /* --- everything else is handled generically --- */
2720      default:                                        CPU_GET_INFO_CALL(mips3);           break;
2721   }
2722}
2723
2724CPU_GET_INFO( rm7000le_int )
2725{
2726   switch (state)
2727   {
2728      /* --- the following bits of info are returned as 64-bit signed integers --- */
2729      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_LITTLE;                    break;
2730
2731      /* --- the following bits of info are returned as pointers to data or functions --- */
2732      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(rm7000le);               break;
2733
2734      /* --- the following bits of info are returned as NULL-terminated strings --- */
2735      case CPUINFO_STR_NAME:                          strcpy(info->s, "RM7000 (little)");     break;
2736      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "rm7000le");            break;
2737
2738      /* --- everything else is handled generically --- */
2739      default:                                        CPU_GET_INFO_CALL(mips3);           break;
2740   }
2741}
2742
2743DEFINE_LEGACY_CPU_DEVICE(VR4300BE_INT, vr4300be_int);
2744DEFINE_LEGACY_CPU_DEVICE(VR4300LE_INT, vr4300le_int);
2745DEFINE_LEGACY_CPU_DEVICE(VR4310BE_INT, vr4310be_int);
2746DEFINE_LEGACY_CPU_DEVICE(VR4310LE_INT, vr4310le_int);
2747
2748DEFINE_LEGACY_CPU_DEVICE(R4600BE_INT, r4600be_int);
2749DEFINE_LEGACY_CPU_DEVICE(R4600LE_INT, r4600le_int);
2750
2751DEFINE_LEGACY_CPU_DEVICE(R4650BE_INT, r4650be_int);
2752DEFINE_LEGACY_CPU_DEVICE(R4650LE_INT, r4650le_int);
2753
2754DEFINE_LEGACY_CPU_DEVICE(R4700BE_INT, r4700be_int);
2755DEFINE_LEGACY_CPU_DEVICE(R4700LE_INT, r4700le_int);
2756
2757DEFINE_LEGACY_CPU_DEVICE(R5000BE_INT, r5000be_int);
2758DEFINE_LEGACY_CPU_DEVICE(R5000LE_INT, r5000le_int);
2759
2760DEFINE_LEGACY_CPU_DEVICE(QED5271BE_INT, qed5271be_int);
2761DEFINE_LEGACY_CPU_DEVICE(QED5271LE_INT, qed5271le_int);
2762
2763DEFINE_LEGACY_CPU_DEVICE(RM7000BE_INT, rm7000be_int);
2764DEFINE_LEGACY_CPU_DEVICE(RM7000LE_INT, rm7000le_int);
2765
2766const device_type VR4300BE = &legacy_device_creator_drc<vr4300be_int_device, vr4300be_drc_device>;
2767const device_type VR4300LE = &legacy_device_creator_drc<vr4300le_int_device, vr4300le_drc_device>;
2768const device_type VR4310BE = &legacy_device_creator_drc<vr4310be_int_device, vr4310be_drc_device>;
2769const device_type VR4310LE = &legacy_device_creator_drc<vr4310le_int_device, vr4310le_drc_device>;
2770const device_type R4600BE = &legacy_device_creator_drc<r4600be_int_device, r4600be_drc_device>;
2771const device_type R4600LE = &legacy_device_creator_drc<r4600le_int_device, r4600le_drc_device>;
2772const device_type R4650BE = &legacy_device_creator_drc<r4650be_int_device, r4650be_drc_device>;
2773const device_type R4650LE = &legacy_device_creator_drc<r4650le_int_device, r4650le_drc_device>;
2774const device_type R4700BE = &legacy_device_creator_drc<r4700be_int_device, r4700be_drc_device>;
2775const device_type R4700LE = &legacy_device_creator_drc<r4700le_int_device, r4700le_drc_device>;
2776const device_type R5000BE = &legacy_device_creator_drc<r5000be_int_device, r5000be_drc_device>;
2777const device_type R5000LE = &legacy_device_creator_drc<r5000le_int_device, r5000le_drc_device>;
2778const device_type QED5271BE = &legacy_device_creator_drc<qed5271be_int_device, qed5271be_drc_device>;
2779const device_type QED5271LE = &legacy_device_creator_drc<qed5271le_int_device, qed5271le_drc_device>;
2780const device_type RM7000BE = &legacy_device_creator_drc<rm7000be_int_device, rm7000be_drc_device>;
2781const device_type RM7000LE = &legacy_device_creator_drc<rm7000le_int_device, rm7000le_drc_device>;
trunk/src/emu/cpu/mips/mips3fe.h
r30757r30758
1313#ifndef __MIPS3FE_H__
1414#define __MIPS3FE_H__
1515
16#include "mips3com.h"
17#include "cpu/drcfe.h"
1816
19
2017//**************************************************************************
2118//  MACROS
2219//**************************************************************************
r30757r30758
3330#define REGFLAG_FCC                     (1 << 2)
3431
3532
36
37//**************************************************************************
38//  TYPE DEFINITIONS
39//**************************************************************************
40
41class mips3_frontend : public drc_frontend
42{
43public:
44   // construction/destruction
45   mips3_frontend(mips3_state &state, UINT32 window_start, UINT32 window_end, UINT32 max_sequence);
46
47protected:
48   // required overrides
49   virtual bool describe(opcode_desc &desc, const opcode_desc *prev);
50
51private:
52   // internal helpers
53   bool describe_special(UINT32 op, opcode_desc &desc);
54   bool describe_regimm(UINT32 op, opcode_desc &desc);
55   bool describe_idt(UINT32 op, opcode_desc &desc);
56   bool describe_cop0(UINT32 op, opcode_desc &desc);
57   bool describe_cop1(UINT32 op, opcode_desc &desc);
58   bool describe_cop1x(UINT32 op, opcode_desc &desc);
59   bool describe_cop2(UINT32 op, opcode_desc &desc);
60
61   // internal state
62   mips3_state &m_context;
63};
64
65
6633#endif /* __MIPS3FE_H__ */
trunk/src/emu/cpu/mips/mips3com.h
r30757r30758
1616
1717
1818/***************************************************************************
19    DEBUGGING
20***************************************************************************/
21
22#define PRINTF_TLB              (0)
23#define USE_ABI_REG_NAMES       (1)
24
25#define LOG_UML                         (0)
26#define LOG_NATIVE                      (0)
27
28#define DISABLE_FAST_REGISTERS          (0)
29#define SINGLE_INSTRUCTION_MODE         (0)
30
31#define PRINTF_EXCEPTIONS               (0)
32#define PRINTF_MMU                      (0)
33
34#define PROBE_ADDRESS                   ~0
35
36
37/***************************************************************************
1938    CONSTANTS
2039***************************************************************************/
2140
41/* map variables */
42#define MAPVAR_PC                       M0
43#define MAPVAR_CYCLES                   M1
44
45/* modes */
46#define MODE_KERNEL                     0
47#define MODE_SUPER                      1
48#define MODE_USER                       2
49
50/* compilation boundaries -- how far back/forward does the analysis extend? */
51#define COMPILE_BACKWARDS_BYTES         128
52#define COMPILE_FORWARDS_BYTES          512
53#define COMPILE_MAX_INSTRUCTIONS        ((COMPILE_BACKWARDS_BYTES/4) + (COMPILE_FORWARDS_BYTES/4))
54#define COMPILE_MAX_SEQUENCE            64
55
56/* exit codes */
57#define EXECUTE_OUT_OF_CYCLES           0
58#define EXECUTE_MISSING_CODE            1
59#define EXECUTE_UNMAPPED_CODE           2
60#define EXECUTE_RESET_CACHE             3
61
62
63
64#define LOPTR(x)                ((UINT32 *)(x) + NATIVE_ENDIAN_VALUE_LE_BE(0,1))
65
66
67/***************************************************************************
68    CONSTANTS
69***************************************************************************/
70
2271/* core parameters */
2372#define MIPS3_MIN_PAGE_SHIFT        12
2473#define MIPS3_MIN_PAGE_SIZE         (1 << MIPS3_MIN_PAGE_SHIFT)
2574#define MIPS3_MIN_PAGE_MASK         (MIPS3_MIN_PAGE_SIZE - 1)
2675#define MIPS3_MAX_PADDR_SHIFT       32
27#define MIPS3_MAX_TLB_ENTRIES       48
2876
2977/* cycle parameters */
3078#define MIPS3_COUNT_READ_CYCLES     250
3179#define MIPS3_CAUSE_READ_CYCLES     250
3280
33/* MIPS flavors */
34enum mips3_flavor
35{
36   /* MIPS III variants */
37   MIPS3_TYPE_MIPS_III,
38   MIPS3_TYPE_VR4300,
39   MIPS3_TYPE_R4600,
40   MIPS3_TYPE_R4650,
41   MIPS3_TYPE_R4700,
42
43   /* MIPS IV variants */
44   MIPS3_TYPE_MIPS_IV,
45   MIPS3_TYPE_R5000,
46   MIPS3_TYPE_QED5271,
47   MIPS3_TYPE_RM7000
48};
49
5081/* TLB bits */
5182#define TLB_GLOBAL              0x01
5283#define TLB_VALID               0x02
r30757r30758
158189#define LIMMVAL         (op & 0x03ffffff)
159190
160191
161
162/***************************************************************************
163    STRUCTURES & TYPEDEFS
164***************************************************************************/
165
166/* MIPS3 TLB entry */
167struct mips3_tlb_entry
168{
169   UINT64          page_mask;
170   UINT64          entry_hi;
171   UINT64          entry_lo[2];
172};
173
174
175/* forward declaration of implementation-specific state */
176struct mips3imp_state;
177
178
179/* MIPS3 state */
180struct mips3_state
181{
182   /* core registers */
183   UINT32          pc;
184   int             icount;
185   UINT64          r[35];
186
187   /* COP registers */
188   UINT64          cpr[3][32];
189   UINT64          ccr[3][32];
190   UINT32          llbit;
191
192   /* internal stuff */
193   mips3_flavor    flavor;
194   device_irq_acknowledge_delegate irq_callback;
195   legacy_cpu_device * device;
196   address_space *program;
197   direct_read_data *direct;
198   UINT32          system_clock;
199   UINT32          cpu_clock;
200   UINT64          count_zero_time;
201   UINT32          compare_armed;
202   emu_timer *     compare_int_timer;
203
204   /* derived info based on flavor */
205   UINT32          pfnmask;
206   UINT8           tlbentries;
207
208   /* memory accesses */
209   UINT8           bigendian;
210   data_accessors  memory;
211
212   /* cache memory */
213   size_t          icache_size;
214   size_t          dcache_size;
215
216   /* MMU */
217   vtlb_state *    vtlb;
218   mips3_tlb_entry tlb[MIPS3_MAX_TLB_ENTRIES];
219
220   /* for use by specific implementations */
221   mips3imp_state *impstate;
222};
223
224
225
226/***************************************************************************
227    FUNCTION PROTOTYPES
228***************************************************************************/
229
230void mips3com_init(mips3_state *mips, mips3_flavor flavor, int bigendian, legacy_cpu_device *device, device_irq_acknowledge_delegate irqcallback);
231void mips3com_exit(mips3_state *mips);
232
233void mips3com_reset(mips3_state *mips);
234offs_t mips3com_dasm(mips3_state *mips, char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram);
235void mips3com_update_cycle_counting(mips3_state *mips);
236
237void mips3com_asid_changed(mips3_state *mips);
238int mips3com_translate_address(mips3_state *mips, address_spacenum space, int intention, offs_t *address);
239void mips3com_tlbr(mips3_state *mips);
240void mips3com_tlbwi(mips3_state *mips);
241void mips3com_tlbwr(mips3_state *mips);
242void mips3com_tlbp(mips3_state *mips);
243
244void mips3com_set_info(mips3_state *mips, UINT32 state, cpuinfo *info);
245void mips3com_get_info(mips3_state *mips, UINT32 state, cpuinfo *info);
246
247
248
249/***************************************************************************
250    INLINE FUNCTIONS
251***************************************************************************/
252
253/*-------------------------------------------------
254    mips3com_set_irq_line - set or clear the given
255    IRQ line
256-------------------------------------------------*/
257
258INLINE void mips3com_set_irq_line(mips3_state *mips, int irqline, int state)
259{
260   if (state != CLEAR_LINE)
261      mips->cpr[0][COP0_Cause] |= 0x400 << irqline;
262   else
263      mips->cpr[0][COP0_Cause] &= ~(0x400 << irqline);
264}
265
266192#endif /* __MIPS3COM_H__ */
trunk/src/emu/cpu/mips/mips3.h
r30757r30758
1515#define __MIPS3_H__
1616
1717
18#include "cpu/vtlb.h"
19#include "cpu/drcfe.h"
20#include "cpu/drcuml.h"
21#include "cpu/drcumlsh.h"
1822
23
24// NEC VR4300 series is MIPS III with 32-bit address bus and slightly custom COP0/TLB
25extern const device_type VR4300BE;
26extern const device_type VR4300LE;
27// VR4310 = VR4300 with different speed bin
28extern const device_type VR4310BE;
29extern const device_type VR4310LE;
30extern const device_type R4600BE;
31extern const device_type R4600LE;
32extern const device_type R4650BE;
33extern const device_type R4650LE;
34extern const device_type R4700BE;
35extern const device_type R4700LE;
36extern const device_type R5000BE;
37extern const device_type R5000LE;
38extern const device_type QED5271BE;
39extern const device_type QED5271LE;
40extern const device_type RM7000BE;
41extern const device_type RM7000LE;
42
43
1944/***************************************************************************
2045    REGISTER ENUMERATION
2146***************************************************************************/
r30757r30758
208233    STRUCTURES
209234***************************************************************************/
210235
211struct mips3_config
236/* MIPS3 TLB entry */
237struct mips3_tlb_entry
212238{
213   size_t      icache;                         /* code cache size */
214   size_t      dcache;                         /* data cache size */
215   UINT32      system_clock;                   /* system clock rate */
239   UINT64          page_mask;
240   UINT64          entry_hi;
241   UINT64          entry_lo[2];
216242};
217243
244/* internal compiler state */
245struct compiler_state
246{
247   UINT32              cycles;                     /* accumulated cycles */
248   UINT8               checkints;                  /* need to check interrupts before next instruction */
249   UINT8               checksoftints;              /* need to check software interrupts before next instruction */
250   uml::code_label  labelnum;                   /* index for local labels */
251};
218252
253#define MIPS3_MAX_TLB_ENTRIES       48
219254
220/***************************************************************************
221    PUBLIC FUNCTIONS
222***************************************************************************/
255#define MCFG_MIPS3_ICACHE_SIZE(_size) \
256   mips3_device::set_icache_size(*device, _size);
223257
224void mips3drc_set_options(device_t *device, UINT32 options);
225void mips3drc_add_fastram(device_t *device, offs_t start, offs_t end, UINT8 readonly, void *base);
226void mips3drc_add_hotspot(device_t *device, offs_t pc, UINT32 opcode, UINT32 cycles);
258#define MCFG_MIPS3_DCACHE_SIZE(_size) \
259   mips3_device::set_dcache_size(*device, _size);
227260
228DECLARE_LEGACY_CPU_DEVICE(VR4300BE_INT, vr4300be_int);
229DECLARE_LEGACY_CPU_DEVICE(VR4300LE_INT, vr4300le_int);
230DECLARE_LEGACY_CPU_DEVICE(VR4310BE_INT, vr4310be_int);
231DECLARE_LEGACY_CPU_DEVICE(VR4310LE_INT, vr4310le_int);
261#define MCFG_MIPS3_SYSTEM_CLOCK(_clock) \
262   mips3_device::set_system_clock(*device, _clock);
232263
233DECLARE_LEGACY_CPU_DEVICE(R4600BE_INT, r4600be_int);
234DECLARE_LEGACY_CPU_DEVICE(R4600LE_INT, r4600le_int);
235264
236DECLARE_LEGACY_CPU_DEVICE(R4650BE_INT, r4650be_int);
237DECLARE_LEGACY_CPU_DEVICE(R4650LE_INT, r4650le_int);
265class mips3_frontend;
238266
239DECLARE_LEGACY_CPU_DEVICE(R4700BE_INT, r4700be_int);
240DECLARE_LEGACY_CPU_DEVICE(R4700LE_INT, r4700le_int);
267class mips3_device : public cpu_device
268{
269   friend class mips3_frontend;
241270
242DECLARE_LEGACY_CPU_DEVICE(R5000BE_INT, r5000be_int);
243DECLARE_LEGACY_CPU_DEVICE(R5000LE_INT, r5000le_int);
271protected:
272   /* MIPS flavors */
273   enum mips3_flavor
274   {
275      /* MIPS III variants */
276      MIPS3_TYPE_MIPS_III,
277      MIPS3_TYPE_VR4300,
278      MIPS3_TYPE_R4600,
279      MIPS3_TYPE_R4650,
280      MIPS3_TYPE_R4700,
244281
245DECLARE_LEGACY_CPU_DEVICE(QED5271BE_INT, qed5271be_int);
246DECLARE_LEGACY_CPU_DEVICE(QED5271LE_INT, qed5271le_int);
282      /* MIPS IV variants */
283      MIPS3_TYPE_MIPS_IV,
284      MIPS3_TYPE_R5000,
285      MIPS3_TYPE_QED5271,
286      MIPS3_TYPE_RM7000
287   };
247288
248DECLARE_LEGACY_CPU_DEVICE(RM7000BE_INT, rm7000be_int);
249DECLARE_LEGACY_CPU_DEVICE(RM7000LE_INT, rm7000le_int);
289public:
290   // construction/destruction
291   mips3_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, mips3_flavor flavor, endianness_t endiannes);
250292
251DECLARE_LEGACY_CPU_DEVICE(VR4300BE_DRC, vr4300be_drc);
252DECLARE_LEGACY_CPU_DEVICE(VR4300LE_DRC, vr4300le_drc);
253DECLARE_LEGACY_CPU_DEVICE(VR4310BE_DRC, vr4310be_drc);
254DECLARE_LEGACY_CPU_DEVICE(VR4310LE_DRC, vr4310le_drc);
293   static void set_icache_size(device_t &device, size_t icache_size) { downcast<mips3_device &>(device).c_icache_size = icache_size; }
294   static void set_dcache_size(device_t &device, size_t dcache_size) { downcast<mips3_device &>(device).c_dcache_size = dcache_size; }
295   static void set_system_clock(device_t &device, UINT32 system_clock) { downcast<mips3_device &>(device).c_system_clock = system_clock; }
255296
256DECLARE_LEGACY_CPU_DEVICE(R4600BE_DRC, r4600be_drc);
257DECLARE_LEGACY_CPU_DEVICE(R4600LE_DRC, r4600le_drc);
297   TIMER_CALLBACK_MEMBER(compare_int_callback);
258298
259DECLARE_LEGACY_CPU_DEVICE(R4650BE_DRC, r4650be_drc);
260DECLARE_LEGACY_CPU_DEVICE(R4650LE_DRC, r4650le_drc);
299   void mips3drc_set_options(UINT32 options);
300   void mips3drc_add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base);
301   void mips3drc_add_hotspot(offs_t pc, UINT32 opcode, UINT32 cycles);
261302
262DECLARE_LEGACY_CPU_DEVICE(R4700BE_DRC, r4700be_drc);
263DECLARE_LEGACY_CPU_DEVICE(R4700LE_DRC, r4700le_drc);
303protected:
304   // device-level overrides
305   virtual void device_start();
306   virtual void device_reset();
307   virtual void device_stop();
264308
265DECLARE_LEGACY_CPU_DEVICE(R5000BE_DRC, r5000be_drc);
266DECLARE_LEGACY_CPU_DEVICE(R5000LE_DRC, r5000le_drc);
309   // device_execute_interface overrides
310   virtual UINT32 execute_min_cycles() const { return 1; }
311   virtual UINT32 execute_max_cycles() const { return 40; }
312   virtual UINT32 execute_input_lines() const { return 6; }
313   virtual void execute_run();
314   virtual void execute_set_input(int inputnum, int state);
267315
268DECLARE_LEGACY_CPU_DEVICE(QED5271BE_DRC, qed5271be_drc);
269DECLARE_LEGACY_CPU_DEVICE(QED5271LE_DRC, qed5271le_drc);
316   // device_memory_interface overrides
317   virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
318   virtual bool memory_translate(address_spacenum spacenum, int intention, offs_t &address);
270319
271DECLARE_LEGACY_CPU_DEVICE(RM7000BE_DRC, rm7000be_drc);
272DECLARE_LEGACY_CPU_DEVICE(RM7000LE_DRC, rm7000le_drc);
320   // device_state_interface overrides
321   virtual void state_export(const device_state_entry &entry);
322   void state_string_export(const device_state_entry &entry, astring &string);
273323
274extern const device_type VR4300BE;
275extern const device_type VR4300LE;
276extern const device_type VR4310BE;
277extern const device_type VR4310LE;
278extern const device_type R4600BE;
279extern const device_type R4600LE;
280extern const device_type R4650BE;
281extern const device_type R4650LE;
282extern const device_type R4700BE;
283extern const device_type R4700LE;
284extern const device_type R5000BE;
285extern const device_type R5000LE;
286extern const device_type QED5271BE;
287extern const device_type QED5271LE;
288extern const device_type RM7000BE;
289extern const device_type RM7000LE;
324   // device_disasm_interface overrides
325   virtual UINT32 disasm_min_opcode_bytes() const { return 4; }
326   virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
327   virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
290328
329private:
330   struct internal_mips3_state
331   {
332      /* core registers */
333      UINT32          pc;
334      int             icount;
335      UINT64          r[35];
291336
337      /* COP registers */
338      UINT64          cpr[3][32];
339      UINT64          ccr[3][32];
340      UINT32          llbit;
341
342      UINT32          mode;                       /* current global mode */
343
344      /* parameters for subroutines */
345      UINT64          numcycles;                  /* return value from gettotalcycles */
346      const char *    format;                     /* format string for print_debug */
347      UINT32          arg0;                       /* print_debug argument 1 */
348      UINT32          arg1;                       /* print_debug argument 2 */
349
350      UINT64          count_zero_time;
351      UINT32          compare_armed;
352      UINT32          jmpdest;                    /* destination jump target */
353
354   };
355
356   address_space_config m_program_config;
357   mips3_flavor m_flavor;
358
359   /* core state */
360   internal_mips3_state *m_core;
361
362    /* internal stuff */
363   UINT32      m_ppc;
364   UINT32      m_nextpc;
365   UINT32      m_pcbase;
366   UINT8       m_cf[4][8];
367   int         m_op;
368   int         m_interrupt_cycles;
369   UINT32      m_ll_value;
370   UINT64      m_lld_value;
371   UINT32      m_badcop_value;
372   const vtlb_entry *m_tlb_table;
373
374   /* endian-dependent load/store */
375   typedef void (mips3_device::*loadstore_func)(UINT32 op);
376   loadstore_func m_lwl;
377   loadstore_func m_lwr;
378   loadstore_func m_swl;
379   loadstore_func m_swr;
380   loadstore_func m_ldl;
381   loadstore_func m_ldr;
382   loadstore_func m_sdl;
383   loadstore_func m_sdr;
384
385   address_space *m_program;
386   direct_read_data *m_direct;
387   UINT32          c_system_clock;
388   UINT32          m_cpu_clock;
389   emu_timer *     m_compare_int_timer;
390
391   /* derived info based on flavor */
392   UINT32          m_pfnmask;
393   UINT8           m_tlbentries;
394
395   /* memory accesses */
396   bool            m_bigendian;
397   data_accessors  m_memory;
398
399   /* cache memory */
400   size_t          c_icache_size;
401   size_t          c_dcache_size;
402
403   /* MMU */
404   vtlb_state *    m_vtlb;
405   mips3_tlb_entry m_tlb[MIPS3_MAX_TLB_ENTRIES];
406
407   UINT64 m_debugger_temp;
408
409   /* core state */
410   drc_cache           m_cache;                      /* pointer to the DRC code cache */
411   drcuml_state *      m_drcuml;                     /* DRC UML generator state */
412   mips3_frontend *    m_drcfe;                      /* pointer to the DRC front-end state */
413   UINT32              m_drcoptions;                 /* configurable DRC options */
414
415   /* internal stuff */
416   UINT8               m_cache_dirty;                /* true if we need to flush the cache */
417
418   /* tables */
419   UINT8               m_fpmode[4];                  /* FPU mode table */
420
421   /* register mappings */
422   uml::parameter   m_regmap[34];                 /* parameter to register mappings for all 32 integer registers */
423   uml::parameter   m_regmaplo[34];               /* parameter to register mappings for all 32 integer registers */
424
425   /* subroutines */
426   uml::code_handle *   m_entry;                      /* entry point */
427   uml::code_handle *   m_nocode;                     /* nocode exception handler */
428   uml::code_handle *   m_out_of_cycles;              /* out of cycles exception handler */
429   uml::code_handle *   m_tlb_mismatch;               /* tlb mismatch handler */
430   uml::code_handle *   m_read8[3];                   /* read byte */
431   uml::code_handle *   m_write8[3];                  /* write byte */
432   uml::code_handle *   m_read16[3];                  /* read half */
433   uml::code_handle *   m_write16[3];                 /* write half */
434   uml::code_handle *   m_read32[3];                  /* read word */
435   uml::code_handle *   m_read32mask[3];              /* read word masked */
436   uml::code_handle *   m_write32[3];                 /* write word */
437   uml::code_handle *   m_write32mask[3];             /* write word masked */
438   uml::code_handle *   m_read64[3];                  /* read double */
439   uml::code_handle *   m_read64mask[3];              /* read double masked */
440   uml::code_handle *   m_write64[3];                 /* write double */
441   uml::code_handle *   m_write64mask[3];             /* write double masked */
442   uml::code_handle *   m_exception[18/*EXCEPTION_COUNT*/]; /* array of exception handlers */
443   uml::code_handle *   m_exception_norecover[18/*EXCEPTION_COUNT*/];   /* array of no-recover exception handlers */
444
445   /* fast RAM */
446   UINT32              m_fastram_select;
447   struct
448   {
449      offs_t              start;                      /* start of the RAM block */
450      offs_t              end;                        /* end of the RAM block */
451      UINT8               readonly;                   /* TRUE if read-only */
452      void *              base;                       /* base in memory where the RAM lives */
453   }       m_fastram[MIPS3_MAX_FASTRAM];
454
455   /* hotspots */
456   UINT32              m_hotspot_select;
457   struct
458   {
459      offs_t              pc;                         /* PC to consider */
460      UINT32              opcode;                     /* required opcode at that PC */
461      UINT32              cycles;                     /* number of cycles to eat when hit */
462   }       m_hotspot[MIPS3_MAX_HOTSPOTS];
463   bool m_isdrc;
464
465
466   void generate_exception(int exception, int backup);
467   void generate_tlb_exception(int exception, offs_t address);
468   void invalid_instruction(UINT32 op);
469   void check_irqs();
470public:
471   void mips3com_update_cycle_counting();
472   void mips3com_asid_changed();
473   void mips3com_tlbr();
474   void mips3com_tlbwi();
475   void mips3com_tlbwr();
476   void mips3com_tlbp();
477private:
478   UINT32 compute_config_register();
479   UINT32 compute_prid_register();
480   void tlb_map_entry(int tlbindex);
481   void tlb_write_common(int tlbindex);
482   int RBYTE(offs_t address, UINT32 *result);
483   int RHALF(offs_t address, UINT32 *result);
484   int RWORD(offs_t address, UINT32 *result);
485   int RWORD_MASKED(offs_t address, UINT32 *result, UINT32 mem_mask);
486   int RDOUBLE(offs_t address, UINT64 *result);
487   int RDOUBLE_MASKED(offs_t address, UINT64 *result, UINT64 mem_mask);
488   void WBYTE(offs_t address, UINT8 data);
489   void WHALF(offs_t address, UINT16 data);
490   void WWORD(offs_t address, UINT32 data);
491   void WWORD_MASKED(offs_t address, UINT32 data, UINT32 mem_mask);
492   void WDOUBLE(offs_t address, UINT64 data);
493   void WDOUBLE_MASKED(offs_t address, UINT64 data, UINT64 mem_mask);
494   UINT64 get_cop0_reg(int idx);
495   void set_cop0_reg(int idx, UINT64 val);
496   UINT64 get_cop0_creg(int idx);
497   void set_cop0_creg(int idx, UINT64 val);
498   void handle_cop0(UINT32 op);
499   UINT32 get_cop1_reg32(int idx);
500   UINT64 get_cop1_reg64(int idx);
501   void set_cop1_reg32(int idx, UINT32 val);
502   void set_cop1_reg64(int idx, UINT64 val);
503   UINT64 get_cop1_creg(int idx);
504   void set_cop1_creg(int idx, UINT64 val);
505   void handle_cop1_fr0(UINT32 op);
506   void handle_cop1_fr1(UINT32 op);
507   void handle_cop1x_fr0(UINT32 op);
508   void handle_cop1x_fr1(UINT32 op);
509   UINT64 get_cop2_reg(int idx);
510   void set_cop2_reg(int idx, UINT64 val);
511   UINT64 get_cop2_creg(int idx);
512   void set_cop2_creg(int idx, UINT64 val);
513   void handle_cop2(UINT32 op);
514   void lwl_be(UINT32 op);
515   void lwr_be(UINT32 op);
516   void ldl_be(UINT32 op);
517   void ldr_be(UINT32 op);
518   void swl_be(UINT32 op);
519   void swr_be(UINT32 op);
520   void sdl_be(UINT32 op);
521   void sdr_be(UINT32 op);
522   void lwl_le(UINT32 op);
523   void lwr_le(UINT32 op);
524   void ldl_le(UINT32 op);
525   void ldr_le(UINT32 op);
526   void swl_le(UINT32 op);
527   void swr_le(UINT32 op);
528   void sdl_le(UINT32 op);
529   void sdr_le(UINT32 op);
530   void load_fast_iregs(drcuml_block *block);
531   void save_fast_iregs(drcuml_block *block);
532   void code_flush_cache();
533   void code_compile_block(UINT8 mode, offs_t pc);
534public:
535   void func_get_cycles();
536   void func_printf_exception();
537   void func_printf_debug();
538   void func_printf_probe();
539   void func_unimplemented();
540private:
541   void static_generate_entry_point();
542   void static_generate_nocode_handler();
543   void static_generate_out_of_cycles();
544   void static_generate_tlb_mismatch();
545   void static_generate_exception(UINT8 exception, int recover, const char *name);
546   void static_generate_memory_accessor(int mode, int size, int iswrite, int ismasked, const char *name, uml::code_handle **handleptr);
547   void generate_update_mode(drcuml_block *block);
548   void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception);
549   void generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast);
550   void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
551   void generate_delay_slot_and_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 linkreg);
552   int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
553   int generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
554   int generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
555   int generate_idt(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
556   int generate_set_cop0_reg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 reg);
557   int generate_get_cop0_reg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 reg);
558   int generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
559   int generate_cop1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
560   int generate_cop1x(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
561   void log_add_disasm_comment(drcuml_block *block, UINT32 pc, UINT32 op);
562   const char *log_desc_flags_to_string(UINT32 flags);
563   void log_register_list(drcuml_state *drcuml, const char *string, const UINT32 *reglist, const UINT32 *regnostarlist);
564   void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, int indent);
565
566};
567
568
569class vr4300be_device : public mips3_device
570{
571public:
572   // construction/destruction
573   vr4300be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
574      : mips3_device(mconfig, VR4300BE, "VR4300 (big)", tag, owner, clock, "vr4300be", MIPS3_TYPE_VR4300, ENDIANNESS_BIG)
575   { }
576};
577
578class vr4300le_device : public mips3_device
579{
580public:
581   // construction/destruction
582   vr4300le_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
583      : mips3_device(mconfig, VR4300LE, "VR4300 (little)", tag, owner, clock, "vr4300le", MIPS3_TYPE_VR4300, ENDIANNESS_LITTLE)
584   { }
585};
586
587class vr4310be_device : public mips3_device
588{
589public:
590   // construction/destruction
591   vr4310be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
592      : mips3_device(mconfig, VR4310BE, "VR4310 (big)", tag, owner, clock, "vr4310be", MIPS3_TYPE_VR4300, ENDIANNESS_BIG)
593   { }
594};
595
596class vr4310le_device : public mips3_device
597{
598public:
599   // construction/destruction
600   vr4310le_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
601      : mips3_device(mconfig, VR4310LE, "VR4310 (little)", tag, owner, clock, "vr4310le", MIPS3_TYPE_VR4300, ENDIANNESS_LITTLE)
602   { }
603};
604
605class r4600be_device : public mips3_device
606{
607public:
608   // construction/destruction
609   r4600be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
610      : mips3_device(mconfig, R4600BE, "R4600 (big)", tag, owner, clock, "r4600be", MIPS3_TYPE_R4600, ENDIANNESS_BIG)
611   { }
612};
613
614class r4600le_device : public mips3_device
615{
616public:
617   // construction/destruction
618   r4600le_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
619      : mips3_device(mconfig, R4600LE, "R4600 (little)", tag, owner, clock, "r4600le", MIPS3_TYPE_R4600, ENDIANNESS_LITTLE)
620   { }
621};
622
623class r4650be_device : public mips3_device
624{
625public:
626   // construction/destruction
627   r4650be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
628      : mips3_device(mconfig, R4650BE, "IDT R4650 (big)", tag, owner, clock, "r4650be", MIPS3_TYPE_R4650, ENDIANNESS_BIG)
629   { }
630};
631
632class r4650le_device : public mips3_device
633{
634public:
635   // construction/destruction
636   r4650le_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
637      : mips3_device(mconfig, R4650LE, "IDT R4650 (little)", tag, owner, clock, "r4650le", MIPS3_TYPE_R4650, ENDIANNESS_LITTLE)
638   { }
639};
640
641class r4700be_device : public mips3_device
642{
643public:
644   // construction/destruction
645   r4700be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
646      : mips3_device(mconfig, R4700BE, "R4700 (big)", tag, owner, clock, "r4700be", MIPS3_TYPE_R4700, ENDIANNESS_BIG)
647   { }
648};
649
650class r4700le_device : public mips3_device
651{
652public:
653   // construction/destruction
654   r4700le_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
655      : mips3_device(mconfig, R4700LE, "R4700 (little)", tag, owner, clock, "r4700le", MIPS3_TYPE_R4700, ENDIANNESS_LITTLE)
656   { }
657};
658
659class r5000be_device : public mips3_device
660{
661public:
662   // construction/destruction
663   r5000be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
664      : mips3_device(mconfig, R5000BE, "R5000 (big)", tag, owner, clock, "r5000be", MIPS3_TYPE_R5000, ENDIANNESS_BIG)
665   { }
666};
667
668class r5000le_device : public mips3_device
669{
670public:
671   // construction/destruction
672   r5000le_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
673      : mips3_device(mconfig, R5000LE, "R5000 (little)", tag, owner, clock, "r5000le", MIPS3_TYPE_R5000, ENDIANNESS_LITTLE)
674   { }
675};
676
677class qed5271be_device : public mips3_device
678{
679public:
680   // construction/destruction
681   qed5271be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
682      : mips3_device(mconfig, QED5271BE, "QED5271 (big)", tag, owner, clock, "qed5271be", MIPS3_TYPE_QED5271, ENDIANNESS_BIG)
683   { }
684};
685
686class qed5271le_device : public mips3_device
687{
688public:
689   // construction/destruction
690   qed5271le_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
691      : mips3_device(mconfig, QED5271LE, "QED5271 (little)", tag, owner, clock, "qed5271le", MIPS3_TYPE_QED5271, ENDIANNESS_LITTLE)
692   { }
693};
694
695class rm7000be_device : public mips3_device
696{
697public:
698   // construction/destruction
699   rm7000be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
700      : mips3_device(mconfig, RM7000BE, "RM7000 (big)", tag, owner, clock, "rm7000be", MIPS3_TYPE_RM7000, ENDIANNESS_BIG)
701   { }
702};
703
704class rm7000le_device : public mips3_device
705{
706public:
707   // construction/destruction
708   rm7000le_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
709      : mips3_device(mconfig, RM7000LE, "RM7000 (little)", tag, owner, clock, "rm7000le", MIPS3_TYPE_RM7000, ENDIANNESS_LITTLE)
710   { }
711};
712
713
714
715class mips3_frontend : public drc_frontend
716{
717public:
718   // construction/destruction
719   mips3_frontend(mips3_device *mips3, UINT32 window_start, UINT32 window_end, UINT32 max_sequence);
720
721protected:
722   // required overrides
723   virtual bool describe(opcode_desc &desc, const opcode_desc *prev);
724
725private:
726   // internal helpers
727   bool describe_special(UINT32 op, opcode_desc &desc);
728   bool describe_regimm(UINT32 op, opcode_desc &desc);
729   bool describe_idt(UINT32 op, opcode_desc &desc);
730   bool describe_cop0(UINT32 op, opcode_desc &desc);
731   bool describe_cop1(UINT32 op, opcode_desc &desc);
732   bool describe_cop1x(UINT32 op, opcode_desc &desc);
733   bool describe_cop2(UINT32 op, opcode_desc &desc);
734
735   // internal state
736   mips3_device *m_mips3;
737};
738
739
292740/***************************************************************************
293741    COMPILER-SPECIFIC OPTIONS
294742***************************************************************************/
r30757r30758
304752#define MIPS3DRC_FASTEST_OPTIONS    (0)
305753
306754
307
308755#endif /* __MIPS3_H__ */
trunk/src/emu/cpu/mips/mips3drc.c
r30757r30758
3535
3636using namespace uml;
3737
38/***************************************************************************
39    DEBUGGING
40***************************************************************************/
4138
42#define LOG_UML                         (0)
43#define LOG_NATIVE                      (0)
44
45#define DISABLE_FAST_REGISTERS          (0)
46#define SINGLE_INSTRUCTION_MODE         (0)
47
48#define PRINTF_EXCEPTIONS               (0)
49#define PRINTF_MMU                      (0)
50
51#define PROBE_ADDRESS                   ~0
52
53
54
5539/***************************************************************************
56    CONSTANTS
57***************************************************************************/
58
59/* map variables */
60#define MAPVAR_PC                       M0
61#define MAPVAR_CYCLES                   M1
62
63/* modes */
64#define MODE_KERNEL                     0
65#define MODE_SUPER                      1
66#define MODE_USER                       2
67
68/* size of the execution code cache */
69#define CACHE_SIZE                      (32 * 1024 * 1024)
70
71/* compilation boundaries -- how far back/forward does the analysis extend? */
72#define COMPILE_BACKWARDS_BYTES         128
73#define COMPILE_FORWARDS_BYTES          512
74#define COMPILE_MAX_INSTRUCTIONS        ((COMPILE_BACKWARDS_BYTES/4) + (COMPILE_FORWARDS_BYTES/4))
75#define COMPILE_MAX_SEQUENCE            64
76
77/* exit codes */
78#define EXECUTE_OUT_OF_CYCLES           0
79#define EXECUTE_MISSING_CODE            1
80#define EXECUTE_UNMAPPED_CODE           2
81#define EXECUTE_RESET_CACHE             3
82
83
84
85/***************************************************************************
8640    MACROS
8741***************************************************************************/
8842
89#define LOPTR(x)                ((UINT32 *)(x) + NATIVE_ENDIAN_VALUE_LE_BE(0,1))
90
91#define R32(reg)                mips3->impstate->regmaplo[reg]
43#define R32(reg)                m_regmaplo[reg]
9244#define LO32                    R32(REG_LO)
9345#define HI32                    R32(REG_HI)
94#define CPR032(reg)             mem(LOPTR(&mips3->cpr[0][reg]))
95#define CCR032(reg)             mem(LOPTR(&mips3->ccr[0][reg]))
96#define FPR32(reg)              mem(((mips3->impstate->mode & 1) == 0) ? &((float *)&mips3->cpr[1][0])[reg] : (float *)&mips3->cpr[1][reg])
97#define CCR132(reg)             mem(LOPTR(&mips3->ccr[1][reg]))
98#define CPR232(reg)             mem(LOPTR(&mips3->cpr[2][reg]))
99#define CCR232(reg)             mem(LOPTR(&mips3->ccr[2][reg]))
46#define CPR032(reg)             mem(LOPTR(&m_core->cpr[0][reg]))
47#define CCR032(reg)             mem(LOPTR(&m_core->ccr[0][reg]))
48#define FPR32(reg)              mem(((m_core->mode & 1) == 0) ? &((float *)&m_core->cpr[1][0])[reg] : (float *)&m_core->cpr[1][reg])
49#define CCR132(reg)             mem(LOPTR(&m_core->ccr[1][reg]))
50#define CPR232(reg)             mem(LOPTR(&m_core->cpr[2][reg]))
51#define CCR232(reg)             mem(LOPTR(&m_core->ccr[2][reg]))
10052
101#define R64(reg)                mips3->impstate->regmap[reg]
53#define R64(reg)                m_regmap[reg]
10254#define LO64                    R64(REG_LO)
10355#define HI64                    R64(REG_HI)
104#define CPR064(reg)             mem(&mips3->cpr[0][reg])
105#define CCR064(reg)             mem(&mips3->ccr[0][reg])
106#define FPR64(reg)              mem(((mips3->impstate->mode & 1) == 0) ? (double *)&mips3->cpr[1][(reg)/2] : (double *)&mips3->cpr[1][reg])
107#define CCR164(reg)             mem(&mips3->ccr[1][reg])
108#define CPR264(reg)             mem(&mips3->cpr[2][reg])
109#define CCR264(reg)             mem(&mips3->ccr[2][reg])
56#define CPR064(reg)             mem(&m_core->cpr[0][reg])
57#define CCR064(reg)             mem(&m_core->ccr[0][reg])
58#define FPR64(reg)              mem(((m_core->mode & 1) == 0) ? (double *)&m_core->cpr[1][(reg)/2] : (double *)&m_core->cpr[1][reg])
59#define CCR164(reg)             mem(&m_core->ccr[1][reg])
60#define CPR264(reg)             mem(&m_core->cpr[2][reg])
61#define CCR264(reg)             mem(&m_core->ccr[2][reg])
11062
111#define FCCSHIFT(which)         fcc_shift[(mips3->flavor < MIPS3_TYPE_MIPS_IV) ? 0 : ((which) & 7)]
63#define FCCSHIFT(which)         fcc_shift[(m_flavor < MIPS3_TYPE_MIPS_IV) ? 0 : ((which) & 7)]
11264#define FCCMASK(which)          ((UINT32)(1 << FCCSHIFT(which)))
11365
11466
11567
11668/***************************************************************************
117    STRUCTURES & TYPEDEFS
118***************************************************************************/
119
120/* fast RAM info */
121struct fast_ram_info
122{
123   offs_t              start;                      /* start of the RAM block */
124   offs_t              end;                        /* end of the RAM block */
125   UINT8               readonly;                   /* TRUE if read-only */
126   void *              base;                       /* base in memory where the RAM lives */
127};
128
129
130/* hotspot info */
131struct hotspot_info
132{
133   offs_t              pc;                         /* PC to consider */
134   UINT32              opcode;                     /* required opcode at that PC */
135   UINT32              cycles;                     /* number of cycles to eat when hit */
136};
137
138
139/* internal compiler state */
140struct compiler_state
141{
142   UINT32              cycles;                     /* accumulated cycles */
143   UINT8               checkints;                  /* need to check interrupts before next instruction */
144   UINT8               checksoftints;              /* need to check software interrupts before next instruction */
145   code_label  labelnum;                   /* index for local labels */
146};
147
148
149/* MIPS3 registers */
150struct mips3imp_state
151{
152   /* core state */
153   drc_cache *         cache;                      /* pointer to the DRC code cache */
154   drcuml_state *      drcuml;                     /* DRC UML generator state */
155   mips3_frontend *    drcfe;                      /* pointer to the DRC front-end state */
156   UINT32              drcoptions;                 /* configurable DRC options */
157
158   /* internal stuff */
159   UINT8               cache_dirty;                /* true if we need to flush the cache */
160   UINT32              jmpdest;                    /* destination jump target */
161
162   /* parameters for subroutines */
163   UINT64              numcycles;                  /* return value from gettotalcycles */
164   UINT32              mode;                       /* current global mode */
165   const char *        format;                     /* format string for print_debug */
166   UINT32              arg0;                       /* print_debug argument 1 */
167   UINT32              arg1;                       /* print_debug argument 2 */
168
169   /* tables */
170   UINT8               fpmode[4];                  /* FPU mode table */
171
172   /* register mappings */
173   parameter   regmap[34];                 /* parameter to register mappings for all 32 integer registers */
174   parameter   regmaplo[34];               /* parameter to register mappings for all 32 integer registers */
175
176   /* subroutines */
177   code_handle *   entry;                      /* entry point */
178   code_handle *   nocode;                     /* nocode exception handler */
179   code_handle *   out_of_cycles;              /* out of cycles exception handler */
180   code_handle *   tlb_mismatch;               /* tlb mismatch handler */
181   code_handle *   read8[3];                   /* read byte */
182   code_handle *   write8[3];                  /* write byte */
183   code_handle *   read16[3];                  /* read half */
184   code_handle *   write16[3];                 /* write half */
185   code_handle *   read32[3];                  /* read word */
186   code_handle *   read32mask[3];              /* read word masked */
187   code_handle *   write32[3];                 /* write word */
188   code_handle *   write32mask[3];             /* write word masked */
189   code_handle *   read64[3];                  /* read double */
190   code_handle *   read64mask[3];              /* read double masked */
191   code_handle *   write64[3];                 /* write double */
192   code_handle *   write64mask[3];             /* write double masked */
193   code_handle *   exception[EXCEPTION_COUNT]; /* array of exception handlers */
194   code_handle *   exception_norecover[EXCEPTION_COUNT];   /* array of no-recover exception handlers */
195
196   /* fast RAM */
197   UINT32              fastram_select;
198   fast_ram_info       fastram[MIPS3_MAX_FASTRAM];
199
200   /* hotspots */
201   UINT32              hotspot_select;
202   hotspot_info        hotspot[MIPS3_MAX_HOTSPOTS];
203};
204
205
206
207/***************************************************************************
20869    FUNCTION PROTOTYPES
20970***************************************************************************/
21071
211static void code_flush_cache(mips3_state *mips3);
212static void code_compile_block(mips3_state *mips3, UINT8 mode, offs_t pc);
213
21472static void cfunc_printf_exception(void *param);
21573static void cfunc_get_cycles(void *param);
21674static void cfunc_printf_probe(void *param);
21775
218static void static_generate_entry_point(mips3_state *mips3);
219static void static_generate_nocode_handler(mips3_state *mips3);
220static void static_generate_out_of_cycles(mips3_state *mips3);
221static void static_generate_tlb_mismatch(mips3_state *mips3);
222static void static_generate_exception(mips3_state *mips3, UINT8 exception, int recover, const char *name);
223static void static_generate_memory_accessor(mips3_state *mips3, int mode, int size, int iswrite, int ismasked, const char *name, code_handle **handleptr);
22476
225static void generate_update_mode(mips3_state *mips3, drcuml_block *block);
226static void generate_update_cycles(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, parameter param, int allow_exception);
227static void generate_checksum_block(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast);
228static void generate_sequence_instruction(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
229static void generate_delay_slot_and_branch(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 linkreg);
230static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
231static int generate_special(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
232static int generate_regimm(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
233static int generate_idt(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
234static int generate_set_cop0_reg(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 reg);
235static int generate_get_cop0_reg(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 reg);
236static int generate_cop0(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
237static int generate_cop1(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
238static int generate_cop1x(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
239
240static void log_add_disasm_comment(mips3_state *mips3, drcuml_block *block, UINT32 pc, UINT32 op);
241static const char *log_desc_flags_to_string(UINT32 flags);
242static void log_register_list(drcuml_state *drcuml, const char *string, const UINT32 *reglist, const UINT32 *regnostarlist);
243static void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, int indent);
244
245
246
24777/***************************************************************************
24878    PRIVATE GLOBAL VARIABLES
24979***************************************************************************/
r30757r30758
25181/* bit indexes for various FCCs */
25282static const UINT8 fcc_shift[8] = { 23, 25, 26, 27, 28, 29, 30, 31 };
25383
254/* lookup table for FP modes */
255static const UINT8 fpmode_source[4] =
256{
257   ROUND_ROUND,
258   ROUND_TRUNC,
259   ROUND_CEIL,
260   ROUND_FLOOR
261};
26284
263
264
26585/***************************************************************************
26686    INLINE FUNCTIONS
26787***************************************************************************/
26888
269INLINE mips3_state *get_safe_token(device_t *device)
270{
271   assert(device != NULL);
272   assert(device->type() == VR4300BE_DRC ||
273         device->type() == VR4300LE_DRC ||
274         device->type() == VR4310BE_DRC ||
275         device->type() == VR4310LE_DRC ||
276         device->type() == R4600BE_DRC ||
277         device->type() == R4600LE_DRC ||
278         device->type() == R4650BE_DRC ||
279         device->type() == R4650LE_DRC ||
280         device->type() == R4700BE_DRC ||
281         device->type() == R4700LE_DRC ||
282         device->type() == R5000BE_DRC ||
283         device->type() == R5000LE_DRC ||
284         device->type() == QED5271BE_DRC ||
285         device->type() == QED5271LE_DRC ||
286         device->type() == RM7000BE_DRC ||
287         device->type() == RM7000LE_DRC);
288   return *(mips3_state **)downcast<legacy_cpu_device *>(device)->token();
289}
290
291
29289/*-------------------------------------------------
29390    epc - compute the exception PC from a
29491    descriptor
r30757r30758
317114    registers
318115-------------------------------------------------*/
319116
320INLINE void load_fast_iregs(mips3_state *mips3, drcuml_block *block)
117inline void mips3_device::load_fast_iregs(drcuml_block *block)
321118{
322119   int regnum;
323120
324   for (regnum = 0; regnum < ARRAY_LENGTH(mips3->impstate->regmap); regnum++)
325      if (mips3->impstate->regmap[regnum].is_int_register())
326         UML_DMOV(block, ireg(mips3->impstate->regmap[regnum].ireg() - REG_I0), mem(&mips3->r[regnum]));
121   for (regnum = 0; regnum < ARRAY_LENGTH(m_regmap); regnum++)
122      if (m_regmap[regnum].is_int_register())
123         UML_DMOV(block, ireg(m_regmap[regnum].ireg() - REG_I0), mem(&m_core->r[regnum]));
327124}
328125
329126
r30757r30758
332129    registers
333130-------------------------------------------------*/
334131
335INLINE void save_fast_iregs(mips3_state *mips3, drcuml_block *block)
132inline void mips3_device::save_fast_iregs(drcuml_block *block)
336133{
337134   int regnum;
338135
339   for (regnum = 0; regnum < ARRAY_LENGTH(mips3->impstate->regmap); regnum++)
340      if (mips3->impstate->regmap[regnum].is_int_register())
341         UML_DMOV(block, mem(&mips3->r[regnum]), ireg(mips3->impstate->regmap[regnum].ireg() - REG_I0));
136   for (regnum = 0; regnum < ARRAY_LENGTH(m_regmap); regnum++)
137      if (m_regmap[regnum].is_int_register())
138         UML_DMOV(block, mem(&m_core->r[regnum]), ireg(m_regmap[regnum].ireg() - REG_I0));
342139}
343140
344141
r30757r30758
348145***************************************************************************/
349146
350147/*-------------------------------------------------
351    mips3_init - initialize the processor
352-------------------------------------------------*/
353
354static void mips3_init(mips3_flavor flavor, int bigendian, legacy_cpu_device *device, device_irq_acknowledge_delegate irqcallback)
355{
356   mips3_state *mips3;
357   drc_cache *cache;
358   drcbe_info beinfo;
359   UINT32 flags = 0;
360   int regnum;
361
362   /* allocate enough space for the cache and the core */
363   cache = auto_alloc(device->machine(), drc_cache(CACHE_SIZE + sizeof(*mips3)));
364   if (cache == NULL)
365      fatalerror("Unable to allocate cache of size %d\n", (UINT32)(CACHE_SIZE + sizeof(*mips3)));
366
367   /* allocate the core memory */
368   *(mips3_state **)device->token() = mips3 = (mips3_state *)cache->alloc_near(sizeof(*mips3));
369   memset(mips3, 0, sizeof(*mips3));
370
371   /* initialize the core */
372   mips3com_init(mips3, flavor, bigendian, device, irqcallback);
373
374   /* allocate the implementation-specific state from the full cache */
375   mips3->impstate = (mips3imp_state *)cache->alloc_near(sizeof(*mips3->impstate));
376   memset(mips3->impstate, 0, sizeof(*mips3->impstate));
377   mips3->impstate->cache = cache;
378
379   /* initialize the UML generator */
380   if (LOG_UML)
381      flags |= DRCUML_OPTION_LOG_UML;
382   if (LOG_NATIVE)
383      flags |= DRCUML_OPTION_LOG_NATIVE;
384   mips3->impstate->drcuml = auto_alloc(device->machine(), drcuml_state(*device, *cache, flags, 8, 32, 2));
385
386   /* add symbols for our stuff */
387   mips3->impstate->drcuml->symbol_add(&mips3->pc, sizeof(mips3->pc), "pc");
388   mips3->impstate->drcuml->symbol_add(&mips3->icount, sizeof(mips3->icount), "icount");
389   for (regnum = 0; regnum < 32; regnum++)
390   {
391      char buf[10];
392      sprintf(buf, "r%d", regnum);
393      mips3->impstate->drcuml->symbol_add(&mips3->r[regnum], sizeof(mips3->r[regnum]), buf);
394      sprintf(buf, "f%d", regnum);
395      mips3->impstate->drcuml->symbol_add(&mips3->cpr[1][regnum], sizeof(mips3->cpr[1][regnum]), buf);
396   }
397   mips3->impstate->drcuml->symbol_add(&mips3->r[REG_LO], sizeof(mips3->r[REG_LO]), "lo");
398   mips3->impstate->drcuml->symbol_add(&mips3->r[REG_HI], sizeof(mips3->r[REG_LO]), "hi");
399   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_Index], sizeof(mips3->cpr[0][COP0_Index]), "Index");
400   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_Random], sizeof(mips3->cpr[0][COP0_Random]), "Random");
401   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_EntryLo0], sizeof(mips3->cpr[0][COP0_EntryLo0]), "EntryLo0");
402   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_EntryLo1], sizeof(mips3->cpr[0][COP0_EntryLo1]), "EntryLo1");
403   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_Context], sizeof(mips3->cpr[0][COP0_Context]), "Context");
404   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_PageMask], sizeof(mips3->cpr[0][COP0_PageMask]), "PageMask");
405   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_Wired], sizeof(mips3->cpr[0][COP0_Wired]), "Wired");
406   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_BadVAddr], sizeof(mips3->cpr[0][COP0_BadVAddr]), "BadVAddr");
407   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_Count], sizeof(mips3->cpr[0][COP0_Count]), "Count");
408   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_EntryHi], sizeof(mips3->cpr[0][COP0_EntryHi]), "EntryHi");
409   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_Compare], sizeof(mips3->cpr[0][COP0_Compare]), "Compare");
410   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_Status], sizeof(mips3->cpr[0][COP0_Status]), "Status");
411   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_Cause], sizeof(mips3->cpr[0][COP0_Cause]), "Cause");
412   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_EPC], sizeof(mips3->cpr[0][COP0_EPC]), "EPC");
413   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_PRId], sizeof(mips3->cpr[0][COP0_PRId]), "PRId");
414   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_Config], sizeof(mips3->cpr[0][COP0_Config]), "Config");
415   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_LLAddr], sizeof(mips3->cpr[0][COP0_LLAddr]), "LLAddr");
416   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_XContext], sizeof(mips3->cpr[0][COP0_XContext]), "XContext");
417   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_ECC], sizeof(mips3->cpr[0][COP0_ECC]), "ECC");
418   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_CacheErr], sizeof(mips3->cpr[0][COP0_CacheErr]), "CacheErr");
419   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_TagLo], sizeof(mips3->cpr[0][COP0_TagLo]), "TagLo");
420   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_TagHi], sizeof(mips3->cpr[0][COP0_TagHi]), "TagHi");
421   mips3->impstate->drcuml->symbol_add(&mips3->cpr[0][COP0_ErrorPC], sizeof(mips3->cpr[0][COP0_ErrorPC]), "ErrorPC");
422   mips3->impstate->drcuml->symbol_add(&mips3->ccr[1][31], sizeof(mips3->cpr[1][31]), "fcr31");
423   mips3->impstate->drcuml->symbol_add(&mips3->impstate->mode, sizeof(mips3->impstate->mode), "mode");
424   mips3->impstate->drcuml->symbol_add(&mips3->impstate->arg0, sizeof(mips3->impstate->arg0), "arg0");
425   mips3->impstate->drcuml->symbol_add(&mips3->impstate->arg1, sizeof(mips3->impstate->arg1), "arg1");
426   mips3->impstate->drcuml->symbol_add(&mips3->impstate->numcycles, sizeof(mips3->impstate->numcycles), "numcycles");
427   mips3->impstate->drcuml->symbol_add(&mips3->impstate->fpmode, sizeof(mips3->impstate->fpmode), "fpmode");
428
429   /* initialize the front-end helper */
430   mips3->impstate->drcfe = auto_alloc(device->machine(), mips3_frontend(*mips3, COMPILE_BACKWARDS_BYTES, COMPILE_FORWARDS_BYTES, SINGLE_INSTRUCTION_MODE ? 1 : COMPILE_MAX_SEQUENCE));
431
432   /* allocate memory for cache-local state and initialize it */
433   memcpy(mips3->impstate->fpmode, fpmode_source, sizeof(fpmode_source));
434
435   /* compute the register parameters */
436   for (regnum = 0; regnum < 34; regnum++)
437   {
438      mips3->impstate->regmap[regnum] = (regnum == 0) ? parameter(0) : parameter::make_memory(&mips3->r[regnum]);
439      mips3->impstate->regmaplo[regnum] = (regnum == 0) ? parameter(0) : parameter::make_memory(LOPTR(&mips3->r[regnum]));
440   }
441
442   /* if we have registers to spare, assign r2, r3, r4 to leftovers */
443   if (!DISABLE_FAST_REGISTERS)
444   {
445      mips3->impstate->drcuml->get_backend_info(beinfo);
446      if (beinfo.direct_iregs > 4)
447      {
448         mips3->impstate->regmap[2] = I4;
449         mips3->impstate->regmaplo[2] = I4;
450      }
451      if (beinfo.direct_iregs > 5)
452      {
453         mips3->impstate->regmap[3] = I5;
454         mips3->impstate->regmaplo[3] = I5;
455      }
456      if (beinfo.direct_iregs > 6)
457      {
458         mips3->impstate->regmap[4] = I6;
459         mips3->impstate->regmaplo[4] = I6;
460      }
461   }
462
463   /* mark the cache dirty so it is updated on next execute */
464   mips3->impstate->cache_dirty = TRUE;
465}
466
467
468/*-------------------------------------------------
469    mips3_reset - reset the processor
470-------------------------------------------------*/
471
472static CPU_RESET( mips3 )
473{
474   mips3_state *mips3 = get_safe_token(device);
475
476   /* reset the common code and mark the cache dirty */
477   mips3com_reset(mips3);
478   mips3->impstate->mode = (MODE_KERNEL << 1) | 0;
479   mips3->impstate->cache_dirty = TRUE;
480}
481
482
483/*-------------------------------------------------
484    mips3_execute - execute the CPU for the
485    specified number of cycles
486-------------------------------------------------*/
487
488static CPU_EXECUTE( mips3 )
489{
490   mips3_state *mips3 = get_safe_token(device);
491   drcuml_state *drcuml = mips3->impstate->drcuml;
492   int execute_result;
493
494   /* reset the cache if dirty */
495   if (mips3->impstate->cache_dirty)
496      code_flush_cache(mips3);
497   mips3->impstate->cache_dirty = FALSE;
498
499   /* execute */
500   do
501   {
502      /* run as much as we can */
503      execute_result = drcuml->execute(*mips3->impstate->entry);
504
505      /* if we need to recompile, do it */
506      if (execute_result == EXECUTE_MISSING_CODE)
507         code_compile_block(mips3, mips3->impstate->mode, mips3->pc);
508      else if (execute_result == EXECUTE_UNMAPPED_CODE)
509         fatalerror("Attempted to execute unmapped code at PC=%08X\n", mips3->pc);
510      else if (execute_result == EXECUTE_RESET_CACHE)
511         code_flush_cache(mips3);
512
513   } while (execute_result != EXECUTE_OUT_OF_CYCLES);
514}
515
516
517/*-------------------------------------------------
518    mips3_exit - cleanup from execution
519-------------------------------------------------*/
520
521static CPU_EXIT( mips3 )
522{
523   mips3_state *mips3 = get_safe_token(device);
524   mips3com_exit(mips3);
525
526   /* clean up the DRC */
527   auto_free(device->machine(), mips3->impstate->drcfe);
528   auto_free(device->machine(), mips3->impstate->drcuml);
529   auto_free(device->machine(), mips3->impstate->cache);
530}
531
532
533/*-------------------------------------------------
534    mips3_translate - perform virtual-to-physical
535    address translation
536-------------------------------------------------*/
537
538static CPU_TRANSLATE( mips3 )
539{
540   mips3_state *mips3 = get_safe_token(device);
541   return mips3com_translate_address(mips3, space, intention, address);
542}
543
544
545/*-------------------------------------------------
546    mips3_dasm - disassemble an instruction
547-------------------------------------------------*/
548
549static CPU_DISASSEMBLE( mips3 )
550{
551   mips3_state *mips3 = get_safe_token(device);
552   return mips3com_dasm(mips3, buffer, pc, oprom, opram);
553}
554
555
556/*-------------------------------------------------
557    mips3_set_info - set information about a given
558    CPU instance
559-------------------------------------------------*/
560
561static CPU_SET_INFO( mips3 )
562{
563   mips3_state *mips3 = get_safe_token(device);
564
565   /* --- everything is handled generically --- */
566   mips3com_set_info(mips3, state, info);
567}
568
569
570/*-------------------------------------------------
571    mips3_get_info - return information about a
572    given CPU instance
573-------------------------------------------------*/
574
575static CPU_GET_INFO( mips3 )
576{
577   mips3_state *mips3 = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
578   switch (state)
579   {
580      /* --- the following bits of info are returned as 64-bit signed integers --- */
581      case CPUINFO_INT_CONTEXT_SIZE:                  info->i = sizeof(mips3_state *);                break;
582      case CPUINFO_INT_PREVIOUSPC:                    /* not implemented */                           break;
583
584      /* --- the following bits of info are returned as pointers to data or functions --- */
585      case CPUINFO_FCT_SET_INFO:                      info->setinfo = CPU_SET_INFO_NAME(mips3);       break;
586      case CPUINFO_FCT_INIT:                          /* provided per-CPU */                          break;
587      case CPUINFO_FCT_RESET:                         info->reset = CPU_RESET_NAME(mips3);            break;
588      case CPUINFO_FCT_EXIT:                          info->exit = CPU_EXIT_NAME(mips3);              break;
589      case CPUINFO_FCT_EXECUTE:                       info->execute = CPU_EXECUTE_NAME(mips3);        break;
590      case CPUINFO_FCT_DISASSEMBLE:                   info->disassemble = CPU_DISASSEMBLE_NAME(mips3);break;
591      case CPUINFO_FCT_TRANSLATE:                     info->translate = CPU_TRANSLATE_NAME(mips3);    break;
592
593      /* --- the following bits of info are returned as NULL-terminated strings --- */
594      case CPUINFO_STR_SOURCE_FILE:                       strcpy(info->s, __FILE__);                      break;
595
596      /* --- everything else is handled generically --- */
597      default:                                        mips3com_get_info(mips3, state, info);          break;
598   }
599}
600
601
602/*-------------------------------------------------
603148    mips3drc_set_options - configure DRC options
604149-------------------------------------------------*/
605150
606void mips3drc_set_options(device_t *device, UINT32 options)
151void mips3_device::mips3drc_set_options(UINT32 options)
607152{
608   if (!device->machine().options().drc()) return;
609   mips3_state *mips3 = get_safe_token(device);
610   mips3->impstate->drcoptions = options;
153   if (!machine().options().drc()) return;
154   m_drcoptions = options;
611155}
612156
613157
r30757r30758
616160    region
617161-------------------------------------------------*/
618162
619void mips3drc_add_fastram(device_t *device, offs_t start, offs_t end, UINT8 readonly, void *base)
163void mips3_device::mips3drc_add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base)
620164{
621   if (!device->machine().options().drc()) return;
622   mips3_state *mips3 = get_safe_token(device);
623   if (mips3->impstate->fastram_select < ARRAY_LENGTH(mips3->impstate->fastram))
165   if (!machine().options().drc()) return;
166   if (m_fastram_select < ARRAY_LENGTH(m_fastram))
624167   {
625      mips3->impstate->fastram[mips3->impstate->fastram_select].start = start;
626      mips3->impstate->fastram[mips3->impstate->fastram_select].end = end;
627      mips3->impstate->fastram[mips3->impstate->fastram_select].readonly = readonly;
628      mips3->impstate->fastram[mips3->impstate->fastram_select].base = base;
629      mips3->impstate->fastram_select++;
168      m_fastram[m_fastram_select].start = start;
169      m_fastram[m_fastram_select].end = end;
170      m_fastram[m_fastram_select].readonly = readonly;
171      m_fastram[m_fastram_select].base = base;
172      m_fastram_select++;
630173   }
631174}
632175
r30757r30758
635178    mips3drc_add_hotspot - add a new hotspot
636179-------------------------------------------------*/
637180
638void mips3drc_add_hotspot(device_t *device, offs_t pc, UINT32 opcode, UINT32 cycles)
181void mips3_device::mips3drc_add_hotspot(offs_t pc, UINT32 opcode, UINT32 cycles)
639182{
640   if (!device->machine().options().drc()) return;
641   mips3_state *mips3 = get_safe_token(device);
642   if (mips3->impstate->hotspot_select < ARRAY_LENGTH(mips3->impstate->hotspot))
183   if (!machine().options().drc()) return;
184   if (m_hotspot_select < ARRAY_LENGTH(m_hotspot))
643185   {
644      mips3->impstate->hotspot[mips3->impstate->hotspot_select].pc = pc;
645      mips3->impstate->hotspot[mips3->impstate->hotspot_select].opcode = opcode;
646      mips3->impstate->hotspot[mips3->impstate->hotspot_select].cycles = cycles;
647      mips3->impstate->hotspot_select++;
186      m_hotspot[m_hotspot_select].pc = pc;
187      m_hotspot[m_hotspot_select].opcode = opcode;
188      m_hotspot[m_hotspot_select].cycles = cycles;
189      m_hotspot_select++;
648190   }
649191}
650192
r30757r30758
659201    regenerate static code
660202-------------------------------------------------*/
661203
662static void code_flush_cache(mips3_state *mips3)
204void mips3_device::code_flush_cache()
663205{
664206   int mode;
665207
666208   /* empty the transient cache contents */
667   mips3->impstate->drcuml->reset();
209   m_drcuml->reset();
668210
669211   try
670212   {
671213      /* generate the entry point and out-of-cycles handlers */
672      static_generate_entry_point(mips3);
673      static_generate_nocode_handler(mips3);
674      static_generate_out_of_cycles(mips3);
675      static_generate_tlb_mismatch(mips3);
214      static_generate_entry_point();
215      static_generate_nocode_handler();
216      static_generate_out_of_cycles();
217      static_generate_tlb_mismatch();
676218
677219      /* append exception handlers for various types */
678      static_generate_exception(mips3, EXCEPTION_INTERRUPT,     TRUE,  "exception_interrupt");
679      static_generate_exception(mips3, EXCEPTION_INTERRUPT,     FALSE, "exception_interrupt_norecover");
680      static_generate_exception(mips3, EXCEPTION_TLBMOD,        TRUE,  "exception_tlbmod");
681      static_generate_exception(mips3, EXCEPTION_TLBLOAD,       TRUE,  "exception_tlbload");
682      static_generate_exception(mips3, EXCEPTION_TLBSTORE,      TRUE,  "exception_tlbstore");
683      static_generate_exception(mips3, EXCEPTION_TLBLOAD_FILL,  TRUE,  "exception_tlbload_fill");
684      static_generate_exception(mips3, EXCEPTION_TLBSTORE_FILL, TRUE,  "exception_tlbstore_fill");
685      static_generate_exception(mips3, EXCEPTION_ADDRLOAD,      TRUE,  "exception_addrload");
686      static_generate_exception(mips3, EXCEPTION_ADDRSTORE,     TRUE,  "exception_addrstore");
687      static_generate_exception(mips3, EXCEPTION_SYSCALL,       TRUE,  "exception_syscall");
688      static_generate_exception(mips3, EXCEPTION_BREAK,         TRUE,  "exception_break");
689      static_generate_exception(mips3, EXCEPTION_INVALIDOP,     TRUE,  "exception_invalidop");
690      static_generate_exception(mips3, EXCEPTION_BADCOP,        TRUE,  "exception_badcop");
691      static_generate_exception(mips3, EXCEPTION_OVERFLOW,      TRUE,  "exception_overflow");
692      static_generate_exception(mips3, EXCEPTION_TRAP,          TRUE,  "exception_trap");
220      static_generate_exception(EXCEPTION_INTERRUPT,     TRUE,  "exception_interrupt");
221      static_generate_exception(EXCEPTION_INTERRUPT,     FALSE, "exception_interrupt_norecover");
222      static_generate_exception(EXCEPTION_TLBMOD,        TRUE,  "exception_tlbmod");
223      static_generate_exception(EXCEPTION_TLBLOAD,       TRUE,  "exception_tlbload");
224      static_generate_exception(EXCEPTION_TLBSTORE,      TRUE,  "exception_tlbstore");
225      static_generate_exception(EXCEPTION_TLBLOAD_FILL,  TRUE,  "exception_tlbload_fill");
226      static_generate_exception(EXCEPTION_TLBSTORE_FILL, TRUE,  "exception_tlbstore_fill");
227      static_generate_exception(EXCEPTION_ADDRLOAD,      TRUE,  "exception_addrload");
228      static_generate_exception(EXCEPTION_ADDRSTORE,     TRUE,  "exception_addrstore");
229      static_generate_exception(EXCEPTION_SYSCALL,       TRUE,  "exception_syscall");
230      static_generate_exception(EXCEPTION_BREAK,         TRUE,  "exception_break");
231      static_generate_exception(EXCEPTION_INVALIDOP,     TRUE,  "exception_invalidop");
232      static_generate_exception(EXCEPTION_BADCOP,        TRUE,  "exception_badcop");
233      static_generate_exception(EXCEPTION_OVERFLOW,      TRUE,  "exception_overflow");
234      static_generate_exception(EXCEPTION_TRAP,          TRUE,  "exception_trap");
693235
694236      /* add subroutines for memory accesses */
695237      for (mode = 0; mode < 3; mode++)
696238      {
697         static_generate_memory_accessor(mips3, mode, 1, FALSE, FALSE, "read8",       &mips3->impstate->read8[mode]);
698         static_generate_memory_accessor(mips3, mode, 1, TRUE,  FALSE, "write8",      &mips3->impstate->write8[mode]);
699         static_generate_memory_accessor(mips3, mode, 2, FALSE, FALSE, "read16",      &mips3->impstate->read16[mode]);
700         static_generate_memory_accessor(mips3, mode, 2, TRUE,  FALSE, "write16",     &mips3->impstate->write16[mode]);
701         static_generate_memory_accessor(mips3, mode, 4, FALSE, FALSE, "read32",      &mips3->impstate->read32[mode]);
702         static_generate_memory_accessor(mips3, mode, 4, FALSE, TRUE,  "read32mask",  &mips3->impstate->read32mask[mode]);
703         static_generate_memory_accessor(mips3, mode, 4, TRUE,  FALSE, "write32",     &mips3->impstate->write32[mode]);
704         static_generate_memory_accessor(mips3, mode, 4, TRUE,  TRUE,  "write32mask", &mips3->impstate->write32mask[mode]);
705         static_generate_memory_accessor(mips3, mode, 8, FALSE, FALSE, "read64",      &mips3->impstate->read64[mode]);
706         static_generate_memory_accessor(mips3, mode, 8, FALSE, TRUE,  "read64mask",  &mips3->impstate->read64mask[mode]);
707         static_generate_memory_accessor(mips3, mode, 8, TRUE,  FALSE, "write64",     &mips3->impstate->write64[mode]);
708         static_generate_memory_accessor(mips3, mode, 8, TRUE,  TRUE,  "write64mask", &mips3->impstate->write64mask[mode]);
239         static_generate_memory_accessor(mode, 1, FALSE, FALSE, "read8",       &m_read8[mode]);
240         static_generate_memory_accessor(mode, 1, TRUE,  FALSE, "write8",      &m_write8[mode]);
241         static_generate_memory_accessor(mode, 2, FALSE, FALSE, "read16",      &m_read16[mode]);
242         static_generate_memory_accessor(mode, 2, TRUE,  FALSE, "write16",     &m_write16[mode]);
243         static_generate_memory_accessor(mode, 4, FALSE, FALSE, "read32",      &m_read32[mode]);
244         static_generate_memory_accessor(mode, 4, FALSE, TRUE,  "read32mask",  &m_read32mask[mode]);
245         static_generate_memory_accessor(mode, 4, TRUE,  FALSE, "write32",     &m_write32[mode]);
246         static_generate_memory_accessor(mode, 4, TRUE,  TRUE,  "write32mask", &m_write32mask[mode]);
247         static_generate_memory_accessor(mode, 8, FALSE, FALSE, "read64",      &m_read64[mode]);
248         static_generate_memory_accessor(mode, 8, FALSE, TRUE,  "read64mask",  &m_read64mask[mode]);
249         static_generate_memory_accessor(mode, 8, TRUE,  FALSE, "write64",     &m_write64[mode]);
250         static_generate_memory_accessor(mode, 8, TRUE,  TRUE,  "write64mask", &m_write64mask[mode]);
709251      }
710252   }
711253   catch (drcuml_block::abort_compilation &)
r30757r30758
720262    given mode at the specified pc
721263-------------------------------------------------*/
722264
723static void code_compile_block(mips3_state *mips3, UINT8 mode, offs_t pc)
265void mips3_device::code_compile_block(UINT8 mode, offs_t pc)
724266{
725   drcuml_state *drcuml = mips3->impstate->drcuml;
267   drcuml_state *drcuml = m_drcuml;
726268   compiler_state compiler = { 0 };
727269   const opcode_desc *seqhead, *seqlast;
728270   const opcode_desc *desclist;
r30757r30758
732274   g_profiler.start(PROFILER_DRC_COMPILE);
733275
734276   /* get a description of this sequence */
735   desclist = mips3->impstate->drcfe->describe_code(pc);
277   desclist = m_drcfe->describe_code(pc);
736278   if (LOG_UML || LOG_NATIVE)
737279      log_opcode_desc(drcuml, desclist, 0);
738280
r30757r30758
777319            else
778320            {
779321               UML_LABEL(block, seqhead->pc | 0x80000000);                             // label   seqhead->pc | 0x80000000
780               UML_HASHJMP(block, mips3->impstate->mode, seqhead->pc, *mips3->impstate->nocode);
322               UML_HASHJMP(block, m_core->mode, seqhead->pc, *m_nocode);
781323                                                                     // hashjmp <mode>,seqhead->pc,nocode
782324               continue;
783325            }
784326
785327            /* validate this code block if we're not pointing into ROM */
786            if (mips3->program->get_write_ptr(seqhead->physpc) != NULL)
787               generate_checksum_block(mips3, block, &compiler, seqhead, seqlast);
328            if (m_program->get_write_ptr(seqhead->physpc) != NULL)
329               generate_checksum_block(block, &compiler, seqhead, seqlast);
788330
789331            /* label this instruction, if it may be jumped to locally */
790332            if (seqhead->flags & OPFLAG_IS_BRANCH_TARGET)
r30757r30758
792334
793335            /* iterate over instructions in the sequence and compile them */
794336            for (curdesc = seqhead; curdesc != seqlast->next(); curdesc = curdesc->next())
795               generate_sequence_instruction(mips3, block, &compiler, curdesc);
337               generate_sequence_instruction(block, &compiler, curdesc);
796338
797339            /* if we need to return to the start, do it */
798340            if (seqlast->flags & OPFLAG_RETURN_TO_START)
r30757r30758
803345               nextpc = seqlast->pc + (seqlast->skipslots + 1) * 4;
804346
805347            /* count off cycles and go there */
806            generate_update_cycles(mips3, block, &compiler, nextpc, TRUE);          // <subtract cycles>
348            generate_update_cycles(block, &compiler, nextpc, TRUE);          // <subtract cycles>
807349
808350            /* if the last instruction can change modes, use a variable mode; otherwise, assume the same mode */
809351            if (seqlast->flags & OPFLAG_CAN_CHANGE_MODES)
810               UML_HASHJMP(block, mem(&mips3->impstate->mode), nextpc, *mips3->impstate->nocode);
352               UML_HASHJMP(block, mem(&m_core->mode), nextpc, *m_nocode);
811353                                                                     // hashjmp <mode>,nextpc,nocode
812354            else if (seqlast->next() == NULL || seqlast->next()->pc != nextpc)
813               UML_HASHJMP(block, mips3->impstate->mode, nextpc, *mips3->impstate->nocode);
355               UML_HASHJMP(block, m_core->mode, nextpc, *m_nocode);
814356                                                                     // hashjmp <mode>,nextpc,nocode
815357         }
816358
r30757r30758
821363      }
822364      catch (drcuml_block::abort_compilation &)
823365      {
824         code_flush_cache(mips3);
366         code_flush_cache();
825367      }
826368   }
827369}
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832374    C FUNCTION CALLBACKS
833375***************************************************************************/
834376
377static void cfunc_mips3com_update_cycle_counting(void *param)
378{
379   ((mips3_device *)param)->mips3com_update_cycle_counting();
380}
381
382static void cfunc_mips3com_asid_changed(void *param)
383{
384   ((mips3_device *)param)->mips3com_asid_changed();
385}
386
387static void cfunc_mips3com_tlbr(void *param)
388{
389   ((mips3_device *)param)->mips3com_tlbr();
390}
391
392static void cfunc_mips3com_tlbwi(void *param)
393{
394   ((mips3_device *)param)->mips3com_tlbwi();
395}
396
397static void cfunc_mips3com_tlbwr(void *param)
398{
399   ((mips3_device *)param)->mips3com_tlbwr();
400}
401
402static void cfunc_mips3com_tlbp(void *param)
403{
404   ((mips3_device *)param)->mips3com_tlbp();
405}
406
835407/*-------------------------------------------------
836408    cfunc_get_cycles - compute the total number
837409    of cycles executed so far
838410-------------------------------------------------*/
839411
412void mips3_device::func_get_cycles()
413{
414   m_core->numcycles = total_cycles();
415}
416
840417static void cfunc_get_cycles(void *param)
841418{
842   mips3_state *mips3 = (mips3_state *)param;
843   mips3->impstate->numcycles = mips3->device->total_cycles();
419   ((mips3_device *)param)->func_get_cycles();
844420}
845421
846422
r30757r30758
849425    aren't interrupts
850426-------------------------------------------------*/
851427
428void mips3_device::func_printf_exception()
429{
430   printf("Exception: EPC=%08X Cause=%08X BadVAddr=%08X Jmp=%08X\n", (UINT32)m_core->cpr[0][COP0_EPC], (UINT32)m_core->cpr[0][COP0_Cause], (UINT32)m_core->cpr[0][COP0_BadVAddr], m_core->pc);
431   func_printf_probe();
432}
433
852434static void cfunc_printf_exception(void *param)
853435{
854   mips3_state *mips3 = (mips3_state *)param;
855   printf("Exception: EPC=%08X Cause=%08X BadVAddr=%08X Jmp=%08X\n", (UINT32)mips3->cpr[0][COP0_EPC], (UINT32)mips3->cpr[0][COP0_Cause], (UINT32)mips3->cpr[0][COP0_BadVAddr], mips3->pc);
856   cfunc_printf_probe(mips3);
436   ((mips3_device *)param)->func_printf_exception();
857437}
858438
859
860439/*-------------------------------------------------
861440    cfunc_printf_debug - generic printf for
862441    debugging
863442-------------------------------------------------*/
864443
444void mips3_device::func_printf_debug()
445{
446   printf(m_core->format, m_core->arg0, m_core->arg1);
447}
448
865449static void cfunc_printf_debug(void *param)
866450{
867   mips3_state *mips3 = (mips3_state *)param;
868   printf(mips3->impstate->format, mips3->impstate->arg0, mips3->impstate->arg1);
451   ((mips3_device *)param)->func_printf_debug();
869452}
870453
871454
r30757r30758
874457    state and return
875458-------------------------------------------------*/
876459
877static void cfunc_printf_probe(void *param)
460void mips3_device::func_printf_probe()
878461{
879   mips3_state *mips3 = (mips3_state *)param;
880
881462   printf(" PC=%08X          r1=%08X%08X  r2=%08X%08X  r3=%08X%08X\n",
882      mips3->pc,
883      (UINT32)(mips3->r[1] >> 32), (UINT32)mips3->r[1],
884      (UINT32)(mips3->r[2] >> 32), (UINT32)mips3->r[2],
885      (UINT32)(mips3->r[3] >> 32), (UINT32)mips3->r[3]);
463      m_core->pc,
464      (UINT32)(m_core->r[1] >> 32), (UINT32)m_core->r[1],
465      (UINT32)(m_core->r[2] >> 32), (UINT32)m_core->r[2],
466      (UINT32)(m_core->r[3] >> 32), (UINT32)m_core->r[3]);
886467   printf(" r4=%08X%08X  r5=%08X%08X  r6=%08X%08X  r7=%08X%08X\n",
887      (UINT32)(mips3->r[4] >> 32), (UINT32)mips3->r[4],
888      (UINT32)(mips3->r[5] >> 32), (UINT32)mips3->r[5],
889      (UINT32)(mips3->r[6] >> 32), (UINT32)mips3->r[6],
890      (UINT32)(mips3->r[7] >> 32), (UINT32)mips3->r[7]);
468      (UINT32)(m_core->r[4] >> 32), (UINT32)m_core->r[4],
469      (UINT32)(m_core->r[5] >> 32), (UINT32)m_core->r[5],
470      (UINT32)(m_core->r[6] >> 32), (UINT32)m_core->r[6],
471      (UINT32)(m_core->r[7] >> 32), (UINT32)m_core->r[7]);
891472   printf(" r8=%08X%08X  r9=%08X%08X r10=%08X%08X r11=%08X%08X\n",
892      (UINT32)(mips3->r[8] >> 32), (UINT32)mips3->r[8],
893      (UINT32)(mips3->r[9] >> 32), (UINT32)mips3->r[9],
894      (UINT32)(mips3->r[10] >> 32), (UINT32)mips3->r[10],
895      (UINT32)(mips3->r[11] >> 32), (UINT32)mips3->r[11]);
473      (UINT32)(m_core->r[8] >> 32), (UINT32)m_core->r[8],
474      (UINT32)(m_core->r[9] >> 32), (UINT32)m_core->r[9],
475      (UINT32)(m_core->r[10] >> 32), (UINT32)m_core->r[10],
476      (UINT32)(m_core->r[11] >> 32), (UINT32)m_core->r[11]);
896477   printf("r12=%08X%08X r13=%08X%08X r14=%08X%08X r15=%08X%08X\n",
897      (UINT32)(mips3->r[12] >> 32), (UINT32)mips3->r[12],
898      (UINT32)(mips3->r[13] >> 32), (UINT32)mips3->r[13],
899      (UINT32)(mips3->r[14] >> 32), (UINT32)mips3->r[14],
900      (UINT32)(mips3->r[15] >> 32), (UINT32)mips3->r[15]);
478      (UINT32)(m_core->r[12] >> 32), (UINT32)m_core->r[12],
479      (UINT32)(m_core->r[13] >> 32), (UINT32)m_core->r[13],
480      (UINT32)(m_core->r[14] >> 32), (UINT32)m_core->r[14],
481      (UINT32)(m_core->r[15] >> 32), (UINT32)m_core->r[15]);
901482   printf("r16=%08X%08X r17=%08X%08X r18=%08X%08X r19=%08X%08X\n",
902      (UINT32)(mips3->r[16] >> 32), (UINT32)mips3->r[16],
903      (UINT32)(mips3->r[17] >> 32), (UINT32)mips3->r[17],
904      (UINT32)(mips3->r[18] >> 32), (UINT32)mips3->r[18],
905      (UINT32)(mips3->r[19] >> 32), (UINT32)mips3->r[19]);
483      (UINT32)(m_core->r[16] >> 32), (UINT32)m_core->r[16],
484      (UINT32)(m_core->r[17] >> 32), (UINT32)m_core->r[17],
485      (UINT32)(m_core->r[18] >> 32), (UINT32)m_core->r[18],
486      (UINT32)(m_core->r[19] >> 32), (UINT32)m_core->r[19]);
906487   printf("r20=%08X%08X r21=%08X%08X r22=%08X%08X r23=%08X%08X\n",
907      (UINT32)(mips3->r[20] >> 32), (UINT32)mips3->r[20],
908      (UINT32)(mips3->r[21] >> 32), (UINT32)mips3->r[21],
909      (UINT32)(mips3->r[22] >> 32), (UINT32)mips3->r[22],
910      (UINT32)(mips3->r[23] >> 32), (UINT32)mips3->r[23]);
488      (UINT32)(m_core->r[20] >> 32), (UINT32)m_core->r[20],
489      (UINT32)(m_core->r[21] >> 32), (UINT32)m_core->r[21],
490      (UINT32)(m_core->r[22] >> 32), (UINT32)m_core->r[22],
491      (UINT32)(m_core->r[23] >> 32), (UINT32)m_core->r[23]);
911492   printf("r24=%08X%08X r25=%08X%08X r26=%08X%08X r27=%08X%08X\n",
912      (UINT32)(mips3->r[24] >> 32), (UINT32)mips3->r[24],
913      (UINT32)(mips3->r[25] >> 32), (UINT32)mips3->r[25],
914      (UINT32)(mips3->r[26] >> 32), (UINT32)mips3->r[26],
915      (UINT32)(mips3->r[27] >> 32), (UINT32)mips3->r[27]);
493      (UINT32)(m_core->r[24] >> 32), (UINT32)m_core->r[24],
494      (UINT32)(m_core->r[25] >> 32), (UINT32)m_core->r[25],
495      (UINT32)(m_core->r[26] >> 32), (UINT32)m_core->r[26],
496      (UINT32)(m_core->r[27] >> 32), (UINT32)m_core->r[27]);
916497   printf("r28=%08X%08X r29=%08X%08X r30=%08X%08X r31=%08X%08X\n",
917      (UINT32)(mips3->r[28] >> 32), (UINT32)mips3->r[28],
918      (UINT32)(mips3->r[29] >> 32), (UINT32)mips3->r[29],
919      (UINT32)(mips3->r[30] >> 32), (UINT32)mips3->r[30],
920      (UINT32)(mips3->r[31] >> 32), (UINT32)mips3->r[31]);
498      (UINT32)(m_core->r[28] >> 32), (UINT32)m_core->r[28],
499      (UINT32)(m_core->r[29] >> 32), (UINT32)m_core->r[29],
500      (UINT32)(m_core->r[30] >> 32), (UINT32)m_core->r[30],
501      (UINT32)(m_core->r[31] >> 32), (UINT32)m_core->r[31]);
921502   printf(" hi=%08X%08X  lo=%08X%08X\n",
922      (UINT32)(mips3->r[REG_HI] >> 32), (UINT32)mips3->r[REG_HI],
923      (UINT32)(mips3->r[REG_LO] >> 32), (UINT32)mips3->r[REG_LO]);
503      (UINT32)(m_core->r[REG_HI] >> 32), (UINT32)m_core->r[REG_HI],
504      (UINT32)(m_core->r[REG_LO] >> 32), (UINT32)m_core->r[REG_LO]);
924505}
925506
507static void cfunc_printf_probe(void *param)
508{
509   ((mips3_device *)param)->func_printf_probe();
510}
926511
927512/*-------------------------------------------------
928513    cfunc_unimplemented - handler for
929514    unimplemented opcdes
930515-------------------------------------------------*/
931516
517void mips3_device::func_unimplemented()
518{
519   UINT32 opcode = m_core->arg0;
520   fatalerror("PC=%08X: Unimplemented op %08X (%02X,%02X)\n", m_core->pc, opcode, opcode >> 26, opcode & 0x3f);
521}
522
932523static void cfunc_unimplemented(void *param)
933524{
934   mips3_state *mips3 = (mips3_state *)param;
935   UINT32 opcode = mips3->impstate->arg0;
936   fatalerror("PC=%08X: Unimplemented op %08X (%02X,%02X)\n", mips3->pc, opcode, opcode >> 26, opcode & 0x3f);
525   ((mips3_device *)param)->func_unimplemented();
937526}
938527
939528
940
941529/***************************************************************************
942530    STATIC CODEGEN
943531***************************************************************************/
r30757r30758
947535    static entry point
948536-------------------------------------------------*/
949537
950static void static_generate_entry_point(mips3_state *mips3)
538void mips3_device::static_generate_entry_point()
951539{
952   drcuml_state *drcuml = mips3->impstate->drcuml;
540   drcuml_state *drcuml = m_drcuml;
953541   code_label skip = 1;
954542   drcuml_block *block;
955543
956544   block = drcuml->begin_block(20);
957545
958546   /* forward references */
959   alloc_handle(drcuml, &mips3->impstate->exception_norecover[EXCEPTION_INTERRUPT], "interrupt_norecover");
960   alloc_handle(drcuml, &mips3->impstate->nocode, "nocode");
547   alloc_handle(drcuml, &m_exception_norecover[EXCEPTION_INTERRUPT], "interrupt_norecover");
548   alloc_handle(drcuml, &m_nocode, "nocode");
961549
962   alloc_handle(drcuml, &mips3->impstate->entry, "entry");
963   UML_HANDLE(block, *mips3->impstate->entry);                                     // handle  entry
550   alloc_handle(drcuml, &m_entry, "entry");
551   UML_HANDLE(block, *m_entry);                                     // handle  entry
964552
965553   /* reset the FPU mode */
966554   UML_AND(block, I0, CCR132(31), 3);                                  // and     i0,ccr1[31],3
967   UML_LOAD(block, I0, &mips3->impstate->fpmode[0], I0, SIZE_BYTE, SCALE_x1);// load    i0,fpmode,i0,byte
555   UML_LOAD(block, I0, &m_fpmode[0], I0, SIZE_BYTE, SCALE_x1);// load    i0,fpmode,i0,byte
968556   UML_SETFMOD(block, I0);                                                 // setfmod i0
969557
970558   /* load fast integer registers */
971   load_fast_iregs(mips3, block);
559   load_fast_iregs(block);
972560
973561   /* check for interrupts */
974562   UML_AND(block, I0, CPR032(COP0_Cause), CPR032(COP0_Status));                // and     i0,[Cause],[Status]
r30757r30758
978566   UML_JMPc(block, COND_Z, skip);                                                  // jmp     skip,Z
979567   UML_TEST(block, CPR032(COP0_Status), SR_EXL | SR_ERL);                      // test    [Status],SR_EXL | SR_ERL
980568   UML_JMPc(block, COND_NZ, skip);                                                 // jmp     skip,NZ
981   UML_MOV(block, I0, mem(&mips3->pc));                                        // mov     i0,pc
569   UML_MOV(block, I0, mem(&m_core->pc));                                        // mov     i0,pc
982570   UML_MOV(block, I1, 0);                                              // mov     i1,0
983   UML_CALLH(block, *mips3->impstate->exception_norecover[EXCEPTION_INTERRUPT]);   // callh   exception_norecover
571   UML_CALLH(block, *m_exception_norecover[EXCEPTION_INTERRUPT]);   // callh   exception_norecover
984572   UML_LABEL(block, skip);                                                     // skip:
985573
986574   /* generate a hash jump via the current mode and PC */
987   UML_HASHJMP(block, mem(&mips3->impstate->mode), mem(&mips3->pc), *mips3->impstate->nocode);
575   UML_HASHJMP(block, mem(&m_core->mode), mem(&m_core->pc), *m_nocode);
988576                                                               // hashjmp <mode>,<pc>,nocode
989577   block->end();
990578}
r30757r30758
995583    exception handler for "out of code"
996584-------------------------------------------------*/
997585
998static void static_generate_nocode_handler(mips3_state *mips3)
586void mips3_device::static_generate_nocode_handler()
999587{
1000   drcuml_state *drcuml = mips3->impstate->drcuml;
588   drcuml_state *drcuml = m_drcuml;
1001589   drcuml_block *block;
1002590
1003591   /* begin generating */
1004592   block = drcuml->begin_block(10);
1005593
1006594   /* generate a hash jump via the current mode and PC */
1007   alloc_handle(drcuml, &mips3->impstate->nocode, "nocode");
1008   UML_HANDLE(block, *mips3->impstate->nocode);                                        // handle  nocode
595   alloc_handle(drcuml, &m_nocode, "nocode");
596   UML_HANDLE(block, *m_nocode);                                        // handle  nocode
1009597   UML_GETEXP(block, I0);                                                      // getexp  i0
1010   UML_MOV(block, mem(&mips3->pc), I0);                                        // mov     [pc],i0
1011   save_fast_iregs(mips3, block);
598   UML_MOV(block, mem(&m_core->pc), I0);                                        // mov     [pc],i0
599   save_fast_iregs(block);
1012600   UML_EXIT(block, EXECUTE_MISSING_CODE);                                      // exit    EXECUTE_MISSING_CODE
1013601
1014602   block->end();
r30757r30758
1020608    out of cycles exception handler
1021609-------------------------------------------------*/
1022610
1023static void static_generate_out_of_cycles(mips3_state *mips3)
611void mips3_device::static_generate_out_of_cycles()
1024612{
1025   drcuml_state *drcuml = mips3->impstate->drcuml;
613   drcuml_state *drcuml = m_drcuml;
1026614   drcuml_block *block;
1027615
1028616   /* begin generating */
1029617   block = drcuml->begin_block(10);
1030618
1031619   /* generate a hash jump via the current mode and PC */
1032   alloc_handle(drcuml, &mips3->impstate->out_of_cycles, "out_of_cycles");
1033   UML_HANDLE(block, *mips3->impstate->out_of_cycles);                             // handle  out_of_cycles
620   alloc_handle(drcuml, &m_out_of_cycles, "out_of_cycles");
621   UML_HANDLE(block, *m_out_of_cycles);                             // handle  out_of_cycles
1034622   UML_GETEXP(block, I0);                                                      // getexp  i0
1035   UML_MOV(block, mem(&mips3->pc), I0);                                        // mov     <pc>,i0
1036   save_fast_iregs(mips3, block);
623   UML_MOV(block, mem(&m_core->pc), I0);                                        // mov     <pc>,i0
624   save_fast_iregs(block);
1037625   UML_EXIT(block, EXECUTE_OUT_OF_CYCLES);                                 // exit    EXECUTE_OUT_OF_CYCLES
1038626
1039627   block->end();
r30757r30758
1045633    TLB mismatch handler
1046634-------------------------------------------------*/
1047635
1048static void static_generate_tlb_mismatch(mips3_state *mips3)
636void mips3_device::static_generate_tlb_mismatch()
1049637{
1050   drcuml_state *drcuml = mips3->impstate->drcuml;
638   drcuml_state *drcuml = m_drcuml;
1051639   drcuml_block *block;
1052640
1053641   /* forward references */
1054   alloc_handle(drcuml, &mips3->impstate->exception[EXCEPTION_TLBLOAD], "exception_tlbload");
1055   alloc_handle(drcuml, &mips3->impstate->exception[EXCEPTION_TLBLOAD_FILL], "exception_tlbload_fill");
642   alloc_handle(drcuml, &m_exception[EXCEPTION_TLBLOAD], "exception_tlbload");
643   alloc_handle(drcuml, &m_exception[EXCEPTION_TLBLOAD_FILL], "exception_tlbload_fill");
1056644
1057645   /* begin generating */
1058646   block = drcuml->begin_block(20);
1059647
1060648   /* generate a hash jump via the current mode and PC */
1061   alloc_handle(drcuml, &mips3->impstate->tlb_mismatch, "tlb_mismatch");
1062   UML_HANDLE(block, *mips3->impstate->tlb_mismatch);                              // handle  tlb_mismatch
649   alloc_handle(drcuml, &m_tlb_mismatch, "tlb_mismatch");
650   UML_HANDLE(block, *m_tlb_mismatch);                              // handle  tlb_mismatch
1063651   UML_RECOVER(block, I0, MAPVAR_PC);                                          // recover i0,PC
1064   UML_MOV(block, mem(&mips3->pc), I0);                                        // mov     <pc>,i0
652   UML_MOV(block, mem(&m_core->pc), I0);                                        // mov     <pc>,i0
1065653   UML_SHR(block, I1, I0, 12);                                     // shr     i1,i0,12
1066   UML_LOAD(block, I1, (void *)vtlb_table(mips3->vtlb), I1, SIZE_DWORD, SCALE_x4);// load    i1,[vtlb_table],i1,dword
654   UML_LOAD(block, I1, (void *)vtlb_table(m_vtlb), I1, SIZE_DWORD, SCALE_x4);// load    i1,[vtlb_table],i1,dword
1067655   if (PRINTF_MMU)
1068656   {
1069657      static const char text[] = "TLB mismatch @ %08X (ent=%08X)\n";
1070      UML_MOV(block, mem(&mips3->impstate->format), (FPTR)text);              // mov     [format],text
1071      UML_MOV(block, mem(&mips3->impstate->arg0), I0);                        // mov     [arg0],i0
1072      UML_MOV(block, mem(&mips3->impstate->arg1), I1);                        // mov     [arg1],i1
1073      UML_CALLC(block, cfunc_printf_debug, mips3);                                // callc   printf_debug
658      UML_MOV(block, mem(&m_core->format), (FPTR)text);              // mov     [format],text
659      UML_MOV(block, mem(&m_core->arg0), I0);                        // mov     [arg0],i0
660      UML_MOV(block, mem(&m_core->arg1), I1);                        // mov     [arg1],i1
661      UML_CALLC(block, cfunc_printf_debug, this);                                // callc   printf_debug
1074662   }
1075663   UML_TEST(block, I1, VTLB_FETCH_ALLOWED);                                // test    i1,VTLB_FETCH_ALLOWED
1076664   UML_JMPc(block, COND_NZ, 1);                                                        // jmp     1,nz
1077665   UML_TEST(block, I1, VTLB_FLAG_FIXED);                                   // test    i1,VTLB_FLAG_FIXED
1078   UML_EXHc(block, COND_NZ, *mips3->impstate->exception[EXCEPTION_TLBLOAD], I0);   // exh     exception[TLBLOAD],i0,nz
1079   UML_EXH(block, *mips3->impstate->exception[EXCEPTION_TLBLOAD_FILL], I0);    // exh     exception[TLBLOAD_FILL],i0
666   UML_EXHc(block, COND_NZ, *m_exception[EXCEPTION_TLBLOAD], I0);   // exh     exception[TLBLOAD],i0,nz
667   UML_EXH(block, *m_exception[EXCEPTION_TLBLOAD_FILL], I0);    // exh     exception[TLBLOAD_FILL],i0
1080668   UML_LABEL(block, 1);                                                        // 1:
1081   save_fast_iregs(mips3, block);
669   save_fast_iregs(block);
1082670
1083671   // the saved PC may be set 1 instruction back with the low bit set to indicate
1084672   // a delay slot; in this path we want the original instruction address, so recover it
1085   UML_ADD(block, I0, mem(&mips3->pc), 3);                             // add     i0,<pc>,3
1086   UML_AND(block, mem(&mips3->pc), I0, ~3);                                // and     <pc>,i0,~3
673   UML_ADD(block, I0, mem(&m_core->pc), 3);                             // add     i0,<pc>,3
674   UML_AND(block, mem(&m_core->pc), I0, ~3);                                // and     <pc>,i0,~3
1087675   UML_EXIT(block, EXECUTE_MISSING_CODE);                                      // exit    EXECUTE_MISSING_CODE
1088676
1089677   block->end();
r30757r30758
1095683    exception handler
1096684-------------------------------------------------*/
1097685
1098static void static_generate_exception(mips3_state *mips3, UINT8 exception, int recover, const char *name)
686void mips3_device::static_generate_exception(UINT8 exception, int recover, const char *name)
1099687{
1100   code_handle *&exception_handle = recover ? mips3->impstate->exception[exception] : mips3->impstate->exception_norecover[exception];
1101   drcuml_state *drcuml = mips3->impstate->drcuml;
688   code_handle *&exception_handle = recover ? m_exception[exception] : m_exception_norecover[exception];
689   drcuml_state *drcuml = m_drcuml;
1102690   UINT32 offset = 0x180;
1103691   code_label next = 1;
1104692   code_label skip = 2;
r30757r30758
1163751   /* set EXL in the SR */
1164752   UML_OR(block, I0, CPR032(COP0_Status), SR_EXL);                     // or      i0,[Status],SR_EXL
1165753   UML_MOV(block, CPR032(COP0_Status), I0);                                    // mov     [Status],i0
1166   generate_update_mode(mips3, block);
754   generate_update_mode(block);
1167755
1168756   /* optionally print exceptions */
1169757   if ((PRINTF_EXCEPTIONS && exception != EXCEPTION_INTERRUPT && exception != EXCEPTION_SYSCALL) ||
1170758      (PRINTF_MMU && (exception == EXCEPTION_TLBLOAD || exception == EXCEPTION_TLBSTORE)))
1171759   {
1172      UML_CALLC(block, cfunc_printf_exception, mips3);                            // callc   cfunc_printf_exception,NULL
760      UML_CALLC(block, cfunc_printf_exception, this);                            // callc   cfunc_printf_exception,NULL
1173761   }
1174762
1175763   /* choose our target PC */
r30757r30758
1180768   UML_LABEL(block, skip);                                                     // <skip>:
1181769
1182770   /* adjust cycles */
1183   UML_SUB(block, mem(&mips3->icount), mem(&mips3->icount), I1);               // sub icount,icount,cycles,S
1184   UML_EXHc(block, COND_S, *mips3->impstate->out_of_cycles, I0);                   // exh     out_of_cycles,i0
771   UML_SUB(block, mem(&m_core->icount), mem(&m_core->icount), I1);               // sub icount,icount,cycles,S
772   UML_EXHc(block, COND_S, *m_out_of_cycles, I0);                   // exh     out_of_cycles,i0
1185773
1186   UML_HASHJMP(block, mem(&mips3->impstate->mode), I0, *mips3->impstate->nocode);// hashjmp <mode>,i0,nocode
774   UML_HASHJMP(block, mem(&m_core->mode), I0, *m_nocode);// hashjmp <mode>,i0,nocode
1187775
1188776   block->end();
1189777}
r30757r30758
1193781    static_generate_memory_accessor
1194782------------------------------------------------------------------*/
1195783
1196static void static_generate_memory_accessor(mips3_state *mips3, int mode, int size, int iswrite, int ismasked, const char *name, code_handle **handleptr)
784void mips3_device::static_generate_memory_accessor(int mode, int size, int iswrite, int ismasked, const char *name, code_handle **handleptr)
1197785{
1198786   /* on entry, address is in I0; data for writes is in I1; mask for accesses is in I2 */
1199787   /* on exit, read result is in I0 */
1200788   /* routine trashes I0-I3 */
1201   code_handle &exception_tlb = *mips3->impstate->exception[iswrite ? EXCEPTION_TLBSTORE : EXCEPTION_TLBLOAD];
1202   code_handle &exception_tlbfill = *mips3->impstate->exception[iswrite ? EXCEPTION_TLBSTORE_FILL : EXCEPTION_TLBLOAD_FILL];
1203   code_handle &exception_addrerr = *mips3->impstate->exception[iswrite ? EXCEPTION_ADDRSTORE : EXCEPTION_ADDRLOAD];
1204   drcuml_state *drcuml = mips3->impstate->drcuml;
789   code_handle &exception_tlb = *m_exception[iswrite ? EXCEPTION_TLBSTORE : EXCEPTION_TLBLOAD];
790   code_handle &exception_tlbfill = *m_exception[iswrite ? EXCEPTION_TLBSTORE_FILL : EXCEPTION_TLBLOAD_FILL];
791   code_handle &exception_addrerr = *m_exception[iswrite ? EXCEPTION_ADDRSTORE : EXCEPTION_ADDRLOAD];
792   drcuml_state *drcuml = m_drcuml;
1205793   drcuml_block *block;
1206794   int tlbmiss = 0;
1207795   int label = 1;
r30757r30758
1235823
1236824   /* general case: assume paging and perform a translation */
1237825   UML_SHR(block, I3, I0, 12);                                     // shr     i3,i0,12
1238   UML_LOAD(block, I3, (void *)vtlb_table(mips3->vtlb), I3, SIZE_DWORD, SCALE_x4);// load    i3,[vtlb_table],i3,dword
826   UML_LOAD(block, I3, (void *)vtlb_table(m_vtlb), I3, SIZE_DWORD, SCALE_x4);// load    i3,[vtlb_table],i3,dword
1239827   UML_TEST(block, I3, iswrite ? VTLB_WRITE_ALLOWED : VTLB_READ_ALLOWED);// test    i3,iswrite ? VTLB_WRITE_ALLOWED : VTLB_READ_ALLOWED
1240828   UML_JMPc(block, COND_Z, tlbmiss = label++);                                     // jmp     tlbmiss,z
1241829   UML_ROLINS(block, I0, I3, 0, 0xfffff000);                   // rolins  i0,i3,0,0xfffff000
1242830
1243   if ((mips3->device->machine().debug_flags & DEBUG_FLAG_ENABLED) == 0)
831   if ((machine().debug_flags & DEBUG_FLAG_ENABLED) == 0)
1244832      for (ramnum = 0; ramnum < MIPS3_MAX_FASTRAM; ramnum++)
1245         if (mips3->impstate->fastram[ramnum].base != NULL && (!iswrite || !mips3->impstate->fastram[ramnum].readonly))
833         if (m_fastram[ramnum].base != NULL && (!iswrite || !m_fastram[ramnum].readonly))
1246834         {
1247            void *fastbase = (UINT8 *)mips3->impstate->fastram[ramnum].base - mips3->impstate->fastram[ramnum].start;
835            void *fastbase = (UINT8 *)m_fastram[ramnum].base - m_fastram[ramnum].start;
1248836            UINT32 skip = label++;
1249            if (mips3->impstate->fastram[ramnum].end != 0xffffffff)
837            if (m_fastram[ramnum].end != 0xffffffff)
1250838            {
1251               UML_CMP(block, I0, mips3->impstate->fastram[ramnum].end);   // cmp     i0,end
839               UML_CMP(block, I0, m_fastram[ramnum].end);   // cmp     i0,end
1252840               UML_JMPc(block, COND_A, skip);                                      // ja      skip
1253841            }
1254            if (mips3->impstate->fastram[ramnum].start != 0x00000000)
842            if (m_fastram[ramnum].start != 0x00000000)
1255843            {
1256               UML_CMP(block, I0, mips3->impstate->fastram[ramnum].start);// cmp     i0,fastram_start
844               UML_CMP(block, I0, m_fastram[ramnum].start);// cmp     i0,fastram_start
1257845               UML_JMPc(block, COND_B, skip);                                      // jb      skip
1258846            }
1259847
r30757r30758
1261849            {
1262850               if (size == 1)
1263851               {
1264                  UML_XOR(block, I0, I0, mips3->bigendian ? BYTE4_XOR_BE(0) : BYTE4_XOR_LE(0));
852                  UML_XOR(block, I0, I0, m_bigendian ? BYTE4_XOR_BE(0) : BYTE4_XOR_LE(0));
1265853                                                                  // xor     i0,i0,bytexor
1266854                  UML_LOAD(block, I0, fastbase, I0, SIZE_BYTE, SCALE_x1);             // load    i0,fastbase,i0,byte
1267855               }
1268856               else if (size == 2)
1269857               {
1270                  UML_XOR(block, I0, I0, mips3->bigendian ? WORD_XOR_BE(0) : WORD_XOR_LE(0));
858                  UML_XOR(block, I0, I0, m_bigendian ? WORD_XOR_BE(0) : WORD_XOR_LE(0));
1271859                                                                  // xor     i0,i0,wordxor
1272860                  UML_LOAD(block, I0, fastbase, I0, SIZE_WORD, SCALE_x1);         // load    i0,fastbase,i0,word_x1
1273861               }
r30757r30758
1278866               else if (size == 8)
1279867               {
1280868                  UML_DLOAD(block, I0, fastbase, I0, SIZE_QWORD, SCALE_x1);           // dload   i0,fastbase,i0,qword_x1
1281                  UML_DROR(block, I0, I0, 32 * (mips3->bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0)));
869                  UML_DROR(block, I0, I0, 32 * (m_bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0)));
1282870                                                                  // dror    i0,i0,32*bytexor
1283871               }
1284872               UML_RET(block);                                                     // ret
r30757r30758
1287875            {
1288876               if (size == 1)
1289877               {
1290                  UML_XOR(block, I0, I0, mips3->bigendian ? BYTE4_XOR_BE(0) : BYTE4_XOR_LE(0));
878                  UML_XOR(block, I0, I0, m_bigendian ? BYTE4_XOR_BE(0) : BYTE4_XOR_LE(0));
1291879                                                                  // xor     i0,i0,bytexor
1292880                  UML_STORE(block, fastbase, I0, I1, SIZE_BYTE, SCALE_x1);// store   fastbase,i0,i1,byte
1293881               }
1294882               else if (size == 2)
1295883               {
1296                  UML_XOR(block, I0, I0, mips3->bigendian ? WORD_XOR_BE(0) : WORD_XOR_LE(0));
884                  UML_XOR(block, I0, I0, m_bigendian ? WORD_XOR_BE(0) : WORD_XOR_LE(0));
1297885                                                                  // xor     i0,i0,wordxor
1298886                  UML_STORE(block, fastbase, I0, I1, SIZE_WORD, SCALE_x1);// store   fastbase,i0,i1,word_x1
1299887               }
r30757r30758
1310898               }
1311899               else if (size == 8)
1312900               {
1313                  UML_DROR(block, I1, I1, 32 * (mips3->bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0)));
901                  UML_DROR(block, I1, I1, 32 * (m_bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0)));
1314902                                                                  // dror    i1,i1,32*bytexor
1315903                  if (ismasked)
1316904                  {
1317                     UML_DROR(block, I2, I2, 32 * (mips3->bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0)));
905                     UML_DROR(block, I2, I2, 32 * (m_bigendian ? BYTE_XOR_BE(0) : BYTE_XOR_LE(0)));
1318906                                                                  // dror    i2,i2,32*bytexor
1319907                     UML_DLOAD(block, I3, fastbase, I0, SIZE_QWORD, SCALE_x1);       // dload   i3,fastbase,i0,qword_x1
1320908                     UML_DROLINS(block, I3, I1, 0, I2);      // drolins i3,i1,0,i2
r30757r30758
1387975      if (iswrite)
1388976      {
1389977         UML_TEST(block, I3, VTLB_READ_ALLOWED);                     // test    i3,VTLB_READ_ALLOWED
1390         UML_EXHc(block, COND_NZ, *mips3->impstate->exception[EXCEPTION_TLBMOD], I0);
978         UML_EXHc(block, COND_NZ, *m_exception[EXCEPTION_TLBMOD], I0);
1391979                                                               // exh     tlbmod,i0,nz
1392980      }
1393981      UML_TEST(block, I3, VTLB_FLAG_FIXED);                               // test    i3,VTLB_FLAG_FIXED
r30757r30758
1409997    on a new SR (in i0); trashes i2
1410998-------------------------------------------------*/
1411999
1412static void generate_update_mode(mips3_state *mips3, drcuml_block *block)
1000void mips3_device::generate_update_mode(drcuml_block *block)
14131001{
14141002   UML_ROLAND(block, I2, I0, 32-2, 0x06);                      // roland  i2,i0,32-2,0x06
14151003   UML_TEST(block, I0, SR_EXL | SR_ERL);                                   // test    i0,SR_EXL | SR_ERL
14161004   UML_MOVc(block, COND_NZ, I2, 0);                                        // mov     i2,0,nz
14171005   UML_ROLINS(block, I2, I0, 32-26, 0x01);                     // rolins  i2,i0,32-26,0x01
1418   UML_MOV(block, mem(&mips3->impstate->mode), I2);                            // mov     [mode],i2
1006   UML_MOV(block, mem(&m_core->mode), I2);                            // mov     [mode],i2
14191007}
14201008
14211009
r30757r30758
14251013    an exception if out
14261014-------------------------------------------------*/
14271015
1428static void generate_update_cycles(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, parameter param, int allow_exception)
1016void mips3_device::generate_update_cycles(drcuml_block *block, compiler_state *compiler, parameter param, int allow_exception)
14291017{
14301018   /* check software interrupts if pending */
14311019   if (compiler->checksoftints)
r30757r30758
14381026      UML_JMPc(block, COND_Z, skip = compiler->labelnum++);                           // jmp     skip,Z
14391027      UML_MOV(block, I0, param);                              // mov     i0,nextpc
14401028      UML_MOV(block, I1, compiler->cycles);                               // mov     i1,cycles
1441      UML_CALLH(block, *mips3->impstate->exception_norecover[EXCEPTION_INTERRUPT]);// callh   interrupt_norecover
1029      UML_CALLH(block, *m_exception_norecover[EXCEPTION_INTERRUPT]);// callh   interrupt_norecover
14421030      UML_LABEL(block, skip);                                                 // skip:
14431031   }
14441032
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14571045      UML_JMPc(block, COND_NZ, skip);                                             // jmp     skip,NZ
14581046      UML_MOV(block, I0, param);                              // mov     i0,nextpc
14591047      UML_MOV(block, I1, compiler->cycles);                               // mov     i1,cycles
1460      UML_CALLH(block, *mips3->impstate->exception_norecover[EXCEPTION_INTERRUPT]);// callh   interrupt_norecover
1048      UML_CALLH(block, *m_exception_norecover[EXCEPTION_INTERRUPT]);// callh   interrupt_norecover
14611049      UML_LABEL(block, skip);                                                 // skip:
14621050   }
14631051
14641052   /* account for cycles */
14651053   if (compiler->cycles > 0)
14661054   {
1467      UML_SUB(block, mem(&mips3->icount), mem(&mips3->icount), MAPVAR_CYCLES);    // sub     icount,icount,cycles
1055      UML_SUB(block, mem(&m_core->icount), mem(&m_core->icount), MAPVAR_CYCLES);    // sub     icount,icount,cycles
14681056      UML_MAPVAR(block, MAPVAR_CYCLES, 0);                                        // mapvar  cycles,0
14691057      if (allow_exception)
1470         UML_EXHc(block, COND_S, *mips3->impstate->out_of_cycles, param);
1058         UML_EXHc(block, COND_S, *m_out_of_cycles, param);
14711059                                                               // exh     out_of_cycles,nextpc
14721060   }
14731061   compiler->cycles = 0;
r30757r30758
14791067    validate a sequence of opcodes
14801068-------------------------------------------------*/
14811069
1482static void generate_checksum_block(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast)
1070void mips3_device::generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast)
14831071{
14841072   const opcode_desc *curdesc;
14851073   if (LOG_UML)
14861074      block->append_comment("[Validation for %08X]", seqhead->pc);                // comment
14871075
14881076   /* loose verify or single instruction: just compare and fail */
1489   if (!(mips3->impstate->drcoptions & MIPS3DRC_STRICT_VERIFY) || seqhead->next() == NULL)
1077   if (!(m_drcoptions & MIPS3DRC_STRICT_VERIFY) || seqhead->next() == NULL)
14901078   {
14911079      if (!(seqhead->flags & OPFLAG_VIRTUAL_NOOP))
14921080      {
14931081         UINT32 sum = seqhead->opptr.l[0];
1494         void *base = mips3->direct->read_decrypted_ptr(seqhead->physpc);
1082         void *base = m_direct->read_decrypted_ptr(seqhead->physpc);
14951083         UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4);         // load    i0,base,0,dword
14961084
14971085         if (seqhead->delay.first() != NULL && seqhead->physpc != seqhead->delay.first()->physpc)
14981086         {
1499            base = mips3->direct->read_decrypted_ptr(seqhead->delay.first()->physpc);
1087            base = m_direct->read_decrypted_ptr(seqhead->delay.first()->physpc);
15001088            UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4);                 // load    i1,base,dword
15011089            UML_ADD(block, I0, I0, I1);                     // add     i0,i0,i1
15021090
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15041092         }
15051093
15061094         UML_CMP(block, I0, sum);                                    // cmp     i0,opptr[0]
1507         UML_EXHc(block, COND_NE, *mips3->impstate->nocode, epc(seqhead));       // exne    nocode,seqhead->pc
1095         UML_EXHc(block, COND_NE, *m_nocode, epc(seqhead));       // exne    nocode,seqhead->pc
15081096      }
15091097   }
15101098
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15151103      for (curdesc = seqhead->next(); curdesc != seqlast->next(); curdesc = curdesc->next())
15161104         if (!(curdesc->flags & OPFLAG_VIRTUAL_NOOP))
15171105         {
1518            void *base = mips3->direct->read_decrypted_ptr(seqhead->physpc);
1106            void *base = m_direct->read_decrypted_ptr(seqhead->physpc);
15191107            UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4);     // load    i0,base,0,dword
15201108            UML_CMP(block, I0, curdesc->opptr.l[0]);                    // cmp     i0,opptr[0]
1521            UML_EXHc(block, COND_NE, *mips3->impstate->nocode, epc(seqhead));   // exne    nocode,seqhead->pc
1109            UML_EXHc(block, COND_NE, *m_nocode, epc(seqhead));   // exne    nocode,seqhead->pc
15221110         }
15231111#else
15241112      UINT32 sum = 0;
1525      void *base = mips3->direct->read_decrypted_ptr(seqhead->physpc);
1113      void *base = m_direct->read_decrypted_ptr(seqhead->physpc);
15261114      UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4);             // load    i0,base,0,dword
15271115      sum += seqhead->opptr.l[0];
15281116      for (curdesc = seqhead->next(); curdesc != seqlast->next(); curdesc = curdesc->next())
15291117         if (!(curdesc->flags & OPFLAG_VIRTUAL_NOOP))
15301118         {
1531            base = mips3->direct->read_decrypted_ptr(curdesc->physpc);
1119            base = m_direct->read_decrypted_ptr(curdesc->physpc);
15321120            UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4);     // load    i1,base,dword
15331121            UML_ADD(block, I0, I0, I1);                         // add     i0,i0,i1
15341122            sum += curdesc->opptr.l[0];
15351123
15361124            if (curdesc->delay.first() != NULL && (curdesc == seqlast || (curdesc->next() != NULL && curdesc->next()->physpc != curdesc->delay.first()->physpc)))
15371125            {
1538               base = mips3->direct->read_decrypted_ptr(curdesc->delay.first()->physpc);
1126               base = m_direct->read_decrypted_ptr(curdesc->delay.first()->physpc);
15391127               UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4); // load    i1,base,dword
15401128               UML_ADD(block, I0, I0, I1);                     // add     i0,i0,i1
15411129               sum += curdesc->delay.first()->opptr.l[0];
15421130            }
15431131         }
15441132      UML_CMP(block, I0, sum);                                            // cmp     i0,sum
1545      UML_EXHc(block, COND_NE, *mips3->impstate->nocode, epc(seqhead));           // exne    nocode,seqhead->pc
1133      UML_EXHc(block, COND_NE, *m_nocode, epc(seqhead));           // exne    nocode,seqhead->pc
15461134#endif
15471135   }
15481136}
r30757r30758
15531141    for a single instruction in a sequence
15541142-------------------------------------------------*/
15551143
1556static void generate_sequence_instruction(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
1144void mips3_device::generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
15571145{
15581146   offs_t expc;
15591147   int hotnum;
15601148
15611149   /* add an entry for the log */
15621150   if (LOG_UML && !(desc->flags & OPFLAG_VIRTUAL_NOOP))
1563      log_add_disasm_comment(mips3, block, desc->pc, desc->opptr.l[0]);
1151      log_add_disasm_comment(block, desc->pc, desc->opptr.l[0]);
15641152
15651153   /* set the PC map variable */
15661154   expc = (desc->flags & OPFLAG_IN_DELAY_SLOT) ? desc->pc - 3 : desc->pc;
r30757r30758
15711159
15721160   /* is this a hotspot? */
15731161   for (hotnum = 0; hotnum < MIPS3_MAX_HOTSPOTS; hotnum++)
1574      if (mips3->impstate->hotspot[hotnum].pc != 0 && desc->pc == mips3->impstate->hotspot[hotnum].pc && desc->opptr.l[0] == mips3->impstate->hotspot[hotnum].opcode)
1162      if (m_hotspot[hotnum].pc != 0 && desc->pc == m_hotspot[hotnum].pc && desc->opptr.l[0] == m_hotspot[hotnum].opcode)
15751163      {
1576         compiler->cycles += mips3->impstate->hotspot[hotnum].cycles;
1164         compiler->cycles += m_hotspot[hotnum].cycles;
15771165         break;
15781166      }
15791167
r30757r30758
15831171   /* if we want a probe, add it here */
15841172   if (desc->pc == PROBE_ADDRESS)
15851173   {
1586      UML_MOV(block, mem(&mips3->pc), desc->pc);                              // mov     [pc],desc->pc
1587      UML_CALLC(block, cfunc_printf_probe, mips3);                                // callc   cfunc_printf_probe,mips3
1174      UML_MOV(block, mem(&m_core->pc), desc->pc);                              // mov     [pc],desc->pc
1175      UML_CALLC(block, cfunc_printf_probe, this);                                // callc   cfunc_printf_probe,mips3
15881176   }
15891177
15901178   /* if we are debugging, call the debugger */
1591   if ((mips3->device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
1179   if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
15921180   {
1593      UML_MOV(block, mem(&mips3->pc), desc->pc);                              // mov     [pc],desc->pc
1594      save_fast_iregs(mips3, block);
1181      UML_MOV(block, mem(&m_core->pc), desc->pc);                              // mov     [pc],desc->pc
1182      save_fast_iregs(block);
15951183      UML_DEBUG(block, desc->pc);                                         // debug   desc->pc
15961184   }
15971185
15981186   /* if we hit an unmapped address, fatal error */
15991187   if (desc->flags & OPFLAG_COMPILER_UNMAPPED)
16001188   {
1601      UML_MOV(block, mem(&mips3->pc), desc->pc);                              // mov     [pc],desc->pc
1602      save_fast_iregs(mips3, block);
1189      UML_MOV(block, mem(&m_core->pc), desc->pc);                              // mov     [pc],desc->pc
1190      save_fast_iregs(block);
16031191      UML_EXIT(block, EXECUTE_UNMAPPED_CODE);                             // exit    EXECUTE_UNMAPPED_CODE
16041192   }
16051193
r30757r30758
16091197      if (PRINTF_MMU)
16101198      {
16111199         static const char text[] = "Compiler page fault @ %08X";
1612         UML_MOV(block, mem(&mips3->impstate->format), (FPTR)text);          // mov     [format],text
1613         UML_MOV(block, mem(&mips3->impstate->arg0), desc->pc);              // mov     [arg0],desc->pc
1614         UML_CALLC(block, cfunc_printf_debug, mips3);                            // callc   printf_debug
1200         UML_MOV(block, mem(&m_core->format), (FPTR)text);          // mov     [format],text
1201         UML_MOV(block, mem(&m_core->arg0), desc->pc);              // mov     [arg0],desc->pc
1202         UML_CALLC(block, cfunc_printf_debug, this);                            // callc   printf_debug
16151203      }
1616      UML_EXH(block, *mips3->impstate->tlb_mismatch, 0);                      // exh     tlb_mismatch,0
1204      UML_EXH(block, *m_tlb_mismatch, 0);                      // exh     tlb_mismatch,0
16171205   }
16181206
16191207   /* validate our TLB entry at this PC; if we fail, we need to handle it */
16201208   if ((desc->flags & OPFLAG_VALIDATE_TLB) && (desc->pc < 0x80000000 || desc->pc >= 0xc0000000))
16211209   {
1622      const vtlb_entry *tlbtable = vtlb_table(mips3->vtlb);
1210      const vtlb_entry *tlbtable = vtlb_table(m_vtlb);
16231211
16241212      /* if we currently have a valid TLB read entry, we just verify */
16251213      if (tlbtable[desc->pc >> 12] & VTLB_FETCH_ALLOWED)
r30757r30758
16271215         if (PRINTF_MMU)
16281216         {
16291217            static const char text[] = "Checking TLB at @ %08X\n";
1630            UML_MOV(block, mem(&mips3->impstate->format), (FPTR)text);      // mov     [format],text
1631            UML_MOV(block, mem(&mips3->impstate->arg0), desc->pc);          // mov     [arg0],desc->pc
1632            UML_CALLC(block, cfunc_printf_debug, mips3);                        // callc   printf_debug
1218            UML_MOV(block, mem(&m_core->format), (FPTR)text);      // mov     [format],text
1219            UML_MOV(block, mem(&m_core->arg0), desc->pc);          // mov     [arg0],desc->pc
1220            UML_CALLC(block, cfunc_printf_debug, this);                        // callc   printf_debug
16331221         }
16341222         UML_LOAD(block, I0, &tlbtable[desc->pc >> 12], 0, SIZE_DWORD, SCALE_x4);        // load i0,tlbtable[desc->pc >> 12],0,dword
16351223         UML_CMP(block, I0, tlbtable[desc->pc >> 12]);                   // cmp     i0,*tlbentry
1636         UML_EXHc(block, COND_NE, *mips3->impstate->tlb_mismatch, 0);            // exh     tlb_mismatch,0,NE
1224         UML_EXHc(block, COND_NE, *m_tlb_mismatch, 0);            // exh     tlb_mismatch,0,NE
16371225      }
16381226
16391227      /* otherwise, we generate an unconditional exception */
r30757r30758
16421230         if (PRINTF_MMU)
16431231         {
16441232            static const char text[] = "No valid TLB @ %08X\n";
1645            UML_MOV(block, mem(&mips3->impstate->format), (FPTR)text);      // mov     [format],text
1646            UML_MOV(block, mem(&mips3->impstate->arg0), desc->pc);          // mov     [arg0],desc->pc
1647            UML_CALLC(block, cfunc_printf_debug, mips3);                        // callc   printf_debug
1233            UML_MOV(block, mem(&m_core->format), (FPTR)text);      // mov     [format],text
1234            UML_MOV(block, mem(&m_core->arg0), desc->pc);          // mov     [arg0],desc->pc
1235            UML_CALLC(block, cfunc_printf_debug, this);                        // callc   printf_debug
16481236         }
1649         UML_EXH(block, *mips3->impstate->tlb_mismatch, 0);                  // exh     tlb_mismatch,0
1237         UML_EXH(block, *m_tlb_mismatch, 0);                  // exh     tlb_mismatch,0
16501238      }
16511239   }
16521240
16531241   /* if this is an invalid opcode, generate the exception now */
16541242   if (desc->flags & OPFLAG_INVALID_OPCODE)
1655      UML_EXH(block, *mips3->impstate->exception[EXCEPTION_INVALIDOP], 0);    // exh     invalidop,0
1243      UML_EXH(block, *m_exception[EXCEPTION_INVALIDOP], 0);    // exh     invalidop,0
16561244
16571245   /* otherwise, unless this is a virtual no-op, it's a regular instruction */
16581246   else if (!(desc->flags & OPFLAG_VIRTUAL_NOOP))
16591247   {
16601248      /* compile the instruction */
1661      if (!generate_opcode(mips3, block, compiler, desc))
1249      if (!generate_opcode(block, compiler, desc))
16621250      {
1663         UML_MOV(block, mem(&mips3->pc), desc->pc);                          // mov     [pc],desc->pc
1664         UML_MOV(block, mem(&mips3->impstate->arg0), desc->opptr.l[0]);      // mov     [arg0],desc->opptr.l
1665         UML_CALLC(block, cfunc_unimplemented, mips3);                           // callc   cfunc_unimplemented
1251         UML_MOV(block, mem(&m_core->pc), desc->pc);                          // mov     [pc],desc->pc
1252         UML_MOV(block, mem(&m_core->arg0), desc->opptr.l[0]);      // mov     [arg0],desc->opptr.l
1253         UML_CALLC(block, cfunc_unimplemented, this);                           // callc   cfunc_unimplemented
16661254      }
16671255   }
16681256}
r30757r30758
16721260    generate_delay_slot_and_branch
16731261------------------------------------------------------------------*/
16741262
1675static void generate_delay_slot_and_branch(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 linkreg)
1263void mips3_device::generate_delay_slot_and_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 linkreg)
16761264{
16771265   compiler_state compiler_temp = *compiler;
16781266   UINT32 op = desc->opptr.l[0];
r30757r30758
16801268   /* fetch the target register if dynamic, in case it is modified by the delay slot */
16811269   if (desc->targetpc == BRANCH_TARGET_DYNAMIC)
16821270   {
1683      UML_MOV(block, mem(&mips3->impstate->jmpdest), R32(RSREG));                 // mov     [jmpdest],<rsreg>
1271      UML_MOV(block, mem(&m_core->jmpdest), R32(RSREG));                 // mov     [jmpdest],<rsreg>
16841272
16851273   }
16861274
r30757r30758
16921280
16931281   /* compile the delay slot using temporary compiler state */
16941282   assert(desc->delay.first() != NULL);
1695   generate_sequence_instruction(mips3, block, &compiler_temp, desc->delay.first());       // <next instruction>
1283   generate_sequence_instruction(block, &compiler_temp, desc->delay.first());       // <next instruction>
16961284
16971285   /* update the cycles and jump through the hash table to the target */
16981286   if (desc->targetpc != BRANCH_TARGET_DYNAMIC)
16991287   {
1700      generate_update_cycles(mips3, block, &compiler_temp, desc->targetpc, TRUE); // <subtract cycles>
1288      generate_update_cycles(block, &compiler_temp, desc->targetpc, TRUE); // <subtract cycles>
17011289      if (desc->flags & OPFLAG_INTRABLOCK_BRANCH)
17021290         UML_JMP(block, desc->targetpc | 0x80000000);                            // jmp     desc->targetpc | 0x80000000
17031291      else
1704         UML_HASHJMP(block, mips3->impstate->mode, desc->targetpc, *mips3->impstate->nocode);
1292         UML_HASHJMP(block, m_core->mode, desc->targetpc, *m_nocode);
17051293                                                               // hashjmp <mode>,desc->targetpc,nocode
17061294   }
17071295   else
17081296   {
1709      generate_update_cycles(mips3, block, &compiler_temp, mem(&mips3->impstate->jmpdest), TRUE);
1297      generate_update_cycles(block, &compiler_temp, mem(&m_core->jmpdest), TRUE);
17101298                                                               // <subtract cycles>
1711      UML_HASHJMP(block, mips3->impstate->mode, mem(&mips3->impstate->jmpdest), *mips3->impstate->nocode);
1299      UML_HASHJMP(block, m_core->mode, mem(&m_core->jmpdest), *m_nocode);
17121300                                                               // hashjmp <mode>,<rsreg>,nocode
17131301   }
17141302
r30757r30758
17261314    opcode
17271315-------------------------------------------------*/
17281316
1729static int generate_opcode(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
1317int mips3_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
17301318{
17311319   int in_delay_slot = ((desc->flags & OPFLAG_IN_DELAY_SLOT) != 0);
17321320   UINT32 op = desc->opptr.l[0];
r30757r30758
17381326      /* ----- sub-groups ----- */
17391327
17401328      case 0x00:  /* SPECIAL - MIPS I */
1741         return generate_special(mips3, block, compiler, desc);
1329         return generate_special(block, compiler, desc);
17421330
17431331      case 0x01:  /* REGIMM - MIPS I */
1744         return generate_regimm(mips3, block, compiler, desc);
1332         return generate_regimm(block, compiler, desc);
17451333
17461334      case 0x1c:  /* IDT-specific */
1747         return generate_idt(mips3, block, compiler, desc);
1335         return generate_idt(block, compiler, desc);
17481336
17491337
17501338      /* ----- jumps and branches ----- */
17511339
17521340      case 0x02:  /* J - MIPS I */
1753         generate_delay_slot_and_branch(mips3, block, compiler, desc, 0);        // <next instruction + hashjmp>
1341         generate_delay_slot_and_branch(block, compiler, desc, 0);        // <next instruction + hashjmp>
17541342         return TRUE;
17551343
17561344      case 0x03:  /* JAL - MIPS I */
1757         generate_delay_slot_and_branch(mips3, block, compiler, desc, 31);       // <next instruction + hashjmp>
1345         generate_delay_slot_and_branch(block, compiler, desc, 31);       // <next instruction + hashjmp>
17581346         return TRUE;
17591347
17601348      case 0x04:  /* BEQ - MIPS I */
17611349      case 0x14:  /* BEQL - MIPS II */
17621350         UML_DCMP(block, R64(RSREG), R64(RTREG));                                // dcmp    <rsreg>,<rtreg>
17631351         UML_JMPc(block, COND_NE, skip = compiler->labelnum++);                  // jmp     skip,NE
1764         generate_delay_slot_and_branch(mips3, block, compiler, desc, 0);        // <next instruction + hashjmp>
1352         generate_delay_slot_and_branch(block, compiler, desc, 0);        // <next instruction + hashjmp>
17651353         UML_LABEL(block, skip);                                             // skip:
17661354         return TRUE;
17671355
r30757r30758
17691357      case 0x15:  /* BNEL - MIPS II */
17701358         UML_DCMP(block, R64(RSREG), R64(RTREG));                                // dcmp    <rsreg>,<rtreg>
17711359         UML_JMPc(block, COND_E, skip = compiler->labelnum++);                       // jmp     skip,E
1772         generate_delay_slot_and_branch(mips3, block, compiler, desc, 0);        // <next instruction + hashjmp>
1360         generate_delay_slot_and_branch(block, compiler, desc, 0);        // <next instruction + hashjmp>
17731361         UML_LABEL(block, skip);                                             // skip:
17741362         return TRUE;
17751363
r30757r30758
17791367         {
17801368            UML_DCMP(block, R64(RSREG), 0);                             // dcmp    <rsreg>,0
17811369            UML_JMPc(block, COND_G, skip = compiler->labelnum++);                   // jmp     skip,G
1782            generate_delay_slot_and_branch(mips3, block, compiler, desc, 0);    // <next instruction + hashjmp>
1370            generate_delay_slot_and_branch(block, compiler, desc, 0);    // <next instruction + hashjmp>
17831371            UML_LABEL(block, skip);                                         // skip:
17841372         }
17851373         else
1786            generate_delay_slot_and_branch(mips3, block, compiler, desc, 0);    // <next instruction + hashjmp>
1374            generate_delay_slot_and_branch(block, compiler, desc, 0);    // <next instruction + hashjmp>
17871375         return TRUE;
17881376
17891377      case 0x07:  /* BGTZ - MIPS I */
17901378      case 0x17:  /* BGTZL - MIPS II */
17911379         UML_DCMP(block, R64(RSREG), 0);                                 // dcmp    <rsreg>,0
17921380         UML_JMPc(block, COND_LE, skip = compiler->labelnum++);                  // jmp     skip,LE
1793         generate_delay_slot_and_branch(mips3, block, compiler, desc, 0);        // <next instruction + hashjmp>
1381         generate_delay_slot_and_branch(block, compiler, desc, 0);        // <next instruction + hashjmp>
17941382         UML_LABEL(block, skip);                                             // skip:
17951383         return TRUE;
17961384
r30757r30758
18041392
18051393      case 0x08:  /* ADDI - MIPS I */
18061394         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
1807         if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS)
1808            UML_EXHc(block, COND_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], 0);
1395         if (m_drcoptions & MIPS3DRC_CHECK_OVERFLOWS)
1396            UML_EXHc(block, COND_V, *m_exception[EXCEPTION_OVERFLOW], 0);
18091397                                                               // exh    overflow,0
18101398         if (RTREG != 0)
18111399            UML_DSEXT(block, R64(RTREG), I0, SIZE_DWORD);                       // dsext   <rtreg>,i0,dword
r30757r30758
18211409
18221410      case 0x18:  /* DADDI - MIPS III */
18231411         UML_DADD(block, I0, R64(RSREG), SIMMVAL);                       // dadd    i0,<rsreg>,SIMMVAL
1824         if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS)
1825            UML_EXHc(block, COND_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], 0);
1412         if (m_drcoptions & MIPS3DRC_CHECK_OVERFLOWS)
1413            UML_EXHc(block, COND_V, *m_exception[EXCEPTION_OVERFLOW], 0);
18261414                                                               // exh    overflow,0
18271415         if (RTREG != 0)
18281416            UML_DMOV(block, R64(RTREG), I0);                                // dmov    <rtreg>,i0
r30757r30758
18691457
18701458      case 0x20:  /* LB - MIPS I */
18711459         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
1872         UML_CALLH(block, *mips3->impstate->read8[mips3->impstate->mode >> 1]);  // callh   read8
1460         UML_CALLH(block, *m_read8[m_core->mode >> 1]);  // callh   read8
18731461         if (RTREG != 0)
18741462            UML_DSEXT(block, R64(RTREG), I0, SIZE_BYTE);                        // dsext   <rtreg>,i0,byte
18751463         if (!in_delay_slot)
1876            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1464            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
18771465         return TRUE;
18781466
18791467      case 0x21:  /* LH - MIPS I */
18801468         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
1881         UML_CALLH(block, *mips3->impstate->read16[mips3->impstate->mode >> 1]); // callh   read16
1469         UML_CALLH(block, *m_read16[m_core->mode >> 1]); // callh   read16
18821470         if (RTREG != 0)
18831471            UML_DSEXT(block, R64(RTREG), I0, SIZE_WORD);                        // dsext   <rtreg>,i0,word
18841472         if (!in_delay_slot)
1885            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1473            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
18861474         return TRUE;
18871475
18881476      case 0x23:  /* LW - MIPS I */
18891477         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
1890         UML_CALLH(block, *mips3->impstate->read32[mips3->impstate->mode >> 1]); // callh   read32
1478         UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh   read32
18911479         if (RTREG != 0)
18921480            UML_DSEXT(block, R64(RTREG), I0, SIZE_DWORD);                       // dsext   <rtreg>,i0
18931481         if (!in_delay_slot)
1894            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1482            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
18951483         return TRUE;
18961484
18971485      case 0x30:  /* LL - MIPS II */
18981486         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
1899         UML_CALLH(block, *mips3->impstate->read32[mips3->impstate->mode >> 1]); // callh   read32
1487         UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh   read32
19001488         if (RTREG != 0)
19011489            UML_DSEXT(block, R64(RTREG), I0, SIZE_DWORD);                       // dsext   <rtreg>,i0
1902         UML_MOV(block, mem(&mips3->llbit), 1);                              // mov     [llbit],1
1490         UML_MOV(block, mem(&m_core->llbit), 1);                              // mov     [llbit],1
19031491         if (!in_delay_slot)
1904            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1492            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
19051493         return TRUE;
19061494
19071495      case 0x24:  /* LBU - MIPS I */
19081496         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
1909         UML_CALLH(block, *mips3->impstate->read8[mips3->impstate->mode >> 1]);  // callh   read8
1497         UML_CALLH(block, *m_read8[m_core->mode >> 1]);  // callh   read8
19101498         if (RTREG != 0)
19111499            UML_DAND(block, R64(RTREG), I0, 0xff);                  // dand    <rtreg>,i0,0xff
19121500         if (!in_delay_slot)
1913            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1501            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
19141502         return TRUE;
19151503
19161504      case 0x25:  /* LHU - MIPS I */
19171505         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
1918         UML_CALLH(block, *mips3->impstate->read16[mips3->impstate->mode >> 1]); // callh   read16
1506         UML_CALLH(block, *m_read16[m_core->mode >> 1]); // callh   read16
19191507         if (RTREG != 0)
19201508            UML_DAND(block, R64(RTREG), I0, 0xffff);                    // dand    <rtreg>,i0,0xffff
19211509         if (!in_delay_slot)
1922            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1510            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
19231511         return TRUE;
19241512
19251513      case 0x27:  /* LWU - MIPS III */
19261514         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
1927         UML_CALLH(block, *mips3->impstate->read32[mips3->impstate->mode >> 1]); // callh   read32
1515         UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh   read32
19281516         if (RTREG != 0)
19291517            UML_DAND(block, R64(RTREG), I0, 0xffffffff);                // dand    <rtreg>,i0,0xffffffff
19301518         if (!in_delay_slot)
1931            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1519            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
19321520         return TRUE;
19331521
19341522      case 0x37:  /* LD - MIPS III */
19351523         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
1936         UML_CALLH(block, *mips3->impstate->read64[mips3->impstate->mode >> 1]); // callh   read64
1524         UML_CALLH(block, *m_read64[m_core->mode >> 1]); // callh   read64
19371525         if (RTREG != 0)
19381526            UML_DMOV(block, R64(RTREG), I0);                                // dmov    <rtreg>,i0
19391527         if (!in_delay_slot)
1940            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1528            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
19411529         return TRUE;
19421530
19431531      case 0x34:  /* LLD - MIPS III */
19441532         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
1945         UML_CALLH(block, *mips3->impstate->read64[mips3->impstate->mode >> 1]); // callh   read64
1533         UML_CALLH(block, *m_read64[m_core->mode >> 1]); // callh   read64
19461534         if (RTREG != 0)
19471535            UML_DMOV(block, R64(RTREG), I0);                                // dmov    <rtreg>,i0
1948         UML_MOV(block, mem(&mips3->llbit), 1);                              // mov     [llbit],1
1536         UML_MOV(block, mem(&m_core->llbit), 1);                              // mov     [llbit],1
19491537         if (!in_delay_slot)
1950            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1538            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
19511539         return TRUE;
19521540
19531541      case 0x22:  /* LWL - MIPS I */
19541542         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
19551543         UML_SHL(block, I1, I0, 3);                              // shl     i1,i0,3
19561544         UML_AND(block, I0, I0, ~3);                             // and     i0,i0,~3
1957         if (!mips3->bigendian)
1545         if (!m_bigendian)
19581546            UML_XOR(block, I1, I1, 0x18);                       // xor     i1,i1,0x18
19591547         UML_SHR(block, I2, ~0, I1);                             // shr     i2,~0,i1
1960         UML_CALLH(block, *mips3->impstate->read32mask[mips3->impstate->mode >> 1]);
1548         UML_CALLH(block, *m_read32mask[m_core->mode >> 1]);
19611549                                                               // callh   read32mask
19621550         if (RTREG != 0)
19631551         {
r30757r30758
19671555            UML_DSEXT(block, R64(RTREG), I3, SIZE_DWORD);                       // dsext   <rtreg>,i3,dword
19681556         }
19691557         if (!in_delay_slot)
1970            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1558            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
19711559         return TRUE;
19721560
19731561      case 0x26:  /* LWR - MIPS I */
19741562         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
19751563         UML_SHL(block, I1, I0, 3);                              // shl     i1,i0,3
19761564         UML_AND(block, I0, I0, ~3);                             // and     i0,i0,~3
1977         if (mips3->bigendian)
1565         if (m_bigendian)
19781566            UML_XOR(block, I1, I1, 0x18);                       // xor     i1,i1,0x18
19791567         UML_SHL(block, I2, ~0, I1);                             // shl     i2,~0,i1
1980         UML_CALLH(block, *mips3->impstate->read32mask[mips3->impstate->mode >> 1]);
1568         UML_CALLH(block, *m_read32mask[m_core->mode >> 1]);
19811569                                                               // callh   read32mask
19821570         if (RTREG != 0)
19831571         {
r30757r30758
19881576            UML_DSEXT(block, R64(RTREG), I3, SIZE_DWORD);                       // dsext   <rtreg>,i3,dword
19891577         }
19901578         if (!in_delay_slot)
1991            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1579            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
19921580         return TRUE;
19931581
19941582      case 0x1a:  /* LDL - MIPS III */
19951583         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
19961584         UML_SHL(block, I1, I0, 3);                              // shl     i1,i0,3
19971585         UML_AND(block, I0, I0, ~7);                             // and     i0,i0,~7
1998         if (!mips3->bigendian)
1586         if (!m_bigendian)
19991587            UML_XOR(block, I1, I1, 0x38);                       // xor     i1,i1,0x38
20001588         UML_DSHR(block, I2, (UINT64)~0, I1);                        // dshr    i2,~0,i1
2001         UML_CALLH(block, *mips3->impstate->read64mask[mips3->impstate->mode >> 1]);
1589         UML_CALLH(block, *m_read64mask[m_core->mode >> 1]);
20021590                                                               // callh   read64mask
20031591         if (RTREG != 0)
20041592         {
r30757r30758
20061594            UML_DROLINS(block, R64(RTREG), I0, I1, I2);         // drolins <rtreg>,i0,i1,i2
20071595         }
20081596         if (!in_delay_slot)
2009            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1597            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
20101598         return TRUE;
20111599
20121600      case 0x1b:  /* LDR - MIPS III */
20131601         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
20141602         UML_SHL(block, I1, I0, 3);                              // shl     i1,i0,3
20151603         UML_AND(block, I0, I0, ~7);                             // and     i0,i0,~7
2016         if (mips3->bigendian)
1604         if (m_bigendian)
20171605            UML_XOR(block, I1, I1, 0x38);                       // xor     i1,i1,0x38
20181606         UML_DSHL(block, I2, (UINT64)~0, I1);                        // dshl    i2,~0,i1
2019         UML_CALLH(block, *mips3->impstate->read64mask[mips3->impstate->mode >> 1]);
1607         UML_CALLH(block, *m_read64mask[m_core->mode >> 1]);
20201608                                                               // callh   read64mask
20211609         if (RTREG != 0)
20221610         {
r30757r30758
20251613            UML_DROLINS(block, R64(RTREG), I0, I1, I2);         // drolins <rtreg>,i0,i1,i2
20261614         }
20271615         if (!in_delay_slot)
2028            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1616            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
20291617         return TRUE;
20301618
20311619      case 0x31:  /* LWC1 - MIPS I */
20321620         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
2033         UML_CALLH(block, *mips3->impstate->read32[mips3->impstate->mode >> 1]); // callh   read32
1621         UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh   read32
20341622         UML_MOV(block, FPR32(RTREG), I0);                                   // mov     <cpr1_rt>,i0
20351623         if (!in_delay_slot)
2036            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1624            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
20371625         return TRUE;
20381626
20391627      case 0x35:  /* LDC1 - MIPS III */
20401628         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
2041         UML_CALLH(block, *mips3->impstate->read64[mips3->impstate->mode >> 1]); // callh   read64
1629         UML_CALLH(block, *m_read64[m_core->mode >> 1]); // callh   read64
20421630         UML_DMOV(block, FPR64(RTREG), I0);                                  // dmov    <cpr1_rt>,i0
20431631         if (!in_delay_slot)
2044            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1632            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
20451633         return TRUE;
20461634
20471635      case 0x32:  /* LWC2 - MIPS I */
20481636         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
2049         UML_CALLH(block, *mips3->impstate->read32[mips3->impstate->mode >> 1]); // callh   read32
1637         UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh   read32
20501638         UML_DAND(block, CPR264(RTREG), I0, 0xffffffff);             // dand    <cpr2_rt>,i0,0xffffffff
20511639         if (!in_delay_slot)
2052            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1640            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
20531641         return TRUE;
20541642
20551643      case 0x36:  /* LDC2 - MIPS II */
20561644         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
2057         UML_CALLH(block, *mips3->impstate->read64[mips3->impstate->mode >> 1]); // callh   read64
1645         UML_CALLH(block, *m_read64[m_core->mode >> 1]); // callh   read64
20581646         UML_DMOV(block, CPR264(RTREG), I0);                             // dmov    <cpr2_rt>,i0
20591647         if (!in_delay_slot)
2060            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1648            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
20611649         return TRUE;
20621650
20631651
r30757r30758
20661654      case 0x28:  /* SB - MIPS I */
20671655         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
20681656         UML_MOV(block, I1, R32(RTREG));                                 // mov     i1,<rtreg>
2069         UML_CALLH(block, *mips3->impstate->write8[mips3->impstate->mode >> 1]); // callh   write8
1657         UML_CALLH(block, *m_write8[m_core->mode >> 1]); // callh   write8
20701658         if (!in_delay_slot)
2071            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1659            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
20721660         return TRUE;
20731661
20741662      case 0x29:  /* SH - MIPS I */
20751663         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
20761664         UML_MOV(block, I1, R32(RTREG));                                 // mov     i1,<rtreg>
2077         UML_CALLH(block, *mips3->impstate->write16[mips3->impstate->mode >> 1]);    // callh   write16
1665         UML_CALLH(block, *m_write16[m_core->mode >> 1]);    // callh   write16
20781666         if (!in_delay_slot)
2079            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1667            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
20801668         return TRUE;
20811669
20821670      case 0x2b:  /* SW - MIPS I */
20831671         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
20841672         UML_MOV(block, I1, R32(RTREG));                                 // mov     i1,<rtreg>
2085         UML_CALLH(block, *mips3->impstate->write32[mips3->impstate->mode >> 1]);    // callh   write32
1673         UML_CALLH(block, *m_write32[m_core->mode >> 1]);    // callh   write32
20861674         if (!in_delay_slot)
2087            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1675            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
20881676         return TRUE;
20891677
20901678      case 0x38:  /* SC - MIPS II */
2091         UML_CMP(block, mem(&mips3->llbit), 0);                              // cmp     [llbit],0
1679         UML_CMP(block, mem(&m_core->llbit), 0);                              // cmp     [llbit],0
20921680         UML_JMPc(block, COND_E, skip = compiler->labelnum++);                       // je      skip
20931681         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
20941682         UML_MOV(block, I1, R32(RTREG));                                 // mov     i1,<rtreg>
2095         UML_CALLH(block, *mips3->impstate->write32[mips3->impstate->mode >> 1]);    // callh   write32
1683         UML_CALLH(block, *m_write32[m_core->mode >> 1]);    // callh   write32
20961684         UML_LABEL(block, skip);                                             // skip:
2097         UML_DSEXT(block, R64(RTREG), mem(&mips3->llbit), SIZE_DWORD);               // dsext   <rtreg>,[llbit],dword
1685         UML_DSEXT(block, R64(RTREG), mem(&m_core->llbit), SIZE_DWORD);               // dsext   <rtreg>,[llbit],dword
20981686         if (!in_delay_slot)
2099            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1687            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
21001688         return TRUE;
21011689
21021690      case 0x3f:  /* SD - MIPS III */
21031691         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
21041692         UML_DMOV(block, I1, R64(RTREG));                                    // dmov    i1,<rtreg>
2105         UML_CALLH(block, *mips3->impstate->write64[mips3->impstate->mode >> 1]);    // callh   write64
1693         UML_CALLH(block, *m_write64[m_core->mode >> 1]);    // callh   write64
21061694         if (!in_delay_slot)
2107            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1695            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
21081696         return TRUE;
21091697
21101698      case 0x3c:  /* SCD - MIPS III */
2111         UML_CMP(block, mem(&mips3->llbit), 0);                              // cmp     [llbit],0
1699         UML_CMP(block, mem(&m_core->llbit), 0);                              // cmp     [llbit],0
21121700         UML_JMPc(block, COND_E, skip = compiler->labelnum++);                       // je      skip
21131701         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
21141702         UML_DMOV(block, I1, R64(RTREG));                                    // dmov    i1,<rtreg>
2115         UML_CALLH(block, *mips3->impstate->write64[mips3->impstate->mode >> 1]);    // callh   write64
1703         UML_CALLH(block, *m_write64[m_core->mode >> 1]);    // callh   write64
21161704         UML_LABEL(block, skip);                                             // skip:
2117         UML_DSEXT(block, R64(RTREG), mem(&mips3->llbit), SIZE_DWORD);               // dsext   <rtreg>,[llbit],dword
1705         UML_DSEXT(block, R64(RTREG), mem(&m_core->llbit), SIZE_DWORD);               // dsext   <rtreg>,[llbit],dword
21181706         if (!in_delay_slot)
2119            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1707            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
21201708         return TRUE;
21211709
21221710      case 0x2a:  /* SWL - MIPS I */
r30757r30758
21241712         UML_SHL(block, I3, I0, 3);                              // shl     i3,i0,3
21251713         UML_AND(block, I0, I0, ~3);                             // and     i0,i0,~3
21261714         UML_MOV(block, I1, R32(RTREG));                                 // mov     i1,<rtreg>
2127         if (!mips3->bigendian)
1715         if (!m_bigendian)
21281716            UML_XOR(block, I3, I3, 0x18);                       // xor     i3,i3,0x18
21291717         UML_SHR(block, I2, ~0, I3);                             // shr     i2,~0,i3
21301718         UML_SHR(block, I1, I1, I3);                             // shr     i1,i1,i3
2131         UML_CALLH(block, *mips3->impstate->write32mask[mips3->impstate->mode >> 1]);
1719         UML_CALLH(block, *m_write32mask[m_core->mode >> 1]);
21321720                                                               // callh   write32mask
21331721         if (!in_delay_slot)
2134            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1722            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
21351723         return TRUE;
21361724
21371725      case 0x2e:  /* SWR - MIPS I */
r30757r30758
21391727         UML_SHL(block, I3, I0, 3);                              // shl     i3,i0,3
21401728         UML_AND(block, I0, I0, ~3);                             // and     i0,i0,~3
21411729         UML_MOV(block, I1, R32(RTREG));                                 // mov     i1,<rtreg>
2142         if (mips3->bigendian)
1730         if (m_bigendian)
21431731            UML_XOR(block, I3, I3, 0x18);                       // xor     i3,i3,0x18
21441732         UML_SHL(block, I2, ~0, I3);                             // shl     i2,~0,i3
21451733         UML_SHL(block, I1, I1, I3);                             // shl     i1,i1,i3
2146         UML_CALLH(block, *mips3->impstate->write32mask[mips3->impstate->mode >> 1]);
1734         UML_CALLH(block, *m_write32mask[m_core->mode >> 1]);
21471735                                                               // callh   write32mask
21481736         if (!in_delay_slot)
2149            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1737            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
21501738         return TRUE;
21511739
21521740      case 0x2c:  /* SDL - MIPS III */
r30757r30758
21541742         UML_SHL(block, I3, I0, 3);                              // shl     i3,i0,3
21551743         UML_AND(block, I0, I0, ~7);                             // and     i0,i0,~7
21561744         UML_DMOV(block, I1, R64(RTREG));                                    // dmov    i1,<rtreg>
2157         if (!mips3->bigendian)
1745         if (!m_bigendian)
21581746            UML_XOR(block, I3, I3, 0x38);                       // xor     i3,i3,0x38
21591747         UML_DSHR(block, I2, (UINT64)~0, I3);                        // dshr    i2,~0,i3
21601748         UML_DSHR(block, I1, I1, I3);                                // dshr    i1,i1,i3
2161         UML_CALLH(block, *mips3->impstate->write64mask[mips3->impstate->mode >> 1]);
1749         UML_CALLH(block, *m_write64mask[m_core->mode >> 1]);
21621750                                                               // callh   write64mask
21631751         if (!in_delay_slot)
2164            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1752            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
21651753         return TRUE;
21661754
21671755      case 0x2d:  /* SDR - MIPS III */
r30757r30758
21691757         UML_SHL(block, I3, I0, 3);                              // shl     i3,i0,3
21701758         UML_AND(block, I0, I0, ~7);                             // and     i0,i0,~7
21711759         UML_DMOV(block, I1, R64(RTREG));                                    // dmov    i1,<rtreg>
2172         if (mips3->bigendian)
1760         if (m_bigendian)
21731761            UML_XOR(block, I3, I3, 0x38);                       // xor     i3,i3,0x38
21741762         UML_DSHL(block, I2, (UINT64)~0, I3);                        // dshl    i2,~0,i3
21751763         UML_DSHL(block, I1, I1, I3);                                // dshl    i1,i1,i3
2176         UML_CALLH(block, *mips3->impstate->write64mask[mips3->impstate->mode >> 1]);
1764         UML_CALLH(block, *m_write64mask[m_core->mode >> 1]);
21771765                                                               // callh   write64mask
21781766         if (!in_delay_slot)
2179            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1767            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
21801768         return TRUE;
21811769
21821770      case 0x39:  /* SWC1 - MIPS I */
21831771         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
21841772         UML_MOV(block, I1, FPR32(RTREG));                                   // mov     i1,<cpr1_rt>
2185         UML_CALLH(block, *mips3->impstate->write32[mips3->impstate->mode >> 1]);    // callh   write32
1773         UML_CALLH(block, *m_write32[m_core->mode >> 1]);    // callh   write32
21861774         if (!in_delay_slot)
2187            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1775            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
21881776         return TRUE;
21891777
21901778      case 0x3d:  /* SDC1 - MIPS III */
21911779         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
21921780         UML_DMOV(block, I1, FPR64(RTREG));                                  // dmov    i1,<cpr1_rt>
2193         UML_CALLH(block, *mips3->impstate->write64[mips3->impstate->mode >> 1]);    // callh   write64
1781         UML_CALLH(block, *m_write64[m_core->mode >> 1]);    // callh   write64
21941782         if (!in_delay_slot)
2195            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1783            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
21961784         return TRUE;
21971785
21981786      case 0x3a:  /* SWC2 - MIPS I */
21991787         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
22001788         UML_MOV(block, I1, CPR232(RTREG));                                  // mov     i1,<cpr2_rt>
2201         UML_CALLH(block, *mips3->impstate->write32[mips3->impstate->mode >> 1]);    // callh   write32
1789         UML_CALLH(block, *m_write32[m_core->mode >> 1]);    // callh   write32
22021790         if (!in_delay_slot)
2203            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1791            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
22041792         return TRUE;
22051793
22061794      case 0x3e:  /* SDC2 - MIPS II */
22071795         UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
22081796         UML_DMOV(block, I1, CPR264(RTREG));                             // dmov    i1,<cpr2_rt>
2209         UML_CALLH(block, *mips3->impstate->write64[mips3->impstate->mode >> 1]);    // callh   write64
1797         UML_CALLH(block, *m_write64[m_core->mode >> 1]);    // callh   write64
22101798         if (!in_delay_slot)
2211            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
1799            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
22121800         return TRUE;
22131801
22141802
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22221810      /* ----- coprocessor instructions ----- */
22231811
22241812      case 0x10:  /* COP0 - MIPS I */
2225         return generate_cop0(mips3, block, compiler, desc);
1813         return generate_cop0(block, compiler, desc);
22261814
22271815      case 0x11:  /* COP1 - MIPS I */
2228         return generate_cop1(mips3, block, compiler, desc);
1816         return generate_cop1(block, compiler, desc);
22291817
22301818      case 0x13:  /* COP1X - MIPS IV */
2231         return generate_cop1x(mips3, block, compiler, desc);
1819         return generate_cop1x(block, compiler, desc);
22321820
22331821      case 0x12:  /* COP2 - MIPS I */
2234         UML_EXH(block, *mips3->impstate->exception[EXCEPTION_INVALIDOP], 0);// exh     invalidop,0
1822         UML_EXH(block, *m_exception[EXCEPTION_INVALIDOP], 0);// exh     invalidop,0
22351823         return TRUE;
22361824
22371825
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22491837    'SPECIAL' group
22501838-------------------------------------------------*/
22511839
2252static int generate_special(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
1840int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
22531841{
22541842   UINT32 op = desc->opptr.l[0];
22551843   UINT8 opswitch = op & 63;
r30757r30758
23551943      /* ----- basic arithmetic ----- */
23561944
23571945      case 0x20:  /* ADD - MIPS I */
2358         if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS)
1946         if (m_drcoptions & MIPS3DRC_CHECK_OVERFLOWS)
23591947         {
23601948            UML_ADD(block, I0, R32(RSREG), R32(RTREG));                 // add     i0,<rsreg>,<rtreg>
2361            UML_EXHc(block, COND_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], 0);
1949            UML_EXHc(block, COND_V, *m_exception[EXCEPTION_OVERFLOW], 0);
23621950                                                               // exh     overflow,0,V
23631951            if (RDREG != 0)
23641952               UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD);                   // dsext   <rdreg>,i0,dword
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23791967         return TRUE;
23801968
23811969      case 0x2c:  /* DADD - MIPS III */
2382         if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS)
1970         if (m_drcoptions & MIPS3DRC_CHECK_OVERFLOWS)
23831971         {
23841972            UML_DADD(block, I0, R64(RSREG), R64(RTREG));                    // dadd    i0,<rsreg>,<rtreg>
2385            UML_EXHc(block, COND_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], 0);
1973            UML_EXHc(block, COND_V, *m_exception[EXCEPTION_OVERFLOW], 0);
23861974                                                               // exh     overflow,0,V
23871975            if (RDREG != 0)
23881976               UML_DMOV(block, R64(RDREG), I0);                            // dmov    <rdreg>,i0
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23971985         return TRUE;
23981986
23991987      case 0x22:  /* SUB - MIPS I */
2400         if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS)
1988         if (m_drcoptions & MIPS3DRC_CHECK_OVERFLOWS)
24011989         {
24021990            UML_SUB(block, I0, R32(RSREG), R32(RTREG));                 // sub     i0,<rsreg>,<rtreg>
2403            UML_EXHc(block, COND_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], 0);
1991            UML_EXHc(block, COND_V, *m_exception[EXCEPTION_OVERFLOW], 0);
24041992                                                               // exh     overflow,0,V
24051993            if (RDREG != 0)
24061994               UML_DSEXT(block, R64(RDREG), I0, SIZE_DWORD);                   // dsext   <rdreg>,i0,dword
r30757r30758
24212009         return TRUE;
24222010
24232011      case 0x2e:  /* DSUB - MIPS III */
2424         if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS)
2012         if (m_drcoptions & MIPS3DRC_CHECK_OVERFLOWS)
24252013         {
24262014            UML_DSUB(block, I0, R64(RSREG), R64(RTREG));                    // dsub    i0,<rsreg>,<rtreg>
2427            UML_EXHc(block, COND_V, *mips3->impstate->exception[EXCEPTION_OVERFLOW], 0);
2015            UML_EXHc(block, COND_V, *m_exception[EXCEPTION_OVERFLOW], 0);
24282016                                                               // exh     overflow,0,V
24292017            if (RDREG != 0)
24302018               UML_DMOV(block, R64(RDREG), I0);                            // dmov    <rdreg>,i0
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25282116
25292117      case 0x30:  /* TGE - MIPS II */
25302118         UML_DCMP(block, R64(RSREG), R64(RTREG));                                // dcmp    <rsreg>,<rtreg>
2531         UML_EXHc(block, COND_GE, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh     trap,0,GE
2119         UML_EXHc(block, COND_GE, *m_exception[EXCEPTION_TRAP], 0);// exh     trap,0,GE
25322120         return TRUE;
25332121
25342122      case 0x31:  /* TGEU - MIPS II */
25352123         UML_DCMP(block, R64(RSREG), R64(RTREG));                                // dcmp    <rsreg>,<rtreg>
2536         UML_EXHc(block, COND_AE, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh     trap,0,AE
2124         UML_EXHc(block, COND_AE, *m_exception[EXCEPTION_TRAP], 0);// exh     trap,0,AE
25372125         return TRUE;
25382126
25392127      case 0x32:  /* TLT - MIPS II */
25402128         UML_DCMP(block, R64(RSREG), R64(RTREG));                                // dcmp    <rsreg>,<rtreg>
2541         UML_EXHc(block, COND_L, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh     trap,0,LT
2129         UML_EXHc(block, COND_L, *m_exception[EXCEPTION_TRAP], 0);// exh     trap,0,LT
25422130         return TRUE;
25432131
25442132      case 0x33:  /* TLTU - MIPS II */
25452133         UML_DCMP(block, R64(RSREG), R64(RTREG));                                // dcmp    <rsreg>,<rtreg>
2546         UML_EXHc(block, COND_B, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh     trap,0,B
2134         UML_EXHc(block, COND_B, *m_exception[EXCEPTION_TRAP], 0);// exh     trap,0,B
25472135         return TRUE;
25482136
25492137      case 0x34:  /* TEQ - MIPS II */
25502138         UML_DCMP(block, R64(RSREG), R64(RTREG));                                // dcmp    <rsreg>,<rtreg>
2551         UML_EXHc(block, COND_E, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh     trap,0,E
2139         UML_EXHc(block, COND_E, *m_exception[EXCEPTION_TRAP], 0);// exh     trap,0,E
25522140         return TRUE;
25532141
25542142      case 0x36:  /* TNE - MIPS II */
25552143         UML_DCMP(block, R64(RSREG), R64(RTREG));                                // dcmp    <rsreg>,<rtreg>
2556         UML_EXHc(block, COND_NE, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh     trap,0,NE
2144         UML_EXHc(block, COND_NE, *m_exception[EXCEPTION_TRAP], 0);// exh     trap,0,NE
25572145         return TRUE;
25582146
25592147
r30757r30758
25882176      /* ----- jumps and branches ----- */
25892177
25902178      case 0x08:  /* JR - MIPS I */
2591         generate_delay_slot_and_branch(mips3, block, compiler, desc, 0);        // <next instruction + hashjmp>
2179         generate_delay_slot_and_branch(block, compiler, desc, 0);        // <next instruction + hashjmp>
25922180         return TRUE;
25932181
25942182      case 0x09:  /* JALR - MIPS I */
2595         generate_delay_slot_and_branch(mips3, block, compiler, desc, RDREG);    // <next instruction + hashjmp>
2183         generate_delay_slot_and_branch(block, compiler, desc, RDREG);    // <next instruction + hashjmp>
25962184         return TRUE;
25972185
25982186
25992187      /* ----- system calls ----- */
26002188
26012189      case 0x0c:  /* SYSCALL - MIPS I */
2602         UML_EXH(block, *mips3->impstate->exception[EXCEPTION_SYSCALL], 0);  // exh     syscall,0
2190         UML_EXH(block, *m_exception[EXCEPTION_SYSCALL], 0);  // exh     syscall,0
26032191         return TRUE;
26042192
26052193      case 0x0d:  /* BREAK - MIPS I */
2606         UML_EXH(block, *mips3->impstate->exception[EXCEPTION_BREAK], 0);    // exh     break,0
2194         UML_EXH(block, *m_exception[EXCEPTION_BREAK], 0);    // exh     break,0
26072195         return TRUE;
26082196
26092197
r30757r30758
26422230    'REGIMM' group
26432231-------------------------------------------------*/
26442232
2645static int generate_regimm(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
2233int mips3_device::generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
26462234{
26472235   UINT32 op = desc->opptr.l[0];
26482236   UINT8 opswitch = RTREG;
r30757r30758
26582246         {
26592247            UML_DCMP(block, R64(RSREG), 0);                             // dcmp    <rsreg>,0
26602248            UML_JMPc(block, COND_GE, skip = compiler->labelnum++);              // jmp     skip,GE
2661            generate_delay_slot_and_branch(mips3, block, compiler, desc, (opswitch & 0x10) ? 31 : 0);
2249            generate_delay_slot_and_branch(block, compiler, desc, (opswitch & 0x10) ? 31 : 0);
26622250                                                               // <next instruction + hashjmp>
26632251            UML_LABEL(block, skip);                                         // skip:
26642252         }
r30757r30758
26722260         {
26732261            UML_DCMP(block, R64(RSREG), 0);                             // dcmp    <rsreg>,0
26742262            UML_JMPc(block, COND_L, skip = compiler->labelnum++);                   // jmp     skip,L
2675            generate_delay_slot_and_branch(mips3, block, compiler, desc, (opswitch & 0x10) ? 31 : 0);
2263            generate_delay_slot_and_branch(block, compiler, desc, (opswitch & 0x10) ? 31 : 0);
26762264                                                               // <next instruction + hashjmp>
26772265            UML_LABEL(block, skip);                                         // skip:
26782266         }
26792267         else
2680            generate_delay_slot_and_branch(mips3, block, compiler, desc, (opswitch & 0x10) ? 31 : 0);
2268            generate_delay_slot_and_branch(block, compiler, desc, (opswitch & 0x10) ? 31 : 0);
26812269                                                               // <next instruction + hashjmp>
26822270         return TRUE;
26832271
26842272      case 0x08:  /* TGEI */
26852273         UML_DCMP(block, R64(RSREG), SIMMVAL);                               // dcmp    <rsreg>,SIMMVAL
2686         UML_EXHc(block, COND_GE, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh     trap,0,GE
2274         UML_EXHc(block, COND_GE, *m_exception[EXCEPTION_TRAP], 0);// exh     trap,0,GE
26872275         return TRUE;
26882276
26892277      case 0x09:  /* TGEIU */
26902278         UML_DCMP(block, R64(RSREG), SIMMVAL);                               // dcmp    <rsreg>,SIMMVAL
2691         UML_EXHc(block, COND_AE, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh     trap,0,AE
2279         UML_EXHc(block, COND_AE, *m_exception[EXCEPTION_TRAP], 0);// exh     trap,0,AE
26922280         return TRUE;
26932281
26942282      case 0x0a:  /* TLTI */
26952283         UML_DCMP(block, R64(RSREG), SIMMVAL);                               // dcmp    <rsreg>,SIMMVAL
2696         UML_EXHc(block, COND_L, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh     trap,0,L
2284         UML_EXHc(block, COND_L, *m_exception[EXCEPTION_TRAP], 0);// exh     trap,0,L
26972285         return TRUE;
26982286
26992287      case 0x0b:  /* TLTIU */
27002288         UML_DCMP(block, R64(RSREG), SIMMVAL);                               // dcmp    <rsreg>,SIMMVAL
2701         UML_EXHc(block, COND_B, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh     trap,0,B
2289         UML_EXHc(block, COND_B, *m_exception[EXCEPTION_TRAP], 0);// exh     trap,0,B
27022290         return TRUE;
27032291
27042292      case 0x0c:  /* TEQI */
27052293         UML_DCMP(block, R64(RSREG), SIMMVAL);                               // dcmp    <rsreg>,SIMMVAL
2706         UML_EXHc(block, COND_E, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh     trap,0,E
2294         UML_EXHc(block, COND_E, *m_exception[EXCEPTION_TRAP], 0);// exh     trap,0,E
27072295         return TRUE;
27082296
27092297      case 0x0e:  /* TNEI */
27102298         UML_DCMP(block, R64(RSREG), SIMMVAL);                               // dcmp    <rsreg>,SIMMVAL
2711         UML_EXHc(block, COND_NE, *mips3->impstate->exception[EXCEPTION_TRAP], 0);// exh     trap,0,NE
2299         UML_EXHc(block, COND_NE, *m_exception[EXCEPTION_TRAP], 0);// exh     trap,0,NE
27122300         return TRUE;
27132301   }
27142302   return FALSE;
r30757r30758
27202308    specific group
27212309-------------------------------------------------*/
27222310
2723static int generate_idt(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
2311int mips3_device::generate_idt(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
27242312{
27252313   UINT32 op = desc->opptr.l[0];
27262314   UINT8 opswitch = op & 0x1f;
27272315
27282316   /* only enabled on IDT processors */
2729   if (mips3->flavor != MIPS3_TYPE_R4650)
2317   if (m_flavor != MIPS3_TYPE_R4650)
27302318      return FALSE;
27312319
27322320   switch (opswitch)
r30757r30758
27702358    handle special COP0 registers
27712359-------------------------------------------------*/
27722360
2773static int generate_set_cop0_reg(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 reg)
2361int mips3_device::generate_set_cop0_reg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 reg)
27742362{
27752363   int in_delay_slot = ((desc->flags & OPFLAG_IN_DELAY_SLOT) != 0);
27762364   code_label link;
r30757r30758
27812369         UML_ROLINS(block, CPR032(COP0_Cause), I0, 0, ~0xfc00);  // rolins  [Cause],i0,0,~0xfc00
27822370         compiler->checksoftints = TRUE;
27832371         if (!in_delay_slot)
2784            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
2372            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
27852373         return TRUE;
27862374
27872375      case COP0_Status:
2788         generate_update_cycles(mips3, block, compiler, desc->pc, !in_delay_slot);   // <subtract cycles>
2376         generate_update_cycles(block, compiler, desc->pc, !in_delay_slot);   // <subtract cycles>
27892377         UML_MOV(block, I1, CPR032(COP0_Status));                            // mov     i1,[Status]
27902378         UML_MOV(block, CPR032(COP0_Status), I0);                            // mov     [Status],i0
2791         generate_update_mode(mips3, block);                                     // <update mode>
2379         generate_update_mode(block);                                     // <update mode>
27922380         UML_XOR(block, I0, I0, I1);                             // xor     i0,i0,i1
27932381         UML_TEST(block, I0, 0x8000);                                    // test    i0,0x8000
2794         UML_CALLCc(block, COND_NZ, (c_function)mips3com_update_cycle_counting, mips3);      // callc   mips3com_update_cycle_counting,mips.core,NZ
2382         UML_CALLCc(block, COND_NZ, cfunc_mips3com_update_cycle_counting, this);      // callc   mips3com_update_cycle_counting,mips.core,NZ
27952383         compiler->checkints = TRUE;
27962384         if (!in_delay_slot)
2797            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
2385            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
27982386         return TRUE;
27992387
28002388      case COP0_Count:
2801         generate_update_cycles(mips3, block, compiler, desc->pc, !in_delay_slot);   // <subtract cycles>
2389         generate_update_cycles(block, compiler, desc->pc, !in_delay_slot);   // <subtract cycles>
28022390         UML_MOV(block, CPR032(COP0_Count), I0);                         // mov     [Count],i0
2803         UML_CALLC(block, cfunc_get_cycles, mips3);                              // callc   cfunc_get_cycles,mips3
2391         UML_CALLC(block, cfunc_get_cycles, this);                              // callc   cfunc_get_cycles,mips3
28042392         UML_DAND(block, I0, I0, 0xffffffff);                        // and     i0,i0,0xffffffff
28052393         UML_DADD(block, I0, I0, I0);                                // dadd    i0,i0,i0
2806         UML_DSUB(block, mem(&mips3->count_zero_time), mem(&mips3->impstate->numcycles), I0);
2807                                                               // dsub    [count_zero_time],[mips3->impstate->numcycles],i0
2808         UML_CALLC(block, (c_function)mips3com_update_cycle_counting, mips3);                // callc   mips3com_update_cycle_counting,mips.core
2394         UML_DSUB(block, mem(&m_core->count_zero_time), mem(&m_core->numcycles), I0);
2395                                                               // dsub    [count_zero_time],[m_numcycles],i0
2396         UML_CALLC(block, cfunc_mips3com_update_cycle_counting, this);                // callc   mips3com_update_cycle_counting,mips.core
28092397         return TRUE;
28102398
28112399      case COP0_Compare:
2812         UML_MOV(block, mem(&mips3->compare_armed), 1);                      // mov     [compare_armed],1
2813         generate_update_cycles(mips3, block, compiler, desc->pc, !in_delay_slot);   // <subtract cycles>
2400         UML_MOV(block, mem(&m_core->compare_armed), 1);                      // mov     [compare_armed],1
2401         generate_update_cycles(block, compiler, desc->pc, !in_delay_slot);   // <subtract cycles>
28142402         UML_MOV(block, CPR032(COP0_Compare), I0);                           // mov     [Compare],i0
28152403         UML_AND(block, CPR032(COP0_Cause), CPR032(COP0_Cause), ~0x8000);    // and     [Cause],[Cause],~0x8000
2816         UML_CALLC(block, (c_function)mips3com_update_cycle_counting, mips3);                // callc   mips3com_update_cycle_counting,mips.core
2404         UML_CALLC(block, cfunc_mips3com_update_cycle_counting, this);                // callc   mips3com_update_cycle_counting,mips.core
28172405         return TRUE;
28182406
28192407      case COP0_PRId:
r30757r30758
28282416         UML_MOV(block, CPR032(reg), I0);                                    // mov     cpr0[reg],i0
28292417         UML_TEST(block, I1, 0xff);                                  // test    i1,0xff
28302418         UML_JMPc(block, COND_Z, link = compiler->labelnum++);                       // jmp     link,z
2831         UML_CALLC(block, (c_function)mips3com_asid_changed, mips3);                         // callc   mips3com_asid_changed
2419         UML_CALLC(block, cfunc_mips3com_asid_changed, this);                         // callc   mips3com_asid_changed
28322420         UML_LABEL(block, link);                                             // link:
28332421         return TRUE;
28342422
r30757r30758
28442432    read special COP0 registers
28452433-------------------------------------------------*/
28462434
2847static int generate_get_cop0_reg(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 reg)
2435int mips3_device::generate_get_cop0_reg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 reg)
28482436{
28492437   code_label link1, link2;
28502438
28512439   switch (reg)
28522440   {
28532441      case COP0_Count:
2854         generate_update_cycles(mips3, block, compiler, desc->pc, FALSE);            // <subtract cycles>
2855         UML_CALLC(block, cfunc_get_cycles, mips3);                              // callc   cfunc_get_cycles,mips3
2856         UML_DSUB(block, I0, mem(&mips3->impstate->numcycles), mem(&mips3->count_zero_time));
2442         generate_update_cycles(block, compiler, desc->pc, FALSE);            // <subtract cycles>
2443         UML_CALLC(block, cfunc_get_cycles, this);                              // callc   cfunc_get_cycles,mips3
2444         UML_DSUB(block, I0, mem(&m_core->numcycles), mem(&m_core->count_zero_time));
28572445                                                               // dsub    i0,[numcycles],[count_zero_time]
28582446         UML_DSHR(block, I0, I0, 1);                             // dshr    i0,i0,1
28592447         UML_DSEXT(block, I0, I0, SIZE_DWORD);                               // dsext   i0,i0,dword
28602448         return TRUE;
28612449
28622450      case COP0_Random:
2863         generate_update_cycles(mips3, block, compiler, desc->pc, FALSE);            // <subtract cycles>
2864         UML_CALLC(block, cfunc_get_cycles, mips3);                              // callc   cfunc_get_cycles,mips3
2865         UML_DSUB(block, I0, mem(&mips3->impstate->numcycles), mem(&mips3->count_zero_time));
2451         generate_update_cycles(block, compiler, desc->pc, FALSE);            // <subtract cycles>
2452         UML_CALLC(block, cfunc_get_cycles, this);                              // callc   cfunc_get_cycles,mips3
2453         UML_DSUB(block, I0, mem(&m_core->numcycles), mem(&m_core->count_zero_time));
28662454                                                               // dsub    i0,[numcycles],[count_zero_time]
28672455         UML_AND(block, I1, CPR032(COP0_Wired), 0x3f);                   // and     i1,[Wired],0x3f
28682456         UML_SUB(block, I2, 48, I1);                             // sub     i2,48,i1
r30757r30758
28882476    generate_cop0 - compile COP0 opcodes
28892477-------------------------------------------------*/
28902478
2891static int generate_cop0(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
2479int mips3_device::generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
28922480{
28932481   UINT32 op = desc->opptr.l[0];
28942482   UINT8 opswitch = RSREG;
28952483   int skip;
28962484
28972485   /* generate an exception if COP0 is disabled unless we are in kernel mode */
2898   if ((mips3->impstate->mode >> 1) != MODE_KERNEL)
2486   if ((m_core->mode >> 1) != MODE_KERNEL)
28992487   {
29002488      UML_TEST(block, CPR032(COP0_Status), SR_COP0);                          // test    [Status],SR_COP0
2901      UML_EXHc(block, COND_Z, *mips3->impstate->exception[EXCEPTION_BADCOP], 0);// exh     cop,0,Z
2489      UML_EXHc(block, COND_Z, *m_exception[EXCEPTION_BADCOP], 0);// exh     cop,0,Z
29022490   }
29032491
29042492   switch (opswitch)
r30757r30758
29062494      case 0x00:  /* MFCz */
29072495         if (RTREG != 0)
29082496         {
2909            generate_get_cop0_reg(mips3, block, compiler, desc, RDREG);         // <get cop0 reg>
2497            generate_get_cop0_reg(block, compiler, desc, RDREG);         // <get cop0 reg>
29102498            UML_DSEXT(block, R64(RTREG), I0, SIZE_DWORD);                       // dsext   <rtreg>,i0,dword
29112499         }
29122500         return TRUE;
r30757r30758
29142502      case 0x01:  /* DMFCz */
29152503         if (RTREG != 0)
29162504         {
2917            generate_get_cop0_reg(mips3, block, compiler, desc, RDREG);         // <get cop0 reg>
2505            generate_get_cop0_reg(block, compiler, desc, RDREG);         // <get cop0 reg>
29182506            UML_DMOV(block, R64(RTREG), I0);                                // dmov    <rtreg>,i0
29192507         }
29202508         return TRUE;
r30757r30758
29262514
29272515      case 0x04:  /* MTCz */
29282516         UML_DSEXT(block, I0, R32(RTREG), SIZE_DWORD);                           // dsext   i0,<rtreg>,dword
2929         generate_set_cop0_reg(mips3, block, compiler, desc, RDREG);             // <set cop0 reg>
2517         generate_set_cop0_reg(block, compiler, desc, RDREG);             // <set cop0 reg>
29302518         return TRUE;
29312519
29322520      case 0x05:  /* DMTCz */
29332521         UML_DMOV(block, I0, R64(RTREG));                                    // dmov    i0,<rtreg>
2934         generate_set_cop0_reg(mips3, block, compiler, desc, RDREG);             // <set cop0 reg>
2522         generate_set_cop0_reg(block, compiler, desc, RDREG);             // <set cop0 reg>
29352523         return TRUE;
29362524
29372525      case 0x06:  /* CTCz */
r30757r30758
29572545         switch (op & 0x01ffffff)
29582546         {
29592547            case 0x01:  /* TLBR */
2960               UML_CALLC(block, (c_function)mips3com_tlbr, mips3);                         // callc   mips3com_tlbr,mips3
2548               UML_CALLC(block, cfunc_mips3com_tlbr, this);                         // callc   mips3com_tlbr,mips3
29612549               return TRUE;
29622550
29632551            case 0x02:  /* TLBWI */
2964               UML_CALLC(block, (c_function)mips3com_tlbwi, mips3);                        // callc   mips3com_tlbwi,mips3
2552               UML_CALLC(block, cfunc_mips3com_tlbwi, this);                        // callc   mips3com_tlbwi,mips3
29652553               return TRUE;
29662554
29672555            case 0x06:  /* TLBWR */
2968               UML_CALLC(block, (c_function)mips3com_tlbwr, mips3);                        // callc   mips3com_tlbwr,mips3
2556               UML_CALLC(block, cfunc_mips3com_tlbwr, this);                        // callc   mips3com_tlbwr,mips3
29692557               return TRUE;
29702558
29712559            case 0x08:  /* TLBP */
2972               UML_CALLC(block, (c_function)mips3com_tlbp, mips3);                         // callc   mips3com_tlbp,mips3
2560               UML_CALLC(block, cfunc_mips3com_tlbp, this);                         // callc   mips3com_tlbp,mips3
29732561               return TRUE;
29742562
29752563            case 0x18:  /* ERET */
2976               UML_MOV(block, mem(&mips3->llbit), 0);                      // mov     [llbit],0
2564               UML_MOV(block, mem(&m_core->llbit), 0);                      // mov     [llbit],0
29772565               UML_MOV(block, I0, CPR032(COP0_Status));                    // mov     i0,[Status]
29782566               UML_TEST(block, I0, SR_ERL);                            // test    i0,SR_ERL
29792567               UML_JMPc(block, COND_NZ, skip = compiler->labelnum++);          // jmp     skip,nz
29802568               UML_AND(block, I0, I0, ~SR_EXL);                    // and     i0,i0,~SR_EXL
29812569               UML_MOV(block, CPR032(COP0_Status), I0);                    // mov     [Status],i0
2982               generate_update_mode(mips3, block);
2570               generate_update_mode(block);
29832571               compiler->checkints = TRUE;
2984               generate_update_cycles(mips3, block, compiler, CPR032(COP0_EPC), TRUE);// <subtract cycles>
2985               UML_HASHJMP(block, mem(&mips3->impstate->mode), CPR032(COP0_EPC), *mips3->impstate->nocode);
2572               generate_update_cycles(block, compiler, CPR032(COP0_EPC), TRUE);// <subtract cycles>
2573               UML_HASHJMP(block, mem(&m_core->mode), CPR032(COP0_EPC), *m_nocode);
29862574                                                               // hashjmp <mode>,[EPC],nocode
29872575               UML_LABEL(block, skip);                                     // skip:
29882576               UML_AND(block, I0, I0, ~SR_ERL);                    // and     i0,i0,~SR_ERL
29892577               UML_MOV(block, CPR032(COP0_Status), I0);                    // mov     [Status],i0
2990               generate_update_mode(mips3, block);
2578               generate_update_mode(block);
29912579               compiler->checkints = TRUE;
2992               generate_update_cycles(mips3, block, compiler, CPR032(COP0_ErrorPC), TRUE);
2580               generate_update_cycles(block, compiler, CPR032(COP0_ErrorPC), TRUE);
29932581                                                               // <subtract cycles>
2994               UML_HASHJMP(block, mem(&mips3->impstate->mode), CPR032(COP0_ErrorPC), *mips3->impstate->nocode);
2582               UML_HASHJMP(block, mem(&m_core->mode), CPR032(COP0_ErrorPC), *m_nocode);
29952583                                                               // hashjmp <mode>,[EPC],nocode
29962584               return TRUE;
29972585
r30757r30758
30142602    generate_cop1 - compile COP1 opcodes
30152603-------------------------------------------------*/
30162604
3017static int generate_cop1(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
2605int mips3_device::generate_cop1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
30182606{
30192607   UINT32 op = desc->opptr.l[0];
30202608   code_label skip;
30212609   condition_t condition;
30222610
30232611   /* generate an exception if COP1 is disabled */
3024   if (mips3->impstate->drcoptions & MIPS3DRC_STRICT_COP1)
2612   if (m_drcoptions & MIPS3DRC_STRICT_COP1)
30252613   {
30262614      UML_TEST(block, CPR032(COP0_Status), SR_COP1);                          // test    [Status],SR_COP1
3027      UML_EXHc(block, COND_Z, *mips3->impstate->exception[EXCEPTION_BADCOP], 1);// exh     cop,1,Z
2615      UML_EXHc(block, COND_Z, *m_exception[EXCEPTION_BADCOP], 1);// exh     cop,1,Z
30282616   }
30292617
30302618   switch (RSREG)
r30757r30758
30622650            UML_TEST(block, I0, 3);                                 // test    i0,3
30632651            UML_JMPc(block, COND_Z, skip = compiler->labelnum++);                   // jmp     skip,Z
30642652            UML_AND(block, I0, CCR132(31), 3);                      // and     i0,ccr1[31],3
3065            UML_LOAD(block, I0, &mips3->impstate->fpmode[0], I0, SIZE_BYTE, SCALE_x1);// load   i0,fpmode,i0,byte
2653            UML_LOAD(block, I0, &m_fpmode[0], I0, SIZE_BYTE, SCALE_x1);// load   i0,fpmode,i0,byte
30662654            UML_SETFMOD(block, I0);                                     // setfmod i0
30672655            UML_LABEL(block, skip);                                         // skip:
30682656         }
r30757r30758
30752663            case 0x02:  /* BCzFL - MIPS II */
30762664               UML_TEST(block, CCR132(31), FCCMASK(op >> 18));         // test    ccr1[31],fccmask[which]
30772665               UML_JMPc(block, COND_NZ, skip = compiler->labelnum++);          // jmp     skip,NZ
3078               generate_delay_slot_and_branch(mips3, block, compiler, desc, 0);// <next instruction + hashjmp>
2666               generate_delay_slot_and_branch(block, compiler, desc, 0);// <next instruction + hashjmp>
30792667               UML_LABEL(block, skip);                                     // skip:
30802668               return TRUE;
30812669
r30757r30758
30832671            case 0x03:  /* BCzTL - MIPS II */
30842672               UML_TEST(block, CCR132(31), FCCMASK(op >> 18));         // test    ccr1[31],fccmask[which]
30852673               UML_JMPc(block, COND_Z, skip = compiler->labelnum++);               // jmp     skip,Z
3086               generate_delay_slot_and_branch(mips3, block, compiler, desc, 0);// <next instruction + hashjmp>
2674               generate_delay_slot_and_branch(block, compiler, desc, 0);// <next instruction + hashjmp>
30872675               UML_LABEL(block, skip);                                     // skip:
30882676               return TRUE;
30892677         }
r30757r30758
33902978    generate_cop1x - compile COP1X opcodes
33912979-------------------------------------------------*/
33922980
3393static int generate_cop1x(mips3_state *mips3, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
2981int mips3_device::generate_cop1x(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
33942982{
33952983   int in_delay_slot = ((desc->flags & OPFLAG_IN_DELAY_SLOT) != 0);
33962984   UINT32 op = desc->opptr.l[0];
33972985
3398   if (mips3->impstate->drcoptions & MIPS3DRC_STRICT_COP1)
2986   if (m_drcoptions & MIPS3DRC_STRICT_COP1)
33992987   {
34002988      UML_TEST(block, CPR032(COP0_Status), SR_COP1);                          // test    [Status],SR_COP1
3401      UML_EXHc(block, COND_Z, *mips3->impstate->exception[EXCEPTION_BADCOP], 1);// exh     cop,1,Z
2989      UML_EXHc(block, COND_Z, *m_exception[EXCEPTION_BADCOP], 1);// exh     cop,1,Z
34022990   }
34032991
34042992   switch (op & 0x3f)
34052993   {
34062994      case 0x00:      /* LWXC1 - MIPS IV */
34072995         UML_ADD(block, I0, R32(RSREG), R32(RTREG));                     // add     i0,<rsreg>,<rtreg>
3408         UML_CALLH(block, *mips3->impstate->read32[mips3->impstate->mode >> 1]); // callh   read32
2996         UML_CALLH(block, *m_read32[m_core->mode >> 1]); // callh   read32
34092997         UML_MOV(block, FPR32(FDREG), I0);                                   // mov     <cpr1_fd>,i0
34102998         if (!in_delay_slot)
3411            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
2999            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
34123000         return TRUE;
34133001
34143002      case 0x01:      /* LDXC1 - MIPS IV */
34153003         UML_ADD(block, I0, R32(RSREG), R32(RTREG));                     // add     i0,<rsreg>,<rtreg>
3416         UML_CALLH(block, *mips3->impstate->read64[mips3->impstate->mode >> 1]); // callh   read64
3004         UML_CALLH(block, *m_read64[m_core->mode >> 1]); // callh   read64
34173005         UML_DMOV(block, FPR64(FDREG), I0);                                  // dmov    <cpr1_fd>,i0
34183006         if (!in_delay_slot)
3419            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
3007            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
34203008         return TRUE;
34213009
34223010      case 0x08:      /* SWXC1 - MIPS IV */
34233011         UML_ADD(block, I0, R32(RSREG), R32(RTREG));                     // add     i0,<rsreg>,<rtreg>
34243012         UML_MOV(block, I1, FPR32(FSREG));                                   // mov     i1,<cpr1_fs>
3425         UML_CALLH(block, *mips3->impstate->write32[mips3->impstate->mode >> 1]);    // callh   write32
3013         UML_CALLH(block, *m_write32[m_core->mode >> 1]);    // callh   write32
34263014         if (!in_delay_slot)
3427            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
3015            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
34283016         return TRUE;
34293017
34303018      case 0x09:      /* SDXC1 - MIPS IV */
34313019         UML_ADD(block, I0, R32(RSREG), R32(RTREG));                     // add     i0,<rsreg>,<rtreg>
34323020         UML_DMOV(block, I1, FPR64(FSREG));                                  // dmov    i1,<cpr1_fs>
3433         UML_CALLH(block, *mips3->impstate->write64[mips3->impstate->mode >> 1]);    // callh   write64
3021         UML_CALLH(block, *m_write64[m_core->mode >> 1]);    // callh   write64
34343022         if (!in_delay_slot)
3435            generate_update_cycles(mips3, block, compiler, desc->pc + 4, TRUE);
3023            generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
34363024         return TRUE;
34373025
34383026      case 0x0f:      /* PREFX */
r30757r30758
34983086    including disassembly of a MIPS instruction
34993087-------------------------------------------------*/
35003088
3501static void log_add_disasm_comment(mips3_state *mips3, drcuml_block *block, UINT32 pc, UINT32 op)
3089void mips3_device::log_add_disasm_comment(drcuml_block *block, UINT32 pc, UINT32 op)
35023090{
35033091#if (LOG_UML)
35043092   char buffer[100];
r30757r30758
35143102    flags
35153103-------------------------------------------------*/
35163104
3517static const char *log_desc_flags_to_string(UINT32 flags)
3105const char *mips3_device::log_desc_flags_to_string(UINT32 flags)
35183106{
35193107   static char tempbuf[30];
35203108   char *dest = tempbuf;
r30757r30758
35683156    log_register_list - log a list of GPR registers
35693157-------------------------------------------------*/
35703158
3571static void log_register_list(drcuml_state *drcuml, const char *string, const UINT32 *reglist, const UINT32 *regnostarlist)
3159void mips3_device::log_register_list(drcuml_state *drcuml, const char *string, const UINT32 *reglist, const UINT32 *regnostarlist)
35723160{
35733161   int count = 0;
35743162   int regnum;
r30757r30758
36223210    log_opcode_desc - log a list of descriptions
36233211-------------------------------------------------*/
36243212
3625static void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, int indent)
3213void mips3_device::log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, int indent)
36263214{
36273215   /* open the file, creating it if necessary */
36283216   if (indent == 0)
r30757r30758
36593247   }
36603248}
36613249
3662/***************************************************************************
3663    NEC VR4300 VARIANTS
3664***************************************************************************/
3665
3666// NEC VR4300 series is MIPS III with 32-bit address bus and slightly custom COP0/TLB
3667static CPU_INIT( vr4300be )
3668{
3669   mips3_init(MIPS3_TYPE_VR4300, TRUE, device, irqcallback);
3670}
3671
3672static CPU_INIT( vr4300le )
3673{
3674   mips3_init(MIPS3_TYPE_VR4300, FALSE, device, irqcallback);
3675}
3676
3677CPU_GET_INFO( vr4300be_drc )
3678{
3679   switch (state)
3680   {
3681      /* --- the following bits of info are returned as 64-bit signed integers --- */
3682      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_BIG;                   break;
3683
3684      /* --- the following bits of info are returned as pointers to data or functions --- */
3685      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(vr4300be);               break;
3686
3687      /* --- the following bits of info are returned as NULL-terminated strings --- */
3688      case CPUINFO_STR_NAME:                          strcpy(info->s, "VR4300 (big) DRC");            break;
3689      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "vr4300be_drc");                 break;
3690
3691      /* --- everything else is handled generically --- */
3692      default:                                        CPU_GET_INFO_CALL(mips3);           break;
3693   }
3694}
3695
3696CPU_GET_INFO( vr4300le_drc )
3697{
3698   switch (state)
3699   {
3700      /* --- the following bits of info are returned as 64-bit signed integers --- */
3701      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_LITTLE;                    break;
3702
3703      /* --- the following bits of info are returned as pointers to data or functions --- */
3704      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(vr4300le);               break;
3705
3706      /* --- the following bits of info are returned as NULL-terminated strings --- */
3707      case CPUINFO_STR_NAME:                          strcpy(info->s, "VR4300 (little) DRC");     break;
3708      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "vr4300le_drc");                 break;
3709
3710      /* --- everything else is handled generically --- */
3711      default:                                        CPU_GET_INFO_CALL(mips3);           break;
3712   }
3713}
3714
3715// VR4310 = VR4300 with different speed bin
3716CPU_GET_INFO( vr4310be_drc )
3717{
3718   switch (state)
3719   {
3720      /* --- the following bits of info are returned as 64-bit signed integers --- */
3721      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_BIG;                   break;
3722
3723      /* --- the following bits of info are returned as pointers to data or functions --- */
3724      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(vr4300be);               break;
3725
3726      /* --- the following bits of info are returned as NULL-terminated strings --- */
3727      case CPUINFO_STR_NAME:                          strcpy(info->s, "VR4310 (big) DRC");            break;
3728      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "vr4310be_drc");                 break;
3729
3730      /* --- everything else is handled generically --- */
3731      default:                                        CPU_GET_INFO_CALL(mips3);           break;
3732   }
3733}
3734
3735CPU_GET_INFO( vr4310le_drc )
3736{
3737   switch (state)
3738   {
3739      /* --- the following bits of info are returned as 64-bit signed integers --- */
3740      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_LITTLE;                    break;
3741
3742      /* --- the following bits of info are returned as pointers to data or functions --- */
3743      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(vr4300le);               break;
3744
3745      /* --- the following bits of info are returned as NULL-terminated strings --- */
3746      case CPUINFO_STR_NAME:                          strcpy(info->s, "VR4310 (little) DRC");     break;
3747      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "vr4310le_drc");                 break;
3748
3749      /* --- everything else is handled generically --- */
3750      default:                                        CPU_GET_INFO_CALL(mips3);           break;
3751   }
3752}
3753
3754
3755/***************************************************************************
3756    R4600 VARIANTS
3757***************************************************************************/
3758
3759static CPU_INIT( r4600be )
3760{
3761   mips3_init(MIPS3_TYPE_R4600, TRUE, device, irqcallback);
3762}
3763
3764static CPU_INIT( r4600le )
3765{
3766   mips3_init(MIPS3_TYPE_R4600, FALSE, device, irqcallback);
3767}
3768
3769CPU_GET_INFO( r4600be_drc )
3770{
3771   switch (state)
3772   {
3773      /* --- the following bits of info are returned as 64-bit signed integers --- */
3774      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_BIG;                   break;
3775
3776      /* --- the following bits of info are returned as pointers to data or functions --- */
3777      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(r4600be);                break;
3778
3779      /* --- the following bits of info are returned as NULL-terminated strings --- */
3780      case CPUINFO_STR_NAME:                          strcpy(info->s, "R4600 (big) DRC");         break;
3781      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "r4600be_drc");                 break;
3782
3783      /* --- everything else is handled generically --- */
3784      default:                                        CPU_GET_INFO_CALL(mips3);           break;
3785   }
3786}
3787
3788CPU_GET_INFO( r4600le_drc )
3789{
3790   switch (state)
3791   {
3792      /* --- the following bits of info are returned as 64-bit signed integers --- */
3793      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_LITTLE;                    break;
3794
3795      /* --- the following bits of info are returned as pointers to data or functions --- */
3796      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(r4600le);                break;
3797
3798      /* --- the following bits of info are returned as NULL-terminated strings --- */
3799      case CPUINFO_STR_NAME:                          strcpy(info->s, "R4600 (little) DRC");      break;
3800      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "r4600le_drc");                 break;
3801      /* --- everything else is handled generically --- */
3802      default:                                        CPU_GET_INFO_CALL(mips3);           break;
3803   }
3804}
3805
3806
3807
3808/***************************************************************************
3809    R4650 VARIANTS
3810***************************************************************************/
3811
3812static CPU_INIT( r4650be )
3813{
3814   mips3_init(MIPS3_TYPE_R4650, TRUE, device, irqcallback);
3815}
3816
3817static CPU_INIT( r4650le )
3818{
3819   mips3_init(MIPS3_TYPE_R4650, FALSE, device, irqcallback);
3820}
3821
3822CPU_GET_INFO( r4650be_drc )
3823{
3824   switch (state)
3825   {
3826      /* --- the following bits of info are returned as 64-bit signed integers --- */
3827      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_BIG;                   break;
3828
3829      /* --- the following bits of info are returned as pointers to data or functions --- */
3830      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(r4650be);                break;
3831
3832      /* --- the following bits of info are returned as NULL-terminated strings --- */
3833      case CPUINFO_STR_NAME:                          strcpy(info->s, "IDT R4650 (big) DRC");     break;
3834      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "r4650be_drc");                 break;
3835
3836      /* --- everything else is handled generically --- */
3837      default:                                        CPU_GET_INFO_CALL(mips3);           break;
3838   }
3839}
3840
3841CPU_GET_INFO( r4650le_drc )
3842{
3843   switch (state)
3844   {
3845      /* --- the following bits of info are returned as 64-bit signed integers --- */
3846      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_LITTLE;                    break;
3847
3848      /* --- the following bits of info are returned as pointers to data or functions --- */
3849      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(r4650le);                break;
3850
3851      /* --- the following bits of info are returned as NULL-terminated strings --- */
3852      case CPUINFO_STR_NAME:                          strcpy(info->s, "IDT R4650 (little) DRC");  break;
3853      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "r4650le_drc");                 break;
3854
3855      /* --- everything else is handled generically --- */
3856      default:                                        CPU_GET_INFO_CALL(mips3);           break;
3857   }
3858}
3859
3860
3861
3862/***************************************************************************
3863    R4700 VARIANTS
3864***************************************************************************/
3865
3866static CPU_INIT( r4700be )
3867{
3868   mips3_init(MIPS3_TYPE_R4700, TRUE, device, irqcallback);
3869}
3870
3871static CPU_INIT( r4700le )
3872{
3873   mips3_init(MIPS3_TYPE_R4700, FALSE, device, irqcallback);
3874}
3875
3876CPU_GET_INFO( r4700be_drc )
3877{
3878   switch (state)
3879   {
3880      /* --- the following bits of info are returned as 64-bit signed integers --- */
3881      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_BIG;                   break;
3882
3883      /* --- the following bits of info are returned as pointers to data or functions --- */
3884      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(r4700be);                break;
3885
3886      /* --- the following bits of info are returned as NULL-terminated strings --- */
3887      case CPUINFO_STR_NAME:                          strcpy(info->s, "R4700 (big) DRC");         break;
3888      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "r4700be_drc");                 break;
3889
3890      /* --- everything else is handled generically --- */
3891      default:                                        CPU_GET_INFO_CALL(mips3);           break;
3892   }
3893}
3894
3895CPU_GET_INFO( r4700le_drc )
3896{
3897   switch (state)
3898   {
3899      /* --- the following bits of info are returned as 64-bit signed integers --- */
3900      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_LITTLE;                    break;
3901
3902      /* --- the following bits of info are returned as pointers to data or functions --- */
3903      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(r4700le);                break;
3904
3905      /* --- the following bits of info are returned as NULL-terminated strings --- */
3906      case CPUINFO_STR_NAME:                          strcpy(info->s, "R4700 (little) DRC");      break;
3907      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "r4700le_drc");                 break;
3908
3909      /* --- everything else is handled generically --- */
3910      default:                                        CPU_GET_INFO_CALL(mips3);           break;
3911   }
3912}
3913
3914
3915
3916/***************************************************************************
3917    R5000 VARIANTS
3918***************************************************************************/
3919
3920static CPU_INIT( r5000be )
3921{
3922   mips3_init(MIPS3_TYPE_R5000, TRUE, device, irqcallback);
3923}
3924
3925static CPU_INIT( r5000le )
3926{
3927   mips3_init(MIPS3_TYPE_R5000, FALSE, device, irqcallback);
3928}
3929
3930CPU_GET_INFO( r5000be_drc )
3931{
3932   switch (state)
3933   {
3934      /* --- the following bits of info are returned as 64-bit signed integers --- */
3935      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_BIG;                   break;
3936
3937      /* --- the following bits of info are returned as pointers to data or functions --- */
3938      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(r5000be);                break;
3939
3940      /* --- the following bits of info are returned as NULL-terminated strings --- */
3941      case CPUINFO_STR_NAME:                          strcpy(info->s, "R5000 (big) DRC");         break;
3942      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "r5000be_drc");                 break;
3943
3944      /* --- everything else is handled generically --- */
3945      default:                                        CPU_GET_INFO_CALL(mips3);           break;
3946   }
3947}
3948
3949CPU_GET_INFO( r5000le_drc )
3950{
3951   switch (state)
3952   {
3953      /* --- the following bits of info are returned as 64-bit signed integers --- */
3954      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_LITTLE;                    break;
3955
3956      /* --- the following bits of info are returned as pointers to data or functions --- */
3957      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(r5000le);                break;
3958
3959      /* --- the following bits of info are returned as NULL-terminated strings --- */
3960      case CPUINFO_STR_NAME:                          strcpy(info->s, "R5000 (little) DRC");      break;
3961      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "r5000le_drc");                 break;
3962
3963      /* --- everything else is handled generically --- */
3964      default:                                        CPU_GET_INFO_CALL(mips3);           break;
3965   }
3966}
3967
3968
3969
3970/***************************************************************************
3971    QED5271 VARIANTS
3972***************************************************************************/
3973
3974static CPU_INIT( qed5271be )
3975{
3976   mips3_init(MIPS3_TYPE_QED5271, TRUE, device, irqcallback);
3977}
3978
3979static CPU_INIT( qed5271le )
3980{
3981   mips3_init(MIPS3_TYPE_QED5271, FALSE, device, irqcallback);
3982}
3983
3984CPU_GET_INFO( qed5271be_drc )
3985{
3986   switch (state)
3987   {
3988      /* --- the following bits of info are returned as 64-bit signed integers --- */
3989      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_BIG;                   break;
3990
3991      /* --- the following bits of info are returned as pointers to data or functions --- */
3992      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(qed5271be);          break;
3993
3994      /* --- the following bits of info are returned as NULL-terminated strings --- */
3995      case CPUINFO_STR_NAME:                          strcpy(info->s, "QED5271 (big) DRC");       break;
3996      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "qed5271be_drc");                 break;
3997
3998      /* --- everything else is handled generically --- */
3999      default:                                        CPU_GET_INFO_CALL(mips3);           break;
4000   }
4001}
4002
4003CPU_GET_INFO( qed5271le_drc )
4004{
4005   switch (state)
4006   {
4007      /* --- the following bits of info are returned as 64-bit signed integers --- */
4008      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_LITTLE;                    break;
4009
4010      /* --- the following bits of info are returned as pointers to data or functions --- */
4011      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(qed5271le);          break;
4012
4013      /* --- the following bits of info are returned as NULL-terminated strings --- */
4014      case CPUINFO_STR_NAME:                          strcpy(info->s, "QED5271 (little) DRC");    break;
4015      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "qed5271le_drc");                 break;
4016
4017      /* --- everything else is handled generically --- */
4018      default:                                        CPU_GET_INFO_CALL(mips3);           break;
4019   }
4020}
4021
4022
4023
4024/***************************************************************************
4025    RM7000 VARIANTS
4026***************************************************************************/
4027
4028static CPU_INIT( rm7000be )
4029{
4030   mips3_init(MIPS3_TYPE_RM7000, TRUE, device, irqcallback);
4031}
4032
4033static CPU_INIT( rm7000le )
4034{
4035   mips3_init(MIPS3_TYPE_RM7000, FALSE, device, irqcallback);
4036}
4037
4038CPU_GET_INFO( rm7000be_drc )
4039{
4040   switch (state)
4041   {
4042      /* --- the following bits of info are returned as 64-bit signed integers --- */
4043      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_BIG;                   break;
4044
4045      /* --- the following bits of info are returned as pointers to data or functions --- */
4046      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(rm7000be);               break;
4047
4048      /* --- the following bits of info are returned as NULL-terminated strings --- */
4049      case CPUINFO_STR_NAME:                          strcpy(info->s, "RM7000 (big) DRC");        break;
4050      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "rm7000be_drc");        break;
4051
4052      /* --- everything else is handled generically --- */
4053      default:                                        CPU_GET_INFO_CALL(mips3);           break;
4054   }
4055}
4056
4057CPU_GET_INFO( rm7000le_drc )
4058{
4059   switch (state)
4060   {
4061      /* --- the following bits of info are returned as 64-bit signed integers --- */
4062      case CPUINFO_INT_ENDIANNESS:                    info->i = ENDIANNESS_LITTLE;                    break;
4063
4064      /* --- the following bits of info are returned as pointers to data or functions --- */
4065      case CPUINFO_FCT_INIT:                          info->init = CPU_INIT_NAME(rm7000le);               break;
4066
4067      /* --- the following bits of info are returned as NULL-terminated strings --- */
4068      case CPUINFO_STR_NAME:                          strcpy(info->s, "RM7000 (little) DRC");     break;
4069      case CPUINFO_STR_SHORTNAME:                     strcpy(info->s, "rm7000le_drc");        break;
4070
4071      /* --- everything else is handled generically --- */
4072      default:                                        CPU_GET_INFO_CALL(mips3);           break;
4073   }
4074}
4075
4076DEFINE_LEGACY_CPU_DEVICE(VR4300BE_DRC, vr4300be_drc);
4077DEFINE_LEGACY_CPU_DEVICE(VR4300LE_DRC, vr4300le_drc);
4078DEFINE_LEGACY_CPU_DEVICE(VR4310BE_DRC, vr4310be_drc);
4079DEFINE_LEGACY_CPU_DEVICE(VR4310LE_DRC, vr4310le_drc);
4080
4081DEFINE_LEGACY_CPU_DEVICE(R4600BE_DRC, r4600be_drc);
4082DEFINE_LEGACY_CPU_DEVICE(R4600LE_DRC, r4600le_drc);
4083
4084DEFINE_LEGACY_CPU_DEVICE(R4650BE_DRC, r4650be_drc);
4085DEFINE_LEGACY_CPU_DEVICE(R4650LE_DRC, r4650le_drc);
4086
4087DEFINE_LEGACY_CPU_DEVICE(R4700BE_DRC, r4700be_drc);
4088DEFINE_LEGACY_CPU_DEVICE(R4700LE_DRC, r4700le_drc);
4089
4090DEFINE_LEGACY_CPU_DEVICE(R5000BE_DRC, r5000be_drc);
4091DEFINE_LEGACY_CPU_DEVICE(R5000LE_DRC, r5000le_drc);
4092
4093DEFINE_LEGACY_CPU_DEVICE(QED5271BE_DRC, qed5271be_drc);
4094DEFINE_LEGACY_CPU_DEVICE(QED5271LE_DRC, qed5271le_drc);
4095
4096DEFINE_LEGACY_CPU_DEVICE(RM7000BE_DRC, rm7000be_drc);
4097DEFINE_LEGACY_CPU_DEVICE(RM7000LE_DRC, rm7000le_drc);
trunk/src/emu/cpu/mips/mips3fe.c
r30757r30758
2121//  mips3_frontend - constructor
2222//-------------------------------------------------
2323
24mips3_frontend::mips3_frontend(mips3_state &state, UINT32 window_start, UINT32 window_end, UINT32 max_sequence)
25   : drc_frontend(*state.device, window_start, window_end, max_sequence),
26      m_context(state)
24mips3_frontend::mips3_frontend(mips3_device *mips3, UINT32 window_start, UINT32 window_end, UINT32 max_sequence)
25   : drc_frontend(*mips3, window_start, window_end, max_sequence),
26      m_mips3(mips3)
2727{
2828}
2929
r30757r30758
3939
4040   // compute the physical PC
4141   assert((desc.physpc & 3) == 0);
42   if (!mips3com_translate_address(&m_context, AS_PROGRAM, TRANSLATE_FETCH, &desc.physpc))
42   if (!m_mips3->memory_translate(AS_PROGRAM, TRANSLATE_FETCH, desc.physpc))
4343   {
4444      // uh-oh: a page fault; leave the description empty and just if this is the first instruction, leave it empty and
4545      // mark as needing to validate; otherwise, just end the sequence here
r30757r30758
4949
5050   // fetch the opcode
5151   assert((desc.physpc & 3) == 0);
52   op = desc.opptr.l[0] = m_context.direct->read_decrypted_dword(desc.physpc);
52   op = desc.opptr.l[0] = m_mips3->m_direct->read_decrypted_dword(desc.physpc);
5353
5454   // all instructions are 4 bytes and default to a single cycle each
5555   desc.length = 4;
r30757r30758
7575         return describe_cop2(op, desc);
7676
7777      case 0x13:  // COP1X - MIPS IV
78         if (m_context.flavor < MIPS3_TYPE_MIPS_IV)
78         if (m_mips3->m_flavor < mips3_device::MIPS3_TYPE_MIPS_IV)
7979            return false;
8080         return describe_cop1x(op, desc);
8181
r30757r30758
214214         return true;
215215
216216      case 0x33:  // PREF
217         if (m_context.flavor < MIPS3_TYPE_MIPS_IV)
217         if (m_mips3->m_flavor < mips3_device::MIPS3_TYPE_MIPS_IV)
218218            return false;
219219      case 0x2f:  // CACHE
220220         // effective no-op
r30757r30758
249249
250250      case 0x0a:  // MOVZ - MIPS IV
251251      case 0x0b:  // MOVN - MIPS IV
252         if (m_context.flavor < MIPS3_TYPE_MIPS_IV)
252         if (m_mips3->m_flavor < mips3_device::MIPS3_TYPE_MIPS_IV)
253253            return false;
254254         desc.regin[0] |= REGFLAG_R(RDREG);
255255      case 0x04:  // SLLV
r30757r30758
292292         return true;
293293
294294      case 0x01:  // MOVF - MIPS IV
295         if (m_context.flavor < MIPS3_TYPE_MIPS_IV)
295         if (m_mips3->m_flavor < mips3_device::MIPS3_TYPE_MIPS_IV)
296296            return false;
297297         desc.regin[0] |= REGFLAG_R(RSREG);
298298         desc.regin[2] |= REGFLAG_FCC;
r30757r30758
441441bool mips3_frontend::describe_idt(UINT32 op, opcode_desc &desc)
442442{
443443   // only on the R4650
444   if (m_context.flavor != MIPS3_TYPE_R4650)
444   if (m_mips3->m_flavor != mips3_device::MIPS3_TYPE_R4650)
445445      return false;
446446
447447   switch (op & 0x1f)
r30757r30758
593593         {
594594            case 0x12:  // MOVZ - MIPS IV
595595            case 0x13:  // MOVN - MIPS IV
596               if (m_context.flavor < MIPS3_TYPE_MIPS_IV)
596               if (m_mips3->m_flavor < mips3_device::MIPS3_TYPE_MIPS_IV)
597597                  return false;
598598            case 0x00:  // ADD
599599            case 0x01:  // SUB
r30757r30758
605605
606606            case 0x15:  // RECIP - MIPS IV
607607            case 0x16:  // RSQRT - MIPS IV
608               if (m_context.flavor < MIPS3_TYPE_MIPS_IV)
608               if (m_mips3->m_flavor < mips3_device::MIPS3_TYPE_MIPS_IV)
609609                  return false;
610610            case 0x04:  // SQRT
611611            case 0x05:  // ABS
r30757r30758
628628               return true;
629629
630630            case 0x11:  // MOVT/F - MIPS IV
631               if (m_context.flavor < MIPS3_TYPE_MIPS_IV)
631               if (m_mips3->m_flavor < mips3_device::MIPS3_TYPE_MIPS_IV)
632632                  return false;
633633               desc.regin[1] |= REGFLAG_CPR1(FSREG);
634634               desc.regin[2] |= REGFLAG_FCC;
trunk/src/mess/drivers/ip22.c
r30757r30758
112112   {
113113   }
114114
115   required_device<cpu_device> m_maincpu;
115   required_device<mips3_device> m_maincpu;
116116   required_device<wd33c93_device> m_wd33c93;
117117   required_shared_ptr<UINT32> m_unkpbus0;
118118   required_shared_ptr<UINT32> m_mainram;
r30757r30758
12221222
12231223   m_PBUS_DMA.nActive = 0;
12241224
1225   mips3drc_set_options(m_maincpu, MIPS3DRC_COMPATIBLE_OPTIONS | MIPS3DRC_CHECK_OVERFLOWS);
1225   m_maincpu->mips3drc_set_options(MIPS3DRC_COMPATIBLE_OPTIONS | MIPS3DRC_CHECK_OVERFLOWS);
12261226}
12271227
12281228void ip22_state::dump_chain(address_space &space, UINT32 ch_base)

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