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r30729 Friday 30th May, 2014 at 20:23:03 UTC by David Haywood
start to make the z84 a proper cpu type, migrate code from niyanpai to the cpu.

spent most of the day (many hours) trying to work out why this was hanging with my changes only to find out the 68k change broke the driver (it's still broken, i don't have time to fix it) :/
[src/emu/cpu/z80]z80.c z80.h
[src/mame/drivers]niyanpai.c
[src/mame/includes]niyanpai.h

trunk/src/emu/cpu/z80/z80.c
r30728r30729
37373737const device_type NSC800 = &device_creator<nsc800_device>;
37383738
37393739
3740// todo, move per-driver implementations (eg. nbmj9195.c) to here with callbacks for the ports
37413740
3741READ8_MEMBER(tmpz84c011_device::porta_default_r) { logerror("%s read port A but no handler assigned\n", machine().describe_context()); return 0xff; }
3742READ8_MEMBER(tmpz84c011_device::portb_default_r) { logerror("%s read port B but no handler assigned\n", machine().describe_context()); return 0xff; }
3743READ8_MEMBER(tmpz84c011_device::portc_default_r) { logerror("%s read port C but no handler assigned\n", machine().describe_context()); return 0xff; }
3744READ8_MEMBER(tmpz84c011_device::portd_default_r) { logerror("%s read port D but no handler assigned\n", machine().describe_context()); return 0xff; }
3745READ8_MEMBER(tmpz84c011_device::porte_default_r) { logerror("%s read port E but no handler assigned\n", machine().describe_context()); return 0xff; }
3746
3747WRITE8_MEMBER(tmpz84c011_device::porta_default_w) { logerror("%s write %02x to port A but no handler assigned\n", machine().describe_context(), data); }
3748WRITE8_MEMBER(tmpz84c011_device::portb_default_w) { logerror("%s write %02x to port B but no handler assigned\n", machine().describe_context(), data); }
3749WRITE8_MEMBER(tmpz84c011_device::portc_default_w) { logerror("%s write %02x to port C but no handler assigned\n", machine().describe_context(), data); }
3750WRITE8_MEMBER(tmpz84c011_device::portd_default_w) { logerror("%s write %02x to port D but no handler assigned\n", machine().describe_context(), data); }
3751WRITE8_MEMBER(tmpz84c011_device::porte_default_w) { logerror("%s write %02x to port E but no handler assigned\n", machine().describe_context(), data); }
3752
3753
3754READ8_MEMBER(tmpz84c011_device::tmpz84c011_pio_r)
3755{
3756   int portdata = 0xff;
3757
3758   switch (offset)
3759   {
3760      case 0:         /* PA_0 */
3761         portdata = m_inports0();
3762         break;
3763      case 1:         /* PB_0 */
3764         portdata = m_inports1();
3765         break;
3766      case 2:         /* PC_0 */
3767         portdata = m_inports2();
3768         break;
3769      case 3:         /* PD_0 */
3770         portdata = m_inports3();
3771         break;
3772      case 4:         /* PE_0 */
3773         portdata = m_inports4();
3774         break;
3775   }
3776
3777   return portdata;
3778}
3779
3780WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_pio_w)
3781{
3782   switch (offset)
3783   {
3784      case 0:         /* PA_0 */
3785         m_outports0(data);
3786         break;
3787      case 1:         /* PB_0 */
3788         m_outports1(data);
3789         break;
3790      case 2:         /* PC_0 */
3791         m_outports2(data);
3792         break;
3793      case 3:         /* PD_0 */
3794         m_outports3(data);
3795         break;
3796      case 4:         /* PE_0 */
3797         m_outports4(data);
3798         break;
3799   }
3800}
3801
3802/* CPU interface */
3803READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pa_r)
3804{
3805   return (tmpz84c011_pio_r(space,0) & ~m_pio_dir[0]) | (m_pio_latch[0] & m_pio_dir[0]);
3806}
3807
3808READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pb_r)
3809{
3810   return (tmpz84c011_pio_r(space,1) & ~m_pio_dir[1]) | (m_pio_latch[1] & m_pio_dir[1]);
3811}
3812
3813READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pc_r)
3814{
3815   return (tmpz84c011_pio_r(space,2) & ~m_pio_dir[2]) | (m_pio_latch[2] & m_pio_dir[2]);
3816}
3817
3818READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pd_r)
3819{
3820   return (tmpz84c011_pio_r(space,3) & ~m_pio_dir[3]) | (m_pio_latch[3] & m_pio_dir[3]);
3821}
3822
3823READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pe_r)
3824{
3825   return (tmpz84c011_pio_r(space,4) & ~m_pio_dir[4]) | (m_pio_latch[4] & m_pio_dir[4]);
3826}
3827
3828WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pa_w)
3829{
3830   m_pio_latch[0] = data;
3831   tmpz84c011_pio_w(space, 0, data);
3832}
3833
3834WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pb_w)
3835{
3836   m_pio_latch[1] = data;
3837   tmpz84c011_pio_w(space, 1, data);
3838}
3839WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pc_w)
3840{
3841   m_pio_latch[2] = data;
3842   tmpz84c011_pio_w(space, 2, data);
3843}
3844
3845WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pd_w)
3846{
3847   m_pio_latch[3] = data;
3848   tmpz84c011_pio_w(space, 3, data);
3849}
3850
3851WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pe_w)
3852{
3853   m_pio_latch[4] = data;
3854   tmpz84c011_pio_w(space, 4, data);
3855}
3856
3857READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pa_r)
3858{
3859   return m_pio_dir[0];
3860}
3861
3862READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pb_r)
3863{
3864   return m_pio_dir[1];
3865}
3866
3867READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pc_r)
3868{
3869   return m_pio_dir[2];
3870}
3871
3872READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pd_r)
3873{
3874   return m_pio_dir[3];
3875}
3876
3877READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pe_r)
3878{
3879   return m_pio_dir[4];
3880}
3881
3882WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pa_w)
3883{
3884   m_pio_dir[0] = data;
3885}
3886
3887WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pb_w)
3888{
3889   m_pio_dir[1] = data;
3890}
3891
3892WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pc_w)
3893{
3894   m_pio_dir[2] = data;
3895}
3896
3897WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pd_w)
3898{
3899   m_pio_dir[3] = data;
3900}
3901
3902WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pe_w)
3903{
3904   m_pio_dir[4] = data;
3905}
3906
3907
3908
3909static ADDRESS_MAP_START( tmpz84c011_internal_io_map, AS_IO, 8, tmpz84c011_device )
3910   AM_RANGE(0x50, 0x50) AM_READWRITE(tmpz84c011_0_pa_r, tmpz84c011_0_pa_w) AM_MIRROR(0xff00)
3911   AM_RANGE(0x51, 0x51) AM_READWRITE(tmpz84c011_0_pb_r, tmpz84c011_0_pb_w) AM_MIRROR(0xff00)
3912   AM_RANGE(0x52, 0x52) AM_READWRITE(tmpz84c011_0_pc_r, tmpz84c011_0_pc_w) AM_MIRROR(0xff00)
3913   AM_RANGE(0x30, 0x30) AM_READWRITE(tmpz84c011_0_pd_r, tmpz84c011_0_pd_w) AM_MIRROR(0xff00)
3914   AM_RANGE(0x40, 0x40) AM_READWRITE(tmpz84c011_0_pe_r, tmpz84c011_0_pe_w) AM_MIRROR(0xff00)
3915   AM_RANGE(0x54, 0x54) AM_READWRITE(tmpz84c011_0_dir_pa_r, tmpz84c011_0_dir_pa_w) AM_MIRROR(0xff00)
3916   AM_RANGE(0x55, 0x55) AM_READWRITE(tmpz84c011_0_dir_pb_r, tmpz84c011_0_dir_pb_w) AM_MIRROR(0xff00)
3917   AM_RANGE(0x56, 0x56) AM_READWRITE(tmpz84c011_0_dir_pc_r, tmpz84c011_0_dir_pc_w) AM_MIRROR(0xff00)
3918   AM_RANGE(0x34, 0x34) AM_READWRITE(tmpz84c011_0_dir_pd_r, tmpz84c011_0_dir_pd_w) AM_MIRROR(0xff00)
3919   AM_RANGE(0x44, 0x44) AM_READWRITE(tmpz84c011_0_dir_pe_r, tmpz84c011_0_dir_pe_w) AM_MIRROR(0xff00)
3920ADDRESS_MAP_END
3921
3922
37423923tmpz84c011_device::tmpz84c011_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
3743   : z80_device(mconfig, TMPZ84C011, "TMPZ84C011", tag, owner, clock, "tmpz84c011", __FILE__)
3924   : z80_device(mconfig, TMPZ84C011, "TMPZ84C011", tag, owner, clock, "tmpz84c011", __FILE__),
3925   m_io_space_config( "io", ENDIANNESS_LITTLE, 8, 16, 0, ADDRESS_MAP_NAME( tmpz84c011_internal_io_map ) ),
3926   m_outports0(*this),
3927   m_outports1(*this),
3928   m_outports2(*this),
3929   m_outports3(*this),
3930   m_outports4(*this),
3931   m_inports0(*this),
3932   m_inports1(*this),
3933   m_inports2(*this),
3934   m_inports3(*this),
3935   m_inports4(*this)
37443936{
37453937}
37463938
37473939const device_type TMPZ84C011 = &device_creator<tmpz84c011_device>;
37483940
37493941
3942void tmpz84c011_device::device_start()
3943{
3944   z80_device::device_start();
3945
3946   m_outports0.resolve_safe();
3947   m_outports1.resolve_safe();
3948   m_outports2.resolve_safe();
3949   m_outports3.resolve_safe();
3950   m_outports4.resolve_safe();
3951
3952   m_inports0.resolve_safe(0);
3953   m_inports1.resolve_safe(0);
3954   m_inports2.resolve_safe(0);
3955   m_inports3.resolve_safe(0);
3956   m_inports4.resolve_safe(0);
3957}
3958
3959void tmpz84c011_device::device_reset()
3960{
3961   z80_device::device_reset();
3962
3963   // initialize TMPZ84C011 PIO
3964   for (int i = 0; i < 5; i++)
3965   {
3966      m_pio_dir[i] = m_pio_latch[i] = 0;
3967      tmpz84c011_pio_w(*m_io, i, 0);
3968   }
3969}
3970
3971
37503972WRITE_LINE_MEMBER( z80_device::irq_line )
37513973{
37523974   set_input_line( INPUT_LINE_IRQ0, state );
trunk/src/emu/cpu/z80/z80.h
r30728r30729
334334   }
335335};
336336
337
338
337339extern const device_type TLCS_Z80;
338340
339341
342
343#define MCFG_TMPZ84C011_PORTA_READ_CALLBACK(_devcb) \
344   devcb = &tmpz84c011_device::set_inports0_cb(*device, DEVCB_##_devcb);
345
346#define MCFG_TMPZ84C011_PORTB_READ_CALLBACK(_devcb) \
347   devcb = &tmpz84c011_device::set_inports1_cb(*device, DEVCB_##_devcb);
348
349#define MCFG_TMPZ84C011_PORTC_READ_CALLBACK(_devcb) \
350   devcb = &tmpz84c011_device::set_inports2_cb(*device, DEVCB_##_devcb);
351
352#define MCFG_TMPZ84C011_PORTD_READ_CALLBACK(_devcb) \
353   devcb = &tmpz84c011_device::set_inports3_cb(*device, DEVCB_##_devcb);
354
355#define MCFG_TMPZ84C011_PORTE_READ_CALLBACK(_devcb) \
356   devcb = &tmpz84c011_device::set_inports4_cb(*device, DEVCB_##_devcb);
357
358
359#define MCFG_TMPZ84C011_PORTA_WRITE_CALLBACK(_devcb) \
360   devcb = &tmpz84c011_device::set_outports0_cb(*device, DEVCB_##_devcb);
361
362#define MCFG_TMPZ84C011_PORTB_WRITE_CALLBACK(_devcb) \
363   devcb = &tmpz84c011_device::set_outports1_cb(*device, DEVCB_##_devcb);
364
365#define MCFG_TMPZ84C011_PORTC_WRITE_CALLBACK(_devcb) \
366   devcb = &tmpz84c011_device::set_outports2_cb(*device, DEVCB_##_devcb);
367
368#define MCFG_TMPZ84C011_PORTD_WRITE_CALLBACK(_devcb) \
369   devcb = &tmpz84c011_device::set_outports3_cb(*device, DEVCB_##_devcb);
370
371#define MCFG_TMPZ84C011_PORTE_WRITE_CALLBACK(_devcb) \
372   devcb = &tmpz84c011_device::set_outports4_cb(*device, DEVCB_##_devcb);
373
374
375
376
377
340378class tmpz84c011_device : public z80_device
341379{
342380public:
343381   tmpz84c011_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32);
344382
383   template<class _Object> static devcb_base & set_outports0_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports0.set_callback(object); }
384   template<class _Object> static devcb_base & set_outports1_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports1.set_callback(object); }
385   template<class _Object> static devcb_base & set_outports2_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports2.set_callback(object); }
386   template<class _Object> static devcb_base & set_outports3_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports3.set_callback(object); }
387   template<class _Object> static devcb_base & set_outports4_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports4.set_callback(object); }
388
389   template<class _Object> static devcb_base & set_inports0_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports0.set_callback(object); }
390   template<class _Object> static devcb_base & set_inports1_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports1.set_callback(object); }
391   template<class _Object> static devcb_base & set_inports2_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports2.set_callback(object); }
392   template<class _Object> static devcb_base & set_inports3_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports3.set_callback(object); }
393   template<class _Object> static devcb_base & set_inports4_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports4.set_callback(object); }
394
395
396   DECLARE_READ8_MEMBER(tmpz84c011_pio_r);
397   DECLARE_WRITE8_MEMBER(tmpz84c011_pio_w);
398   DECLARE_READ8_MEMBER(tmpz84c011_0_pa_r);
399   DECLARE_READ8_MEMBER(tmpz84c011_0_pb_r);
400   DECLARE_READ8_MEMBER(tmpz84c011_0_pc_r);
401   DECLARE_READ8_MEMBER(tmpz84c011_0_pd_r);
402   DECLARE_READ8_MEMBER(tmpz84c011_0_pe_r);
403   DECLARE_WRITE8_MEMBER(tmpz84c011_0_pa_w);
404   DECLARE_WRITE8_MEMBER(tmpz84c011_0_pb_w);
405   DECLARE_WRITE8_MEMBER(tmpz84c011_0_pc_w);
406   DECLARE_WRITE8_MEMBER(tmpz84c011_0_pd_w);
407   DECLARE_WRITE8_MEMBER(tmpz84c011_0_pe_w);
408   DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pa_r);
409   DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pb_r);
410   DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pc_r);
411   DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pd_r);
412   DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pe_r);
413   DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pa_w);
414   DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pb_w);
415   DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pc_w);
416   DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pd_w);
417   DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pe_w);
418
419   DECLARE_READ8_MEMBER(porta_default_r);
420   DECLARE_READ8_MEMBER(portb_default_r);
421   DECLARE_READ8_MEMBER(portc_default_r);
422   DECLARE_READ8_MEMBER(portd_default_r);
423   DECLARE_READ8_MEMBER(porte_default_r);
424
425   DECLARE_WRITE8_MEMBER(porta_default_w);
426   DECLARE_WRITE8_MEMBER(portb_default_w);
427   DECLARE_WRITE8_MEMBER(portc_default_w);
428   DECLARE_WRITE8_MEMBER(portd_default_w);
429   DECLARE_WRITE8_MEMBER(porte_default_w);
430
431
432
345433protected:
434   // device-level overrides
435   virtual void device_start();
436   virtual void device_reset();
437
438   const address_space_config m_io_space_config;
439
440   const address_space_config *memory_space_config(address_spacenum spacenum) const
441   {
442      switch (spacenum)
443      {
444         case AS_IO: return &m_io_space_config;
445         default: return z80_device::memory_space_config(spacenum);
446      }
447   }
448
449
450   UINT8 m_pio_dir[5];
451   UINT8 m_pio_latch[5];
452
453private:
454   devcb_write8      m_outports0;
455   devcb_write8      m_outports1;
456   devcb_write8      m_outports2;
457   devcb_write8      m_outports3;
458   devcb_write8      m_outports4;
459
460   devcb_read8       m_inports0;
461   devcb_read8       m_inports1;
462   devcb_read8       m_inports2;
463   devcb_read8       m_inports3;
464   devcb_read8       m_inports4;
465
346466};
347467
348468extern const device_type TMPZ84C011;
trunk/src/mame/includes/niyanpai.h
r30728r30729
2121
2222   int m_musobana_inputport;
2323   int m_musobana_outcoin_flag;
24   UINT8 m_pio_dir[5];
25   UINT8 m_pio_latch[5];
24
2625   int m_scrollx[VRAM_MAX];
2726   int m_scrolly[VRAM_MAX];
2827   int m_blitter_destx[VRAM_MAX];
r30728r30729
4948   DECLARE_READ8_MEMBER(niyanpai_sound_r);
5049   DECLARE_WRITE16_MEMBER(niyanpai_sound_w);
5150   DECLARE_WRITE8_MEMBER(niyanpai_soundclr_w);
52   DECLARE_READ8_MEMBER(tmpz84c011_pio_r);
53   DECLARE_WRITE8_MEMBER(tmpz84c011_pio_w);
54   DECLARE_READ8_MEMBER(tmpz84c011_0_pa_r);
55   DECLARE_READ8_MEMBER(tmpz84c011_0_pb_r);
56   DECLARE_READ8_MEMBER(tmpz84c011_0_pc_r);
57   DECLARE_READ8_MEMBER(tmpz84c011_0_pd_r);
58   DECLARE_READ8_MEMBER(tmpz84c011_0_pe_r);
59   DECLARE_WRITE8_MEMBER(tmpz84c011_0_pa_w);
60   DECLARE_WRITE8_MEMBER(tmpz84c011_0_pb_w);
61   DECLARE_WRITE8_MEMBER(tmpz84c011_0_pc_w);
62   DECLARE_WRITE8_MEMBER(tmpz84c011_0_pd_w);
63   DECLARE_WRITE8_MEMBER(tmpz84c011_0_pe_w);
64   DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pa_r);
65   DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pb_r);
66   DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pc_r);
67   DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pd_r);
68   DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pe_r);
69   DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pa_w);
70   DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pb_w);
71   DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pc_w);
72   DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pd_w);
73   DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pe_w);
51
52   DECLARE_READ8_MEMBER(cpu_portd_r);
53   DECLARE_WRITE8_MEMBER(cpu_porta_w);
54   DECLARE_WRITE8_MEMBER(cpu_portb_w);
55   DECLARE_WRITE8_MEMBER(cpu_portc_w);
56   DECLARE_WRITE8_MEMBER(cpu_porte_w);
57   
7458   DECLARE_READ16_MEMBER(niyanpai_dipsw_r);
7559   DECLARE_READ16_MEMBER(musobana_inputport_0_r);
7660   DECLARE_WRITE16_MEMBER(musobana_inputport_w);
trunk/src/mame/drivers/niyanpai.c
r30728r30729
6969}
7070
7171
72/* TMPZ84C011 PIO emulation */
73
74READ8_MEMBER(niyanpai_state::tmpz84c011_pio_r)
72READ8_MEMBER(niyanpai_state::cpu_portd_r)
7573{
76   int portdata;
77
78   switch (offset)
79   {
80      case 0:         /* PA_0 */
81         portdata = 0xff;
82         break;
83      case 1:         /* PB_0 */
84         portdata = 0xff;
85         break;
86      case 2:         /* PC_0 */
87         portdata = 0xff;
88         break;
89      case 3:         /* PD_0 */
90         portdata = niyanpai_sound_r(space, 0);
91         break;
92      case 4:         /* PE_0 */
93         portdata = 0xff;
94         break;
95
96      default:
97         logerror("%s: TMPZ84C011_PIO Unknown Port Read %02X\n", machine().describe_context(), offset);
98         portdata = 0xff;
99         break;
100   }
101
102   return portdata;
74   return niyanpai_sound_r(space, 0);
10375}
10476
105WRITE8_MEMBER(niyanpai_state::tmpz84c011_pio_w)
77WRITE8_MEMBER(niyanpai_state::cpu_porta_w)
10678{
107   switch (offset)
108   {
109      case 0:         /* PA_0 */
110         niyanpai_soundbank_w(data & 0x03);
111         break;
112      case 1:         /* PB_0 */
113         m_dac1->write_unsigned8(data);
114         break;
115      case 2:         /* PC_0 */
116         m_dac2->write_unsigned8(data);
117         break;
118      case 3:         /* PD_0 */
119         break;
120      case 4:         /* PE_0 */
121         if (!(data & 0x01)) niyanpai_soundclr_w(space, 0, 0);
122         break;
123
124      default:
125         logerror("%s: TMPZ84C011_PIO Unknown Port Write %02X, %02X\n", machine().describe_context(), offset, data);
126         break;
127   }
79   niyanpai_soundbank_w(data & 0x03);
12880}
12981
130/* CPU interface */
131READ8_MEMBER(niyanpai_state::tmpz84c011_0_pa_r)
82WRITE8_MEMBER(niyanpai_state::cpu_portb_w)
13283{
133   return (tmpz84c011_pio_r(space,0) & ~m_pio_dir[0]) | (m_pio_latch[0] & m_pio_dir[0]);
84   m_dac1->write_unsigned8(data);
13485}
13586
136READ8_MEMBER(niyanpai_state::tmpz84c011_0_pb_r)
87WRITE8_MEMBER(niyanpai_state::cpu_portc_w)
13788{
138   return (tmpz84c011_pio_r(space,1) & ~m_pio_dir[1]) | (m_pio_latch[1] & m_pio_dir[1]);
89   m_dac2->write_unsigned8(data);
13990}
14091
141READ8_MEMBER(niyanpai_state::tmpz84c011_0_pc_r)
92WRITE8_MEMBER(niyanpai_state::cpu_porte_w)
14293{
143   return (tmpz84c011_pio_r(space,2) & ~m_pio_dir[2]) | (m_pio_latch[2] & m_pio_dir[2]);
94   if (!(data & 0x01)) niyanpai_soundclr_w(space, 0, 0);
14495}
14596
146READ8_MEMBER(niyanpai_state::tmpz84c011_0_pd_r)
147{
148   return (tmpz84c011_pio_r(space,3) & ~m_pio_dir[3]) | (m_pio_latch[3] & m_pio_dir[3]);
149}
15097
151READ8_MEMBER(niyanpai_state::tmpz84c011_0_pe_r)
152{
153   return (tmpz84c011_pio_r(space,4) & ~m_pio_dir[4]) | (m_pio_latch[4] & m_pio_dir[4]);
154}
155
156WRITE8_MEMBER(niyanpai_state::tmpz84c011_0_pa_w)
157{
158   m_pio_latch[0] = data;
159   tmpz84c011_pio_w(space, 0, data);
160}
161
162WRITE8_MEMBER(niyanpai_state::tmpz84c011_0_pb_w)
163{
164   m_pio_latch[1] = data;
165   tmpz84c011_pio_w(space, 1, data);
166}
167WRITE8_MEMBER(niyanpai_state::tmpz84c011_0_pc_w)
168{
169   m_pio_latch[2] = data;
170   tmpz84c011_pio_w(space, 2, data);
171}
172
173WRITE8_MEMBER(niyanpai_state::tmpz84c011_0_pd_w)
174{
175   m_pio_latch[3] = data;
176   tmpz84c011_pio_w(space, 3, data);
177}
178
179WRITE8_MEMBER(niyanpai_state::tmpz84c011_0_pe_w)
180{
181   m_pio_latch[4] = data;
182   tmpz84c011_pio_w(space, 4, data);
183}
184
185READ8_MEMBER(niyanpai_state::tmpz84c011_0_dir_pa_r)
186{
187   return m_pio_dir[0];
188}
189
190READ8_MEMBER(niyanpai_state::tmpz84c011_0_dir_pb_r)
191{
192   return m_pio_dir[1];
193}
194
195READ8_MEMBER(niyanpai_state::tmpz84c011_0_dir_pc_r)
196{
197   return m_pio_dir[2];
198}
199
200READ8_MEMBER(niyanpai_state::tmpz84c011_0_dir_pd_r)
201{
202   return m_pio_dir[3];
203}
204
205READ8_MEMBER(niyanpai_state::tmpz84c011_0_dir_pe_r)
206{
207   return m_pio_dir[4];
208}
209
210WRITE8_MEMBER(niyanpai_state::tmpz84c011_0_dir_pa_w)
211{
212   m_pio_dir[0] = data;
213}
214
215WRITE8_MEMBER(niyanpai_state::tmpz84c011_0_dir_pb_w)
216{
217   m_pio_dir[1] = data;
218}
219
220WRITE8_MEMBER(niyanpai_state::tmpz84c011_0_dir_pc_w)
221{
222   m_pio_dir[2] = data;
223}
224
225WRITE8_MEMBER(niyanpai_state::tmpz84c011_0_dir_pd_w)
226{
227   m_pio_dir[3] = data;
228}
229
230WRITE8_MEMBER(niyanpai_state::tmpz84c011_0_dir_pe_w)
231{
232   m_pio_dir[4] = data;
233}
234
235
23698void niyanpai_state::machine_reset()
23799{
238   address_space &space = m_maincpu->space(AS_PROGRAM);
239   int i;
240
241   // initialize TMPZ84C011 PIO
242   for (i = 0; i < 5; i++)
243   {
244      m_pio_dir[i] = m_pio_latch[i] = 0;
245      tmpz84c011_pio_w(space, i, 0);
246   }
247100}
248101
249102DRIVER_INIT_MEMBER(niyanpai_state,niyanpai)
r30728r30729
484337static ADDRESS_MAP_START( niyanpai_sound_io_map, AS_IO, 8, niyanpai_state )
485338   ADDRESS_MAP_GLOBAL_MASK(0xff)
486339   AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("ctc", z80ctc_device, read, write)
487   AM_RANGE(0x50, 0x50) AM_READWRITE(tmpz84c011_0_pa_r, tmpz84c011_0_pa_w)
488   AM_RANGE(0x51, 0x51) AM_READWRITE(tmpz84c011_0_pb_r, tmpz84c011_0_pb_w)
489   AM_RANGE(0x52, 0x52) AM_READWRITE(tmpz84c011_0_pc_r, tmpz84c011_0_pc_w)
490   AM_RANGE(0x30, 0x30) AM_READWRITE(tmpz84c011_0_pd_r, tmpz84c011_0_pd_w)
491   AM_RANGE(0x40, 0x40) AM_READWRITE(tmpz84c011_0_pe_r, tmpz84c011_0_pe_w)
492   AM_RANGE(0x54, 0x54) AM_READWRITE(tmpz84c011_0_dir_pa_r, tmpz84c011_0_dir_pa_w)
493   AM_RANGE(0x55, 0x55) AM_READWRITE(tmpz84c011_0_dir_pb_r, tmpz84c011_0_dir_pb_w)
494   AM_RANGE(0x56, 0x56) AM_READWRITE(tmpz84c011_0_dir_pc_r, tmpz84c011_0_dir_pc_w)
495   AM_RANGE(0x34, 0x34) AM_READWRITE(tmpz84c011_0_dir_pd_r, tmpz84c011_0_dir_pd_w)
496   AM_RANGE(0x44, 0x44) AM_READWRITE(tmpz84c011_0_dir_pe_r, tmpz84c011_0_dir_pe_w)
497340   AM_RANGE(0x80, 0x81) AM_DEVWRITE("ymsnd", ym3812_device, write)
498341ADDRESS_MAP_END
499342
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926769   { NULL }
927770};
928771
772
773
929774static MACHINE_CONFIG_START( niyanpai, niyanpai_state )
930775
931776   /* basic machine hardware */
r30728r30729
937782   MCFG_DEVICE_ADD("tmp68301", TMP68301, 0)
938783   MCFG_TMP68301_OUT_PARALLEL_CB(WRITE16(niyanpai_state, tmp68301_parallel_port_w))
939784
940   MCFG_CPU_ADD("audiocpu", Z80, 8000000)                  /* TMPZ84C011, 8.00 MHz */
785   MCFG_CPU_ADD("audiocpu", TMPZ84C011, 8000000)                  /* TMPZ84C011, 8.00 MHz */
941786   MCFG_CPU_CONFIG(daisy_chain_sound)
942787   MCFG_CPU_PROGRAM_MAP(niyanpai_sound_map)
943788   MCFG_CPU_IO_MAP(niyanpai_sound_io_map)
789   MCFG_TMPZ84C011_PORTD_READ_CALLBACK(READ8(niyanpai_state, cpu_portd_r))
790   MCFG_TMPZ84C011_PORTA_WRITE_CALLBACK(WRITE8(niyanpai_state, cpu_porta_w))
791   MCFG_TMPZ84C011_PORTB_WRITE_CALLBACK(WRITE8(niyanpai_state,cpu_portb_w))
792   MCFG_TMPZ84C011_PORTC_WRITE_CALLBACK(WRITE8(niyanpai_state,cpu_portc_w))
793   MCFG_TMPZ84C011_PORTE_WRITE_CALLBACK(WRITE8(niyanpai_state,cpu_porte_w))
944794
945795   MCFG_DEVICE_ADD("ctc", Z80CTC, 8000000 /* same as "audiocpu" */)
946796   MCFG_Z80CTC_INTR_CB(INPUTLINE("audiocpu", INPUT_LINE_IRQ0))
947797   MCFG_Z80CTC_ZC0_CB(DEVWRITELINE("ctc", z80ctc_device, trg3))
948798
949799   MCFG_NVRAM_ADD_0FILL("nvram")
950
800   
951801   /* video hardware */
952802   MCFG_SCREEN_ADD("screen", RASTER)
953803   MCFG_SCREEN_REFRESH_RATE(60)

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