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r29623 Monday 14th April, 2014 at 00:12:03 UTC by Robbbert
(MESS) amust : connected up devices
[src/mess/drivers]amust.c

trunk/src/mess/drivers/amust.c
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2020
2121The main rom is identical between the 2 halves, except that the initial
2222crtc parameters are slightly different. I've chosen to ignore the first
23half.
23half. (perhaps 50/60 Hz selectable by jumper?)
2424
25Preliminary I/O ports
26---------------------
2700-01 uart 1
2802-03 uart 2
2904-07 ppi 1
3008-0b ppi 2
310d-0f crtc
3210-11 fdc
3314-17 pit
34
35PIT.
36Having the PIT on ports 14-17 seems to make sense. It sets counters 1 and 2
37to mode 3, binary, initial count = 0x80. Counter 0 not used?
38
2539Floppy Parameters:
2640Double Density
2741Two Side
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4357- Everything
4458- Need software
4559- If booting straight to CP/M, the load message should be in the middle of the screen.
46- Beeper is a low pulse on bit 0 of port 0b - enable a pit event?
60- Beeper is a low pulse on bit 0 of port 0b
4761
4862****************************************************************************/
4963
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5266#include "video/mc6845.h"
5367#include "machine/upd765.h"
5468#include "machine/keyboard.h"
55//#include "machine/pit8253.h"
56//#include "machine/i8255.h"
57//#include "machine/i8251.h"
69#include "machine/pit8253.h"
70#include "machine/i8255.h"
71#include "machine/i8251.h"
5872
5973
6074class amust_state : public driver_device
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7286   DECLARE_DRIVER_INIT(amust);
7387   DECLARE_MACHINE_RESET(amust);
7488   DECLARE_READ8_MEMBER(port00_r);
89   DECLARE_READ8_MEMBER(port01_r);
90   DECLARE_READ8_MEMBER(port04_r);
91   DECLARE_WRITE8_MEMBER(port04_w);
92   DECLARE_READ8_MEMBER(port05_r);
93   DECLARE_READ8_MEMBER(port06_r);
94   DECLARE_WRITE8_MEMBER(port06_w);
95   DECLARE_READ8_MEMBER(port08_r);
7596   DECLARE_WRITE8_MEMBER(port08_w);
7697   DECLARE_READ8_MEMBER(port09_r);
7798   DECLARE_READ8_MEMBER(port0a_r);
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83104   const UINT8 *m_p_chargen;
84105   required_device<palette_device> m_palette;
85106private:
107   UINT8 m_port04;
108   UINT8 m_port06;
86109   UINT8 m_port08;
87110   UINT8 m_port0a;
88111   UINT8 m_term_data;
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112135static ADDRESS_MAP_START(amust_io, AS_IO, 8, amust_state)
113136   ADDRESS_MAP_UNMAP_HIGH
114137   ADDRESS_MAP_GLOBAL_MASK(0xff)
138   //AM_RANGE(0x00, 0x00) AM_DEVREADWRITE("uart1", i8251_device, data_r, data_w)
139   //AM_RANGE(0x01, 0x01) AM_DEVREADWRITE("uart1", i8251_device, status_r, control_w)
115140   AM_RANGE(0x00, 0x00) AM_READ(port00_r)
116   AM_RANGE(0x08, 0x08) AM_WRITE(port08_w)
117   AM_RANGE(0x09, 0x09) AM_READ(port09_r)
118   AM_RANGE(0x0a, 0x0a) AM_READWRITE(port0a_r,port0a_w)
119   AM_RANGE(0x0d, 0x0d) AM_WRITE(port0d_w)
141   AM_RANGE(0x01, 0x01) AM_READ(port01_r)
142   AM_RANGE(0x02, 0x02) AM_DEVREADWRITE("uart2", i8251_device, data_r, data_w)
143   AM_RANGE(0x03, 0x03) AM_DEVREADWRITE("uart2", i8251_device, status_r, control_w)
144   AM_RANGE(0x04, 0x07) AM_DEVREADWRITE("ppi1", i8255_device, read, write)
145   AM_RANGE(0x08, 0x0b) AM_DEVREADWRITE("ppi2", i8255_device, read, write)
146   AM_RANGE(0x0d, 0x0d) AM_READNOP AM_WRITE(port0d_w)
120147   AM_RANGE(0x0e, 0x0e) AM_DEVREADWRITE("crtc", mc6845_device, status_r, address_w)
121148   AM_RANGE(0x0f, 0x0f) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
122149   AM_RANGE(0x10, 0x11) AM_DEVICE("fdc", upd765a_device, map)
123   //AM_RANGE(0x00, 0x00) AM_DEVREADWRITE("uart1", i8251_device, data_r, data_w)
124   //AM_RANGE(0x01, 0x01) AM_DEVREADWRITE("uart1", i8251_device, status_r, control_w)
125   //AM_RANGE(0x02, 0x02) AM_DEVREADWRITE("uart2", i8251_device, data_r, data_w)
126   //AM_RANGE(0x03, 0x03) AM_DEVREADWRITE("uart2", i8251_device, status_r, control_w)
127   //AM_RANGE(0x04, 0x07) AM_DEVREADWRITE("ppi1", i8255_device, read, write)
128   //AM_RANGE(0x08, 0x0b) AM_DEVREADWRITE("ppi2", i8255_device, read, write)
129   //AM_RANGE(0x14, 0x17) AM_DEVREADWRITE("pit", pit8253_device, read, write)
150   AM_RANGE(0x14, 0x17) AM_DEVREADWRITE("pit", pit8253_device, read, write)
130151ADDRESS_MAP_END
131152
132153static SLOT_INTERFACE_START( amust_floppies )
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144165   return ret;
145166}
146167
168READ8_MEMBER( amust_state::port01_r )
169{
170   return 0xff;
171}
172
173// bodgy
174INTERRUPT_GEN_MEMBER( amust_state::irq_vs )
175{
176   m_maincpu->set_input_line_and_vector(INPUT_LINE_IRQ0, ASSERT_LINE, 0xcf);
177}
178
179READ8_MEMBER( amust_state::port04_r )
180{
181   return m_port04;
182}
183
184WRITE8_MEMBER( amust_state::port04_w )
185{
186   m_port04 = data;
187}
188
189READ8_MEMBER( amust_state::port05_r )
190{
191   return 0;
192}
193
194READ8_MEMBER( amust_state::port06_r )
195{
196   return m_port06;
197}
198
199WRITE8_MEMBER( amust_state::port06_w )
200{
201   m_port06 = data;
202}
203
204static I8255_INTERFACE( ppi1_intf )
205{
206   DEVCB_DRIVER_MEMBER(amust_state, port04_r),   // Port A read
207   DEVCB_DRIVER_MEMBER(amust_state, port04_w),   // Port A write
208   DEVCB_DRIVER_MEMBER(amust_state, port05_r),   // Port B read
209   DEVCB_NULL,                                   // Port B write
210   DEVCB_DRIVER_MEMBER(amust_state, port06_r),   // Port C read
211   DEVCB_DRIVER_MEMBER(amust_state, port06_w),   // Port C write
212};
213
214READ8_MEMBER( amust_state::port08_r )
215{
216   return m_port08;
217}
218
147219WRITE8_MEMBER( amust_state::port08_w )
148220{
149221   m_port08 = data;
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165237   m_port0a = data;
166238}
167239
240static I8255_INTERFACE( ppi2_intf )
241{
242   DEVCB_DRIVER_MEMBER(amust_state, port08_r),   // Port A read
243   DEVCB_DRIVER_MEMBER(amust_state, port08_w),   // Port A write
244   DEVCB_DRIVER_MEMBER(amust_state, port09_r),   // Port B read
245   DEVCB_NULL,                                   // Port B write
246   DEVCB_DRIVER_MEMBER(amust_state, port0a_r),   // Port C read
247   DEVCB_DRIVER_MEMBER(amust_state, port0a_w),   // Port C write
248};
249
168250WRITE8_MEMBER( amust_state::port0d_w )
169251{
170252   UINT16 video_address = m_port08 | ((m_port0a & 7) << 8);
171253   m_p_videoram[video_address] = data;
172254}
173255
174// bodgy
175INTERRUPT_GEN_MEMBER( amust_state::irq_vs )
176{
177   m_maincpu->set_input_line_and_vector(INPUT_LINE_IRQ0, ASSERT_LINE, 0xcf);
178}
179
180//static I8255_INTERFACE( ppi1_intf )
181//{
182//  DEVCB_DRIVER_MEMBER(amust_state, ppi1_pa_r),   // Port A read
183//  DEVCB_DRIVER_MEMBER(amust_state, ppi1_pa_w),   // Port A write
184//  DEVCB_DRIVER_MEMBER(amust_state, ppi1_pb_r),   // Port B read
185//  DEVCB_DRIVER_MEMBER(amust_state, ppi1_pb_w),   // Port B write
186//  DEVCB_DRIVER_MEMBER(amust_state, ppi1_pc_r),   // Port C read
187//  DEVCB_DRIVER_MEMBER(amust_state, ppi1_pc_w),   // Port C write
188//};
189
190//static I8255_INTERFACE( ppi2_intf )
191//{
192//  DEVCB_DRIVER_MEMBER(amust_state, ppi2_pa_r),   // Port A read
193//  DEVCB_DRIVER_MEMBER(amust_state, ppi2_pa_w),   // Port A write
194//  DEVCB_DRIVER_MEMBER(amust_state, ppi2_pb_r),   // Port B read
195//  DEVCB_DRIVER_MEMBER(amust_state, ppi2_pb_w),   // Port B write
196//  DEVCB_DRIVER_MEMBER(amust_state, ppi2_pc_r),   // Port C read
197//  DEVCB_DRIVER_MEMBER(amust_state, ppi2_pc_w),   // Port C write
198//};
199
200256WRITE8_MEMBER( amust_state::kbd_put )
201257{
202258   m_term_data = data;
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273329   membank("bankw0")->set_entry(0); // always write to ram
274330   address_space &space = m_maincpu->space(AS_PROGRAM);
275331   space.write_byte(8, 0xc9);
332   m_port04 = 0;
333   m_port06 = 0;
334   m_port08 = 0;
335   m_port0a = 0;
276336   m_maincpu->set_state_int(Z80_PC, 0xf800);
277337}
278338
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316376   //MCFG_I8251_DTR_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_dtr))
317377   //MCFG_I8251_RTS_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_rts))
318378
319   //MCFG_DEVICE_ADD("uart2", I8251, 0)
379   MCFG_DEVICE_ADD("uart2", I8251, 0)
320380   //MCFG_I8251_TXD_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_txd))
321381   //MCFG_I8251_DTR_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_dtr))
322382   //MCFG_I8251_RTS_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_rts))
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326386   //MCFG_RS232_CTS_HANDLER(DEVWRITELINE("uart8251", i8251_device, write_cts))
327387   //MCFG_RS232_DSR_HANDLER(DEVWRITELINE("uart8251", i8251_device, write_dsr))
328388
329   //MCFG_DEVICE_ADD("pit", PIT8253, 0)
330
331   //MCFG_I8255A_ADD("ppi1", ppi1_intf)
332   //MCFG_I8255A_ADD("ppi2", ppi2_intf)
389   MCFG_DEVICE_ADD("pit", PIT8253, 0)
390   MCFG_I8255A_ADD("ppi1", ppi1_intf)
391   MCFG_I8255A_ADD("ppi2", ppi2_intf)
333392MACHINE_CONFIG_END
334393
335394/* ROM definition */
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349408/* Driver */
350409
351410/*    YEAR  NAME    PARENT  COMPAT   MACHINE    INPUT    CLASS          INIT     COMPANY       FULLNAME       FLAGS */
352COMP( 1983, amust,  0,      0,       amust,     amust,   amust_state,   amust,  "Amust",       "Compak", GAME_IS_SKELETON)
411COMP( 1983, amust,  0,      0,       amust,     amust,   amust_state,   amust,  "Amust", "Amust Executive 816", GAME_IS_SKELETON)

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